Efficient Radio Frequency Inductive Discharges in Near Atmospheric Pressure Using Immittance Conversion Topology

NASA Astrophysics Data System (ADS)

Razzak, M. Abdur; Takamura, Shuichi; Uesugi, Yoshihiko; Ohno, Noriyasu

A radio frequency (rf) inductive discharge in atmospheric pressure range requires high voltage in the initial startup phase and high power during the steady state sustainment phase. It is, therefore, necessary to inject high rf power into the plasma ensuring the maximum use of the power source, especially where the rf power is limited. In order to inject the maximum possible rf power into the plasma with a moderate rf power source of few kilowatts range, we employ the immittance conversion topology by converting a constant voltage source into a constant current source to generate efficient rf discharge by inductively coupled plasma (ICP) technique at a gas pressure with up to one atmosphere in argon. A novel T-LCL immittance circuit is designed for constant-current high-power operation, which is practically very important in the high-frequency range, to provide high effective rf power to the plasma. The immittance conversion system combines the static induction transistor (SIT)-based radio frequency (rf) high-power inverter circuit and the immittance conversion elements including the rf induction coil. The basic properties of the immittance circuit are studied by numerical analysis and verified the results by experimental measurements with the inductive plasma as a load at a relatively high rf power of about 4 kW. The performances of the immittance circuit are also evaluated and compared with that of the conventional series resonance circuit in high-pressure induction plasma generation. The experimental results reveal that the immittance conversion circuit confirms injecting higher effective rf power into the plasma as much as three times than that of the series resonance circuit under the same operating conditions and same dc supply voltage to the inverter, thereby enhancing the plasma heating efficiency to generate efficient rf inductive discharges.

Sensitivity Enhancement of an Inductively Coupled Local Detector Using a HEMT-based Current Amplifier

PubMed Central

Qian, Chunqi; Duan, Qi; Dodd, Steve; Koretsky, Alan; Murphy-Boesch, Joe

2015-01-01

Purpose To improve the signal transmission efficiency and sensitivity of a local detection coil that is weakly inductively coupled to a larger receive coil. Methods The resonant detection coil is connected in parallel with the gate of a HEMT transistor without impedance matching. When the drain of the transistor is capacitively shunted to ground, current amplification occurs in the resonator by feedback that transforms a capacitive impedance on the transistor’s source to a negative resistance on its gate. Results High resolution images were obtained from a mouse brain using a small, 11 mm diameter surface coil that was inductively coupled to a commercial, phased array chest coil. Although the power consumption of the amplifier was only 88 µW, 14 dB gain was obtained with excellent noise performance. Conclusion An integrated current amplifier based on a High Electron Mobility Transistor (HEMT) can enhance the sensitivity of inductively coupled local detectors when weakly coupled. This amplifier enables efficient signal transmission between customized user coils and commercial clinical coils, without the need for a specialized signal interface. PMID:26192998

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

NASA Technical Reports Server (NTRS)

Niedra, Janis M.; Schwarze, Gene E.

2005-01-01

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Improved circuit for measuring capacitive and inductive reactances

NASA Technical Reports Server (NTRS)

Dalins, I.; Mc Carty, V.

1967-01-01

Amplifier circuit measures very small changes of capacitive or inductive reactance, such as produced by a variable capacitance or a variable inductance displacement transducer. The circuit employs reactance-sensing oscillators in which field effect transistors serve as the active elements.

High-performance vertical organic transistors.

PubMed

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

DC switching regulated power supply for driving an inductive load

DOEpatents

Dyer, G.R.

1983-11-29

A dc switching regulated power supply for driving an inductive load is provided. The regulator basic circuit is a bridge arrangement of diodes and transistors. First and second opposite legs of the bridge are formed by first and second parallel-connected transistor arrays, respectively, while the third and fourth legs of the bridge are formed by appropriately connected first and second parallel connected diode arrays, respectively. A dc power supply is connected to the input of the bridge and the output is connected to the load. A servo controller is provided to control the switching rate of the transistors to maintain a desired current to the load. The regulator may be operated in three stages or modes: (1) for current runup in the load, both first and second transistor switch arrays are turned on and current is supplied to the load through both transistor arrays. (2) When load current reaches the desired level, the first switch is turned off, and load current flywheels through the second switch array and the fourth leg diode array connecting the second switch array in series with the load. Current is maintained by alternating between modes 1 and 2 at a suitable duty cycle and switching rate set by the controller. (3) Rapid current rundown is accomplished by turning both switch arrays off, allowing load current to be dumped back into the source through the third and fourth diode arrays connecting the source in series opposition with the load to recover energy from the inductive load.

Nanocrystal-mediated charge screening effects in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, C. J.; Yeom, D. H.; Jeong, D. Y.; Lee, M. G.; Moon, B. M.; Kim, S. S.; Choi, C. Y.; Koo, S. M.

2009-03-01

ZnO nanowire field-effect transistors having an omega-shaped floating gate (OSFG) have been successfully fabricated by directly coating CdTe nanocrystals (˜6±2.5 nm) at room temperature, and compared to simultaneously prepared control devices without nanocrystals. Herein, we demonstrate that channel punchthrough may occur when the depletion from the OSFG takes place due to the trapped charges in the nanocrystals. Electrical measurements on the OSFG nanowire devices showed static-induction transistorlike behavior in the drain output IDS-VDS characteristics and a hysteresis window as large as ˜3.1 V in the gate transfer IDS-VGS characteristics. This behavior is ascribed to the presence of the CdTe nanocrystals, and is indicative of the trapping and emission of electrons in the nanocrystals. The numerical simulations clearly show qualitatively the same characteristics as the experimental data and confirm the effect, showing that the change in the potential distribution across the channel, induced by both the wrapping-around gate and the drain, affects the transport characteristics of the device. The cross-sectional energy band and potential profile of the OSFG channel corresponding to the "programed (noncharged)" and "erased (charged)" operations for the device are also discussed on the basis of the numerical capacitance-voltage simulations.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

An Ultra-Sensitive Electrometer based on the Cavity-Embedded Cooper-Pair Transistor

NASA Astrophysics Data System (ADS)

Li, Juliang; Miller, Marco; Rimberg, Alex

2015-03-01

We discuss use of a cavity-embedded Cooper-pair transistor (cCPT) as a potentially quantum-limited electrometer. The cCPT consists of a Cooper pair transistor placed at the voltage antinode of a 5.7 GHz shorted quarter-wave resonator so that the CPT provides a galvanic connection between the cavity's central conductor and ground plane. The quantum inductance of the CPT, which appears in parallel with the effective inductance of the cavity resonance, can be modulated by application of either a gate voltage to the CPT island or a flux bias to the CPT/cavity loop. Changes in the CPT inductance shift the cavity resonant frequency, and therefore the phase of a microwave signal reflected from the cavity. The reflected wave is amplified by both SLUG and HEMT amplifiers before its phase is measured. Results of recent measurements on the cCPT electrometer will be compared with theoretical predictions. This work was supported by the NSF under Grant No. DMR-1104821, by the ARO under Contract No, W911NF-13-1-0377 and by AFOSR/DARPA under Agreement No. FA8750-12-2-0339.

Space station power semiconductor package

NASA Technical Reports Server (NTRS)

Balodis, Vilnis; Berman, Albert; Devance, Darrell; Ludlow, Gerry; Wagner, Lee

1987-01-01

A package of high-power switching semiconductors for the space station have been designed and fabricated. The package includes a high-voltage (600 volts) high current (50 amps) NPN Fast Switching Power Transistor and a high-voltage (1200 volts), high-current (50 amps) Fast Recovery Diode. The package features an isolated collector for the transistors and an isolated anode for the diode. Beryllia is used as the isolation material resulting in a thermal resistance for both devices of .2 degrees per watt. Additional features include a hermetical seal for long life -- greater than 10 years in a space environment. Also, the package design resulted in a low electrical energy loss with the reduction of eddy currents, stray inductances, circuit inductance, and capacitance. The required package design and device parameters have been achieved. Test results for the transistor and diode utilizing the space station package is given.

Transistor screening evaluation SJ6708H

NASA Technical Reports Server (NTRS)

Barton, J. L.

1978-01-01

A manufacturer was contracted to screen 125 transistors capable of withstanding the high level inductive voltages obtained when switching inductive loads. Planned differences included a change in die bonding to comply with NASA's desire for hard solder die attachment which further necessitated a change in package to conform to the required die mounting system. Evaluation of the electrical performance and recommended changes were made during the preliminary build phase of the program. The following sections are outlined: (1) narrative outline; (2) customer data summary and X-ray reports; (3) device specification; (4) failure analysis reports; (5) test facilities list; and (6) test measurement data.

Studies Of Single-Event-Upset Models

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.

1988-01-01

Report presents latest in series of investigations of "soft" bit errors known as single-event upsets (SEU). In this investigation, SEU response of low-power, Schottky-diode-clamped, transistor/transistor-logic (TTL) static random-access memory (RAM) observed during irradiation by Br and O ions in ranges of 100 to 240 and 20 to 100 MeV, respectively. Experimental data complete verification of computer model used to simulate SEU in this circuit.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

Multiplexing of Radio-Frequency Single Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, Thomas R.; Pellerano, F. A.; Stahle, C. M.; Aidala, K.; Schoelkopf, R. J.; Krebs, Carolyn (Technical Monitor)

2001-01-01

We present results on wavelength division multiplexing of radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. A two-channel demonstration of this concept using discrete components successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.

Nonlinear Contact Effects in Staggered Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fischer, Axel; Zündorf, Hilke; Kaschura, Felix; Widmer, Johannes; Leo, Karl; Kraft, Ulrike; Klauk, Hagen

2017-11-01

The static and dynamic electrical characteristics of thin-film transistors (TFTs) are often limited by the parasitic contact resistances, especially for TFTs with a small channel length. For the smallest possible contact resistance, the staggered device architecture has a general advantage over the coplanar architecture of a larger injection area. Since the charge transport occurs over an extended area, it is inherently more difficult to develop an accurate analytical device model for staggered TFTs. Most analytical models for staggered TFTs, therefore, assume that the contact resistance is linear, even though this is commonly accepted not to be the case. Here, we introduce a semiphenomenological approach to accurately fit experimental data based on a highly discretized equivalent network circuit explicitly taking into account the inherent nonlinearity of the contact resistance. The model allows us to investigate the influence of nonlinear contact resistances on the static and dynamic performance of staggered TFTs for different contact layouts with a relatively short computation time. The precise extraction of device parameters enables us to calculate the transistor behavior as well as the potential for optimization in real circuits.

I-V Characteristics of a Static Random Access Memory Cell Utilizing Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Cody; Hunt, Mitchell; Ho, Fat D.; MacLeod, Todd C.

2012-01-01

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

Rectifier cabinet static breaker

DOEpatents

Costantino, Jr, Roger A.; Gliebe, Ronald J.

1992-09-01

A rectifier cabinet static breaker replaces a blocking diode pair with an SCR and the installation of a power transistor in parallel with the latch contactor to commutate the SCR to the off state. The SCR serves as a static breaker with fast turnoff capability providing an alternative way of achieving reactor scram in addition to performing the function of the replaced blocking diodes. The control circuitry for the rectifier cabinet static breaker includes on-line test capability and an LED indicator light to denote successful test completion. Current limit circuitry provides high-speed protection in the event of overload.

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

DC switching regulated power supply for driving an inductive load

DOEpatents

Dyer, George R.

1986-01-01

A power supply for driving an inductive load current from a dc power supply hrough a regulator circuit including a bridge arrangement of diodes and switching transistors controlled by a servo controller which regulates switching in response to the load current to maintain a selected load current. First and second opposite legs of the bridge are formed by first and second parallel-connected transistor arrays, respectively, while the third and fourth legs of the bridge are formed by appropriately connected first and second parallel connected diode arrays, respectively. The regulator may be operated in three "stages" or modes: (1) For current runup in the load, both first and second transistor switch arrays are turned "on" and current is supplied to the load through both transistor arrays. (2) When load current reaches the desired level, the first switch is turned "off", and load current "flywheels" through the second switch array and the fourth leg diode array connecting the second switch array in series with the load. Current is maintained by alternating between modes 1 and 2 at a suitable duty cycle and switching rate set by the controller. (3) Rapid current rundown is accomplished by turning both switch arrays "off", allowing load current to be dumped back into the source through the third and fourth diode arrays connecting the source in series opposition with the load to recover energy from the inductive load. The three operating states are controlled automatically by the controller.

Wavelength Division Multiplexing Scheme for Radio-Frequency Single Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, Thomas R.; Pellerano, F. A.; Stahle, C. M.; Aidala, K.; Schoelkopf, R. J.; Krebs, Carolyn (Technical Monitor)

2001-01-01

We describe work on a wavelength division multiplexing scheme for radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. Using discrete components, we made a two-channel demonstration of this concept and successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Johnson, R. Wayne; Askew, Ray; Bromstead, James; Weir, Bennett

1991-01-01

The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

High-gain subnanowatt power consumption hybrid complementary logic inverter with WSe2 nanosheet and ZnO nanowire transistors on glass.

PubMed

Shokouh, Seyed Hossein Hosseini; Pezeshki, Atiye; Ali Raza, Syed Raza; Lee, Hee Sung; Min, Sung-Wook; Jeon, Pyo Jin; Shin, Jae Min; Im, Seongil

2015-01-07

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Energetic distributions of interface states Dit(phi sub s) of MOS transistors in extension of Kuhn's quasistatic C(V)-method

NASA Astrophysics Data System (ADS)

Krautschneider, W.; Wagemann, H. G.

1983-10-01

Kuhn's quasi-static C(V)-method has been extended to MOS transistors by considering the capacitances of the source and drain p-n junctions additionally to the MOS varactor circuit model. The width of the space charge layers w(phi sub s) is calculated as a function of the surface potential phi sub s and applied to the MOS capacitance as a function of the gate voltage. Capacitance behavior for different channel length is presented as a model and compared to measurement results and evaluations of energetic distributions of interface states Dit(phi sub s) for MOS transistor and MOS varactor on the same chip.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

NASA Astrophysics Data System (ADS)

Ogasawara, Ryosuke; Endoh, Tetsuo

2018-04-01

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient

NASA Astrophysics Data System (ADS)

Xue, Peng; Fu, Guicui

2017-03-01

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT's dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600 V/150 A CSTBT and a Infineon 600 V/200 A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT's clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT's dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT's experimental results implies that the CSTBT's abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT's abnormal dynamic avalanche mechanism. Moreover, the CSTBT's negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT's dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

Use of vacuum tubes in test instrumentation for measuring characteristics of fast high-voltage semiconductor devices

NASA Technical Reports Server (NTRS)

Berning, D.

1981-01-01

Circuits are described that permit measurement of fast events occurring in power semiconductors. These circuits were developed for the dynamic characterization of transistors used in inductive-load switching applications. Fast voltage clamping using vacuum diodes is discussed, and reference is made to a unique circuit that was built for performing nondestructive, reverse-bias, second-breakdown tests on transistors.

Ultrasensitive Electrometry with a Cavity-Embedded Cooper Pair Transistor

NASA Astrophysics Data System (ADS)

Rimberg, A. J.; Li, Juliang

In this experiment a cavity-embedded Cooper-pair transistor (cCPT) is used as a potentially quantum-limited electrometer. The cCPT consists of a Cooper pair transistor placed at the voltage antinode of a 5.7 GHz shorted quarter-wave resonator so that the CPT provides a galvanic connection between the cavity's central conductor and ground plane. The quantum inductance of the CPT, which appears in parallel with the effective inductance of the cavity resonance, can be modulated by application of either a gate voltage to the CPT island or a flux bias to the CPT/cavity loop. Changes in the CPT inductance shift the cavity resonant frequency, and therefore the phase of a microwave signal reflected from the cavity. The reflected wave is amplified by both SLUG and HEMT amplifiers before its phase is measured. The cCPT can also be operated as a Josephson parametric amplifier (JPA). A pump tone at 11.4 GHz sent into the flux bias line has been shown to provide about 10dB gain. The possibility of parametrically amplifying the side bands produced by a charge detection measurement, thereby increasing the overall sensitivity of the cCPT, will also be investigated. Supported by Grants ARO W911NF-13-10377 and NSF DMR 1507400.

A static induction device manufactured by silicon direct bonding

NASA Astrophysics Data System (ADS)

Chen, Xin'an; Liu, Su; Huang, Qing'an

2004-07-01

It is always a key problem how to improve the gate-source breakdown voltage (VGK) of static induction devices during manufacturing. By using a silicon direct bonding process to replace the high resistivity epitaxy process, a bonding buried gate structure is formed, which is different from an epitaxy buried gate structure. The new structure can improve the gate-source breakdown voltage from the process and the structure. It is shown that the bonding buried gate structure is a promising structure, that can improve the VGK and other performances of devices, by manufacture of a static induction thyristor.

Static and Dynamic Water Motion-Induced Instability in Oxide Thin-Film Transistors and Its Suppression by Using Low-k Fluoropolymer Passivation.

PubMed

Choi, Seungbeom; Jo, Jeong-Wan; Kim, Jaeyoung; Song, Seungho; Kim, Jaekyun; Park, Sung Kyu; Kim, Yong-Hoon

2017-08-09

Here, we report static and dynamic water motion-induced instability in indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) and its effective suppression with the use of a simple, solution-processed low-k (ε ∼ 1.9) fluoroplastic resin (FPR) passivation layer. The liquid-contact electrification effect, in which an undesirable drain current modulation is induced by a dynamic motion of a charged liquid such as water, can cause a significant instability in IGZO TFTs. It was found that by adopting a thin (∼44 nm) FPR passivation layer for IGZO TFTs, the current modulation induced by the water-contact electrification was greatly reduced in both off- and on-states of the device. In addition, the FPR-passivated IGZO TFTs exhibited an excellent stability to static water exposure (a threshold voltage shift of +0.8 V upon 3600 s of water soaking), which is attributed to the hydrophobicity of the FPR passivation layer. Here, we discuss the origin of the current instability caused by the liquid-contact electrification as well as various static and dynamic stability tests for IGZO TFTs. On the basis of our findings, we believe that the use of a thin, solution-processed FPR passivation layer is effective in suppressing the static and dynamic water motion-induced instabilities, which may enable the realization of high-performance and environment-stable oxide TFTs for emerging wearable and skin-like electronics.

Coupling Inductor Based Hybrid Millimeter-Wave Switch

NASA Technical Reports Server (NTRS)

Gu, Qun (Inventor); Drouin, Brian J. (Inventor); Tang, Adrian J. (Inventor); Shu, Ran (Inventor)

2017-01-01

A switch comprising a plurality of inductors and a plurality of shunt transistors is described. Each inductor can be electrically coupled between adjacent shunt transistors to form a distributed switch structure. At least two inductors in the plurality of inductors can be inductively coupled with each other. The plurality of inductors can correspond to portions of a coupling inductor, wherein the coupling inductor can have an irregular octagonal shape.

Low noise tuned amplifier

NASA Technical Reports Server (NTRS)

Kleinberg, L. L. (Inventor)

1984-01-01

A bandpass amplifier employing a field effect transistor amplifier first stage is described with a resistive load either a.c. or directly coupled to the non-inverting input of an operational amplifier second stage which is loaded in a Wien Bridge configuration. The bandpass amplifier may be operated with a signal injected into the gate terminal of the field effect transistor and the signal output taken from the output terminal of the operational amplifier. The operational amplifier stage appears as an inductive reactance, capacitive reactance and negative resistance at the non-inverting input of the operational amplifier, all of which appear in parallel with the resistive load of the field effect transistor.

Radio-frequency Bloch-transistor electrometer.

PubMed

Zorin, A B

2001-04-09

A quantum electrometer is proposed which is based on charge modulation of the Josephson supercurrent in the Bloch transistor inserted in a superconducting ring. As this ring is inductively coupled to a high- Q resonance tank circuit, the variations of the charge on the transistor island are converted into variations of amplitude and phase of oscillations in the tank. These variations are amplified and then detected. At sufficiently low temperature of the tank the device sensitivity is determined by the energy resolution of the amplifier, that can be reduced down to the standard quantum limit of 1 / 2Planck's over 2pi. A "back-action-evading" scheme of subquantum limit measurements is proposed.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-12-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

PubMed Central

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-01-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption. PMID:26656113

75 FR 29723 - Foreign-Trade Zone 29-Louisville, KY; Application for Expansion and Expansion of Manufacturing...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-05-27

..., plates, filters, bearings, air pumps/compressors, valves, switches, electric motors, tubes/pipes/profiles... electric motors, pinions, magnets, ignition parts, diodes, transistors, resistors, semiconductors, liquid..., starter motors, motor/generator units, alternators, distributors, other static converters, inverter...

76 FR 9000 - Foreign-Trade Zone 29-Louisville, KY, Application for Expansion of Manufacturing Authority...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-02-16

..., springs, brackets, plates, filters, bearings, air pumps/compressors, valves, switches, electric motors..., clutches, parts of electric motors, pinions, magnets, ignition parts, diodes, transistors, resistors... and chambers, starter motors, motor/generator units, alternators, distributors, other static...

Regulated dc-to-dc converter for voltage step-up or step-down with input-output isolation

NASA Technical Reports Server (NTRS)

Feng, S. Y.; Wilson, T. G. (Inventor)

1973-01-01

A closed loop regulated dc-to-dc converter employing an unregulated two winding inductive energy storage converter is provided by using a magnetically coupled multivibrator acting as duty cycle generator to drive the converter. The multivibrator is comprised of two transistor switches and a saturable transformer. The output of the converter is compared with a reference in a comparator which transmits a binary zero until the output exceeds the reference. When the output exceeds the reference, the binary output of the comparator drives transistor switches to turn the multivibrator off. The multivibrator is unbalanced so that a predetermined transistor will always turn on first when the binary feedback signal becomes zero.

Ultralow-power complementary metal-oxide-semiconductor inverters constructed on Schottky barrier modified nanowire metal-oxide-semiconductor field-effect-transistors.

PubMed

Ma, R M; Peng, R M; Wen, X N; Dai, L; Liu, C; Sun, T; Xu, W J; Qin, G G

2010-10-01

We show that the threshold voltages of both n- and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) can be lowered to close to zero by adding extra Schottky contacts on top of nanowires (NWs). Novel complementary metal-oxide-semiconductor (CMOS) inverters are constructed on these Schottky barrier modified n- and p-channel NW MOSFETs. Based on the high performances of the modified n- and p-channel MOSFETs, especially the low threshold voltages, the as-fabricated CMOS inverters have low operating voltage, high voltage gain, and ultra-low static power dissipation.

Quantum Device Applications of Mesoscopic Superconductivity

NASA Astrophysics Data System (ADS)

Hakonen, P. J.

2006-08-01

A brief account is given on the possibilities of mesoscopic superconductivity in low-noise amplifier and detector applications. In particular, three devices will be described: 1) Bloch oscillating transistor (BOT), 2) Inductively-read superconducting Cooper pair transistor (L-SET), and 3) Quantum capacitive phase detector (C-SET). The BOT is a low-noise current amplifier while the L-SET and C-SET act as ultra-sensitive charge and phase detectors, respectively. The basic operating principles and the main characteristics of these devices will be reviewed and discussed.

Static air-gap eccentricity fault diagnosis using rotor slot harmonics in line neutral voltage of three-phase squirrel cage induction motor

NASA Astrophysics Data System (ADS)

Oumaamar, Mohamed El Kamel; Maouche, Yassine; Boucherma, Mohamed; Khezzar, Abdelmalek

2017-02-01

The mixed eccentricity fault detection in a squirrel cage induction motor has been thoroughly investigated. However, a few papers have been related to pure static eccentricity fault and the authors focused on the RSH harmonics presented in stator current. The main objective of this paper is to present an alternative method based on the analysis of line neutral voltage taking place between the supply and the stator neutrals in order to detect air-gap static eccentricity, and to highlight the classification of all RSH harmonics in line neutral voltage. The model of squirrel cage induction machine relies on the rotor geometry and winding layout. Such developed model is used to analyze the impact of the pure static air-gap eccentricity by predicting the related frequencies in the line neutral voltage spectrum. The results show that the line neutral voltage spectrum are more sensitive to the air-gap static eccentricity fault compared to stator current one. The theoretical analysis and simulated results are confirmed by experiments.

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

PubMed

Singh, Kunwar; Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC(2)MOSff1. Postlayout simulations indicate that mC(2)MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

PubMed Central

Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. PMID:24723808

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

NASA Astrophysics Data System (ADS)

Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

Unusual Thermoelectric Behavior Indicating a Hopping to Bandlike Transport Transition in Pentacene

NASA Astrophysics Data System (ADS)

Germs, W. Chr.; Guo, K.; Janssen, R. A. J.; Kemerink, M.

2012-07-01

An unusual increase in the Seebeck coefficient with increasing charge carrier density is observed in pentacene thin film transistors. This behavior is interpreted as being due to a transition from hopping transport in static localized states to bandlike transport, occurring at temperatures below ˜250K. Such a transition can be expected for organic materials in which both static energetic disorder and dynamic positional disorder are important. While clearly visible in the temperature and density dependent Seebeck coefficient, the transition hardly shows up in the charge carrier mobility.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays.

PubMed

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon; Hussain, Muhammad Mustafa

2018-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

NASA Astrophysics Data System (ADS)

Tavel, B.; Duriez, B.; Gwoziecki, R.; Basso, M. T.; Julien, C.; Ortolland, C.; Laplanche, Y.; Fox, R.; Sabouret, E.; Detcheverry, C.; Boeuf, F.; Morin, P.; Barge, D.; Bidaud, M.; Biénacel, J.; Garnier, P.; Cooper, K.; Chapon, J. D.; Trouiller, Y.; Belledent, J.; Broekaart, M.; Gouraud, P.; Denais, M.; Huard, V.; Rochereau, K.; Difrenza, R.; Planes, N.; Marin, M.; Boret, S.; Gloria, D.; Vanbergue, S.; Abramowitz, P.; Vishnubhotla, L.; Reber, D.; Stolk, P.; Woo, M.; Arnaud, F.

2006-04-01

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with FT = 160 GHz for LP and 280 GHz for GP nMOS transistors.

Analysis and modeling of a family of two-transistor parallel inverters

NASA Technical Reports Server (NTRS)

Lee, F. C. Y.; Wilson, T. G.

1973-01-01

A family of five static dc-to-square-wave inverters, each employing a square-loop magnetic core in conjunction with two switching transistors, is analyzed using piecewise-linear models for the nonlinear characteristics of the transistors, diodes, and saturable-core devices. Four of the inverters are analyzed in detail for the first time. These analyses show that, by proper choice of a frame of reference, each of the five quite differently appearing inverter circuits can be described by a common equivalent circuit. This equivalent circuit consists of a five-segment nonlinear resistor, a nonlinear saturable reactor, and a linear capacitor. Thus, by proper interpretation and identification of the parameters in the different circuits, the results of a detailed solution for one of the inverter circuits provide similar information and insight into the local and global behavior of each inverter in the family.

Break-before-make CMOS inverter for power-efficient delay implementation.

PubMed

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

PubMed Central

Raič, Dušan

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

Progress on advanced dc and ac induction drives for electric vehicles

NASA Technical Reports Server (NTRS)

Schwartz, H. J.

1982-01-01

Progress is reported in the development of complete electric vehicle propulsion systems, and the results of tests on the Road Load Simulator of two such systems representative of advanced dc and ac drive technology are presented. One is the system used in the DOE's ETV-1 integrated test vehicle which consists of a shunt wound dc traction motor under microprocessor control using a transistorized controller. The motor drives the vehicle through a fixed ratio transmission. The second system uses an ac induction motor controlled by transistorized pulse width modulated inverter which drives through a two speed automatically shifted transmission. The inverter and transmission both operate under the control of a microprocessor. The characteristics of these systems are also compared with the propulsion system technology available in vehicles being manufactured at the inception of the DOE program and with an advanced, highly integrated propulsion system upon which technology development was recently initiated.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Switching Characteristics of a 4H-SiC Based Bipolar Junction Transistor to 200 C

NASA Technical Reports Server (NTRS)

Niedra, Janis M.

2006-01-01

Static curves and resistive load switching characteristics of a 600 V, 4 A rated, SiC-based NPN bipolar power transistor (BJT) were observed at selected temperatures from room to 200 C. All testing was done in a pulse mode at low duty cycle (approx.0.1 percent). Turn-on was driven by an adjustable base current pulse and turn-off was accelerated by a negative base voltage pulse of 7 V. These base drive signals were implemented by 850 V, gated power pulsers, having rise-times of roughly 10 ns, or less. Base charge sweep-out with a 7 V negative pulse did not produce the large reverse base current pulse seen in a comparably rated Si-based BJT. This may be due to a very low charge storage time. The decay of the collector current was more linear than its exponential-like rise. Switching observations were done at base drive currents (I(sub B)) up to 400 mA and collector currents (I(sub C)) up to 4 A, using a 100 Omega non-inductive load. At I(sub B) = 400 mA and I(sub C) = 4 A, turn-on times typically varied from 80 to 94 ns, over temperatures from 23 to 200 C. As expected, lowering the base drive greatly extended the turn-on time. Similarly, decreasing the load current to I(sub C) = 1 A with I(sub B) = 400 mA produced turn-on times as short as 34 ns. Over the 23 to 200 C range, with I(sub B) = 400 mA and I(sub C) = 4 A, turn-off times were in the range of 72 to 84 ns with the 7 V sweep-out.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

MCT/MOSFET Switch

NASA Technical Reports Server (NTRS)

Rippel, Wally E.

1990-01-01

Metal-oxide/semiconductor-controlled thyristor (MCT) and metal-oxide/semiconductor field-effect transistor (MOSFET) connected in switching circuit to obtain better performance. Offers high utilization of silicon, low forward voltage drop during "on" period of operating cycle, fast turnon and turnoff, and large turnoff safe operating area. Includes ability to operate at high temperatures, high static blocking voltage, and ease of drive.

Modelling switching-time effects in high-frequency power conditioning networks

NASA Technical Reports Server (NTRS)

Owen, H. A.; Sloane, T. H.; Rimer, B. H.; Wilson, T. G.

1979-01-01

Power transistor networks which switch large currents in highly inductive environments are beginning to find application in the hundred kilohertz switching frequency range. Recent developments in the fabrication of metal-oxide-semiconductor field-effect transistors in the power device category have enhanced the movement toward higher switching frequencies. Models for switching devices and of the circuits in which they are imbedded are required to properly characterize the mechanisms responsible for turning on and turning off effects. Easily interpreted results in the form of oscilloscope-like plots assist in understanding the effects of parametric studies using topology oriented computer-aided analysis methods.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

NASA Astrophysics Data System (ADS)

Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

2014-04-01

Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

High-performance a MoS2 nanosheet-based nonvolatile memory transistor with a ferroelectric polymer and graphene source-drain electrode

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Im, Seongil

2015-11-01

Two-dimensional (2D) van der Waals (vdWs) materials are a class of new materials due to their unique physical properties. Of the many 2D vdWs materials, molybdenum disulfide (MoS2) is a representative n-type transition-metal dichalcogenide (TMD) semiconductor. Here, we report on a high-performance MoS2 nanosheet-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. In order to enhance the ohmic contact property, we use graphene flakes as source/drain electrodes prepared by using the direct imprinting method with an elastomer stamp. The MoS2 ferroelectric field-effect transistor (FeFET) shows the highest linear electron mobility value of 175 cm2/Vs with a high on/off current ratio of more than 107, and a very clear memory window of more than 15 V. The program and erase dynamics and the static retention properties are also well demonstrated.

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

PubMed Central

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

effect of the parameters of AlN/GaN/AlGaN and AlN/GaN/InAlN heterostructures with a two-dimensional electron gas on their electrical properties and the characteristics of transistors on their basis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsatsulnikov, A. F., E-mail: andrew@beam.ioffe.ru; Lundin, V. W.; Zavarin, E. E.

The effect of the layer thickness and composition in AlGaN/AlN/GaN and InAlN/AlN/GaN transistor heterostructures with a two-dimensional electron gas on their electrical and the static parameters of test transistors fabricated from such heterostructures are experimentally and theoretically studied. It is shown that the use of an InAlN barrier layer instead of AlGaN results in a more than twofold increase in the carrier concentration in the channel, which leads to a corresponding increase in the saturation current. In situ dielectric-coating deposition on the InAlN/AlN/GaN heterostructure surface during growth process allows an increase in the maximum saturation current and breakdown voltages whilemore » retaining high transconductance.« less

Printed thin film transistors and CMOS inverters based on semiconducting carbon nanotube ink purified by a nonlinear conjugated copolymer

NASA Astrophysics Data System (ADS)

Xu, Wenya; Dou, Junyan; Zhao, Jianwen; Tan, Hongwei; Ye, Jun; Tange, Masayoshi; Gao, Wei; Xu, Weiwei; Zhang, Xiang; Guo, Wenrui; Ma, Changqi; Okazaki, Toshiya; Zhang, Kai; Cui, Zheng

2016-02-01

Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (+/-2 V) and subthreshold swing (SS) (122-161 mV dec-1), high effective mobility (up to 17.6-37.7 cm2 V-1 s-1) and high on/off ratio (104-107). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption.Two innovative research studies are reported in this paper. One is the sorting of semiconducting carbon nanotubes and ink formulation by a novel semiconductor copolymer and second is the development of CMOS inverters using not the p-type and n-type transistors but a printed p-type transistor and a printed ambipolar transistor. A new semiconducting copolymer (named P-DPPb5T) was designed and synthesized with a special nonlinear structure and more condensed conjugation surfaces, which can separate large diameter semiconducting single-walled carbon nanotubes (sc-SWCNTs) from arc discharge SWCNTs according to their chiralities with high selectivity. With the sorted sc-SWCNTs ink, thin film transistors (TFTs) have been fabricated by aerosol jet printing. The TFTs displayed good uniformity, low operating voltage (+/-2 V) and subthreshold swing (SS) (122-161 mV dec-1), high effective mobility (up to 17.6-37.7 cm2 V-1 s-1) and high on/off ratio (104-107). With the printed TFTs, a CMOS inverter was constructed, which is based on the p-type TFT and ambipolar TFT instead of the conventional p-type and n-type TFTs. Compared with other recently reported inverters fabricated by printing, the printed CMOS inverters demonstrated a better noise margin (74% 1/2 Vdd) and was hysteresis free. The inverter has a voltage gain of up to 16 at an applied voltage of only 1 V and low static power consumption. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00015k

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Technical Reliability Studies. EOS/ESD Technology Abstracts

DTIC Science & Technology

1982-01-01

RESISTANT BIPOLAR TRANSISTOR DESIGN AND ITS APPLICATIONS TO LINEAR INTEGRATED CIRCUITS 16145 MODULE ELECTROSTATIC DISCHARGE SIMULATOR 15786 SOME...T.M. 16476 STATIC DISCHARGE MODELING TECHNIQUES FOR EVALUATION OF INTEGRATED (FET) CIRCUIT DESTRUCTION 16145 MODULE ELECTAOSTATIC DISCHARGE SIMULATOR...PLASTIC LSI CIRCUITS PRklE, L.A., II 16145 MODULE ELECTROSTATIC DISCHARGE SIMULATOR PRICE, R.D. 13455 EVALUATION OF PLASTIC LSI CIRCUITS PSHAENICH, A

Measurement of brightness temperature of two-dimensional electron gas in channel of a high electron mobility transistor at ultralow dissipation power

NASA Astrophysics Data System (ADS)

Korolev, A. M.; Shulga, V. M.; Turutanov, O. G.; Shnyrkov, V. I.

2016-07-01

A technically simple and physically clear method is suggested for direct measurement of the brightness temperature of two-dimensional electron gas (2DEG) in the channel of a high electron mobility transistor (HEMT). The usage of the method was demonstrated with the pseudomorphic HEMT as a specimen. The optimal HEMT dc regime, from the point of view of the "back action" problem, was found to belong to the unsaturated area of the static characteristics possibly corresponding to the ballistic electron transport mode. The proposed method is believed to be a convenient tool to explore the ballistic transport, electron diffusion, 2DEG properties and other electrophysical processes in heterostructures.

Particle sensor array

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor); Lieneweg, Udo (Inventor)

1994-01-01

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Every Day a New 3D Printing Material

ERIC Educational Resources Information Center

Hughes, Bill; Mona, Lynn; Wilson, Greg; Seamans, Jeff; McAninch, Steve; Stout, Heath

2017-01-01

A handful of technological episodes: fire, wheel and axle, Industrial Revolution, Faraday's discovery of electromagnetic induction, the transistor, and the digital age, have historically altered humanity. We are now witnessing/participating in the next transformational technology: 3D printing. Although dating back nearly 30 years, the technology…

Comparative evaluation of power factor impovement techniques for squirrel cage induction motors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Spee, R.; Wallace, A.K.

1992-04-01

This paper describes the results obtained from a series of tests of relatively simple methods of improving the power factor of squirrel-cage induction motors. The methods, which are evaluated under controlled laboratory conditions for a 10-hp, high-efficiency motor, include terminal voltage reduction; terminal static capacitors; and a floating'' winding with static capacitors. The test results are compared with equivalent circuit model predictions that are then used to identify optimum conditions for each of the power factor improvement techniques compared with the basic induction motor. Finally, the relative economic value, and the implications of component failures, of the three methods aremore » discussed.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dell'Erba, Giorgio; Natali, Dario; Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano

Ambipolar semiconducting polymers, characterized by both high electron (μ{sub e}) and hole (μ{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μ{sub h} = 0.29 cm{sup 2}/V s and μ{sub e} = 0.001more » cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μ{sub e} = 0.12 cm{sup 2}/V s and μ{sub h} = 8 × 10{sup −4} cm{sup 2}/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.« less

A magnetic phase-transition graphene transistor with tunable spin polarization

NASA Astrophysics Data System (ADS)

Vancsó, Péter; Hagymási, Imre; Tapasztó, Levente

2017-06-01

Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge and spin signals, integrated within the simplest three-terminal device configuration. In a conventional FET device, a gate electrode is employed to tune the Fermi level of the system in and out of a static bandgap. By contrast, in the switching mechanism proposed here, the applied gate voltage can dynamically open and close an interaction gap, with only a minor shift of the Fermi level. Furthermore, the strong interplay of the band structure and edge spin configuration in zigzag ribbons enables such transistors to carry spin polarized current without employing an external magnetic field or ferromagnetic contacts. Using an experimentally validated theoretical model, we show that such transistors can switch at low voltages and high speed, and the spin polarization of the current can be tuned from 0% to 50% by using the same back gate electrode. Furthermore, such devices are expected to be robust against edge irregularities and can operate at room temperature. Controlling both charge and spin signal within the simplest FET device configuration could open up new routes in data processing with graphene based devices.

Nature of size effects in compact models of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Torkhov, N. A., E-mail: trkf@mail.ru; Scientific-Research Institute of Semiconductor Devices, Tomsk 634050; Tomsk State University of Control Systems and Radioelectronics, Tomsk 634050

Investigations have shown that in the local approximation (for sizes L < 100 μm), AlGaN/GaN high electron mobility transistor (HEMT) structures satisfy to all properties of chaotic systems and can be described in the language of fractal geometry of fractional dimensions. For such objects, values of their electrophysical characteristics depend on the linear sizes of the examined regions, which explain the presence of the so-called size effects—dependences of the electrophysical and instrumental characteristics on the linear sizes of the active elements of semiconductor devices. In the present work, a relationship has been established for the linear model parameters of themore » equivalent circuit elements of internal transistors with fractal geometry of the heteroepitaxial structure manifested through a dependence of its relative electrophysical characteristics on the linear sizes of the examined surface areas. For the HEMTs, this implies dependences of their relative static (A/mm, mA/V/mm, Ω/mm, etc.) and microwave characteristics (W/mm) on the width d of the sink-source channel and on the number of sections n that leads to a nonlinear dependence of the retrieved parameter values of equivalent circuit elements of linear internal transistor models on n and d. Thus, it has been demonstrated that the size effects in semiconductors determined by the fractal geometry must be taken into account when investigating the properties of semiconductor objects on the levels less than the local approximation limit and designing and manufacturing field effect transistors. In general, the suggested approach allows a complex of problems to be solved on designing, optimizing, and retrieving the parameters of equivalent circuits of linear and nonlinear models of not only field effect transistors but also any arbitrary semiconductor devices with nonlinear instrumental characteristics.« less

Design of a three-phase, 15-kilovolt-ampere static inverter for motor-starting a Brayton space power system

NASA Technical Reports Server (NTRS)

Frye, R. J.; Birchenough, A. G.

1971-01-01

The design of a three-phase, 400-Hz, 15-kVA static inverter for motor-starting the 2- to 15-kWe Brayton electrical space power system is described. The inverter operates from a nominal 56-V dc source to provide a 28-V, rms, quasi-square-wave output. The inverter is capable of supplying a 200-A peak current. Integrated circuitry is used to generate the three-phase, 400-Hz reference signals. Performance data for a drive stage that improves switching speed and provides efficient operation over a range of output current and drive supply voltage are presented. A transformerless, transistor output stage is used.

Nanoelectronics and Plasma Processing---The Next 15 Years and Beyond

NASA Astrophysics Data System (ADS)

Lieberman, Michael A.

2006-10-01

The number of transistors per chip has doubled every 2 years since 1959, and this doubling will continue over the next 15 years as transistor sizes shrink. There has been a 25 million-fold decrease in cost for the same performance, and in 15 years a desktop computer will be hundreds of times more powerful than one today. Transistors now have 37 nm (120 atoms) gate lengths and 1.5 nm (5 atoms) gate oxide thicknesses. The smallest working transistor has a 5 nm (17 atoms) gate length, close to the limiting gate length, from simulations, of about 4 nm. Plasma discharges are used to fabricate hundreds of billions of these nano-size transistors on a silicon wafer. These discharges have evolved from a first generation of ``low density'' reactors capacitively driven by a single source, to a second generation of ``high density'' reactors (inductive and electron cyclotron resonance) having two rf power sources, in order to control independently the ion flux and ion bombarding energy to the substrate. A third generation of ``moderate density'' reactors, driven capacitively by one high and one low frequency rf source, is now widely used. Recently, triple frequency and combined dc/dual frequency discharges have been investigated, to further control processing characteristics, such as ion energy distributions, uniformity, and plasma etch selectivities. There are many interesting physics issues associated with these discharges, including stochastic heating of discharge electrons by dual frequency sheaths, nonlinear frequency interactions, powers supplied by the multi-frequency sources, and electromagnetic effects such as standing waves and skin effects. Beyond the 4 nm transistor limit lies a decade of further performance improvements for conventional nanoelectronics, and beyond that, a dimly-seen future of spintronics, single-electron transistors, cross-bar latches, and molecular electronics.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

NASA Astrophysics Data System (ADS)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Modeling of static electrical properties in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Minari, Takeo; Tsukagoshi, Kazuhito; Gwoziecki, Romain; Coppard, Romain; Benwadih, Mohamed; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-07-01

A modeling of organic field-effect transistors' (OFETs') electrical characteristics is presented. This model is based on a one-dimensional (1-D) Poisson's equation solution that solves the potential profile in the organic semiconducting film. Most importantly, it demonstrates that, due to the common open-surface configuration used in organic transistors, the conduction occurs in the film volume below threshold. This is because the potential at the free surface is not fixed to zero but rather rises also with the gate bias. The tail of carrier concentration at the free surface is therefore significantly modulated by the gate bias, which partially explains the gate-voltage dependent contact resistance. At the same time in the so-called subthreshold region, we observe a clear charge trapping from the difference between C-V and I-V measurements; hence a traps study by numerical simulation is also performed. By combining the analytical modeling and the traps analysis, the questions on the C-V and I-V characteristics are answered. Finally, the combined results obtained with traps fit well the experimental data in both pentacene and bis(triisopropylsilylethynyl)-pentacene OFETs.

Static and dynamic behavior of a Si/Si0.8Ge0.2/Si heterojunction bipolar transistor using Monte Carlo simulation

NASA Astrophysics Data System (ADS)

Galdin, Sylvie; Dollfus, Philippe; Hesto, Patrice

1994-03-01

A theoretical study of a Si/Si1-xGex/Si heterojunction bipolar transistor using Monte Carlo simulations is reported. The geometry and composition of the emitter-base junction are optimized using one-dimensional simulations with a view to improving electron transport in the base. It is proposed to introduce a thin Si-P spacer layer, between the Si-N emitter and the SiGe-P base, which allows launching hot electrons into the base despite the lack of natural conduction-band discontinuity between Si and strain SiGe. The high-frequency behavior of the complete transistor is then studied using 2D modeling. A method of microwave analysis using small signal Monte Carlo simulations that consists of expanding the terminal currents in Fourier series is presented. A cutoff frequency fT of 68 GHz has been extracted. Finally, the occurrence of a parasitic electron barrier at the collector-base junction is responsible for the fT fall-off at high collector current density. This parasitic barrier is lowered through the influence of the collector potential.

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions.

PubMed

Trommer, Jens; Heinzig, André; Mühle, Uwe; Löffler, Markus; Winzer, Annett; Jordan, Paul M; Beister, Jürgen; Baldauf, Tim; Geidel, Marion; Adolphi, Barbara; Zschech, Ehrenfried; Mikolajick, Thomas; Weber, Walter M

2017-02-28

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

PubMed Central

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Wireless thin film transistor based on micro magnetic induction coupling antenna.

PubMed

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-12-22

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the 'internet of things' (IoT).

Wireless thin film transistor based on micro magnetic induction coupling antenna

PubMed Central

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-01-01

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the ‘internet of things’ (IoT). PMID:26691929

Improved transistorized AC motor controller for battery powered urban electric passenger vehicles

NASA Technical Reports Server (NTRS)

Peak, S. C.

1982-01-01

An ac motor controller for an induction motor electric vehicle drive system was designed, fabricated, tested, evaluated, and cost analyzed. A vehicle performance analysis was done to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of ac motor and ac controller requirements. The power inverter is a three-phase bridge using power Darlington transistors. The induction motor was optimized for use with an inverter power source. The drive system has a constant torque output to base motor speed and a constant horsepower output to maximum speed. A gear shifting transmission is not required. The ac controller was scaled from the base 20 hp (41 hp peak) at 108 volts dec to an expanded horsepower and battery voltage range. Motor reversal was accomplished by electronic reversal of the inverter phase sequence. The ac controller can also be used as a boost chopper battery charger. The drive system was tested on a dynamometer and results are presented. The current-controlled pulse width modulation control scheme yielded improved motor current waveforms. The ac controller favors a higher system voltage.

Wireless thin film transistor based on micro magnetic induction coupling antenna

NASA Astrophysics Data System (ADS)

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-12-01

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the ‘internet of things’ (IoT).

Effect of high density H 2 plasmas on InGaP/GaAs and AlGaAs/GaAs HEMTs

NASA Astrophysics Data System (ADS)

Ren, F.; Kopf, R. F.; Kuo, J. M.; Lothian, J. R.; Lee, J. W.; Pearton, S. J.; Shul, R. J.; Constantine, C.; Johnson, D.

1998-05-01

InGaP/GaAs and AlGaAs/GaAs high electron mobility transistors have been exposed to inductively coupled plasma or electron cyclotron resonance H 2 plasmas as a function of pressure, source power and rf chuck power. The transconductance, gate ideality factor and saturated drain-source current are all degraded by the plasma treatment. Two mechanisms are identified: passivation of Si dopants in the InGaP or AlGaAs donor layers by H 0 and lattice disorder created by H + and H 2+ ion bombardment. HEMTs are found to be more susceptible to plasma-induced degradation than heterojunction bipolar transistors.

Cycle of charge carrier states with formation and extinction of a floating gate in an ambipolar tetracyanoquaterthienoquinoid-based field-effect transistor

NASA Astrophysics Data System (ADS)

Itoh, Takuro; Toyota, Taro; Higuchi, Hiroyuki; Matsushita, Michio M.; Suzuki, Kentaro; Sugawara, Tadashi

2017-03-01

A tetracyanoquaterthienoquinoid (TCT4Q)-based field effect transistor is characterized by the ambipolar transfer characteristics and the facile shift of the threshold voltage induced by the bias stress. The trapping and detrapping kinetics of charge carriers was investigated in detail by the temperature dependence of the decay of source-drain current (ISD). We found a repeatable formation of a molecular floating gate is derived from a 'charge carrier-and-gate' cycle comprising four stages, trapping of mobile carriers, formation of a floating gate, induction of oppositely charged mobile carriers, and recombination between mobile and trapped carriers to restore the initial state.

An improved model to predict bandwidth enhancement in an inductively tuned common source amplifier.

PubMed

Reza, Ashif; Misra, Anuraag; Das, Parnika

2016-05-01

This paper presents an improved model for the prediction of bandwidth enhancement factor (BWEF) in an inductively tuned common source amplifier. In this model, we have included the effect of drain-source channel resistance of field effect transistor along with load inductance and output capacitance on BWEF of the amplifier. A frequency domain analysis of the model is performed and a closed-form expression is derived for BWEF of the amplifier. A prototype common source amplifier is designed and tested. The BWEF of amplifier is obtained from the measured frequency response as a function of drain current and load inductance. In the present work, we have clearly demonstrated that inclusion of drain-source channel resistance in the proposed model helps to estimate the BWEF, which is accurate to less than 5% as compared to the measured results.

MOSFET Electric-Charge Sensor

NASA Technical Reports Server (NTRS)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Pinch current limitation effect in plasma focus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, S.; Saw, S. H.; INTI International University College, 71800 Nilai

The Lee model couples the electrical circuit with plasma focus dynamics, thermodynamics, and radiation. It is used to design and simulate experiments. A beam-target mechanism is incorporated, resulting in realistic neutron yield scaling with pinch current and increasing its versatility for investigating all Mather-type machines. Recent runs indicate a previously unsuspected 'pinch current limitation' effect. The pinch current does not increase beyond a certain value however low the static inductance is reduced to. The results indicate that decreasing the present static inductance of the PF1000 machine will neither increase the pinch current nor the neutron yield, contrary to expectations.

Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs

NASA Astrophysics Data System (ADS)

Ibrahim, Mohamed Farhat

Silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) have the properties of producing very low noise and high gain over a wide bandwidth. Because of these properties, SiGe HBTs have continually improved and now compete with InP and GaAs HEMTs for low-noise amplification. This thesis investigates the theoretical characterizations and optimizations of SiGe HBT low noise amplifiers (LNAs) for low-noise low-power applications, using SiGe BiCMOS (bipolar complementary metal-oxide-semiconductor) technology. The theoretical characterization of SiGe HBT transistors is investigated by a comprehensive study of the DC and small-signal transistor modeling. Based on a selected small-signal model, a noise model for the SiGe HBT transistor is produced. This noise model is used to build a cascode inductively degenerated SiGe HBT LNA circuit. The noise figure (NF) equation for this LNA is derived. This NF equation shows better than 94.4% agreement with the simulation results. With the small-signal model verification, a new analytical method for optimizing the noise figure of the SiGe HBT LNA circuits is presented. The novelty feature of this optimization is the inclusion of the noise contributions of the base inductor parasitic resistance, the emitter inductor parasitic resistance and the bond-wire inductor parasitic resistances. The optimization is performed by reducing the number of design variables as possible. This improved theoretical optimization results in LNA designs that achieve better noise figure performance compared to previously published results in bipolar and BiCMOS technologies. Different design constraints are discussed for the LNA optimization techniques. Three different LNAs are designed. The three designs are fully integrated and fabricated in a single chip to achieve a fully monolithic realization. The LNA designs are experimentally verified. The low noise design produced a NF of 1.5dB, S21 of 15dB, and power consumption of 15mW. The three LNA designs occupied 1.4mum 2 in 130 nm BiCMOS technology.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

PubMed

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B; Lindau, Manfred; Holowka, David A; Baird, Barbara A; Kan, Edwin C

2015-12-21

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors

PubMed Central

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B.; Lindau, Manfred; Holowka, David A.; Baird, Barbara A.; Kan, Edwin C.

2015-01-01

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry. PMID:26686301

Naval Research Laboratory 1986 Review

DTIC Science & Technology

1986-01-01

Behavior and Properties of Materials 84 Constrained- Layer Damping of Structure-Borne Sound 85 Computer-Controlled Emissivity Measurement System 87...Epitaxial Layers 128 Phase-Controlltd Gyrotron Oscillators 130 -SiC Transistor Development 133 Kinetic Inductance Microstrip Lines 136 Energetic...experiments in --- the areas of upper atmospheric, solar , and astro- ., ._ .nomical research aboard NASA, DoD, and foreign space projects. Division

Immediate Effects of Kinesiology Taping of Quadriceps on Motor Performance after Muscle Fatigued Induction.

PubMed

Ahn, Ick Keun; Kim, You Lim; Bae, Young-Hyeon; Lee, Suk Min

2015-01-01

Objectives. The purpose of this cross-sectional single-blind study was to investigate the immediate effects of Kinesiology taping of quadriceps on motor performance after muscle fatigued induction. Design. Randomized controlled cross-sectional design. Subjects. Forty-five subjects participated in this study. Participants were divided into three groups: Kinesiology taping group, placebo taping group, and nontaping group. Methods. Subjects performed short-term exercise for muscle fatigued induction, followed by the application of each intervention. Peak torque test, one-leg single hop test, active joint position sense test, and one-leg static balance test were carried out before and after the intervention. Results. Peak torque and single-leg hopping distance were significantly increased when Kinesiology taping was applied (p < 0.05). But there were no significant effects on active joint position sense and single-leg static balance. Conclusions. We proved that Kinesiology taping is effective in restoring muscle power reduced after muscle fatigued induction. Therefore, we suggest that Kinesiology taping is beneficial for fatigued muscles.

Comparison and statistical analysis of four write stability metrics in bulk CMOS static random access memory cells

NASA Astrophysics Data System (ADS)

Qiu, Hao; Mizutani, Tomoko; Saraya, Takuya; Hiramoto, Toshiro

2015-04-01

The commonly used four metrics for write stability were measured and compared based on the same set of 2048 (2k) six-transistor (6T) static random access memory (SRAM) cells by the 65 nm bulk technology. The preferred one should be effective for yield estimation and help predict edge of stability. Results have demonstrated that all metrics share the same worst SRAM cell. On the other hand, compared to butterfly curve with non-normality and write N-curve where no cell state flip happens, bit-line and word-line margins have good normality as well as almost perfect correlation. As a result, both bit line method and word line method prove themselves preferred write stability metrics.

Electric characteristics of a surface barrier discharge with a plasma induction electrode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alemskii, I. N.; Lelevkin, V. M.; Tokarev, A. V.

2006-07-15

Static and dynamic current-voltage and charge-voltage characteristics of a surface barrier discharge with a plasma induction electrode have been investigated experimentally. The dependences of the discharge current on both the gas pressure in the induction electrode tube and the winding pitch of the corona electrode, as well as of the discharge power efficiency on the applied voltage, have been measured.

Gaining Insight Into Femtosecond-scale CMOS Effects using FPGAs

DTIC Science & Technology

2015-03-24

paths or detecting gross path delay faults , but for characterizing subtle aging effects, there is a need to isolate very short paths and detect very...data using COTS FPGAs and novel self-test. Hardware experiments using a 28 nm FPGA demonstrate isolation of small sets of transistors, detection of...hold the static configuration data specifying the LUT function. A set of inverters drive the SRAM contents into a pass-gate multiplexor tree; we

Comparative Demonstration and Evaluation of Classification Technologies: Closed Castner Range, Fort Bliss, Texas

DTIC Science & Technology

2017-01-23

of classification technologies for Munitions Response (MR). This demonstration was designed to evaluate advanced classification methodology at the...advanced electromagnetic induction sensors and static, cued surveys to classify anomalies as either targets of interest (TOI) or non -TOI. Static data...17  5.1  Conceptual Experimental Design

Perform MetalMapper Classification Treatability Investigations as Part of Remedial Investigation/Feasibility Studies: Live Site Demonstrations: Pueblo Chemical Depot

DTIC Science & Technology

2016-03-14

DoD Department of Defense EMI electromagnetic induction ESTCP Environmental Security Technology Certification Program ft. foot GPS global...three primary objectives:  Test and validate detection and discrimination capabilities of a currently available advanced electromagnetic induction ... induction (EMI) sensors in dynamic and static data acquisition modes and associated analysis software. To achieve these objectives, a controlled test was

Inductively Coupled Plasma and Electron Cyclotron Resonance Plasma Etching of InGaAlP Compound Semiconductor System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Abernathy, C.R.; Hobson, W.S.; Hong, J.

1998-11-04

Current and future generations of sophisticated compound semiconductor devices require the ability for submicron scale patterning. The situation is being complicated since some of the new devices are based on a wider diversity of materials to be etched. Conventional IUE (Reactive Ion Etching) has been prevalent across the industry so far, but has limitations for materials with high bond strengths or multiple elements. IrI this paper, we suggest high density plasmas such as ECR (Electron Cyclotron Resonance) and ICP (Inductively Coupled Plasma), for the etching of ternary compound semiconductors (InGaP, AIInP, AlGaP) which are employed for electronic devices like heterojunctionmore » bipolar transistors (HBTs) or high electron mobility transistors (HEMTs), and photonic devices such as light-emitting diodes (LEDs) and lasers. High density plasma sources, opeiating at lower pressure, are expected to meet target goals determined in terms of etch rate, surface morphology, surface stoichiometry, selectivity, etc. The etching mechanisms, which are described in this paper, can also be applied to other III-V (GaAs-based, InP-based) as well as III-Nitride since the InGaAIP system shares many of the same properties.« less

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

NASA Technical Reports Server (NTRS)

Eldin, A. G.

1991-01-01

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Effect of Static and Rotating Magnetic Fields on Low-Temperature Fabrication of InGaZnO Thin-Film Transistors.

PubMed

Park, Jeong Woo; Tak, Young Jun; Na, Jae Won; Lee, Heesoo; Kim, Won-Gi; Kim, Hyun Jae

2018-05-16

We suggest thermal treatment with static magnetic fields (SMFs) or rotating magnetic fields (RMFs) as a new technique for the activation of indium-gallium-zinc oxide thin-film transistors (IGZO TFTs). Magnetic interactions between metal atoms in IGZO films and oxygen atoms in air by SMFs or RMFs can be expected to enhance metal-oxide (M-O) bonds, even at low temperature (150 °C), through attraction of metal and oxygen atoms having their magnetic moments aligned in the same direction. Compared to IGZO TFTs with only thermal treatment at 300 °C, IGZO TFTs under an RMF (1150 rpm) at 150 °C show superior or comparable characteristics: field-effect mobility of 12.68 cm 2 V -1 s -1 , subthreshold swing of 0.37 V dec -1 , and on/off ratio of 1.86 × 10 8 . Although IGZO TFTs under an SMF (0 rpm) can be activated at 150 °C, the electrical performance is further improved in IGZO TFTs under an RMF (1150 rpm). These improvements of IGZO TFTs under an RMF (1150 rpm) are induced by increases in the number of M-O bonds due to enhancement of the magnetic interaction per unit time as the rpm value increases. We suggest that this new process of activating IGZO TFTs at low temperature widens the choice of substrates in flexible or transparent devices.

On utilizing alternating current-flow field effect transistor for flexibly manipulating particles in microfluidics and nanofluidics

PubMed Central

Liu, Weiyu; Shao, Jinyou; Ren, Yukun; Liu, Jiangwei; Tao, Ye; Jiang, Hongyuan; Ding, Yucheng

2016-01-01

By imposing a biased gate voltage to a center metal strip, arbitrary symmetry breaking in induced-charge electroosmotic flow occurs on the surface of this planar gate electrode, a phenomenon termed as AC-flow field effect transistor (AC-FFET). In this work, the potential of AC-FFET with a shiftable flow stagnation line to flexibly manipulate micro-nano particle samples in both a static and continuous flow condition is demonstrated via theoretical analysis and experimental validation. The effect of finite Debye length of induced double-layer and applied field frequency on the manipulating flexibility factor for static condition is investigated, which indicates AC-FFET turns out to be more effective for achieving a position-controllable concentrating of target nanoparticle samples in nanofluidics compared to the previous trial in microfluidics. Besides, a continuous microfluidics-based particle concentrator/director is developed to deal with incoming analytes in dynamic condition, which exploits a design of tandem electrode configuration to consecutively flow focus and divert incoming particle samples to a desired downstream branch channel, as prerequisite for a following biochemical analysis. Our physical demonstrations with AC-FFET prove valuable for innovative designs of flexible electrokinetic frameworks, which can be conveniently integrated with other microfluidic or nanofluidic components into a complete lab-on-chip diagnostic platform due to a simple electrode structure. PMID:27190570

On utilizing alternating current-flow field effect transistor for flexibly manipulating particles in microfluidics and nanofluidics.

PubMed

Liu, Weiyu; Shao, Jinyou; Ren, Yukun; Liu, Jiangwei; Tao, Ye; Jiang, Hongyuan; Ding, Yucheng

2016-05-01

By imposing a biased gate voltage to a center metal strip, arbitrary symmetry breaking in induced-charge electroosmotic flow occurs on the surface of this planar gate electrode, a phenomenon termed as AC-flow field effect transistor (AC-FFET). In this work, the potential of AC-FFET with a shiftable flow stagnation line to flexibly manipulate micro-nano particle samples in both a static and continuous flow condition is demonstrated via theoretical analysis and experimental validation. The effect of finite Debye length of induced double-layer and applied field frequency on the manipulating flexibility factor for static condition is investigated, which indicates AC-FFET turns out to be more effective for achieving a position-controllable concentrating of target nanoparticle samples in nanofluidics compared to the previous trial in microfluidics. Besides, a continuous microfluidics-based particle concentrator/director is developed to deal with incoming analytes in dynamic condition, which exploits a design of tandem electrode configuration to consecutively flow focus and divert incoming particle samples to a desired downstream branch channel, as prerequisite for a following biochemical analysis. Our physical demonstrations with AC-FFET prove valuable for innovative designs of flexible electrokinetic frameworks, which can be conveniently integrated with other microfluidic or nanofluidic components into a complete lab-on-chip diagnostic platform due to a simple electrode structure.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

High-Performance Power-Semiconductor Packages

NASA Technical Reports Server (NTRS)

Renz, David; Hansen, Irving; Berman, Albert

1989-01-01

A 600-V, 50-A transistor and 1,200-V, 50-A diode in rugged, compact, lightweight packages intended for use in inverter-type power supplies having switching frequencies up to 20 kHz. Packages provide low-inductance connections, low loss, electrical isolation, and long-life hermetic seal. Low inductance achieved by making all electrical connections to each package on same plane. Also reduces high-frequency losses by reducing coupling into inherent shorted turns in packaging material around conductor axes. Stranded internal power conductors aid conduction at high frequencies, where skin effect predominates. Design of packages solves historical problem of separation of electrical interface from thermal interface of high-power semiconductor device.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Instrumentation for measuring aircraft noise and sonic boom

NASA Technical Reports Server (NTRS)

Zuckerwar, A. J. (Inventor)

1976-01-01

Improved instrumentation suitable for measuring aircraft noise and sonic booms is described. An electric current proportional to the sound pressure level at a condenser microphone is produced and transmitted over a cable and amplified by a zero drive amplifier. The converter consists of a local oscillator, a dual-gate field-effect transistor mixer, and a voltage regulator/impedance translator. The improvements include automatic tuning compensation against changes in static microphone capacitance and means for providing a remote electrical calibration capability.

High-performance hybrid complementary logic inverter through monolithic integration of a MEMS switch and an oxide TFT.

PubMed

Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo

2015-03-25

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

In situ determination of the static inductance and resistance of a plasma focus capacitor bank.

PubMed

Saw, S H; Lee, S; Roy, F; Chong, P L; Vengadeswaran, V; Sidik, A S M; Leong, Y W; Singh, A

2010-05-01

The static (unloaded) electrical parameters of a capacitor bank are of utmost importance for the purpose of modeling the system as a whole when the capacitor bank is discharged into its dynamic electromagnetic load. Using a physical short circuit across the electromagnetic load is usually technically difficult and is unnecessary. The discharge can be operated at the highest pressure permissible in order to minimize current sheet motion, thus simulating zero dynamic load, to enable bank parameters, static inductance L(0), and resistance r(0) to be obtained using lightly damped sinusoid equations given the bank capacitance C(0). However, for a plasma focus, even at the highest permissible pressure it is found that there is significant residual motion, so that the assumption of a zero dynamic load introduces unacceptable errors into the determination of the circuit parameters. To overcome this problem, the Lee model code is used to fit the computed current trace to the measured current waveform. Hence the dynamics is incorporated into the solution and the capacitor bank parameters are computed using the Lee model code, and more accurate static bank parameters are obtained.

In situ determination of the static inductance and resistance of a plasma focus capacitor bank

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saw, S. H.; Institute for Plasma Focus Studies, 32 Oakpark Drive, Chadstone, Victoria 3148; Lee, S.

2010-05-15

The static (unloaded) electrical parameters of a capacitor bank are of utmost importance for the purpose of modeling the system as a whole when the capacitor bank is discharged into its dynamic electromagnetic load. Using a physical short circuit across the electromagnetic load is usually technically difficult and is unnecessary. The discharge can be operated at the highest pressure permissible in order to minimize current sheet motion, thus simulating zero dynamic load, to enable bank parameters, static inductance L{sub 0}, and resistance r{sub 0} to be obtained using lightly damped sinusoid equations given the bank capacitance C{sub 0}. However, formore » a plasma focus, even at the highest permissible pressure it is found that there is significant residual motion, so that the assumption of a zero dynamic load introduces unacceptable errors into the determination of the circuit parameters. To overcome this problem, the Lee model code is used to fit the computed current trace to the measured current waveform. Hence the dynamics is incorporated into the solution and the capacitor bank parameters are computed using the Lee model code, and more accurate static bank parameters are obtained.« less

Origin of low-frequency noise in pentacene field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Minari, Takeo; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-07-01

Measurements of power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors reveal the preponderance of a 1/ f-type PSD behavior with the amplitude varying as the squared transistor gain and increasing as the inverse of the gate surface area. Such features impose an interpretation of LFN by carrier number fluctuations model involving capture/release of charges on traps uniformly distributed over the gate surface. The surface slow trap density extracted by the noise analysis is close to the surface states density deduced independently from static I(V) data, which confirms the validity of the proposed LFN interpretation. Further, we found that the trap densities in bottom-contact (BC) devices were higher than in their top-contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in the contact regions in particular. At the highest bias the noise originating from the contact resistance is also shown to be a dominant component in the PSD, and it is well explained by the noise originating from a gate-voltage dependent contact resistance. A gate area scaling was also performed, and the good scaling and the dispersion at the highest bias confirm the validity of the applied carrier number fluctuations model and the predominant contact noise at high current intensities.

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

DTIC Science & Technology

2015-10-13

transistors. There are several reasons for this gigantic disparity: insufficient funding and lack of profit-driven investments in superconductor ...Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers,” IEEE Trans. Appl. Supercond., vol...vol. 25, No. 3, 1301704, June 2015. [7] V. Ambegaokar and A. Baratoff, “Tunneling between superconductors ,” Phys. Rev. Lett., vol. 10, no. 11, pp

Structure of the Global Nanoscience and Nanotechnology Research Literature

DTIC Science & Technology

2006-01-01

Transistors, Nature, 424 (6949): 654-657, 2003. Joannopoulos, JD, Meade, RD, Winn, JN, Photonic Crystals: Molding the Flow of Light, Princeton...1.27 Force Microscopy 40 0.10 0.00 Electron Spectroscopy 40 0.10 0.00 Rutherford backscattering spectrometry 38 0.10 0.00 flow cytometry 36 0.09...Backscattering Spectroscopy/Spectrometry • Flow Cytometry • Spectrophotometry (UV-Visible) • Deep Level Transient Spectroscopy • Inductively

Gallium Nitride (GaN) High Power Electronics (FY11)

DTIC Science & Technology

2012-01-01

GaN films grown by metal-organic chemical vapor deposition (MOCVD) and ~1010 in films grown by molecular beam epitaxy (MBE) when they are deposited...inductively coupled plasma I-V current-voltage L-HVPE low doped HVPE MBE molecular beam epitaxy MOCVD metal-organic chemical vapor deposition...figure of merit HEMT high electron mobility transistor H-HVPE high doped HVPE HPE high power electronics HVPE hydride vapor phase epitaxy ICP

Comparative Study of Fault Diagnostic Methods in Voltage Source Inverter Fed Three Phase Induction Motor Drive

NASA Astrophysics Data System (ADS)

Dhumale, R. B.; Lokhande, S. D.

2017-05-01

Three phase Pulse Width Modulation inverter plays vital role in industrial applications. The performance of inverter demeans as several types of faults take place in it. The widely used switching devices in power electronics are Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Field Effect Transistors (MOSFET). The IGBTs faults are broadly classified as base or collector open circuit fault, misfiring fault and short circuit fault. To develop consistency and performance of inverter, knowledge of fault mode is extremely important. This paper presents the comparative study of IGBTs fault diagnosis. Experimental set up is implemented for data acquisition under various faulty and healthy conditions. Recent methods are executed using MATLAB-Simulink and compared using key parameters like average accuracy, fault detection time, implementation efforts, threshold dependency, and detection parameter, resistivity against noise and load dependency.

4 Kelvin Cryogenic Characterization of Commercial pHEMT Transistors at 9 kHz to 8.5 GHz Range

NASA Astrophysics Data System (ADS)

Ibarra-Medel, E.; Velázquez, M.; Ventura, S.; Ferrusca, D.; Gómez-Rivera, V.

2016-07-01

Nowadays, the technology innovations in large format array detectors at low temperature for millimetric observational astronomy demand the development of electronics capable to keep their functionality at cryogenic temperatures. In kinetic inductance detectors, the first stage of electronics readout requires high-bandwidth low-noise amplifiers (LNAs). These devices are commonly fabricated in monolithic microwave integrated circuit (MMIC) processes which commercially achieve a noise temperature level of 5 K. An alternative approach to the MMIC are the hybrid microwave circuit which mixes RF lumped elements and discrete electronic components. This paper describes the characterization of six commercial pHEMT transistors tested at cryogenic temperatures. DC properties such as I-V curves and transconductance (g_m) were measured for each transistor; these measurements allow us to calculate the best bias point versus gain, with the lowest noise figure and power consumption within the range of 9 kHz to 8.5 GHz at the operating temperature of 4 K. Experimental results suggest that the characterized pHEMTs have a noise figure that allow them to be used in hybrid LNAs arranges with a comparable MMIC performance.

Performance evaluation of bottom gate ZnO based thin film transistors with different W/L ratios for UV sensing

NASA Astrophysics Data System (ADS)

Varma, Tarun; Periasamy, C.; Boolchandani, Dharmendar

2018-02-01

In this paper, we report the simulation, fabrication and characterisation of UV photo-detectors with bottom gate ZnO Thin Film Transistors (TFTs), grown on silicon at room temperature using RF magnetron sputtering process. The static performance of these detectors have been explored by varying the channel lengths (6 μm and 12 μm). The fabricated devices show low leakage currents with threshold voltages of 1.18 & 2.33 V, sub-threshold swings of 13.5 & 12.8 V/dec for channel lengths of 6 μm and 12 μm TFT, respectively. They also exhibit superior electrical characteristics with an ON-OFF ratio of the order of 3. The detector was also tested for device stability, with the transfer characteristics of the TFTs, which got deteriorated mainly by the negative bias-stress. The TFTs were further tested for UV detector applications and found to exhibit good photo-response.

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

2008-08-01

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

NASA Astrophysics Data System (ADS)

Shauly, Eitan N.; Levi, Shimon; Schwarzband, Ishai; Adan, Ofer; Latinsky, Sergey

2015-04-01

A fully automated silicon-based methodology for systematic analysis of electrical features is shown. The system was developed for process monitoring and electrical variability reduction. A mapping step was created by dedicated structures such as static-random-access-memory (SRAM) array or standard cell library, or by using a simple design rule checking run-set. The resulting database was then used as an input for choosing locations for critical dimension scanning electron microscope images and for specific layout parameter extraction then was input to SPICE compact modeling simulation. Based on the experimental data, we identified two items that must be checked and monitored using the method described here: transistor's sensitivity to the distance between the poly end cap and edge of active area (AA) due to AA rounding, and SRAM leakage due to a too close N-well to P-well. Based on this example, for process monitoring and variability analyses, we extensively used this method to analyze transistor gates having different shapes. In addition, analysis for a large area of high density standard cell library was done. Another set of monitoring focused on a high density SRAM array is also presented. These examples provided information on the poly and AA layers, using transistor parameters such as leakage current and drive current. We successfully define "robust" and "less-robust" transistor configurations included in the library and identified unsymmetrical transistors in the SRAM bit-cells. These data were compared to data extracted from the same devices at the end of the line. Another set of analyses was done to samples after Cu M1 etch. Process monitoring information on M1 enclosed contact was extracted based on contact resistance as a feedback. Guidelines for the optimal M1 space for different layout configurations were also extracted. All these data showed the successful in-field implementation of our methodology as a useful process monitoring method.

Quantitative prediction of repaglinide-rifampicin complex drug interactions using dynamic and static mechanistic models: delineating differential CYP3A4 induction and OATP1B1 inhibition potential of rifampicin.

PubMed

Varma, Manthena V S; Lin, Jian; Bi, Yi-An; Rotter, Charles J; Fahmi, Odette A; Lam, Justine L; El-Kattan, Ayman F; Goosen, Theunis C; Lai, Yurong

2013-05-01

Repaglinide is mainly metabolized by cytochrome P450 enzymes CYP2C8 and CYP3A4, and it is also a substrate to a hepatic uptake transporter, organic anion transporting polypeptide (OATP)1B1. The purpose of this study is to predict the dosing time-dependent pharmacokinetic interactions of repaglinide with rifampicin, using mechanistic models. In vitro hepatic transport of repaglinide, characterized using sandwich-cultured human hepatocytes, and intrinsic metabolic parameters were used to build a dynamic whole-body physiologically-based pharmacokinetic (PBPK) model. The PBPK model adequately described repaglinide plasma concentration-time profiles and successfully predicted area under the plasma concentration-time curve ratios of repaglinide (within ± 25% error), dosed (staggered 0-24 hours) after rifampicin treatment when primarily considering induction of CYP3A4 and reversible inhibition of OATP1B1 by rifampicin. Further, a static mechanistic "extended net-effect" model incorporating transport and metabolic disposition parameters of repaglinide and interaction potency of rifampicin was devised. Predictions based on the static model are similar to those observed in the clinic (average error ∼19%) and to those based on the PBPK model. Both the models suggested that the combined effect of increased gut extraction and decreased hepatic uptake caused minimal repaglinide systemic exposure change when repaglinide is dosed simultaneously or 1 hour after the rifampicin dose. On the other hand, isolated induction effect as a result of temporal separation of the two drugs translated to an approximate 5-fold reduction in repaglinide systemic exposure. In conclusion, both dynamic and static mechanistic models are instrumental in delineating the quantitative contribution of transport and metabolism in the dosing time-dependent repaglinide-rifampicin interactions.

SQUID-based microwave cavity search for dark-matter axions.

PubMed

Asztalos, S J; Carosi, G; Hagmann, C; Kinion, D; van Bibber, K; Hotz, M; Rosenberg, L J; Rybka, G; Hoskins, J; Hwang, J; Sikivie, P; Tanner, D B; Bradley, R; Clarke, J

2010-01-29

Axions in the microeV mass range are a plausible cold dark-matter candidate and may be detected by their conversion into microwave photons in a resonant cavity immersed in a static magnetic field. We report the first result from such an axion search using a superconducting first-stage amplifier (SQUID) replacing a conventional GaAs field-effect transistor amplifier. This experiment excludes KSVZ dark-matter axions with masses between 3.3 microeV and 3.53 microeV and sets the stage for a definitive axion search utilizing near quantum-limited SQUID amplifiers.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Specific spice modeling of microcrystalline silicon TFTs

NASA Astrophysics Data System (ADS)

Moustapha, O.; Bui, V. D.; Bonnassieux, Y.; Parey, J. Y.

2008-03-01

In this paper we present a specific spice static and dynamic model of microcrystalline silicon (μc-Si) thin film transistors (TFTs) taking into account the access resistances and the capacitors contributions. The previously existing models of amorphous silicon and polysilicon TFTs were not completely suited, so we combined them to build a new specific model of μc-Si TFTs. The reliability of the model is then checked by the comparison of experimental measurements to simulations and by simulating the characteristics of some electronic devices (OLED pixels, inverters, and so on).

Magnetoacoustic Tomography with Magnetic Induction: A Rigorous Theory

PubMed Central

Ma, Qingyu; He, Bin

2013-01-01

We have proposed a new theory on mechanism of the magnetoacoustic signal generation with magnetic induction for an object with an arbitrary shape. An object under a static magnetic field emits acoustic signals when excited by a time-varying magnetic field, and that the acoustic waveform is mainly generated at the conductivity boundaries within the object. The proposed theory on the magnetoacoustic tomography with magnetic induction produced highly consistent results among computational and experimental paradigms in a two-layer sample phantom and suggests the potential applications for bioimpedance imaging. PMID:18270025

Inductive detection of the free surface of liquid metals

NASA Astrophysics Data System (ADS)

Zürner, Till; Ratajczak, Matthias; Wondrak, Thomas; Eckert, Sven

2017-11-01

A novel measurement system to determine the surface position and topology of liquid metals is presented. It is based on the induction of eddy currents by a time-harmonic magnetic field and the subsequent measurement of the resulting secondary magnetic field using gradiometric induction coils. The system is validated experimentally for static and dynamic surfaces of the low-melting liquid metal alloy gallium-indium-tin in a narrow vessel. It is shown that a precision below 1 mm and a time resolution of at least 20 Hz can be achieved.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Carbon Nanotube Driver Circuit for 6 × 6 Organic Light Emitting Diode Display

NASA Astrophysics Data System (ADS)

Zou, Jianping; Zhang, Kang; Li, Jingqi; Zhao, Yongbiao; Wang, Yilei; Pillai, Suresh Kumar Raman; Volkan Demir, Hilmi; Sun, Xiaowei; Chan-Park, Mary B.; Zhang, Qing

2015-06-01

Single-walled carbon nanotube (SWNT) is expected to be a very promising material for flexible and transparent driver circuits for active matrix organic light emitting diode (AM OLED) displays due to its high field-effect mobility, excellent current carrying capacity, optical transparency and mechanical flexibility. Although there have been several publications about SWNT driver circuits, none of them have shown static and dynamic images with the AM OLED displays. Here we report on the first successful chemical vapor deposition (CVD)-grown SWNT network thin film transistor (TFT) driver circuits for static and dynamic AM OLED displays with 6 × 6 pixels. The high device mobility of ~45 cm2V-1s-1 and the high channel current on/off ratio of ~105 of the SWNT-TFTs fully guarantee the control capability to the OLED pixels. Our results suggest that SWNT-TFTs are promising backplane building blocks for future OLED displays.

Carbon Nanotube Driver Circuit for 6 × 6 Organic Light Emitting Diode Display.

PubMed

Zou, Jianping; Zhang, Kang; Li, Jingqi; Zhao, Yongbiao; Wang, Yilei; Pillai, Suresh Kumar Raman; Volkan Demir, Hilmi; Sun, Xiaowei; Chan-Park, Mary B; Zhang, Qing

2015-06-29

Single-walled carbon nanotube (SWNT) is expected to be a very promising material for flexible and transparent driver circuits for active matrix organic light emitting diode (AM OLED) displays due to its high field-effect mobility, excellent current carrying capacity, optical transparency and mechanical flexibility. Although there have been several publications about SWNT driver circuits, none of them have shown static and dynamic images with the AM OLED displays. Here we report on the first successful chemical vapor deposition (CVD)-grown SWNT network thin film transistor (TFT) driver circuits for static and dynamic AM OLED displays with 6 × 6 pixels. The high device mobility of ~45 cm(2)V(-1)s(-1) and the high channel current on/off ratio of ~10(5) of the SWNT-TFTs fully guarantee the control capability to the OLED pixels. Our results suggest that SWNT-TFTs are promising backplane building blocks for future OLED displays.

Temperature responsive transmitter

NASA Technical Reports Server (NTRS)

Kleinberg, Leonard L. (Inventor)

1987-01-01

A temperature responsive transmitter is provided in which frequency varies linearly with temperature. The transmitter includes two identically biased transistors connected in parallel. A capacitor, which reflects into the common bases to generate negative resistance effectively in parallel with the capacitor, is connected to the common emitters. A crystal is effectively in parallel with the capacitor and the negative resistance. Oscillations occur if the magnitude of the absolute value of the negative resistance is less than the positive resistive impedance of the capacitor and the inductance of the crystal. The crystal has a large linear temperature coefficient and a resonant frequency which is substantially less than the gain-bandwidth product of the transistors to ensure that the crystal primarily determines the frequency of oscillation. A high-Q tank circuit having an inductor and a capacitor is connected to the common collectors to increase the collector current flow which in turn enhances the radiation of the oscillator frequency by the inductor.

Analysis of High Power IGBT Short Circuit Failures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pappas, G.

2005-02-11

The Next Linear Collider (NLC) accelerator proposal at SLAC requires a highly efficient and reliable, low cost, pulsed-power modulator to drive the klystrons. A solid-state induction modulator has been developed at SLAC to power the klystrons; this modulator uses commercial high voltage and high current Insulated Gate Bipolar Transistor (IGBT) modules. Testing of these IGBT modules under pulsed conditions was very successful; however, the IGBTs failed when tests were performed into a low inductance short circuit. The internal electrical connections of a commercial IGBT module have been analyzed to extract self and mutual partial inductances for the main current pathsmore » as well as for the gate structure. The IGBT module, together with the partial inductances, has been modeled using PSpice. Predictions for electrical paths that carry the highest current correlate with the sites of failed die under short circuit tests. A similar analysis has been carried out for a SLAC proposal for an IGBT module layout. This paper discusses the mathematical model of the IGBT module geometry and presents simulation results.« less

Characterization of metal oxide field-effect transistors for first helical tomotherapy Hi-Art II unit in India.

PubMed

Kinhikar, Rajesh A; Pai, Rajeshree; Master, Zubin; Deshpande, Deepak D

2009-01-01

To characterize metal oxide semiconductor field-effect transistors (MOSFETs) for a 6-MV photon beam with a first helical tomotherapy Hi-Art II unit in India. Standard sensitivity MOSFETs were first calibrated and then characterized for reproducibility, field size dependence, angular dependence, fade effects, and temperature dependence. The detector sensitivity was estimated for static as well as rotational modes for three jaw settings (1.0 cm x 40 cm, 2.5 cm x 40 cm, and 5 cm x 40 cm) at 1.5-cm depth with a source-to-axis distance (SAD) of 85 cm in virtual water slabs. The A1SL ion chamber and thermoluminescence dosimeters (TLDs) were used to compare the results. No significant difference was found in the detector sensitivity for static and rotational procedures. The average detector sensitivity for static procedures was 1.10 mV/cGy (SD 0.02) while it was 1.12 mV/cGy (SD 0.02) for rotational procedures. The average detector sensitivity found was the same within the experimental uncertainty for static and rotational dose deliveries. The MOSFET reading was consistent and its reproducibility was excellent (+0.5%) while there was no significant dependence of field size. The angular dependence of less than 1.0% was observed. There was negligible fading effect of the MOSFET. The MOSFET response was found independent of temperature in the range 18 degrees-30 degrees. The ion chamber readings were assumed to be a reference for the estimation of the MOSFET calibration factor. The ion chamber and the TLD were in good agreement (+2%) with each other. This study deals only with the measurements and calibration performed on the surface of the phantom. MOSFET was calibrated and validated for phantom surface measurements for a 6-MV photon beam generated by a tomotherapy machine. The sensitivity of the detector was the same for both modes of treatment delivery with tomotherapy. The performance of the MOSFET was validated for and satisfactory for the helical tomotherapy Hi-Art II unit. However, MOSFET may be used for in vivo surface dosimetry only after it is calibrated under the conditions replicating as much as possible the manner in which the dosimeter will be used clinically.

Enhanced efficiency of solid-state NMR investigations of energy materials using an external automatic tuning/matching (eATM) robot.

PubMed

Pecher, Oliver; Halat, David M; Lee, Jeongjae; Liu, Zigeng; Griffith, Kent J; Braun, Marco; Grey, Clare P

2017-02-01

We have developed and explored an external automatic tuning/matching (eATM) robot that can be attached to commercial and/or home-built magic angle spinning (MAS) or static nuclear magnetic resonance (NMR) probeheads. Complete synchronization and automation with Bruker and Tecmag spectrometers is ensured via transistor-transistor-logic (TTL) signals. The eATM robot enables an automated "on-the-fly" re-calibration of the radio frequency (rf) carrier frequency, which is beneficial whenever tuning/matching of the resonance circuit is required, e.g. variable temperature (VT) NMR, spin-echo mapping (variable offset cumulative spectroscopy, VOCS) and/or in situ NMR experiments of batteries. This allows a significant increase in efficiency for NMR experiments outside regular working hours (e.g. overnight) and, furthermore, enables measurements of quadrupolar nuclei which would not be possible in reasonable timeframes due to excessively large spectral widths. Additionally, different tuning/matching capacitor (and/or coil) settings for desired frequencies (e.g. 7 Li and 31 P at 117 and 122MHz, respectively, at 7.05 T) can be saved and made directly accessible before automatic tuning/matching, thus enabling automated measurements of multiple nuclei for one sample with no manual adjustment required by the user. We have applied this new eATM approach in static and MAS spin-echo mapping NMR experiments in different magnetic fields on four energy storage materials, namely: (1) paramagnetic 7 Li and 31 P MAS NMR (without manual recalibration) of the Li-ion battery cathode material LiFePO 4 ; (2) paramagnetic 17 O VT-NMR of the solid oxide fuel cell cathode material La 2 NiO 4+δ ; (3) broadband 93 Nb static NMR of the Li-ion battery material BNb 2 O 5 ; and (4) broadband static 127 I NMR of a potential Li-air battery product LiIO 3 . In each case, insight into local atomic structure and dynamics arises primarily from the highly broadened (1-25MHz) NMR lineshapes that the eATM robot is uniquely suited to collect. These new developments in automation of NMR experiments are likely to advance the application of in and ex situ NMR investigations to an ever-increasing range of energy storage materials and systems. Copyright © 2016 The Authors. Published by Elsevier Inc. All rights reserved.

Enhanced efficiency of solid-state NMR investigations of energy materials using an external automatic tuning/matching (eATM) robot

NASA Astrophysics Data System (ADS)

Pecher, Oliver; Halat, David M.; Lee, Jeongjae; Liu, Zigeng; Griffith, Kent J.; Braun, Marco; Grey, Clare P.

2017-02-01

We have developed and explored an external automatic tuning/matching (eATM) robot that can be attached to commercial and/or home-built magic angle spinning (MAS) or static nuclear magnetic resonance (NMR) probeheads. Complete synchronization and automation with Bruker and Tecmag spectrometers is ensured via transistor-transistor-logic (TTL) signals. The eATM robot enables an automated "on-the-fly" re-calibration of the radio frequency (rf) carrier frequency, which is beneficial whenever tuning/matching of the resonance circuit is required, e.g. variable temperature (VT) NMR, spin-echo mapping (variable offset cumulative spectroscopy, VOCS) and/or in situ NMR experiments of batteries. This allows a significant increase in efficiency for NMR experiments outside regular working hours (e.g. overnight) and, furthermore, enables measurements of quadrupolar nuclei which would not be possible in reasonable timeframes due to excessively large spectral widths. Additionally, different tuning/matching capacitor (and/or coil) settings for desired frequencies (e.g.7Li and 31P at 117 and 122 MHz, respectively, at 7.05 T) can be saved and made directly accessible before automatic tuning/matching, thus enabling automated measurements of multiple nuclei for one sample with no manual adjustment required by the user. We have applied this new eATM approach in static and MAS spin-echo mapping NMR experiments in different magnetic fields on four energy storage materials, namely: (1) paramagnetic 7Li and 31P MAS NMR (without manual recalibration) of the Li-ion battery cathode material LiFePO4; (2) paramagnetic 17O VT-NMR of the solid oxide fuel cell cathode material La2NiO4+δ; (3) broadband 93Nb static NMR of the Li-ion battery material BNb2O5; and (4) broadband static 127I NMR of a potential Li-air battery product LiIO3. In each case, insight into local atomic structure and dynamics arises primarily from the highly broadened (1-25 MHz) NMR lineshapes that the eATM robot is uniquely suited to collect. These new developments in automation of NMR experiments are likely to advance the application of in and ex situ NMR investigations to an ever-increasing range of energy storage materials and systems.

System Noise Prediction of the DGEN 380 Turbofan Engine

NASA Technical Reports Server (NTRS)

Berton, Jeffrey J.

2015-01-01

The DGEN 380 is a small, separate-flow, geared turbofan. Its manufacturer, Price Induction, is promoting it for a small twinjet application in the emerging personal light jet market. Smaller, and producing less thrust than other entries in the industry, Price Induction is seeking to apply the engine to a 4- to 5-place twinjet designed to compete in an area currently dominated by propeller-driven airplanes. NASA is considering purchasing a DGEN 380 turbofan to test new propulsion noise reduction technologies in a relevant engine environment. To explore this possibility, NASA and Price Induction have signed a Space Act Agreement and have agreed to cooperate on engine acoustic testing. Static acoustic measurements of the engine were made by NASA researchers during July, 2014 at the Glenn Research Center. In the event that a DGEN turbofan becomes a NASA noise technology research testbed, it is in the interest of NASA to develop procedures to evaluate engine system noise metrics. This report documents the procedures used to project the DGEN static noise measurements to flight conditions and the prediction of system noise of a notional airplane powered by twin DGEN engines.

Investigation on magnetoacoustic signal generation with magnetic induction and its application to electrical conductivity reconstruction.

PubMed

Ma, Qingyu; He, Bin

2007-08-21

A theoretical study on the magnetoacoustic signal generation with magnetic induction and its applications to electrical conductivity reconstruction is conducted. An object with a concentric cylindrical geometry is located in a static magnetic field and a pulsed magnetic field. Driven by Lorentz force generated by the static magnetic field, the magnetically induced eddy current produces acoustic vibration and the propagated sound wave is received by a transducer around the object to reconstruct the corresponding electrical conductivity distribution of the object. A theory on the magnetoacoustic waveform generation for a circular symmetric model is provided as a forward problem. The explicit formulae and quantitative algorithm for the electrical conductivity reconstruction are then presented as an inverse problem. Computer simulations were conducted to test the proposed theory and assess the performance of the inverse algorithms for a multi-layer cylindrical model. The present simulation results confirm the validity of the proposed theory and suggest the feasibility of reconstructing electrical conductivity distribution based on the proposed theory on the magnetoacoustic signal generation with magnetic induction.

Potassium conductance dynamics confer robust spike-time precision in a neuromorphic model of the auditory brain stem

PubMed Central

Boahen, Kwabena

2013-01-01

A fundamental question in neuroscience is how neurons perform precise operations despite inherent variability. This question also applies to neuromorphic engineering, where low-power microchips emulate the brain using large populations of diverse silicon neurons. Biological neurons in the auditory pathway display precise spike timing, critical for sound localization and interpretation of complex waveforms such as speech, even though they are a heterogeneous population. Silicon neurons are also heterogeneous, due to a key design constraint in neuromorphic engineering: smaller transistors offer lower power consumption and more neurons per unit area of silicon, but also more variability between transistors and thus between silicon neurons. Utilizing this variability in a neuromorphic model of the auditory brain stem with 1,080 silicon neurons, we found that a low-voltage-activated potassium conductance (gKL) enables precise spike timing via two mechanisms: statically reducing the resting membrane time constant and dynamically suppressing late synaptic inputs. The relative contribution of these two mechanisms is unknown because blocking gKL in vitro eliminates dynamic adaptation but also lengthens the membrane time constant. We replaced gKL with a static leak in silico to recover the short membrane time constant and found that silicon neurons could mimic the spike-time precision of their biological counterparts, but only over a narrow range of stimulus intensities and biophysical parameters. The dynamics of gKL were required for precise spike timing robust to stimulus variation across a heterogeneous population of silicon neurons, thus explaining how neural and neuromorphic systems may perform precise operations despite inherent variability. PMID:23554436

Brain Tumor Hyperthermia with Static and Moving Seeds

NASA Astrophysics Data System (ADS)

Molloy, Janelle Arlene

1990-01-01

Thermodynamic studies are presented for both static and moving ferromagnetic "seeds" imbedded in biological media. These studies were performed in support of the development of a system which delivers localized hyperthermia to deep-seated brain tumors. In this system, a magnetic "seed" of approximately 5 mm dimension (length and diameter) is remotely repositioned within the brain by an externally produced magnetic field. The seed is inductively heated and repositioned throughout the tumor volume. An induction heating system was built for experimental use with tissue phantoms and animals. The maximum level of direct tissue heating produced by this system was measured in vivo in three animals. An upper limit on the power absorption was placed at 0.46 mW cm^{ -3}, a factor of 10^{-4 } below the power density produced in ferromagnetic seeds by the same system. Measurements were made of the temporal and spatial dependence of the temperature rise in the vicinity of a statically placed 6 mm diameter nickel sphere, in vivo in four pigs, and in one which was euthanized. These results were compared to a theroetical model which was based on a point source solution to the thermal diffusion equation and estimates of blood flow rates, tissue thermal conductivity and seed power absorption were found using a parameter estimation algorithm. Studies were also made of the temperature gradients produced by a heated iron ellipsoid of 4.8 mm diameter and 9.6 mm length in a brain tissue phantom. Temperature measurements were made both with the seed statically imbedded in the tissue phantom and with the phantom moving at a constant velocity of 0.11 mm s^{-1 } with respect to the seed. These static and moving data were compared to obtain an estimate for the thermal field and convective cooling of a moving seed. In addition, an exploratory study was performed in which the dependence of seed heating efficiency on material and geometry were tested. A "hybrid" seed was developed consisting of a permanent magnet core surrounded by a non -magnetic spacing material and a 0.5 mm thick ferromagnetic outer sleeve. This seed was designed to accommodate potentially conflicting magnetic force and induction heating requirements.

Evaluation of two inflow control devices for flight simulation of fan noise using a JT15D engine

NASA Technical Reports Server (NTRS)

Jones, W. L.; Mcardle, J. G.; Homyak, L.

1979-01-01

The program was developed to accurately simulate flight fan noise on ground static test stands. The results generally indicated that both the induct and external ICD's were effective in reducing the inflow turbulence and the fan blade passing frequency tone generated by the turbulence. The external ICD was essentially transparent to the propagating fan tone but the induct ICD caused attenuation under most conditions.

The ac propulsion system for an electric vehicle, phase 1

NASA Astrophysics Data System (ADS)

Geppert, S.

1981-08-01

A functional prototype of an electric vehicle ac propulsion system was built consisting of a 18.65 kW rated ac induction traction motor, pulse width modulated (PWM) transistorized inverter, two speed mechanically shifted automatic transmission, and an overall drive/vehicle controller. Design developmental steps, and test results of individual components and the complex system on an instrumented test frame are described. Computer models were developed for the inverter, motor and a representative vehicle. A preliminary reliability model and failure modes effects analysis are given.

The ac propulsion system for an electric vehicle, phase 1

NASA Technical Reports Server (NTRS)

Geppert, S.

1981-01-01

A functional prototype of an electric vehicle ac propulsion system was built consisting of a 18.65 kW rated ac induction traction motor, pulse width modulated (PWM) transistorized inverter, two speed mechanically shifted automatic transmission, and an overall drive/vehicle controller. Design developmental steps, and test results of individual components and the complex system on an instrumented test frame are described. Computer models were developed for the inverter, motor and a representative vehicle. A preliminary reliability model and failure modes effects analysis are given.

Firefighters' Radios

NASA Technical Reports Server (NTRS)

1976-01-01

Public Technology Inc. asked for NASA assistance to devise the original firefighter's radio. Good short-range radio communications are essential during a fire to coordinate hose lines, rescue victims, and otherwise increase efficiency. Useful firefighting tool is lower cost, more rugged short range two-way radio. Inductorless electronic circuit replaced inductances and coils in radio circuits with combination of transistors and other low-cost components. Substitution promises reduced circuit size and cost. Enhanced electrical performance made radio more durable and improved maintainability by incorporating modular construction.

Black Phosphorus-Zinc Oxide Nanomaterial Heterojunction for p-n Diode and Junction Field-Effect Transistor.

PubMed

Jeon, Pyo Jin; Lee, Young Tack; Lim, June Yeong; Kim, Jin Sung; Hwang, Do Kyung; Im, Seongil

2016-02-10

Black phosphorus (BP) nanosheet is two-dimensional (2D) semiconductor with distinct band gap and attracting recent attention from researches because it has some similarity to gapless 2D semiconductor graphene in the following two aspects: single element (P) for its composition and quite high mobilities depending on its fabrication conditions. Apart from several electronic applications reported with BP nanosheet, here we report for the first time BP nanosheet-ZnO nanowire 2D-1D heterojunction applications for p-n diodes and BP-gated junction field effect transistors (JFETs) with n-ZnO channel on glass. For these nanodevices, we take advantages of the mechanical flexibility of p-type conducting of BP and van der Waals junction interface between BP and ZnO. As a result, our BP-ZnO nanodimension p-n diode displays a high ON/OFF ratio of ∼10(4) in static rectification and shows kilohertz dynamic rectification as well while ZnO nanowire channel JFET operations are nicely demonstrated by BP gate switching in both electrostatics and kilohertz dynamics.

Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics

NASA Astrophysics Data System (ADS)

Knoll, L.; Richter, S.; Nichau, A.; Trellenkamp, S.; Schäfer, A.; Wirths, S.; Blaeser, S.; Buca, D.; Bourdelle, K. K.; Zhao, Q.-T.; Mantl, S.

2014-08-01

Electrical characteristics of silicon nanowire tunnel field effect transistors (TFETs) are presented and benchmarked versus other concepts. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the functional core of the device. Dopant segregation from ion implanted ultrathin silicide contacts is proved as a viable method to achieve steep tunneling junctions. This reduces defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method is applied to strained silicon, specifically to nanowire array transistors, enabling the realization of n-type and p-type TFETs with fairly high currents and complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Gate-all-around Si nanowire array p-type TFETs have been fabricated to demonstrate the impact of electrostatic control on the device performance. A high on-current of 78 μA/μm at VD = VG = 1.1 V is obtained.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

PubMed

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

An organic water-gated ambipolar transistor with a bulk heterojunction active layer for stable and tunable photodetection

NASA Astrophysics Data System (ADS)

Xu, Haihua; Zhu, Qingqing; Wu, Tongyuan; Chen, Wenwen; Zhou, Guodong; Li, Jun; Zhang, Huisheng; Zhao, Ni

2016-11-01

Organic water-gated transistors (OWGTs) have emerged as promising sensing architectures for biomedical applications and environmental monitoring due to their ability of in-situ detection of biological substances with high sensitivity and low operation voltage, as well as compatibility with various read-out circuits. Tremendous progress has been made in the development of p-type OWGTs. However, achieving stable n-type operation in OWGTs due to the presence of solvated oxygen in water is still challenging. Here, we report an ambipolar OWGT based on a bulk heterojunction active layer, which exhibits a stable hole and electron transport when exposed to aqueous environment. The device can be used as a photodetector both in the hole and electron accumulation regions to yield a maximum responsivity of 0.87 A W-1. More importantly, the device exhibited stable static and dynamic photodetection even when operated in the n-type mode. These findings bring possibilities for the device to be adopted for future biosensing platforms, which are fully compatible with low-cost and low-power organic complementary circuits.

A high voltage dielectrically isolated smart power technology based on silicon direct bonding

NASA Astrophysics Data System (ADS)

Macary, Veronique

1992-09-01

The feasibility of a dielectrically isolated technology based on the silicon direct bonding technique, for high voltage smart power applications in the 1000 to 1550 V/1 to 20 A range, where a vertical power switch is necessary, is investigated and demonstrated. Static and dynamic isolation of the low voltage circuitry integrated beside the vertical power transistor is the main concern of this family of circuits. The dielectric isolation offers better protection to the low voltage part than does the junction isolation, because of the elimination of the parasitic bipolar transistor inherent to the latter isolation technique. Silicon direct bonding provides a cost effective way to obtain a buried oxide isolation layer. In addition, the application requires a Si/Si bonded area in the active region of the vertical power switch. Strong influence of the prebonding cleaning in the electrical characteristics of the Si/Si interface is pointed out, and presence of crystalline defects is assumed to be at the origin of electrical failures. The main problems of silicon direct bonding process compatibility with standard processes were overcome, and a complete process flow, including the simultaneous integration of a vertical power bipolar transistor together with a bipolar control circuitry, was validated. Using a peripheral biased ring is shown to provide an easy way to optimize high voltage termination for the smart power circuit, while adding a non-additional technological step. This technique was studied by dimensional electrical simulations (BIDIM2 software), as well as analytically computed.

Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits

NASA Astrophysics Data System (ADS)

Patil, Ganesh C.; Bonge, Vijaysinh H.; Malode, Mayur M.; Jain, Rahul G.

2016-02-01

In this paper, δ-doped partially insulated junctionless transistor (δ-Pi-OXJLT) has been proposed which shows that, employing highly doped δ-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed δ-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed δ-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed δ-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed δ-Pi-OXJLT clearly shows that the proposed δ-Pi-OXJLT is the promising device for mixed signal integrated circuits.

Identification of Malicious Web Pages by Inductive Learning

NASA Astrophysics Data System (ADS)

Liu, Peishun; Wang, Xuefang

Malicious web pages are an increasing threat to current computer systems in recent years. Traditional anti-virus techniques focus typically on detection of the static signatures of Malware and are ineffective against these new threats because they cannot deal with zero-day attacks. In this paper, a novel classification method for detecting malicious web pages is presented. This method is generalization and specialization of attack pattern based on inductive learning, which can be used for updating and expanding knowledge database. The attack pattern is established from an example and generalized by inductive learning, which can be used to detect unknown attacks whose behavior is similar to the example.

1.5-V-threshold-voltage Schottky barrier normally-off AlGaN/GaN high-electron-mobility transistors with f T/f max of 41/125 GHz

NASA Astrophysics Data System (ADS)

Hou, Bin; Ma, Xiaohua; Yang, Ling; Zhu, Jiejie; Zhu, Qing; Chen, Lixiang; Mi, Minhan; Zhang, Hengshuang; Zhang, Meng; Zhang, Peng; Zhou, Xiaowei; Hao, Yue

2017-07-01

In this paper, a normally-off AlGaN/GaN high-electron-mobility transistors (HEMT) fabricated using inductively coupled plasma (ICP) CF4 plasma recessing and an implantation technique is reported. A gate-to-channel distance of ˜10 nm and an equivalent negative fluorine sheet charge density of -1.21 × 1013 cm-2 extracted using a simple threshold voltage (V th) analytical model result in a high V th of 1.5 V, a peak transconductance of 356 mS/mm, and a subthreshold slope of 133 mV/decade. A small degradation of channel mobility leads to a high RF performance with f T/f max of 41/125 GHz, resulting in a record high f T × L g product of 10.66 GHz·µm among Schottky barrier AlGaN/GaN normally-off HEMTs with V th exceeding 1 V, to the best of our knowledge.

Carbon Nanotube Driver Circuit for 6 × 6 Organic Light Emitting Diode Display

PubMed Central

Zou, Jianping; Zhang, Kang; Li, Jingqi; Zhao, Yongbiao; Wang, Yilei; Pillai, Suresh Kumar Raman; Volkan Demir, Hilmi; Sun, Xiaowei; Chan-Park, Mary B.; Zhang, Qing

2015-01-01

Single-walled carbon nanotube (SWNT) is expected to be a very promising material for flexible and transparent driver circuits for active matrix organic light emitting diode (AM OLED) displays due to its high field-effect mobility, excellent current carrying capacity, optical transparency and mechanical flexibility. Although there have been several publications about SWNT driver circuits, none of them have shown static and dynamic images with the AM OLED displays. Here we report on the first successful chemical vapor deposition (CVD)-grown SWNT network thin film transistor (TFT) driver circuits for static and dynamic AM OLED displays with 6 × 6 pixels. The high device mobility of ~45 cm2V−1s−1 and the high channel current on/off ratio of ~105 of the SWNT-TFTs fully guarantee the control capability to the OLED pixels. Our results suggest that SWNT-TFTs are promising backplane building blocks for future OLED displays. PMID:26119218

Global electromagnetic induction in the moon and planets. [poloidal eddy current transient response

NASA Technical Reports Server (NTRS)

Dyal, P.; Parkin, C. W.

1973-01-01

Experiments and analyses concerning electromagnetic induction in the moon and other extraterrestrial bodies are summarized. The theory of classical electromagnetic induction in a sphere is first considered, and this treatment is extended to the case of the moon, where poloidal eddy-current response has been found experimentally to dominate other induction modes. Analysis of lunar poloidal induction yields lunar internal electrical conductivity and temperature profiles. Two poloidal-induction analytical techniques are discussed: a transient-response method applied to time-series magnetometer data, and a harmonic-analysis method applied to data numerically Fourier-transformed to the frequency domain, with emphasis on the former technique. Attention is given to complicating effects of the solar wind interaction with both induced poloidal fields and remanent steady fields. The static magnetization field induction mode is described, from which are calculated bulk magnetic permeability profiles. Magnetic field measurements obtained from the moon and from fly-bys of Venus and Mars are studied to determine the feasibility of extending theoretical and experimental induction techniques to other bodies in the solar system.

Lateral power MOSFETs in silicon carbide

NASA Astrophysics Data System (ADS)

Spitz, Jan

2001-07-01

Because of its large bandgap, its high critical electric field, and its high quality native SiO2, silicon carbide is considered to be the material of choice for power switching electronics in the future. Until 1997 the maximum thickness of commercially available epilayers serving as the drift region for power devices has been limited to 10--15 mum, limiting the maximum blocking voltage to 1500 V for vertical power devices in silicon carbide. In this study, we present the first lateral power devices on a semi-insulating vanadium doped substrate of silicon carbide. The first generation of lateral DMOSFETs in 4H-SiC yielded a blocking voltage of 2.6 kV---more than twice what was previously reported for any SiC MOSFETs---but suffered from low MOS channel mobility caused by the high anneal temperatures (≥1600°C) required to activate the p-type ion-implant. Combining the high blocking-voltage of the vanadium-doped substrate with the higher MOS mobility previously achieved by an epitaxially-grown accumulation channel leads us to the LACCUFET device: No p-type implant is necessary. This device shows a blocking voltage of 2.7 kV unmatched by any SiC transistor until February 2000 combined with a much lower specific on-resistance of 3.6 O•cm2. The ability to combine long-channel test MOSFETs with high channel mobility of 27 cm2/(volt·sec) in 4H-SiC with power devices of 13 cm2/(volt·sec) on the same chip has been demonstrated. The Figure of Merit Vblock 2/Ron,sp for this new NON-RESURF LDMOSFET in 4H-SiC is close to the theoretical limit for vertical power devices made of silicon. The specific on-resistance can be reduced by factor 2.5 by forward-biasing the p-base to source junction by 2 to 3 volts. Basic operation in Static Induction Injection Accumulation FET (SIAFET) mode has been demonstrated. Lateral (Non-Punch-Through) Insulated Gate Bipolar Transistors (LIGBT) have been presented for the first time showing similar on-resistance and blocking voltages but significantly higher on-currents for both 4H and 6H-SiC devices compared to their MOSFET counterparts. Test p-i-n diodes show lower on-resistance by carrier injection into the drift region.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Manipulation of electron transport in graphene by nanopatterned electrostatic potential on an electret

NASA Astrophysics Data System (ADS)

Wang, Xiaowei; Wang, Rui; Wang, Shengnan; Zhang, Dongdong; Jiang, Xingbin; Cheng, Zhihai; Qiu, Xiaohui

2018-01-01

The electron transport characteristics of graphene can be finely tuned using local electrostatic fields. Here, we use a scanning probe technique to construct a statically charged electret gate that enables in-situ fabrication of graphene devices with precisely designed potential landscapes, including p-type and n-type unipolar graphene transistors and p-n junctions. Electron dynamic simulation suggests that electron beam collimation and focusing in graphene can be achieved via periodic charge lines and concentric charge circles. This approach to spatially manipulating carrier density distribution may offer an efficient way to investigate the novel electronic properties of graphene and other low-dimensional materials.

A Comparative Study of the Gas Sensing Behavior in P3HT- and PBTTT-Based OTFTs: The Influence of Film Morphology and Contact Electrode Position

PubMed Central

Manoli, Kyriaki; Dumitru, Liviu Mihai; Mulla, Mohammad Yusuf; Magliulo, Maria; Di Franco, Cinzia; Santacroce, Maria Vittoria; Scamarcio, Gaetano; Torsi, Luisa

2014-01-01

Bottom- and top-contact organic thin film transistors (OTFTs) were fabricated, using poly(3-hexylthiophene-2,5-diyl) (P3HT) and poly[2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene] (PBTTT-C16) as p-type channel semiconductors. Four different types of OTFTs were fabricated and investigated as gas sensors against three volatile organic compounds, with different associated dipole moments. The OTFT-based sensor responses were evaluated with static and transient current measurements. A comparison between the different architectures and the relative organic semiconductor was made. PMID:25215940

Effect of the mobility on (I-V) characteristics of the MOSFET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Benzaoui, Ouassila, E-mail: o-benzaoui@yahoo.fr; Azizi, Cherifa, E-mail: aziziche@yahoo.fr

2013-12-16

MOSFET Transistor was the subject of many studies and research works (electronics, data-processing, telecommunications...) in order to exploit its interesting and promising characteristics. The aim of this contribution is devoted to the effect of the mobility on the static characteristics I-V of the MOSFET. The study enables us to calculate the drain current as function of bias in both linear and saturated modes; this effect is evaluated using a numerical simulation program. The influence of mobility was studied. Obtained results allow us to determine the mobility law in the MOSFET which gives optimal (I-V) characteristics of the component.

PWM-switching pattern-based diagnosis scheme for single and multiple open-switch damages in VSI-fed induction motor drives.

PubMed

Trabelsi, Mohamed; Boussak, Mohamed; Gossa, Moncef

2012-03-01

This paper deals with a fault detection technique for insulated-gate bipolar transistors (IGBTs) open-circuit faults in voltage source inverter (VSI)-fed induction motor drives. The novelty of this idea consists in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. The proposed method requires line-to-line voltage measurement, which provides information about switching states and is not affected by the load. The fault diagnosis scheme is achieved using simple hardware and can be included in the existing inverter system without any difficulty. In addition, it allows not only accurate single and multiple faults diagnosis but also minimization of the fault detection time to a maximum of one switching period (T(c)). Simulated and experimental results on a 3-kW squirrel-cage induction motor drive are displayed to validate the feasibility and the effectiveness of the proposed strategy. Crown Copyright © 2011. Published by Elsevier Ltd. All rights reserved.

Piezoelectric response of a PZT thin film to magnetic fields from permanent magnet and coil combination

NASA Astrophysics Data System (ADS)

Guiffard, B.; Seveno, R.

2015-01-01

In this study, we report the magnetically induced electric field E 3 in Pb(Zr0.57Ti0.43)O3 (PZT) thin films, when they are subjected to both dynamic magnetic induction (magnitude B ac at 45 kHz) and static magnetic induction ( B dc) generated by a coil and a single permanent magnet, respectively. It is found that highest sensitivity to B dc——is achieved for the thin film with largest effective electrode. This magnetoelectric (ME) effect is interpreted in terms of coupling between eddy current-induced Lorentz forces (stress) in the electrodes of PZT and piezoelectricity. Such coupling was evidenced by convenient modelling of experimental variations of electric field magnitude with both B ac and B dc induction magnitudes, providing imperfect open circuit condition was considered. Phase angle of E 3 versus B dc could also be modelled. At last, the results show that similar to multilayered piezoelectric-magnetostrictive composite film, a PZT thin film made with a simple manufacturing process can behave as a static or dynamic magnetic field sensor. In this latter case, a large ME voltage coefficient of under B dc = 0.3 T was found. All these results may provide promising low-cost magnetic energy harvesting applications with microsized systems.

Is there a relationship between curvature and inductance in the Josephson junction?

NASA Astrophysics Data System (ADS)

Dobrowolski, T.; Jarmoliński, A.

2018-03-01

A Josephson junction is a device made of two superconducting electrodes separated by a very thin layer of isolator or normal metal. This relatively simple device has found a variety of technical applications in the form of Superconducting Quantum Interference Devices (SQUIDs) and Single Electron Transistors (SETs). One can expect that in the near future the Josephson junction will find applications in digital electronics technology RSFQ (Rapid Single Flux Quantum) and in the more distant future in construction of quantum computers. Here we concentrate on the relation of the curvature of the Josephson junction with its inductance. We apply a simple Capacitively Shunted Junction (CSJ) model in order to find condition which guarantees consistency of this model with prediction based on the Maxwell and London equations with Landau-Ginzburg current of Cooper pairs. This condition can find direct experimental verification.

Broadband pH-Sensing Organic Transistors with Polymeric Sensing Layers Featuring Liquid Crystal Microdomains Encapsulated by Di-Block Copolymer Chains.

PubMed

Seo, Jooyeok; Song, Myeonghun; Jeong, Jaehoon; Nam, Sungho; Heo, Inseok; Park, Soo-Young; Kang, Inn-Kyu; Lee, Joon-Hyung; Kim, Hwajeong; Kim, Youngkyoo

2016-09-14

We report broadband pH-sensing organic field-effect transistors (OFETs) with the polymer-dispersed liquid crystal (PDLC) sensing layers. The PDLC layers are prepared by spin-coating using ethanol solutions containing 4-cyano-4'-pentyl-biphenyl (5CB) and a diblock copolymer (PAA-b-PCBOA) that consists of LC-philic block [poly(4-cyano-biphenyl-4-oxyundecyl acrylate) (PCBOA)] and acrylic acid block [poly(acrylic acid) (PAA)]. The spin-coated sensing layers feature of 5CB microdomains (<5 μm) encapsulated by the PAA-b-PCBOA polymer chains. The resulting LC-integrated-OFETs (PDLC-i-OFETs) can detect precisely and reproducibly a wide range of pH with only small amounts (10-40 μL) of analyte solutions in both static and dynamic perfusion modes. The positive drain current change is measured for acidic solutions (pH < 7), whereas basic solutions (pH > 7) result in the negative change of drain current. The drain current trend in the present PDLC-i-OFET devices is explained by the shrinking-expanding mechanism of the PAA chains in the diblock copolymer layers.

A Direct Method to Extract Transient Sub-Gap Density of State (DOS) Based on Dual Gate Pulse Spectroscopy

NASA Astrophysics Data System (ADS)

Dai, Mingzhi; Khan, Karim; Zhang, Shengnan; Jiang, Kemin; Zhang, Xingye; Wang, Weiliang; Liang, Lingyan; Cao, Hongtao; Wang, Pengjun; Wang, Peng; Miao, Lijing; Qin, Haiming; Jiang, Jun; Xue, Lixin; Chu, Junhao

2016-06-01

Sub-gap density of states (DOS) is a key parameter to impact the electrical characteristics of semiconductor materials-based transistors in integrated circuits. Previously, spectroscopy methodologies for DOS extractions include the static methods, temperature dependent spectroscopy and photonic spectroscopy. However, they might involve lots of assumptions, calculations, temperature or optical impacts into the intrinsic distribution of DOS along the bandgap of the materials. A direct and simpler method is developed to extract the DOS distribution from amorphous oxide-based thin-film transistors (TFTs) based on Dual gate pulse spectroscopy (GPS), introducing less extrinsic factors such as temperature and laborious numerical mathematical analysis than conventional methods. From this direct measurement, the sub-gap DOS distribution shows a peak value on the band-gap edge and in the order of 1017-1021/(cm3·eV), which is consistent with the previous results. The results could be described with the model involving both Gaussian and exponential components. This tool is useful as a diagnostics for the electrical properties of oxide materials and this study will benefit their modeling and improvement of the electrical properties and thus broaden their applications.

Wafer-scalable high-performance CVD graphene devices and analog circuits

NASA Astrophysics Data System (ADS)

Tao, Li; Lee, Jongho; Li, Huifeng; Piner, Richard; Ruoff, Rodney; Akinwande, Deji

2013-03-01

Graphene field effect transistors (GFETs) will serve as an essential component for functional modules like amplifier and frequency doublers in analog circuits. The performance of these modules is directly related to the mobility of charge carriers in GFETs, which per this study has been greatly improved. Low-field electrostatic measurements show field mobility values up to 12k cm2/Vs at ambient conditions with our newly developed scalable CVD graphene. For both hole and electron transport, fabricated GFETs offer substantial amplification for small and large signals at quasi-static frequencies limited only by external capacitances at high-frequencies. GFETs biased at the peak transconductance point featured high small-signal gain with eventual output power compression similar to conventional transistor amplifiers. GFETs operating around the Dirac voltage afforded positive conversion gain for the first time, to our knowledge, in experimental graphene frequency doublers. This work suggests a realistic prospect for high performance linear and non-linear analog circuits based on the unique electron-hole symmetry and fast transport now accessible in wafer-scalable CVD graphene. *Support from NSF CAREER award (ECCS-1150034) and the W. M. Keck Foundation are appreicated.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

The effects of vestibular stimulation and fatigue on postural control in classical ballet dancers.

PubMed

Hopper, Diana M; Grisbrook, Tiffany L; Newnham, Prudence J; Edwards, Dylan J

2014-01-01

This study aimed to investigate the effects of ballet-specific vestibular stimulation and fatigue on static postural control in ballet dancers and to establish whether these effects differ across varying levels of ballet training. Dancers were divided into three groups: professional, pre-professional, and recreational. Static postural control of 23 dancers was measured on a force platform at baseline and then immediately, 30 seconds, and 60 seconds after vestibular stimulation (pirouettes) and induction of fatigue (repetitive jumps). The professional dancers' balance was unaffected by both the vestibular stimulation and the fatigue task. The pre-professional and recreational dancers' static sway increased following both perturbations. It is concluded that professional dancers are able to compensate for vestibular and fatiguing perturbations due to a higher level of skill-specific motor training.

Design of single-winding energy-storage reactors for dc-to-dc converters using air-gapped magnetic-core structures

NASA Technical Reports Server (NTRS)

Ohri, A. K.; Wilson, T. G.; Owen, H. A., Jr.

1977-01-01

A procedure is presented for designing air-gapped energy-storage reactors for nine different dc-to-dc converters resulting from combinations of three single-winding power stages for voltage stepup, current stepup and voltage stepup/current stepup and three controllers with control laws that impose constant-frequency, constant transistor on-time and constant transistor off-time operation. The analysis, based on the energy-transfer requirement of the reactor, leads to a simple relationship for the required minimum volume of the air gap. Determination of this minimum air gap volume then permits the selection of either an air gap or a cross-sectional core area. Having picked one parameter, the minimum value of the other immediately leads to selection of the physical magnetic structure. Other analytically derived equations are used to obtain values for the required turns, the inductance, and the maximum rms winding current. The design procedure is applicable to a wide range of magnetic material characteristics and physical configurations for the air-gapped magnetic structure.

Fabrication of high-performance InGaZnOx thin film transistors based on control of oxidation using a low-temperature plasma

NASA Astrophysics Data System (ADS)

Takenaka, Kosuke; Endo, Masashi; Uchida, Giichiro; Setsuhara, Yuichi

2018-04-01

This work demonstrated the low-temperature control of the oxidation of Amorphous InGaZnOx (a-IGZO) films using inductively coupled plasma as a means of precisely tuning the properties of thin film transistors (TFTs) and as an alternative to post-deposition annealing at high temperatures. The effects of the plasma treatment of the as-deposited a-IGZO films were investigated by assessing the electrical properties of TFTs incorporating these films. A TFT fabricated using an a-IGZO film exposed to an Ar-H2-O2 plasma at substrate temperatures as low as 300 °C exhibited the best performance, with a field effect mobility as high as 42.2 cm2 V-1 s-1, a subthreshold gate voltage swing of 1.2 V decade-1, and a threshold voltage of 2.8 V. The improved transfer characteristics of TFTs fabricated with a-IGZO thin films treated using an Ar-H2-O2 plasma are attributed to the termination of oxygen vacancies around Ga and Zn atoms by OH radicals in the gas phase.

Formation of low resistance ohmic contacts in GaN-based high electron mobility transistors with BCl3 surface plasma treatment

NASA Astrophysics Data System (ADS)

Fujishima, Tatsuya; Joglekar, Sameer; Piedra, Daniel; Lee, Hyung-Seok; Zhang, Yuhao; Uedono, Akira; Palacios, Tomás

2013-08-01

A BCl3 surface plasma treatment technique to reduce the resistance and to increase the uniformity of ohmic contacts in AlGaN/GaN high electron mobility transistors with a GaN cap layer has been established. This BCl3 plasma treatment was performed by an inductively coupled plasma reactive ion etching system under conditions that prevented any recess etching. The average contact resistances without plasma treatment, with SiCl4, and with BCl3 plasma treatment were 0.34, 0.41, and 0.17 Ω mm, respectively. Also, the standard deviation of the ohmic contact resistance with BCl3 plasma treatment was decreased. This decrease in the standard deviation of contact resistance can be explained by analyzing the surface condition of GaN with x-ray photoelectron spectroscopy and positron annihilation spectroscopy. We found that the proposed BCl3 plasma treatment technique can not only remove surface oxide but also introduce surface donor states that contribute to lower the ohmic contact resistance.

Circuit analysis on the inductance evolution based on electrical signal from various type plasma focus device

NASA Astrophysics Data System (ADS)

Mohamad, Saiful Najmee; Ismail, Fairuz Diana; Noorden, Ahmad Fakhrurrazi Ahmad; Haider, Zuhaib; Ali, Jalil

2017-03-01

Numerous configurations of plasma focus devices (PFD) have been introduced around the globe. The distinct electrode configuration of the PFD will give out different inductance profile. A circuit analysis has been done to study on the significant difference between the inductance evolution in a coaxial discharge based on various published results of PFD. The discharge current signal, tube voltage and current derivative of the particular shots from distinct PFD was digitized and analyze. The investigation was piloted for three different types of PFD. It was observed that there is a significant difference for the normalize inductance profile during the discharge between the individual PFD with different electrode configuration. The depletion of the radial start current with the normalised inductance development for Mather type (PF-1000) is found to be 25.9% from static discharge. The current depletion continues to drop 1.1% and 1.3% more for a Spherical type (PNK-13) and Filippov type (PF-3) respectively.

Zero-static power radio-frequency switches based on MoS2 atomristors.

PubMed

Kim, Myungsoo; Ge, Ruijing; Wu, Xiaohan; Lan, Xing; Tice, Jesse; Lee, Jack C; Akinwande, Deji

2018-06-28

Recently, non-volatile resistance switching or memristor (equivalently, atomristor in atomic layers) effect was discovered in transitional metal dichalcogenides (TMD) vertical devices. Owing to the monolayer-thin transport and high crystalline quality, ON-state resistances below 10 Ω are achievable, making MoS 2 atomristors suitable as energy-efficient radio-frequency (RF) switches. MoS 2 RF switches afford zero-hold voltage, hence, zero-static power dissipation, overcoming the limitation of transistor and mechanical switches. Furthermore, MoS 2 switches are fully electronic and can be integrated on arbitrary substrates unlike phase-change RF switches. High-frequency results reveal that a key figure of merit, the cutoff frequency (f c ), is about 10 THz for sub-μm 2 switches with favorable scaling that can afford f c above 100 THz for nanoscale devices, exceeding the performance of contemporary switches that suffer from an area-invariant scaling. These results indicate a new electronic application of TMDs as non-volatile switches for communication platforms, including mobile systems, low-power internet-of-things, and THz beam steering.

Cotton defense induction patterns under spatially, temporally and quantitatively varying herbivory levels

USDA-ARS?s Scientific Manuscript database

The optimal defense theory (ODT) predicts that plants allocate defense compounds to their tissues depending on its value and the likelihood of herbivore attack. Whereas ODT has been confirmed for static damage levels it remains poorly understood if ODT holds true for defense organization of inducibl...

Flat-roof phenomenon of dynamic equilibrium phase in the negative bias temperature instability effect on a power MOSFET

NASA Astrophysics Data System (ADS)

Zhang, Yue; Zhuo, Qing-Qing; Liu, Hong-Xia; Ma, Xiao-Hua; Hao, Yue

2014-05-01

The effect of the static negative bias temperature (NBT) stress on a p-channel power metal—oxide—semiconductor field-effect transistor (MOSFET) is investigated by experiment and simulation. The time evolution of the negative bias temperature instability (NBTI) degradation has the trend predicted by the reaction—diffusion (R—D) model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R—D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.

Predicting performance of power converters operating with switching frequencies in the vicinity of 100 kHZ

NASA Technical Reports Server (NTRS)

Bahler, D. D.; Owen, H. A., Jr.; Wilson, T. G.

1978-01-01

A model describing the turning-on period of a power switching transistor in an energy storage voltage step-up converter is presented. Comparisons between an experimental layout and the circuit model during the turning-on interval demonstrate the ability of the model to closely predict the effects of circuit topology on the performance of the converter. A phenomenon of particular importance that is observed in the experimental circuits and is predicted by the model is the deleterious feedback effect of the parasitic emitter lead inductance on the base current waveform during the turning-on interval.

Method and apparatus for controlling current in inductive loads such as large diameter coils

DOEpatents

Riveros, Carlos A.

1981-01-01

A method and apparatus for controlling electric current in loads that are essentially inductive, such that sparking and "ringing" current problems are reduced or eliminated. The circuit apparatus employs a pair of solid state switches (each of which switch may be an array of connected or parallel solid state switching devices such as transistors) and means for controlling those switches such that a power supply supplying two d.c. voltages (e.g. positive 150 volts d.c. and negative 150 volts d.c.) at low resistance may be connected across an essentially inductive load (e.g. a 6 gauge wire loop one hundred meters in diameter) alternatively and such that the first solid state switch is turned off and the second is turned on such that both are not on at the same time but the first turned on and the other on in less time than the inductive time constant (L/R) so that the load is essentially always presented with a low resistance path across its input. In this manner a steady AC current may be delivered to the load at a frequency desired. Shut-off problems are avoided by gradually shortening the period of switching to less than the time constant so that the maximum energy contained in the inductive load is reduced to approximately zero and dissipated in the inherent resistance. The invention circuit may be employed by adjusting the timing of switching to deliver a desired waveform (such as sinusoidal) to the load.

An exposure-response analysis based on rifampin suggests CYP3A4 induction is driven by AUC: an in vitro investigation.

PubMed

Chang, Cheng; Yang, Xin; Fahmi, Odette A; Riccardi, Keith A; Di, Li; Obach, R Scott

2017-08-01

1. Induction is an important mechanism contributing to drug-drug interactions. It is most commonly evaluated in the human hepatocyte assay over 48-h or 72-h incubation period. However, whether the overall exposure (i.e. Area Under the Curve (AUC) or C ave ) or maximum exposure (i.e. C max ) of the inducer is responsible for the magnitude of subsequent induction has not been thoroughly investigated. Additionally, in vitro induction assays are typically treated as static systems, which could lead to inaccurate induction potency estimation. Hence, European Medicines Agency (EMA) guidance now specifies quantitation of drug levels in the incubation. 2. This work treated the typical in vitro evaluation of rifampin induction as an in vivo system by generating various target engagement profiles, measuring free rifampin concentration over 3 d of incubation and evaluating the impact of these factors on final induction response. 3. This rifampin-based analysis demonstrates that the induction process is driven by time-averaged target engagement (i.e. AUC-driven). Additionally, depletion of rifampin in the incubation medium over 3 d as well as non-specific/specific binding were observed. 4. These findings should help aid the discovery of clinical candidates with minimal induction liability and further expand our knowledge in the quantitative translatability of in vitro induction assays.

Magnetoacoustic tomography with magnetic induction for high-resolution bioimepedance imaging through vector source reconstruction under the static field of MRI magnet.

PubMed

Mariappan, Leo; Hu, Gang; He, Bin

2014-02-01

Magnetoacoustic tomography with magnetic induction (MAT-MI) is an imaging modality to reconstruct the electrical conductivity of biological tissue based on the acoustic measurements of Lorentz force induced tissue vibration. This study presents the feasibility of the authors' new MAT-MI system and vector source imaging algorithm to perform a complete reconstruction of the conductivity distribution of real biological tissues with ultrasound spatial resolution. In the present study, using ultrasound beamformation, imaging point spread functions are designed to reconstruct the induced vector source in the object which is used to estimate the object conductivity distribution. Both numerical studies and phantom experiments are performed to demonstrate the merits of the proposed method. Also, through the numerical simulations, the full width half maximum of the imaging point spread function is calculated to estimate of the spatial resolution. The tissue phantom experiments are performed with a MAT-MI imaging system in the static field of a 9.4 T magnetic resonance imaging magnet. The image reconstruction through vector beamformation in the numerical and experimental studies gives a reliable estimate of the conductivity distribution in the object with a ∼ 1.5 mm spatial resolution corresponding to the imaging system frequency of 500 kHz ultrasound. In addition, the experiment results suggest that MAT-MI under high static magnetic field environment is able to reconstruct images of tissue-mimicking gel phantoms and real tissue samples with reliable conductivity contrast. The results demonstrate that MAT-MI is able to image the electrical conductivity properties of biological tissues with better than 2 mm spatial resolution at 500 kHz, and the imaging with MAT-MI under a high static magnetic field environment is able to provide improved imaging contrast for biological tissue conductivity reconstruction.

Bianisotropic-critical-state model to study flux cutting in type-II superconductors at parallel geometry

NASA Astrophysics Data System (ADS)

Romero-Salazar, C.

2016-04-01

A critical-state model is postulated that incorporates, for the first time, the structural anisotropy and flux-line cutting effect in a type-II superconductor. The model is constructed starting from the theoretical scheme of Romero-Salazar and Pérez-Rodríguez to study the anisotropy induced by flux cutting. Here, numerical calculations of the magnetic induction and static magnetization are presented for samples under an alternating magnetic field, orthogonal to a static dc-bias one. The interplay of the two anisotropies is analysed by comparing the numerical results with available experimental data for an yttrium barium copper oxide (YBCO) plate, and a vanadium-titanium (VTi) strip, subjected to a slowly oscillating field {H}y({H}z) in the presence of a static field {H}z({H}y).

Three-dimensional joint inversion for magnetotelluric resistivity and static shift distributions in complex media

NASA Astrophysics Data System (ADS)

Sasaki, Yutaka; Meju, Max A.

2006-05-01

Accurate interpretation of magnetotelluric (MT) data in the presence of static shift arising from near-surface inhomogeneities is an unresolved problem in three-dimensional (3-D) inversion. While it is well known in 1-D and 2-D studies that static shift can lead to erroneous interpretation, how static shift can influence the result of 3-D inversion is not fully understood and is relevant to improved subsurface analysis. Using the synthetic data generated from 3-D models with randomly distributed heterogeneous overburden and elongate homogeneous overburden that are consistent with geological observations, this paper examines the effects of near-surface inhomogeneity on the accuracy of 3-D inversion models. It is found that small-scale and shallow depth structures are severely distorted while the large-scale structure is marginally distorted in 3-D inversion not accounting for static shift; thus the erroneous near-surface structure does degrade the reconstruction of smaller-scale structure at any depth. However, 3-D joint inversion for resistivity and static shift significantly reduces the artifacts caused by static shifts and improves the overall resolution, irrespective of whether a zero-sum or Gaussian distribution of static shifts is assumed. The 3-D joint inversion approach works equally well for situations where the shallow bodies are of small size or long enough to allow some induction such that the effects of near-surface inhomogeneity are manifested as a frequency-dependent shift rather than a constant shift.

High-Efficiency Microwave Power Amplifier

NASA Technical Reports Server (NTRS)

Sims, Williams H.

2005-01-01

A high-efficiency power amplifier that operates in the S band (frequencies of the order of a few gigahertz) utilizes transistors operating under class-D bias and excitation conditions. Class-D operation has been utilized at lower frequencies, but, until now, has not been exploited in the S band. Nominally, in class D operation, a transistor is switched rapidly between "on" and "off" states so that at any given instant, it sustains either high current or high voltage, but not both at the same time. In the ideal case of zero "on" resistance, infinite "off" resistance, zero inductance and capacitance, and perfect switching, the output signal would be a perfect square wave. Relative to the traditional classes A, B, and C of amplifier operation, class D offers the potential to achieve greater power efficiency. In addition, relative to class-A amplifiers, class-D amplifiers are less likely to go into oscillation. In order to design this amplifier, it was necessary to derive mathematical models of microwave power transistors for incorporation into a larger mathematical model for computational simulation of the operation of a class-D microwave amplifier. The design incorporates state-of-the-art switching techniques applicable only in the microwave frequency range. Another major novel feature is a transmission-line power splitter/combiner designed with the help of phasing techniques to enable an approximation of a square-wave signal (which is inherently a wideband signal) to propagate through what would, if designed in a more traditional manner, behave as a more severely band-limited device (see figure). The amplifier includes an input, a driver, and a final stage. Each stage contains a pair of GaAs-based field-effect transistors biased in class D. The input signal can range from -10 to +10 dBm into a 50-ohm load. The table summarizes the performances of the three stages

Effects of Cascaded Voltage Collapse and Protection of Many Induction Machine Loads upon Load Characteristics Viewed from Bulk Transmission System

NASA Astrophysics Data System (ADS)

Kumano, Teruhisa

As known well, two of the fundamental processes which give rise to voltage collapse in power systems are the on load tap changers of transformers and dynamic characteristics of loads such as induction machines. It has been well established that, comparing among these two, the former makes slower collapse while the latter makes faster. However, in realistic situations, the load level of each induction machine is not uniform and it is well expected that only a part of loads collapses first, followed by collapse process of each load which did not go into instability during the preceding collapses. In such situations the over all equivalent collapse behavior viewed from bulk transmission level becomes somewhat different from the simple collapse driven by one aggregated induction machine. This paper studies the process of cascaded voltage collapse among many induction machines by time simulation, where load distribution on a feeder line is modeled by several hundreds of induction machines and static impedance loads. It is shown that in some cases voltage collapse really cascades among induction machines, where the macroscopic load dynamics viewed from upper voltage level makes slower collapse than expected by the aggregated load model. Also shown is the effects of machine protection of induction machines, which also makes slower collapse.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

The voltage control for self-excited induction generator based on STATCOM

NASA Astrophysics Data System (ADS)

Yan, Dandan; Wang, Feifeng; Pan, Juntao; Long, Weijie

2018-05-01

The small independent induction generator can build up voltage under its remanent magnetizing and excitation capacitance, but it is prone to voltage sag and harmonic increment when running with load. Therefore, the controller for constant voltage is designed based on the natural coordinate system to adjust the static synchronous compensator (STATCOM), which provides two-way dynamic reactive power compensation for power generation system to achieve voltage stability and harmonic suppression. The control strategy is verified on Matlab/Sinmulik, and the results show that the STATCOM under the controller can effectively improve the load capacity and reliability of asynchronous generator.

FinFET memory cell improvements for higher immunity against single event upsets

NASA Astrophysics Data System (ADS)

Sajit, Ahmed Sattar

The 21st century is witnessing a tremendous demand for transistors. Life amenities have incorporated the transistor in every aspect of daily life, ranging from toys to rocket science. Day by day, scaling down the transistor is becoming an imperious necessity. However, it is not a straightforward process; instead, it faces overwhelming challenges. Due to these scaling changes, new technologies, such as FinFETs for example, have emerged as alternatives to the conventional bulk-CMOS technology. FinFET has more control over the channel, therefore, leakage current is reduced. FinFET could bridge the gap between silicon devices and non-silicon devices. The semiconductor industry is now incorporating FinFETs in systems and subsystems. For example, Intel has been using them in their newest processors, delivering potential saving powers and increased speeds to memory circuits. Memory sub-systems are considered a vital component in the digital era. In memory, few rows are read or written at a time, while the most rows are static; hence, reducing leakage current increases the performance. However, as a transistor shrinks, it becomes more vulnerable to the effects from radioactive particle strikes. If a particle hits a node in a memory cell, the content might flip; consequently, leading to corrupting stored data. Critical fields, such as medical and aerospace, where there are no second chances and cannot even afford to operate at 99.99% accuracy, has induced me to find a rigid circuit in a radiated working environment. This research focuses on a wide spectrum of memories such as 6T SRAM, 8T SRAM, and DICE memory cells using FinFET technology and finding the best platform in terms of Read and Write delay, susceptibility level of SNM, RSNM, leakage current, energy consumption, and Single Event Upsets (SEUs). This research has shown that the SEU tolerance that 6T and 8T FinFET SRAMs provide may not be acceptable in medical and aerospace applications where there is a very high likelihood of SEUs. Consequently, FinFET DICE memory can be a good candidate due to its high ability to tolerate SEUs of different amplitudes and long periods for both read and hold operations.

Study of G-S/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model

NASA Astrophysics Data System (ADS)

Maity, Subir Kumar; Pandit, Soumya

2017-01-01

InGaAs (and its variant) appears to be a promising channel material for high-performance, low-power scaled CMOS applications due to its excellent carrier transport properties. However, MOS transistors made of this suffer from poor electrostatic integrity. In this work, we consider an underlap ultra thin body (UTB) InAs-on-Insulator n-channel MOS transistor, and study the effect of varying the gate-source/drain (G-S/D) underlap length on the analog performance of the device with the help of technology computer-aided design (TCAD) simulation, calibrated with Schrodinger-Poisson solver and experimental results. The underlap technique improves the gate electrostatic integrity which in turn improves the analog performance. We develop a non-quasi-static (NQS) small signal equivalent circuit model of the device which is used for study of the RF performance. With increase of the underlap length, the unity gain cut-off frequency degrades and the maximum oscillation frequency improves beyond a certain value of the underlap length. We further study the gain-frequency response of a common source amplifier using the NQS model, through SPICE simulation and observe that the voltage gain and the gain bandwidth improves.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Analysis and design of negative resistance oscillators using surface transverse wave-based single port resonators.

PubMed

Avramov, Ivan D

2003-03-01

This practically oriented paper presents the fundamentals for analysis, optimization, and design of negative resistance oscillators (NRO) stabilized with surface transverse wave (STW)-based single-port resonators (SPR). Data on a variety of high-Q, low-loss SPR devices in the 900- to 2000-MHz range, suitable for NRO applications, are presented, and a simple method for SPR parameter extraction through Pi-circuit measurements is outlined. Negative resistance analysis, based on S-parameter data of the active device, is performed on a tuned-base, grounded collector transistor NRO, known for its good stability and tuning at microwave frequencies. By adding a SPR in the emitter network, the static transducer capacitance is absorbed by the circuit and is used to generate negative resistance only over the narrow bandwidth of the acoustic device, eliminating the risk of spurious oscillations. The analysis allows exact prediction of the oscillation frequency, tuning range, loaded Q, and excess gain. Simulation and experimental data on a 915-MHz fixed-frequency NRO and a wide tuning range, voltage-controlled STW oscillator, built and tested experimentally, are presented. Practical design aspects including the choice of transistor, negative feedback circuits, load coupling, and operation at the highest phase slope for minimum phase noise are discussed.

Piezoelectric coupling in a field-effect transistor with a nanohybrid channel of ZnO nanorods grown vertically on graphene.

PubMed

Quang Dang, Vinh; Kim, Do-Il; Thai Duy, Le; Kim, Bo-Yeong; Hwang, Byeong-Ung; Jang, Mi; Shin, Kyung-Sik; Kim, Sang-Woo; Lee, Nae-Eung

2014-12-21

Piezoelectric coupling phenomena in a graphene field-effect transistor (GFET) with a nano-hybrid channel of chemical-vapor-deposited Gr (CVD Gr) and vertically aligned ZnO nanorods (NRs) under mechanical pressurization were investigated. Transfer characteristics of the hybrid channel GFET clearly indicated that the piezoelectric effect of ZnO NRs under static or dynamic pressure modulated the channel conductivity (σ) and caused a positive shift of 0.25% per kPa in the Dirac point. However, the GFET without ZnO NRs showed no change in either σ or the Dirac point. Analysis of the Dirac point shifts indicated transfer of electrons from the CVD Gr to ZnO NRs due to modulation of their interfacial barrier height under pressure. High responsiveness of the hybrid channel device with fast response and recovery times was evident in the time-dependent behavior at a small gate bias. In addition, the hybrid channel FET could be gated by mechanical pressurization only. Therefore, a piezoelectric-coupled hybrid channel GFET can be used as a pressure-sensing device with low power consumption and a fast response time. Hybridization of piezoelectric 1D nanomaterials with a 2D semiconducting channel in FETs enables a new design for future nanodevices.

Electric Field Feature of Moving Magnetic Field

NASA Astrophysics Data System (ADS)

Chen, You Jun

2001-05-01

A new fundamental relationship of electric field with magnetic field has been inferred from the fundamental experimental laws and theories of classical electromagnetics. It can be described as moving magnetic field has or gives electric feature. When a field with magnetic induction of B moves in the velocity of V, it will show electric field character, the electric field intensity E is E = B x V and the direction of E is in the direction of the vector B x V. It is improper to use the time-varying electromagnetics theories as the fundamental theory of the electromagnetics and group the electromagnetic field into static kind and time-varying kind for the static is relative to motional not only time-varying. The relationship of time variation of magnetic field induction or magnetic flux with electric field caused by magnetic field is fellowship not causality. Thus time-varying magnetic field can cause electric field is not a nature principle. Sometime the time variation of magnetic flux is equal to the negative electromotive force or the time variation of magnetic field induction is equal to the negative curl of electric field caused by magnetic field motion, but not always. And not all motion of magnetic field can cause time variation of magnetic field. Therefore Faraday-Lenz`s law can only be used as mathematics tool to calculate the quantity relation of the electricity with the magnetism in some case like the magnetic field moving in uniform medium. Faraday-Lenz`s law is unsuitable to be used in moving uniform magnetic field or there is magnetic shield. Key word: Motional magnetic field, Magnetic induction, Electric field intensity, Velocity, Faraday-Lenz’s law

Enzymatic defenses against the toxicity of oxygen and of streptonigrin in Escherichia coli.

PubMed

Hassan, H M; Fridovich, I

1977-03-01

Anaerobically grown Escherichia coli K-12 contain only one superoxide dismutase and that is the iron-containing isozyme found in the periplasmic space. Exposure to oxygen caused the induction of a manganese-containing superoxide dismutase and of another, previously undescribed, superoxide dismutase, as well as of catalase and peroxidase. These inductions differed in their responsiveness towards oxygen. Thus the very low levels of oxygen present in deep, static, aerobic cultures were enough for nearly maximal induction of the manganese-superoxide dismutase. In contrast, induction of the new superoxide dismutase, catalase, and peroxidase required the much higher levels of oxygen achieved in vigorously agitated aerobic cultures. Anaerobically grown cells showed a much greater oxygen enhancement of the lethality of streptonigrin than did aerobically grown cells, in accord with the proposal that streptonigrin can serve as an intracellular source of superoxide. Anaerobically grown cells in which enzyme inductions were prevented by puromycin were damaged by exposure to air. This damage was evidenced both as a decline in viable cell count and as structural abnormalities evident under an electron microscope.

Dispersive Readout of a Superconducting Flux Qubit Using a Microstrip SQUID Amplifier

NASA Astrophysics Data System (ADS)

Johnson, J. E.; Hoskinson, E. M.; Macklin, C.; Siddiqi, I.; Clarke, John

2011-03-01

Dispersive techniques for the readout of superconducting qubits offer the possibility of high repetition-rate, quantum non-demolition measurement by avoiding dissipation close to the qubit. To achieve dispersive readout, we couple our three-junction aluminum flux qubit inductively to a 1-2 GHz non-linear oscillator formed by a capacitively shunted DC SQUID. The frequency of this resonator is modulated by the state of the qubit via the flux-dependent inductance of the SQUID. Readout is performed by probing the resonator in the linear (weak drive) regime with a microwave tone and monitoring the phase of the reflected signal. A microstrip SQUID amplifier (MSA) is used to increase the sensitivity of the measurement over that of a HEMT (high electron mobility transistor) amplifier. We report measurements of the performance of our amplification chain. Increased fidelity and reduced measurement backaction resulting from the implementation of the MSA will also be discussed. This work was funded in part by the U.S. Government and by BBN Technologies.

Multi-oxide active layer deposition using Applied Materials Pivot array coater for high-mobility metal oxide TFT

NASA Astrophysics Data System (ADS)

Park, Hyun Chan; Scheer, Evelyn; Witting, Karin; Hanika, Markus; Bender, Marcus; Hsu, Hao Chien; Yim, Dong Kil

2015-11-01

By controlling a thin indium tin oxide (ITO), indium zinc oxide interface layer between gate insulator and indium gallium zinc oxide (IGZO), the thin-film transistor (TFT) performance can reach higher mobility as conventional IGZO as well as superior stability. For large-area display application, Applied Materials static PVD array coater (Applied Materials GmbH & Co. KG, Alzenau, Germany) using rotary targets has been developed to enable uniform thin layer deposition in display industry. Unique magnet motion parameter optimization in Pivot sputtering coater is shown to provide very uniform thin ITO layer to reach TFT performance with high mobility, not only on small scale, but also on Gen8.5 (2500 × 2200 mm glass size) production system.

Thickness-dependent carrier mobility of ambipolar MoTe2: Interplay between interface trap and Coulomb scattering

NASA Astrophysics Data System (ADS)

Ji, Hyunjin; Lee, Gwanmu; Joo, Min-Kyu; Yun, Yoojoo; Yi, Hojoon; Park, Ji-Hoon; Suh, Dongseok; Lim, Seong Chu

2017-05-01

The correlation between the channel thickness and the carrier mobility is investigated by conducting static and low frequency (LF) noise characterization for ambipolar carriers in multilayer MoTe2 transistors. For channel thicknesses in the range of 5-15 nm, both the low-field carrier mobility and the Coulomb-scattering-limited carrier mobility (μC) are maximal at a thickness of ˜10 nm. For LF noise, the interplay of interface trap density (NST), which was minimal at ˜10 nm, and the interfacial Coulomb scattering parameter (αSC), which decreased up to 10 nm and saturated above 10 nm, explained the mobility (μC) peaked near 10 nm by the carrier fluctuation and charge distribution.

Sulfur as a surface passivation for InP

NASA Technical Reports Server (NTRS)

Iyer, R.; Chang, R. R.; Lile, D. L.

1988-01-01

The use of liquid and gas phase sulfur pretreatment of the surface of InP as a way to form a near-ideal passivated surface prior to chemical vapor deposition of SiO2 was investigated. Results of high-frequency and quasi-static capacitance-voltage measurements, as well as enhancement mode insulated gate field-effect transistor (FET) transductance and drain current stability studies, all support the efficacy of this approach for metal-insulator-semiconductor application of this semiconductor. In particular, surface state values in the range of 10 to the 10th to a few 10 to the 11th/sq cm per eV and enhancement mode FET drain current drifts of less than 5 percent over a 12 h test period were measured.

Nonlinear resonance of the rotating circular plate under static loads in magnetic field

NASA Astrophysics Data System (ADS)

Hu, Yuda; Wang, Tong

2015-11-01

The rotating circular plate is widely used in mechanical engineering, meanwhile the plates are often in the electromagnetic field in modern industry with complex loads. In order to study the resonance of a rotating circular plate under static loads in magnetic field, the nonlinear vibration equation about the spinning circular plate is derived according to Hamilton principle. The algebraic expression of the initial deflection and the magneto elastic forced disturbance differential equation are obtained through the application of Galerkin integral method. By mean of modified Multiple scale method, the strongly nonlinear amplitude-frequency response equation in steady state is established. The amplitude frequency characteristic curve and the relationship curve of amplitude changing with the static loads and the excitation force of the plate are obtained according to the numerical calculation. The influence of magnetic induction intensity, the speed of rotation and the static loads on the amplitude and the nonlinear characteristics of the spinning plate are analyzed. The proposed research provides the theory reference for the research of nonlinear resonance of rotating plates in engineering.

GeneiASE: Detection of condition-dependent and static allele-specific expression from RNA-seq data without haplotype information

PubMed Central

Edsgärd, Daniel; Iglesias, Maria Jesus; Reilly, Sarah-Jayne; Hamsten, Anders; Tornvall, Per; Odeberg, Jacob; Emanuelsson, Olof

2016-01-01

Allele-specific expression (ASE) is the imbalance in transcription between maternal and paternal alleles at a locus and can be probed in single individuals using massively parallel DNA sequencing technology. Assessing ASE within a single sample provides a static picture of the ASE, but the magnitude of ASE for a given transcript may vary between different biological conditions in an individual. Such condition-dependent ASE could indicate a genetic variation with a functional role in the phenotypic difference. We investigated ASE through RNA-sequencing of primary white blood cells from eight human individuals before and after the controlled induction of an inflammatory response, and detected condition-dependent and static ASE at 211 and 13021 variants, respectively. We developed a method, GeneiASE, to detect genes exhibiting static or condition-dependent ASE in single individuals. GeneiASE performed consistently over a range of read depths and ASE effect sizes, and did not require phasing of variants to estimate haplotypes. We observed condition-dependent ASE related to the inflammatory response in 19 genes, and static ASE in 1389 genes. Allele-specific expression was confirmed by validation of variants through real-time quantitative RT-PCR, with RNA-seq and RT-PCR ASE effect-size correlations r = 0.67 and r = 0.94 for static and condition-dependent ASE, respectively. PMID:26887787

A materials test system for static compression at elevated temperatures

NASA Astrophysics Data System (ADS)

Korellis, J. S.; Steinhaus, C. A.; Totten, J. J.

1992-06-01

This report documents modifications to our existing computer-controlled compression testing system to allow elevated temperature testing in an evacuated environment. We have adopted an 'inverse' design configuration where the evacuated test volume is located within the induction heating coil, eliminating the expense and minimizing the evacuation time of a much larger traditional vacuum chamber.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

Plasma-assisted ohmic contact for AlGaN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhang, Jiaqi; Wang, Lei; Wang, Qingpeng; Jiang, Ying; Li, Liuan; Zhu, Huichao; Ao, Jin-Ping

2016-03-01

An Al-based ohmic process assisted by an inductively coupled plasma (ICP) recess treatment is proposed for AlGaN/GaN heterostructure field-effect transistors (HFETs) to realize ohmic contact, which is only needed to anneal at 500 °C. The recess treatment was done with SiCl4 plasma with 100 W ICP power for 20 s and annealing at 575 °C for 1 min. Under these conditions, contact resistance of 0.52 Ωmm was confirmed. To suppress the ball-up phenomenon and improve the surface morphology, an Al/TiN structure was also fabricated with the same conditions. The contact resistance was further improved to 0.30 Ωmm. By using this plasma-assisted ohmic process, a gate-first HFET was fabricated. The device showed high drain current density and high transconductance. The leakage current of the TiN-gate device decreased to 10-9 A, which was 5 orders of magnitude lower than that of the device annealed at 800 °C. The results showed that the low-temperature ohmic contact process assisted by ICP treatment is promising for the fabrication of gate-first and self-aligned gate HFETs.

High-field modulated ion-selective field-effect-transistor (FET) sensors with sensitivity higher than the ideal Nernst sensitivity.

PubMed

Chen, Yi-Ting; Sarangadharan, Indu; Sukesan, Revathi; Hseih, Ching-Yen; Lee, Geng-Yen; Chyi, Jen-Inn; Wang, Yu-Lin

2018-05-29

Lead ion selective membrane (Pb-ISM) coated AlGaN/GaN high electron mobility transistors (HEMT) was used to demonstrate a whole new methodology for ion-selective FET sensors, which can create ultra-high sensitivity (-36 mV/log [Pb 2+ ]) surpassing the limit of ideal sensitivity (-29.58 mV/log [Pb 2+ ]) in a typical Nernst equation for lead ion. The largely improved sensitivity has tremendously reduced the detection limit (10 -10  M) for several orders of magnitude of lead ion concentration compared to typical ion-selective electrode (ISE) (10 -7  M). The high sensitivity was obtained by creating a strong filed between the gate electrode and the HEMT channel. Systematical investigation was done by measuring different design of the sensor and gate bias, indicating ultra-high sensitivity and ultra-low detection limit obtained only in sufficiently strong field. Theoretical study in the sensitivity consistently agrees with the experimental finding and predicts the maximum and minimum sensitivity. The detection limit of our sensor is comparable to that of Inductively-Coupled-Plasma Mass Spectrum (ICP-MS), which also has detection limit near 10 -10  M.

GaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors

NASA Astrophysics Data System (ADS)

Yu, Feng; Yao, Shengbo; Römer, Friedhard; Witzigmann, Bernd; Schimpke, Tilman; Strassburg, Martin; Bakin, Andrey; Schumacher, Hans Werner; Peiner, Erwin; Suryo Wasisto, Hutomo; Waag, Andreas

2017-03-01

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

GaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors.

PubMed

Yu, Feng; Yao, Shengbo; Römer, Friedhard; Witzigmann, Bernd; Schimpke, Tilman; Strassburg, Martin; Bakin, Andrey; Schumacher, Hans Werner; Peiner, Erwin; Wasisto, Hutomo Suryo; Waag, Andreas

2017-03-03

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Total Ionizing Dose Influence on the Single-Event Upset Sensitivity of 130-nm PD SOI SRAMs

NASA Astrophysics Data System (ADS)

Zheng, Qiwen; Cui, Jiangwei; Liu, Mengxin; Zhou, Hang; Liu, Mohan; Wei, Ying; Su, Dandan; Ma, Teng; Lu, Wu; Yu, Xuefeng; Guo, Qi; He, Chengfa

2017-07-01

Effect of total ionizing dose (TID) on single-event upset (SEU) hardness of 130 nm partially depleted (PD) silicon-on-insulator (SOI) static random access memories (SRAMs) is investigated in this paper. The measurable synergistic effect of TID on SEU sensitivity of 130-nm PD SOI SRAM was observed in our experiment, even though that is far less than micrometer and submicrometer devices. Moreover, SEU cross section after TID irradiation has no dependence on the data pattern that was applied during TID exposure: SEU cross sections are characterized by TID data pattern and its complement data pattern are decreased consistently rather than a preferred state and a nonpreferred state as micrometer and sub-micrometer SRAMs. The memory cell test structure allowing direct measurement of static noise margin (SNM) under standby operation was designed using identical memory cell layout of SRAM. Direct measurement of the memory cell SNM shows that both data sides' SNM is decreased by TID, indicating that SEU cross section of 130-nm PD SOI SRAM will be increased by TID. And, the decreased SNM is caused by threshold shift in memory cell transistors induced by “radiation-induced narrow channel effect”.

Lack of effects on key cellular parameters of MRC-5 human lung fibroblasts exposed to 370 mT static magnetic field

NASA Astrophysics Data System (ADS)

Romeo, Stefania; Sannino, Anna; Scarfì, Maria Rosaria; Massa, Rita; D'Angelo, Raffaele; Zeni, Olga

2016-01-01

The last decades have seen increased interest toward possible adverse effects arising from exposure to intense static magnetic fields. This concern is mainly due to the wider and wider applications of such fields in industry and clinical practice; among them, Magnetic Resonance Imaging (MRI) facilities are the main sources of exposure to static magnetic fields for both general public (patients) and workers. In recent investigations, exposures to static magnetic fields have been demonstrated to elicit, in different cell models, both permanent and transient modifications in cellular endpoints critical for the carcinogenesis process. The World Health Organization has therefore recommended in vitro investigations as important research need, to be carried out under strictly controlled exposure conditions. Here we report on the absence of effects on cell viability, reactive oxygen species levels and DNA integrity in MRC-5 human foetal lung fibroblasts exposed to 370 mT magnetic induction level, under different exposure regimens. Exposures have been performed by using an experimental apparatus designed and realized for operating with the static magnetic field generated by permanent magnets, and confined in a magnetic circuit, to allow cell cultures exposure in absence of confounding factors like heating or electric field components.

Lack of effects on key cellular parameters of MRC-5 human lung fibroblasts exposed to 370 mT static magnetic field

PubMed Central

Romeo, Stefania; Sannino, Anna; Scarfì, Maria Rosaria; Massa, Rita; d’Angelo, Raffaele; Zeni, Olga

2016-01-01

The last decades have seen increased interest toward possible adverse effects arising from exposure to intense static magnetic fields. This concern is mainly due to the wider and wider applications of such fields in industry and clinical practice; among them, Magnetic Resonance Imaging (MRI) facilities are the main sources of exposure to static magnetic fields for both general public (patients) and workers. In recent investigations, exposures to static magnetic fields have been demonstrated to elicit, in different cell models, both permanent and transient modifications in cellular endpoints critical for the carcinogenesis process. The World Health Organization has therefore recommended in vitro investigations as important research need, to be carried out under strictly controlled exposure conditions. Here we report on the absence of effects on cell viability, reactive oxygen species levels and DNA integrity in MRC-5 human foetal lung fibroblasts exposed to 370 mT magnetic induction level, under different exposure regimens. Exposures have been performed by using an experimental apparatus designed and realized for operating with the static magnetic field generated by permanent magnets, and confined in a magnetic circuit, to allow cell cultures exposure in absence of confounding factors like heating or electric field components. PMID:26762783

Forback DC-to-DC converter

NASA Technical Reports Server (NTRS)

Lukemire, Alan T. (Inventor)

1995-01-01

A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

Sensors for noncontact vibration diagnostics in rotating machinery

NASA Astrophysics Data System (ADS)

Procházka, Pavel

2016-06-01

The paper deals with electromagnetic sensors for noncontact vibration diagnostics in rotating machinery. The sensors were designed for operational measurements in turbomachinery by means of the tip-timing method. The main properties of eddy-current, Hall effect, induction and magnetoresistive sensors are described and compared. Possible arrangements of the experimental systems for static and dynamic calibration of the sensors are suggested and discussed.

Chemical kinetic modeling of propene oxidation at low and intermediate temperatures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wilk, R.D.; Cernansky, N.P.; Pitz, W.J.

1986-01-13

A detailed chemical kinetic mechanism for propene oxidation is developed and used to model reactions in a static reactor at temperatures of 590 to 740/sup 0/K, equivalence ratios of 0.8 to 2.0, and a pressure of 600 torr. Modeling of hydrocarbon oxidation in this temperature range is important for the validation of detailed models to be used for performing calculations related to automotive engine knock. The model predicted induction periods and species concentrations for all the species measured experimentally in a static reactor by Wilk, Cernansky, and Cohen. The detailed model predicted a temperature region of approximately constant induction periodmore » which corresponded very closely to the region of negative temperature coefficient behavior found in the experiment. Overall, the calculated concentrations of acetaldehyde, ethene, and methane were somewhat low compared to the experimental measurements, and the calculated concentrations of formaldehyde and methanol were high. The characteristic s-shape of the fuel concentration history was well predicted. The importance of OH+C/sub 3/H/sub 6/ and related rections in determining product distributions and the importance of consumption reactions for allyl radicals was demonstrated by the modeling calculations. 18 refs., 4 figs., 1 tab.« less

Magnetoacoustic tomography with magnetic induction for high-resolution bioimepedance imaging through vector source reconstruction under the static field of MRI magnet

PubMed Central

Mariappan, Leo; Hu, Gang; He, Bin

2014-01-01

Purpose: Magnetoacoustic tomography with magnetic induction (MAT-MI) is an imaging modality to reconstruct the electrical conductivity of biological tissue based on the acoustic measurements of Lorentz force induced tissue vibration. This study presents the feasibility of the authors' new MAT-MI system and vector source imaging algorithm to perform a complete reconstruction of the conductivity distribution of real biological tissues with ultrasound spatial resolution. Methods: In the present study, using ultrasound beamformation, imaging point spread functions are designed to reconstruct the induced vector source in the object which is used to estimate the object conductivity distribution. Both numerical studies and phantom experiments are performed to demonstrate the merits of the proposed method. Also, through the numerical simulations, the full width half maximum of the imaging point spread function is calculated to estimate of the spatial resolution. The tissue phantom experiments are performed with a MAT-MI imaging system in the static field of a 9.4 T magnetic resonance imaging magnet. Results: The image reconstruction through vector beamformation in the numerical and experimental studies gives a reliable estimate of the conductivity distribution in the object with a ∼1.5 mm spatial resolution corresponding to the imaging system frequency of 500 kHz ultrasound. In addition, the experiment results suggest that MAT-MI under high static magnetic field environment is able to reconstruct images of tissue-mimicking gel phantoms and real tissue samples with reliable conductivity contrast. Conclusions: The results demonstrate that MAT-MI is able to image the electrical conductivity properties of biological tissues with better than 2 mm spatial resolution at 500 kHz, and the imaging with MAT-MI under a high static magnetic field environment is able to provide improved imaging contrast for biological tissue conductivity reconstruction. PMID:24506649

Metal Solidification Imaging Process by Magnetic Induction Tomography.

PubMed

Ma, Lu; Spagnul, Stefano; Soleimani, Manuchehr

2017-11-06

There are growing number of important applications that require a contactless method for monitoring an object surrounded inside a metallic enclosure. Imaging metal solidification is a great example for which there is no real time monitoring technique at present. This paper introduces a technique - magnetic induction tomography - for the real time in-situ imaging of the metal solidification process. Rigorous experimental verifications are presented. Firstly, a single inductive coil is placed on the top of a melting wood alloy to examine the changes of its inductance during solidification process. Secondly, an array of magnetic induction coils are designed to investigate the feasibility of a tomographic approach, i.e., when one coil is driven by an alternating current as a transmitter and a vector of phase changes are measured from the remaining of the coils as receivers. Phase changes are observed when the wood alloy state changes from liquid to solid. Thirdly, a series of static cold phantoms are created to represent various liquid/solid interfaces to verify the system performance. Finally, a powerful temporal reconstruction method is applied to realise real time in-situ visualisation of the solidification and the measurement of solidified shell thickness, a first report of its kind.

Evaluation of a single-pixel one-transistor active pixel sensor for fingerprint imaging

NASA Astrophysics Data System (ADS)

Xu, Man; Ou, Hai; Chen, Jun; Wang, Kai

2015-08-01

Since it first appeared in iPhone 5S in 2013, fingerprint identification (ID) has rapidly gained popularity among consumers. Current fingerprint-enabled smartphones unanimously consists of a discrete sensor to perform fingerprint ID. This architecture not only incurs higher material and manufacturing cost, but also provides only static identification and limited authentication. Hence as the demand for a thinner, lighter, and more secure handset grows, we propose a novel pixel architecture that is a photosensitive device embedded in a display pixel and detects the reflected light from the finger touch for high resolution, high fidelity and dynamic biometrics. To this purpose, an amorphous silicon (a-Si:H) dual-gate photo TFT working in both fingerprint-imaging mode and display-driving mode will be developed.

Nanowire NMOS Logic Inverter Characterization.

PubMed

Hashim, Yasir

2016-06-01

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

[Cyclorotation of the eye in wavefront-guided LASIK using a static eyetracker with iris recognition].

PubMed

Kohnen, T; Kühne, C; Cichocki, M; Strenger, A

2007-01-01

Centration of the ablation zone decisively influences the result of wavefront-guided LASIK. Cyclorotation of the eye occurs as the patient changes from the sitting position during aberrometry to the supine position during laser surgery and may lead to induction of lower and higher order aberrations. Twenty patients (40 eyes) underwent wavefront-guided LASIK (B&L 217z 100 excimer laser) with a static eyetracker driven by iris recognition (mean preoperative SE: -4.72+/-1.45 D; range: -1.63 to -7.00 D). The iris patterns of the patients' eyes were memorized during aberrometry and after flap creation. The mean absolute value of the measured cyclorotation was -1.5+/-4.2 degrees (range: -11.0 to 6.9 degrees ). The mean cyclorotation was 3.5+/-2.7 masculine (range: 0.1 to 11.0 degrees ). In 65% of all eyes cyclorotation was >2 masculine. A static eyetracker driven by iris recognition demonstrated that cyclorotation of up to 11 degrees may occur in myopic and myopic astigmatic eyes when changing from a sitting to a supine position. Use of static eyetrackers with iris recognition may provide a more precise positioning of the ablation profile as they detect and compensate cyclorotation.

A thick-walled sphere rotating in a uniform magnetic field: The next step to de-spin a space object

NASA Astrophysics Data System (ADS)

Nurge, Mark A.; Youngquist, Robert C.; Caracciolo, Ryan A.; Peck, Mason; Leve, Frederick A.

2017-08-01

Modeling the interaction between a moving conductor and a static magnetic field is critical to understanding the operation of induction motors, eddy current braking, and the dynamics of satellites moving through Earth's magnetic field. Here, we develop the case of a thick-walled sphere rotating in a uniform magnetic field, which is the simplest, non-trivial, magneto-statics problem that leads to complete closed-form expressions for the resulting potentials, fields, and currents. This solution requires knowledge of all of Maxwell's time independent equations, scalar and vector potential equations, and the Lorentz force law. The paper presents four cases and their associated experimental results, making this topic appropriate for an advanced student lab project.

Diffusion-mediated dephasing in the dipole field around a single spherical magnetic object.

PubMed

Buschle, Lukas R; Kurz, Felix T; Kampf, Thomas; Triphan, Simon M F; Schlemmer, Heinz-Peter; Ziener, Christian Herbert

2015-11-01

In this work, the time evolution of the free induction decay caused by the local dipole field of a spherical magnetic perturber is analyzed. The complicated treatment of the diffusion process is replaced by the strong-collision-approximation that allows a determination of the free induction decay in dependence of the underlying microscopic tissue parameters such as diffusion coefficient, sphere radius and susceptibility difference. The interplay between susceptibility- and diffusion-mediated effects yields several dephasing regimes of which, so far, only the classical regimes of motional narrowing and static dephasing for dominant and negligible diffusion, respectively, were extensively examined. Due to the asymmetric form of the dipole field for spherical objects, the free induction decay exhibits a complex component in contradiction to the cylindrical case, where the symmetric local dipole field only causes a purely real induction decay. Knowledge of the shape of the corresponding frequency distribution is necessary for the evaluation of more sophisticated pulse sequences and a detailed understanding of the off-resonance distribution allows improved quantification of transverse relaxation. Copyright © 2015 Elsevier Inc. All rights reserved.

Known Good Substrates Year 1

DTIC Science & Technology

2007-12-05

yield record setting carrier lifetime values and very low concentrations of point defects. Epiwafers delivered for fabrication of RF static induction ...boules and on improved furnace uniformity (adding rotation, etc.). Pareto analysis was performed on wafer yield loss at the start of every quarter...100mm PVT process. Work focused on modeling the process for longer (50 mm) boules and on improved furnace uniformity. Pareto analysis was performed

STABILIZED TRANSISTOR AMPLIFIER

DOEpatents

Noe, J.B.

1963-05-01

A temperature stabilized transistor amplifier having a pair of transistors coupled in cascade relation that are capable of providing amplification through a temperature range of - 100 un. Concent 85% F to 400 un. Concent 85% F described. The stabilization of the amplifier is attained by coupling a feedback signal taken from the emitter of second transistor at a junction between two serially arranged biasing resistances in the circuit of the emitter of the second transistor to the base of the first transistor. Thus, a change in the emitter current of the second transistor is automatically corrected by the feedback adjustment of the base-emitter potential of the first transistor and by a corresponding change in the base-emitter potential of the second transistor. (AEC)

Self-terminated etching of GaN with a high selectivity over AlGaN under inductively coupled Cl2/N2/O2 plasma with a low-energy ion bombardment

NASA Astrophysics Data System (ADS)

Zhong, Yaozong; Zhou, Yu; Gao, Hongwei; Dai, Shujun; He, Junlei; Feng, Meixin; Sun, Qian; Zhang, Jijun; Zhao, Yanfei; DingSun, An; Yang, Hui

2017-10-01

Etching of GaN/AlGaN heterostructure by O-containing inductively coupled Cl2/N2 plasma with a low-energy ion bombardment can be self-terminated at the surface of the AlGaN layer. The estimated etching rates of GaN and AlGaN were 42 and 0.6 nm/min, respectively, giving a selective etching ratio of 70:1. To study the mechanism of the etching self-termination, detailed characterization and analyses were carried out, including X-ray photoelectron spectroscopy (XPS) and time-of-flight secondary ion mass spectroscopy (TOF-SIMS). It was found that in the presence of oxygen, the top surface of the AlGaN layer was converted into a thin film of (Al,Ga)Ox with a high bonding energy, which effectively prevented the underlying atoms from a further etching, resulting in a nearly self-terminated etching. This technique enables a uniform and reproducible fabrication process for enhancement-mode high electron mobility transistors with a p-GaN gate.

Transistor Effect in Improperly Connected Transistors.

ERIC Educational Resources Information Center

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Evolvable circuit with transistor-level reconfigurability

NASA Technical Reports Server (NTRS)

Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

2004-01-01

An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

The Influence of Static and Rotating Magnetic Fields on Heat and Mass Transfer in Silicon Floating Zones

NASA Technical Reports Server (NTRS)

Croell, Arne; Dold, P.; Kaiser, Th.; Szofran, Frank; Benz, K. W.

1999-01-01

Hear and mass transfer in float-zone processing are strongly influenced by convective flows in the zone. They are caused by buoyancy convection, thermocapillary (Marangoni) convection, or artificial sources such as rotation and radio frequency heating. Flows in conducting melts can be controlled by the use of magnetic fields, either by damping fluid motion with static fields or by generating a def@ned flow with rotating fields. The possibilities of using static and rotating magnetic fields in silicon floating-zone growth have been investigated by experiments in axial static fields up to ST and in transverse rotating magnetic fields up to 7.S mT. Static fields of a few 100 MT already suppress most striations but are detrimental to the radial segregation by introducing a coring effect. A complete suppression of dopant striations caused by time-dependent thermocapillary convection and a reduction of the coring to insignificant values, combined with a shift of the axial segregation profile towards a more diffusion-limited case, is possible with static fields ? 1T. However, under certain conditions the use of high axial magnetic fields can lead to the appearance of a new type of pronounced dopant striations, caused by thermoelec:romagnetic convection. The use of a transverse rotating magnetic field influences the microscopic segregation at quite low inductions, of the order of a few mT. The field shifts time-dependent flows and the resulting striation patterns from a broad range of low frequencies at high amplitudes to a few high frequencies at low amplitudes

The Influence of Static and Rotating Magnetic Fields on Heat and Mass Transfer in Silicon Floating Zones

NASA Technical Reports Server (NTRS)

Croll, A.; Dold, P.; Kaiser, Th.; Szofran, F. R.; Benz, K. W.

1999-01-01

Heat and mass transfer in float-zone processing are strongly influenced by convective flows in the zone. They are caused by buoyancy convection, thermocapillary (Marangoni) convection, or artificial sources such as rotation and radio-frequency heating. Flows in conducting melts can be controlled by the use of magnetic fields, either by damping fluid motion with static fields or by generating a defined flow with rotating fields. The possibilities of using static and rotating magnetic fields in silicon floating-zone growth have been investigated by experiments in axial static fields up to 5 T and in transverse rotating magnetic fields up to 7.5 mT. Static fields of a few 100 mT already suppress most striations but are detrimental to the radial segregation by introducing a coring effect. A complete suppression of dopant striations caused by time-dependent thermocapillary convection and a reduction of the coring to insignificant values, combined with a shift of the axial segregation profile toward a more diffusion-limited case, is possible with static fields greater than or equal to 1 T. However, under certain conditions the use of high axial magnetic fields can lead to the appearance of a new type of pronounced dopant striations, caused by thermoelectromagnetic convection. The use of a transverse rotating magnetic field influences the microscopic segregation at quite low inductions, of the order of a few millitesla. The field shifts time- dependent flows and the resulting striation patterns from a broad range of low frequencies at high amplitudes to a few high frequencies at low amplitudes.

[Dynamic hierarchy of regulatory peptides. Structure of the induction relations of regulators as the target for therapeutic agents].

PubMed

Koroleva, S V; Miasoedov, N F

2012-01-01

Based on the database information (literature period 1970-2010 gg.) on the effects of regulatory peptides (RP) and non-peptide neurotransmitters (dopamine, serotonin, norepi-nephrine, acetylcholine) it was analyzed of possible cascade processes of endogenous regulators. It was found that the entire continuum of RP and mediators is a chaotic soup of the ordered three-level compartments. Such a dynamic functional hierarchy of endogenous regulators allows to create start-up and corrective tasks for a variety of physiological functions. Some examples of static and dynamic patterns of induction processes of RP and mediators (that regulate the states of anxiety, depression, learning and memory, feeding behavior, reproductive processes, etc.) are considered.

Welding of Aluminum Alloys to Steels: An Overview

DTIC Science & Technology

2013-08-01

and deformations are a few examples of the unwanted consequences which somehow would lead to brittle fracture, fatigue fracture, shape instability...was made under the copper tips of the spot welding machine. The fatigue results showed higher fatigue strength of the joints with transition layer...kHz ultrasonic butt welding system with a vibration source applying eight bolt-clamped Langevin type PZT transducers and a 50 kW static induction

Calculation of the magnetic field in the active zone of a hysteresis clutch

NASA Technical Reports Server (NTRS)

Ermilov, M. A.; Glukhov, O. M.

1977-01-01

The initial distribution of magnetic induction in the armature stationary was calculated relative to the polar system of a hysteresis clutch. Using several assumptions, the problem is reduced to calculating the static magnetic field in the ferromagnetic plate with finite and continuous magnetic permeability placed in the air gap between two identical, parallel semiconductors with rack fixed relative to the tooth or slot position.

Nonlinear Dynamics of a Magnetically Driven Duffing-Type Spring-Magnet Oscillator in the Static Magnetic Field of a Coil

ERIC Educational Resources Information Center

Donoso, Guillermo; Ladera, Celso L.

2012-01-01

We study the nonlinear oscillations of a forced and weakly dissipative spring-magnet system moving in the magnetic fields of two fixed coaxial, hollow induction coils. As the first coil is excited with a dc current, both a linear and a cubic magnet-position dependent force appear on the magnet-spring system. The second coil, located below the…

Nitrogen Gas Plasma Generated by a Static Induction Thyristor as a Pulsed Power Supply Inactivates Adenovirus

PubMed Central

Sakudo, Akikazu; Toyokawa, Yoichi; Imanishi, Yuichiro

2016-01-01

Adenovirus is one of the most important causative agents of iatrogenic infections derived from contaminated medical devices or finger contact. In this study, we investigated whether nitrogen gas plasma, generated by applying a short high-voltage pulse to nitrogen using a static induction thyristor power supply (1.5 kilo pulse per second), exhibited a virucidal effect against adenoviruses. Viral titer was reduced by one log within 0.94 min. Results from detection of viral capsid proteins, hexon and penton, by Western blotting and immunochromatography were unaffected by the plasma treatment. In contrast, analysis using the polymerase chain reaction suggested that plasma treatment damages the viral genomic DNA. Reactive chemical products (hydrogen peroxide, nitrate, and nitrite), ultraviolet light (UV-A) and slight temperature elevations were observed during the operation of the gas plasma device. Viral titer versus intensity of each potential virucidal factor were used to identify the primary mechanism of disinfection of adenovirus. Although exposure to equivalent levels of UV-A or heat treatment did not inactivate adenovirus, treatment with a relatively low concentration of hydrogen peroxide efficiently inactivated the virus. Our results suggest the nitrogen gas plasma generates reactive chemical products that inactivate adenovirus by damaging the viral genomic DNA. PMID:27322066

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Transistor-based interface circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2007-02-13

Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

Transistor-based particle detection systems and methods

DOEpatents

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Theoretical analysis for the design of the French watt balance experiment force comparator

NASA Astrophysics Data System (ADS)

Pinot, Patrick; Genevès, Gerard; Haddad, Darine; David, Jean; Juncar, Patrick; Lecollinet, Michel; Macé, Stéphane; Villar, François

2007-09-01

This paper presents a preliminary analysis for designing a force comparator to be used in the French watt balance experiment. The first stage of this experiment consists in a static equilibrium, by means of a mechanical beam balance, between a gravitational force (a weight of an artefact having a known mass submitted to the acceleration due to the gravity) and a vertical electromagnetic force acting on a coil driven by a current subject to the magnetic induction field provided by a permanent magnet. The principle of the force comparison in the French experiment is explained. The general design configuration of the force balance using flexure strips as pivots is discussed and theoretical calculation results based on realistic assumptions of the static and dynamic behaviors of the balance are presented.

Theoretical analysis for the design of the French watt balance experiment force comparator.

PubMed

Pinot, Patrick; Genevès, Gerard; Haddad, Darine; David, Jean; Juncar, Patrick; Lecollinet, Michel; Macé, Stéphane; Villar, François

2007-09-01

This paper presents a preliminary analysis for designing a force comparator to be used in the French watt balance experiment. The first stage of this experiment consists in a static equilibrium, by means of a mechanical beam balance, between a gravitational force (a weight of an artefact having a known mass submitted to the acceleration due to the gravity) and a vertical electromagnetic force acting on a coil driven by a current subject to the magnetic induction field provided by a permanent magnet. The principle of the force comparison in the French experiment is explained. The general design configuration of the force balance using flexure strips as pivots is discussed and theoretical calculation results based on realistic assumptions of the static and dynamic behaviors of the balance are presented.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Potts, C.; Faber, M.; Gunderson, G.

The as-built lattice of the Rapid Cycling Synchrotron (RCS) had two sets of correction sextupoles and two sets of quadrupoles energized by dc power supplies to control the tune and the tune tilt. With this method of powering these magnets, adjustment of tune conditions during the accelerating cycle as needed was not possible. A set of dynamically programmable power supplies has been built and operated to provide the required chromaticity adjustment. The short accelerating time (16.7 ms) of the RCS and the inductance of the magnets dictated large transistor amplifier power supplies. The required time resolution and waveform flexibility indicatedmore » the desirability of computer control. Both the amplifiers and controls are described, along with resulting improvements in the beam performance. 5 refs.« less

A study of the high frequency limitations of series resonant converters

NASA Technical Reports Server (NTRS)

Stuart, T. A.; King, R. J.

1982-01-01

A transformer induced oscillation in series resonant (SR) converters is studied. It may occur in the discontinuous current mode. The source of the oscillation is an unexpected resonant circuit formed by normal resonance components in series with the magnetizing inductance of the output transformers. The methods for achieving cyclic stability are: to use a half bridge SR converter where q0.5. Q should be as close to 1.0 as possible. If 0.5q1.0, the instability will be avoided if psi2/3q-1/3. The second objective was to investigate a power field effect transistor (FET) version of the SR converter capable of operating at frequencies above 100 KHz, to study component stress and losses at various frequencies.

Application of Static Var Compensator (SVC) With PI Controller for Grid Integration of Wind Farm Using Harmony Search

NASA Astrophysics Data System (ADS)

Keshta, H. E.; Ali, A. A.; Saied, E. M.; Bendary, F. M.

2016-10-01

Large-scale integration of wind turbine generators (WTGs) may have significant impacts on power system operation with respect to system frequency and bus voltages. This paper studies the effect of Static Var Compensator (SVC) connected to wind energy conversion system (WECS) on voltage profile and the power generated from the induction generator (IG) in wind farm. Also paper presents, a dynamic reactive power compensation using Static Var Compensator (SVC) at the a point of interconnection of wind farm while static compensation (Fixed Capacitor Bank) is unable to prevent voltage collapse. Moreover, this paper shows that using advanced optimization techniques based on artificial intelligence (AI) such as Harmony Search Algorithm (HS) and Self-Adaptive Global Harmony Search Algorithm (SGHS) instead of a Conventional Control Method to tune the parameters of PI controller for SVC and pitch angle. Also paper illustrates that the performance of the system with controllers based on AI is improved under different operating conditions. MATLAB/Simulink based simulation is utilized to demonstrate the application of SVC in wind farm integration. It is also carried out to investigate the enhancement in performance of the WECS achieved with a PI Controller tuned by Harmony Search Algorithm as compared to a Conventional Control Method.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Multiple-channel detection of cellular activities by ion-sensitive transistors

NASA Astrophysics Data System (ADS)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

A system for automated noise parameter measurements on MR preamplifiers and application to high B(0) fields.

PubMed

Lagore, Russell L; Roberts, Brodi Roduta; Possanzini, Cecilia; Saylor, Charles; Fallone, B Gino; De Zanche, Nicola

2014-08-01

A noise figure and noise parameter measurement system was developed that consists of a combination spectrum and network analyzer, preamplifier, programmable power supply, noise source, tuning board, and desktop computer. The system uses the Y-factor method for noise figure calculation and allows calibrations to correct for a decrease in excess noise ratio between the noise source and device under test, second stage (system) noise, ambient temperature variations, and available gain of the device under test. Noise parameters are extracted by performing noise figure measurements at several source impedance values obtained by adjusting an electronically controlled tuner. Results for several amplifiers at 128 MHz and 200 MHz agree with independent measurements and with the corresponding datasheets. With some modifications, the system was also used to characterize the noise figure of MRI preamplifiers in strong static magnetic fields up to 9.4 T. In most amplifiers tested the gain was found to be reduced by the magnetic field, while the noise figure increased. These changes are detrimental to signal quality (SNR) and are dependent on the electron mobility and design of the amplifier's semiconductor devices. Consequently, gallium arsenide (GaAs) field-effect transistors are most sensitive to magnetic fields due to their high electron mobility and long, narrow channel, while silicon-germanium (SiGe) bipolar transistor amplifiers are largely immune due to their very thin base. Copyright © 2014 John Wiley & Sons, Ltd.

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

PubMed

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (∼4.1 eV) compared to that of a pristine Au electrode (∼4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ∼0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ∼0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) < 70 nA when I(on) > 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ∼12 kHz) based on a solution-processed ambipolar polymer are demonstrated.

Programmable ion-sensitive transistor interfaces. II. Biomolecular sensing and manipulation.

PubMed

Jayant, Krishna; Auluck, Kshitij; Funke, Mary; Anwar, Sharlin; Phelps, Joshua B; Gordon, Philip H; Rajwade, Shantanu R; Kan, Edwin C

2013-07-01

The chemoreceptive neuron metal-oxide-semiconductor transistor described in the preceding paper is further used to monitor the adsorption and interaction of DNA molecules and subsequently manipulate the adsorbed biomolecules with injected static charge. Adsorption of DNA molecules onto poly-L-lysine-coated sensing gates (SGs) modulates the floating gate (FG) potential ψ(O), which is reflected as a threshold voltage shift measured from the control gate (CG) V(th_CG). The asymmetric capacitive coupling between the CG and SG to the FG results in V(th_CG) amplification. The electric field in the SG oxide E(SG_ox) is fundamentally different when we drive the current readout with V(CG) and V(ref) (i.e., the potential applied to the CG and reference electrode, respectively). The V(CG)-driven readout induces a larger E(SG_ox), leading to a larger V(th_CG) shift when DNA is present. Simulation studies indicate that the counterion screening within the DNA membrane is responsible for this effect. The DNA manipulation mechanism is enabled by tunneling electrons (program) or holes (erase) onto FGs to produce repulsive or attractive forces. Programming leads to repulsion and eventual desorption of DNA, while erasing reestablishes adsorption. We further show that injected holes or electrons prior to DNA addition either aids or disrupts the immobilization process, which can be used for addressable sensor interfaces. To further substantiate DNA manipulation, we used impedance spectroscopy with a split ac-dc technique to reveal the net interface impedance before and after charge injection.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

Static voltage distribution between turns of secondary winding of air-core spiral strip transformer and its application

NASA Astrophysics Data System (ADS)

Zhang, Hong-bo; Liu, Jin-liang; Cheng, Xin-bing; Zhang, Yu

2011-09-01

The static voltage distribution between winding turns has great impact on output characteristics and lifetime of the air-core spiral strip pulse transformer (ACSSPT). In this paper, winding inductance was calculated by electromagnetic theory, so that the static voltage distribution between turns of secondary winding of ACSSPT was analyzed conveniently. According to theoretical analysis, a voltage gradient because of the turn-to-turn capacitance was clearly noticeable across the ground turns. Simulation results of Pspice and CST EM Studio codes showed that the voltage distribution between turns of secondary winding had linear increments from the output turn to the ground turn. In experiment, the difference in increased voltage between the ground turns and the output turns of a 20-turns secondary winding is almost 50%, which is believed to be responsible for premature breakdown of the insulation, particularly between the ground turns. The experimental results demonstrated the theoretical analysis and simulation results, which had important value for stable and long lifetime ACSSPT design. A new ACSSPT with improved structure has been used successfully in intense electron beam accelerators steadily.

Electrochemical doping for lowering contact barriers in organic field effect transistors

PubMed Central

Schaur, Stefan; Stadler, Philipp; Meana-Esteban, Beatriz; Neugebauer, Helmut; Serdar Sariciftci, N.

2012-01-01

By electrochemically p-doping pentacene in the vicinity of the source-drain electrodes in organic field effect transistors the injection barrier for holes is decreased. The focus of this work is put on the influence of the p-doping process on the transistor performance. Cyclic voltammetry performed on a pentacene based transistor exhibits a reversible p-doping response. This doped state is evoked at the transistor injection electrodes. An improvement is observed when comparing transistor characteristics before and after the doping process apparent by an improved transistor on-current. This effect is reflected in the analysis of the contact resistances of the devices. PMID:23483101

VOLTAGE-CONTROLLED TRANSISTOR OSCILLATOR

DOEpatents

Scheele, P.F.

1958-09-16

This patent relates to transistor oscillators and in particular to those transistor oscillators whose frequencies vary according to controlling voltages. A principal feature of the disclosed transistor oscillator circuit resides in the temperature compensation of the frequency modulating stage by the use of a resistorthermistor network. The resistor-thermistor network components are selected to have the network resistance, which is in series with the modulator transistor emitter circuit, vary with temperature to compensate for variation in the parameters of the transistor due to temperature change.

Evolutionary Technique for Automated Synthesis of Electronic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

2007-01-01

An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Magnetoacoustic tomography with magnetic induction for imaging electrical impedance of biological tissue

NASA Astrophysics Data System (ADS)

Li, Xu; Xu, Yuan; He, Bin

2006-03-01

An experimental feasibility study was conducted on magnetoacoustic tomography with magnetic induction (MAT-MI). It is demonstrated that the two-dimensional MAT-MI system can detect and image the boundaries between regions of different electrical conductivities with high spatial resolution. Utilizing a magnetic stimulation coil, MAT-MI evokes magnetically induced eddy current in an object which is placed in a static magnetic field. Because of the existence of Lorenz forces, the eddy current in turn causes acoustic vibrations, which are measured around the object in order to reconstruct the electrical impedance distribution of the object. The present experimental results from the saline and gel phantoms are promising and suggest the merits of MAT-MI in imaging electrical impedance of biological tissue with high spatial resolution.

Interband Lateral Resonant Tunneling Transistor.

DTIC Science & Technology

1994-11-14

INTERBAND LATERAL RESONANT TUNNELING TRANSISTOR 10 BACKGROUND OF THE INVENTION Field of the Invention This invention pertains to a tunneling transistor...and in 15 particular to an interband lateral resonant tunneling transistor. Description of Related Art Conventional semiconductor technologies are... interband lateral resonant tunneling transistor along the cross-section B-B of Figure 2c. Figure 4 is another preferred embodiment cross-sectional 20

Finite element analysis and performance study of switched reluctance generator

NASA Astrophysics Data System (ADS)

Zhang, Qianhan; Guo, Yingjun; Xu, Qi; Yu, Xiaoying; Guo, Yajie

2017-03-01

Analyses a three-phase 12/8 switched reluctance generator (SRG) which is based on its structure and performance principle. The initial size data were calculated by MathCAD, and the simulation model was set up in the ANSOFT software environment with the maximum efficiency and the maximum output power as the main reference parameters. The outer diameter of the stator and the inner diameter of the rotor were parameterized. The static magnetic field distribution, magnetic flux, magnetic energy, torque, inductance characteristics, back electromotive force and phase current waveform of SRG is obtained by analyzing the static magnetic field and the steady state motion of two-dimensional transient magnetic field in ANSOFT environment. Finally, the experimental data of the prototype are compared with the simulation results, which provide a reliable basis for the design and research of SRG wind turbine system.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

PubMed

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Resistive switching characteristics and mechanisms in silicon oxide memory devices

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

2016-05-01

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

Minimizing the effect of process mismatch in a neuromorphic system using spike-timing-dependent adaptation.

PubMed

Cameron, Katherine; Murray, Alan

2008-05-01

This paper investigates whether spike-timing-dependent plasticity (STDP) can minimize the effect of mismatch within the context of a depth-from-motion algorithm. To improve noise rejection, this algorithm contains a spike prediction element, whose performance is degraded by analog very large scale integration (VLSI) mismatch. The error between the actual spike arrival time and the prediction is used as the input to an STDP circuit, to improve future predictions. Before STDP adaptation, the error reflects the degree of mismatch within the prediction circuitry. After STDP adaptation, the error indicates to what extent the adaptive circuitry can minimize the effect of transistor mismatch. The circuitry is tested with static and varying prediction times and chip results are presented. The effect of noisy spikes is also investigated. Under all conditions the STDP adaptation is shown to improve performance.

Superconducting flux flow digital circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.

1993-03-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-[mu]m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps,more » and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic.« less

Negative inductance circuits for metamaterial bandwidth enhancement

NASA Astrophysics Data System (ADS)

Avignon-Meseldzija, Emilie; Lepetit, Thomas; Ferreira, Pietro Maris; Boust, Fabrice

2017-12-01

Passive metamaterials have yet to be translated into applications on a large scale due in large part to their limited bandwidth. To overcome this limitation many authors have suggested coupling metamaterials to non-Foster circuits. However, up to now, the number of convincing demonstrations based on non-Foster metamaterials has been very limited. This paper intends to clarify why progress has been so slow, i.e., the fundamental difficulty in making a truly broadband and efficient non-Foster metamaterial. To this end, we consider two families of metamaterials, namely Artificial Magnetic Media and Artificial Magnetic Conductors. In both cases, it turns out that bandwidth enhancement requires negative inductance with almost zero resistance. To estimate bandwidth enhancement with actual non-Foster circuits, we consider two classes of such circuits, namely Linvill and gyrator. The issue of stability being critical, both metamaterial families are studied with equivalent circuits that include advanced models of these non-Foster circuits. Conclusions are different for Artificial Magnetic Media coupled to Linvill circuits and Artificial Magnetic Conductors coupled to gyrator circuits. In the first case, requirements for bandwidth enhancement and stability are very hard to meet simultaneously whereas, in the second case, an adjustment of the transistor gain does significantly increase bandwidth.

Recent progress in photoactive organic field-effect transistors.

PubMed

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

Advanced Propulsion Power Distribution System for Next Generation Electric/Hybrid Vehicle. Phase 1; Preliminary System Studies

NASA Technical Reports Server (NTRS)

Bose, Bimal K.; Kim, Min-Huei

1995-01-01

The report essentially summarizes the work performed in order to satisfy the above project objective. In the beginning, different energy storage devices, such as battery, flywheel and ultra capacitor are reviewed and compared, establishing the superiority of the battery. Then, the possible power sources, such as IC engine, diesel engine, gas turbine and fuel cell are reviewed and compared, and the superiority of IC engine has been established. Different types of machines for drive motor/engine generator, such as induction machine, PM synchronous machine and switched reluctance machine are compared, and the induction machine is established as the superior candidate. Similar discussion was made for power converters and devices. The Insulated Gate Bipolar Transistor (IGBT) appears to be the most superior device although Mercury Cadmium Telluride (MCT) shows future promise. Different types of candidate distribution systems with the possible combinations of power and energy sources have been discussed and the most viable system consisting of battery, IC engine and induction machine has been identified. Then, HFAC system has been compared with the DC system establishing the superiority of the former. The detailed component sizing calculations of HFAC and DC systems reinforce the superiority of the former. A preliminary control strategy has been developed for the candidate HFAC system. Finally, modeling and simulation study have been made to validate the system performance. The study in the report demonstrates the superiority of HFAC distribution system for next generation electric/hybrid vehicle.

MR 201104: Evaluation of Discrimination Technologies and Classification Results and MR 201157: Demonstration of MetalMapper Static Data Acquisition and Data Analysis

DTIC Science & Technology

2016-09-23

Acquisition and Data Analysis). EMI sensors, MetalMapper, man-portable Time-domain Electromagnetic Multi-sensor Towed Array Detection System (TEMTADS...California Department of Toxic Substances Control EM61 EM61-MK2 EMI electromagnetic induction ESTCP Environmental Security Technology Certification...SOP Standard Operating Procedure v TEMTADS Time-domain Electromagnetic Multi-sensor Towed Array Detection System man-portable 2x2 TOI target(s

Development of a high-power solid-state switch using static induction thyristors for a klystron modulator

NASA Astrophysics Data System (ADS)

Tokuchi, Akira; Kamitsukasa, Fumiyoshi; Furukawa, Kazuya; Kawase, Keigo; Kato, Ryukou; Irizawa, Akinori; Fujimoto, Masaki; Osumi, Hiroki; Funakoshi, Sousuke; Tsutsumi, Ryouta; Suemine, Shoji; Honda, Yoshihide; Isoyama, Goro

2015-01-01

We developed a solid-state switch with static induction thyristors for the klystron modulator of the L-band electron linear accelerator (linac) at the Institute of Scientific and Industrial Research, Osaka University. This switch is designed to have maximum specifications of a holding voltage of 25 kV and a current of 6 kA at the repetition frequency of 10 Hz for forced air cooling. The turn-on time of the switch was measured with a matched resistor to be 270 ns, which is sufficiently fast for the klystron modulator. The switch is retrofitted in the modulator to generate 1.3 GHz RF pulses with durations of either 4 or 8 μs using a 30 MW klystron, and the linac is successfully operated under maximum conditions. This finding demonstrates that the switch can be used as a high-power switch for the modulator. Pulse-to-pulse variations of the klystron voltage are measured to be less than 0.015%, and those of RF power and phase are lower than 0.15% and 0.1°, respectively. These values are significantly smaller than those obtained with a thyratron; hence, the stability of the main RF system is improved. The solid-state switch has been used in normal operation of the linac for more than a year without any serious trouble. Thus, we confirmed the switch's robustness and long-term reliability.

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries.

PubMed

Lee, Yi-Ying; Hsu, Chih-Yuan; Lin, Ling-Jiun; Chang, Chih-Chun; Cheng, Hsiao-Chun; Yeh, Tsung-Hsien; Hu, Rei-Hsing; Lin, Che; Xie, Zhen; Chen, Bor-Sen

2013-10-27

Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components.According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries

PubMed Central

2013-01-01

Background Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Results Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components. According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. Conclusion This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching. PMID:24160305

A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector

NASA Astrophysics Data System (ADS)

Parkalian, N.; Robens, M.; Grewing, C.; Christ, V.; Kruth, A.; Liebau, D.; Muralidharan, P.; Nielinger, D.; Roth, C.; Yegin, U.; Zambanini, A.; van Waasen, S.

2018-02-01

This paper presents a 4 GHz phase locked loop (PLL), which is implemented in a 65 nm standard CMOS process to provide low noise and high frequency sampling clocks for readout electronics to be used in the Jiangmen Underground Neutrino Observatory (JUNO) experiment. Based on the application requirements the target of the design is to find the best compromise between power consumption, area and phase noise for a highly reliable topology. The design implements a novel method for the charge pump that suppresses current mismatch when the PLL is locked. This reduces static phase offset at the inputs of the phase-frequency detector (PFD) that otherwise would introduce spurs at the PLL output. In addition, a technique of amplitude regulation for the voltage controlled oscillator (VCO) is presented to provide low noise and reliable operation. The combination of thin and thick oxide varactor transistors ensures optimum tuning range and linearity over process as well as temperature changes for the VCO without additional calibration steps. The current mismatch at the output of the charge pump for the control voltage at about half the 1 V supply voltage is below 0.3% and static phase offset down to 0.25% is reached. The total PLL consumes 18.5 mW power at 1.8 V supply for the VCO and 1 V supply for the other parts.

Stretchable transistors with buckled carbon nanotube films as conducting channels

DOEpatents

Arnold, Michael S; Xu, Feng

2015-03-24

Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

PubMed Central

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-01-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing. PMID:26349444

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

NASA Astrophysics Data System (ADS)

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-09-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing.

Current control circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2005-03-15

Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Triple-mode single-transistor graphene amplifier and its applications.

PubMed

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Self-protecting transistor oscillator for treating animal tissues

DOEpatents

Doss, James D.

1980-01-01

A transistor oscillator circuit wherein the load current applied to animal tissue treatment electrodes is fed back to the transistor. Removal of load is sensed to automatically remove feedback and stop oscillations. A thermistor on one treatment electrode senses temperature, and by means of a control circuit controls oscillator transistor current.

Development and Experimental Evaluation of an Automated Multi-Media Course on Transistors.

ERIC Educational Resources Information Center

Whitted, J.H., Jr.; And Others

A completely automated multi-media self-study program for teaching a portion of electronic solid-state fundamentals was developed. The subject matter areas included were fundamental theory of transistors, transistor amplifier fundamentals, and simple mathematical analysis of transistors including equivalent circuits, parameters, and characteristic…

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

A novel adaptive control method for induction motor based on Backstepping approach using dSpace DS 1104 control board

NASA Astrophysics Data System (ADS)

Ben Regaya, Chiheb; Farhani, Fethi; Zaafouri, Abderrahmen; Chaari, Abdelkader

2018-02-01

This paper presents a new adaptive Backstepping technique to handle the induction motor (IM) rotor resistance tracking problem. The proposed solution leads to improve the robustness of the control system. Given the presence of static error when estimating the rotor resistance with classical methods, and the sensitivity to the load torque variation at low speed, a new Backstepping observer enhanced with an integral action of the tracking errors is presented, which can be established in two steps. The first one consists to estimate the rotor flux using a Backstepping observer. The second step, defines the adaptation mechanism of the rotor resistance based on the estimated rotor-flux. The asymptotic stability of the observer is proven by Lyapunov theory. To validate the proposed solution, a simulation and experimental benchmarking of a 3 kW induction motor are presented and analyzed. The obtained results show the effectiveness of the proposed solution compared to the model reference adaptive system (MRAS) rotor resistance observer presented in other recent works.

An Intelligent Harmonic Synthesis Technique for Air-Gap Eccentricity Fault Diagnosis in Induction Motors

NASA Astrophysics Data System (ADS)

Li, De Z.; Wang, Wilson; Ismail, Fathy

2017-11-01

Induction motors (IMs) are commonly used in various industrial applications. To improve energy consumption efficiency, a reliable IM health condition monitoring system is very useful to detect IM fault at its earliest stage to prevent operation degradation, and malfunction of IMs. An intelligent harmonic synthesis technique is proposed in this work to conduct incipient air-gap eccentricity fault detection in IMs. The fault harmonic series are synthesized to enhance fault features. Fault related local spectra are processed to derive fault indicators for IM air-gap eccentricity diagnosis. The effectiveness of the proposed harmonic synthesis technique is examined experimentally by IMs with static air-gap eccentricity and dynamic air-gap eccentricity states under different load conditions. Test results show that the developed harmonic synthesis technique can extract fault features effectively for initial IM air-gap eccentricity fault detection.

Initial evaluation of developmental malformation as an end point in mixture toxicity hazard assessment for aquatic vertebrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dawson, D.A.; Wilke, T.S.

1991-04-01

The joint toxic action of three binary mixtures was determined for the embryo malformation endpoint of the aquatic FETAX (frog embryo teratogenesis assay: Xenopus) test system. Osteolathyrogenic compounds and short-chain carboxylic acids, representing separate, distinct modes of action for induction of malformation, were selected for testing in 96-hr, static-renewal tests. Three mixtures were tested for each combination, with each combination being tested on three separate occasions. Using toxic unit analysis, the combination of osteolathyrogens and the combination of carboxylic acids produced strictly additive (concentration addition) rates of malformation, while the combination of an osteolathyrogen and a carboxylic acid was less-than-additivemore » (response addition) for induction of malformation. Therefore, developmental malformation may have value as an endpoint in mixture toxicity hazard assessment.« less

First Stage of a Highly Reliable Reusable Launch System

NASA Technical Reports Server (NTRS)

Kloesel, Kurt J.; Pickrel, Jonathan B.; Sayles, Emily L.; Wright, Michael; Marriott, Darin; Holland, Leo; Kuznetsov, Stephen

2009-01-01

Electromagnetic launch assist has the potential to provide a highly reliable reusable first stage to a space access system infrastructure at a lower overall cost. This paper explores the benefits of a smaller system that adds the advantages of a high specific impulse air-breathing stage and supersonic launch speeds. The method of virtual specific impulse is introduced as a tool to emphasize the gains afforded by launch assist. Analysis shows launch assist can provide a 278-s virtual specific impulse for a first-stage solid rocket. Additional trajectory analysis demonstrates that a system composed of a launch-assisted first-stage ramjet plus a bipropellant second stage can provide a 48-percent gross lift-off weight reduction versus an all-rocket system. The combination of high-speed linear induction motors and ramjets is identified, as the enabling technologies and benchtop prototypes are investigated. The high-speed response of a standard 60 Hz linear induction motor was tested with a pulse width modulated variable frequency drive to 150 Hz using a 10-lb load, achieving 150 mph. A 300-Hz stator-compensated linear induction motor was constructed and static-tested to 1900 lbf average. A matching ramjet design was developed for use on the 300-Hz linear induction motor.

Method and Circuit for Injecting a Precise Amount of Charge onto a Circuit Node

NASA Technical Reports Server (NTRS)

Hancock, Bruce R. (Inventor)

2016-01-01

A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

PubMed

Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

2015-10-01

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

Ocean Magnetics: 1. Fundamental Survey and Estimates of Induction Phenomena

DTIC Science & Technology

1977-10-01

sensitivities of /i0-• /Hz only in the far infra - sonic regime. We may note that, for a noise souce at great distances (R) such that its radiation...Various Ocean Depths (D), Pycnocline Depths (d), and Density Changes (6p/p), Sonic Mode (0), with IW Truncated at Brunt-Vaisala Frequency for aJ 25-m...Changes (6p/p), Sonic Mode MQ, with 1WI ~Truncated at Brunt Vaisala Frequency for a 25-rn-Thick Pycnocline.I Dashed line separates quasi-static (left

Measurements of temperature and pressure fluctuations in the T prime 2 cryogenic wind tunnel

NASA Technical Reports Server (NTRS)

Blanchard, A.; Dor, J. B.; Breil, J. F.

1980-01-01

Cold wire measurement of temperature fluctuations were made in a DERAT T'2 induction powered cryogenic wind tunnel for 2 types of liquid nitrogen injectors. Thermal turbulence measured in the tranquilization chamber depends to a great extent on the injector used; for fine spray of nitrogen drops, this level of turbulence seemed completely acceptable. Fluctuations in static pressure taken from the walls of the vein by Kulite sensors showed that there was no increase in aerodynamic noise during cryogenic gusts.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

Graphene-based flexible and stretchable thin film transistors.

PubMed

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

Micro-power dissipation device described

NASA Astrophysics Data System (ADS)

Mao, X.; Zhou, L.; Zhou, J.

1985-11-01

The common-emitter current gain beta of a common two-pole transistor is generally below 250. They are referred to as high-beta or high gain transistors when the beta of such transistors exceeds 300. When the beta of a transistor is higher than 1,000, it is called a super-beta transistor (SBT) or supergain transistor. The micropower dissipation type has the widest applications among the high-beta. Micropower dissipation high-beta means that there is a high gain or a superhigh gain under a microcurrent. The device is widely used in small signal-detection systems and stereo audio equipment because of their characteristics of high gain, low frequency and low noise under small signals.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

DTIC Science & Technology

2014-06-19

PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Evan R. Kemp, Ctr...United States. AFIT-ENP-T-14-J-39 PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Presented to...PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS Evan R. Kemp, BS Ctr, USAF Approved: // Signed

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 2

NASA Technical Reports Server (NTRS)

Lee, F. C.; Chen, D. Y.; Jovanic, M.; Hopkins, D. C.

1985-01-01

Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

PubMed Central

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-01-01

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development. PMID:28350370

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording.

PubMed

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-03-28

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

Copper atomic-scale transistors.

PubMed

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

PubMed

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizingmore » controllable high-performance stable transistors.« less

Copper atomic-scale transistors

PubMed Central

Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors. PMID:28382242

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

Thermo-piezo-electro-mechanical simulation of AlGaN (aluminum gallium nitride) / GaN (gallium nitride) High Electron Mobility Transistors

NASA Astrophysics Data System (ADS)

Stevens, Lorin E.

Due to the current public demand of faster, more powerful, and more reliable electronic devices, research is prolific these days in the area of high electron mobility transistor (HEMT) devices. This is because of their usefulness in RF (radio frequency) and microwave power amplifier applications including microwave vacuum tubes, cellular and personal communications services, and widespread broadband access. Although electrical transistor research has been ongoing since its inception in 1947, the transistor itself continues to evolve and improve much in part because of the many driven researchers and scientists throughout the world who are pushing the limits of what modern electronic devices can do. The purpose of the research outlined in this paper was to better understand the mechanical stresses and strains that are present in a hybrid AlGaN (Aluminum Gallium Nitride) / GaN (Gallium Nitride) HEMT, while under electrically-active conditions. One of the main issues currently being researched in these devices is their reliability, or their consistent ability to function properly, when subjected to high-power conditions. The researchers of this mechanical study have performed a static (i.e. frequency-independent) reliability analysis using powerful multiphysics computer modeling/simulation to get a better idea of what can cause failure in these devices. Because HEMT transistors are so small (micro/nano-sized), obtaining experimental measurements of stresses and strains during the active operation of these devices is extremely challenging. Physical mechanisms that cause stress/strain in these structures include thermo-structural phenomena due to mismatch in both coefficient of thermal expansion (CTE) and mechanical stiffness between different materials, as well as stress/strain caused by "piezoelectric" effects (i.e. mechanical deformation caused by an electric field, and conversely voltage induced by mechanical stress) in the AlGaN and GaN device portions (both piezoelectric materials). This piezoelectric effect can be triggered by voltage applied to the device's gate contact and the existence of an HEMT-unique "two-dimensional electron gas" (2DEG) at the GaN-AlGaN interface. COMSOL Multiphysics computer software has been utilized to create a finite element (i.e. piece-by-piece) simulation to visualize both temperature and stress/strain distributions that can occur in the device, by coupling together (i.e. solving simultaneously) the thermal, electrical, structural, and piezoelectric effects inherent in the device. The 2DEG has been modeled not with the typically-used self-consistent quantum physics analytical equations, rather as a combined localized heat source* (thermal) and surface charge density* (electrical) boundary condition. Critical values of stress/strain and their respective locations in the device have been identified. Failure locations have been estimated based on the critical values of stress and strain, and compared with reports in literature. The knowledge of the overall stress/strain distribution has assisted in determining the likely device failure mechanisms and possible mitigation approaches. The contribution and interaction of individual stress mechanisms including piezoelectric effects and thermal expansion caused by device self-heating (i.e. fast-moving electrons causing heat) have been quantified. * Values taken from results of experimental studies in literature.

Research on design feasibility of high-power light-weight dc-to-dc converters for space power applications

NASA Technical Reports Server (NTRS)

Wilson, T. G.

1981-01-01

Utilizing knowledge gained from past experience with experimental current-or-voltage step-up dc-to-dc converter power stages operating at output powers up to and in excess of 2 kW, a new experimental current-or-voltage step-up power stage using paralleled bipolar junction transistors (BJTs) as the controlled power switch, was constructed during the current reporting period. The major motivation behind the construction of this new experimental power stage was to improve the circuit layout so as to reduce the effects of stray circuit parasitic inductances resulting from excess circuit lead lengths and circuit loops, and to take advantage of the layout improvements which could be made when some recently-available power components, particularly power diodes and polypropylene filter capacitors, were incorporated into the design.

Wireless Passive Stimulation of Engineered Cardiac Tissues.

PubMed

Liu, Shiyi; Navaei, Ali; Meng, Xueling; Nikkhah, Mehdi; Chae, Junseok

2017-07-28

We present a battery-free radio frequency (RF) microwave activated wireless stimulator, 25 × 42 × 1.6 mm 3 on a flexible substrate, featuring high current delivery, up to 60 mA, to stimulate engineered cardiac tissues. An external antenna shines 2.4 GHz microwave, which is modulated by an inverted pulse to directly control the stimulating waveform, to the wireless passive stimulator. The stimulator is equipped with an on-board antenna, multistage diode multipliers, and a control transistor. Rat cardiomyocytes, seeded on electrically conductive gelatin-based hydrogels, demonstrate synchronous contractions and Ca 2+ transients immediately upon stimulation. Notably, the stimulator output voltage and current profiles match the tissue contraction frequency within 0.5-2 Hz. Overall, our results indicate the promising potential of the proposed wireless passive stimulator for cardiac stimulation and therapy by induction of precisely controlled and synchronous contractions.

ac propulsion system for an electric vehicle

NASA Technical Reports Server (NTRS)

Geppert, S.

1980-01-01

It is pointed out that dc drives will be the logical choice for current production electric vehicles (EV). However, by the mid-80's, there is a good chance that the price and reliability of suitable high-power semiconductors will allow for a competitive ac system. The driving force behind the ac approach is the induction motor, which has specific advantages relative to a dc shunt or series traction motor. These advantages would be an important factor in the case of a vehicle for which low maintenance characteristics are of primary importance. A description of an EV ac propulsion system is provided, taking into account the logic controller, the inverter, the motor, and a two-speed transmission-differential-axle assembly. The main barrier to the employment of the considered propulsion system in EV is not any technical problem, but inverter transistor cost.

Joule-Thief Circuit Performance for Electricity Energy Saving of Emergency Lamps

NASA Astrophysics Data System (ADS)

Nuryanto Budisusila, Eka; Arifin, Bustanul

2017-04-01

The alternative energy such as battery as power source is required as energy source failures. The other need is outdoor lighting. The electrical power source is expected to be a power saving, optimum and has long life operating. The Joule-Thief circuit is one of solution method for energy saving by using raised electromagnetic force on cored coil when there is back-current. This circuit has a transistor operated as a switch to cut voltage and current flowing along the coils. The present of current causing magnetic induction and generates energy. Experimental prototype was designed by using battery 1.5V to activate Light Emitting Diode or LED as load. The LED was connected in parallel or serial circuit configuration. The result show that the joule-thief circuit able to supply LED circuits up to 40 LEDs.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

High voltage power transistor development

NASA Technical Reports Server (NTRS)

Hower, P. L.

1981-01-01

Design considerations, fabrication procedures, and methods of evaluation for high-voltage power-transistor development are discussed. Technique improvements such as controlling the electric field at the surface and perserving lifetimes in the collector region which have advanced the state of the art in high-voltage transistors are discussed. These improvements can be applied directly to the development of 1200 volt, 200 ampere transistors.

Metal Oxide Silicon /MOS/ transistors protected from destructive damage by wire

NASA Technical Reports Server (NTRS)

Deboo, G. J.; Devine, E. J.

1966-01-01

Loop of flexible, small diameter, nickel wire protects metal oxide silicon /MOS/ transistors from a damaging electrostatic potential. The wire is attached to a music-wire spring, slipped over the MOS transistor case, and released so the spring tensions the wire loop around all the transistor leads, shorting them together. This allows handling without danger of damage.

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2011 CFR

2011-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2012 CFR

2012-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2014 CFR

2014-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2013 CFR

2013-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2010 CFR

2010-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Enhanced Amplification and Fan-Out Operation in an All-Magnetic Transistor

PubMed Central

Barman, Saswati; Saha, Susmita; Mondal, Sucheta; Kumar, Dheeraj; Barman, Anjan

2016-01-01

Development of all-magnetic transistor with favorable properties is an important step towards a new paradigm of all-magnetic computation. Recently, we showed such possibility in a Magnetic Vortex Transistor (MVT). Here, we demonstrate enhanced amplification in MVT achieved by introducing geometrical asymmetry in a three vortex sequence. The resulting asymmetry in core to core distance in the three vortex sequence led to enhanced amplification of the MVT output. A cascade of antivortices travelling in different trajectories including a nearly elliptical trajectory through the dynamic stray field is found to be responsible for this amplification. This asymmetric vortex transistor is further used for a successful fan-out operation, which gives large and nearly equal gains in two output branches. This large amplification in magnetic vortex gyration in magnetic vortex transistor is proposed to be maintained for a network of vortex transistor. The above observations promote the magnetic vortex transistors to be used in complex circuits and logic operations. PMID:27624662

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

PubMed

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

PubMed

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Universal power transistor base drive control unit

DOEpatents

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Universal power transistor base drive control unit

DOEpatents

Gale, A.R.; Gritter, D.J.

1988-06-07

A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

Magnetic nanoparticles stimulation to enhance liquid-liquid two-phase mass transfer under static and rotating magnetic fields

NASA Astrophysics Data System (ADS)

Azimi, Neda; Rahimi, Masoud

2017-01-01

Rotating magnetic field (RMF) was applied on a micromixer to break the laminar flow and induce chaotic flow to enhance mass transfer between two-immiscible organic and aqueous phases. The results of RMF were compared to those of static magnetic field (SMF). For this purpose, experiments were carried out in a T-micromixer at equal volumetric flow rates of organic and aqueous phases. Fe3O4 nanoparticles were synthesized by co-precipitation technique and they were dissolved in organic phase. Results obtained from RMF and SMF were compared in terms of overall volumetric mass transfer coefficient (KLa) and extraction efficiency (E) at various Reynolds numbers. Generally, RMF showed higher effect in mass transfer characteristics enhancement compared with SMF. The influence of rotational speeds of magnets (ω) in RMF was investigated, and measurable enhancements of KLa and E were observed. In RMF, the effect of magnetic field induction (B) was investigated. The results reveal that at constant concentration of nanoparticles, by increasing of B, mass transfer characteristics will be enhanced. The effect of various nanoparticles concentrations (ϕ) within 0.002-0.01 (w/v) on KLa and E at maximum induction of RMF (B=76 mT) was evaluated. Maximum values of KLa (2.1±0.001) and E (0.884±0.001) were achieved for the layout of RMF (B=76 mT), ω=16 rad/s and MNPs concentration of 0.008-0.01 (w/v).

Phosphorus doped graphene by inductively coupled plasma and triphenylphosphine treatments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shin, Dong-Wook, E-mail: shindong37@skku.edu; Kim, Tae Sung; Yoo, Ji-Beom, E-mail: jbyoo@skku.edu

Highlights: • Substitution doping is a promising method for opening the energy band gap of graphene. • Substitution doping with phosphorus in the graphene lattice has numerous advantage such as high band gap, low formation energy, and high net charge density compared to nitrogen. • V{sub dirac} of Inductively coupled plasma (ICP) and triphenylphosphine (TPP) treated graphene was −57 V, which provided clear evidence of n-type doping. • Substitutional doping of graphene with phosphorus is verified by the XPS spectra of P 2p core level and EELS mapping of phosphorus. • The chemical bonding between P and graphene is verymore » stable for a long time in air (2 months). - Abstract: Graphene is considered a host material for various applications in next-generation electronic devices. However, despite its excellent properties, one of the most important issues to be solved as an electronic material is the creation of an energy band gap. Substitution doping is a promising method for opening the energy band gap of graphene. Herein, we demonstrate the substitutional doping of graphene with phosphorus using inductively coupled plasma (ICP) and triphenylphosphine (TPP) treatments. The electrical transfer characteristics of the phosphorus doped graphene field effect transistor (GFET) have a V{sub dirac} of ∼ − 54 V. The chemical bonding between P and C was clearly observed in XPS spectra, and uniform distribution of phosphorus within graphene domains was confirmed by EELS mapping. The capability for substitutional doping of graphene with phosphorus can significantly promote the development of graphene based electronic devices.« less

Transistor-based filter for inhibiting load noise from entering a power supply

DOEpatents

Taubman, Matthew S

2013-07-02

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

Transistor-based filter for inhibiting load noise from entering a power supply

DOEpatents

Taubman, Matthew S

2015-02-24

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

Transistor circuit increases range of logarithmic current amplifier

NASA Technical Reports Server (NTRS)

Gilmour, G.

1966-01-01

Circuit increases the range of a logarithmic current amplifier by combining a commercially available amplifier with a silicon epitaxial transistor. A temperature compensating network is provided for the transistor.

Magnetoacoustic Tomography with Magnetic Induction: Bioimepedance reconstruction through vector source imaging

PubMed Central

Mariappan, Leo; He, Bin

2013-01-01

Magneto acoustic tomography with magnetic induction (MAT-MI) is a technique proposed to reconstruct the conductivity distribution in biological tissue at ultrasound imaging resolution. A magnetic pulse is used to generate eddy currents in the object, which in the presence of a static magnetic field induces Lorentz force based acoustic waves in the medium. This time resolved acoustic waves are collected with ultrasound transducers and, in the present work, these are used to reconstruct the current source which gives rise to the MAT-MI acoustic signal using vector imaging point spread functions. The reconstructed source is then used to estimate the conductivity distribution of the object. Computer simulations and phantom experiments are performed to demonstrate conductivity reconstruction through vector source imaging in a circular scanning geometry with a limited bandwidth finite size piston transducer. The results demonstrate that the MAT-MI approach is capable of conductivity reconstruction in a physical setting. PMID:23322761

Inductively guided circuits for ultracold dressed atoms

PubMed Central

Sinuco-León, German A.; Burrows, Kathryn A.; Arnold, Aidan S.; Garraway, Barry M.

2014-01-01

Recent progress in optics, atomic physics and material science has paved the way to study quantum effects in ultracold atomic alkali gases confined to non-trivial geometries. Multiply connected traps for cold atoms can be prepared by combining inhomogeneous distributions of DC and radio-frequency electromagnetic fields with optical fields that require complex systems for frequency control and stabilization. Here we propose a flexible and robust scheme that creates closed quasi-one-dimensional guides for ultracold atoms through the ‘dressing’ of hyperfine sublevels of the atomic ground state, where the dressing field is spatially modulated by inductive effects over a micro-engineered conducting loop. Remarkably, for commonly used atomic species (for example, 7Li and 87Rb), the guide operation relies entirely on controlling static and low-frequency fields in the regimes of radio-frequency and microwave frequencies. This novel trapping scheme can be implemented with current technology for micro-fabrication and electronic control. PMID:25348163

Application of the Johnson criteria to graphene transistors

NASA Astrophysics Data System (ADS)

Kelly, M. J.

2013-12-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications.

Assessment of Phospohrene Field Effect Transistors

DTIC Science & Technology

2018-01-28

electronics industry. To this end, transistor test structures would initially be fabricated on phosphorene exfoliated from black phosphorus and, later, on...34Phosphorene FETs-Promising Transistors Based on a few Layers of Phosphorus Atoms," Nanjing Electronic Devices Institute, Nanjing, China, Jul. 2015...OH, Nov. 2015. J.C. M. Hwang, "Phosphorene Transistors-Transient or Lasting Electronics ?" Workshop Frontier Electronics , San Juan, PR, Dec. 2015

Subtractive Plasma-Assisted-Etch Process for Developing High Performance Nanocrystalline Zinc-Oxide Thin-Film-Transistors

DTIC Science & Technology

2015-03-26

THIN - FILM - TRANSISTORS THESIS Thomas M. Donigan, First Lieutenant, USAF AFIT-ENG-MS-15-M-027 DEPARTMENT OF THE AIR FORCE AIR UNIVERSITY AIR...DEVELOPING HIGH PERFORMANCE NANOCRYSTALLINE ZINC-OXIDE THIN - FILM - TRANSISTORS THESIS Presented to the Faculty Department of Electrical and...15-M-027 SUBTRACTIVE PLASMA-ASSISTED-ETCH PROCESS FOR DEVELOPING HIGH PERFORMANCE NANOCRYSTALLINE ZINC-OXIDE THIN - FILM - TRANSISTORS

Oxide Based Transistor for Flexible Displays

DTIC Science & Technology

2014-09-15

thin film transistors (TFTs) for next generation display technologies. A detailed and comprehensive study was carried out to ascertain the process...Box 12211 Research Triangle Park, NC 27709-2211 Thin film transistors , flexible electronics, RF sputtering, Transparent amorphous oxide semiconductors...NC A&T and RTI, International investigated In free GaSnZnO (GSZO) material system, as the active channel in thin film transistors (TFTs) for next

Coaxial inverted geometry transistor having buried emitter

NASA Technical Reports Server (NTRS)

Hruby, R. J.; Cress, S. B.; Dunn, W. R. (Inventor)

1973-01-01

The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

Transistor Laser Optical NOR Gate for High Speed Optical Logic Processors

DTIC Science & Technology

2017-03-20

proposes an optical bistable latch can be built with two universal photonic NOR gate circuits, which are implemented by the three-port tunneling ... Tunneling Junction Transistor Laser (TJ-TL); Optical NOR Gate. Introduction To fulfill the future national security and intelligence needs in this...two-terminal diode lasers. Three-Port Transistor Laser – an Integration of Quantum-Wells into Heterojunction Bipolar Transistor Different than

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

PRESSURE TRANSDUCER

DOEpatents

Sander, H.H.

1959-10-01

A pressure or mechanical force transducer particularly adaptable to miniature telemetering systems is described. Basically the device consists of a transistor located within a magnetic field adapted to change in response to mechanical force. The conduction characteristics of the transistor in turn vary proportionally with changes in the magnetic flux across the transistor such that the output (either frequency of amplitude) of the transistor circuit is proportional to mechanical force or pressure.

2.3-MW Medium-Voltage, Three-Level Wind Energy Inverter Applying a Unique Bus Structure and 4.5-kV Si/SiC Hybrid Isolated Power Modules: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Erdman, W.; Keller, J.; Grider, D.

A high-efficiency, 2.3-MW, medium-voltage, three-level inverter utilizing 4.5-kV Si/SiC (silicon carbide) hybrid modules for wind energy applications is discussed. The inverter addresses recent trends in siting the inverter within the base of multimegawatt turbine towers. A simplified split, three-layer laminated bus structure that maintains low parasitic inductances is introduced along with a low-voltage, high-current test method for determining these inductances. Feed-thru bushings, edge fill methods, and other design features of the laminated bus structure provide voltage isolation that is consistent with the 10.4-kV module isolation levels. Inverter efficiency improvement is a result of the (essential) elimination of the reverse recoverymore » charge present in 4.5-kV Si PIN diodes, which can produce a significant reduction in diode turn-off losses as well as insulated-gate bipolar transistor (IGBT) turn-on losses. The hybrid modules are supplied in industry-standard 140 mm x 130 mm and 190 mm x 130 mm packages to demonstrate direct module substitution into existing inverter designs. A focus on laminated bus/capacitor-bank/module subassembly level switching performance is presented.« less

Towards Terabit Memories

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet little data on their energy/b. As a read-out memory with unparalleled retention and lifetime, the ROM with electron-beam direct-write-lithography (Chap. 8) should be considered for its projected 2D density of 250 Gb/cm², a very small read energy of 0.1 μW/Gb/s. The lithography write-speed 10 ms/Terabit makes this ROM a serious contentender for the optimum in non-volatile, tamper-proof storage.

Boron nitride housing cools transistors

NASA Technical Reports Server (NTRS)

1965-01-01

Boron nitride ceramic heat sink cools transistors in r-f transmitter and receiver circuits. Heat dissipated by the transistor is conducted by the boron nitride housing to the metal chassis on which it is mounted.

Current sensing circuit

NASA Technical Reports Server (NTRS)

Franke, Ralph J. (Inventor)

1996-01-01

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Three dimensional-stacked complementary thin-film transistors using n-type Al:ZnO and p-type NiO thin-film transistors.

PubMed

Lee, Ching-Ting; Chen, Chia-Chi; Lee, Hsin-Ying

2018-03-05

The three dimensional inverters were fabricated using novel complementary structure of stacked bottom n-type aluminum-doped zinc oxide (Al:ZnO) thin-film transistor and top p-type nickel oxide (NiO) thin-film transistor. When the inverter operated at the direct voltage (V DD ) of 10 V and the input voltage from 0 V to 10 V, the obtained high performances included the output swing of 9.9 V, the high noise margin of 2.7 V, and the low noise margin of 2.2 V. Furthermore, the high performances of unskenwed inverter were demonstrated by using the novel complementary structure of the stacked n-type Al:ZnO thin-film transistor and p-type nickel oxide (NiO) thin-film transistor.

Tunable organic transistors that use microfluidic source and drain electrodes

NASA Astrophysics Data System (ADS)

Maltezos, George; Nortrup, Robert; Jeon, Seokwoo; Zaumseil, Jana; Rogers, John A.

2003-09-01

This letter describes a type of transistor that uses conducting fluidic source and drain electrodes of mercury which flow on top of a thin film of the organic semiconductor pentacene. Pumping the mercury through suitably designed microchannels changes the width of the transistor channel and, therefore, the electrical characteristics of the device. Measurements on transistors with a range of channel lengths reveal low contact resistances between mercury and pentacene. Data collected before, during, and after pumping the mercury through the microchannels demonstrate reversible and systematic tuning of the devices. This unusual type of organic transistor has the potential to be useful in plastic microfluidic devices that require active elements for pumps, sensors, or other components. It also represents a noninvasive way to build transistor test structures that incorporate certain classes of chemically and mechanically fragile organic semiconductors.

Apparatus and method for recharging a string a avalanche transistors within a pulse generator

DOEpatents

Fulkerson, E. Stephen

2000-01-01

An apparatus and method for recharging a string of avalanche transistors within a pulse generator is disclosed. A plurality of amplification stages are connected in series. Each stage includes an avalanche transistor and a capacitor. A trigger signal, causes the apparatus to generate a very high voltage pulse of a very brief duration which discharges the capacitors. Charge resistors inject current into the string of avalanche transistors at various points, recharging the capacitors. The method of the present invention includes the steps of supplying current to charge resistors from a power supply; using the charge resistors to charge capacitors connected to a set of serially connected avalanche transistors; triggering the avalanche transistors; generating a high-voltage pulse from the charge stored in the capacitors; and recharging the capacitors through the charge resistors.

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

p-Type Transparent Electronics

DTIC Science & Technology

2003-09-25

thin - film transistors (TTFTs) reported to date in the literature are summarized. 2.2.1 Thin - Film Transistor Structure and Fabrication A TFT ...is incapable of controlling the TFT regardless of gate voltage, as described in Sec. 2.2.3.1. 2.2.4 Transparent Thin - Film Transistors (TTFTs...Transparent thin - film transistors (TTFTs) described in the literature to date are all n-channel devices. Several n-channel TTFTs (n-TTFTs) based on

Theory and Device Modeling for Nano-Structured Transistor Channels

DTIC Science & Technology

2011-06-01

zinc oxide ( ZnO ) thin film transistors ( TFTs ) that contain nanocrystalline grains on the order of ~20nm. The authors of ref. 1 present results...problem in order to determine the threshold voltage. 15. SUBJECT TERMS nano-structured transistor , mesoscopic, zinc oxide , ZnO , field-effect...and R. Neidhard, “Microwave ZnO Thin - Film Transistors ”, IEEE Electron Dev. Lett. 29, 1024 (2008); doi: 10.1109/LED.2008.2001635.

AlGaSb Buffer Layers for Sb-Based Transistors

DTIC Science & Technology

2010-01-01

transistor ( HEMT ), molecular beam epitaxy (MBE), field-effect transistor (FET), buffer layer INTRODUCTION High-electron-mobility transistors ( HEMTs ) with InAs...monolayers/s. The use of thinner buffer layers reduces molecular beam epitaxial growth time and source consumption. The buffer layers also exhibit...source. In addition, some of the flux from an Sb cell in a molecular beam epitaxy (MBE) system will deposit near the mouth of the cell, eventually

Photonic transistor and router using a single quantum-dot-confined spin in a single-sided optical microcavity

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2017-03-01

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic transistor that forms the basis of modern electronics. In sharp contrast to previous all-optical tran-sistors which are all based on optical nonlinearities, here I introduce a novel design for a high-gain and high-speed (up to terahertz) photonic transistor and its counterpart in the quantum limit, i.e., single-photon transistor based on a linear optical effect: giant Faraday rotation induced by a single electronic spin in a single-sided optical microcavity. A single-photon or classical optical pulse as the gate sets the spin state via projective measurement and controls the polarization of a strong light to open/block the photonic channel. Due to the duality as quantum gate for quantum information processing and transistor for optical information processing, this versatile spin-cavity quantum transistor provides a solid-state platform ideal for all-optical networks and quantum networks.

Photonic transistor and router using a single quantum-dot-confined spin in a single-sided optical microcavity

PubMed Central

Hu, C. Y.

2017-01-01

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic transistor that forms the basis of modern electronics. In sharp contrast to previous all-optical tran-sistors which are all based on optical nonlinearities, here I introduce a novel design for a high-gain and high-speed (up to terahertz) photonic transistor and its counterpart in the quantum limit, i.e., single-photon transistor based on a linear optical effect: giant Faraday rotation induced by a single electronic spin in a single-sided optical microcavity. A single-photon or classical optical pulse as the gate sets the spin state via projective measurement and controls the polarization of a strong light to open/block the photonic channel. Due to the duality as quantum gate for quantum information processing and transistor for optical information processing, this versatile spin-cavity quantum transistor provides a solid-state platform ideal for all-optical networks and quantum networks. PMID:28349960

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Npn double heterostructure bipolar transistor with ingaasn base region

DOEpatents

Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.

2004-07-20

An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Magnetoacoustic Tomography with Magnetic Induction (MAT-MI) for Imaging Electrical Conductivity of Biological Tissue: A Tutorial Review

PubMed Central

Li, Xu; Yu, Kai; He, Bin

2016-01-01

Magnetoacoustic tomography with magnetic induction (MAT-MI) is a noninvasive imaging method developed to map electrical conductivity of biological tissue with millimeter level spatial resolution. In MAT-MI, a time-varying magnetic stimulation is applied to induce eddy current inside the conductive tissue sample. With the existence of a static magnetic field, the Lorentz force acting on the induced eddy current drives mechanical vibrations producing detectable ultrasound signals. These ultrasound signals can then be acquired to reconstruct a map related to the sample’s electrical conductivity contrast. This work reviews fundamental ideas of MAT-MI and major techniques developed in these years. First, the physical mechanisms underlying MAT-MI imaging are described including the magnetic induction and Lorentz force induced acoustic wave propagation. Second, experimental setups and various imaging strategies for MAT-MI are reviewed and compared together with the corresponding experimental results. In addition, as a recently developed reverse mode of MAT-MI, magneto-acousto-electrical tomography with magnetic induction (MAET-MI) is briefly reviewed in terms of its theory and experimental studies. Finally, we give our opinions on existing challenges and future directions for MAT-MI research. With all the reported and future technical advancement, MAT-MI has the potential to become an important noninvasive modality for electrical conductivity imaging of biological tissue. PMID:27542088

University Physics, Study Guide, Revised Edition

NASA Astrophysics Data System (ADS)

Benson, Harris

1996-01-01

Partial table of contents: Vectors. One-Dimensional Kinematics. Particle Dynamics II. Work and Energy. Linear Momentum. Systems of Particles. Angular Momentum and Statics. Gravitation. Solids and Fluids. Oscillations. Mechanical Waves. Sound. First Law of Thermodynamics. Kinetic Theory. Entropy and the Second Law of Thermodynamics. Electrostatics. The Electric Field. Gauss's Law. Electric Potential. Current and Resistance. The Magnetic Field. Sources of the Magnetic Field. Electromagnetic Induction. Light: Reflection and Refraction. Lenses and Optical Instruments. Wave Optics I. Special Relativity. Early Quantum Theory. Nuclear Physics. Appendices. Answers to Odd-Numbered Exercises and Problems. Index.

Composition and methods of preparation of target material for producing radionuclides

DOEpatents

Seropeghin, Yurii D; Zhuikov, Boris L

2013-05-28

A composition suitable for use as a target containing antimony to be irradiated by accelerated charged particles (e.g., by protons to produce tin-117m) comprises an intermetallic compound of antimony and titanium which is synthesized at high-temperature, for example, in an arc furnace. The formed material is powdered and melted in an induction furnace, or heated at high gas pressure in gas static camera. The obtained product has a density, temperature stability, and heat conductivity sufficient to provide an appropriate target material.

TRANSISTOR HIGH VOLTAGE POWER SUPPLY

DOEpatents

Driver, G.E.

1958-07-15

High voltage, direct current power supplies are described for use with battery powered nuclear detection equipment. The particular advantages of the power supply described, are increased efficiency and reduced size and welght brought about by the use of transistors in the circuit. An important feature resides tn the employment of a pair of transistors in an alternatefiring oscillator circuit having a coupling transformer and other circuit components which are used for interconnecting the various electrodes of the transistors.

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

Organic transistors manufactured using inkjet technology with subfemtoliter accuracy

PubMed Central

Sekitani, Tsuyoshi; Noguchi, Yoshiaki; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2008-01-01

A major obstacle to the development of organic transistors for large-area sensor, display, and circuit applications is the fundamental compromise between manufacturing efficiency, transistor performance, and power consumption. In the past, improving the manufacturing efficiency through the use of printing techniques has inevitably resulted in significantly lower performance and increased power consumption, while attempts to improve performance or reduce power have led to higher process temperatures and increased manufacturing cost. Here, we lift this fundamental limitation by demonstrating subfemtoliter inkjet printing to define metal contacts with single-micrometer resolution on the surface of high-mobility organic semiconductors to create high-performance p-channel and n-channel transistors and low-power complementary circuits. The transistors employ an ultrathin low-temperature gate dielectric based on a self-assembled monolayer that allows transistors and circuits on rigid and flexible substrates to operate with very low voltages. PMID:18362348

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Back bias induced dynamic and steep subthreshold swing in junctionless transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Parihar, Mukta Singh; Kranti, Abhinav, E-mail: akranti@iiti.ac.in

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of −0.9 V, achieves over 5 orders of change inmore » drain current at a gate overdrive of 200 mV and drain bias of 1 V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.« less

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

High-Performance Vertical Organic Electrochemical Transistors.

PubMed

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Statistically Modeling I-V Characteristics of CNT-FET with LASSO

NASA Astrophysics Data System (ADS)

Ma, Dongsheng; Ye, Zuochang; Wang, Yan

2017-08-01

With the advent of internet of things (IOT), the need for studying new material and devices for various applications is increasing. Traditionally we build compact models for transistors on the basis of physics. But physical models are expensive and need a very long time to adjust for non-ideal effects. As the vision for the application of many novel devices is not certain or the manufacture process is not mature, deriving generalized accurate physical models for such devices is very strenuous, whereas statistical modeling is becoming a potential method because of its data oriented property and fast implementation. In this paper, one classical statistical regression method, LASSO, is used to model the I-V characteristics of CNT-FET and a pseudo-PMOS inverter simulation based on the trained model is implemented in Cadence. The normalized relative mean square prediction error of the trained model versus experiment sample data and the simulation results show that the model is acceptable for digital circuit static simulation. And such modeling methodology can extend to general devices.

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2018-03-05

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10 -14 A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (10 7 ) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2018-03-01

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10-14A/μm) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (107) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

Tunable Quantum Dot Solids: Impact of Interparticle Interactions on Bulk Properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sinclair, Michael B.; Fan, Hongyou; Brener, Igal

2015-09-01

QD-solids comprising self-assembled semiconductor nanocrystals such as CdSe are currently under investigation for use in a wide array of applications including light emitting diodes, solar cells, field effect transistors, photodetectors, and biosensors. The goal of this LDRD project was develop a fundamental understanding of the relationship between nanoparticle interactions and the different regimes of charge and energy transport in semiconductor quantum dot (QD) solids. Interparticle spacing was tuned through the application of hydrostatic pressure in a diamond anvil cell, and the impact on interparticle interactions was probed using x-ray scattering and a variety of static and transient optical spectroscopies. Duringmore » the course of this LDRD, we discovered a new, previously unknown, route to synthesize semiconductor quantum wires using high pressure sintering of self-assembled quantum dot crystals. We believe that this new, pressure driven synthesis approach holds great potential as a new tool for nanomaterials synthesis and engineering.« less

Resonant and nondissipative tunneling in independently contacted graphene structures

NASA Astrophysics Data System (ADS)

Vasko, F. T.

2013-02-01

The tunneling processes between independently contacted graphene sheets separated by thin insulator are restricted by the momentum and energy conservation laws. Because of this, both dissipative tunneling transitions, with momentum transfer due to disorder scattering, and nondissipative regime of tunneling, which appears due to intersection of electron and hole branches of energy spectrum, must be taken into account. The tunneling current density is calculated for the graphene-boron nitride-graphene layers, which is described by the tight-binding approach, and for the predominant momentum scattering by static disorder. Dependencies of current on concentrations in top and bottom graphene layers, which are governed by the voltages applied through independent contacts and gates, are considered for the back- and double-gated structures. The current-voltage characteristics of the back-gated structure are in agreement with the recent experiment [ScienceSCIEAS0036-807510.1126/science.1218461 335, 947 (2012)]. For the double-gated structures, the resonant dissipative tunneling causes a 10-fold enhancement of response which is important for transistor applications.

Static ferroelectric memory transistor having improved data retention

DOEpatents

Evans, Jr., Joseph T.; Warren, William L.; Tuttle, Bruce A.

1996-01-01

An improved ferroelectric FET structure in which the ferroelectric layer is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer having first and second contacts thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode and a ferroelectric layer which is sandwiched between the semiconductor layer and the bottom electrode. The ferroelectric layer is constructed from a perovskite structure of the chemical composition ABO.sub.3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentrations between 1% and 8%.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Scanning Probe Microscopy and Electrical Transport Studies of Ferroelectric Thin Films and 2D van der Waals Materials

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong

In this dissertation, I present the scanning microscopy and electrical transport studies of ferroelectric thin films and ferroic/2D van der Waals heterostructures. Based on the conducting probe atomic force microscopy and piezo-response force microscopy (PFM) studies of the static and dynamic behavior of ferroelectric domain walls (DW), we found that the ferroelectric polymer poly(vinylidene-fluoride-trifluorethylene) P(VDF-TrFE) is composed of two-dimensional (2D) ferroelectric monolayers (MLs) that are weakly coupled to each other. We also observed polarization asymmetry in epitaxial thin films of ferroelectric Pb(Zr,Ti)O3, which is attributed to the screening properties of the underlying conducting oxide. PFM studies also reveal ferroelectric relaxor-type behavior in ultrathin Sr(Zr,Ti)O3 films epitaxially deposited on Ge. We exploited scanning-probe-controlled domain patterning in a P(VDF-TrFE) top layer to induce nonvolatile modulation of the conduction characteristic of ML molybdenum disulfide (MoS2) between a transistor and a junction state. In the presence of a DW, MoS2 exhibits rectified Ids-Vds (IV) characteristics that are well described by the thermionic emission model. This approach can be applied to a wide range of van der Waals materials to design various functional homojunctions and nanostructures. We also studied the interfacial charge transfer effect between graphene and magnetoelectric Cr2O3 via electrostatic force microscopy and Kelvin probe force microscopy, which reveal p-type doping with up to 150 meV shift of the Fermi level. The graphene/Cr2O3 heterostructure is promising for developing magnetoelectric graphene transistors for spintronic applications.

3D printed microfluidic circuitry via multijet-based additive manufacturing†

PubMed Central

Sochol, R. D.; Sweet, E.; Glick, C. C.; Venkatesh, S.; Avetisyan, A.; Ekman, K. F.; Raulinaitis, A.; Tsai, A.; Wienkers, A.; Korner, K.; Hanson, K.; Long, A.; Hightower, B. J.; Slatton, G.; Burnett, D. C.; Massey, T. L.; Iwai, K.; Lee, L. P.; Pister, K. S. J.; Lin, L.

2016-01-01

The miniaturization of integrated fluidic processors affords extensive benefits for chemical and biological fields, yet traditional, monolithic methods of microfabrication present numerous obstacles for the scaling of fluidic operators. Recently, researchers have investigated the use of additive manufacturing or “three-dimensional (3D) printing” technologies – predominantly stereolithography – as a promising alternative for the construction of submillimeter-scale fluidic components. One challenge, however, is that current stereolithography methods lack the ability to simultaneously print sacrificial support materials, which limits the geometric versatility of such approaches. In this work, we investigate the use of multijet modelling (alternatively, polyjet printing) – a layer-by-layer, multi-material inkjetting process – for 3D printing geometrically complex, yet functionally advantageous fluidic components comprised of both static and dynamic physical elements. We examine a fundamental class of 3D printed microfluidic operators, including fluidic capacitors, fluidic diodes, and fluidic transistors. In addition, we evaluate the potential to advance on-chip automation of integrated fluidic systems via geometric modification of component parameters. Theoretical and experimental results for 3D fluidic capacitors demonstrated that transitioning from planar to non-planar diaphragm architectures improved component performance. Flow rectification experiments for 3D printed fluidic diodes revealed a diodicity of 80.6 ± 1.8. Geometry-based gain enhancement for 3D printed fluidic transistors yielded pressure gain of 3.01 ± 0.78. Consistent with additional additive manufacturing methodologies, the use of digitally-transferrable 3D models of fluidic components combined with commercially-available 3D printers could extend the fluidic routing capabilities presented here to researchers in fields beyond the core engineering community. PMID:26725379

Failure rates for accelerated acceptance testing of silicon transistors

NASA Technical Reports Server (NTRS)

Toye, C. R.

1968-01-01

Extrapolation tables for the control of silicon transistor product reliability have been compiled. The tables are based on a version of the Arrhenius statistical relation and are intended to be used for low- and medium-power silicon transistors.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Current Source Logic Gate

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2017-01-01

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

Maskless writing of a flexible nanoscale transistor with Au-contacted carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Dockendorf, Cedric P. R.; Poulikakos, Dimos; Hwang, Gilgueng; Nelson, Bradley J.; Grigoropoulos, Costas P.

2007-12-01

A flexible polymer field effect transistor with a nanoscale carbon nanotube channel is conceptualized and realized herein. Carbon nanotubes (CNTs) were dispersed on a polyimide substrate and marked in an scanning electron microscope with focused ion beam such that they could be contacted with gold nanoink. The CNTs were divided into two parts forming the source and drain of the transistor. A micropipette writing method was used to contact the carbon nanotube electrodes with gold nanoink and to deposit the poly(3-hexylthiophene) as an active layer. The mobility of the transistors is of the order of 10-5cm/Vs. After fabrication, the flexible transistors can be peeled off the substrate.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Ripple gate drive circuit for fast operation of series connected IGBTs

DOEpatents

Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

2005-09-20

A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

Pentacene Organic Thin-Film Transistors on Flexible Paper and Glass Substrates

DTIC Science & Technology

2014-02-12

FEB 2014 2. REPORT TYPE 3. DATES COVERED 00-00-2014 to 00-00-2014 4. TITLE AND SUBTITLE Pentacene organic thin - film transistors on flexible...Nanotechnology 25 (2014) 094005 (7pp) doi:10.1088/0957-4484/25/9/094005 Pentacene organic thin - film transistors on flexible paper and glass substrates Adam T...organic thin - film transistors (OTFTs) were fabricated on several types of flexible substrate: commercial photo paper, ultra-smooth specialty paper and

Organic field effect transistor with ultra high amplification

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio

2016-09-01

High-gain transistors are essential for the large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show organic transistors fabricated on plastic foils enabling unipolar amplifiers with ultra-gain. The proposed approach is general and opens up new opportunities for ultra-large signal amplification in organic circuits and sensors.

Analytical design equations for self-tuned Class-E power amplifier.

PubMed

Hu, Zhe; Troyk, Philip

2011-01-01

For many emerging neural prosthesis designs that are powered by inductive coupling, their small physical size requires large current in the extracorporeal transmitter coil, and the Class-E power amplifier topology is often used for the transmitter design. Tuning of Class-E circuits for efficient operation is difficult and a self-tuned circuit can facilitate the tuning. The coil current is sensed and used to tune the switching of the transistor switch in the Class-E circuit in order to maintain its high-efficiency operation. Although mathematically complex, the analysis and design procedure for the self-tuned Class-E circuit can be simplified due to the current feedback control, which makes the phase angle between the switching pulse and the coil current predetermined. In this paper explicit analytical design equations are derived and a detailed design procedure is presented and compared with the conventional Class-E design approaches.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Potts, C.; Faber, M.; Gunderson, G.

The as-built lattice of the Rapid-Cycling Synchrotron (RCS) had two sets of correction sextupoles and two sets of quadrupoles energized by dc power supplies to control the tune and the tune tilt. With this method of powering these magnets, adjustment of tune conditions during the accelerating cycle as needed was not possible. A set of dynamically programmable power supplies has been built and operated to provide the required chromaticity adjustment. The short accelerating time (16.7 ms) of the RCS and the inductance of the magnets dictated large transistor amplifier power supplies. The required time resolution and waveform flexibility indicated themore » desirability of computer control. Both the amplifiers and controls are described, along with resulting improvements in the beam performance. A set of octupole magnets and programmable power supplies with similar dynamic qualities have been constructed and installed to control the anticipated high-intensity transverse instability. This system will be operational in the spring of 1981.« less

Extraction method of interfacial injected charges for SiC power MOSFETs

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Li, Sheng; Song, Haiyang; Chen, Xin; Li, Ting; Fang, Jiong; Sun, Weifeng

2018-01-01

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Large scale electromechanical transistor with application in mass sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Leisheng; Li, Lijie, E-mail: L.Li@swansea.ac.uk

Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to bemore » used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.« less

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Dual-mode operation of 2D material-base hot electron transistors

PubMed Central

Lan, Yann-Wen; Torres, Jr., Carlos M.; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications. PMID:27581550

Dual-mode operation of 2D material-base hot electron transistors.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Unified planar process for fabricating heterojunction bipolar transistors and buried-heterostructure lasers utilizing impurity-induced disordering

NASA Astrophysics Data System (ADS)

Thornton, R. L.; Mosby, W. J.; Chung, H. F.

1988-12-01

We describe results on a novel geometry of heterojunction bipolar transistor that has been realized by impurity-induced disordering. This structure is fabricated by a method that is compatible with techniques for the fabrication of low threshold current buried-heterostructure lasers. We have demonstrated this compatibility by fabricating a hybrid laser/transistor structure that operates as a laser with a threshold current of 6 mA at room temperature, and as a transistor with a current gain of 5.

The total switch time of silicon bipolar transistors with base doping gradients or with germanium gradients in the base

NASA Astrophysics Data System (ADS)

Karlsteen, M.; Willander, M.

1993-11-01

In this paper the total switch time for a transistor in a Direct Coupled Transistor Logic (DCTL) circuit is simulated by using Laplace transformations of the Ebers-Moll equations. The influence of doping gradients and germanium gradients in the base is investigated and their relative importance and their limitations are established. In a well designed bipolar transistor only a minor enhancement of the total switch time is obtained with the use of a doping gradient in the base. However, for bipolar transistors with base thickness over 500 Å, an improperly selected doping profile could be devastating for the total switch time. For a bipolar transistor the improvement of the total switch time due to a linear germanium gradient in the base could be up to about 30% compared with an ordinary silicon bipolar transistor. Still, a too high germanium gradient forces the normal transistor current gain (α N) to grow and the total switch time is thereby increased. Further enhancement could be achieved by the use of a second degree polynomial germanium profile in the base. Also in this case, care must be taken not to enlarge the germanium gradient too much as the total switch time then starts to increase. In all cases the betterment of the base transit time that is introduced by the electric field will not be directly used to reduce the base transit time. Instead the improvement is mostly used to lower the emitter transition charging time. However, the most important parameter to control is the normal transistor current gain (α N) that has to be kept within a narrow range to keep the total switch time low.

Influence on cell death of high frequency motion of magnetic nanoparticles during magnetic hyperthermia experiments

NASA Astrophysics Data System (ADS)

Hallali, N.; Clerc, P.; Fourmy, D.; Gigoux, V.; Carrey, J.

2016-07-01

Studies with transplanted tumors in animals and clinical trials have provided the proof-of-concept of magnetic hyperthermia (MH) therapy of cancers using iron oxide nanoparticles. Interestingly, in several studies, the application of an alternating magnetic field (AMF) to tumor cells having internalized and accumulated magnetic nanoparticles (MNPs) into their lysosomes can induce cell death without detectable temperature increase. To explain these results, among other hypotheses, it was proposed that cell death could be due to the high-frequency translational motion of MNPs under the influence of the AMF gradient generated involuntarily by most inductors. Such mechanical actions of MNPs might cause cellular damages and participate in the induction of cell death under MH conditions. To test this hypothesis, we developed a setup maximizing this effect. It is composed of an anti-Helmholtz coil and two permanent magnets, which produce an AMF gradient and a superimposed static MF. We have measured the MNP heating power and treated tumor cells by a standard AMF and by an AMF gradient, on which was added or not a static magnetic field. We showed that the presence of a static magnetic field prevents MNP heating and cell death in standard MH conditions. The heating power of MNPs in an AMF gradient is weak, position-dependent, and related to the presence of a non-zero AMF. Under an AMF gradient and a static field, no MNP heating and cell death were measured. Consequently, the hypothesis that translational motions could be involved in cell death during MH experiments is ruled out by our experiments.

Metal nanoparticle film-based room temperature Coulomb transistor.

PubMed

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity.

PubMed

Li, Jin-Jin; Zhu, Ka-Di

2011-02-04

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

N-Heterocyclic-Carbene-Treated Gold Surfaces in Pentacene Organic Field-Effect Transistors: Improved Stability and Contact at the Interface.

PubMed

Lv, Aifeng; Freitag, Matthias; Chepiga, Kathryn M; Schäfer, Andreas H; Glorius, Frank; Chi, Lifeng

2018-04-16

N-Heterocyclic carbenes (NHCs), which react with the surface of Au electrodes, have been successfully applied in pentacene transistors. With the application of NHCs, the charge-carrier mobility of pentacene transistors increased by five times, while the contact resistance at the pentacene-Au interface was reduced by 85 %. Even after annealing the NHC-Au electrodes at 200 °C for 2 h before pentacene deposition, the charge-carrier mobility of the pentacene transistors did not decrease. The distinguished performance makes NHCs as excellent alternatives to thiols as metal modifiers for the application in organic field-effect transistors (OFETs). © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Voltage controlled spintronic devices for logic applications

DOEpatents

You, Chun-Yeol; Bader, Samuel D.

2001-01-01

A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

Module failure isolation circuit for paralleled inverters. [preventing system failure during power conditioning for spacecraft applications

NASA Technical Reports Server (NTRS)

Nagano, S. (Inventor)

1979-01-01

A module failure isolation circuit is described which senses and averages the collector current of each paralled inverter power transistor and compares the collector current of each power transistor the average collector current of all power transistors to determine when the sensed collector current of a power transistor in any one inverter falls below a predetermined ratio of the average collector current. The module associated with any transistor that fails to maintain a current level above the predetermined radio of the average collector current is then shut off. A separate circuit detects when there is no load, or a light load, to inhibit operation of the isolation circuit during no load or light load conditions.

Specifics of Pulsed Arc Welding Power Supply Performance Based On A Transistor Switch

NASA Astrophysics Data System (ADS)

Krampit, N. Yu; Kust, T. S.; Krampit, M. A.

2016-08-01

Specifics of designing a pulsed arc welding power supply device are presented in the paper. Electronic components for managing large current was analyzed. Strengths and shortcomings of power supply circuits based on thyristor, bipolar transistor and MOSFET are outlined. As a base unit for pulsed arc welding was chosen MOSFET transistor, which is easy to manage. Measures to protect a transistor are given. As for the transistor control device is a microcontroller Arduino which has a low cost and adequate performance of the work. Bead transfer principle is to change the voltage on the arc in the formation of beads on the wire end. Microcontroller controls transistor when the arc voltage reaches the threshold voltage. Thus there is a separation and transfer of beads without splashing. Control strategies tested on a real device and presented. The error in the operation of the device is less than 25 us, it can be used controlling drop transfer at high frequencies (up to 1300 Hz).

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

PubMed

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Efficient generation of hepatic cells from mesenchymal stromal cells by an innovative bio-microfluidic cell culture device.

PubMed

Yen, Meng-Hua; Wu, Yuan-Yi; Liu, Yi-Shiuan; Rimando, Marilyn; Ho, Jennifer Hui-Chun; Lee, Oscar Kuang-Sheng

2016-08-19

Mesenchymal stromal cells (MSCs) are multipotent and have great potential in cell therapy. Previously we reported the differentiation potential of human MSCs into hepatocytes in vitro and that these cells can rescue fulminant hepatic failure. However, the conventional static culture method neither maintains growth factors at an optimal level constantly nor removes cellular waste efficiently. In addition, not only is the duration of differentiating hepatocyte lineage cells from MSCs required to improve, but also the need for a large number of hepatocytes for cell therapy has not to date been addressed fully. The purpose of this study is to design and develop an innovative microfluidic device to overcome these shortcomings. We designed and fabricated a microfluidic device and a culture system for hepatic differentiation of MSCs using our protocol reported previously. The microfluidic device contains a large culture chamber with a stable uniform flow to allow homogeneous distribution and expansion as well as efficient induction of hepatic differentiation for MSCs. The device enables real-time observation under light microscopy and exhibits a better differentiation efficiency for MSCs compared with conventional static culture. MSCs grown in the microfluidic device showed a higher level of hepatocyte marker gene expression under hepatic induction. Functional analysis of hepatic differentiation demonstrated significantly higher urea production in the microfluidic device after 21 days of hepatic differentiation. The microfluidic device allows the generation of a large number of MSCs and induces hepatic differentiation of MSCs efficiently. The device can be adapted for scale-up production of hepatic cells from MSCs for cellular therapy.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes.

PubMed

Cao, Xuan; Chen, Haitian; Gu, Xiaofei; Liu, Bilu; Wang, Wenli; Cao, Yu; Wu, Fanqi; Zhou, Chongwu

2014-12-23

Semiconducting single-wall carbon nanotubes are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible electronics. Nonetheless, developing scalable and low-cost approaches for manufacturing fully printed high-performance single-wall carbon nanotube thin-film transistors remains a major challenge. Here we report that screen printing, which is a simple, scalable, and cost-effective technique, can be used to produce both rigid and flexible thin-film transistors using separated single-wall carbon nanotubes. Our fully printed top-gated nanotube thin-film transistors on rigid and flexible substrates exhibit decent performance, with mobility up to 7.67 cm2 V(-1) s(-1), on/off ratio of 10(4)∼10(5), minimal hysteresis, and low operation voltage (<10 V). In addition, outstanding mechanical flexibility of printed nanotube thin-film transistors (bent with radius of curvature down to 3 mm) and driving capability for organic light-emitting diode have been demonstrated. Given the high performance of the fully screen-printed single-wall carbon nanotube thin-film transistors, we believe screen printing stands as a low-cost, scalable, and reliable approach to manufacture high-performance nanotube thin-film transistors for application in display electronics. Moreover, this technique may be used to fabricate thin-film transistors based on other materials for large-area flexible macroelectronics, and low-cost display electronics.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Silicon switching transistor with high power and low saturation voltage

NASA Technical Reports Server (NTRS)

Stonebraker, E.; Stoneburner, D.; Ferree, H.

1973-01-01

Assembly of two individually encapsulated silicon-chip transistors produces silicon power-transistor that has low electrical resistance and low thermal impedance. Electrical resistance and thermal impedance are low because of short lead lengths, and external contact surfaces are plated to reduce resistance at interfaces.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

NASA Technical Reports Server (NTRS)

Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

1981-01-01

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

Charge transport and trapping in organic field effect transistors exposed to polar analytes

NASA Astrophysics Data System (ADS)

Duarte, Davianne; Sharma, Deepak; Cobb, Brian; Dodabalapur, Ananth

2011-03-01

Pentacene based organic thin-film transistors were used to study the effects of polar analytes on charge transport and trapping behavior during vapor sensing. Three sets of devices with differing morphology and mobility (0.001-0.5 cm2/V s) were employed. All devices show enhanced trapping upon exposure to analyte molecules. The organic field effect transistors with different mobilities also provide evidence for morphology dependent partition coefficients. This study helps provide a physical basis for many reports on organic transistor based sensor response.

AlN/GaN heterostructures for normally-off transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Development and fabrication of improved power transistor switches

NASA Technical Reports Server (NTRS)

Hower, P. L.; Chu, C. K.

1979-01-01

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

Metal nanoparticle film–based room temperature Coulomb transistor

PubMed Central

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

PubMed

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Effect of mass concentration of composite phase change material CA-DE on HCFC-141b hydrate induction time and system stability

NASA Astrophysics Data System (ADS)

Li, Juan; Sun, Zhigao; Liu, Chenggang; Zhu, Minggui

2018-03-01

HCFC-141b hydrate is a new type of environment-friendly cold storage medium which may be adopted to balance energy supply and demand, achieve peak load shifting and energy saving, wherein the hydrate induction time and system stability are key factors to promote and realize its application in industrial practice. Based on step cooling curve measurement, two kinds of aliphatic hydrocarbon organics, n-capric acid (CA) and lauryl alcohol (DE), were selected to form composite phase change material and to promote the generation of HCFC-141b hydrate. Five kinds of CA-DE mass concentration were chosen to compare the induction time and hydration system stability. In order to accelerate temperature reduction rate, the metal Cu with high heat conductivity performance was adopted to conduct out the heat generated during phase change. Instability index was introduced to appraise system stability. Experimental results show that phase change temperature and sub-cooling degree of CA-DE is 11.1°C and 3.0°C respectively, which means it is a preferable medium for HCFC-141b hydrate formation. For the experimental hydration systems, segmented emulsification is achieved by special titration manner to avoid rapid layering under static condition. Induction time can achieve up to 23.3min with the densest HCFC-141b hydrate and the lowest instability index, wherein CA-DE mass concentration is 3%.

Laser singular Theta-pinch

NASA Astrophysics Data System (ADS)

Okulov, A. Yu.

2010-10-01

The interaction of the two counter-propagating ultrashort laser pulses with singular wavefronts in the thin slice of the underdense plasma is considered. It is shown that ion-acoustic wave is excited via Brillouin three-wave resonance by corkscrew interference pattern of paraxial singular laser beams. The orbital angular momentum carried by light is transferred to plasma ion-acoustic vortex. The rotation of the density perturbations of electron fluid is the cause of helical current which produces the kilogauss axial quasi-static magnetic field. The exact analytical configurations are presented for an ion-acoustic current field and magnetic induction. The range of experimentally accessible parameters is evaluated.

OP-AMPS on Flexible Substrates with Printable Materials

DTIC Science & Technology

2011-08-10

Zinc Tin Oxide Thin - Film - Transistor Enhancement...II196, 2010. [3] D. Geng, D. H. Kang, and J. Jang, "High-Performance Amorphous Indium-Gallium- Zinc - Oxide Thin - Film Transistor With a Self-Aligned...B., Dodabalapur, A., “Band transport and mobility edge in amorphous solution-processed zinc tin oxide thin - film transistors ”, Applied

E-Learning System for Design and Construction of Amplifier Using Transistors

ERIC Educational Resources Information Center

Takemura, Atsushi

2014-01-01

This paper proposes a novel e-Learning system for the comprehensive understanding of electronic circuits with transistors. The proposed e-Learning system allows users to learn a wide range of topics, encompassing circuit theories, design, construction, and measurement. Given the fact that the amplifiers with transistors are an integral part of…

Analysis of long-channel nanotube field-effect-transistors (NT FETs)

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Kwak, Dochan (Technical Monitor)

2001-01-01

This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).

Spin-based single-photon transistor, dynamic random access memory, diodes, and routers in semiconductors

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2016-12-01

The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect: giant circular birefringence induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet: a mixture of all-optical Internet with quantum Internet.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

High Accuracy Transistor Compact Model Calibrations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirementsmore » require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.« less

Hafnium transistor design for neural interfacing.

PubMed

Parent, David W; Basham, Eric J

2008-01-01

A design methodology is presented that uses the EKV model and the g(m)/I(D) biasing technique to design hafnium oxide field effect transistors that are suitable for neural recording circuitry. The DC gain of a common source amplifier is correlated to the structural properties of a Field Effect Transistor (FET) and a Metal Insulator Semiconductor (MIS) capacitor. This approach allows a transistor designer to use a design flow that starts with simple and intuitive 1-D equations for gain that can be verified in 1-D MIS capacitor TCAD simulations, before final TCAD process verification of transistor properties. The DC gain of a common source amplifier is optimized by using fast 1-D simulations and using slower, complex 2-D simulations only for verification. The 1-D equations are used to show that the increased dielectric constant of hafnium oxide allows a higher DC gain for a given oxide thickness. An additional benefit is that the MIS capacitor can be employed to test additional performance parameters important to an open gate transistor such as dielectric stability and ionic penetration.

Imperceptible and Ultraflexible p-Type Transistors and Macroelectronics Based on Carbon Nanotubes.

PubMed

Cao, Xuan; Cao, Yu; Zhou, Chongwu

2016-01-26

Flexible thin-film transistors based on semiconducting single-wall carbon nanotubes are promising for flexible digital circuits, artificial skins, radio frequency devices, active-matrix-based displays, and sensors due to the outstanding electrical properties and intrinsic mechanical strength of carbon nanotubes. Nevertheless, previous research effort only led to nanotube thin-film transistors with the smallest bending radius down to 1 mm. In this paper, we have realized the full potential of carbon nanotubes by making ultraflexible and imperceptible p-type transistors and circuits with a bending radius down to 40 μm. In addition, the resulted transistors show mobility up to 12.04 cm(2) V(-1) S(-1), high on-off ratio (∼10(6)), ultralight weight (<3 g/m(2)), and good mechanical robustness (accommodating severe crumpling and 67% compressive strain). Furthermore, the nanotube circuits can operate properly with 33% compressive strain. On the basis of the aforementioned features, our ultraflexible p-type nanotube transistors and circuits have great potential to work as indispensable components for ultraflexible complementary electronics.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

PubMed

Cao, Xuan; Wu, Fanqi; Lau, Christian; Liu, Yihang; Liu, Qingzhou; Zhou, Chongwu

2017-02-28

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼10 5 , low-voltage operation, and good mobility of ∼15.03 cm 2 V -1 s -1 . These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

Low-noise SQUID

DOEpatents

Dantsker, Eugene; Clarke, John

2000-01-01

The present invention comprises a high-transition-temperature superconducting device having low-magnitude low-frequency noise-characteristics in magnetic fields comprising superconducting films wherein the films have a width that is less than or equal to a critical width, w.sub.C, which depends on an ambient magnetic field. For operation in the Earth's magnetic field, the critical width is about 6 micrometers (.mu.m). When made with film widths of about 4 .mu.m an inventive high transition-temperature, superconducting quantum interference device (SQUID) excluded magnetic flux vortices up to a threshold ambient magnetic field of about 100 microTesla (.mu.T). SQUIDs were fabricated having several different film strip patterns. When the film strip width was kept at about 4 .mu.m, the SQUIDs exhibited essentially no increase in low-frequency noise, even when cooled in static magnetic fields of magnitude up to 100 .mu.T. Furthermore, the mutual inductance between the inventive devices and a seven-turn spiral coil was at least 85% of that for inductive coupling to a conventional SQUID.

Wind-energy recovery by a static Scherbius induction generator

NASA Astrophysics Data System (ADS)

Smith, G. A.; Nigim, K. A.

1981-11-01

The paper describes a technique for controlling a doubly fed induction generator driven by a windmill, or other form of variable-speed prime mover, to provide power generation into the national grid system. The secondary circuit of the generator is supplied at a variable frequency from a current source inverter which for test purposes is rated to allow energy recovery, from a simulated windmill, from maximum speed to standstill. To overcome the stability problems normally associated with doubly fed machines a novel signal generator, which is locked in phase with the rotor EMF, controls the secondary power to provide operation over a wide range of subsynchronous and supersynchronous speeds. Consideration of power flow enables the VA rating of the secondary power source to be determined as a function of the gear ratio and online operating range of the system. A simple current source model is used to predict performance which is compared with experimental results. The results indicate a viable system, and suggestions for further work are proposed.

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

NASA Technical Reports Server (NTRS)

Mclyman, W. T. (Inventor)

1981-01-01

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

High-mobility field-effect transistor based on crystalline ZnSnO3 thin films

NASA Astrophysics Data System (ADS)

Minato, Hiroya; Fujiwara, Kohei; Tsukazaki, Atsushi

2018-05-01

We propose crystalline ZnSnO3 as a new channel material for field-effect transistors. By molecular-beam epitaxy on LiNbO3(0001) substrates, we synthesized films of ZnSnO3, which crystallizes in the LiNbO3-type polar structure. Field-effect transistors on ZnSnO3 exhibit n-type operation with field-effect mobility of as high as 45 cm2V-1s-1 at room temperature. Systematic examination of the transistor operation for channels with different Zn/Sn compositional ratios revealed that the observed high-mobility reflects the nature of stoichiometric ZnSnO3 phase. Moreover, we found an indication of coupling of transistor characteristics with intrinsic spontaneous polarization in ZnSnO3, potentially leading to a distinct type of polarization-induced conduction.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

Fabrication of eco-friendly PNP transistor using RF magnetron sputtering

NASA Astrophysics Data System (ADS)

Kumar, B. Santhosh; Harinee, N.; Purvaja, K.; Shanker, N. Praveen; Manikandan, M.; Aparnadevi, N.; Mukilraj, T.; Venkateswaran, C.

2018-05-01

An effort has been made to fabricate a thin film transistor using eco-friendly oxide semiconductor materials. Oxide semiconductor materials are cost - effective, thermally and chemically stable with high electron/hole mobility. Copper (II) oxide is a p-type semiconductor and zinc oxide is an n-type semiconductor. A pnp thin film transistor was fabricated using RF magnetron sputtering. The films deposited have been subjected to structural characterization using AFM. I-V characterization of the fabricated device, Ag/CuO/ZnO/CuO/Ag, confirms transistor behaviour. The mechanism of electron/hole transport of the device is discussed below.

Design and Analysis of Reconfigurable Analog System

DTIC Science & Technology

2011-02-01

the number of the bits of the sub-ADC, the range of V is smaller than the full-scale input range by a factor of -L. If it is desired that Vin and Vst ...Transistor M1, M9, and M8 are off. Transistor M3 turns on which turns on transistor M7. As a result Vst is connected to V2. Since V2 was charged to Vdd when...Vutb), it disconnects the other output voltage ( Vst ) from the lower transistors (M2). A regenerative action helps both V0st and Vtb to reach their final

Application of Transistors in Textiles: Monitoring Water Transportation Behaviour in Fibrous Assemblies

NASA Astrophysics Data System (ADS)

Chatterjee, Arobindo; Singh, Pratibha; Ghosh, Subrata

2017-06-01

Simple semiconductor device has been used for amplifying the analog signals, obtained with the change in electrical resistance in fibrous assembly and converting these amplified copies of signals to digital signals. This paper deals with the application of transistors as amplifier, as well as switch. Different circuit configurations using transistors have been tried for sensing and reciprocating the real time data on suitable display device. It is found that transistors configured as common-emitter amplifiers can precisely sense the liquid at the surface of fibrous assembly at different levels with respect to time.

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

PubMed

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Influence of polymer dielectrics on C60-based field-effect transistors

NASA Astrophysics Data System (ADS)

Zhou, Jianlin; Zhang, Fujia; Lan, Lifeng; Wen, Shangsheng; Peng, Junbiao

2007-12-01

Fullerene C60 organic field-effect transistors (OFETs) have been fabricated based on two different polymer dielectric materials, poly(methylmethacrylate) (PMMA) and cross-linkable poly(4-vinylphenol). The large grain size of C60 film and small number of traps at the interface of PMMA /C60 were obtained with high electron mobility of 0.66cm2/Vs in the PMMA transistor. The result suggests that the C60 semiconductor cooperating with polymer dielectric is a promising application in the fabrication of n-type organic transistors because of low threshold voltage and high electron mobility.

N Channel JFET Based Digital Logic Gate Structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J (Inventor)

2013-01-01

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

DTIC Science & Technology

2016-03-01

Fabrication with 0.09-µm High-Electron-Mobility Transistors (HEMTs) Using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC) by John E Penn...for Fabrication with 0.09-µm High-Electron-Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide by John E Penn...µm High-Electron-Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c

Dynamics of current sheath in a hollow electrode Z-pinch discharge using slug model

NASA Astrophysics Data System (ADS)

Abd Al-Halim, Mohamed A.; Afify, M. S.

2017-03-01

The hollow electrode Z-pinch (HEZP) experiment is a new construction for the electromagnetic propulsion application in which the plasma is formed by the discharge between a plate and ring electrodes through which the plasma is propelled. The experimental results for 8 kV charging voltage shows that the peak discharge current is about 109 kA, which is in good agreement with the value obtained from the simulation in the slug model that simulates the sheath dynamics in the HEZP. The fitting of the discharge current from the slug model indicates that the total system inductance is 238 nH which is relatively a high static inductance accompanied with a deeper pinch depth indicating that the fitted anomalous resistance would be about 95 mΩ. The current and mass factors vary with the changing the gas pressure and the charging voltage. The current factor is between 0.4 and 0.5 on average which is relatively low value. The mass factor decreases by increasing the gas pressure indicating that the sheath is heavy to be driven by the magnetic pressure, which is also indicated from the decreases of the drive factor, hence the radial sheath velocity decreases. The plasma inductance and temperature increase with the increase of the drive factor while the minimum pinch radius decreases.