7 CFR 1435.104 - Loan maintenance.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.104... result of the execution of security agreements by sugarcane and sugar beet processors shall be superior to all statutory and common law liens on raw cane sugar, refined beet sugar, and in-process sugar for...

7 CFR 1435.104 - Loan maintenance.

Code of Federal Regulations, 2010 CFR

2010-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.104... result of the execution of security agreements by sugarcane and sugar beet processors shall be superior to all statutory and common law liens on raw cane sugar, refined beet sugar, and in-process sugar for...

7 CFR 1435.104 - Loan maintenance.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.104... result of the execution of security agreements by sugarcane and sugar beet processors shall be superior to all statutory and common law liens on raw cane sugar, refined beet sugar, and in-process sugar for...

7 CFR 1435.104 - Loan maintenance.

Code of Federal Regulations, 2014 CFR

2014-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.104... result of the execution of security agreements by sugarcane and sugar beet processors shall be superior to all statutory and common law liens on raw cane sugar, refined beet sugar, and in-process sugar for...

7 CFR 1435.104 - Loan maintenance.

Code of Federal Regulations, 2012 CFR

2012-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.104... result of the execution of security agreements by sugarcane and sugar beet processors shall be superior to all statutory and common law liens on raw cane sugar, refined beet sugar, and in-process sugar for...

7 CFR 1435.504 - Timing of distribution of CCC-owned sugar.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Timing of distribution of CCC-owned sugar. 1435.504... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind (PIK) Program § 1435.504 Timing of distribution of CCC-owned sugar. Distribution of sugar...

7 CFR 1435.504 - Timing of distribution of CCC-owned sugar.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 10 2011-01-01 2011-01-01 false Timing of distribution of CCC-owned sugar. 1435.504... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind (PIK) Program § 1435.504 Timing of distribution of CCC-owned sugar. Distribution of sugar...

7 CFR 1435.504 - Timing of distribution of CCC-owned sugar.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 10 2012-01-01 2012-01-01 false Timing of distribution of CCC-owned sugar. 1435.504... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind (PIK) Program § 1435.504 Timing of distribution of CCC-owned sugar. Distribution of sugar...

7 CFR 1435.504 - Timing of distribution of CCC-owned sugar.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 10 2013-01-01 2013-01-01 false Timing of distribution of CCC-owned sugar. 1435.504... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind (PIK) Program § 1435.504 Timing of distribution of CCC-owned sugar. Distribution of sugar...

7 CFR 1435.504 - Timing of distribution of CCC-owned sugar.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Timing of distribution of CCC-owned sugar. 1435.504... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind (PIK) Program § 1435.504 Timing of distribution of CCC-owned sugar. Distribution of sugar...

78 FR 45494 - Notice of Second Sugar Purchase and Exchange for Re-export Program Credits

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-29

... raw cane sugar to be offered in exchange for Refined Sugar Re- export Program credits as a follow-up..., 2013. CCC will invite domestic sugarcane processors to offer raw cane sugar to CCC, as authorized by...

7 CFR 1435.300 - Applicability.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... allotments for: (1) Processor marketings of sugar domestically processed from sugar beets or in-process beet sugar, whether such sugar beets or in-process beet sugar were produced domestically or imported, (2...

7 CFR 1435.300 - Applicability.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... allotments for: (1) Processor marketings of sugar domestically processed from sugar beets or in-process beet sugar, whether such sugar beets or in-process beet sugar were produced domestically or imported, (2...

7 CFR 1435.300 - Applicability.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... allotments for: (1) Processor marketings of sugar domestically processed from sugar beets or in-process beet sugar, whether such sugar beets or in-process beet sugar were produced domestically or imported, (2...

7 CFR 1435.300 - Applicability.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... allotments for: (1) Processor marketings of sugar domestically processed from sugar beets or in-process beet sugar, whether such sugar beets or in-process beet sugar were produced domestically or imported, (2...

7 CFR 1435.300 - Applicability.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... allotments for: (1) Processor marketings of sugar domestically processed from sugar beets or in-process beet sugar, whether such sugar beets or in-process beet sugar were produced domestically or imported, (2...

78 FR 45441 - Sugar Program; Feedstock Flexibility Program for Bioenergy Producers

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-29

... sugarcane processors may borrow from CCC, pledging their sugar production as collateral for any such loan... sugar for bioenergy production under FFP as a proactive means for CCC to avoid forfeitures. FFP is... production. In addition, CCC will make quarterly announcements of revised estimates of such quantity. CCC's...

7 CFR 1435.309 - Reassignment of deficits.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.309 Reassignment of deficits. (a) CCC will determine, from time to time, whether sugar beet or sugarcane processors will be unable to market their allocations. (b) Sugar beet and sugar cane...

7 CFR 1435.309 - Reassignment of deficits.

Code of Federal Regulations, 2010 CFR

2010-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.309 Reassignment of deficits. (a) CCC will determine, from time to time, whether sugar beet or sugarcane processors will be unable to market their allocations. (b) Sugar beet and sugar cane...

7 CFR 1435.309 - Reassignment of deficits.

Code of Federal Regulations, 2014 CFR

2014-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.309 Reassignment of deficits. (a) CCC will determine, from time to time, whether sugar beet or sugarcane processors will be unable to market their allocations. (b) Sugar beet and sugar cane...

7 CFR 1435.309 - Reassignment of deficits.

Code of Federal Regulations, 2012 CFR

2012-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.309 Reassignment of deficits. (a) CCC will determine, from time to time, whether sugar beet or sugarcane processors will be unable to market their allocations. (b) Sugar beet and sugar cane...

7 CFR 1435.309 - Reassignment of deficits.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.309 Reassignment of deficits. (a) CCC will determine, from time to time, whether sugar beet or sugarcane processors will be unable to market their allocations. (b) Sugar beet and sugar cane...

7 CFR 1435.315 - Adjustments to proportionate shares.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.315 Adjustments to proportionate shares. Whenever CCC determines that, because of... sufficient to enable state processors to produce sufficient sugar to meet the State's cane sugar allotment...

7 CFR 1435.315 - Adjustments to proportionate shares.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.315 Adjustments to proportionate shares. Whenever CCC determines that, because of... sufficient to enable state processors to produce sufficient sugar to meet the State's cane sugar allotment...

7 CFR 1435.315 - Adjustments to proportionate shares.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.315 Adjustments to proportionate shares. Whenever CCC determines that, because of... sufficient to enable state processors to produce sufficient sugar to meet the State's cane sugar allotment...

7 CFR 1435.315 - Adjustments to proportionate shares.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.315 Adjustments to proportionate shares. Whenever CCC determines that, because of... sufficient to enable state processors to produce sufficient sugar to meet the State's cane sugar allotment...

7 CFR 1435.315 - Adjustments to proportionate shares.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.315 Adjustments to proportionate shares. Whenever CCC determines that, because of... sufficient to enable state processors to produce sufficient sugar to meet the State's cane sugar allotment...

7 CFR 1435.505 - Miscellaneous provisions.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind... acreage, desugarizing capacity or other measures of sugar production as CCC determines. (b) The contract... specified in the CCC production diversion contract. (c) CCC will transfer title of the sugar to the...

7 CFR 1435.502 - Bid selection procedures.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind... acreage of sugar beets or sugarcane from production, CCC will rank bids on the basis of the bid amount as a percentage of the expected sugar produced from the retired acreage. Bids with the lowest of such...

7 CFR 1435.2 - Definitions.

Code of Federal Regulations, 2012 CFR

2012-01-01

... cane sugar allotments, the highest single year of sugar production for the State during the 1999... other than Louisiana, the highest single year of sugar production for the processor during the 1999... of the 2 highest years of sugar production during the 1996 through 2000 crop years; for Louisiana...

The Holidays Are Coming! Time to Start Planning for Healthy Holiday Meals

MedlinePlus

... 1 medium orange, quartered and seeds removed 1 apple, cored ¾ cup to 1 cup sugar (or substitute non-sugar sweetener) Put berries, orange and apple through food processor, blender or food mill until ...

Marketing potential of advanced breeding clones

USDA-ARS?s Scientific Manuscript database

The accumulation of reducing sugars during cold storage of potato tubers is a serious and costly problem for producers and processors. The degree to which cultivars accumulate reducing sugars during storage determines their processing and market potential. Cultivars or advanced breeding lines with...

Heat stress during development alters post-harvest sugar contents and chip processing quality of potato tubers

USDA-ARS?s Scientific Manuscript database

Environmental stresses that increase tuber contents of the reducing sugars glucose and fructose decrease the value of chipping potatoes because such tubers produce dark-colored chips that are unacceptable to processors and consumers. Stem-end chip defect (SECD), which causes regions of dark color al...

77 FR 23450 - USDA Increases and Reassigns Fiscal Year 2012 Overall Allotment Quantity and Increases Fiscal...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-19

... Raw Sugar Tariff-Rate Quota AGENCY: Office of the Secretary, USDA. ACTION: Notice. SUMMARY: The U.S. Department of Agriculture (USDA) today announced a 51,000 short tons raw value (STRV) increase in the fiscal... from domestic sugarcane processors to a 420,000 STRV increase in the FY 2012 raw sugar tariff-rate...

Seasonal variations on sugarcane trash quantity and quality that directly concern factory processors and refiners

USDA-ARS?s Scientific Manuscript database

In sugar manufacture, there is a trend in the United States and worldwide to produce very high purity (VHP) and very low color (VLC) raw sugars for vertical integration from the field to the refinery. New refineries in Louisiana (LA) are expected to be operational in the next few years. One of thes...

The Results of a Laboratory Feasibility Study for the Biological Treatment of Umatilla Groundwater

DTIC Science & Technology

2012-01-01

high fructose corn syrup Kroger brand lactose Columbia River Processors, Boardman, OR cheese whey Columbia River Processors, Boardman, OR lactate...Processing Roy Dugan 541·481-3771 79588 Rippee Road 55 High Fructose Corn Syrup Malt Products Corp. Joanne McGuire 530-677-8282 #677 Blackstrap...communication with experts) tested in Run 1 were: • high - fructose corn sugar (based on promising results obtained using soft drink by-products

Vigilante: Ultrafast Smart Sensor for Target Recognition and Precision Tracking in a Simulated CMD Scenario

NASA Technical Reports Server (NTRS)

Uldomkesmalee, Suraphol; Suddarth, Steven C.

1997-01-01

VIGILANTE is an ultrafast smart sensor testbed for generic Automatic Target Recognition (ATR) applications with a series of capability demonstration focussed on cruise missile defense (CMD). VIGILANTE's sensor/processor architecture is based on next-generation UV/visible/IR sensors and a tera-operations per second sugar-cube processor, as well as supporting airborne vehicle. Excellent results of efficient ATR methodologies that use an eigenvectors/neural network combination and feature-based precision tracking have been demonstrated in the laboratory environment.

Multithreading in vector processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Array processor architecture

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Suppression of the vacuolar invertase gene delays senescent sweetening in chipping potatoes

USDA-ARS?s Scientific Manuscript database

Background: Potato chip processors require potato tubers that meet quality specifications for fried chip color, and color depends largely upon tuber sugar contents. At later times in storage, potatoes accumulate sucrose, glucose and fructose. This developmental process, senescent sweetening, manifes...

7 CFR 1435.2 - Definitions.

Code of Federal Regulations, 2014 CFR

2014-01-01

... sugarcane processors. Cane sugar refiner means any person in the U.S. Customs Territory that refines raw... further refined or improved in quality and that is to be distributed for human consumption, either directly or in molasses-containing products. Edible syrups means syrups that are not to be further refined...

7 CFR 1435.2 - Definitions.

Code of Federal Regulations, 2010 CFR

2010-01-01

... sugarcane processors. Cane sugar refiner means any person in the U.S. Customs Territory that refines raw... further refined or improved in quality and that is to be distributed for human consumption, either directly or in molasses-containing products. Edible syrups means syrups that are not to be further refined...

7 CFR 1435.2 - Definitions.

Code of Federal Regulations, 2013 CFR

2013-01-01

... sugarcane processors. Cane sugar refiner means any person in the U.S. Customs Territory that refines raw... further refined or improved in quality and that is to be distributed for human consumption, either directly or in molasses-containing products. Edible syrups means syrups that are not to be further refined...

7 CFR 1435.2 - Definitions.

Code of Federal Regulations, 2011 CFR

2011-01-01

... sugarcane processors. Cane sugar refiner means any person in the U.S. Customs Territory that refines raw... further refined or improved in quality and that is to be distributed for human consumption, either directly or in molasses-containing products. Edible syrups means syrups that are not to be further refined...

Development of a Portable Blood Sugar Apparatus and GOD Enzyme Strip.

PubMed

Zhen-Cheng, Chen; Yu-Qian, Zhao; Jing-Tian, Tang; Ling-Yun, Li

2005-01-01

A pocket blood sugar apparatus tested by enzyme electrode, which was designed using carbon and silver plasma as conducting materials. Both the work and reference electrodes are applied to the parts of enzyme electrode. The glucose oxidase is taken as the medium of blood sugar measuring. And the range of measuring glucose is about 50mg/dL - 500mgl/dL. It has better linear for the results and fit coefficient arrives at 0.985. Its sensitivity of measurement is higher than current glucose biosensor obviously. A single chip microcomputer, AD mu C812, is used for central control processor of the instrument parts. It measures the output of microampere level currency, which is conduced by blood sugar reacting with the glucose oxidase on the enzyme electrode. And at the same time, the microampere level currency is amplified, processed. Then the results are displayed on LCD. The apparatus are better for measuring blood sugar, and the results are consistent with what the large biochemical instruments get.

The implementation and use of Ada on distributed systems with reliability requirements

NASA Technical Reports Server (NTRS)

Reynolds, P. F.; Knight, J. C.; Urquhart, J. I. A.

1983-01-01

The issues involved in the use of the programming language Ada on distributed systems are discussed. The effects of Ada programs on hardware failures such as loss of a processor are emphasized. It is shown that many Ada language elements are not well suited to this environment. Processor failure can easily lead to difficulties on those processors which remain. As an example, the calling task in a rendezvous may be suspended forever if the processor executing the serving task fails. A mechanism for detecting failure is proposed and changes to the Ada run time support system are suggested which avoid most of the difficulties. Ada program structures are defined which allow programs to reconfigure and continue to provide service following processor failure.

78 FR 68764 - Fisheries Off West Coast States; Pacific Coast Groundfish Fishery Management Plan; Commercial...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-11-15

... (coop) programs for the at-sea mothership and catcher/processor trawl fleets (whiting only). Since that... permit holder (vessel owner) to change their vessel ownership, 9. Clarify that the processor obligation..., Mothership Coop (MS) Program--Whiting At-sea Trawl Fishery, and Catcher-Processor (C/P) Coop Program--Whiting...

A debugger-interpreter with setup facilities for assembly programs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dolinskii, I.S.; Zisel`man, I.M.; Belotskii, S.L.

1995-11-01

In this paper a software program allowing one to introduce and debug the descriptions of the von Nuemann architecture processors and their assemblers, efficiently debug assembly programs, and investigate the instruction sets of the described processors is considered. For a description of the processor sematics and assembler syntax, a metassembly language is suggested.

76 FR 52147 - Fisheries of the Exclusive Economic Zone Off Alaska; Groundfish of the Gulf of Alaska; Amendment 88

Federal Register 2010, 2011, 2012, 2013, 2014

2011-08-19

... Pilot Program and the proposed Rockfish Program are a type of a limited access privilege program (LAPP... Central GOA fishermen, shoreside processors, catcher/processors, and communities by (1) providing greater... the ability to choose when to fish, (3) providing greater stability for processors by spreading...

7 CFR 1435.201 - Civil penalties.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 10 2011-01-01 2011-01-01 false Civil penalties. 1435.201 Section 1435.201... Recordkeeping Requirements § 1435.201 Civil penalties. (a) Any processor, refiner, or importer of sugar, syrup... false data required under § 1435.200(a) through (e), is subject to a civil penalty of no more than the...

7 CFR 1435.201 - Civil penalties.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 10 2013-01-01 2013-01-01 false Civil penalties. 1435.201 Section 1435.201... Recordkeeping Requirements § 1435.201 Civil penalties. (a) Any processor, refiner, or importer of sugar, syrup... false data required under § 1435.200(a) through (e), is subject to a civil penalty of no more than the...

7 CFR 1435.201 - Civil penalties.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Civil penalties. 1435.201 Section 1435.201... Recordkeeping Requirements § 1435.201 Civil penalties. (a) Any processor, refiner, or importer of sugar, syrup... false data required under § 1435.200(a) through (e), is subject to a civil penalty of no more than $10...

7 CFR 1435.201 - Civil penalties.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 10 2012-01-01 2012-01-01 false Civil penalties. 1435.201 Section 1435.201... Recordkeeping Requirements § 1435.201 Civil penalties. (a) Any processor, refiner, or importer of sugar, syrup... false data required under § 1435.200(a) through (e), is subject to a civil penalty of no more than the...

7 CFR 1435.201 - Civil penalties.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Civil penalties. 1435.201 Section 1435.201... Recordkeeping Requirements § 1435.201 Civil penalties. (a) Any processor, refiner, or importer of sugar, syrup... false data required under § 1435.200(a) through (e), is subject to a civil penalty of no more than the...

New Modular Ultrasonic Signal Processing Building Blocks for Real-Time Data Acquisition and Post Processing

NASA Astrophysics Data System (ADS)

Weber, Walter H.; Mair, H. Douglas; Jansen, Dion

2003-03-01

A suite of basic signal processors has been developed. These basic building blocks can be cascaded together to form more complex processors without the need for programming. The data structures between each of the processors are handled automatically. This allows a processor built for one purpose to be applied to any type of data such as images, waveform arrays and single values. The processors are part of Winspect Data Acquisition software. The new processors are fast enough to work on A-scan signals live while scanning. Their primary use is to extract features, reduce noise or to calculate material properties. The cascaded processors work equally well on live A-scan displays, live gated data or as a post-processing engine on saved data. Researchers are able to call their own MATLAB or C-code from anywhere within the processor structure. A built-in formula node processor that uses a simple algebraic editor may make external user programs unnecessary. This paper also discusses the problems associated with ad hoc software development and how graphical programming languages can tie up researchers writing software rather than designing experiments.

The Use of a Microcomputer Based Array Processor for Real Time Laser Velocimeter Data Processing

NASA Technical Reports Server (NTRS)

Meyers, James F.

1990-01-01

The application of an array processor to laser velocimeter data processing is presented. The hardware is described along with the method of parallel programming required by the array processor. A portion of the data processing program is described in detail. The increase in computational speed of a microcomputer equipped with an array processor is illustrated by comparative testing with a minicomputer.

System support software for the Space Ultrareliable Modular Computer (SUMC)

NASA Technical Reports Server (NTRS)

Hill, T. E.; Hintze, G. C.; Hodges, B. C.; Austin, F. A.; Buckles, B. P.; Curran, R. T.; Lackey, J. D.; Payne, R. E.

1974-01-01

The highly transportable programming system designed and implemented to support the development of software for the Space Ultrareliable Modular Computer (SUMC) is described. The SUMC system support software consists of program modules called processors. The initial set of processors consists of the supervisor, the general purpose assembler for SUMC instruction and microcode input, linkage editors, an instruction level simulator, a microcode grid print processor, and user oriented utility programs. A FORTRAN 4 compiler is undergoing development. The design facilitates the addition of new processors with a minimum effort and provides the user quasi host independence on the ground based operational software development computer. Additional capability is provided to accommodate variations in the SUMC architecture without consequent major modifications in the initial processors.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

DOEpatents

Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

2013-05-21

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

NASA Astrophysics Data System (ADS)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

Implementing the PM Programming Language using MPI and OpenMP - a New Tool for Programming Geophysical Models on Parallel Systems

NASA Astrophysics Data System (ADS)

Bellerby, Tim

2015-04-01

PM (Parallel Models) is a new parallel programming language specifically designed for writing environmental and geophysical models. The language is intended to enable implementers to concentrate on the science behind the model rather than the details of running on parallel hardware. At the same time PM leaves the programmer in control - all parallelisation is explicit and the parallel structure of any given program may be deduced directly from the code. This paper describes a PM implementation based on the Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) standards, looking at issues involved with translating the PM parallelisation model to MPI/OpenMP protocols and considering performance in terms of the competing factors of finer-grained parallelisation and increased communication overhead. In order to maximise portability, the implementation stays within the MPI 1.3 standard as much as possible, with MPI-2 MPI-IO file handling the only significant exception. Moreover, it does not assume a thread-safe implementation of MPI. PM adopts a two-tier abstract representation of parallel hardware. A PM processor is a conceptual unit capable of efficiently executing a set of language tasks, with a complete parallel system consisting of an abstract N-dimensional array of such processors. PM processors may map to single cores executing tasks using cooperative multi-tasking, to multiple cores or even to separate processing nodes, efficiently sharing tasks using algorithms such as work stealing. While tasks may move between hardware elements within a PM processor, they may not move between processors without specific programmer intervention. Tasks are assigned to processors using a nested parallelism approach, building on ideas from Reyes et al. (2009). The main program owns all available processors. When the program enters a parallel statement then either processors are divided out among the newly generated tasks (number of new tasks < number of processors) or tasks are divided out among the available processors (number of tasks > number of processors). Nested parallel statements may further subdivide the processor set owned by a given task. Tasks or processors are distributed evenly by default, but uneven distributions are possible under programmer control. It is also possible to explicitly enable child tasks to migrate within the processor set owned by their parent task, reducing load unbalancing at the potential cost of increased inter-processor message traffic. PM incorporates some programming structures from the earlier MIST language presented at a previous EGU General Assembly, while adopting a significantly different underlying parallelisation model and type system. PM code is available at www.pm-lang.org under an unrestrictive MIT license. Reference Ruymán Reyes, Antonio J. Dorta, Francisco Almeida, Francisco de Sande, 2009. Automatic Hybrid MPI+OpenMP Code Generation with llc, Recent Advances in Parallel Virtual Machine and Message Passing Interface, Lecture Notes in Computer Science Volume 5759, 185-195

7 CFR 1530.100 - General statement.

Code of Federal Regulations, 2010 CFR

2010-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM... the Refined Sugar Re-Export Program, the Sugar Containing Products Re-Export Program, and the Polyhydric Alcohol Program. Under these provisions, refiners may enter raw sugar unrestricted by the...

7 CFR 1530.100 - General statement.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM... the Refined Sugar Re-Export Program, the Sugar Containing Products Re-Export Program, and the Polyhydric Alcohol Program. Under these provisions, refiners may enter raw sugar unrestricted by the...

7 CFR 1530.100 - General statement.

Code of Federal Regulations, 2012 CFR

2012-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM... the Refined Sugar Re-Export Program, the Sugar Containing Products Re-Export Program, and the Polyhydric Alcohol Program. Under these provisions, refiners may enter raw sugar unrestricted by the...

7 CFR 1530.100 - General statement.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM... the Refined Sugar Re-Export Program, the Sugar Containing Products Re-Export Program, and the Polyhydric Alcohol Program. Under these provisions, refiners may enter raw sugar unrestricted by the...

Neurovision processor for designing intelligent sensors

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

Factors Influencing Rural Women Cassava Processors' Intention to Participate in an Agricultural Extension Education Program. Summary of Research 80.

ERIC Educational Resources Information Center

Ojomo, Christian O.; McCaslin, N. L.

A study examined factors influencing female cassava processors' intentions regarding participation in an extension education program on cassava processing in rural Nigeria. Interviews were conducted with 224 women who were purposely selected from areas of zone 3 of Ondo State, Nigeria, which has large concentrations of cassava processors.…

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 9 2013-01-01 2013-01-01 false Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 9 2012-01-01 2012-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 9 2014-01-01 2013-01-01 true Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 9 2011-01-01 2011-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

Optimal partitioning of random programs across two processors

NASA Technical Reports Server (NTRS)

Nicol, D. M.

1986-01-01

The optimal partitioning of random distributed programs is discussed. It is concluded that the optimal partitioning of a homogeneous random program over a homogeneous distributed system either assigns all modules to a single processor, or distributes the modules as evenly as possible among all processors. The analysis rests heavily on the approximation which equates the expected maximum of a set of independent random variables with the set's maximum expectation. The results are strengthened by providing an approximation-free proof of this result for two processors under general conditions on the module execution time distribution. It is also shown that use of this approximation causes two of the previous central results to be false.

Networked Workstations and Parallel Processing Utilizing Functional Languages

DTIC Science & Technology

1993-03-01

program . This frees the programmer to concentrate on what the program is to do, not how the program is...traditional ’von Neumann’ architecture uses a timer based (e.g., the program counter), sequentially pro- grammed, single processor approach to problem...traditional ’von Neumann’ architecture uses a timer based (e.g., the program counter), sequentially programmed , single processor approach to

Implementation of context independent code on a new array processor: The Super-65

NASA Technical Reports Server (NTRS)

Colbert, R. O.; Bowhill, S. A.

1981-01-01

The feasibility of rewriting standard uniprocessor programs into code which contains no context-dependent branches is explored. Context independent code (CIC) would contain no branches that might require different processing elements to branch different ways. In order to investigate the possibilities and restrictions of CIC, several programs were recoded into CIC and a four-element array processor was built. This processor (the Super-65) consisted of three 6502 microprocessors and the Apple II microcomputer. The results obtained were somewhat dependent upon the specific architecture of the Super-65 but within bounds, the throughput of the array processor was found to increase linearly with the number of processing elements (PEs). The slope of throughput versus PEs is highly dependent on the program and varied from 0.33 to 1.00 for the sample programs.

Word Processors: A Look at Four Popular Programs.

ERIC Educational Resources Information Center

Press, Larry

1980-01-01

Described are types of programs used for processing text (editors, print formatters, and word processors), followed by the comparison of four word-processing packages: Auto Scribe, Electric Pencil, Magic Want and Word Star. With the exception of Auto Scribe, all programs reviewed are CP/M versions. (KC)

JPRS Report, Science & Technology, Europe.

DTIC Science & Technology

1991-04-30

processor in collaboration with Intel . The processor , christened Touchstone, will be used as the core of a parallel computer with 2,000 processors . One of...ELECTRONIQUE HEBDO in French 24 Jan 91 pp 14-15 [Article by Claire Remy: "Everything Set for Neural Signal Processors " first paragraph is ELECTRONIQUE...paving the way for neural signal processors in so doing. The principal advantage of this specific circuit over a neuromimetic software program is

Transient Finite Element Computations on a Variable Transputer System

NASA Technical Reports Server (NTRS)

Smolinski, Patrick J.; Lapczyk, Ireneusz

1993-01-01

A parallel program to analyze transient finite element problems was written and implemented on a system of transputer processors. The program uses the explicit time integration algorithm which eliminates the need for equation solving, making it more suitable for parallel computations. An interprocessor communication scheme was developed for arbitrary two dimensional grid processor configurations. Several 3-D problems were analyzed on a system with a small number of processors.

High-performance computing — an overview

NASA Astrophysics Data System (ADS)

Marksteiner, Peter

1996-08-01

An overview of high-performance computing (HPC) is given. Different types of computer architectures used in HPC are discussed: vector supercomputers, high-performance RISC processors, various parallel computers like symmetric multiprocessors, workstation clusters, massively parallel processors. Software tools and programming techniques used in HPC are reviewed: vectorizing compilers, optimization and vector tuning, optimization for RISC processors; parallel programming techniques like shared-memory parallelism, message passing and data parallelism; and numerical libraries.

Language and Program for Documenting Software Design

NASA Technical Reports Server (NTRS)

Kleine, H.; Zepko, T. M.

1986-01-01

Software Design and Documentation Language (SDDL) provides effective communication medium to support design and documentation of complex software applications. SDDL supports communication among all members of software design team and provides for production of informative documentation on design effort. Use of SDDL-generated document to analyze design makes it possible to eliminate many errors not detected until coding and testing attempted. SDDL processor program translates designer's creative thinking into effective document for communication. Processor performs as many automatic functions as possible, freeing designer's energy for creative effort. SDDL processor program written in PASCAL.

7 CFR 1435.100 - Applicability.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.100 Applicability... not be available for sugar produced from imported sugar beets, sugarcane, molasses, syrups and in-process sugar. ...

7 CFR 1435.100 - Applicability.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.100 Applicability... not be available for sugar produced from imported sugar beets, sugarcane, molasses, syrups and in-process sugar. ...

7 CFR 1435.100 - Applicability.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.100 Applicability... not be available for sugar produced from imported sugar beets, sugarcane, molasses, syrups and in-process sugar. ...

7 CFR 1435.100 - Applicability.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.100 Applicability... not be available for sugar produced from imported sugar beets, sugarcane, molasses, syrups and in-process sugar. ...

7 CFR 1435.100 - Applicability.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.100 Applicability... not be available for sugar produced from imported sugar beets, sugarcane, molasses, syrups and in-process sugar. ...

75 FR 39892 - Fisheries of the Exclusive Economic Zone Off Alaska; Community Development Quota Program

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-13

... Fisheries Act (AFA) trawl catcher/processor sector (otherwise known as the Amendment 80 sector... catcher/processors. Hook-and-line catcher/processors are allocated 48.7 percent of the annual BSAI Pacific... harvest of Pacific cod by hook-and-line catcher/processors, although this is one of the major groundfish...

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G; Salapura, Valentina

2014-12-02

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Simulation of a master-slave event set processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comfort, J.C.

1984-03-01

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. The paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principal processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation program modeling this system was constructed, and was run with tracemore » output taken from two different simulation programs. Output from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and interprocessor communication times). A comparison between actual and simulation run times for a one-processor system was used to assist in the validation of the simulation. 7 references.« less

Buffered coscheduling for parallel programming and enhanced fault tolerance

DOEpatents

Petrini, Fabrizio [Los Alamos, NM; Feng, Wu-chun [Los Alamos, NM

2006-01-31

A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors

7 CFR 1435.603 - Eligible sugar seller.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Eligible sugar seller. 1435.603 Section 1435.603... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Feedstock Flexibility Program § 1435.603 Eligible sugar seller. (a) To be considered an eligible sugar seller, the sugar seller must be...

Tailoring Software for Multiple Processor Systems

DTIC Science & Technology

1982-10-01

resource management decisions . Despite the lack of programming support, the use of multiple processor systems has grown sub- -stantially. Software has...making resource management decisions . Specifically, program- 1 mers need not allocate specific hardware resources to individual program components...Instead, such allocation decisions are automatically made based on high-level resource directives stated by ap- plication programmers, where each directive

Computer program documentation for the pasture/range condition assessment processor

NASA Technical Reports Server (NTRS)

Mcintyre, K. S.; Miller, T. G. (Principal Investigator)

1982-01-01

The processor which drives for the RANGE software allows the user to analyze LANDSAT data containing pasture and rangeland. Analysis includes mapping, generating statistics, calculating vegetative indexes, and plotting vegetative indexes. Routines for using the processor are given. A flow diagram is included.

Design of RISC Processor Using VHDL and Cadence

NASA Astrophysics Data System (ADS)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

Orthorectification by Using Gpgpu Method

NASA Astrophysics Data System (ADS)

Sahin, H.; Kulur, S.

2012-07-01

Thanks to the nature of the graphics processing, the newly released products offer highly parallel processing units with high-memory bandwidth and computational power of more than teraflops per second. The modern GPUs are not only powerful graphic engines but also they are high level parallel programmable processors with very fast computing capabilities and high-memory bandwidth speed compared to central processing units (CPU). Data-parallel computations can be shortly described as mapping data elements to parallel processing threads. The rapid development of GPUs programmability and capabilities attracted the attentions of researchers dealing with complex problems which need high level calculations. This interest has revealed the concepts of "General Purpose Computation on Graphics Processing Units (GPGPU)" and "stream processing". The graphic processors are powerful hardware which is really cheap and affordable. So the graphic processors became an alternative to computer processors. The graphic chips which were standard application hardware have been transformed into modern, powerful and programmable processors to meet the overall needs. Especially in recent years, the phenomenon of the usage of graphics processing units in general purpose computation has led the researchers and developers to this point. The biggest problem is that the graphics processing units use different programming models unlike current programming methods. Therefore, an efficient GPU programming requires re-coding of the current program algorithm by considering the limitations and the structure of the graphics hardware. Currently, multi-core processors can not be programmed by using traditional programming methods. Event procedure programming method can not be used for programming the multi-core processors. GPUs are especially effective in finding solution for repetition of the computing steps for many data elements when high accuracy is needed. Thus, it provides the computing process more quickly and accurately. Compared to the GPUs, CPUs which perform just one computing in a time according to the flow control are slower in performance. This structure can be evaluated for various applications of computer technology. In this study covers how general purpose parallel programming and computational power of the GPUs can be used in photogrammetric applications especially direct georeferencing. The direct georeferencing algorithm is coded by using GPGPU method and CUDA (Compute Unified Device Architecture) programming language. Results provided by this method were compared with the traditional CPU programming. In the other application the projective rectification is coded by using GPGPU method and CUDA programming language. Sample images of various sizes, as compared to the results of the program were evaluated. GPGPU method can be used especially in repetition of same computations on highly dense data, thus finding the solution quickly.

7 CFR 1530.103 - License eligibility.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE POLYHYDRIC ALCOHOL PROGRAM § 1530.103 License eligibility. (a) A raw cane sugar refiner, a manufacturer of sugar containing products, or a producer of certain polyhydric alcohols, that owns and operates...

7 CFR 1530.103 - License eligibility.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE POLYHYDRIC ALCOHOL PROGRAM § 1530.103 License eligibility. (a) A raw cane sugar refiner, a manufacturer of sugar containing products, or a producer of certain polyhydric alcohols, that owns and operates...

Understanding the impact of crop and food production on the water environment--using sugar as a model.

PubMed

Hess, Tim; Aldaya, Maite; Fawell, John; Franceschini, Helen; Ober, Eric; Schaub, Ruediger; Schulze-Aurich, Jochen

2014-01-15

The availability of fresh water and the quality of aquatic ecosystems are important global concerns, and agriculture plays a major role. Consumers and manufacturers are increasingly sensitive to sustainability issues related to processed food products and drinks. The present study examines the production of sugar from the growing cycle through to processing to the factory gate, and identifies the potential impacts on water scarcity and quality and the ways in which the impact of water use can be minimised. We have reviewed the production phases and processing steps, and how calculations of water use can be complicated, or in some cases how assessments can be relatively straightforward. Finally, we outline several ways that growers and sugar processors are improving the efficiency of water use and reducing environmental impact, and where further advances can be made. This provides a template for the assessment of other crops. © 2013 Society of Chemical Industry.

Automatic Dynamic Aircraft Modeler (ADAM) for the Computer Program NASTRAN

NASA Technical Reports Server (NTRS)

Griffis, H.

1985-01-01

Large general purpose finite element programs require users to develop large quantities of input data. General purpose pre-processors are used to decrease the effort required to develop structural models. Further reduction of effort can be achieved by specific application pre-processors. Automatic Dynamic Aircraft Modeler (ADAM) is one such application specific pre-processor. General purpose pre-processors use points, lines and surfaces to describe geometric shapes. Specifying that ADAM is used only for aircraft structures allows generic structural sections, wing boxes and bodies, to be pre-defined. Hence with only gross dimensions, thicknesses, material properties and pre-defined boundary conditions a complete model of an aircraft can be created.

7 CFR 1530.101 - Definitions.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... sugar without the required re-export within the program guidelines. Certain polyhydric alcohols means... as a substitute for sugar as a sweetener in human food. Co-packer means a person who adds value to a...

7 CFR 1530.101 - Definitions.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... sugar without the required re-export within the program guidelines. Certain polyhydric alcohols means... as a substitute for sugar as a sweetener in human food. Co-packer means a person who adds value to a...

7 CFR 1530.101 - Definitions.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... sugar without the required re-export within the program guidelines. Certain polyhydric alcohols means... as a substitute for sugar as a sweetener in human food. Co-packer means a person who adds value to a...

7 CFR 1530.101 - Definitions.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... sugar without the required re-export within the program guidelines. Certain polyhydric alcohols means... as a substitute for sugar as a sweetener in human food. Co-packer means a person who adds value to a...

Development of small scale cluster computer for numerical analysis

NASA Astrophysics Data System (ADS)

Zulkifli, N. H. N.; Sapit, A.; Mohammed, A. N.

2017-09-01

In this study, two units of personal computer were successfully networked together to form a small scale cluster. Each of the processor involved are multicore processor which has four cores in it, thus made this cluster to have eight processors. Here, the cluster incorporate Ubuntu 14.04 LINUX environment with MPI implementation (MPICH2). Two main tests were conducted in order to test the cluster, which is communication test and performance test. The communication test was done to make sure that the computers are able to pass the required information without any problem and were done by using simple MPI Hello Program where the program written in C language. Additional, performance test was also done to prove that this cluster calculation performance is much better than single CPU computer. In this performance test, four tests were done by running the same code by using single node, 2 processors, 4 processors, and 8 processors. The result shows that with additional processors, the time required to solve the problem decrease. Time required for the calculation shorten to half when we double the processors. To conclude, we successfully develop a small scale cluster computer using common hardware which capable of higher computing power when compare to single CPU processor, and this can be beneficial for research that require high computing power especially numerical analysis such as finite element analysis, computational fluid dynamics, and computational physics analysis.

Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

NASA Astrophysics Data System (ADS)

Chen, Paul; Butts, Mike; Budlong, Brad; Wasson, Paul

2008-04-01

This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

76 FR 41450 - Notice of Request for Extension of a Currently Approved Information Collection

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-14

... approved information collection procedure for Sugar Import Licensing Programs described in 7 CFR part 1530... INFORMATION: Title: Sugar Imported for Export as Refined Sugar or as a Sugar- Containing Product, or used in... primary objective of the Sugar Import Licensing Program is to permit entry of raw cane sugar, unrestricted...

78 FR 33243 - Amendment 94 to the Gulf of Alaska Fishery Management Plan and Regulatory Amendments for...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-06-04

... floating processor landing reporting requirements; and to consolidate CQE Program eligibility by community... determine their annual reporting requirements. CQE Floating Processor Landing Report Requirements This action revises the recordkeeping and reporting regulations at Sec. 679.5(e) for CQE floating processors...

78 FR 14490 - Amendment 94 to the Gulf of Alaska Fishery Management Plan and Regulatory Amendments for...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-03-06

... clarify the CQE floating processor landing reporting requirements; and to consolidate CQE Program... their annual reporting requirements. CQE Floating Processor Landing Report Requirements This action would revise the recordkeeping and reporting regulations at Sec. 679.5(e) for CQE floating processors...

7 CFR 1435.604 - Eligible sugar buyer.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Eligible sugar buyer. 1435.604 Section 1435.604... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Feedstock Flexibility Program § 1435.604 Eligible sugar buyer. (a) To be considered an eligible sugar buyer, the bioenergy producer...

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, G. H.

1985-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90 percent for sufficiently large problems.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, B. H.

1984-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90% for sufficiently large problems.

Mass Memory Storage Devices for AN/SLQ-32(V).

DTIC Science & Technology

1985-06-01

tactical programs and libraries into the AN/UYK-19 computer , the RP-16 microprocessor, and other peripheral processors (e.g., ADLS and Band 1) will be...software must be loaded into computer memory from the 4-track magnetic tape cartridges (MTCs) on which the programs are stored. Program load begins...software. Future computer programs , which will reside in peripheral processors, include the Automated Decoy Launching System (ADLS) and Band 1. As

Development for SSV on a parallel processing system (PARAGON)

NASA Astrophysics Data System (ADS)

Gothard, Benny M.; Allmen, Mark; Carroll, Michael J.; Rich, Dan

1995-12-01

A goal of the surrogate semi-autonomous vehicle (SSV) program is to have multiple vehicles navigate autonomously and cooperatively with other vehicles. This paper describes the process and tools used in porting UGV/SSV (unmanned ground vehicle) autonomous mobility and target recognition algorithms from a SISD (single instruction single data) processor architecture (i.e., a Sun SPARC workstation running C/UNIX) to a MIMD (multiple instruction multiple data) parallel processor architecture (i.e., PARAGON-a parallel set of i860 processors running C/UNIX). It discusses the gains in performance and the pitfalls of such a venture. It also examines the merits of this processor architecture (based on this conceptual prototyping effort) and programming paradigm to meet the final SSV demonstration requirements.

Reduction of solar vector magnetograph data using a microMSP array processor

NASA Technical Reports Server (NTRS)

Kineke, Jack

1990-01-01

The processing of raw data obtained by the solar vector magnetograph at NASA-Marshall requires extensive arithmetic operations on large arrays of real numbers. The objectives of this summer faculty fellowship study are to: (1) learn the programming language of the MicroMSP Array Processor and adapt some existing data reduction routines to exploit its capabilities; and (2) identify other applications and/or existing programs which lend themselves to array processor utilization which can be developed by undergraduate student programmers under the provisions of project JOVE.

75 FR 14015 - Fisheries of the Exclusive Economic Zone Off Alaska; Chinook Salmon Bycatch Management in the...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-23

... Pollock Fishery This proposed rule applies to owners and operators of catcher vessels, catcher/processors, motherships, inshore processors, and the six Western Alaska Community Development Quota (CDQ) Program groups... fishery by identifying the vessels and processors eligible to participate in the fishery and allocating...

76 FR 77757 - Fisheries of the Exclusive Economic Zone Off Alaska; Chinook Salmon Bycatch Management in the...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-12-14

... the program to allow participation by all types of near shore, stationary processors for halibut... This proposed rule would apply to owners and operators of catcher vessels, catcher/processors, and inshore processors participating in the pollock (Theragra chalcogramma) trawl fisheries in the Central and...

Stanford Hardware Development Program

NASA Technical Reports Server (NTRS)

Peterson, A.; Linscott, I.; Burr, J.

1986-01-01

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

7 CFR 1435.602 - Eligible sugar to be purchased by CCC.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Eligible sugar to be purchased by CCC. 1435.602... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Feedstock Flexibility Program § 1435.602 Eligible sugar to be purchased by CCC. (a) CCC will only purchase raw sugar...

Mechanism to support generic collective communication across a variety of programming models

DOEpatents

Almasi, Gheorghe [Ardsley, NY; Dozsa, Gabor [Ardsley, NY; Kumar, Sameer [White Plains, NY

2011-07-19

A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation, an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.

An intelligent allocation algorithm for parallel processing

NASA Technical Reports Server (NTRS)

Carroll, Chester C.; Homaifar, Abdollah; Ananthram, Kishan G.

1988-01-01

The problem of allocating nodes of a program graph to processors in a parallel processing architecture is considered. The algorithm is based on critical path analysis, some allocation heuristics, and the execution granularity of nodes in a program graph. These factors, and the structure of interprocessor communication network, influence the allocation. To achieve realistic estimations of the executive durations of allocations, the algorithm considers the fact that nodes in a program graph have to communicate through varying numbers of tokens. Coarse and fine granularities have been implemented, with interprocessor token-communication duration, varying from zero up to values comparable to the execution durations of individual nodes. The effect on allocation of communication network structures is demonstrated by performing allocations for crossbar (non-blocking) and star (blocking) networks. The algorithm assumes the availability of as many processors as it needs for the optimal allocation of any program graph. Hence, the focus of allocation has been on varying token-communication durations rather than varying the number of processors. The algorithm always utilizes as many processors as necessary for the optimal allocation of any program graph, depending upon granularity and characteristics of the interprocessor communication network.

78 FR 40103 - Proposed Information Collection; Comment Request; Amendment 80 Economic Data Report for the...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-03

... Collection; Comment Request; Amendment 80 Economic Data Report for the Catcher/Processor Non-AFA Trawl Sector.../processor sector. The Amendment 80 economic data report (EDR) collects cost, revenue, ownership, and... Program. The purpose of the EDR is to understand the economic effects of the Amendment 80 program on...

The LOGO Processor; A Guide for System Programmers.

ERIC Educational Resources Information Center

Weiner, Walter B.; And Others

A detailed specification of the LOGO programing system is given. The level of description is intended to enable system programers to design LOGO processors of their own. The discussion of storage allocation and garbage collection algorithms is virtually complete. An annotated LOGO system listing for the PDP-10 computer system may be obtained on…

Space Station Water Processor Process Pump

NASA Technical Reports Server (NTRS)

Parker, David

1995-01-01

This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

SPAR reference manual

NASA Technical Reports Server (NTRS)

Whetstone, W. D.

1976-01-01

The functions and operating rules of the SPAR system, which is a group of computer programs used primarily to perform stress, buckling, and vibrational analyses of linear finite element systems, were given. The following subject areas were discussed: basic information, structure definition, format system matrix processors, utility programs, static solutions, stresses, sparse matrix eigensolver, dynamic response, graphics, and substructure processors.

DIALIGN P: fast pair-wise and multiple sequence alignment using parallel processors.

PubMed

Schmollinger, Martin; Nieselt, Kay; Kaufmann, Michael; Morgenstern, Burkhard

2004-09-09

Parallel computing is frequently used to speed up computationally expensive tasks in Bioinformatics. Herein, a parallel version of the multi-alignment program DIALIGN is introduced. We propose two ways of dividing the program into independent sub-routines that can be run on different processors: (a) pair-wise sequence alignments that are used as a first step to multiple alignment account for most of the CPU time in DIALIGN. Since alignments of different sequence pairs are completely independent of each other, they can be distributed to multiple processors without any effect on the resulting output alignments. (b) For alignments of large genomic sequences, we use a heuristics by splitting up sequences into sub-sequences based on a previously introduced anchored alignment procedure. For our test sequences, this combined approach reduces the program running time of DIALIGN by up to 97%. By distributing sub-routines to multiple processors, the running time of DIALIGN can be crucially improved. With these improvements, it is possible to apply the program in large-scale genomics and proteomics projects that were previously beyond its scope.

76 FR 40628 - Groundfish Fisheries of the EEZ Off Alaska; Pacific Halibut Fisheries; CDQ Program; Bering Sea...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-11

..., business telephone number, e-mail address, port of landing, operation type (for catcher/processors.../processor, the at-sea operation type is pre-filled automatically. (3) If an SFP and crab delivery is... Registered Crab Receiver record in eLandings the region in which the stationary floating processor is located...

77 FR 68106 - Second Fishing Capacity Reduction Program for the Longline Catcher Processor Subsector of the...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-11-15

... reduction contract is in full force and effect and NMFS is preparing to tender and disburse a reduction... license LLG2085 with area endorsements for Bering Sea Catcher/ Processor Hook and Longline and Aleutian Islands Catcher/Processor Hook and Longline. NMFS will tender the reduction payment on or about December...

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G.; Salapura, Valentina

2012-07-24

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

7 CFR 1435.103 - Availability, disbursement, and maturity of loans.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.103 Availability, disbursement, and maturity of loans. (a) Before obtaining a... on sugar or in-process sugar pledged as loan collateral, obtain waivers that fully protect CCC's...

7 CFR 1435.103 - Availability, disbursement, and maturity of loans.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.103 Availability, disbursement, and maturity of loans. (a) Before obtaining a... on sugar or in-process sugar pledged as loan collateral, obtain waivers that fully protect CCC's...

7 CFR 1435.105 - Loan settlement and foreclosure.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program...) Forfeiture of sugar loan collateral will be accepted as payment in full of the principal and interest due... specifications reported on the sugar loan certification report and actual loadout characteristics. (c)(1...

7 CFR 1435.105 - Loan settlement and foreclosure.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program...) Forfeiture of sugar loan collateral will be accepted as payment in full of the principal and interest due... specifications reported on the sugar loan certification report and actual loadout characteristics. (c)(1...

7 CFR 1435.103 - Availability, disbursement, and maturity of loans.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.103 Availability, disbursement, and maturity of loans. (a) Before obtaining a... on sugar or in-process sugar pledged as loan collateral, obtain waivers that fully protect CCC's...

7 CFR 1435.105 - Loan settlement and foreclosure.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program...) Forfeiture of sugar loan collateral will be accepted as payment in full of the principal and interest due... specifications reported on the sugar loan certification report and actual loadout characteristics. (c)(1...

7 CFR 1435.103 - Availability, disbursement, and maturity of loans.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.103 Availability, disbursement, and maturity of loans. (a) Before obtaining a... on sugar or in-process sugar pledged as loan collateral, obtain waivers that fully protect CCC's...

7 CFR 1435.601 - Sugar surplus determination and public announcement.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Sugar surplus determination and public announcement...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Feedstock Flexibility Program § 1435.601 Sugar surplus determination and public announcement. (a) CCC will...

7 CFR 1435.105 - Loan settlement and foreclosure.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program...) Forfeiture of sugar loan collateral will be accepted as payment in full of the principal and interest due... specifications reported on the sugar loan certification report and actual loadout characteristics. (c)(1...

7 CFR 1435.103 - Availability, disbursement, and maturity of loans.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.103 Availability, disbursement, and maturity of loans. (a) Before obtaining a... on sugar or in-process sugar pledged as loan collateral, obtain waivers that fully protect CCC's...

7 CFR 1435.105 - Loan settlement and foreclosure.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program...) Forfeiture of sugar loan collateral will be accepted as payment in full of the principal and interest due... specifications reported on the sugar loan certification report and actual loadout characteristics. (c)(1...

Antidumping Action in the United States and Around the World: An Analysis of International Data. CBO Paper.

DTIC Science & Technology

1998-06-01

the price of sugar to the point that some processors, such as soft-drink producers, have replaced it with high - fructose corn syrup . That example...United States, both one on one and in the aggregate. Antidumping duty rates are high enough to be significant impediments to trade, especially the duties...the United States, although their rates are still high enough to be significant impediments to trade. Among the most active users, Canada had the next

7 CFR 1530.101 - Definitions.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE...-packers. Bond or letter of credit means an insurance agreement pledging surety for the entry of foreign sugar without the required re-export within the program guidelines. Certain polyhydric alcohols means...

75 FR 23631 - Sugar Re-Export Program, the Sugar-Containing Products Re-Export Program, and the Polyhydric...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-05-04

...), Additional U.S. Note 6, which authorizes entry of raw cane sugar under subheading 1701.11.20 of the HTS for..., or to be substituted for domestically produced raw cane sugar that has been or will be exported. The...

78 FR 25415 - Waivers Under the Refined Sugar Re-Export Program

Federal Register 2010, 2011, 2012, 2013, 2014

2013-05-01

... license amounts and provide greater flexibility to offset exports and transfers with raw sugar imports...-Export Program, refiners may enter raw sugar unrestricted by the quantitative limit established for the raw sugar tariff-rate quota or the requirements of certificates of quota eligibility provided for in...

7 CFR 1435.102 - Eligibility requirements.

Code of Federal Regulations, 2010 CFR

2010-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.102... sugar beets or sugarcane, including share rent landowners, at both the time of harvest and the time of... CFR part 718. (b) In addition to all other provisions of this part, a sugar beet or sugarcane...

7 CFR 1435.101 - Loan rates.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.101 Loan rates. (a) The national average loan rate for raw cane sugar produced from domestically grown sugarcane is: 18... for the 2012 crop year. (b) The national average loan rate for refined beet sugar from domestically...

7 CFR 1435.101 - Loan rates.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.101 Loan rates. (a) The national average loan rate for raw cane sugar produced from domestically grown sugarcane is: 18... for the 2012 crop year. (b) The national average loan rate for refined beet sugar from domestically...

7 CFR 1435.102 - Eligibility requirements.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.102... sugar beets or sugarcane, including share rent landowners, at both the time of harvest and the time of... CFR part 718. (b) In addition to all other provisions of this part, a sugar beet or sugarcane...

7 CFR 1435.101 - Loan rates.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.101 Loan rates. (a) The national average loan rate for raw cane sugar produced from domestically grown sugarcane is: 18... for the 2012 crop year. (b) The national average loan rate for refined beet sugar from domestically...

7 CFR 1435.102 - Eligibility requirements.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.102... sugar beets or sugarcane, including share rent landowners, at both the time of harvest and the time of... CFR part 718. (b) In addition to all other provisions of this part, a sugar beet or sugarcane...

7 CFR 1435.101 - Loan rates.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.101 Loan rates. (a) The national average loan rate for raw cane sugar produced from domestically grown sugarcane is: 18... for the 2012 crop year. (b) The national average loan rate for refined beet sugar from domestically...

7 CFR 1435.101 - Loan rates.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.101 Loan rates. (a) The national average loan rate for raw cane sugar produced from domestically grown sugarcane is: 18... for the 2012 crop year. (b) The national average loan rate for refined beet sugar from domestically...

7 CFR 1435.102 - Eligibility requirements.

Code of Federal Regulations, 2014 CFR

2014-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.102... sugar beets or sugarcane, including share rent landowners, at both the time of harvest and the time of... CFR part 718. (b) In addition to all other provisions of this part, a sugar beet or sugarcane...

7 CFR 1435.102 - Eligibility requirements.

Code of Federal Regulations, 2012 CFR

2012-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.102... sugar beets or sugarcane, including share rent landowners, at both the time of harvest and the time of... CFR part 718. (b) In addition to all other provisions of this part, a sugar beet or sugarcane...

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Meteorological Processors and Accessory Programs

EPA Pesticide Factsheets

Surface and upper air data, provided by NWS, are important inputs for air quality models. Before these data are used in some of the EPA dispersion models, meteorological processors are used to manipulate the data.

50 CFR 679.50 - Groundfish Observer Program.

Code of Federal Regulations, 2012 CFR

2012-10-01

... completion of the electronic vessel and/or processor survey(s); (B) Complete NMFS electronic vessel and/or processor surveys before performing other jobs or duties which are not part of NMFS groundfish observer...

50 CFR 679.50 - Groundfish Observer Program.

Code of Federal Regulations, 2011 CFR

2011-10-01

... completion of the electronic vessel and/or processor survey(s); (B) Complete NMFS electronic vessel and/or processor surveys before performing other jobs or duties which are not part of NMFS groundfish observer...

Developing a Contemporary Dairy Foods Extension Program: A Training and Technical Resource Needs Assessment of Pennsylvania Dairy Foods Processors

ERIC Educational Resources Information Center

Syrko, Joseph; Kaylegian, Kerry E.

2015-01-01

Growth in the dairy industry and the passage of the Food Safety Modernization Act have renewed interest in dairy foods processing extension positions. A needs assessment survey was sent to Pennsylvania dairy processors and raw milk providers to guide priorities for a dairy foods extension program. The successful development and delivery of…

7 CFR 1530.105 - Terms and conditions.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM...) shall, not later than 90 days after entering a quantity of raw cane sugar under subheading 1701.11.20 of the HTS, export or transfer an equivalent quantity of refined sugar if the entry results in a positive...

7 CFR 1530.104 - Application for a license.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM... of any co-packer(s); (4) In the case of a refined sugar product, the polarity of the product and the formula proposed by the refiner for calculating the refined sugar in the product; (5) In the case of a...

7 CFR 1530.104 - Application for a license.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM... of any co-packer(s); (4) In the case of a refined sugar product, the polarity of the product and the formula proposed by the refiner for calculating the refined sugar in the product; (5) In the case of a...

Conditional load and store in a shared memory

DOEpatents

Blumrich, Matthias A; Ohmacht, Martin

2015-02-03

A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

NASA Astrophysics Data System (ADS)

Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

2018-02-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

Preliminary study on the potential usefulness of array processor techniques for structural synthesis

NASA Technical Reports Server (NTRS)

Feeser, L. J.

1980-01-01

The effects of the use of array processor techniques within the structural analyzer program, SPAR, are simulated in order to evaluate the potential analysis speedups which may result. In particular the connection of a Floating Point System AP120 processor to the PRIME computer is discussed. Measurements of execution, input/output, and data transfer times are given. Using these data estimates are made as to the relative speedups that can be executed in a more complete implementation on an array processor maxi-mini computer system.

Advanced development of a programmable power processor

NASA Technical Reports Server (NTRS)

Lukens, F. E.; Lanier, J. R., Jr.; Kapustka, R. E.; Graves, J.

1980-01-01

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

Database interfaces on NASA's heterogeneous distributed database system

NASA Technical Reports Server (NTRS)

Huang, Shou-Hsuan Stephen

1987-01-01

The purpose of Distributed Access View Integrated Database (DAVID) interface module (Module 9: Resident Primitive Processing Package) is to provide data transfer between local DAVID systems and resident Data Base Management Systems (DBMSs). The result of current research is summarized. A detailed description of the interface module is provided. Several Pascal templates were constructed. The Resident Processor program was also developed. Even though it is designed for the Pascal templates, it can be modified for templates in other languages, such as C, without much difficulty. The Resident Processor itself can be written in any programming language. Since Module 5 routines are not ready yet, there is no way to test the interface module. However, simulation shows that the data base access programs produced by the Resident Processor do work according to the specifications.

System and method for bearing fault detection using stator current noise cancellation

DOEpatents

Zhou, Wei; Lu, Bin; Habetler, Thomas G.; Harley, Ronald G.; Theisen, Peter J.

2010-08-17

A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to repeatedly receive real-time operating current data from the operating motor and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components.

Extended performance electric propulsion power processor design study. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30cm ion thruster power processor with a beam supply rating of 2.2kW to 10kW. Extensions in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. Preliminary electrical design, mechanical design, and thermal analysis were performed on a 6kW power transformer for the beam supply. Bi-Mod mechanical, structural, and thermal control configurations were evaluated for the power processor, and preliminary estimates of mechanical weight were determined. A program development plan was formulated that outlines the work breakdown structure for the development, qualification and fabrication of the power processor flight hardware.

50 CFR 660.160 - Catcher/processor (C/P) Coop Program.

Code of Federal Regulations, 2013 CFR

2013-10-01

... not be accepted unless it includes all of the required information; the descriptive items listed in... deployment by the completion of the electronic vessel and/or processor survey(s); and (E) Immediately report...

50 CFR 660.160 - Catcher/processor (C/P) Coop Program.

Code of Federal Regulations, 2012 CFR

2012-10-01

... not be accepted unless it includes all of the required information; the descriptive items listed in... deployment by the completion of the electronic vessel and/or processor survey(s); and (E) Immediately report...

50 CFR 660.160 - Catcher/processor (C/P) Coop Program.

Code of Federal Regulations, 2014 CFR

2014-10-01

... not be accepted unless it includes all of the required information; the descriptive items listed in... the completion of the electronic vessel and/or processor survey(s); and (E) Immediately report to the...

50 CFR 660.160 - Catcher/processor (C/P) Coop Program.

Code of Federal Regulations, 2011 CFR

2011-10-01

... information; the descriptive items listed in this paragraph appear to meet the stated purpose; and information... deployment by the completion of the electronic vessel and/or processor survey(s); and (E) Immediately report...

Reduced power processor requirements for the 30-cm diameter HG ion thruster

NASA Technical Reports Server (NTRS)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

3-D parallel program for numerical calculation of gas dynamics problems with heat conductivity on distributed memory computational systems (CS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sofronov, I.D.; Voronin, B.L.; Butnev, O.I.

1997-12-31

The aim of the work performed is to develop a 3D parallel program for numerical calculation of gas dynamics problem with heat conductivity on distributed memory computational systems (CS), satisfying the condition of numerical result independence from the number of processors involved. Two basically different approaches to the structure of massive parallel computations have been developed. The first approach uses the 3D data matrix decomposition reconstructed at temporal cycle and is a development of parallelization algorithms for multiprocessor CS with shareable memory. The second approach is based on using a 3D data matrix decomposition not reconstructed during a temporal cycle.more » The program was developed on 8-processor CS MP-3 made in VNIIEF and was adapted to a massive parallel CS Meiko-2 in LLNL by joint efforts of VNIIEF and LLNL staffs. A large number of numerical experiments has been carried out with different number of processors up to 256 and the efficiency of parallelization has been evaluated in dependence on processor number and their parameters.« less

Discrete sensitivity derivatives of the Navier-Stokes equations with a parallel Krylov solver

NASA Technical Reports Server (NTRS)

Ajmani, Kumud; Taylor, Arthur C., III

1994-01-01

This paper solves an 'incremental' form of the sensitivity equations derived by differentiating the discretized thin-layer Navier Stokes equations with respect to certain design variables of interest. The equations are solved with a parallel, preconditioned Generalized Minimal RESidual (GMRES) solver on a distributed-memory architecture. The 'serial' sensitivity analysis code is parallelized by using the Single Program Multiple Data (SPMD) programming model, domain decomposition techniques, and message-passing tools. Sensitivity derivatives are computed for low and high Reynolds number flows over a NACA 1406 airfoil on a 32-processor Intel Hypercube, and found to be identical to those computed on a single-processor Cray Y-MP. It is estimated that the parallel sensitivity analysis code has to be run on 40-50 processors of the Intel Hypercube in order to match the single-processor processing time of a Cray Y-MP.

Software Acquisition Manager’s Workstation (SAM/WS) System Design.

DTIC Science & Technology

1984-04-30

3. Tactical Digital System Requirements ..................... 31General...pspc t14 3. Tactical Digital System Requirements pspc-tiS 3.1 General pspc-t16 3.2 Program Description pspc-t17 3.2.1 General...pspc-t22 3.3.2 Digital Processor Input/Output Utilization Table pspc t23 3.3.3 Digital Processor Interface Block Diagram pspc-t24 3.3.4 Program

DOE Office of Scientific and Technical Information (OSTI.GOV)

Burge, S.W.

This report describes the FORCE2 flow program input, output, and the graphical post-processor. The manual describes the steps for creating the model, executing the programs and processing the results into graphical form. The FORCE2 post-processor was developed as an interactive program written in FORTRAN-77. It uses the Graphical Kernel System (GKS) graphics standard recently adopted by International Organization for Standardization, ISO, and American National Standards Institute, ANSI, and, therefore, can be used with many terminals. The post-processor vas written with Calcomp subroutine calls and is compatible with Tektkonix terminals and Calcomp and Nicolet pen plotters. B&W has been developing themore » FORCE2 code as a general-purpose tool for flow analysis of B&W equipment. The version of FORCE2 described in this manual was developed under the sponsorship of ASEA-Babcock as part of their participation in the joint R&D venture, ``Erosion of FBC Heat Transfer Tubes,`` and is applicable to the analyses of bubbling fluid beds. This manual is the principal documentation for program usage and is segmented into several sections to facilitate usage. In Section 2.0 the program is described, including assumptions, capabilities, limitations and uses, program status and location, related programs and program hardware and software requirements. Section 3.0 is a quick user`s reference guide for preparing input, executing FORCE2, and using the post-processor. Section 4.0 is a detailed description of the FORCE2 input. In Section 5.0, FORCE2 output is summarized. Section 6.0 contains a sample application, and Section 7.0 is a detailed reference guide.« less

The Event Based Language and Its Multiple Processor Implementations.

DTIC Science & Technology

1980-01-01

10 6.1 "Recursive" Linear Fibonacci ................................................ 105 6.2 The Readers Writers Problem...kinds. Examples of such systems are: C.mmp [Wu-72], Pluribus [He-73], Data Flow [ De -75], the boolean n-cube parallel machine [Su-77], and the MuNet [Wa...concurrency within programs; therefore, we hate concentrated on two types of systems which seem suitable: a processor network, and a data flow processor [ De -77

Design for a Manufacturing Method for Memristor-Based Neuromorphic Computing Processors

DTIC Science & Technology

2013-03-01

DESIGN FOR A MANUFACTURING METHOD FOR MEMRISTOR- BASED NEUROMORPHIC COMPUTING PROCESSORS UNIVERSITY OF PITTSBURGH MARCH 2013...BASED NEUROMORPHIC COMPUTING PROCESSORS 5a. CONTRACT NUMBER FA8750-11-1-0271 5b. GRANT NUMBER N/A 5c. PROGRAM ELEMENT NUMBER 62788F 6. AUTHOR(S...synapses and implemented a neuromorphic computing system based on our proposed synapse designs. The robustness of our system is also evaluated by

76 FR 62339 - Domestic Sugar Program-2011-Crop Cane Sugar and Beet Sugar Marketing Allotments and Company...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-07

... Sugar and Beet Sugar Marketing Allotments and Company Allocations AGENCY: Commodity Credit Corporation... the fiscal year (FY) 2012 State sugar marketing allotments and company allocations to sugarcane and... required to publish the determinations establishing, adjusting, or suspending sugar marketing allotments in...

Scheduler for multiprocessor system switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael Karl; Salapura, Valentina

2015-01-06

System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Total and Free Sugar Content of Canadian Prepackaged Foods and Beverages.

PubMed

Bernstein, Jodi T; Schermel, Alyssa; Mills, Christine M; L'Abbé, Mary R

2016-09-21

A number of recommendations for policy and program interventions to limit excess free sugar consumption have emerged, however there are a lack of data describing the amounts and types of sugar in foods. This study presents an assessment of sugar in Canadian prepackaged foods including: (a) the first systematic calculation of free sugar contents; (b) a comprehensive assessment of total sugar and free sugar levels; and (c) sweetener and free sugar ingredient use, using the University of Toronto's Food Label Information Program (FLIP) database 2013 ( n = 15,342). Food groups with the highest proportion of foods containing free sugar ingredients also had the highest median total sugar and free sugar contents (per 100 g/mL): desserts (94%, 15 g, and 12 g), sugars and sweets (91%, 50 g, and 50 g), and bakery products (83%, 16 g, and 14 g, proportion with free sugar ingredients, median total sugar and free sugar content in Canadian foods, respectively). Free sugar accounted for 64% of total sugar content. Eight of 17 food groups had ≥75% of the total sugar derived from free sugar. Free sugar contributed 20% of calories overall in prepackaged foods and beverages, with the highest at 70% in beverages. These data can be used to inform interventions aimed at limiting free sugar consumption.

Total and Free Sugar Content of Canadian Prepackaged Foods and Beverages

PubMed Central

Bernstein, Jodi T.; Schermel, Alyssa; Mills, Christine M.; L’Abbé, Mary R.

2016-01-01

A number of recommendations for policy and program interventions to limit excess free sugar consumption have emerged, however there are a lack of data describing the amounts and types of sugar in foods. This study presents an assessment of sugar in Canadian prepackaged foods including: (a) the first systematic calculation of free sugar contents; (b) a comprehensive assessment of total sugar and free sugar levels; and (c) sweetener and free sugar ingredient use, using the University of Toronto’s Food Label Information Program (FLIP) database 2013 (n = 15,342). Food groups with the highest proportion of foods containing free sugar ingredients also had the highest median total sugar and free sugar contents (per 100 g/mL): desserts (94%, 15 g, and 12 g), sugars and sweets (91%, 50 g, and 50 g), and bakery products (83%, 16 g, and 14 g, proportion with free sugar ingredients, median total sugar and free sugar content in Canadian foods, respectively). Free sugar accounted for 64% of total sugar content. Eight of 17 food groups had ≥75% of the total sugar derived from free sugar. Free sugar contributed 20% of calories overall in prepackaged foods and beverages, with the highest at 70% in beverages. These data can be used to inform interventions aimed at limiting free sugar consumption. PMID:27657125

Ssip-a processor interconnection simulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Navaux, P.; Weber, R.; Prezzi, J.

1982-01-01

Recent growing interest in multiple processor architectures has given rise to the study of procesor-memory interconnections for the determination of better architectures. This paper concerns the development of the SSIP-sistema simulador de interconexao de processadores (processor interconnection simulating system) which allows the evaluation of different interconnection structures comparing its performance in order to provide parameters which would help the designer to define an architcture. A wide spectrum of systems may be evaluated, and their behaviour observed due to the features incorporated into the simulator program. The system modelling and the simulator program implementation are described. Some results that can bemore » obtained are shown, along with the discussion of their usefulness. 12 references.« less

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

NASA Astrophysics Data System (ADS)

Hayashi, Akihiro; Wada, Yasutaka; Watanabe, Takeshi; Sekiguchi, Takeshi; Mase, Masayoshi; Shirako, Jun; Kimura, Keiji; Kasahara, Hironori

Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

77 FR 50561 - Livestock Mandatory Reporting Program; Establishment of the Reporting Regulation for Wholesale Pork

Federal Register 2010, 2011, 2012, 2013, 2014

2012-08-22

... regulatory text outlined in this final rule. Reporting Requirements Pork processors, or packers, will be... pork, processors of pork, retailers of pork, and buyers of wholesale pork; (iii) the USDA; and (iv... [[Page 50562

Enabling Future Robotic Missions with Multicore Processors

NASA Technical Reports Server (NTRS)

Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

2011-01-01

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

Detailed description of the HP-9825A HFRMP trajectory processor (TRAJ)

NASA Technical Reports Server (NTRS)

Kindall, S. M.; Wilson, S. W.

1979-01-01

The computer code for the trajectory processor of the HP-9825A High Fidelity Relative Motion Program is described in detail. The processor is a 12-degrees-of-freedom trajectory integrator which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. Coding standards and flow charts are given and the computational logic is discussed.

Parallel processing in a host plus multiple array processor system for radar

NASA Technical Reports Server (NTRS)

Barkan, B. Z.

1983-01-01

Host plus multiple array processor architecture is demonstrated to yield a modular, fast, and cost-effective system for radar processing. Software methodology for programming such a system is developed. Parallel processing with pipelined data flow among the host, array processors, and discs is implemented. Theoretical analysis of performance is made and experimentally verified. The broad class of problems to which the architecture and methodology can be applied is indicated.

A High Performance VLSI Computer Architecture For Computer Graphics

NASA Astrophysics Data System (ADS)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

NASA Technical Reports Server (NTRS)

Goldberg, J.; Kautz, W. H.; Melliar-Smith, P. M.; Green, M. W.; Levitt, K. N.; Schwartz, R. L.; Weinstock, C. B.

1984-01-01

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

7 CFR 1530.109 - Reporting.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... transaction; (2) The date of the entry, transfer (only a refiner shall report transfers to the Licensing... license number; (5) The country of origin (entry of raw sugar) or final destination (refined exports...

7 CFR 1530.109 - Reporting.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... transaction; (2) The date of the entry, transfer (only a refiner shall report transfers to the Licensing... license number; (5) The country of origin (entry of raw sugar) or final destination (refined exports...

7 CFR 1530.109 - Reporting.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... transaction; (2) The date of the entry, transfer (only a refiner shall report transfers to the Licensing... license number; (5) The country of origin (entry of raw sugar) or final destination (refined exports...

7 CFR 1530.109 - Reporting.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... transaction; (2) The date of the entry, transfer (only a refiner shall report transfers to the Licensing... license number; (5) The country of origin (entry of raw sugar) or final destination (refined exports...

7 CFR 1530.109 - Reporting.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM, AND THE... transaction; (2) The date of the entry, transfer (only a refiner shall report transfers to the Licensing... license number; (5) The country of origin (entry of raw sugar) or final destination (refined exports...

One Way of Testing a Distributed Processor

NASA Technical Reports Server (NTRS)

Edstrom, R.; Kleckner, D.

1982-01-01

Launch processing for Space Shuttle is checked out, controlled, and monitored with new system. Entire system can be exercised by two computer programs--one in master console and other in each of operations consoles. Control program in each operations console detects change in status and begins task initiation. All of front-end processors are exercised from consoles through common data buffer, and all data are logged to processed-data recorder for posttest analysis.

Automatic differentiation for design sensitivity analysis of structural systems using multiple processors

NASA Technical Reports Server (NTRS)

Nguyen, Duc T.; Storaasli, Olaf O.; Qin, Jiangning; Qamar, Ramzi

1994-01-01

An automatic differentiation tool (ADIFOR) is incorporated into a finite element based structural analysis program for shape and non-shape design sensitivity analysis of structural systems. The entire analysis and sensitivity procedures are parallelized and vectorized for high performance computation. Small scale examples to verify the accuracy of the proposed program and a medium scale example to demonstrate the parallel vector performance on multiple CRAY C90 processors are included.

VIEW-Station software and its graphical user interface

NASA Astrophysics Data System (ADS)

Kawai, Tomoaki; Okazaki, Hiroshi; Tanaka, Koichiro; Tamura, Hideyuki

1992-04-01

VIEW-Station is a workstation-based image processing system which merges the state-of-the- art software environment of Unix with the computing power of a fast image processor. VIEW- Station has a hierarchical software architecture, which facilitates device independence when porting across various hardware configurations, and provides extensibility in the development of application systems. The core image computing language is V-Sugar. V-Sugar provides a set of image-processing datatypes and allows image processing algorithms to be simply expressed, using a functional notation. VIEW-Station provides a hardware independent window system extension called VIEW-Windows. In terms of GUI (Graphical User Interface) VIEW-Station has two notable aspects. One is to provide various types of GUI as visual environments for image processing execution. Three types of interpreters called (mu) V- Sugar, VS-Shell and VPL are provided. Users may choose whichever they prefer based on their experience and tasks. The other notable aspect is to provide facilities to create GUI for new applications on the VIEW-Station system. A set of widgets are available for construction of task-oriented GUI. A GUI builder called VIEW-Kid is developed for WYSIWYG interactive interface design.

System and method for motor fault detection using stator current noise cancellation

DOEpatents

Zhou, Wei; Lu, Bin; Nowak, Michael P.; Dimino, Steven A.

2010-12-07

A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to acquire at least on additional set of real-time operating current data from the motor during operation, redefine the noise component present in each additional set of real-time operating current data, and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components.

Converted and upgraded maps programmed in the newer speech processor for the first generation of multichannel cochlear implant.

PubMed

Magalhães, Ana Tereza de Matos; Goffi-Gomez, M Valéria Schmidt; Hoshino, Ana Cristina; Tsuji, Robinson Koji; Bento, Ricardo Ferreira; Brito, Rubens

2013-09-01

To identify the technological contributions of the newer version of speech processor to the first generation of multichannel cochlear implant and the satisfaction of users of the new technology. Among the new features available, we focused on the effect of the frequency allocation table, the T-SPL and C-SPL, and the preprocessing gain adjustments (adaptive dynamic range optimization). Prospective exploratory study. Cochlear implant center at hospital. Cochlear implant users of the Spectra processor with speech recognition in closed set. Seventeen patients were selected between the ages of 15 and 82 and deployed for more than 8 years. The technology update of the speech processor for the Nucleus 22. To determine Freedom's contribution, thresholds and speech perception tests were performed with the last map used with the Spectra and the maps created for Freedom. To identify the effect of the frequency allocation table, both upgraded and converted maps were programmed. One map was programmed with 25 dB T-SPL and 65 dB C-SPL and the other map with adaptive dynamic range optimization. To assess satisfaction, SADL and APHAB were used. All speech perception tests and all sound field thresholds were statistically better with the new speech processor; 64.7% of patients preferred maintaining the same frequency table that was suggested for the older processor. The sound field threshold was statistically significant at 500, 1,000, 1,500, and 2,000 Hz with 25 dB T-SPL/65 dB C-SPL. Regarding patient's satisfaction, there was a statistically significant improvement, only in the subscale of speech in noise abilities and phone use. The new technology improved the performance of patients with the first generation of multichannel cochlear implant.

Proton exchange membrane fuel cell technology for transportation applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swathirajan, S.

1996-04-01

Proton Exchange Membrane (PEM) fuel cells are extremely promising as future power plants in the transportation sector to achieve an increase in energy efficiency and eliminate environmental pollution due to vehicles. GM is currently involved in a multiphase program with the US Department of Energy for developing a proof-of-concept hybrid vehicle based on a PEM fuel cell power plant and a methanol fuel processor. Other participants in the program are Los Alamos National Labs, Dow Chemical Co., Ballard Power Systems and DuPont Co., In the just completed phase 1 of the program, a 10 kW PEM fuel cell power plantmore » was built and tested to demonstrate the feasibility of integrating a methanol fuel processor with a PEM fuel cell stack. However, the fuel cell power plant must overcome stiff technical and economic challenges before it can be commercialized for light duty vehicle applications. Progress achieved in phase I on the use of monolithic catalyst reactors in the fuel processor, managing CO impurity in the fuel cell stack, low-cost electrode-membrane assembles, and on the integration of the fuel processor with a Ballard PEM fuel cell stack will be presented.« less

Shuttle cryogenics supply system. Optimization study. Volume 5 B-2, part 1: Appendix programmers manual for math model

NASA Technical Reports Server (NTRS)

1973-01-01

An appendix to the programmers manual for the mathematical model pertaining to the design of cryogenic supply systems for spacecraft is presented. The program listing was produced using the EXEC-8 LISTALL processor which lists a file in alphabetical order. Since the processor does not differentiate between subroutines, functions, and procedure definition processors, each subprogram has been relabeled to clearly identify the type of symbolic listing.

Effects of input processing and type of personal frequency modulation system on speech-recognition performance of adults with cochlear implants.

PubMed

Wolfe, Jace; Schafer, Erin; Parkinson, Aaron; John, Andrew; Hudson, Mary; Wheeler, Julie; Mucci, Angie

2013-01-01

The objective of this study was to compare speech recognition in quiet and in noise for cochlear implant recipients using two different types of personal frequency modulation (FM) systems (directly coupled [direct auditory input] versus induction neckloop) with each of two sound processors (Cochlear Nucleus Freedom versus Cochlear Nucleus 5). Two different experiments were conducted within this study. In both these experiments, mixing of the FM signal within the Freedom processor was implemented via the same scheme used clinically for the Freedom sound processor. In Experiment 1, the aforementioned comparisons were conducted with the Nucleus 5 programmed so that the microphone and FM signals were mixed and then the mixed signals were subjected to autosensitivity control (ASC). In Experiment 2, comparisons between the two FM systems and processors were conducted again with the Nucleus 5 programmed to provide a more complex multistage implementation of ASC during the preprocessing stage. This study was a within-subject, repeated-measures design. Subjects were recruited from the patient population at the Hearts for Hearing Foundation in Oklahoma City, OK. Fifteen subjects participated in Experiment 1, and 16 subjects participated in Experiment 2. Subjects were adults who had used either unilateral or bilateral cochlear implants for at least 1 year. In this experiment, no differences were found in speech recognition in quiet obtained with the two different FM systems or the various sound-processor conditions. With each sound processor, speech recognition in noise was better with the directly coupled direct auditory input system relative to the neckloop system. The multistage ASC processing of the Nucleus 5 sound processor provided better performance than the single-stage approach for the Nucleus 5 and the Nucleus Freedom sound processor. Speech recognition in noise is substantially affected by the type of sound processor, FM system, and implementation of ASC used by a Cochlear implant recipient.

Ethernet-Enabled Power and Communication Module for Embedded Processors

NASA Technical Reports Server (NTRS)

Perotti, Jose; Oostdyk, Rebecca

2010-01-01

The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

Fault detection and bypass in a sequence information signal processor

NASA Technical Reports Server (NTRS)

Peterson, John C. (Inventor); Chow, Edward T. (Inventor)

1992-01-01

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

7 CFR 1530.102 - Nature of the license.

Code of Federal Regulations, 2010 CFR

2010-01-01

... subheading 1701.11.20 of the HTS, and export an equivalent quantity of refined sugar onto the world market or transfer an equivalent quantity of refined sugar to licensees under the Sugar Containing Products Re-export... Program or Polyhydric Alcohol Program permits licensees to receive transfers and export an equivalent...

7 CFR 1530.102 - Nature of the license.

Code of Federal Regulations, 2014 CFR

2014-01-01

... subheading 1701.11.20 of the HTS, and export an equivalent quantity of refined sugar onto the world market or transfer an equivalent quantity of refined sugar to licensees under the Sugar Containing Products Re-export... Program or Polyhydric Alcohol Program permits licensees to receive transfers and export an equivalent...

7 CFR 1530.102 - Nature of the license.

Code of Federal Regulations, 2012 CFR

2012-01-01

... subheading 1701.11.20 of the HTS, and export an equivalent quantity of refined sugar onto the world market or transfer an equivalent quantity of refined sugar to licensees under the Sugar Containing Products Re-export... Program or Polyhydric Alcohol Program permits licensees to receive transfers and export an equivalent...

7 CFR 1530.102 - Nature of the license.

Code of Federal Regulations, 2011 CFR

2011-01-01

... subheading 1701.11.20 of the HTS, and export an equivalent quantity of refined sugar onto the world market or transfer an equivalent quantity of refined sugar to licensees under the Sugar Containing Products Re-export... Program or Polyhydric Alcohol Program permits licensees to receive transfers and export an equivalent...

7 CFR 1530.102 - Nature of the license.

Code of Federal Regulations, 2013 CFR

2013-01-01

... subheading 1701.11.20 of the HTS, and export an equivalent quantity of refined sugar onto the world market or transfer an equivalent quantity of refined sugar to licensees under the Sugar Containing Products Re-export... Program or Polyhydric Alcohol Program permits licensees to receive transfers and export an equivalent...

50 CFR 679.50 - Groundfish Observer Program.

Code of Federal Regulations, 2010 CFR

2010-10-01

... following: (A) Identification of the management, organizational structure, and ownership structure of the.../processors. A catcher/processor will be assigned to a fishery category based on the retained groundfish catch... in Federal waters will be assigned to a fishery category based on the retained groundfish catch...

Data processing with microcode designed with source coding

DOEpatents

McCoy, James A; Morrison, Steven E

2013-05-07

Programming for a data processor to execute a data processing application is provided using microcode source code. The microcode source code is assembled to produce microcode that includes digital microcode instructions with which to signal the data processor to execute the data processing application.

7 CFR 1435.304 - Beet and cane sugar allotments.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Beet and cane sugar allotments. 1435.304 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.304 Beet and cane sugar allotments. (a) The allotment for beet sugar will be 54.35...

7 CFR 1435.304 - Beet and cane sugar allotments.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 10 2011-01-01 2011-01-01 false Beet and cane sugar allotments. 1435.304 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.304 Beet and cane sugar allotments. (a) The allotment for beet sugar will be 54.35...

7 CFR 1435.304 - Beet and cane sugar allotments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 10 2013-01-01 2013-01-01 false Beet and cane sugar allotments. 1435.304 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.304 Beet and cane sugar allotments. (a) The allotment for beet sugar will be 54.35...

7 CFR 1435.304 - Beet and cane sugar allotments.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 10 2012-01-01 2012-01-01 false Beet and cane sugar allotments. 1435.304 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.304 Beet and cane sugar allotments. (a) The allotment for beet sugar will be 54.35...

7 CFR 1435.304 - Beet and cane sugar allotments.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Beet and cane sugar allotments. 1435.304 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.304 Beet and cane sugar allotments. (a) The allotment for beet sugar will be 54.35...

Contemporary issues in HIM. The application layer--III.

PubMed

Wear, L L; Pinkert, J R

1993-07-01

We have seen document preparation systems evolve from basic line editors through powerful, sophisticated desktop publishing programs. This component of the application layer is probably one of the most used, and most readily identifiable. Ask grade school children nowadays, and many will tell you that they have written a paper on a computer. Next month will be a "fun" tour through a number of other application programs we find useful. They will range from a simple notebook reminder to a sophisticated photograph processor. Application layer: Software targeted for the end user, focusing on a specific application area, and typically residing in the computer system as distinct components on top of the OS. Desktop publishing: A document preparation program that begins with the text features of a word processor, then adds the ability for a user to incorporate outputs from a variety of graphic programs, spreadsheets, and other applications. Line editor: A document preparation program that manipulates text in a file on the basis of numbered lines. Word processor: A document preparation program that can, among other things, reformat sections of documents, move and replace blocks of text, use multiple character fonts, automatically create a table of contents and index, create complex tables, and combine text and graphics.

Parallel hyperbolic PDE simulation on clusters: Cell versus GPU

NASA Astrophysics Data System (ADS)

Rostrup, Scott; De Sterck, Hans

2010-12-01

Increasingly, high-performance computing is looking towards data-parallel computational devices to enhance computational performance. Two technologies that have received significant attention are IBM's Cell Processor and NVIDIA's CUDA programming model for graphics processing unit (GPU) computing. In this paper we investigate the acceleration of parallel hyperbolic partial differential equation simulation on structured grids with explicit time integration on clusters with Cell and GPU backends. The message passing interface (MPI) is used for communication between nodes at the coarsest level of parallelism. Optimizations of the simulation code at the several finer levels of parallelism that the data-parallel devices provide are described in terms of data layout, data flow and data-parallel instructions. Optimized Cell and GPU performance are compared with reference code performance on a single x86 central processing unit (CPU) core in single and double precision. We further compare the CPU, Cell and GPU platforms on a chip-to-chip basis, and compare performance on single cluster nodes with two CPUs, two Cell processors or two GPUs in a shared memory configuration (without MPI). We finally compare performance on clusters with 32 CPUs, 32 Cell processors, and 32 GPUs using MPI. Our GPU cluster results use NVIDIA Tesla GPUs with GT200 architecture, but some preliminary results on recently introduced NVIDIA GPUs with the next-generation Fermi architecture are also included. This paper provides computational scientists and engineers who are considering porting their codes to accelerator environments with insight into how structured grid based explicit algorithms can be optimized for clusters with Cell and GPU accelerators. It also provides insight into the speed-up that may be gained on current and future accelerator architectures for this class of applications. Program summaryProgram title: SWsolver Catalogue identifier: AEGY_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEGY_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: GPL v3 No. of lines in distributed program, including test data, etc.: 59 168 No. of bytes in distributed program, including test data, etc.: 453 409 Distribution format: tar.gz Programming language: C, CUDA Computer: Parallel Computing Clusters. Individual compute nodes may consist of x86 CPU, Cell processor, or x86 CPU with attached NVIDIA GPU accelerator. Operating system: Linux Has the code been vectorised or parallelized?: Yes. Tested on 1-128 x86 CPU cores, 1-32 Cell Processors, and 1-32 NVIDIA GPUs. RAM: Tested on Problems requiring up to 4 GB per compute node. Classification: 12 External routines: MPI, CUDA, IBM Cell SDK Nature of problem: MPI-parallel simulation of Shallow Water equations using high-resolution 2D hyperbolic equation solver on regular Cartesian grids for x86 CPU, Cell Processor, and NVIDIA GPU using CUDA. Solution method: SWsolver provides 3 implementations of a high-resolution 2D Shallow Water equation solver on regular Cartesian grids, for CPU, Cell Processor, and NVIDIA GPU. Each implementation uses MPI to divide work across a parallel computing cluster. Additional comments: Sub-program numdiff is used for the test run.

7 CFR 1435.302 - Establishment of allotments.

Code of Federal Regulations, 2010 CFR

2010-01-01

..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.302 Establishment of allotments. (a) By the beginning of the crop year, CCC will establish the overall allotment quantity, beet sugar and cane sugar allotments, State cane sugar allotments...

7 CFR 1435.302 - Establishment of allotments.

Code of Federal Regulations, 2011 CFR

2011-01-01

..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.302 Establishment of allotments. (a) By the beginning of the crop year, CCC will establish the overall allotment quantity, beet sugar and cane sugar allotments, State cane sugar allotments...

7 CFR 1435.302 - Establishment of allotments.

Code of Federal Regulations, 2013 CFR

2013-01-01

..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.302 Establishment of allotments. (a) By the beginning of the crop year, CCC will establish the overall allotment quantity, beet sugar and cane sugar allotments, State cane sugar allotments...

7 CFR 1435.302 - Establishment of allotments.

Code of Federal Regulations, 2012 CFR

2012-01-01

..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.302 Establishment of allotments. (a) By the beginning of the crop year, CCC will establish the overall allotment quantity, beet sugar and cane sugar allotments, State cane sugar allotments...

7 CFR 1435.302 - Establishment of allotments.

Code of Federal Regulations, 2014 CFR

2014-01-01

..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.302 Establishment of allotments. (a) By the beginning of the crop year, CCC will establish the overall allotment quantity, beet sugar and cane sugar allotments, State cane sugar allotments...

Parallel computation for biological sequence comparison: comparing a portable model to the native model for the Intel Hypercube.

PubMed

Nadkarni, P M; Miller, P L

1991-01-01

A parallel program for inter-database sequence comparison was developed on the Intel Hypercube using two models of parallel programming. One version was built using machine-specific Hypercube parallel programming commands. The other version was built using Linda, a machine-independent parallel programming language. The two versions of the program provide a case study comparing these two approaches to parallelization in an important biological application area. Benchmark tests with both programs gave comparable results with a small number of processors. As the number of processors was increased, the Linda version was somewhat less efficient. The Linda version was also run without change on Network Linda, a virtual parallel machine running on a network of desktop workstations.

A Tutorial on Parallel and Concurrent Programming in Haskell

NASA Astrophysics Data System (ADS)

Peyton Jones, Simon; Singh, Satnam

This practical tutorial introduces the features available in Haskell for writing parallel and concurrent programs. We first describe how to write semi-explicit parallel programs by using annotations to express opportunities for parallelism and to help control the granularity of parallelism for effective execution on modern operating systems and processors. We then describe the mechanisms provided by Haskell for writing explicitly parallel programs with a focus on the use of software transactional memory to help share information between threads. Finally, we show how nested data parallelism can be used to write deterministically parallel programs which allows programmers to use rich data types in data parallel programs which are automatically transformed into flat data parallel versions for efficient execution on multi-core processors.

Hot Chips and Hot Interconnects for High End Computing Systems

NASA Technical Reports Server (NTRS)

Saini, Subhash

2005-01-01

I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

A Methodolgy, Based on Analytical Modeling, for the Design of Parallel and Distributed Architectures for Relational Database Query Processors.

DTIC Science & Technology

1987-12-01

Application Programs Intelligent Disk Database Controller Manangement System Operating System Host .1’ I% Figure 2. Intelligent Disk Controller Application...8217. /- - • Database Control -% Manangement System Disk Data Controller Application Programs Operating Host I"" Figure 5. Processor-Per- Head data. Therefore, the...However. these ad- ditional properties have been proven in classical set and relation theory [75]. These additional properties are described here

Parallel processors and nonlinear structural dynamics algorithms and software

NASA Technical Reports Server (NTRS)

Belytschko, Ted

1990-01-01

Techniques are discussed for the implementation and improvement of vectorization and concurrency in nonlinear explicit structural finite element codes. In explicit integration methods, the computation of the element internal force vector consumes the bulk of the computer time. The program can be efficiently vectorized by subdividing the elements into blocks and executing all computations in vector mode. The structuring of elements into blocks also provides a convenient way to implement concurrency by creating tasks which can be assigned to available processors for evaluation. The techniques were implemented in a 3-D nonlinear program with one-point quadrature shell elements. Concurrency and vectorization were first implemented in a single time step version of the program. Techniques were developed to minimize processor idle time and to select the optimal vector length. A comparison of run times between the program executed in scalar, serial mode and the fully vectorized code executed concurrently using eight processors shows speed-ups of over 25. Conjugate gradient methods for solving nonlinear algebraic equations are also readily adapted to a parallel environment. A new technique for improving convergence properties of conjugate gradients in nonlinear problems is developed in conjunction with other techniques such as diagonal scaling. A significant reduction in the number of iterations required for convergence is shown for a statically loaded rigid bar suspended by three equally spaced springs.

A proposed microcomputer implementation of an Omega navigation processor

NASA Technical Reports Server (NTRS)

Abel, J. D.

1976-01-01

A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

System-wide power management control via clock distribution network

DOEpatents

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

2015-05-19

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

High Performance Processors for Space Environments: A Subproject of the NASA Exploration Missions Systems Directorate "Radiation Hardened Electronics for Space Environments" Technology Development Program

NASA Technical Reports Server (NTRS)

Johnson, M.; Label, K.; McCabe, J.; Powell, W.; Bolotin, G.; Kolawa, E.; Ng, T.; Hyde, D.

2007-01-01

Implementation of challenging Exploration Systems Missions Directorate objectives and strategies can be constrained by onboard computing capabilities and power efficiencies. The Radiation Hardened Electronics for Space Environments (RHESE) High Performance Processors for Space Environments project will address this challenge by significantly advancing the sustained throughput and processing efficiency of high-per$ormance radiation-hardened processors, targeting delivery of products by the end of FY12.

The 3D laser radar vision processor system

NASA Astrophysics Data System (ADS)

Sebok, T. M.

1990-10-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

The 3D laser radar vision processor system

NASA Technical Reports Server (NTRS)

Sebok, T. M.

1990-01-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

Multi-Core Programming Design Patterns: Stream Processing Algorithms for Dynamic Scene Perceptions

DTIC Science & Technology

2014-05-01

processor developed by IBM and other companies , incorpo- rates the verb—POWER5— processor as the Power Processor Element (PPE), one of the early general...deliver an power efficient single-precision peak performance of more than 256 GFlops. Substantially more raw power became available later, when nVIDIA ...algorithms, including IBM’s Cell/B.E., GPUs from NVidia and AMD and many-core CPUs from Intel.27 The vast growth of digital video content has been a

Single bus star connected reluctance drive and method

DOEpatents

Fahimi, Babak; Shamsi, Pourya

2016-05-10

A system and methods for operating a switched reluctance machine includes a controller, an inverter connected to the controller and to the switched reluctance machine, a hysteresis control connected to the controller and to the inverter, a set of sensors connected to the switched reluctance machine and to the controller, the switched reluctance machine further including a set of phases the controller further comprising a processor and a memory connected to the processor, wherein the processor programmed to execute a control process and a generation process.

7 CFR 1160.604 - Duties of the referendum agent.

Code of Federal Regulations, 2010 CFR

2010-01-01

... SERVICE (Marketing Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM... voting period the total volume of fluid milk products marketed by all processors of fluid milk in the... properly registered. Any challenge of a processor's eligibility to vote must be received by the referendum...

Gyro and Accelerometer Based Navigation System for a Mobile Autonomous Robot.

DTIC Science & Technology

1985-12-02

special thanks goes to our thesis advisor Dr. Matthew Kabrisky for having the confidence to turn us loose on this project. Additionally, we would...Wordmaster Word Processor 1 Wordstar Word Processor 1 Virtual Devices Robo A 6802 Cross Assembler 1 Modem 720 Communication Program 1 CP/M Operating

7 CFR 1435.305 - State cane sugar allotments.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false State cane sugar allotments. 1435.305 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.305 State cane sugar allotments. (a) Hawaii and Puerto Rico will be allotted a total...

7 CFR 1435.305 - State cane sugar allotments.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 10 2011-01-01 2011-01-01 false State cane sugar allotments. 1435.305 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.305 State cane sugar allotments. (a) Hawaii and Puerto Rico will be allotted a total...

7 CFR 1435.305 - State cane sugar allotments.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false State cane sugar allotments. 1435.305 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.305 State cane sugar allotments. (a) Hawaii and Puerto Rico will be allotted a total...

7 CFR 1435.305 - State cane sugar allotments.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 10 2012-01-01 2012-01-01 false State cane sugar allotments. 1435.305 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.305 State cane sugar allotments. (a) Hawaii and Puerto Rico will be allotted a total...

7 CFR 1435.305 - State cane sugar allotments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 10 2013-01-01 2013-01-01 false State cane sugar allotments. 1435.305 Section 1435..., DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.305 State cane sugar allotments. (a) Hawaii and Puerto Rico will be allotted a total...

76 FR 64839 - Sugar Program; Feedstock Flexibility Program for Bioenergy Producers

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-19

... increase and that high fructose corn syrup (HFCS) use in Mexico continues to be strong (but not as strong..., in- process sugar products such as beet thick juice or cane syrup are eligible. Since the program...

Parallel programming with Easy Java Simulations

NASA Astrophysics Data System (ADS)

Esquembre, F.; Christian, W.; Belloni, M.

2018-01-01

Nearly all of today's processors are multicore, and ideally programming and algorithm development utilizing the entire processor should be introduced early in the computational physics curriculum. Parallel programming is often not introduced because it requires a new programming environment and uses constructs that are unfamiliar to many teachers. We describe how we decrease the barrier to parallel programming by using a java-based programming environment to treat problems in the usual undergraduate curriculum. We use the easy java simulations programming and authoring tool to create the program's graphical user interface together with objects based on those developed by Kaminsky [Building Parallel Programs (Course Technology, Boston, 2010)] to handle common parallel programming tasks. Shared-memory parallel implementations of physics problems, such as time evolution of the Schrödinger equation, are available as source code and as ready-to-run programs from the AAPT-ComPADRE digital library.

Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals

DOEpatents

Balasubramonian, Rajeev [Sandy, UT; Dwarkadas, Sandhya [Rochester, NY; Albonesi, David [Ithaca, NY

2009-02-10

In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.

Ray tissues as an indirect measure of relative sap-sugar concentration in sugar maple

Treesearch

Peter W. Garrett; Kenneth R. Dudzik; Kenneth R. Dudzik

1989-01-01

Attempts to correlate ray tissue as a percentage of total wood volume with sap-sugar concentrations of sugar maple progenies were unsuccessful. These results raise doubts about our ability to use a relatively constant value such as ray-tissue volume in a selection program designed to increase the sap-sugar concentration of sugar maple seedlings.

A Programming Framework for Scientific Applications on CPU-GPU Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Owens, John

2013-03-24

At a high level, my research interests center around designing, programming, and evaluating computer systems that use new approaches to solve interesting problems. The rapid change of technology allows a variety of different architectural approaches to computationally difficult problems, and a constantly shifting set of constraints and trends makes the solutions to these problems both challenging and interesting. One of the most important recent trends in computing has been a move to commodity parallel architectures. This sea change is motivated by the industry’s inability to continue to profitably increase performance on a single processor and instead to move to multiplemore » parallel processors. In the period of review, my most significant work has been leading a research group looking at the use of the graphics processing unit (GPU) as a general-purpose processor. GPUs can potentially deliver superior performance on a broad range of problems than their CPU counterparts, but effectively mapping complex applications to a parallel programming model with an emerging programming environment is a significant and important research problem.« less

Transputer parallel processing at NASA Lewis Research Center

NASA Technical Reports Server (NTRS)

Ellis, Graham K.

1989-01-01

The transputer parallel processing lab at NASA Lewis Research Center (LeRC) consists of 69 processors (transputers) that can be connected into various networks for use in general purpose concurrent processing applications. The main goal of the lab is to develop concurrent scientific and engineering application programs that will take advantage of the computational speed increases available on a parallel processor over the traditional sequential processor. Current research involves the development of basic programming tools. These tools will help standardize program interfaces to specific hardware by providing a set of common libraries for applications programmers. The thrust of the current effort is in developing a set of tools for graphics rendering/animation. The applications programmer currently has two options for on-screen plotting. One option can be used for static graphics displays and the other can be used for animated motion. The option for static display involves the use of 2-D graphics primitives that can be called from within an application program. These routines perform the standard 2-D geometric graphics operations in real-coordinate space as well as allowing multiple windows on a single screen.

Real-time trajectory optimization on parallel processors

NASA Technical Reports Server (NTRS)

Psiaki, Mark L.

1993-01-01

A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

Advanced satellite communication system

NASA Technical Reports Server (NTRS)

Staples, Edward J.; Lie, Sen

1992-01-01

The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.

Semi-Automated Identification of Rocks in Images

NASA Technical Reports Server (NTRS)

Bornstein, Benjamin; Castano, Andres; Anderson, Robert

2006-01-01

Rock Identification Toolkit Suite is a computer program that assists users in identifying and characterizing rocks shown in images returned by the Mars Explorer Rover mission. Included in the program are components for automated finding of rocks, interactive adjustments of outlines of rocks, active contouring of rocks, and automated analysis of shapes in two dimensions. The program assists users in evaluating the surface properties of rocks and soil and reports basic properties of rocks. The program requires either the Mac OS X operating system running on a G4 (or more capable) processor or a Linux operating system running on a Pentium (or more capable) processor, plus at least 128MB of random-access memory.

Parallel computation for biological sequence comparison: comparing a portable model to the native model for the Intel Hypercube.

PubMed Central

Nadkarni, P. M.; Miller, P. L.

1991-01-01

A parallel program for inter-database sequence comparison was developed on the Intel Hypercube using two models of parallel programming. One version was built using machine-specific Hypercube parallel programming commands. The other version was built using Linda, a machine-independent parallel programming language. The two versions of the program provide a case study comparing these two approaches to parallelization in an important biological application area. Benchmark tests with both programs gave comparable results with a small number of processors. As the number of processors was increased, the Linda version was somewhat less efficient. The Linda version was also run without change on Network Linda, a virtual parallel machine running on a network of desktop workstations. PMID:1807632

7 CFR 1435.400 - General statement.

Code of Federal Regulations, 2014 CFR

2014-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Disposition of CCC Inventory...-process sugar is owned and held in CCC inventory (accumulated under the program authorized by section 156...

78 FR 38286 - Notice of Change to the CCC Sugar Purchase and Exchange To Include Certificates of Quota...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-06-26

... DEPARTMENT OF AGRICULTURE Commodity Credit Corporation Notice of Change to the CCC Sugar Purchase... TPA) in the sugar purchase and exchange announced on June 18, 2013. DATES: Effective date: June 26... (voice and TDD). SUPPLEMENTARY INFORMATION: USDA's Sugar Program and the Domestic Sugar Market Conditions...

75 FR 10756 - Proposed Information Collection; Comment Request; Amendment 80 Economic Data Report for the...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-09

... Collection; Comment Request; Amendment 80 Economic Data Report for the Catcher/Processor Non-AFA Trawl Sector... catcher/processor sector. The Amendment 80 economic data report (EDR) collects cost, revenue, ownership... review the Program. The purpose of the EDR is to understand the economic effects of the Amendment 80...

The Educational Effects of Word Processors. County of Lacombe No. 14.

ERIC Educational Resources Information Center

Spence, Gary

The main purpose of this 8-month study was to determine whether significant differences in student learning and attitudes occur as a result of the use of word processors, but curriculum changes, inservice teacher requirements, obstacles to incorporating word processing into language arts programs, effective teaching strategies, and effective…

77 FR 38463 - Implementation of National Organic Program (NOP); Sunset Review (2012) Amendments to Pectin on...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-28

... operations to reformulate their products until October 21, 2012. SUPPLEMENTARY INFORMATION: The Organic Foods... processors are currently using amidated, non-organic pectin in their products. The industry indicated that these processors would need time to reformulate these products using either non-amidated, non-organic...

A Framework for a Quality Control System for Vendor/Processor Contracts.

ERIC Educational Resources Information Center

Advanced Technology, Inc., Reston, VA.

A framework for monitoring quality control (QC) of processor contracts administered by the Department of Education's Office of Student Financial Assistance (OSFA) is presented and applied to the Pell Grant program. Guidelines for establishing QC measures and standards are included, and the uses of a sampling procedure in the QC system are…

Distributed memory compiler methods for irregular problems: Data copy reuse and runtime partitioning

NASA Technical Reports Server (NTRS)

Das, Raja; Ponnusamy, Ravi; Saltz, Joel; Mavriplis, Dimitri

1991-01-01

Outlined here are two methods which we believe will play an important role in any distributed memory compiler able to handle sparse and unstructured problems. We describe how to link runtime partitioners to distributed memory compilers. In our scheme, programmers can implicitly specify how data and loop iterations are to be distributed between processors. This insulates users from having to deal explicitly with potentially complex algorithms that carry out work and data partitioning. We also describe a viable mechanism for tracking and reusing copies of off-processor data. In many programs, several loops access the same off-processor memory locations. As long as it can be verified that the values assigned to off-processor memory locations remain unmodified, we show that we can effectively reuse stored off-processor data. We present experimental data from a 3-D unstructured Euler solver run on iPSC/860 to demonstrate the usefulness of our methods.

Parallel machine architecture for production rule systems

DOEpatents

Allen, Jr., John D.; Butler, Philip L.

1989-01-01

A parallel processing system for production rule programs utilizes a host processor for storing production rule right hand sides (RHS) and a plurality of rule processors for storing left hand sides (LHS). The rule processors operate in parallel in the recognize phase of the system recognize -Act Cycle to match their respective LHS's against a stored list of working memory elements (WME) in order to find a self consistent set of WME's. The list of WME is dynamically varied during the Act phase of the system in which the host executes or fires rule RHS's for those rules for which a self-consistent set has been found by the rule processors. The host transmits instructions for creating or deleting working memory elements as dictated by the rule firings until the rule processors are unable to find any further self-consistent working memory element sets at which time the production rule system is halted.

The scaling issue: scientific opportunities

NASA Astrophysics Data System (ADS)

Orbach, Raymond L.

2009-07-01

A brief history of the Leadership Computing Facility (LCF) initiative is presented, along with the importance of SciDAC to the initiative. The initiative led to the initiation of the Innovative and Novel Computational Impact on Theory and Experiment program (INCITE), open to all researchers in the US and abroad, and based solely on scientific merit through peer review, awarding sizeable allocations (typically millions of processor-hours per project). The development of the nation's LCFs has enabled available INCITE processor-hours to double roughly every eight months since its inception in 2004. The 'top ten' LCF accomplishments in 2009 illustrate the breadth of the scientific program, while the 75 million processor hours allocated to American business since 2006 highlight INCITE contributions to US competitiveness. The extrapolation of INCITE processor hours into the future brings new possibilities for many 'classic' scaling problems. Complex systems and atomic displacements to cracks are but two examples. However, even with increasing computational speeds, the development of theory, numerical representations, algorithms, and efficient implementation are required for substantial success, exhibiting the crucial role that SciDAC will play.

Software-defined reconfigurable microwave photonics processor.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

HP-9825A HFRMP trajectory processor (#TRAJ), detailed description. [relative motion of the space shuttle orbiter and a free-flying payload

NASA Technical Reports Server (NTRS)

Kindall, S. M.

1980-01-01

The computer code for the trajectory processor (#TRAJ) of the high fidelity relative motion program is described. The #TRAJ processor is a 12-degrees-of-freedom trajectory integrator (6 degrees of freedom for each of two vehicles) which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. A listing of the code, coding standards and conventions, detailed flow charts, and discussions of the computational logic are included.

MBASIC batch processor architectural overview

NASA Technical Reports Server (NTRS)

Reynolds, S. M.

1978-01-01

The MBASIC (TM) batch processor, a language translator designed to operate in the MBASIC (TM) environment is described. Features include: (1) a CONVERT TO BATCH command, usable from the ready mode; and (2) translation of the users program in stages through several levels of intermediate language and optimization. The processor is to be designed and implemented in both machine-independent and machine-dependent sections. The architecture is planned so that optimization processes are transparent to the rest of the system and need not be included in the first design implementation cycle.

Literal algebra for satellite dynamics. [perturbation analysis

NASA Technical Reports Server (NTRS)

Gaposchkin, E. M.

1975-01-01

A description of the rather general class of operations available is given and the operations are related to problems in satellite dynamics. The implementation of an algebra processor is discussed. The four main categories of symbol processors are related to list processing, string manipulation, symbol manipulation, and formula manipulation. Fundamental required operations for an algebra processor are considered. It is pointed out that algebra programs have been used for a number of problems in celestial mechanics with great success. The advantage of computer algebra is its accuracy and speed.

Proximity Operations Nano-Satellite Flight Demonstration (PONSFD) Rendezvous Proximity Operations Design and Trade Studies

NASA Astrophysics Data System (ADS)

Griesbach, J.; Westphal, J. J.; Roscoe, C.; Hawes, D. R.; Carrico, J. P.

2013-09-01

The Proximity Operations Nano-Satellite Flight Demonstration (PONSFD) program is to demonstrate rendezvous proximity operations (RPO), formation flying, and docking with a pair of 3U CubeSats. The program is sponsored by NASA Ames via the Office of the Chief Technologist (OCT) in support of its Small Spacecraft Technology Program (SSTP). The goal of the mission is to demonstrate complex RPO and docking operations with a pair of low-cost 3U CubeSat satellites using passive navigation sensors. The program encompasses the entire system evolution including system design, acquisition, satellite construction, launch, mission operations, and final disposal. The satellite is scheduled for launch in Fall 2015 with a 1-year mission lifetime. This paper provides a brief mission overview but will then focus on the current design and driving trade study results for the RPO mission specific processor and relevant ground software. The current design involves multiple on-board processors, each specifically tasked with providing mission critical capabilities. These capabilities range from attitude determination and control to image processing. The RPO system processor is responsible for absolute and relative navigation, maneuver planning, attitude commanding, and abort monitoring for mission safety. A low power processor running a Linux operating system has been selected for implementation. Navigation is one of the RPO processor's key tasks. This entails processing data obtained from the on-board GPS unit as well as the on-board imaging sensors. To do this, Kalman filters will be hosted on the processor to ingest and process measurements for maintenance of position and velocity estimates with associated uncertainties. While each satellite carries a GPS unit, it will be used sparsely to conserve power. As such, absolute navigation will mainly consist of propagating past known states, and relative navigation will be considered to be of greater importance. For relative observations, each spacecraft hosts 3 electro-optical sensors dedicated to imaging the companion satellite. The image processor will analyze the images to obtain estimates for range, bearing, and pose, with associated rates and uncertainties. These observations will be fed to the RPO processor's relative Kalman filter to perform relative navigation updates. This paper includes estimates for expected navigation accuracies for both absolute and relative position and velocity. Another key task for the RPO processor is maneuver planning. This includes automation to plan maneuvers to achieve a desired formation configuration or trajectory (including docking), as well as automation to safely react to potentially dangerous situations. This will allow each spacecraft to autonomously plan fuel-efficient maneuvers to achieve a desired trajectory as well as compute adjustment maneuvers to correct for thrusting errors. This paper discusses results from a trade study that has been conducted to examine maneuver targeting algorithms required on-board the spacecraft. Ground software will also work in conjunction with the on-board software to validate and approve maneuvers as necessary.

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

A programmable power processor for a 25-kW power module

NASA Technical Reports Server (NTRS)

Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

1979-01-01

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

Set processing in a network environment. [data bases and magnetic disks and tapes

NASA Technical Reports Server (NTRS)

Hardgrave, W. T.

1975-01-01

A combination of a local network, a mass storage system, and an autonomous set processor serving as a data/storage management machine is described. Its characteristics include: content-accessible data bases usable from all connected devices; efficient storage/access of large data bases; simple and direct programming with data manipulation and storage management handled by the set processor; simple data base design and entry from source representation to set processor representation with no predefinition necessary; capability available for user sort/order specification; significant reduction in tape/disk pack storage and mounts; flexible environment that allows upgrading hardware/software configuration without causing major interruptions in service; minimal traffic on data communications network; and improved central memory usage on large processors.

RASSP signal processing architectures

NASA Astrophysics Data System (ADS)

Shirley, Fred; Bassett, Bob; Letellier, J. P.

1995-06-01

The rapid prototyping of application specific signal processors (RASSP) program is an ARPA/tri-service effort to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are specified, designed, documented, manufactured, and supported. The domain of embedded signal processing was chosen because it is important to a variety of military and commercial applications as well as for the challenge it presents in terms of complexity and performance demands. The principal effort is being performed by two major contractors, Lockheed Sanders (Nashua, NH) and Martin Marietta (Camden, NJ). For both, improvements in methodology are to be exercised and refined through the performance of individual 'Demonstration' efforts. The Lockheed Sanders' Demonstration effort is to develop an infrared search and track (IRST) processor. In addition, both contractors' results are being measured by a series of externally administered (by Lincoln Labs) six-month Benchmark programs that measure process improvement as a function of time. The first two Benchmark programs are designing and implementing a synthetic aperture radar (SAR) processor. Our demonstration team is using commercially available VME modules from Mercury Computer to assemble a multiprocessor system scalable from one to hundreds of Intel i860 microprocessors. Custom modules for the sensor interface and display driver are also being developed. This system implements either proprietary or Navy owned algorithms to perform the compute-intensive IRST function in real time in an avionics environment. Our Benchmark team is designing custom modules using commercially available processor ship sets, communication submodules, and reconfigurable logic devices. One of the modules contains multiple vector processors optimized for fast Fourier transform processing. Another module is a fiberoptic interface that accepts high-rate input data from the sensors and provides video-rate output data to a display. This paper discusses the impact of simulation on choosing signal processing algorithms and architectures, drawing from the experiences of the Demonstration and Benchmark inter-company teams at Lockhhed Sanders, Motorola, Hughes, and ISX.

7 CFR 1435.308 - New entrants.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... demonstrate their ability to process, produce, and market sugar for the applicable crop year, (2) CCC will... a new facility or reopens a facility that currently has no allocation, but last produced beet sugar...

7 CFR 1435.308 - New entrants.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... demonstrate their ability to process, produce, and market sugar for the applicable crop year, (2) CCC will... a new facility or reopens a facility that currently has no allocation, but last produced beet sugar...

7 CFR 1435.308 - New entrants.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... demonstrate their ability to process, produce, and market sugar for the applicable crop year, (2) CCC will... a new facility or reopens a facility that currently has no allocation, but last produced beet sugar...

7 CFR 1435.308 - New entrants.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... demonstrate their ability to process, produce, and market sugar for the applicable crop year, (2) CCC will... a new facility or reopens a facility that currently has no allocation, but last produced beet sugar...

7 CFR 1435.308 - New entrants.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar... demonstrate their ability to process, produce, and market sugar for the applicable crop year, (2) CCC will... a new facility or reopens a facility that currently has no allocation, but last produced beet sugar...

ms2: A molecular simulation tool for thermodynamic properties

NASA Astrophysics Data System (ADS)

Deublein, Stephan; Eckl, Bernhard; Stoll, Jürgen; Lishchuk, Sergey V.; Guevara-Carrion, Gabriela; Glass, Colin W.; Merker, Thorsten; Bernreuther, Martin; Hasse, Hans; Vrabec, Jadran

2011-11-01

This work presents the molecular simulation program ms2 that is designed for the calculation of thermodynamic properties of bulk fluids in equilibrium consisting of small electro-neutral molecules. ms2 features the two main molecular simulation techniques, molecular dynamics (MD) and Monte-Carlo. It supports the calculation of vapor-liquid equilibria of pure fluids and multi-component mixtures described by rigid molecular models on the basis of the grand equilibrium method. Furthermore, it is capable of sampling various classical ensembles and yields numerous thermodynamic properties. To evaluate the chemical potential, Widom's test molecule method and gradual insertion are implemented. Transport properties are determined by equilibrium MD simulations following the Green-Kubo formalism. ms2 is designed to meet the requirements of academia and industry, particularly achieving short response times and straightforward handling. It is written in Fortran90 and optimized for a fast execution on a broad range of computer architectures, spanning from single processor PCs over PC-clusters and vector computers to high-end parallel machines. The standard Message Passing Interface (MPI) is used for parallelization and ms2 is therefore easily portable to different computing platforms. Feature tools facilitate the interaction with the code and the interpretation of input and output files. The accuracy and reliability of ms2 has been shown for a large variety of fluids in preceding work. Program summaryProgram title:ms2 Catalogue identifier: AEJF_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEJF_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Special Licence supplied by the authors No. of lines in distributed program, including test data, etc.: 82 794 No. of bytes in distributed program, including test data, etc.: 793 705 Distribution format: tar.gz Programming language: Fortran90 Computer: The simulation tool ms2 is usable on a wide variety of platforms, from single processor machines over PC-clusters and vector computers to vector-parallel architectures. (Tested with Fortran compilers: gfortran, Intel, PathScale, Portland Group and Sun Studio.) Operating system: Unix/Linux, Windows Has the code been vectorized or parallelized?: Yes. Message Passing Interface (MPI) protocol Scalability. Excellent scalability up to 16 processors for molecular dynamics and >512 processors for Monte-Carlo simulations. RAM:ms2 runs on single processors with 512 MB RAM. The memory demand rises with increasing number of processors used per node and increasing number of molecules. Classification: 7.7, 7.9, 12 External routines: Message Passing Interface (MPI) Nature of problem: Calculation of application oriented thermodynamic properties for rigid electro-neutral molecules: vapor-liquid equilibria, thermal and caloric data as well as transport properties of pure fluids and multi-component mixtures. Solution method: Molecular dynamics, Monte-Carlo, various classical ensembles, grand equilibrium method, Green-Kubo formalism. Restrictions: No. The system size is user-defined. Typical problems addressed by ms2 can be solved by simulating systems containing typically 2000 molecules or less. Unusual features: Feature tools are available for creating input files, analyzing simulation results and visualizing molecular trajectories. Additional comments: Sample makefiles for multiple operation platforms are provided. Documentation is provided with the installation package and is available at http://www.ms-2.de. Running time: The running time of ms2 depends on the problem set, the system size and the number of processes used in the simulation. Running four processes on a "Nehalem" processor, simulations calculating VLE data take between two and twelve hours, calculating transport properties between six and 24 hours.

75 FR 60715 - Domestic Sugar Program-FY 2010 and FY 2011 Cane Sugar and Beet Sugar Marketing Allotments and...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-10-01

...,716 Hawaii Gay & Robinson, Inc 72,401 -18,673 -50,592 3,136 Hawaiian Commercial & Sugar Company... & Sons 495,489 Total Louisiana 1,620,472 Texas: Rio Grande Valley 182,094 Hawaii: Gay & Robinson, Inc 73...

DRACULA: Dynamic range control for broadcasting and other applications

NASA Astrophysics Data System (ADS)

Gilchrist, N. H. C.

The BBC has developed a digital processor which is capable of reducing the dynamic range of audio in an unobtrusive manner. It is ideally suited to the task of controlling the level of musical programs. Operating as a self-contained dynamic range controller, the processor is suitable for controlling levels in conventional AM or FM broadcasting, or for applications such as the compression of program material for in-flight entertainment. It can, alternatively, be used to provide a supplementary signal in DAB (digital audio broadcasting) for optional dynamic compression in the receiver.

Measurement of fault latency in a digital avionic mini processor, part 2

NASA Technical Reports Server (NTRS)

Mcgough, J.; Swern, F.

1983-01-01

The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are described. Several earlier programs were reprogrammed, expanding the instruction set to capitalize on the full power of the BDX-930 computer. As a final demonstration of fault coverage an extensive, 3-axis, high performance flght control computation was added. The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated.

Stream Processors

NASA Astrophysics Data System (ADS)

Erez, Mattan; Dally, William J.

Stream processors, like other multi core architectures partition their functional units and storage into multiple processing elements. In contrast to typical architectures, which contain symmetric general-purpose cores and a cache hierarchy, stream processors have a significantly leaner design. Stream processors are specifically designed for the stream execution model, in which applications have large amounts of explicit parallel computation, structured and predictable control, and memory accesses that can be performed at a coarse granularity. Applications in the streaming model are expressed in a gather-compute-scatter form, yielding programs with explicit control over transferring data to and from on-chip memory. Relying on these characteristics, which are common to many media processing and scientific computing applications, stream architectures redefine the boundary between software and hardware responsibilities with software bearing much of the complexity required to manage concurrency, locality, and latency tolerance. Thus, stream processors have minimal control consisting of fetching medium- and coarse-grained instructions and executing them directly on the many ALUs. Moreover, the on-chip storage hierarchy of stream processors is under explicit software control, as is all communication, eliminating the need for complex reactive hardware mechanisms.

40 CFR 180.408 - Metalaxyl; tolerances for residues.

Code of Federal Regulations, 2013 CFR

2013-07-01

...) PESTICIDE PROGRAMS TOLERANCES AND EXEMPTIONS FOR PESTICIDE CHEMICAL RESIDUES IN FOOD Specific Tolerances...-(methoxyacetyl)-alanine methyl ester, each expressed as metalaxyl equivalents, in or on the following food... Beet, garden, tops 0.1 Beet, sugar 0.1 Beet, sugar, molasses 1.0 Beet, sugar, roots 0.5 Beet, sugar...

40 CFR 180.408 - Metalaxyl; tolerances for residues.

Code of Federal Regulations, 2014 CFR

2014-07-01

...) PESTICIDE PROGRAMS TOLERANCES AND EXEMPTIONS FOR PESTICIDE CHEMICAL RESIDUES IN FOOD Specific Tolerances...-(methoxyacetyl)-alanine methyl ester, each expressed as metalaxyl equivalents, in or on the following food... Beet, garden, tops 0.1 Beet, sugar 0.1 Beet, sugar, molasses 1.0 Beet, sugar, roots 0.5 Beet, sugar...

40 CFR 180.408 - Metalaxyl; tolerances for residues.

Code of Federal Regulations, 2012 CFR

2012-07-01

...) PESTICIDE PROGRAMS TOLERANCES AND EXEMPTIONS FOR PESTICIDE CHEMICAL RESIDUES IN FOOD Specific Tolerances...-(methoxyacetyl)-alanine methyl ester, each expressed as metalaxyl equivalents, in or on the following food... Beet, garden, tops 0.1 Beet, sugar 0.1 Beet, sugar, molasses 1.0 Beet, sugar, roots 0.5 Beet, sugar...

7 CFR 1530.106 - License charges and credits.

Code of Federal Regulations, 2011 CFR

2011-01-01

..., DEPARTMENT OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT... charged or credited for the quantity of sugar entered, transferred, exported, or used, adjusted to a dry... 100 degrees polarity on a dry weight basis. (1) To adjust the raw value for sugar with a polarization...

7 CFR 1530.107 - Bond or letter of credit requirements

Code of Federal Regulations, 2010 CFR

2010-01-01

... SERVICE, DEPARTMENT OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE... export of sugar in sugar containing products, or the production of certain polyhydric alcohols, if the... product, or produce certain polyhydric alcohols may be the principal on the bond or letter of credit...

7 CFR 1435.401 - CCC sugar inventory disposition.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false CCC sugar inventory disposition. 1435.401 Section... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Disposition of CCC Inventory § 1435.401 CCC sugar inventory disposition. (a) CCC will dispose of inventory in the following...

78 FR 8434 - Dairy Tariff-Rate Import Quota Licensing Program

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

..., hand delivery, or courier: Abdelsalam El-Farra, Agricultural Marketing Specialist, Sugar and Dairy...-Farra, Agricultural Marketing Specialist, Sugar and Dairy Branch, Import Programs and Export Reporting..., February 6, 2013 / Proposed Rules#0;#0; [[Page 8434

Embedded Data Processor and Portable Computer Technology testbeds

NASA Technical Reports Server (NTRS)

Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

1993-01-01

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Advanced Avionics and Processor Systems for Space and Lunar Exploration

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Ray, Robert E.; Johnson, Michael A.; Cressler, John D.

2009-01-01

NASA's newly named Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to mature and develop the avionic and processor technologies required to fulfill NASA's goals for future space and lunar exploration. Over the past year, multiple advancements have been made within each of the individual AAPS technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of the project's recent technology advancements, discusses their application to Constellation projects, and addresses the project's plans for the coming year.

Software design and documentation language, revision 1

NASA Technical Reports Server (NTRS)

Kleine, H.

1979-01-01

The Software Design and Documentation Language (SDDL) developed to provide an effective communications medium to support the design and documentation of complex software applications is described. Features of the system include: (1) a processor which can convert design specifications into an intelligible, informative machine-reproducible document; (2) a design and documentation language with forms and syntax that are simple, unrestrictive, and communicative; and (3) methodology for effective use of the language and processor. The SDDL processor is written in the SIMSCRIPT II programming language and is implemented on the UNIVAC 1108, the IBM 360/370, and Control Data machines.

ALI: A CSSL/multiprocessor software interface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Makoui, A.; Karplus, W.J.

ALI (A Language Interface) is a software package which translates simulation models expressed in one of the higher-level languages, CSSL-IV or ACSL, into sequences of instructions for each processor of a network of microprocessors. The partitioning of the source program among the processors is automatically accomplished. The code is converted into a data flow graph, analyzed and divided among the processors to minimize the overall execution time in the presence of interprocessor communication delays. This paper describes ALI from the user's point of view and includes a detailed example of the application of ALI to a specific dynamic system simulation.

Multiprocessor switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

2014-03-11

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

Is random access memory random?

NASA Technical Reports Server (NTRS)

Denning, P. J.

1986-01-01

Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

Method for simultaneous overlapped communications between neighboring processors in a multiple

DOEpatents

Benner, Robert E.; Gustafson, John L.; Montry, Gary R.

1991-01-01

A parallel computing system and method having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system.

A message passing kernel for the hypercluster parallel processing test bed

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Quealy, Angela; Cole, Gary L.

1989-01-01

A Message-Passing Kernel (MPK) for the Hypercluster parallel-processing test bed is described. The Hypercluster is being developed at the NASA Lewis Research Center to support investigations of parallel algorithms and architectures for computational fluid and structural mechanics applications. The Hypercluster resembles the hypercube architecture except that each node consists of multiple processors communicating through shared memory. The MPK efficiently routes information through the Hypercluster, using a message-passing protocol when necessary and faster shared-memory communication whenever possible. The MPK also interfaces all of the processors with the Hypercluster operating system (HYCLOPS), which runs on a Front-End Processor (FEP). This approach distributes many of the I/O tasks to the Hypercluster processors and eliminates the need for a separate I/O support program on the FEP.

Combining high performance simulation, data acquisition, and graphics display computers

NASA Technical Reports Server (NTRS)

Hickman, Robert J.

1989-01-01

Issues involved in the continuing development of an advanced simulation complex are discussed. This approach provides the capability to perform the majority of tests on advanced systems, non-destructively. The controlled test environments can be replicated to examine the response of the systems under test to alternative treatments of the system control design, or test the function and qualification of specific hardware. Field tests verify that the elements simulated in the laboratories are sufficient. The digital computer is hosted by a Digital Equipment Corp. MicroVAX computer with an Aptec Computer Systems Model 24 I/O computer performing the communication function. An Applied Dynamics International AD100 performs the high speed simulation computing and an Evans and Sutherland PS350 performs on-line graphics display. A Scientific Computer Systems SCS40 acts as a high performance FORTRAN program processor to support the complex, by generating numerous large files from programs coded in FORTRAN that are required for the real time processing. Four programming languages are involved in the process, FORTRAN, ADSIM, ADRIO, and STAPLE. FORTRAN is employed on the MicroVAX host to initialize and terminate the simulation runs on the system. The generation of the data files on the SCS40 also is performed with FORTRAN programs. ADSIM and ADIRO are used to program the processing elements of the AD100 and its IOCP processor. STAPLE is used to program the Aptec DIP and DIA processors.

A new implementation of the programming system for structural synthesis (PROSSS-2)

NASA Technical Reports Server (NTRS)

Rogers, James L., Jr.

1984-01-01

This new implementation of the PROgramming System for Structural Synthesis (PROSSS-2) combines a general-purpose finite element computer program for structural analysis, a state-of-the-art optimization program, and several user-supplied, problem-dependent computer programs. The results are flexibility of the optimization procedure, organization, and versatility of the formulation of constraints and design variables. The analysis-optimization process results in a minimized objective function, typically the mass. The analysis and optimization programs are executed repeatedly by looping through the system until the process is stopped by a user-defined termination criterion. However, some of the analysis, such as model definition, need only be one time and the results are saved for future use. The user must write some small, simple FORTRAN programs to interface between the analysis and optimization programs. One of these programs, the front processor, converts the design variables output from the optimizer into the suitable format for input into the analyzer. Another, the end processor, retrieves the behavior variables and, optionally, their gradients from the analysis program and evaluates the objective function and constraints and optionally their gradients. These quantities are output in a format suitable for input into the optimizer. These user-supplied programs are problem-dependent because they depend primarily upon which finite elements are being used in the model. PROSSS-2 differs from the original PROSSS in that the optimizer and front and end processors have been integrated into the finite element computer program. This was done to reduce the complexity and increase portability of the system, and to take advantage of the data handling features found in the finite element program.

Kimberly sugar beet germplasm evaluated for rhizomania and storage rot resistance in Idaho, 2015

USDA-ARS?s Scientific Manuscript database

Rhizomania caused by Beet necrotic yellow vein virus (BNYVV) and storage losses are serious sugar beet production problems. To identify sugar beet germplasm lines with resistance to BNYVV and storage rots, 11germplasm lines from the USDA-ARS Kimberly sugar beet program were screened. The lines wer...

Evaluation of Natural Language Processors.

DTIC Science & Technology

1980-11-01

techniques described. Common practice in describing natural language processors is to describe the programs, then give about 20 examples of correctly...make a decision based on performance as to which approaches are most promising for further research and development. The lack of evaluation leaves...successively more difficult problems. This approach might be compared to children taking achievement tests in school. A 90% score on problems involving

Parallel processing on the Livermore VAX 11/780-4 parallel processor system with compatibility to Cray Research, Inc. (CRI) multitasking. Version 1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Werner, N.E.; Van Matre, S.W.

1985-05-01

This manual describes the CRI Subroutine Library and Utility Package. The CRI library provides Cray multitasking functionality on the four-processor shared memory VAX 11/780-4. Additional functionality has been added for more flexibility. A discussion of the library, utilities, error messages, and example programs is provided.

SPAR thermal analysis processors reference manual, system level 16. Volume 1: Program executive. Volume 2: Theory. Volume 3: Demonstration problems. Volume 4: Experimental thermal element capability. Volume 5: Programmer reference

NASA Technical Reports Server (NTRS)

Marlowe, M. B.; Moore, R. A.; Whetstone, W. D.

1979-01-01

User instructions are given for performing linear and nonlinear steady state and transient thermal analyses with SPAR thermal analysis processors TGEO, SSTA, and TRTA. It is assumed that the user is familiar with basic SPAR operations and basic heat transfer theory.

Grocery store beverage choices by participants in federal food assistance and nutrition programs.

PubMed

Andreyeva, Tatiana; Luedicke, Joerg; Henderson, Kathryn E; Tripp, Amanda S

2012-10-01

Sugar-sweetened beverages are a target for reduction in the 2010 Dietary Guidelines for Americans. Concerns have been raised about sugar-sweetened beverages purchased with Supplemental Nutrition Assistance Program (SNAP) benefits. This paper describes purchases of non-alcoholic refreshment beverages among participants in the U.S. Department of Agriculture's Special Supplemental Nutrition Program for Women, Infants, and Children (WIC) and SNAP. Grocery store scanner data from a regional supermarket chain were used to assess refreshment beverage purchases of 39,172 households in January-June 2011. The sample consisted of families with a history of WIC participation in 2009-2011; about half also participated in SNAP. Beverage spending and volume purchased were compared for WIC sampled households either using SNAP benefits (SNAP) or not (WIC-only). Analyses were completed in 2012. Refreshment beverages were a significant contributor to expenditure on groceries by SNAP and WIC households. Sugar-sweetened beverages accounted for 58% of refreshment beverage purchases made by SNAP households and 48% of purchases by WIC-only households. Soft drinks were purchased most by all households. Fruit-based beverages were mainly 100% juice for WIC-only households and sugary fruit drinks for SNAP households. SNAP benefits paid for 72% of the sugar-sweetened beverage purchases made by SNAP households. Nationwide, SNAP was estimated to pay at least $1.7 to $2.1 billion annually for sugar-sweetened beverages purchased in grocery stores. Considerable amounts of sugar-sweetened beverages are purchased by households participating in WIC and SNAP. The SNAP program pays for most of the sugar-sweetened beverage purchases among SNAP households. The upcoming SNAP reauthorization could be a good time to reconsider the program priorities to align public funds with public health. Copyright © 2012 American Journal of Preventive Medicine. Published by Elsevier Inc. All rights reserved.

State recovery and lockstep execution restart in a system with multiprocessor pairing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switchmore » or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.« less

Multiprocessor speed-up, Amdahl's Law, and the Activity Set Model of parallel program behavior

NASA Technical Reports Server (NTRS)

Gelenbe, Erol

1988-01-01

An important issue in the effective use of parallel processing is the estimation of the speed-up one may expect as a function of the number of processors used. Amdahl's Law has traditionally provided a guideline to this issue, although it appears excessively pessimistic in the light of recent experimental results. In this note, Amdahl's Law is amended by giving a greater importance to the capacity of a program to make effective use of parallel processing, but also recognizing the fact that imbalance of the workload of each processor is bound to occur. An activity set model of parallel program behavior is then introduced along with the corresponding parallelism index of a program, leading to upper and lower bounds to the speed-up.

Sugar-Sweetened Beverage Demand and Tax Simulation for Federal Food Assistance Participants: A Case of Two New England States.

PubMed

Jithitikulchai, Theepakorn; Andreyeva, Tatiana

2018-06-19

Excessive consumption of sugar-sweetened beverages is a major concern in the efforts to improve diet and reduce obesity in USA, particularly among low-income populations. One of the most commonly proposed strategies to reduce sugar-sweetened beverage consumption is increasing beverage prices through taxation. The objective of this study was to evaluate whether and how price-based policies could reduce sugar-sweetened beverage consumption among participants in the federal Supplemental Nutrition Assistance Program. Using point-of-sale data from a regional supermarket chain (58 stores), we estimated the responsiveness of demand to sugar-sweetened beverage price changes among Supplemental Nutrition Assistance Program-participating families with young children. Own-price and cross-price elasticities for non-alcoholic beverages were estimated using a Quadratic Almost Ideal Demand System model. The study found evidence that a tax-induced sugar-sweetened beverage price increase would reduce total sugar-sweetened beverage purchases among Supplemental Nutrition Assistance Program participants, who were driven by purchase shifts away from taxed sodas and sports drinks to non-taxed beverages (bottled water, juice, milk). The substitution of non-taxed caloric beverages decreases the marginal effects of the sugar-sweetened beverage tax, yet the direct tax effects are large enough to reduce the overall caloric intake, with the average net reduction in monthly calories from sugar-sweetened beverages estimated at around 8% for a half-cent per ounce tax and 16% for a one cent per ounce tax. A beverage price increase in the form of an excise tax would reduce sugar-sweetened beverage consumption and increase healthier beverage purchases among low-income families.

Phenotypic selection in sugar maple for superior sap sugar production

Treesearch

William J. Gabriel; William J. Gabriel

1972-01-01

This is a report on the results of the sugar maple selection program at Burlington, Vermont. Because of its possible value to other forestry workers, the method used in making the selections has been treated in detail.

Programs for Testing Processor-in-Memory Computing Systems

NASA Technical Reports Server (NTRS)

Katz, Daniel S.

2006-01-01

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.

Data preprocessing for determining outer/inner parallelization in the nested loop problem using OpenMP

NASA Astrophysics Data System (ADS)

Handhika, T.; Bustamam, A.; Ernastuti, Kerami, D.

2017-07-01

Multi-thread programming using OpenMP on the shared-memory architecture with hyperthreading technology allows the resource to be accessed by multiple processors simultaneously. Each processor can execute more than one thread for a certain period of time. However, its speedup depends on the ability of the processor to execute threads in limited quantities, especially the sequential algorithm which contains a nested loop. The number of the outer loop iterations is greater than the maximum number of threads that can be executed by a processor. The thread distribution technique that had been found previously only be applied by the high-level programmer. This paper generates a parallelization procedure for low-level programmer in dealing with 2-level nested loop problems with the maximum number of threads that can be executed by a processor is smaller than the number of the outer loop iterations. Data preprocessing which is related to the number of the outer loop and the inner loop iterations, the computational time required to execute each iteration and the maximum number of threads that can be executed by a processor are used as a strategy to determine which parallel region that will produce optimal speedup.

Generic HTML Form Processor: A versatile PHP script to save web-collected data into a MySQL database.

PubMed

Göritz, Anja S; Birnbaum, Michael H

2005-11-01

The customizable PHP script Generic HTML Form Processor is intended to assist researchers and students in quickly setting up surveys and experiments that can be administered via the Web. This script relieves researchers from the burdens of writing new CGI scripts and building databases for each Web study. Generic HTML Form Processor processes any syntactically correct HTML forminput and saves it into a dynamically created open-source database. We describe five modes for usage of the script that allow increasing functionality but require increasing levels of knowledge of PHP and Web servers: The first two modes require no previous knowledge, and the fifth requires PHP programming expertise. Use of Generic HTML Form Processor is free for academic purposes, and its Web address is www.goeritz.net/brmic.

7 CFR 1435.106 - Miscellaneous provisions.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Miscellaneous provisions. 1435.106 Section 1435.106 Agriculture Regulations of the Department of Agriculture (Continued) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.106...

7 CFR 1435.106 - Miscellaneous provisions.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 10 2011-01-01 2011-01-01 false Miscellaneous provisions. 1435.106 Section 1435.106 Agriculture Regulations of the Department of Agriculture (Continued) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.106...

7 CFR 1435.106 - Miscellaneous provisions.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 10 2013-01-01 2013-01-01 false Miscellaneous provisions. 1435.106 Section 1435.106 Agriculture Regulations of the Department of Agriculture (Continued) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.106...

7 CFR 1435.106 - Miscellaneous provisions.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 10 2012-01-01 2012-01-01 false Miscellaneous provisions. 1435.106 Section 1435.106 Agriculture Regulations of the Department of Agriculture (Continued) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.106...

7 CFR 1435.106 - Miscellaneous provisions.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Miscellaneous provisions. 1435.106 Section 1435.106 Agriculture Regulations of the Department of Agriculture (Continued) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Sugar Loan Program § 1435.106...

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Towards a Marriage of Two Minds: The Word Processor and Natural Habits of Thought in the "Discovery" Stage of Composing.

ERIC Educational Resources Information Center

Aschauer, Mary Ann; White, Fred D.

Word processing programs offer five capabilities that can help students over the physical and psychological constraints associated with writing. First, producing text on a word processor is more tentative and more noncommital than producing text on paper. This reassures the writer that it is all right to experiment with words. Second, the blinking…

Recent developments of NASTRAN pre- amd post-processors: Response spectrum analysis (RESPAN) and interactive graphics (GIFTS)

NASA Technical Reports Server (NTRS)

Hirt, E. F.; Fox, G. L.

1982-01-01

Two specific NASTRAN preprocessors and postprocessors are examined. A postprocessor for dynamic analysis and a graphical interactive package for model generation and review of resuls are presented. A computer program that provides response spectrum analysis capability based on data from NASTRAN finite element model is described and the GIFTS system, a graphic processor to augment NASTRAN is introduced.

Formulation of consumables management models. Development approach for the mission planning processor working model

NASA Technical Reports Server (NTRS)

Connelly, L. C.

1977-01-01

The mission planning processor is a user oriented tool for consumables management and is part of the total consumables subsystem management concept. The approach to be used in developing a working model of the mission planning processor is documented. The approach includes top-down design, structured programming techniques, and application of NASA approved software development standards. This development approach: (1) promotes cost effective software development, (2) enhances the quality and reliability of the working model, (3) encourages the sharing of the working model through a standard approach, and (4) promotes portability of the working model to other computer systems.

A 20 MHz CMOS reorder buffer for a superscalar microprocessor

NASA Technical Reports Server (NTRS)

Lenell, John; Wallace, Steve; Bagherzadeh, Nader

1992-01-01

Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

A floating-point/multiple-precision processor for airborne applications

NASA Technical Reports Server (NTRS)

Yee, R.

1982-01-01

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

78 FR 54629 - Fisheries of the Exclusive Economic Zone Off Alaska; American Fisheries Act, Amendment 80 Program...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-09-05

... Alaska Community Development Quota (CDQ) Program, and the hook-and-line catcher/processor (freezer... plans to present a draft analysis of the potential effects of cost recovery fee programs to the Council...

7 CFR 1530.105 - Terms and conditions.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 10 2010-01-01 2010-01-01 false Terms and conditions. 1530.105 Section 1530.105 Agriculture Regulations of the Department of Agriculture (Continued) FOREIGN AGRICULTURAL SERVICE, DEPARTMENT OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM...

7 CFR 1530.105 - Terms and conditions.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 10 2012-01-01 2012-01-01 false Terms and conditions. 1530.105 Section 1530.105 Agriculture Regulations of the Department of Agriculture (Continued) FOREIGN AGRICULTURAL SERVICE, DEPARTMENT OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM...

7 CFR 1530.105 - Terms and conditions.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 10 2013-01-01 2013-01-01 false Terms and conditions. 1530.105 Section 1530.105 Agriculture Regulations of the Department of Agriculture (Continued) FOREIGN AGRICULTURAL SERVICE, DEPARTMENT OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM...

7 CFR 1530.105 - Terms and conditions.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 10 2014-01-01 2014-01-01 false Terms and conditions. 1530.105 Section 1530.105 Agriculture Regulations of the Department of Agriculture (Continued) FOREIGN AGRICULTURAL SERVICE, DEPARTMENT OF AGRICULTURE THE REFINED SUGAR RE-EXPORT PROGRAM, THE SUGAR CONTAINING PRODUCTS RE-EXPORT PROGRAM...

Experiences of the use of FOX, an intelligent agent, for programming cochlear implant sound processors in new users.

PubMed

Vaerenberg, Bart; Govaerts, Paul J; de Ceulaer, Geert; Daemers, Kristin; Schauwers, Karen

2011-01-01

This report describes the application of the software tool "Fitting to Outcomes eXpert" (FOX) in programming the cochlear implant (CI) processor in new users. FOX is an intelligent agent to assist in the programming of CI processors. The concept of FOX is to modify maps on the basis of specific outcome measures, achieved using heuristic logic and based on a set of deterministic "rules". A prospective study was conducted on eight consecutive CI-users with a follow-up of three months. Eight adult subjects with postlingual deafness were implanted with the Advanced Bionics HiRes90k device. The implants were programmed using FOX, running a set of rules known as Eargroup's EG0910 advice, which features a set of "automaps". The protocol employed for the initial 3 months is presented, with description of the map modifications generated by FOX and the corresponding psychoacoustic test results. The 3 month median results show 25 dBHL as PTA, 77% (55 dBSPL) and 71% (70 dBSPL) phoneme score at speech audiometry and loudness scaling in or near to the normal zone at different frequencies. It is concluded that this approach is feasible to start up CI fitting and yields good outcome.

Technology transfer of military space microprocessor developments

NASA Astrophysics Data System (ADS)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

7 CFR 1435.311 - Proportionate shares for sugarcane producers.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.311 Proportionate shares for sugarcane producers. (a... sugarcane farms. (b) CCC will determine whether Louisiana sugar production, in the absence of proportionate...

7 CFR 1435.311 - Proportionate shares for sugarcane producers.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.311 Proportionate shares for sugarcane producers. (a... sugarcane farms. (b) CCC will determine whether Louisiana sugar production, in the absence of proportionate...

7 CFR 1435.311 - Proportionate shares for sugarcane producers.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.311 Proportionate shares for sugarcane producers. (a... sugarcane farms. (b) CCC will determine whether Louisiana sugar production, in the absence of proportionate...

7 CFR 1435.311 - Proportionate shares for sugarcane producers.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.311 Proportionate shares for sugarcane producers. (a... sugarcane farms. (b) CCC will determine whether Louisiana sugar production, in the absence of proportionate...

7 CFR 1435.311 - Proportionate shares for sugarcane producers.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.311 Proportionate shares for sugarcane producers. (a... sugarcane farms. (b) CCC will determine whether Louisiana sugar production, in the absence of proportionate...

Review of NASA's (National Aeronautics and Space Administration) Numerical Aerodynamic Simulation Program

NASA Technical Reports Server (NTRS)

1984-01-01

NASA has planned a supercomputer for computational fluid dynamics research since the mid-1970's. With the approval of the Numerical Aerodynamic Simulation Program as a FY 1984 new start, Congress requested an assessment of the program's objectives, projected short- and long-term uses, program design, computer architecture, user needs, and handling of proprietary and classified information. Specifically requested was an examination of the merits of proceeding with multiple high speed processor (HSP) systems contrasted with a single high speed processor system. The panel found NASA's objectives and projected uses sound and the projected distribution of users as realistic as possible at this stage. The multiple-HSP, whereby new, more powerful state-of-the-art HSP's would be integrated into a flexible network, was judged to present major advantages over any single HSP system.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Project Planning and Reporting

NASA Technical Reports Server (NTRS)

1982-01-01

Project Planning Analysis and Reporting System (PPARS) is automated aid in monitoring and scheduling of activities within project. PPARS system consists of PPARS Batch Program, five preprocessor programs, and two post-processor programs. PPARS Batch program is full CPM (Critical Path Method) scheduling program with resource capabilities. Can process networks with up to 10,000 activities.

50 CFR 679.83 - Rockfish Program entry level fishery.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 50 Wildlife and Fisheries 9 2010-10-01 2010-10-01 false Rockfish Program entry level fishery. 679... ALASKA Rockfish Program § 679.83 Rockfish Program entry level fishery. (a) Rockfish entry level fishery—(1) General. A rockfish entry level harvester and rockfish entry level processor may participate in...

7 CFR 1435.307 - Transfer of allocation.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.307 Transfer of allocation. (a) If a sugarcane processing facility is sold or transferred... allocation submitted during the month of May. The request must include the grower's sugar production history...

7 CFR 1435.307 - Transfer of allocation.

Code of Federal Regulations, 2010 CFR

2010-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.307 Transfer of allocation. (a) If a sugarcane processing facility is sold or transferred... allocation submitted during the month of May. The request must include the grower's sugar production history...

7 CFR 1435.307 - Transfer of allocation.

Code of Federal Regulations, 2012 CFR

2012-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.307 Transfer of allocation. (a) If a sugarcane processing facility is sold or transferred... allocation submitted during the month of May. The request must include the grower's sugar production history...

7 CFR 1435.307 - Transfer of allocation.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.307 Transfer of allocation. (a) If a sugarcane processing facility is sold or transferred... allocation submitted during the month of May. The request must include the grower's sugar production history...

7 CFR 1435.307 - Transfer of allocation.

Code of Federal Regulations, 2014 CFR

2014-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.307 Transfer of allocation. (a) If a sugarcane processing facility is sold or transferred... allocation submitted during the month of May. The request must include the grower's sugar production history...

A GaAs vector processor based on parallel RISC microprocessors

NASA Astrophysics Data System (ADS)

Misko, Tim A.; Rasset, Terry L.

A vector processor architecture based on the development of a 32-bit microprocessor using gallium arsenide (GaAs) technology has been developed. The McDonnell Douglas vector processor (MVP) will be fabricated completely from GaAs digital integrated circuits. The MVP architecture includes a vector memory of 1 megabyte, a parallel bus architecture with eight processing elements connected in parallel, and a control processor. The processing elements consist of a reduced instruction set CPU (RISC) with four floating-point coprocessor units and necessary memory interface functions. This architecture has been simulated for several benchmark programs including complex fast Fourier transform (FFT), complex inner product, trigonometric functions, and sort-merge routine. The results of this study indicate that the MVP can process a 1024-point complex FFT at a speed of 112 microsec (389 megaflops) while consuming approximately 618 W of power in a volume of approximately 0.1 ft-cubed.

Vectorization with SIMD extensions speeds up reconstruction in electron tomography.

PubMed

Agulleiro, J I; Garzón, E M; García, I; Fernández, J J

2010-06-01

Electron tomography allows structural studies of cellular structures at molecular detail. Large 3D reconstructions are needed to meet the resolution requirements. The processing time to compute these large volumes may be considerable and so, high performance computing techniques have been used traditionally. This work presents a vector approach to tomographic reconstruction that relies on the exploitation of the SIMD extensions available in modern processors in combination to other single processor optimization techniques. This approach succeeds in producing full resolution tomograms with an important reduction in processing time, as evaluated with the most common reconstruction algorithms, namely WBP and SIRT. The main advantage stems from the fact that this approach is to be run on standard computers without the need of specialized hardware, which facilitates the development, use and management of programs. Future trends in processor design open excellent opportunities for vector processing with processor's SIMD extensions in the field of 3D electron microscopy.

The DISCUS Hardware System,

DTIC Science & Technology

1982-07-01

blocks. DISCUS has no form of hardware synchronisation between the processors. The only synchronisation is at an operating system level. ;ach processor is... operations in global store so that semaphoring on global objects can be done correctly. Write Protect is used by the operating system for read-only...the appropriate operating system program. String Handling primitives . The Z8000 has a rich set of string primitives . However as we saw before if a

Function Allocation in a Robust Distributed Real-Time Environment

DTIC Science & Technology

1991-12-01

fundamental characteristic of a distributed system is its ability to map individual logical functions of an application program onto many physical nodes... how much of a node’s processor time is scheduled for function processing. IMC is the function- to -function communication required to facilitate...indicator of how much excess processor time a node has. The reconfiguration algorithms use these variables to determine the most appropriate node(s) to

Optoelectronic Technology Consortium: Precompetitive Consortium for Optoelectronic Interconnect Technology

DTIC Science & Technology

1992-09-01

demonstrating the producibility of optoelectronic components for high-density/high-data-rate processors and accelerating the insertion of this technology...technology development stage, OETC will advance the development of optical components, produce links for a multiboard processor testbed demonstration, and...components that are affordable, initially at <$100 per line, and reliable, with a li~e BER᝺-15 and MTTF >10 6 hours. Under the OETC program, Honeywell will

Digital Flight Control System Redundancy Study

DTIC Science & Technology

1974-07-01

has its own separate power supr, y . d. Digital Processor The digital processor consists of the followdnq components: (1) Program Counter - This...1-3 Yaw Axis Control 108 1-4 Autothrottle (Airspeed Hold Mode) 109 1-5 Approach Power Compensation 110 1-6 Glideslope Flare 111 I-7 Glideslope Track...considsred to the extent that they imposed constraints on the candidate con- figurations. Cost, size, weight, power , maintainability, survivability and

Integrating a Natural Language Message Pre-Processor with UIMA

DTIC Science & Technology

2008-01-01

Carnegie Mellon Language Technologies Institute NL Message Preprocessing with UIMA Copyright © 2008, Carnegie Mellon. All Rights Reserved...Integrating a Natural Language Message Pre-Processor with UIMA Eric Nyberg, Eric Riebling, Richard C. Wang & Robert Frederking Language Technologies Institute...with UIMA 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) 5d. PROJECT NUMBER 5e. TASK NUMBER 5f. WORK UNIT NUMBER

Parallel implementation of an adaptive and parameter-free N-body integrator

NASA Astrophysics Data System (ADS)

Pruett, C. David; Ingham, William H.; Herman, Ralph D.

2011-05-01

Previously, Pruett et al. (2003) [3] described an N-body integrator of arbitrarily high order M with an asymptotic operation count of O(MN). The algorithm's structure lends itself readily to data parallelization, which we document and demonstrate here in the integration of point-mass systems subject to Newtonian gravitation. High order is shown to benefit parallel efficiency. The resulting N-body integrator is robust, parameter-free, highly accurate, and adaptive in both time-step and order. Moreover, it exhibits linear speedup on distributed parallel processors, provided that each processor is assigned at least a handful of bodies. Program summaryProgram title: PNB.f90 Catalogue identifier: AEIK_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEIK_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC license, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 3052 No. of bytes in distributed program, including test data, etc.: 68 600 Distribution format: tar.gz Programming language: Fortran 90 and OpenMPI Computer: All shared or distributed memory parallel processors Operating system: Unix/Linux Has the code been vectorized or parallelized?: The code has been parallelized but has not been explicitly vectorized. RAM: Dependent upon N Classification: 4.3, 4.12, 6.5 Nature of problem: High accuracy numerical evaluation of trajectories of N point masses each subject to Newtonian gravitation. Solution method: Parallel and adaptive extrapolation in time via power series of arbitrary degree. Running time: 5.1 s for the demo program supplied with the package.

Selection of a Brine Processor Technology for NASA Manned Missions

NASA Technical Reports Server (NTRS)

Carter, Donald L.; Gleich, Andrew F.

2016-01-01

The current ISS Water Recovery System (WRS) reclaims water from crew urine, humidity condensate, and Sabatier product water. Urine is initially processed by the Urine Processor Assembly (UPA) which recovers 75% of the urine as distillate. The remainder of the water is present in the waste brine which is currently disposed of as trash on ISS. For future missions this additional water must be reclaimed due to the significant resupply penalty for missions beyond Low Earth Orbit (LEO). NASA has pursued various technology development programs for a brine processor in the past several years. This effort has culminated in a technology down-select to identify the optimum technology for future manned missions. The technology selection is based on various criteria, including mass, power, reliability, maintainability, and safety. Beginning in 2016 the selected technology will be transitioned to a flight hardware program for demonstration on ISS. This paper summarizes the technology selection process, the competing technologies, and the rationale for the technology selected for future manned missions.

Sugar Free with Justin T.: Diabetes Education through Community Partnerships

ERIC Educational Resources Information Center

Thomas, Justin B.; Donaldson, Joseph L.

2014-01-01

This article describes the design, development, and delivery of an Extension community cable television program, "Sugar Free with Justin T.," in Roane County, Tennessee. The program targets diabetics, pre-diabetics, and those who care for them, with practical information and demonstrations to improve dietary quality. In addition to…

A Diagnostic System for Studying Energy Partitioning and Assessing the Response of the Ionosphere during HAARP Modification Experiments

NASA Technical Reports Server (NTRS)

Djuth, Frank T.; Elder, John H.; Williams, Kenneth L.

1996-01-01

This research program focused on the construction of several key radio wave diagnostics in support of the HF Active Auroral Ionospheric Research Program (HAARP). Project activities led to the design, development, and fabrication of a variety of hardware units and to the development of several menu-driven software packages for data acquisition and analysis. The principal instrumentation includes an HF (28 MHz) radar system, a VHF (50 MHz) radar system, and a high-speed radar processor consisting of three separable processing units. The processor system supports the HF and VHF radars and is capable of acquiring very detailed data with large incoherent scatter radars. In addition, a tunable HF receiver system having high dynamic range was developed primarily for measurements of stimulated electromagnetic emissions (SEE). A separate processor unit was constructed for the SEE receiver. Finally, a large amount of support instrumentation was developed to accommodate complex field experiments. Overall, the HAARP diagnostics are powerful tools for studying diverse ionospheric modification phenomena. They are also flexible enough to support a host of other missions beyond the scope of HAARP. Many new research programs have been initiated by applying the HAARP diagnostics to studies of natural atmospheric processes.

Word Processor Training on Intelligent Videodisc.

ERIC Educational Resources Information Center

Yampolsky, Michael

1983-01-01

Presents an overview of the Wang Word Processing Intelligent Learning Program on interactive videodisc, which is used at Eastman Kodak to train hundreds of word processing operators. Operation of the program is discussed in detail. (MBR)

Parallel community climate model: Description and user`s guide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Drake, J.B.; Flanery, R.E.; Semeraro, B.D.

This report gives an overview of a parallel version of the NCAR Community Climate Model, CCM2, implemented for MIMD massively parallel computers using a message-passing programming paradigm. The parallel implementation was developed on an Intel iPSC/860 with 128 processors and on the Intel Delta with 512 processors, and the initial target platform for the production version of the code is the Intel Paragon with 2048 processors. Because the implementation uses a standard, portable message-passing libraries, the code has been easily ported to other multiprocessors supporting a message-passing programming paradigm. The parallelization strategy used is to decompose the problem domain intomore » geographical patches and assign each processor the computation associated with a distinct subset of the patches. With this decomposition, the physics calculations involve only grid points and data local to a processor and are performed in parallel. Using parallel algorithms developed for the semi-Lagrangian transport, the fast Fourier transform and the Legendre transform, both physics and dynamics are computed in parallel with minimal data movement and modest change to the original CCM2 source code. Sequential or parallel history tapes are written and input files (in history tape format) are read sequentially by the parallel code to promote compatibility with production use of the model on other computer systems. A validation exercise has been performed with the parallel code and is detailed along with some performance numbers on the Intel Paragon and the IBM SP2. A discussion of reproducibility of results is included. A user`s guide for the PCCM2 version 2.1 on the various parallel machines completes the report. Procedures for compilation, setup and execution are given. A discussion of code internals is included for those who may wish to modify and use the program in their own research.« less

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

Programming methodology for a general purpose automation controller

NASA Technical Reports Server (NTRS)

Sturzenbecker, M. C.; Korein, J. U.; Taylor, R. H.

1987-01-01

The General Purpose Automation Controller is a multi-processor architecture for automation programming. A methodology has been developed whose aim is to simplify the task of programming distributed real-time systems for users in research or manufacturing. Programs are built by configuring function blocks (low-level computations) into processes using data flow principles. These processes are activated through the verb mechanism. Verbs are divided into two classes: those which support devices, such as robot joint servos, and those which perform actions on devices, such as motion control. This programming methodology was developed in order to achieve the following goals: (1) specifications for real-time programs which are to a high degree independent of hardware considerations such as processor, bus, and interconnect technology; (2) a component approach to software, so that software required to support new devices and technologies can be integrated by reconfiguring existing building blocks; (3) resistance to error and ease of debugging; and (4) a powerful command language interface.

Current trends of sugar consumption in developing societies.

PubMed

Ismail, A I; Tanzer, J M; Dingle, J L

1997-12-01

This paper reviews recent data on sugar consumption in developing countries that may lead to a potential increase in caries prevalence. A search of the business, dental and nutritional literature was conducted through May 1995. There is evidence that sugar (sucrose) use was increasing in China, India, and Southeast Asia. In South and Central America (except Haiti) sugar use was either equivalent to or higher than that in most developed societies. In the Middle East, average sugar use was higher than that of other developing areas. However, it was either lower than or equivalent to the levels reported by other developed countries. Many central African countries consumed less than 15 kg of sugar/ person/year. Of particular concern is a rise in the consumption of sugar-containing carbonated beverages in a number of developing societies: China, India, Vietnam, Thailand, and other Southeast Asian countries are currently major growth markets for the soft drink industry. Consumption of high-sugar desserts and snacks may also be increasing in urban centers in some developing countries. To counteract the potential increase in the prevalence of dental caries in some developing countries, preventive and oral health promotion programs should be planned and implemented. We contend that taxation of sugar-containing products as well as efforts to reduce the level of sugar consumption to "safe" levels may be impractical, and in most countries, cannot be supported for political, economic, or health reasons. Instead, we recommend that collaboration be established between public health authorities and manufacturers/distributors of soft drinks and sweets in developing countries to establish a dental health fund that could be used to support caries preventive programs. The fund could be supported through donations from manufacturers based on the principle of the "milli-cent" (1 cent for every 1000 cents of sales). This minimal contribution would provide enough financial support for planning and implementing dental preventive and restorative programs in developing countries.

Right-Brain/Left-Brain Integrated Associative Processor Employing Convertible Multiple-Instruction-Stream Multiple-Data-Stream Elements

NASA Astrophysics Data System (ADS)

Hayakawa, Hitoshi; Ogawa, Makoto; Shibata, Tadashi

2005-04-01

A very large scale integrated circuit (VLSI) architecture for a multiple-instruction-stream multiple-data-stream (MIMD) associative processor has been proposed. The processor employs an architecture that enables seamless switching from associative operations to arithmetic operations. The MIMD element is convertible to a regular central processing unit (CPU) while maintaining its high performance as an associative processor. Therefore, the MIMD associative processor can perform not only on-chip perception, i.e., searching for the vector most similar to an input vector throughout the on-chip cache memory, but also arithmetic and logic operations similar to those in ordinary CPUs, both simultaneously in parallel processing. Three key technologies have been developed to generate the MIMD element: associative-operation-and-arithmetic-operation switchable calculation units, a versatile register control scheme within the MIMD element for flexible operations, and a short instruction set for minimizing the memory size for program storage. Key circuit blocks were designed and fabricated using 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. As a result, the full-featured MIMD element is estimated to be 3 mm2, showing the feasibility of an 8-parallel-MIMD-element associative processor in a single chip of 5 mm× 5 mm.

C-MOS array design techniques: SUMC multiprocessor system study

NASA Technical Reports Server (NTRS)

Clapp, W. A.; Helbig, W. A.; Merriam, A. S.

1972-01-01

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Analysis of DuPont and Kodak duplicating films and chemistries in a Fultron spray processor

NASA Technical Reports Server (NTRS)

Weinstein, M. S.

1972-01-01

A test program was conducted with duPont duplicating film type SR 112 and SCOLOR developer and Kodak duplicating film types 2430, 2422, and FE 2628 (SO-467) and MX-641 developer to determine sensitometric and image quality characteristics of these materials when used with a fultron spray processor. The test results show that the SCOLOR developer foams excessively in the fultron processor when used with or without the addition of an antifoaming agent. The Kodak type FE 2628 film with MX-641 chemistry had the longest linear Log E range at a 1.0 gamma. Sensitometric curves and granularity traces for all film process combinations tested are included.

MILC Code Performance on High End CPU and GPU Supercomputer Clusters

NASA Astrophysics Data System (ADS)

DeTar, Carleton; Gottlieb, Steven; Li, Ruizi; Toussaint, Doug

2018-03-01

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.

Hierarchical algorithms for modeling the ocean on hierarchical architectures

NASA Astrophysics Data System (ADS)

Hill, C. N.

2012-12-01

This presentation will describe an approach to using accelerator/co-processor technology that maps hierarchical, multi-scale modeling techniques to an underlying hierarchical hardware architecture. The focus of this work is on making effective use of both CPU and accelerator/co-processor parts of a system, for large scale ocean modeling. In the work, a lower resolution basin scale ocean model is locally coupled to multiple, "embedded", limited area higher resolution sub-models. The higher resolution models execute on co-processor/accelerator hardware and do not interact directly with other sub-models. The lower resolution basin scale model executes on the system CPU(s). The result is a multi-scale algorithm that aligns with hardware designs in the co-processor/accelerator space. We demonstrate this approach being used to substitute explicit process models for standard parameterizations. Code for our sub-models is implemented through a generic abstraction layer, so that we can target multiple accelerator architectures with different programming environments. We will present two application and implementation examples. One uses the CUDA programming environment and targets GPU hardware. This example employs a simple non-hydrostatic two dimensional sub-model to represent vertical motion more accurately. The second example uses a highly threaded three-dimensional model at high resolution. This targets a MIC/Xeon Phi like environment and uses sub-models as a way to explicitly compute sub-mesoscale terms. In both cases the accelerator/co-processor capability provides extra compute cycles that allow improved model fidelity for little or no extra wall-clock time cost.

Yield of glyphosate-resistant sugar beets and efficiency of weed management systems with glyphosate and conventional herbicides under German and Polish crop production.

PubMed

Nichterlein, Henrike; Matzk, Anja; Kordas, Leszek; Kraus, Josef; Stibbe, Carsten

2013-08-01

In sugar beet production, weed control is one of the most important and most expensive practices to ensure yield. Since glyphosate-resistant sugar beets are not yet approved for cultivation in the EU, little commercial experience exists with these sugar beets in Europe. Experimental field trials were conducted at five environments (Germany, Poland, 2010, 2011) to compare the effects of glyphosate with the effects of conventional weed control programs on the development of weeds, weed control efficiency and yield. The results show that the glyphosate weed control programs compared to the conventional methods decreased not only the number of herbicide applications but equally in magnitude decreased the dosage of active ingredients. The results also showed effective weed control with glyphosate when the weed covering was greater and sugar beets had a later growth stage of four true leaves. Glyphosate-resistant sugar beets applied with the glyphosate herbicide two or three times had an increase in white sugar yield from 4 to 18 % in comparison to the high dosage conventional herbicide systems. In summary, under glyphosate management sugar beets can positively contribute to the increasingly demanding requirements regarding efficient sugar beet cultivation and to the demands by society and politics to reduce the use of chemical plant protection products in the environment.

7 CFR 1435.316 - Acreage reports for purposes of proportionate shares.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.316 Acreage reports for purposes of proportionate shares. (a) A report of planted and failed acreage shall be required on farms that produce sugarcane for sugar...

7 CFR 1435.303 - Adjustment of the overall allotment quantity.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.303 Adjustment of the overall allotment quantity. (a) The... than 85 percent of the estimated quantity of sugar for domestic human consumption for the crop year: (1...

7 CFR 1435.312 - Establishment of acreage bases under proportionate shares.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.312 Establishment of acreage bases under proportionate... shares as the simple average of the acreage planted and considered planted for harvest for sugar or seed...

7 CFR 1435.316 - Acreage reports for purposes of proportionate shares.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.316 Acreage reports for purposes of proportionate shares. (a) A report of planted and failed acreage shall be required on farms that produce sugarcane for sugar...

7 CFR 1435.312 - Establishment of acreage bases under proportionate shares.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.312 Establishment of acreage bases under proportionate... shares as the simple average of the acreage planted and considered planted for harvest for sugar or seed...

7 CFR 1435.303 - Adjustment of the overall allotment quantity.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.303 Adjustment of the overall allotment quantity. (a) The... than 85 percent of the estimated quantity of sugar for domestic human consumption for the crop year: (1...

Beet curly top resistance in USDA-ARS Ft. Collins Germplasm, 2012

USDA-ARS?s Scientific Manuscript database

Seventeen sugar beet (Beta vulgaris L.) lines from the USDA-ARS Ft. Collins sugar beet program were screened for resistance to Beet severe curly top virus (BSCTV) and other closely related Curtovirus species in 2012. Commercial sugar beet cultivars Monohikari and HM PM90 were included as susceptibl...

7 CFR 1435.312 - Establishment of acreage bases under proportionate shares.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.312 Establishment of acreage bases under proportionate... shares as the simple average of the acreage planted and considered planted for harvest for sugar or seed...

7 CFR 1435.303 - Adjustment of the overall allotment quantity.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.303 Adjustment of the overall allotment quantity. (a) The... than 85 percent of the estimated quantity of sugar for domestic human consumption for the crop year: (1...

7 CFR 1435.316 - Acreage reports for purposes of proportionate shares.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.316 Acreage reports for purposes of proportionate shares. (a) A report of planted and failed acreage shall be required on farms that produce sugarcane for sugar...

7 CFR 1435.316 - Acreage reports for purposes of proportionate shares.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.316 Acreage reports for purposes of proportionate shares. (a) A report of planted and failed acreage shall be required on farms that produce sugarcane for sugar...

7 CFR 1435.303 - Adjustment of the overall allotment quantity.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.303 Adjustment of the overall allotment quantity. (a) The... than 85 percent of the estimated quantity of sugar for domestic human consumption for the crop year: (1...

7 CFR 1435.303 - Adjustment of the overall allotment quantity.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.303 Adjustment of the overall allotment quantity. (a) The... than 85 percent of the estimated quantity of sugar for domestic human consumption for the crop year: (1...

7 CFR 1435.316 - Acreage reports for purposes of proportionate shares.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.316 Acreage reports for purposes of proportionate shares. (a) A report of planted and failed acreage shall be required on farms that produce sugarcane for sugar...

7 CFR 1435.312 - Establishment of acreage bases under proportionate shares.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.312 Establishment of acreage bases under proportionate... shares as the simple average of the acreage planted and considered planted for harvest for sugar or seed...

7 CFR 1435.312 - Establishment of acreage bases under proportionate shares.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.312 Establishment of acreage bases under proportionate... shares as the simple average of the acreage planted and considered planted for harvest for sugar or seed...

Using Microcomputer Word Processors for Foreign Languages.

ERIC Educational Resources Information Center

Smith, Kim L.

1984-01-01

Describes the programs and modifications needed to do word processing using foreign language characters. One such program, Screenwriter, uses soft character sets -- character sets which can be designed by the program user. This program has a word processing power combined with a foreign language capability that would allow any person to work with…

Development of a General-Purpose Analysis System Based on a Programmable Fluid Processor Final Report CRADA No. TC-2027-01

DOE Office of Scientific and Technical Information (OSTI.GOV)

McConaghy, C. F.; Gascoyne, P. R.

The purpose ofthis project was to develop a general-purpose analysis system based on a programmable fluid processor (PFP). The PFP is an array of electrodes surrounded by fluid reservoirs and injectors. Injected droplets of various reagents are manjpulated and combined on the array by Dielectrophoretic (DEP) forces. The goal was to create a small handheld device that could accomplish the tasks currently undertaken by much larger, time consuming, manual manipulation in the lab. The entire effo1t was funded by DARPA under the Bio-Flips program. MD Anderson Cancer Center was the PI for the DARPA effort. The Bio-Flips program was amore » 3- year program that ran from September 2000 to September 2003. The CRADA was somewhat behind the Bi-Flips program running from June 2001 to June 2004 with a no cost extension to September 2004.« less

Demonstration program for Omega receiver prototype microcomputer data processing

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

The JOLT (TM) commercial microcomputer, based on the MOS Technology 6502 processor chip, for use in Omega navigation system is evaluated. A computer program was prepared in hand-assembled code to demonstrate receiver operation. The processor provides binary processing with interrupts enabled, a carriage return is given to initialize the teleprinter, and a jump is performed to enter the program loop to wait for an interrupt. The program loop operates continuously testing the interrupt flag. The interrupt routine reads the receiver status word and determines whether the current time-slot is the A slot. If so, the interrupt flag, which is also the data index pointer, is reset to zero. The status word is stored in the status buffer. If the time-slot is not A, the interrupt flag/pointer is incremented by one to index the phase and status to the proper buffer words for later use by the print routine.

Ion Thruster Development at NASA Lewis Research Center

NASA Technical Reports Server (NTRS)

Sovey, James S.; Hamley, John A.; Patterson, Michael J.; Rawlin, Vincent K.; Sarver-Verhey, Timothy R.

1992-01-01

Recent ion propulsion technology efforts at NASA's Lewis Research Center including development of kW-class xenon ion thrusters, high power xenon and krypton ion thrusters, and power processors are reviewed. Thruster physical characteristics, performance data, life projections, and power processor component technology are summarized. The ion propulsion technology program is structured to address a broad set of mission applications from satellite stationkeeping and repositioning to primary propulsion using solar or nuclear power systems.

Construction of a parallel processor for simulating manipulators and other mechanical systems

NASA Technical Reports Server (NTRS)

Hannauer, George

1991-01-01

This report summarizes the results of NASA Contract NAS5-30905, awarded under phase 2 of the SBIR Program, for a demonstration of the feasibility of a new high-speed parallel simulation processor, called the Real-Time Accelerator (RTA). The principal goals were met, and EAI is now proceeding with phase 3: development of a commercial product. This product is scheduled for commercial introduction in the second quarter of 1992.

50 CFR 660.160 - Catcher/processor (C/P) Coop Program.

Code of Federal Regulations, 2010 CFR

2010-10-01

... Coop Program, or the Shorebased IFQ Program. As determined necessary by the Regional Administrator... combination. [Reserved] (4) Appeals. [Reserved] (5) Fees. The Regional Administrator is authorized to charge... entry permit owner in the NMFS permit database. (ii) Qualifying criteria for C/P endorsement. In order...

Clinical Validation of a Sound Processor Upgrade in Direct Acoustic Cochlear Implant Subjects

PubMed Central

Kludt, Eugen; D’hondt, Christiane; Lenarz, Thomas; Maier, Hannes

2017-01-01

Objective: The objectives of the investigation were to evaluate the effect of a sound processor upgrade on the speech reception threshold in noise and to collect long-term safety and efficacy data after 2½ to 5 years of device use of direct acoustic cochlear implant (DACI) recipients. Study Design: The study was designed as a mono-centric, prospective clinical trial. Setting: Tertiary referral center. Patients: Fifteen patients implanted with a direct acoustic cochlear implant. Intervention: Upgrade with a newer generation of sound processor. Main Outcome Measures: Speech recognition test in quiet and in noise, pure tone thresholds, subject-reported outcome measures. Results: The speech recognition in quiet and in noise is superior after the sound processor upgrade and stable after long-term use of the direct acoustic cochlear implant. The bone conduction thresholds did not decrease significantly after long-term high level stimulation. Conclusions: The new sound processor for the DACI system provides significant benefits for DACI users for speech recognition in both quiet and noise. Especially the noise program with the use of directional microphones (Zoom) allows DACI patients to have much less difficulty when having conversations in noisy environments. Furthermore, the study confirms that the benefits of the sound processor upgrade are available to the DACI recipients even after several years of experience with a legacy sound processor. Finally, our study demonstrates that the DACI system is a safe and effective long-term therapy. PMID:28406848

Blending better beverage options: a nutrition education and experiential workshop for youths.

PubMed

Isoldi, Kathy K; Dolar, Veronika

2015-01-01

To reduce intake of sugar-sweetened beverages (SSBs) in youths as a means to reduce obesity risk. Youths 5-14 years old attending a summer program were given a two-hour workshop addressing the sugar content in SSBs, the health risks from drinking SSBs, and hands-on preparation as well as tastings of low-sugar beverage alternatives. Data on usual intake of SSBs was obtained at baseline, and pre- and postprogram surveys were conducted to gauge change in knowledge and/or attitudes regarding SSBs. There were 128 participants (63% male) in the program. SSBs were commonly consumed with over 80% reporting regular consumption (mean daily intake 17.9 ounces). Significant increase in knowledge regarding the sugar content of commonly consumed SSBs was achieved; however change in attitudes was not significant. The large majority of youths reported enjoying the workshop and intention to reduce intake of SSBs following program participation. SSBs are commonly consumed by youths. Knowledge regarding the sugar content of SSBs is easier to impart to youths than influencing attitudes held about these beverages. Long-term interventions that reach out to parents and address the widespread availability of SSBs are needed to influence resistant attitudes and beverage choosing behaviors in youths.

40 CFR 180.472 - Imidacloprid; tolerances for residues.

Code of Federal Regulations, 2012 CFR

2012-07-01

...) PESTICIDE PROGRAMS TOLERANCES AND EXEMPTIONS FOR PESTICIDE CHEMICAL RESIDUES IN FOOD Specific Tolerances... 1.0 Banana 0.50 Beet, sugar, molasses 0.30 Beet, sugar, roots 0.05 Beet, sugar, tops 0.50 Biriba 0... Persimmon 3.0 Pistachio 0.05 Pomegranate 0.90 Potato, chip 0.40 Potato, processed potato waste 0.90 Poultry...

40 CFR 180.472 - Imidacloprid; tolerances for residues.

Code of Federal Regulations, 2014 CFR

2014-07-01

...) PESTICIDE PROGRAMS TOLERANCES AND EXEMPTIONS FOR PESTICIDE CHEMICAL RESIDUES IN FOOD Specific Tolerances... 1.0 Banana 0.50 Beet, sugar, molasses 0.30 Beet, sugar, roots 0.05 Beet, sugar, tops 0.50 Biriba 0....75 Pecan 0.05 Persimmon 3.0 Pistachio 0.05 Pomegranate 0.90 Potato, chip 0.40 Potato, processed...

40 CFR 180.472 - Imidacloprid; tolerances for residues.

Code of Federal Regulations, 2013 CFR

2013-07-01

...) PESTICIDE PROGRAMS TOLERANCES AND EXEMPTIONS FOR PESTICIDE CHEMICAL RESIDUES IN FOOD Specific Tolerances... 1.0 Banana 0.50 Beet, sugar, molasses 0.30 Beet, sugar, roots 0.05 Beet, sugar, tops 0.50 Biriba 0....75 Pecan 0.05 Persimmon 3.0 Pistachio 0.05 Pomegranate 0.90 Potato, chip 0.40 Potato, processed...

7 CFR 1435.301 - Annual estimates and quarterly re-estimates.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.301 Annual estimates and quarterly re-estimates. (a) Not later than August 1... later than the beginning of each quarter of such crop year, the: (1) Quantity of sugar that will be...

7 CFR 1435.301 - Annual estimates and quarterly re-estimates.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.301 Annual estimates and quarterly re-estimates. (a) Not later than August 1... later than the beginning of each quarter of such crop year, the: (1) Quantity of sugar that will be...

7 CFR 1435.301 - Annual estimates and quarterly re-estimates.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.301 Annual estimates and quarterly re-estimates. (a) Not later than August 1... later than the beginning of each quarter of such crop year, the: (1) Quantity of sugar that will be...

7 CFR 1435.301 - Annual estimates and quarterly re-estimates.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.301 Annual estimates and quarterly re-estimates. (a) Not later than August 1... later than the beginning of each quarter of such crop year, the: (1) Quantity of sugar that will be...

7 CFR 1435.301 - Annual estimates and quarterly re-estimates.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.301 Annual estimates and quarterly re-estimates. (a) Not later than August 1... later than the beginning of each quarter of such crop year, the: (1) Quantity of sugar that will be...

Computer program documentation for the patch subsampling processor

NASA Technical Reports Server (NTRS)

Nieves, M. J.; Obrien, S. O.; Oney, J. K. (Principal Investigator)

1981-01-01

The programs presented are intended to provide a way to extract a sample from a full-frame scene and summarize it in a useful way. The sample in each case was chosen to fill a 512-by-512 pixel (sample-by-line) image since this is the largest image that can be displayed on the Integrated Multivariant Data Analysis and Classification System. This sample size provides one megabyte of data for manipulation and storage and contains about 3% of the full-frame data. A patch image processor computes means for 256 32-by-32 pixel squares which constitute the 512-by-512 pixel image. Thus, 256 measurements are available for 8 vegetation indexes over a 100-mile square.

GASP-PL/I Simulation of Integrated Avionic System Processor Architectures. M.S. Thesis

NASA Technical Reports Server (NTRS)

Brent, G. A.

1978-01-01

A development study sponsored by NASA was completed in July 1977 which proposed a complete integration of all aircraft instrumentation into a single modular system. Instead of using the current single-function aircraft instruments, computers compiled and displayed inflight information for the pilot. A processor architecture called the Team Architecture was proposed. This is a hardware/software approach to high-reliability computer systems. A follow-up study of the proposed Team Architecture is reported. GASP-PL/1 simulation models are used to evaluate the operating characteristics of the Team Architecture. The problem, model development, simulation programs and results at length are presented. Also included are program input formats, outputs and listings.

An Evaluation of an Ada Implementation of the Rete Algorithm for Embedded Flight Processors

DTIC Science & Technology

1990-12-01

computers was desired. The VAX VMS operating system has many built-in methods for determining program performance (including VAX PCA), but these methods... overviev , of the target environment-- the MIL-STD-1750A VHSIC Avionic Modular Processor ( VA.IP, running under the Ada Avionics Real-Time Software (AARTS... computers . Mil-STD-1750A, the Air Force’s standard flight computer architecture, however, places severe constraints on applications software processing

State University of New York Institute of Technology (SUNYIT) Summer Scholar Program

DTIC Science & Technology

2009-10-01

COVERED (From - To) March 2007 – April 2009 4 . TITLE AND SUBTITLE STATE UNIVERSITY OF NEW YORK INSTITUTE OF TECHNOLOGY (SUNYIT) SUMMER SCHOLAR...Even with access to the Arctic Regional Supercomputer Center (ARSC), evolving a 9/7 wavelet with four multi-resolution levels (MRA 4 ) involves...evaluated over the multiple processing elements in the Cell processor. It was tested on Cell processors in a Sony Playstation 3 and on an IBM QS20 blade

Uses of DARPA Materials Sciences Technology in DoD Systems.

DTIC Science & Technology

1996-05-01

and Lasers NUMBER: University of Central Florida 4000 Central Florida Blvd. P.O. Box 162700 Orlando, FL 32816-2700 9. S PONSO RIN GMO NITO RING AGENCY...course of the program. These advances were communicated to the industry through seminars and workshops, individual plant and agency visits, videotapes on...1995) • P3 ISAR Radar Processor * Digital Signal Processor for OH-58D helicopter * Motorola building a GaAs IC plant for IRIDIUM 26 GALLIUM ARSENIDE

Computational performance of a smoothed particle hydrodynamics simulation for shared-memory parallel computing

NASA Astrophysics Data System (ADS)

Nishiura, Daisuke; Furuichi, Mikito; Sakaguchi, Hide

2015-09-01

The computational performance of a smoothed particle hydrodynamics (SPH) simulation is investigated for three types of current shared-memory parallel computer devices: many integrated core (MIC) processors, graphics processing units (GPUs), and multi-core CPUs. We are especially interested in efficient shared-memory allocation methods for each chipset, because the efficient data access patterns differ between compute unified device architecture (CUDA) programming for GPUs and OpenMP programming for MIC processors and multi-core CPUs. We first introduce several parallel implementation techniques for the SPH code, and then examine these on our target computer architectures to determine the most effective algorithms for each processor unit. In addition, we evaluate the effective computing performance and power efficiency of the SPH simulation on each architecture, as these are critical metrics for overall performance in a multi-device environment. In our benchmark test, the GPU is found to produce the best arithmetic performance as a standalone device unit, and gives the most efficient power consumption. The multi-core CPU obtains the most effective computing performance. The computational speed of the MIC processor on Xeon Phi approached that of two Xeon CPUs. This indicates that using MICs is an attractive choice for existing SPH codes on multi-core CPUs parallelized by OpenMP, as it gains computational acceleration without the need for significant changes to the source code.

Noise reduction technologies implemented in head-worn preprocessors for improving cochlear implant performance in reverberant noise fields.

PubMed

Chung, King; Nelson, Lance; Teske, Melissa

2012-09-01

The purpose of this study was to investigate whether a multichannel adaptive directional microphone and a modulation-based noise reduction algorithm could enhance cochlear implant performance in reverberant noise fields. A hearing aid was modified to output electrical signals (ePreprocessor) and a cochlear implant speech processor was modified to receive electrical signals (eProcessor). The ePreprocessor was programmed to flat frequency response and linear amplification. Cochlear implant listeners wore the ePreprocessor-eProcessor system in three reverberant noise fields: 1) one noise source with variable locations; 2) three noise sources with variable locations; and 3) eight evenly spaced noise sources from 0° to 360°. Listeners' speech recognition scores were tested when the ePreprocessor was programmed to omnidirectional microphone (OMNI), omnidirectional microphone plus noise reduction algorithm (OMNI + NR), and adaptive directional microphone plus noise reduction algorithm (ADM + NR). They were also tested with their own cochlear implant speech processor (CI_OMNI) in the three noise fields. Additionally, listeners rated overall sound quality preferences on recordings made in the noise fields. Results indicated that ADM+NR produced the highest speech recognition scores and the most preferable rating in all noise fields. Factors requiring attention in the hearing aid-cochlear implant integration process are discussed. Copyright © 2012 Elsevier B.V. All rights reserved.

Multicore Programming Challenges

NASA Astrophysics Data System (ADS)

Perrone, Michael

The computer industry is facing fundamental challenges that are driving a major change in the design of computer processors. Due to restrictions imposed by quantum physics, one historical path to higher computer processor performance - by increased clock frequency - has come to an end. Increasing clock frequency now leads to power consumption costs that are too high to justify. As a result, we have seen in recent years that the processor frequencies have peaked and are receding from their high point. At the same time, competitive market conditions are giving business advantage to those companies that can field new streaming applications, handle larger data sets, and update their models to market conditions faster. The desire for newer, faster and larger is driving continued demand for higher computer performance.

Exact diagonalization of quantum lattice models on coprocessors

NASA Astrophysics Data System (ADS)

Siro, T.; Harju, A.

2016-10-01

We implement the Lanczos algorithm on an Intel Xeon Phi coprocessor and compare its performance to a multi-core Intel Xeon CPU and an NVIDIA graphics processor. The Xeon and the Xeon Phi are parallelized with OpenMP and the graphics processor is programmed with CUDA. The performance is evaluated by measuring the execution time of a single step in the Lanczos algorithm. We study two quantum lattice models with different particle numbers, and conclude that for small systems, the multi-core CPU is the fastest platform, while for large systems, the graphics processor is the clear winner, reaching speedups of up to 7.6 compared to the CPU. The Xeon Phi outperforms the CPU with sufficiently large particle number, reaching a speedup of 2.5.

Developing software to use parallel processing effectively. Final report, June-December 1987

DOE Office of Scientific and Technical Information (OSTI.GOV)

Center, J.

1988-10-01

This report describes the difficulties involved in writing efficient parallel programs and describes the hardware and software support currently available for generating software that utilizes processing effectively. Historically, the processing rate of single-processor computers has increased by one order of magnitude every five years. However, this pace is slowing since electronic circuitry is coming up against physical barriers. Unfortunately, the complexity of engineering and research problems continues to require ever more processing power (far in excess of the maximum estimated 3 Gflops achievable by single-processor computers). For this reason, parallel-processing architectures are receiving considerable interest, since they offer high performancemore » more cheaply than a single-processor supercomputer, such as the Cray.« less

Compiler analysis for irregular problems in FORTRAN D

NASA Technical Reports Server (NTRS)

Vonhanxleden, Reinhard; Kennedy, Ken; Koelbel, Charles; Das, Raja; Saltz, Joel

1992-01-01

We developed a dataflow framework which provides a basis for rigorously defining strategies to make use of runtime preprocessing methods for distributed memory multiprocessors. In many programs, several loops access the same off-processor memory locations. Our runtime support gives us a mechanism for tracking and reusing copies of off-processor data. A key aspect of our compiler analysis strategy is to determine when it is safe to reuse copies of off-processor data. Another crucial function of the compiler analysis is to identify situations which allow runtime preprocessing overheads to be amortized. This dataflow analysis will make it possible to effectively use the results of interprocedural analysis in our efforts to reduce interprocessor communication and the need for runtime preprocessing.

A Conformance Test Suite for Arden Syntax Compilers and Interpreters.

PubMed

Wolf, Klaus-Hendrik; Klimek, Mike

2016-01-01

The Arden Syntax for Medical Logic Modules is a standardized and well-established programming language to represent medical knowledge. To test the compliance level of existing compilers and interpreters no public test suite exists. This paper presents the research to transform the specification into a set of unit tests, represented in JUnit. It further reports on the utilization of the test suite testing four different Arden Syntax processors. The presented and compared results reveal the status conformance of the tested processors. How test driven development of Arden Syntax processors can help increasing the compliance with the standard is described with two examples. In the end some considerations how an open source test suite can improve the development and distribution of the Arden Syntax are presented.

Assessment of directionality performances: comparison between Freedom and CP810 sound processors.

PubMed

Razza, Sergio; Albanese, Greta; Ermoli, Lucilla; Zaccone, Monica; Cristofari, Eliana

2013-10-01

To compare speech recognition in noise for the Nucleus Freedom and CP810 sound processors using different directional settings among those available in the SmartSound portfolio. Single-subject, repeated measures study. Tertiary care referral center. Thirty-one monoaurally and binaurally implanted subjects (24 children and 7 adults) were enrolled. They were all experienced Nucleus Freedom sound processor users and achieved a 100% open set word recognition score in quiet listening conditions. Each patient was fitted with the Freedom and the CP810 processor. The program setting incorporated Adaptive Dynamic Range Optimization (ADRO) and adopted the directional algorithm BEAM (both devices) and ZOOM (only on CP810). Speech reception threshold (SRT) was assessed in a free-field layout, with disyllabic word list and interfering multilevel babble noise in the 3 different pre-processing configurations. On average, CP810 improved significantly patients' SRTs as compared to Freedom SP after 1 hour of use. Instead, no significant difference was observed in patients' SRT between the BEAM and the ZOOM algorithm fitted in the CP810 processor. The results suggest that hardware developments achieved in the design of CP810 allow an immediate and relevant directional advantage as compared to the previous-generation Freedom device.

Dynamically programmable cache

NASA Astrophysics Data System (ADS)

Nakkar, Mouna; Harding, John A.; Schwartz, David A.; Franzon, Paul D.; Conte, Thomas

1998-10-01

Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).

7 CFR 1435.319 - Appeals and arbitration.

Code of Federal Regulations, 2010 CFR

2010-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.319 Appeals and arbitration. (a) A person adversely affected by any determination made...

7 CFR 1435.319 - Appeals and arbitration.

Code of Federal Regulations, 2011 CFR

2011-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.319 Appeals and arbitration. (a) A person adversely affected by any determination made...

7 CFR 1435.319 - Appeals and arbitration.

Code of Federal Regulations, 2014 CFR

2014-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.319 Appeals and arbitration. (a) A person adversely affected by any determination made...

7 CFR 1435.319 - Appeals and arbitration.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.319 Appeals and arbitration. (a) A person adversely affected by any determination made...

7 CFR 1435.319 - Appeals and arbitration.

Code of Federal Regulations, 2012 CFR

2012-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.319 Appeals and arbitration. (a) A person adversely affected by any determination made...

Effective Vectorization with OpenMP 4.5

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huber, Joseph N.; Hernandez, Oscar R.; Lopez, Matthew Graham

This paper describes how the Single Instruction Multiple Data (SIMD) model and its extensions in OpenMP work, and how these are implemented in different compilers. Modern processors are highly parallel computational machines which often include multiple processors capable of executing several instructions in parallel. Understanding SIMD and executing instructions in parallel allows the processor to achieve higher performance without increasing the power required to run it. SIMD instructions can significantly reduce the runtime of code by executing a single operation on large groups of data. The SIMD model is so integral to the processor s potential performance that, if SIMDmore » is not utilized, less than half of the processor is ever actually used. Unfortunately, using SIMD instructions is a challenge in higher level languages because most programming languages do not have a way to describe them. Most compilers are capable of vectorizing code by using the SIMD instructions, but there are many code features important for SIMD vectorization that the compiler cannot determine at compile time. OpenMP attempts to solve this by extending the C++/C and Fortran programming languages with compiler directives that express SIMD parallelism. OpenMP is used to pass hints to the compiler about the code to be executed in SIMD. This is a key resource for making optimized code, but it does not change whether or not the code can use SIMD operations. However, in many cases critical functions are limited by a poor understanding of how SIMD instructions are actually implemented, as SIMD can be implemented through vector instructions or simultaneous multi-threading (SMT). We have found that it is often the case that code cannot be vectorized, or is vectorized poorly, because the programmer does not have sufficient knowledge of how SIMD instructions work.« less

Maritime dynamic traffic generator : Volume II. Electronic data processing program.

DOT National Transportation Integrated Search

1975-06-01

The processor program is designed to move 18,000 merchant vessels along standard routes to their destination and keep statistical records of the ports visited, the five degree squares passed through and the occurrence of casualties. This document pre...

CYBER-205 Devectorizer

NASA Technical Reports Server (NTRS)

Lakeotes, Christopher D.

1990-01-01

DEVECT (CYBER-205 Devectorizer) is CYBER-205 FORTRAN source-language-preprocessor computer program reducing vector statements to standard FORTRAN. In addition, DEVECT has many other standard and optional features simplifying conversion of vector-processor programs for CYBER 200 to other computers. Written in FORTRAN IV.

Geospace simulations on the Cell BE processor

NASA Astrophysics Data System (ADS)

Germaschewski, K.; Raeder, J.; Larson, D.

2008-12-01

OpenGGCM (Open Geospace General circulation Model) is an established numerical code that simulates the Earth's space environment. The most computing intensive part is the MHD (magnetohydrodynamics) solver that models the plasma surrounding Earth and its interaction with Earth's magnetic field and the solar wind flowing in from the sun. Like other global magnetosphere codes, OpenGGCM's realism is limited by computational constraints on grid resolution. We investigate porting of the MHD solver to the Cell BE architecture, a novel inhomogeneous multicore architecture capable of up to 230 GFlops per processor. Realizing this high performance on the Cell processor is a programming challenge, though. We implemented the MHD solver using a multi-level parallel approach: On the coarsest level, the problem is distributed to processors based upon the usual domain decomposition approach. Then, on each processor, the problem is divided into 3D columns, each of which is handled by the memory limited SPEs (synergistic processing elements) slice by slice. Finally, SIMD instructions are used to fully exploit the vector/SIMD FPUs in each SPE. Memory management needs to be handled explicitly by the code, using DMA to move data from main memory to the per-SPE local store and vice versa. We obtained excellent performance numbers, a speed-up of a factor of 25 compared to just using the main processor, while still keeping the numerical implementation details of the code maintainable.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

NASA Astrophysics Data System (ADS)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

Second International Workshop on Software Engineering and Code Design in Parallel Meteorological and Oceanographic Applications

NASA Technical Reports Server (NTRS)

OKeefe, Matthew (Editor); Kerr, Christopher L. (Editor)

1998-01-01

This report contains the abstracts and technical papers from the Second International Workshop on Software Engineering and Code Design in Parallel Meteorological and Oceanographic Applications, held June 15-18, 1998, in Scottsdale, Arizona. The purpose of the workshop is to bring together software developers in meteorology and oceanography to discuss software engineering and code design issues for parallel architectures, including Massively Parallel Processors (MPP's), Parallel Vector Processors (PVP's), Symmetric Multi-Processors (SMP's), Distributed Shared Memory (DSM) multi-processors, and clusters. Issues to be discussed include: (1) code architectures for current parallel models, including basic data structures, storage allocation, variable naming conventions, coding rules and styles, i/o and pre/post-processing of data; (2) designing modular code; (3) load balancing and domain decomposition; (4) techniques that exploit parallelism efficiently yet hide the machine-related details from the programmer; (5) tools for making the programmer more productive; and (6) the proliferation of programming models (F--, OpenMP, MPI, and HPF).

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

NASA Technical Reports Server (NTRS)

Lindgren, R. W.; Tarbell, T. D.

1981-01-01

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Ft. Collins sugar beet germplasm evaluated for rhizomania and storage rot resistance in Idaho, 2015

USDA-ARS?s Scientific Manuscript database

Fifty-seven sugar beet (Beta vulgaris L.) lines from the USDA-ARS Ft. Collins sugar beet program and four check cultivars were screened for resistance to Beet necrotic yellow vein virus (BNYVV), the causal agent of rhizomania, and storage rot. The rhizomania evaluation was conducted at the USDA-ARS...

A pilot randomized trial of a cognitive reappraisal obesity prevention program.

PubMed

Stice, Eric; Yokum, Sonja; Burger, Kyle; Rohde, Paul; Shaw, Heather; Gau, Jeff M

2015-01-01

Evaluate a selective obesity prevention program promoting use of cognitive reappraisals to reduce reward region response and increase inhibitory region response to high-fat/high-sugar foods and reduce intake of fat and sugar to prevent blunted reward region response to intake of such foods. Young adults at risk for future weight gain by virtue of weight concerns (N=148) were randomized to this new prevention program (Minding Health), an alternative prevention program promoting participant-driven gradual reductions in caloric intake and increases in physical activity (Healthy Weight), or an obesity education video control condition, completing assessments at pre-, post-, and 6-month follow-up. A subset of Minding Health and control participants completed an fMRI scan at pre- and post-assessing neural response to images of high-fat/sugar foods and to receipt and anticipated receipt of a high-fat/sugar food. Minding Health participants showed significantly greater reductions in body fat than controls and caloric intake from fat and sugar than Healthy Weight participants. Minding Health participants also showed greater activation of an inhibitory control region and reduced activation of an attention/expectation region in response to palatable food images relative to pretest and controls. However, Healthy Weight participants showed greater reductions in BMI and eating disorder symptoms than Minding Health participants. Although the Minding Health intervention produced some of the hypothesized effects, it did not produce lasting reductions in body fat or BMI and showed limited effects on neural responsivity, implying it will be vital to increase the efficacy of this new prevention program. Copyright © 2014 Elsevier Inc. All rights reserved.

7 CFR 1435.317 - Revisions of allocations and proportionate shares.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.317 Revisions of allocations and proportionate shares. The...

7 CFR 1435.317 - Revisions of allocations and proportionate shares.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.317 Revisions of allocations and proportionate shares. The...

7 CFR 1435.317 - Revisions of allocations and proportionate shares.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.317 Revisions of allocations and proportionate shares. The...

7 CFR 1435.317 - Revisions of allocations and proportionate shares.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.317 Revisions of allocations and proportionate shares. The...

7 CFR 1435.317 - Revisions of allocations and proportionate shares.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.317 Revisions of allocations and proportionate shares. The...

Monitoring Data-Structure Evolution in Distributed Message-Passing Programs

NASA Technical Reports Server (NTRS)

Sarukkai, Sekhar R.; Beers, Andrew; Woodrow, Thomas S. (Technical Monitor)

1996-01-01

Monitoring the evolution of data structures in parallel and distributed programs, is critical for debugging its semantics and performance. However, the current state-of-art in tracking and presenting data-structure information on parallel and distributed environments is cumbersome and does not scale. In this paper we present a methodology that automatically tracks memory bindings (not the actual contents) of static and dynamic data-structures of message-passing C programs, using PVM. With the help of a number of examples we show that in addition to determining the impact of memory allocation overheads on program performance, graphical views can help in debugging the semantics of program execution. Scalable animations of virtual address bindings of source-level data-structures are used for debugging the semantics of parallel programs across all processors. In conjunction with light-weight core-files, this technique can be used to complement traditional debuggers on single processors. Detailed information (such as data-structure contents), on specific nodes, can be determined using traditional debuggers after the data structure evolution leading to the semantic error is observed graphically.

Suppression of the vacuolar invertase gene delays senescent sweetening in chipping potatoes.

PubMed

Wiberley-Bradford, Amy E; Bethke, Paul C

2018-01-01

Potato chip processors require potato tubers that meet quality specifications for fried chip color, and color depends largely upon tuber sugar contents. At later times in storage, potatoes accumulate sucrose, glucose, and fructose. This developmental process, senescent sweetening, manifests as a blush of color near the center of the fried chip, becomes more severe with time, and limits the storage period. Vacuolar invertase (VInv) converts sucrose to glucose and fructose and is hypothesized to play a role in senescent sweetening. To test this hypothesis, senescent sweetening was quantified in multiple lines of potato with reduced VInv expression. Chip darkening from senescent sweetening was delayed by about 4 weeks for tubers with reduced VInv expression. A strong positive correlation between frequency of dark chips and tuber hexose content was observed. Tubers with reduced VInv expression had lower hexose to sucrose ratios than controls. VInv activity contributes to reducing sugar accumulation during senescent sweetening. Sucrose breakdown during frying may contribute to chip darkening. Suppressing VInv expression increases the storage period of the chipping potato crop, which is an important consideration, as potatoes with reduced VInv expression are entering commercial production in the USA. © 2017 Society of Chemical Industry. © 2017 Society of Chemical Industry.

Software Reviews: Programs Worth a Second Look.

ERIC Educational Resources Information Center

Classroom Computer Learning, 1989

1989-01-01

Reviews three software programs: (1) "Microsoft Works 2.0": word processing, data processing, and telecommunications, grades 7 and up; (2) "AppleWorks GS": word processor, database, spreadsheet, graphics, and telecommunications, grades 3-12, Apple IIGS; (3) "Choices, Choices: On the Playground, Taking Responsibility":…

DJANAL user's manual

NASA Technical Reports Server (NTRS)

Pitts, E. R.

1976-01-01

The DJANAL (DisJunct ANALyzer) Program provides a means for the LSI designer to format output from the Mask Analysis Program (MAP) for input to the FETLOG (FETSIM/LOGSIM) processor. This document presents a brief description of the operation of DJANAL and provides comprehensive instruction for its use.

Designing systems to satisfy their users - The coming changes in aviation weather and the development of a central weather processor

NASA Technical Reports Server (NTRS)

Bush, M. W.

1984-01-01

Attention is given to the development history of the Central Weather Processor (CWP) program of the Federal Aviation Administration. The CWP will interface with high speed digital communications links, accept data and information products from new sources, generate data processing products, and provide meteorologists with the capability to automate data retrieval and dissemination. The CWP's users are operational (air traffic controllers, meteorologists and pilots), institutional (logistics, maintenance, testing and evaluation personnel), and administrative.

A Linked-Cell Domain Decomposition Method for Molecular Dynamics Simulation on a Scalable Multiprocessor

DOE PAGES

Yang, L. H.; Brooks III, E. D.; Belak, J.

1992-01-01

A molecular dynamics algorithm for performing large-scale simulations using the Parallel C Preprocessor (PCP) programming paradigm on the BBN TC2000, a massively parallel computer, is discussed. The algorithm uses a linked-cell data structure to obtain the near neighbors of each atom as time evoles. Each processor is assigned to a geometric domain containing many subcells and the storage for that domain is private to the processor. Within this scheme, the interdomain (i.e., interprocessor) communication is minimized.

Navy Budget: Potential Reductions for Research, Development, Test, and Evaluation

DTIC Science & Technology

1990-11-01

available for use in future Navy programs, including the MK-50 tor- pedo and Vertical Launch Antisubmarine Rocket. A total of $49.9 million of fiscal...346 Travel 03 07 + 04 Support 224 225 + 01 Total Requested $122.61 $122.61 -0- In addition, the Navy plans to acquire six Acoustic Video Processor...units at $2.4 million in fiscal year 1991. The Acoustic Video Processor pro- gram is experiencing development problems, and the full-scale develop- ment

Template Based Low Data Rate Speech Encoder

DTIC Science & Technology

1993-09-30

Nasality Distinguishes In/ from d/ 95.6 96.9 1m/ from /b/, etc. Sustention Distinguishes /f/ from /p/, $7.5 88.3 ibi from N/, Al from /0 8. etc. Sibilation...processor performs mainly Processor Workstation input/output (I/O) operations. The dynamic random access memory (DRAM) has 16 million bytes of...storage capacity. To execute the 800-b/s voice algorithm, the following amount of memory is needed: 5 MB for tables, 1.5 MB for it "program, and 30 KB for

Hypercluster Parallel Processor

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Cole, Gary L.; Milner, Edward J.; Quealy, Angela

1992-01-01

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

[Effects of the PROALCOOL program on migratory behavior in the state of Sao Paulo: the case of Ribeirao Preto].

PubMed

1983-01-01

The National Program of Alcohol, PROALCOOL, started in November 1975, was created in response to the 1st petroleum crisis. Petroleum prices elevated suddenly between 1973 and 1974, and the cost of importing fuel increased extraordinarily. The PROALCOOL program was still in the early stages of development at the end of the decade when the 2nd petroleum crisis worsened the Brazilian energy situation even further. PROALCOOL had its institutional base strengthened in 1979, and new objectives and more ambitious goals were outlined for the program. A production goal of 10.7 billion liters of alcohol was set for 1985 which would essentially cover the predicted increase in consumption of gasoline for the country. The goal was equivalent, in energy terms, to making Brazil self-sufficient. The automobile industry in Brazil had been intensively developing in the 1970s, turning itself into a fundamental sector in the general process of Brazil's economic development. The distribution of goods in the country is intimately linked to highway transportation; the percentage of products transported by rail and shipping is relatively small. Urban transport is also still based on the automobile for individual transportation and the bus for mass transit. The industrial structure of Brazil was developed with an elevated dependence on gasoline, and until the 2nd crisis few had made any alterations in this picture. Although the primary cause for the development of PROALCOOL was the sharp increase in petroleum prices, another impetus was the collapse of sugar prices on the world market in November 1974. With the creation of PROALCOOL, sugar was transformed from sugar into alcohol, strengthening the options for its use. Response to the stimulus of the program came primarily from the sugar producers, who undertook rapid construction of "annex" distilleries to use the sugar. It was PROALCOOL's response to economic conditions that imparted new life into the sugar agroindustry in the State of Sao Paulo, particularly in the region of Ribeiros Preto.

Long-Term Evolution of the Electrical Stimulation Levels for Cochlear Implant Patients

PubMed Central

Vargas, Jose Luis; Sainz, Manuel; Roldan, Cristina; de la Torre, Angel

2012-01-01

Objectives The stimulation levels programmed in cochlear implant systems are affected by an evolution since the first switch-on of the processor. This study was designed to evaluate the changes in stimulation levels over time and the relationship between post-implantation physiological changes and with the hearing experience provided by the continuous use of the cochlear implant. Methods Sixty-two patients, ranging in age from 4 to 68 years at the moment of implantation participated in this study. All subjects were implanted with the 12 channels COMBI 40+ cochlear implant at San Cecilio University Hospital, Granada, Spain. Hearing loss etiology and progression characteristics varied across subjects. Results The analyzed programming maps show that the stimulation levels suffer a fast evolution during the first weeks after the first switch-on of the processor. Then, the evolution becomes slower and the programming parameters tend to be stable at about 6 months after the first switch-on. The evolution of the stimulation levels implies an increment of the electrical dynamic range, which is increased from 15.4 to 20.7 dB and improves the intensity resolution. A significant increment of the sensitivity to acoustic stimuli is also observed. For some patients, we have also observed transitory changes in the electrode impedances associated to secretory otitis media, which cause important changes in the programming maps. Conclusion We have studied the long-term evolution of the stimulation levels in cochlear implant patients. Our results show the importance of systematic measurements of the electrode impedances before the revision of the programming map. This report also highlights that the evolution of the programming maps is an important factor to be considered in order to determine an adequate calendar fitting of the cochlear implant processor. PMID:23205223

7 CFR 1435.314 - Temporary transfer of proportionate share due to disasters.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.314 Temporary transfer of proportionate share due to...

7 CFR 1435.314 - Temporary transfer of proportionate share due to disasters.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.314 Temporary transfer of proportionate share due to...

7 CFR 1435.314 - Temporary transfer of proportionate share due to disasters.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.314 Temporary transfer of proportionate share due to...

7 CFR 1435.314 - Temporary transfer of proportionate share due to disasters.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.314 Temporary transfer of proportionate share due to...

7 CFR 1435.314 - Temporary transfer of proportionate share due to disasters.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.314 Temporary transfer of proportionate share due to...

Carbohydrate crops as a renewable resource for fuels production. Volume III. Juice preservation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fink, D.J.; Allen, B.R.; Litchfield, J.H.

1980-01-29

The objective of this study was to evaluate a process to preserve sugar crop juices. The process is energy conserving in that concentrated sugar solutions are produced with little evaporation of water. A preliminary investigation was conducted of polysaccharide hydrolysis as a means for preserving mixed sugar solutions obtained from crops such as sweet sorghum. Four subtasks have been addressed during this report period: I. Concentration of Pure Sugar Solutions by Hydrolysis of Purified Starch; II. Concentration of Genuine Sugar Crop Juice by Hydrolysis of Purified Starch; III. Concentration of Pure Sugar Solutions by Hydrolysis of Genuine Biomass Starch; andmore » IV. Concentration of Pure Sugar Solutions by Hydrolysis of Cellulosic Materials. The results obtained from the experiments conducted in Subtasks I and II included the following: (1) Concentrated sucrose-glucose-fructose solutions (greater than 50 percent) can be prepared from simulated or actual sweet sorghum juice using enzymatic thinning and saccharification of pure starch-sugar solution mixtures. (2) Enzymatic saccharification of corn meal and cracked wheat in simulated sorghum juice was also demonstrated. (3) Concentration of sugar solutions also can be accomplished by saccharification of cellulosic materials. In our experiments, inhibition of the cellobiase component of the cellulase preparation was observed. The hydrolysis studies were directed to the demonstration of the feasibility of one approach to the preparation of concentrated, microbiologically stable sugar syrups starting with sweet sorghum juice. Future work on Subtask V of this program will continue the investigations already underway and will consider other approaches to the stabilization of juices. Subtask VI of this program will consider the process economics of the Subtask I to IV approaches, or combinations of two or more methods, that are considered to be most feasible for juice preservation.« less

APT - NASA ENHANCED VERSION OF AUTOMATICALLY PROGRAMMED TOOL SOFTWARE - STAND-ALONE VERSION

NASA Technical Reports Server (NTRS)

Premo, D. A.

1994-01-01

The APT code is one of the most widely used software tools for complex numerically controlled (N/C) machining. APT is an acronym for Automatically Programmed Tools and is used to denote both a language and the computer software that processes that language. Development of the APT language and software system was begun over twenty years ago as a U. S. government sponsored industry and university research effort. APT is a "problem oriented" language that was developed for the explicit purpose of aiding the N/C machine tools. Machine-tool instructions and geometry definitions are written in the APT language to constitute a "part program." The APT part program is processed by the APT software to produce a cutter location (CL) file. This CL file may then be processed by user supplied post processors to convert the CL data into a form suitable for a particular N/C machine tool. This June, 1989 offering of the APT system represents an adaptation, with enhancements, of the public domain version of APT IV/SSX8 to the DEC VAX-11/780 for use by the Engineering Services Division of the NASA Goddard Space Flight Center. Enhancements include the super pocket feature which allows concave and convex polygon shapes of up to 40 points including shapes that overlap, that leave islands of material within the pocket, and that have one or more arcs as part of the pocket boundary. Recent modifications to APT include a rework of the POCKET subroutine and correction of an error that prevented the use within a macro of a macro variable cutter move statement combined with macro variable double check surfaces. Former modifications included the expansion of array and buffer sizes to accommodate larger part programs, and the insertion of a few user friendly error messages. The APT system software on the DEC VAX-11/780 is organized into two separate programs: the load complex and the APT processor. The load complex handles the table initiation phase and is usually only run when changes to the APT processor capabilities are made. This phase initializes character recognition and syntax tables for the APT processor by creating FORTRAN block data programs. The APT processor consists of four components: the translator, the execution complex, the subroutine library, and the CL editor. The translator examines each APT statement in the part program for recognizable structure and generates a new statement, or series of statements, in an intermediate language. The execution complex processes all of the definition, motion, and related statements to generate cutter location coordinates. The subroutine library contains routines defining the algorithms required to process the sequenced list of intermediate language commands generated by the translator. The CL editor re-processes the cutter location coordinates according to user supplied commands to generate a final CL file. A sample post processor is also included which translates a CL file into a form for use with a Wales Strippit Fabramatic Model 30/30 sheet metal punch. The user should be able to readily develop post processors for other N/C machine tools. The APT language is a statement oriented, sequence dependent language. With the exception of such programming techniques as looping and macros, statements in an APT program are executed in a strict first-to-last sequence. In order to provide programming capability for the broadest possible range of parts and of machine tools, APT input (and output) is generalized, as represented by 3-dimensional geometry and tools, and arbitrarily uniform, as represented by the moving tool concept and output data in absolute coordinates. A command procedure allows the user to select the desired part program, ask for a graphics file of cutter motions in IGES format, and submit the procedure as a batch job, if desired. The APT system software is written in FORTRAN 77 for batch and interactive execution and has been implemented on a DEC VAX series computer under VMS 4.4. The enhancements for this version of APT were last updated in June, 1989. The NASA adaptation, with enhancements, of the public domain version of the APT IV/SSX8 software to the DEC VAX-11/780 is available by license for a period of ten (10) years to approved licensees. The licensed program product delivered includes the APT IV/SSX8 system source code, object code, executable images, and command procedures and one set of supporting documentation. Additional copies of the supporting documentation may be purchased at any time at the price indicated below.

Sugar Industry Influence on the Scientific Agenda of the National Institute of Dental Research’s 1971 National Caries Program: A Historical Analysis of Internal Documents

PubMed Central

Kearns, Cristin E.; Glantz, Stanton A.; Schmidt, Laura A.

2015-01-01

Background In 1966, the National Institute of Dental Research (NIDR) began planning a targeted research program to identify interventions for widespread application to eradicate dental caries (tooth decay) within a decade. In 1971, the NIDR launched the National Caries Program (NCP). The objective of this paper is to explore the sugar industry’s interaction with the NIDR to alter the research priorities of the NIDR NCP. Methods and Findings We used internal cane and beet sugar industry documents from 1959 to 1971 to analyze industry actions related to setting research priorities for the NCP. The sugar industry could not deny the role of sucrose in dental caries given the scientific evidence. They therefore adopted a strategy to deflect attention to public health interventions that would reduce the harms of sugar consumption rather than restricting intake. Industry tactics included the following: funding research in collaboration with allied food industries on enzymes to break up dental plaque and a vaccine against tooth decay with questionable potential for widespread application, cultivation of relationships with the NIDR leadership, consulting of members on an NIDR expert panel, and submission of a report to the NIDR that became the foundation of the first request for proposals issued for the NCP. Seventy-eight percent of the sugar industry submission was incorporated into the NIDR’s call for research applications. Research that could have been harmful to sugar industry interests was omitted from priorities identified at the launch of the NCP. Limitations are that this analysis relies on one source of sugar industry documents and that we could not interview key actors. Conclusions The NCP was a missed opportunity to develop a scientific understanding of how to restrict sugar consumption to prevent tooth decay. A key factor was the alignment of research agendas between the NIDR and the sugar industry. This historical example illustrates how industry protects itself from potentially damaging research, which can inform policy makers today. Industry opposition to current policy proposals—including a World Health Organization guideline on sugars proposed in 2014 and changes to the nutrition facts panel on packaged food in the US proposed in 2014 by the US Food and Drug Administration—should be carefully scrutinized to ensure that industry interests do not supersede public health goals. PMID:25756179

Blending Better Beverage Options: A Nutrition Education and Experiential Workshop for Youths

PubMed Central

Isoldi, Kathy K.; Dolar, Veronika

2015-01-01

Objective. To reduce intake of sugar-sweetened beverages (SSBs) in youths as a means to reduce obesity risk. Methods. Youths 5–14 years old attending a summer program were given a two-hour workshop addressing the sugar content in SSBs, the health risks from drinking SSBs, and hands-on preparation as well as tastings of low-sugar beverage alternatives. Data on usual intake of SSBs was obtained at baseline, and pre- and postprogram surveys were conducted to gauge change in knowledge and/or attitudes regarding SSBs. Results. There were 128 participants (63% male) in the program. SSBs were commonly consumed with over 80% reporting regular consumption (mean daily intake 17.9 ounces). Significant increase in knowledge regarding the sugar content of commonly consumed SSBs was achieved; however change in attitudes was not significant. The large majority of youths reported enjoying the workshop and intention to reduce intake of SSBs following program participation. Conclusion. SSBs are commonly consumed by youths. Knowledge regarding the sugar content of SSBs is easier to impart to youths than influencing attitudes held about these beverages. Long-term interventions that reach out to parents and address the widespread availability of SSBs are needed to influence resistant attitudes and beverage choosing behaviors in youths. PMID:25874119

Echo movement and evolution from real-time processing.

NASA Technical Reports Server (NTRS)

Schaffner, M. R.

1972-01-01

Preliminary experimental data on the effectiveness of conventional radars in measuring the movement and evolution of meteorological echoes when the radar is connected to a programmable real-time processor are examined. In the processor programming is accomplished by conceiving abstract machines which constitute the actual programs used in the methods employed. An analysis of these methods, such as the center of gravity method, the contour-displacement method, the method of slope, the cross-section method, the contour crosscorrelation method, the method of echo evolution at each point, and three-dimensional measurements, shows that the motions deduced from them may differ notably (since each method determines different quantities) but the plurality of measurement may give additional information on the characteristics of the precipitation.

Moving target, distributed, real-time simulation using Ada

NASA Technical Reports Server (NTRS)

Collins, W. R.; Feyock, S.; King, L. A.; Morell, L. J.

1985-01-01

Research on a precompiler solution is described for the moving target compiler problem encountered when trying to run parallel simulation algorithms on several microcomputers. The precompiler is under development at NASA-Lewis for simulating jet engines. Since the behavior of any component of a jet engine, e.g., the fan inlet, rear duct, forward sensor, etc., depends on the previous behaviors and not the current behaviors of other components, the behaviors can be modeled on different processors provided the outputs of the processors reach other processors in appropriate time intervals. The simulator works in compute and transfer modes. The Ada procedure sets for the behaviors of different components are divided up and routed by the precompiler, which essentially receives a multitasking program. The subroutines are synchronized after each computation cycle.

Acousto-optic time- and space-integrating spotlight-mode SAR processor

NASA Astrophysics Data System (ADS)

Haney, Michael W.; Levy, James J.; Michael, Robert R., Jr.

1993-09-01

The technical approach and recent experimental results for the acousto-optic time- and space- integrating real-time SAR image formation processor program are reported. The concept overcomes the size and power consumption limitations of electronic approaches by using compact, rugged, and low-power analog optical signal processing techniques for the most computationally taxing portions of the SAR imaging problem. Flexibility and performance are maintained by the use of digital electronics for the critical low-complexity filter generation and output image processing functions. The results include a demonstration of the processor's ability to perform high-resolution spotlight-mode SAR imaging by simultaneously compensating for range migration and range/azimuth coupling in the analog optical domain, thereby avoiding a highly power-consuming digital interpolation or reformatting operation usually required in all-electronic approaches.

A new version of the CADNA library for estimating round-off error propagation in Fortran programs

NASA Astrophysics Data System (ADS)

Jézéquel, Fabienne; Chesneaux, Jean-Marie; Lamotte, Jean-Luc

2010-11-01

The CADNA library enables one to estimate, using a probabilistic approach, round-off error propagation in any simulation program. CADNA provides new numerical types, the so-called stochastic types, on which round-off errors can be estimated. Furthermore CADNA contains the definition of arithmetic and relational operators which are overloaded for stochastic variables and the definition of mathematical functions which can be used with stochastic arguments. On 64-bit processors, depending on the rounding mode chosen, the mathematical library associated with the GNU Fortran compiler may provide incorrect results or generate severe bugs. Therefore the CADNA library has been improved to enable the numerical validation of programs on 64-bit processors. New version program summaryProgram title: CADNA Catalogue identifier: AEAT_v1_1 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEAT_v1_1.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 28 488 No. of bytes in distributed program, including test data, etc.: 463 778 Distribution format: tar.gz Programming language: Fortran NOTE: A C++ version of this program is available in the Library as AEGQ_v1_0 Computer: PC running LINUX with an i686 or an ia64 processor, UNIX workstations including SUN, IBM Operating system: LINUX, UNIX Classification: 6.5 Catalogue identifier of previous version: AEAT_v1_0 Journal reference of previous version: Comput. Phys. Commun. 178 (2008) 933 Does the new version supersede the previous version?: Yes Nature of problem: A simulation program which uses floating-point arithmetic generates round-off errors, due to the rounding performed at each assignment and at each arithmetic operation. Round-off error propagation may invalidate the result of a program. The CADNA library enables one to estimate round-off error propagation in any simulation program and to detect all numerical instabilities that may occur at run time. Solution method: The CADNA library [1-3] implements Discrete Stochastic Arithmetic [4,5] which is based on a probabilistic model of round-off errors. The program is run several times with a random rounding mode generating different results each time. From this set of results, CADNA estimates the number of exact significant digits in the result that would have been computed with standard floating-point arithmetic. Reasons for new version: On 64-bit processors, the mathematical library associated with the GNU Fortran compiler may provide incorrect results or generate severe bugs with rounding towards -∞ and +∞, which the random rounding mode is based on. Therefore a particular definition of mathematical functions for stochastic arguments has been included in the CADNA library to enable its use with the GNU Fortran compiler on 64-bit processors. Summary of revisions: If CADNA is used on a 64-bit processor with the GNU Fortran compiler, mathematical functions are computed with rounding to the nearest, otherwise they are computed with the random rounding mode. It must be pointed out that the knowledge of the accuracy of the stochastic argument of a mathematical function is never lost. Restrictions: CADNA requires a Fortran 90 (or newer) compiler. In the program to be linked with the CADNA library, round-off errors on complex variables cannot be estimated. Furthermore array functions such as product or sum must not be used. Only the arithmetic operators and the abs, min, max and sqrt functions can be used for arrays. Additional comments: In the library archive, users are advised to read the INSTALL file first. The doc directory contains a user guide named ug.cadna.pdf which shows how to control the numerical accuracy of a program using CADNA, provides installation instructions and describes test runs. The source code, which is located in the src directory, consists of one assembly language file (cadna_rounding.s) and eighteen Fortran language files. cadna_rounding.s is a symbolic link to the assembly file corresponding to the processor and the Fortran compiler used. This assembly file contains routines which are frequently called in the CADNA Fortran files to change the rounding mode. The Fortran language files contain the definition of the stochastic types on which the control of accuracy can be performed, CADNA specific functions (for instance to enable or disable the detection of numerical instabilities), the definition of arithmetic and relational operators which are overloaded for stochastic variables and the definition of mathematical functions which can be used with stochastic arguments. The examples directory contains seven test runs which illustrate the use of the CADNA library and the benefits of Discrete Stochastic Arithmetic. Running time: The version of a code which uses CADNA runs at least three times slower than its floating-point version. This cost depends on the computer architecture and can be higher if the detection of numerical instabilities is enabled. In this case, the cost may be related to the number of instabilities detected.

On program restructuring, scheduling, and communication for parallel processor systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Polychronopoulos, Constantine D.

1986-08-01

This dissertation discusses several software and hardware aspects of program execution on large-scale, high-performance parallel processor systems. The issues covered are program restructuring, partitioning, scheduling and interprocessor communication, synchronization, and hardware design issues of specialized units. All this work was performed focusing on a single goal: to maximize program speedup, or equivalently, to minimize parallel execution time. Parafrase, a Fortran restructuring compiler was used to transform programs in a parallel form and conduct experiments. Two new program restructuring techniques are presented, loop coalescing and subscript blocking. Compile-time and run-time scheduling schemes are covered extensively. Depending on the program construct, thesemore » algorithms generate optimal or near-optimal schedules. For the case of arbitrarily nested hybrid loops, two optimal scheduling algorithms for dynamic and static scheduling are presented. Simulation results are given for a new dynamic scheduling algorithm. The performance of this algorithm is compared to that of self-scheduling. Techniques for program partitioning and minimization of interprocessor communication for idealized program models and for real Fortran programs are also discussed. The close relationship between scheduling, interprocessor communication, and synchronization becomes apparent at several points in this work. Finally, the impact of various types of overhead on program speedup and experimental results are presented.« less

FLY MPI-2: a parallel tree code for LSS

NASA Astrophysics Data System (ADS)

Becciani, U.; Comparato, M.; Antonuccio-Delogu, V.

2006-04-01

New version program summaryProgram title: FLY 3.1 Catalogue identifier: ADSC_v2_0 Licensing provisions: yes Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADSC_v2_0 Program obtainable from: CPC Program Library, Queen's University of Belfast, N. Ireland No. of lines in distributed program, including test data, etc.: 158 172 No. of bytes in distributed program, including test data, etc.: 4 719 953 Distribution format: tar.gz Programming language: Fortran 90, C Computer: Beowulf cluster, PC, MPP systems Operating system: Linux, Aix RAM: 100M words Catalogue identifier of previous version: ADSC_v1_0 Journal reference of previous version: Comput. Phys. Comm. 155 (2003) 159 Does the new version supersede the previous version?: yes Nature of problem: FLY is a parallel collisionless N-body code for the calculation of the gravitational force Solution method: FLY is based on the hierarchical oct-tree domain decomposition introduced by Barnes and Hut (1986) Reasons for the new version: The new version of FLY is implemented by using the MPI-2 standard: the distributed version 3.1 was developed by using the MPICH2 library on a PC Linux cluster. Today the FLY performance allows us to consider the FLY code among the most powerful parallel codes for tree N-body simulations. Another important new feature regards the availability of an interface with hydrodynamical Paramesh based codes. Simulations must follow a box large enough to accurately represent the power spectrum of fluctuations on very large scales so that we may hope to compare them meaningfully with real data. The number of particles then sets the mass resolution of the simulation, which we would like to make as fine as possible. The idea to build an interface between two codes, that have different and complementary cosmological tasks, allows us to execute complex cosmological simulations with FLY, specialized for DM evolution, and a code specialized for hydrodynamical components that uses a Paramesh block structure. Summary of revisions: The parallel communication schema was totally changed. The new version adopts the MPICH2 library. Now FLY can be executed on all Unix systems having an MPI-2 standard library. The main data structure, is declared in a module procedure of FLY (fly_h.F90 routine). FLY creates the MPI Window object for one-sided communication for all the shared arrays, with a call like the following: CALL MPI_WIN_CREATE(POS, SIZE, REAL8, MPI_INFO_NULL, MPI_COMM_WORLD, WIN_POS, IERR) the following main window objects are created: win_pos, win_vel, win_acc: particles positions velocities and accelerations, win_pos_cell, win_mass_cell, win_quad, win_subp, win_grouping: cells positions, masses, quadrupole momenta, tree structure and grouping cells. Other windows are created for dynamic load balance and global counters. Restrictions: The program uses the leapfrog integrator schema, but could be changed by the user. Unusual features: FLY uses the MPI-2 standard: the MPICH2 library on Linux systems was adopted. To run this version of FLY the working directory must be shared among all the processors that execute FLY. Additional comments: Full documentation for the program is included in the distribution in the form of a README file, a User Guide and a Reference manuscript. Running time: IBM Linux Cluster 1350, 512 nodes with 2 processors for each node and 2 GB RAM for each processor, at Cineca, was adopted to make performance tests. Processor type: Intel Xeon Pentium IV 3.0 GHz and 512 KB cache (128 nodes have Nocona processors). Internal Network: Myricom LAN Card "C" Version and "D" Version. Operating System: Linux SuSE SLES 8. The code was compiled using the mpif90 compiler version 8.1 and with basic optimization options in order to have performances that could be useful compared with other generic clusters Processors

49 CFR 236.921 - Training and qualification program, general.

Code of Federal Regulations, 2010 CFR

2010-10-01

... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.921 Training and qualification program..., wayside, or onboard subsystems; (2) Persons who dispatch train operations (issue or communicate any...

Automation of Data Traffic Control on DSM Architecture

NASA Technical Reports Server (NTRS)

Frumkin, Michael; Jin, Hao-Qiang; Yan, Jerry

2001-01-01

The design of distributed shared memory (DSM) computers liberates users from the duty to distribute data across processors and allows for the incremental development of parallel programs using, for example, OpenMP or Java threads. DSM architecture greatly simplifies the development of parallel programs having good performance on a few processors. However, to achieve a good program scalability on DSM computers requires that the user understand data flow in the application and use various techniques to avoid data traffic congestions. In this paper we discuss a number of such techniques, including data blocking, data placement, data transposition and page size control and evaluate their efficiency on the NAS (NASA Advanced Supercomputing) Parallel Benchmarks. We also present a tool which automates the detection of constructs causing data congestions in Fortran array oriented codes and advises the user on code transformations for improving data traffic in the application.

Single Event Upset Analysis: On-orbit performance of the Alpha Magnetic Spectrometer Digital Signal Processor Memory aboard the International Space Station

NASA Astrophysics Data System (ADS)

Li, Jiaqiang; Choutko, Vitaly; Xiao, Liyi

2018-03-01

Based on the collection of error data from the Alpha Magnetic Spectrometer (AMS) Digital Signal Processors (DSP), on-orbit Single Event Upsets (SEUs) of the DSP program memory are analyzed. The daily error distribution and time intervals between errors are calculated to evaluate the reliability of the system. The particle density distribution of International Space Station (ISS) orbit is presented and the effects from the South Atlantic Anomaly (SAA) and the geomagnetic poles are analyzed. The impact of solar events on the DSP program memory is carried out combining data analysis and Monte Carlo simulation (MC). From the analysis and simulation results, it is concluded that the area corresponding to the SAA is the main source of errors on the ISS orbit. Solar events can also cause errors on DSP program memory, but the effect depends on the on-orbit particle density.

Neural-network dedicated processor for solving competitive assignment problems

NASA Technical Reports Server (NTRS)

Eberhardt, Silvio P. (Inventor)

1993-01-01

A neural-network processor for solving first-order competitive assignment problems consists of a matrix of N x M processing units, each of which corresponds to the pairing of a first number of elements of (R sub i) with a second number of elements (C sub j), wherein limits of the first number are programmed in row control superneurons, and limits of the second number are programmed in column superneurons as MIN and MAX values. The cost (weight) W sub ij of the pairings is programmed separately into each PU. For each row and column of PU's, a dedicated constraint superneuron insures that the number of active neurons within the associated row or column fall within a specified range. Annealing is provided by gradually increasing the PU gain for each row and column or increasing positive feedback to each PU, the latter being effective to increase hysteresis of each PU or by combining both of these techniques.

78 FR 10135 - Fishing Capacity Reduction Program for the Longline Catcher Processor Subsector of the Bering Sea...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-13

... reduction loan to finance the non-pollock groundfish fishing capacity reduction program. DATES: The non... finance reduction program costs. Subpart L of 50 CFR part 600 is the framework rule generally implementing... higher fee rate will be credited to future landings. Fee collection and submission shall follow...

Creative Computer Detective: The Basics of Teaching Desktop Publishing.

ERIC Educational Resources Information Center

Slothower, Jodie

Teaching desktop publishing (dtp) in college journalism classes is most effective when the instructor integrates into specific courses four types of software--a word processor, a draw program, a paint program and a layout program. In a course on design and layout, the instructor can demonstrate with the computer how good design can be created and…

Multiprocessor programming environment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, M.B.; Fornaro, R.

Programming tools and techniques have been well developed for traditional uniprocessor computer systems. The focus of this research project is on the development of a programming environment for a high speed real time heterogeneous multiprocessor system, with special emphasis on languages and compilers. The new tools and techniques will allow a smooth transition for programmers with experience only on single processor systems.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Parallel eigenanalysis of finite element models in a completely connected architecture

NASA Technical Reports Server (NTRS)

Akl, F. A.; Morel, M. R.

1989-01-01

A parallel algorithm is presented for the solution of the generalized eigenproblem in linear elastic finite element analysis, (K)(phi) = (M)(phi)(omega), where (K) and (M) are of order N, and (omega) is order of q. The concurrent solution of the eigenproblem is based on the multifrontal/modified subspace method and is achieved in a completely connected parallel architecture in which each processor is allowed to communicate with all other processors. The algorithm was successfully implemented on a tightly coupled multiple-instruction multiple-data parallel processing machine, Cray X-MP. A finite element model is divided into m domains each of which is assumed to process n elements. Each domain is then assigned to a processor or to a logical processor (task) if the number of domains exceeds the number of physical processors. The macrotasking library routines are used in mapping each domain to a user task. Computational speed-up and efficiency are used to determine the effectiveness of the algorithm. The effect of the number of domains, the number of degrees-of-freedom located along the global fronts and the dimension of the subspace on the performance of the algorithm are investigated. A parallel finite element dynamic analysis program, p-feda, is documented and the performance of its subroutines in parallel environment is analyzed.

RTEMS SMP and MTAPI for Efficient Multi-Core Space Applications on LEON3/LEON4 Processors

NASA Astrophysics Data System (ADS)

Cederman, Daniel; Hellstrom, Daniel; Sherrill, Joel; Bloom, Gedare; Patte, Mathieu; Zulianello, Marco

2015-09-01

This paper presents the final result of an European Space Agency (ESA) activity aimed at improving the software support for LEON processors used in SMP configurations. One of the benefits of using a multicore system in a SMP configuration is that in many instances it is possible to better utilize the available processing resources by load balancing between cores. This however comes with the cost of having to synchronize operations between cores, leading to increased complexity. While in an AMP system one can use multiple instances of operating systems that are only uni-processor capable, a SMP system requires the operating system to be written to support multicore systems. In this activity we have improved and extended the SMP support of the RTEMS real-time operating system and ensured that it fully supports the multicore capable LEON processors. The targeted hardware in the activity has been the GR712RC, a dual-core core LEON3FT processor, and the functional prototype of ESA's Next Generation Multiprocessor (NGMP), a quad core LEON4 processor. The final version of the NGMP is now available as a product under the name GR740. An implementation of the Multicore Task Management API (MTAPI) has been developed as part of this activity to aid in the parallelization of applications for RTEMS SMP. It allows for simplified development of parallel applications using the task-based programming model. An existing space application, the Gaia Video Processing Unit, has been ported to RTEMS SMP using the MTAPI implementation to demonstrate the feasibility and usefulness of multicore processors for space payload software. The activity is funded by ESA under contract 4000108560/13/NL/JK. Gedare Bloom is supported in part by NSF CNS-0934725.

Optimization strategies for molecular dynamics programs on Cray computers and scalar work stations

NASA Astrophysics Data System (ADS)

Unekis, Michael J.; Rice, Betsy M.

1994-12-01

We present results of timing runs and different optimization strategies for a prototype molecular dynamics program that simulates shock waves in a two-dimensional (2-D) model of a reactive energetic solid. The performance of the program may be improved substantially by simple changes to the Fortran or by employing various vendor-supplied compiler optimizations. The optimum strategy varies among the machines used and will vary depending upon the details of the program. The effect of various compiler options and vendor-supplied subroutine calls is demonstrated. Comparison is made between two scalar workstations (IBM RS/6000 Model 370 and Model 530) and several Cray supercomputers (X-MP/48, Y-MP8/128, and C-90/16256). We find that for a scientific application program dominated by sequential, scalar statements, a relatively inexpensive high-end work station such as the IBM RS/60006 RISC series will outperform single processor performance of the Cray X-MP/48 and perform competitively with single processor performance of the Y-MP8/128 and C-9O/16256.

On the Run-Time Optimization of the Boolean Logic of a Program.

ERIC Educational Resources Information Center

Cadolino, C.; Guazzo, M.

1982-01-01

Considers problem of optimal scheduling of Boolean expression (each Boolean variable represents binary outcome of program module) on single-processor system. Optimization discussed consists of finding operand arrangement that minimizes average execution costs representing consumption of resources (elapsed time, main memory, number of…

75 FR 9087 - Trade Adjustment Assistance for Farmers

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-01

... procedures by which producers of raw agricultural commodities can petition for certification, apply for... processors are eligible for program benefits. The purpose of TAA for Farmers is to assist producers of raw... specifically limits program benefits to producers of raw agricultural commodities. Length of Intensive Training...

Upper Grades Ideas.

ERIC Educational Resources Information Center

Classroom Computer Learning, 1984

1984-01-01

Offers suggestions for five computer-oriented classroom activities. They include uniting a writing class by having them collectively write a book using a word processor, examining FOR/NEXT loops, using a compound interest computer program, and developing a list of facts about computers. Includes four short programs which erase monitor screens. (JN)

7 CFR 1160.210 - Expenses.

Code of Federal Regulations, 2010 CFR

2010-01-01

... and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order National Fluid Milk Processor Promotion Board § 1160.210 Expenses. (a) The Board is authorized to incur... funds to the entity authorized by the laws of the State of California to conduct an advertising program...

Evaluation of Sugar Maple Dieback in the Upper Great Lakes Region and Development of a Forest Health Youth Education Program

ERIC Educational Resources Information Center

Bal, Tara L.

2013-01-01

Sugar Maple, "Acer saccharum" Marsh., is one of the most valuable trees in the northern hardwood forests. Severe dieback was recently reported by area foresters in the western Upper Great Lakes Region. Sugar Maple has had a history of dieback over the last 100 years throughout its range and different variables have been identified as…

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

a Real-Time Computer Music Synthesis System

NASA Astrophysics Data System (ADS)

Lent, Keith Henry

A real time sound synthesis system has been developed at the Computer Music Center of The University of Texas at Austin. This system consists of several stand alone processors that were constructed jointly with White Instruments in Austin. These processors can be programmed as general purpose computers, but are provided with a number of specialized interfaces including: MIDI, 8 bit parallel, high speed serial, 2 channels analog input (18 bit A/Ds, 48kHz sample rate), and 4 channels analog output (18 bit D/As). In addition, a basic music synthesis language (Music56000) has been written in assembly code. On top of this, a symbolic compiler (PatchWork) has been developed to enable algorithms which run in these processors to be created graphically. And finally, a number of efficient time domain numerical models have been developed to enable the construction, simulation, control, and synthesis of many musical acoustics systems in real time on these processors. Specifically, assembly language models for cylindrical and conical horn sections, dissipative losses, tone holes, bells, and a number of linear and nonlinear boundary conditions have been developed.

The Application of Logic Programming to Communication Education.

ERIC Educational Resources Information Center

Sanford, David L.

Recommending that communication students be required to learn to use computers not merely as number crunchers, word processors, data bases, and graphics generators, but also as logical inference makers, this paper examines the recently developed technology of logical programing in computer languages. It presents two syllogisms and shows how they…

The RSZ BASIC programming language manual

NASA Technical Reports Server (NTRS)

Stattel, R. J.; Niswander, J. K.; Kochhar, A. K.

1980-01-01

The RSZ BASIC interactive language is described. The RSZ BASIC interpreter is resident in the Telemetry Data Processor, a system dedicated to the processing and displaying of PCM telemetry data. A series of working examples teaches the fundamentals of RSZ BASIC and shows how to construct, edit, and manage storage of programs.

Limited Area Coverage/High Resolution Picture Transmission (LAC/HRPT) tape IJ grid pixel extraction processor user's manual

NASA Technical Reports Server (NTRS)

Obrien, S. O. (Principal Investigator)

1980-01-01

The program, LACREG, extracted all pixels that are contained in a specific IJ grid section. The pixels, along with a header record are stored in a disk file defined by the user. The program will extract up to 99 IJ grid sections.