77 FR 36727 - Endangered and Threatened Wildlife and Plants; Revised Designation of Critical Habitat for the...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-19

...We, the U.S. Fish and Wildlife Service (Service), designate revised critical habitat for the Pacific Coast distinct population segment (DPS) (Pacific Coast WSP) of the western snowy plover (Charadrius nivosus nivosus, formerly C. alexandrinus nivosus) under the Endangered Species Act of 1973, as amended (Act). In total, approximately 24,527 acres (9,926 hectares) of critical habitat for the Pacific Coast WSP in Washington, Oregon, and California, fall within the boundaries of the critical habitat designation. This revised final designation constitutes an increase of approximately 12,377 ac (5,009 ha) from the 2005 designation of critical habitat for the Pacific Coast WSP. A taxonomic name change has occurred and been accepted for the snowy plover. Throughout the remainder of this document, we will use the currently recognized name for the subspecies, Charadrius nivosus nivosus, to which the listed entity (Pacific Coast WSP) belongs for references to the Pacific Coast WSP.

Development of indicators for measuring outcomes of water safety plans

PubMed Central

Lockhart, Gabriella; Oswald, William E.; Hubbard, Brian; Medlin, Elizabeth; Gelting, Richard J.

2015-01-01

Water safety plans (WSPs) are endorsed by the World Health Organization as the most effective method of protecting a water supply. With the increase in WSPs worldwide, several valuable resources have been developed to assist practitioners in the implementation of WSPs, yet there is still a need for a practical and standardized method of evaluating WSP effectiveness. In 2012, the Centers for Disease Control and Prevention (CDC) published a conceptual framework for the evaluation of WSPs, presenting four key outcomes of the WSP process: institutional, operational, financial and policy change. In this paper, we seek to operationalize this conceptual framework by providing a set of simple and practical indicators for assessing WSP outcomes. Using CDC’s WSP framework as a foundation and incorporating various existing performance monitoring indicators for water utilities, we developed a set of approximately 25 indicators of institutional, operational, financial and policy change within the WSP context. These outcome indicators hold great potential for the continued implementation and expansion of WSPs worldwide. Having a defined framework for evaluating a WSP’s effectiveness, along with a set of measurable indicators by which to carry out that evaluation, will help implementers assess key WSP outcomes internally, as well as benchmark their progress against other WSPs in their region and globally. PMID:26361540

Modeling Nitrogen Dynamics in a Waste Stabilization Pond System Using Flexible Modeling Environment with MCMC.

PubMed

Mukhtar, Hussnain; Lin, Yu-Pin; Shipin, Oleg V; Petway, Joy R

2017-07-12

This study presents an approach for obtaining realization sets of parameters for nitrogen removal in a pilot-scale waste stabilization pond (WSP) system. The proposed approach was designed for optimal parameterization, local sensitivity analysis, and global uncertainty analysis of a dynamic simulation model for the WSP by using the R software package Flexible Modeling Environment (R-FME) with the Markov chain Monte Carlo (MCMC) method. Additionally, generalized likelihood uncertainty estimation (GLUE) was integrated into the FME to evaluate the major parameters that affect the simulation outputs in the study WSP. Comprehensive modeling analysis was used to simulate and assess nine parameters and concentrations of ON-N, NH₃-N and NO₃-N. Results indicate that the integrated FME-GLUE-based model, with good Nash-Sutcliffe coefficients (0.53-0.69) and correlation coefficients (0.76-0.83), successfully simulates the concentrations of ON-N, NH₃-N and NO₃-N. Moreover, the Arrhenius constant was the only parameter sensitive to model performances of ON-N and NH₃-N simulations. However, Nitrosomonas growth rate, the denitrification constant, and the maximum growth rate at 20 °C were sensitive to ON-N and NO₃-N simulation, which was measured using global sensitivity.

Change in soluble phosphorus in soils following fertilization is dependent on initial Mehlich-3 phosphorus.

PubMed

Bond, C Ryan; Maguire, R O; Havlin, J L

2006-01-01

There is a lack of information on how fertilization and initial Mehlich-3 phosphorus (M3P) interact to affect water soluble P (WSP) in soils. Our objectives were to (i) quantify the relationship between WSP and M3P for four textural diverse benchmark soils of North Carolina (NC) and (ii) quantify the change in WSP concentrations following P additions to soils over a wide range of initial M3P. Soils known to represent a wide range in M3P were collected from an Autryville loamy sand (loamy, siliceous, subactive, thermic Arenic Paleudults), Wasda muck (fine-loamy, mixed, semiactive, acid, thermic Histic Humaquepts), Georgeville silt loam (fine, kaolinitic, thermic Typic Kanhapludults), and Pacolet sandy clay loam (fine, kaolinitic, thermic Typic Kanhapludults) and analyzed for M3P, Fe, Al, and WSP. An incubation study was also conducted where four samples representing a range in M3P from each series were fertilized at rates of 150 and 300 kg P ha(-1), and WSP was measured at 1, 7, and 21 d after fertilization. The Wasda muck exhibited a change point at 115 mg P kg(-1) across a broad range of M3P concentrations (60-238 mg kg(-1)) while Autryville, Georgeville, and Pacolet series (with ranges in M3P of 32-328, 119-524, 0-1034 mg P kg(-1), respectively) maintained linear relationships between WSP and M3P. For the fertilized soils, significant increases in WSP occurred regardless of P rate. Yet, WSP concentrations were greater in soils with greater initial M3P. Thus, these data suggest that shifting animal waste applications to fields of relatively lower M3P concentrations would have an immediate impact on reducing risk for P losses, if all other factors are equal.

Performance evaluation of 388 full-scale waste stabilization pond systems with seven different configurations.

PubMed

Espinosa, Maria Fernanda; von Sperling, Marcos; Verbyla, Matthew E

2017-02-01

Waste stabilization ponds (WSPs) and their variants are one the most widely used wastewater treatment systems in the world. However, the scarcity of systematic performance data from full-scale plants has led to challenges associated with their design. The objective of this research was to assess the performance of 388 full-scale WSP systems located in Brazil, Ecuador, Bolivia and the United States through the statistical analysis of available monitoring data. Descriptive statistics were calculated of the influent and effluent concentrations and the removal efficiencies for 5-day biochemical oxygen demand (BOD 5 ), total suspended solids (TSS), ammonia nitrogen (N-Ammonia), and either thermotolerant coliforms (TTC) or Escherichia coli for each WSP system, leading to a broad characterization of actual treatment performance. Compliance with different water quality and system performance goals was also evaluated. The treatment plants were subdivided into seven different categories, according to their units and flowsheet. The median influent concentrations of BOD 5 and TSS were 431 mg/L and 397 mg/L and the effluent concentrations varied from technology to technology, but median values were 50 mg/L and 47 mg/L, respectively. The median removal efficiencies were 85% for BOD 5 and 75% for TSS. The overall removals of TTC and E. coli were 1.74 and 1.63 log 10 units, respectively. Future research is needed to better understand the influence of design, operational and environmental factors on WSP system performance.

Rainfall intensity and phosphorus source effects on phosphorus transport in surface runoff from soil trays.

PubMed

Shigaki, Francirose; Sharpley, Andrew; Prochnow, Luis Ignacio

2007-02-01

Phosphorus runoff from agricultural fields amended with mineral fertilizers and manures has been linked to freshwater eutrophication. A rainfall simulation study was conducted to evaluate the effects of different rainfall intensities and P sources differing in water soluble P (WSP) concentration on P transport in runoff from soil trays packed with a Berks loam and grassed with annual ryegrass (Lolium multiflorum Lam.). Triple superphosphate (TSP; 79% WSP), low-grade super single phosphate (LGSSP; 50% WSP), North Carolina rock phosphate (NCRP; 0.5% WSP) and swine manure (SM; 70% WSP), were broadcast (100 kg total P ha-1) and rainfall applied at 25, 50 and 75 mm h-1 1, 7, 21, and 56 days after P source application. The concentration of dissolved reactive (DRP), particulate (PP), and total P (TP) was significantly (P<0.01) greater in runoff with a rainfall intensity of 75 than 25 mm h-1 for all P sources. Further, runoff DRP increased as P source WSP increased, with runoff from a 50 mm h-1 rain 1 day after source application having a DRP concentration of 0.25 mg L-1 for NCRP and 28.21 mg L-1 for TSP. In contrast, the proportion of runoff TP as PP was greater with low (39% PP for NCRP) than high WSP sources (4% PP for TSP) averaged for all rainfall intensities. The increased PP transport is attributed to the detachment and transport of undissolved P source particles during runoff. These results show that P source water solubility and rainfall intensity can influence P transport in runoff, which is important in evaluating the long-term risks of P source application on P transport in surface runoff.

Anti-Inflammatory Activity of Water-Soluble Polysaccharide of Agaricus blazei Murill on Ovariectomized Osteopenic Rats

PubMed Central

Wang, Peng; Li, Xiao-Tao; Sun, Lei; Shen, Lei

2013-01-01

In the present study, we investigated the anti-inflammatory activity of water-soluble polysaccharide of Agaricus blazei Murill (WSP-AbM) on ovariectomized osteopenic rats. The rats were administered orally WSP-AbM (200 mg/kg BW) for 8 weeks. Subsequent serum maleic dialdehyde (MDA) level, total antioxidant status (TAOS), nuclear factor kappa B (NF-κB) level, polymorphonuclear (PMN) cells level, interleukin-1β (IL-1β) level, inducible nitric oxide synthase (iNOS) level, tumor necrosis factor-α (TNF-α) level, adhesion molecule (ICAM-1), and cyclooxygenase-2 (COX-2) were determined by enzyme linked immunosorbent assay (ELISA) and immunohistochemistry, respectively. WSP-AbM administration markedly (P < 0.05) decreased serum IL-1β and TNF-α levels and the expressions of ICAM-1, COX-2, and iNOS NF-κB compared with OVX rats. WSP-AbM administration alsomarkedly (P < 0.05) decreased PMN infiltration. In conclusion, we observed that WSP-AbM supplementation had anti-inflammatory effects in a model of osteoporosis disease. PMID:24348690

Pectin from Opuntia ficus indica: Optimization of microwave-assisted extraction and preliminary characterization.

PubMed

Lefsih, Khalef; Giacomazza, Daniela; Dahmoune, Farid; Mangione, Maria Rosalia; Bulone, Donatella; San Biagio, Pier Luigi; Passantino, Rosa; Costa, Maria Assunta; Guarrasi, Valeria; Madani, Khodir

2017-04-15

Optimization of microwave-assisted extraction (MAE) of water-soluble pectin (WSP) from Opuntia ficus indica cladodes was performed using Response Surface Methodology. The effect of extraction time (X 1 ), microwave power (X 2 ), pH (X 3 ) and solid-to-liquid ratio (X 4 ) on the extraction yield was examined. The optimum conditions of MAE were as follows: X 1 =2.15min; X 2 =517W; X 3 =2.26 and X 4 =2g/30.6mL. The maximum obtained yield of pectin extraction was 12.57%. Total carbohydrate content of WSP is about 95.5% including 34.4% of Galacturonic acid. Pectin-related proteins represent only the 0.66% of WSP mass. HPSEC and light scattering analyses reveal that WSP is mostly constituted of high molecular pectin and FTIR measurements show that the microwave treatment does not alter the chemical structure of WSP, in which Galacturonic acid content and yield are 34.4% and 4.33%, respectively. Overall, application of MAE can give rise to high quality pectin. Copyright © 2016 Elsevier Ltd. All rights reserved.

Modeling Nitrogen Dynamics in a Waste Stabilization Pond System Using Flexible Modeling Environment with MCMC

PubMed Central

Mukhtar, Hussnain; Lin, Yu-Pin; Shipin, Oleg V.; Petway, Joy R.

2017-01-01

This study presents an approach for obtaining realization sets of parameters for nitrogen removal in a pilot-scale waste stabilization pond (WSP) system. The proposed approach was designed for optimal parameterization, local sensitivity analysis, and global uncertainty analysis of a dynamic simulation model for the WSP by using the R software package Flexible Modeling Environment (R-FME) with the Markov chain Monte Carlo (MCMC) method. Additionally, generalized likelihood uncertainty estimation (GLUE) was integrated into the FME to evaluate the major parameters that affect the simulation outputs in the study WSP. Comprehensive modeling analysis was used to simulate and assess nine parameters and concentrations of ON-N, NH3-N and NO3-N. Results indicate that the integrated FME-GLUE-based model, with good Nash–Sutcliffe coefficients (0.53–0.69) and correlation coefficients (0.76–0.83), successfully simulates the concentrations of ON-N, NH3-N and NO3-N. Moreover, the Arrhenius constant was the only parameter sensitive to model performances of ON-N and NH3-N simulations. However, Nitrosomonas growth rate, the denitrification constant, and the maximum growth rate at 20 °C were sensitive to ON-N and NO3-N simulation, which was measured using global sensitivity. PMID:28704958

Construction Guide to Next-Generation High-Performance Walls in Climate Zones 3-5 - Part 2: 2x4 Walls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kochkin, V.; Wiehagen, J.

2017-06-01

Part 2 of this Construction Guide to High-Performance Walls in Climate Zones 3-5 provides straightforward and cost-effective strategies to construct durable, energy-efficient walls. It addresses walls constructed with 2x4 wood frame studs, wood structural panel (WSP) sheathing as wall bracing and added backing for foam sheathing, a layer of rigid foam sheathing insulation up to 1.5 inches thick over the WSP, and a cladding system installed over the foam sheathing in low-rise residential buildings up to three stories high. Walls with 2x6 framing are addressed in Part 1 of the Guide.

Construction Guide to Next-Generation High-Performance Walls in Climate Zones 3-5 - Part 2: 2x4 Walls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kochkin, V.; Wiehagen, J.

Part 2 of this Construction Guide to High-Performance Walls in Climate Zones 3-5 provides straightforward and cost-effective strategies to construct durable, energy-efficient walls. It addresses walls constructed with 2x4 wood frame studs, wood structural panel (WSP) sheathing as wall bracing and added backing for foam sheathing, a layer of rigid foam sheathing insulation up to 1.5 inches thick over the WSP, and a cladding system installed over the foam sheathing in low-rise residential buildings up to three stories high. Walls with 2x6 framing are addressed in Part 1 of the Guide.

Candida albicans ethanol stimulates Pseudomonas aeruginosa WspR-controlled biofilm formation as part of a cyclic relationship involving phenazines.

PubMed

Chen, Annie I; Dolben, Emily F; Okegbe, Chinweike; Harty, Colleen E; Golub, Yuriy; Thao, Sandy; Ha, Dae Gon; Willger, Sven D; O'Toole, George A; Harwood, Caroline S; Dietrich, Lars E P; Hogan, Deborah A

2014-10-01

In chronic infections, pathogens are often in the presence of other microbial species. For example, Pseudomonas aeruginosa is a common and detrimental lung pathogen in individuals with cystic fibrosis (CF) and co-infections with Candida albicans are common. Here, we show that P. aeruginosa biofilm formation and phenazine production were strongly influenced by ethanol produced by the fungus C. albicans. Ethanol stimulated phenotypes that are indicative of increased levels of cyclic-di-GMP (c-di-GMP), and levels of c-di-GMP were 2-fold higher in the presence of ethanol. Through a genetic screen, we found that the diguanylate cyclase WspR was required for ethanol stimulation of c-di-GMP. Multiple lines of evidence indicate that ethanol stimulates WspR signaling through its cognate sensor WspA, and promotes WspR-dependent activation of Pel exopolysaccharide production, which contributes to biofilm maturation. We also found that ethanol stimulation of WspR promoted P. aeruginosa colonization of CF airway epithelial cells. P. aeruginosa production of phenazines occurs both in the CF lung and in culture, and phenazines enhance ethanol production by C. albicans. Using a C. albicans adh1/adh1 mutant with decreased ethanol production, we found that fungal ethanol strongly altered the spectrum of P. aeruginosa phenazines in favor of those that are most effective against fungi. Thus, a feedback cycle comprised of ethanol and phenazines drives this polymicrobial interaction, and these relationships may provide insight into why co-infection with both P. aeruginosa and C. albicans has been associated with worse outcomes in cystic fibrosis.

Exposure to wood smoke particles produces an inflammation in healthy volunteers

EPA Science Inventory

Background. Human exposure to wood smoke particles (WSP) is of consequence in indoor air quality, exposures from wild fires, burning ofbiomass, and air pollution. This investigation tested the postulate that healthy volunteers exposed to WSP would demonstrate pulmonary and cardio...

Sex Differences in Acute Ethanol Withdrawal Severity After Adrenalectomy and Gonadectomy in WSP and WSR Mice

PubMed Central

Strong, Moriah N.; Kaufman, Katherine R.; Crabbe, John C.; Finn, Deborah A.

2009-01-01

Recent findings suggest that the ability of ethanol (EtOH) to increase the levels of neurosteroids with potent γ-aminobutyric acid (GABA)ergic properties can influence measures of EtOH sensitivity. Earlier studies determined that removal of the adrenals and gonads diminished the steroidogenic effect of EtOH and significantly increased acute EtOH withdrawal severity in two inbred mouse strains that differed in withdrawal severity, suggesting the contribution of anticonvulsant GABAergic steroids to acute withdrawal in intact animals. Thus, the goal of the present studies was to investigate the consequence of steroid removal on acute EtOH withdrawal through excision of the adrenals and gonads, in another genetic animal model of EtOH withdrawal differences, the Withdrawal Seizure-Prone (WSP) and -Resistant (WSR) selected lines. Male and female WSP and WSR mice underwent surgical removal of the adrenals and gonads or no organ removal (SHAM). One to two weeks later, baseline handling-induced convulsions (HICs) were assessed, mice were given a 4 g/kg dose of ethanol, and HICs were measured hourly for 12 hours and then at 24 hours. The combination surgery significantly increased EtOH withdrawal in WSP and WSR female mice, as measured by area under the curve (AUC) and peak HIC scores. AUC was significantly positively correlated with plasma corticosterone levels and significantly negatively correlated with progesterone levels. In contrast, surgical status did not alter withdrawal severity in male WSP and WSR mice. Overall, the increase in acute ethanol withdrawal severity in female WSP and WSR mice following adrenalectomy and gonadectomy corroborate our recent evidence that withdrawal from a high dose of EtOH can be modulated by anticonvulsant steroids produced in the periphery. PMID:19671463

Candida albicans Ethanol Stimulates Pseudomonas aeruginosa WspR-Controlled Biofilm Formation as Part of a Cyclic Relationship Involving Phenazines

PubMed Central

Okegbe, Chinweike; Harty, Colleen E.; Golub, Yuriy; Thao, Sandy; Ha, Dae Gon; Willger, Sven D.; O'Toole, George A.; Harwood, Caroline S.; Dietrich, Lars E. P.; Hogan, Deborah A.

2014-01-01

In chronic infections, pathogens are often in the presence of other microbial species. For example, Pseudomonas aeruginosa is a common and detrimental lung pathogen in individuals with cystic fibrosis (CF) and co-infections with Candida albicans are common. Here, we show that P. aeruginosa biofilm formation and phenazine production were strongly influenced by ethanol produced by the fungus C. albicans. Ethanol stimulated phenotypes that are indicative of increased levels of cyclic-di-GMP (c-di-GMP), and levels of c-di-GMP were 2-fold higher in the presence of ethanol. Through a genetic screen, we found that the diguanylate cyclase WspR was required for ethanol stimulation of c-di-GMP. Multiple lines of evidence indicate that ethanol stimulates WspR signaling through its cognate sensor WspA, and promotes WspR-dependent activation of Pel exopolysaccharide production, which contributes to biofilm maturation. We also found that ethanol stimulation of WspR promoted P. aeruginosa colonization of CF airway epithelial cells. P. aeruginosa production of phenazines occurs both in the CF lung and in culture, and phenazines enhance ethanol production by C. albicans. Using a C. albicans adh1/adh1 mutant with decreased ethanol production, we found that fungal ethanol strongly altered the spectrum of P. aeruginosa phenazines in favor of those that are most effective against fungi. Thus, a feedback cycle comprised of ethanol and phenazines drives this polymicrobial interaction, and these relationships may provide insight into why co-infection with both P. aeruginosa and C. albicans has been associated with worse outcomes in cystic fibrosis. PMID:25340349

Effect of water content on thermal behavior of freeze-dried soy whey and their isolated proteins.

PubMed

Sobral, Pablo A; Palazolo, Gonzalo G; Wagner, Jorge R

2011-04-27

Thermal behavior of lyophilized soy whey (LSW) and whey soy proteins (WSP) at different water contents (WC) was studied by DSC. In anhydrous condition, Kunitz trypsin inhibitor (KTI) and lectin (L) were more heat stable for WSP with respect to LSW sample. The increase of WC destabilized both proteins but differently depending on the sample analyzed. Thermal stability inversion of KTI and L was observed for WSP and LSW at 50.0% and 17.0% WC, respectively, which correspond to the same water-protein content mass ratio (W/P ≈ 1.9). At W/P < 1.9, KTI was more heat stable than L. Before the inversion point, WC strongly modified the peak temperatures (T(p)) of KTI and L for WSP, whereas this behavior was not observed for LSW. The high sugar content was responsible for the thermal behavior of KTI and L in LSW under anhydrous condition and low WC. These results have important implications for the soy whey processing and inactivation of antinutritional factors.

A universal method to assess the potential of phosphorus loss from soil to aquatic ecosystems.

PubMed

Pöthig, Rosemarie; Behrendt, Horst; Opitz, Dieter; Furrer, Gerhard

2010-02-01

Phosphorus loss from terrestrial to the aquatic ecosystems contributes to eutrophication of surface waters. To maintain the world's vital freshwater ecosystems, the reduction of eutrophication is crucial. This needs the prevention of overfertilization of agricultural soils with phosphorus. However, the methods of risk assessment for the P loss potential from soils lack uniformity and are difficult for routine analysis. Therefore, the efficient detection of areas with a high risk of P loss requires a simple and universal soil test method that is cost effective and applicable in both industrialized and developing countries. Soils from areas which varied highly in land use and soil type were investigated regarding the degree of P saturation (DPS) as well as the equilibrium P concentration (EPC(0)) and water-soluble P (WSP) as indicators for the potential of P loss. The parameters DPS and EPC(0) were determined from P sorption isotherms. Our investigation of more than 400 soil samples revealed coherent relationships between DPS and EPC(0) as well as WSP. The complex parameter DPS, characterizing the actual P status of soil, is accessible from a simple standard measurement of WSP based on the equation [Formula: see text]. The parameter WSP in this equation is a function of remaining phosphorous sorption capacity/total accumulated phosphorous (SP/TP). This quotient is independent of soil type due to the mutual compensation of the factors SP and TP. Thus, the relationship between DPS and WSP is also independent of soil type. The degree of P saturation, which reflects the actual state of P fertilization of soil, can be calculated from the easily accessible parameter WSP. Due to the independence from soil type and land use, the relation is valid for all soils. Values of WSP, which exceed 5 mg P/kg soil, signalize a P saturation between 70% and 80% and thus a high risk of P loss from soil. These results reveal a new approach of risk assessment for P loss from soils to surface and ground waters. The consequent application of this method may globally help to save the vital resources of our terrestrial and aquatic ecosystems.

A review of the sustainable value and disposal techniques, wastewater stabilisation ponds sludge characteristics and accumulation.

PubMed

Keffala, Chéma; Harerimana, Casimir; Vasel, Jean-luc

2013-01-01

Based on worldwide works available in international literature, this paper describes the status of sewage sludge resulting from settleable solids in waste stabilisation ponds (WSP). This review presents, in detail, sludge characteristics, production and accumulation rates in order to provide background information to those who expect to advise or get involved with sewage disposal in situations where resources are limited. Knowing that several years are usually required for a sludge removal operation and that the long-term sustainability of WSP systems is dependent on the safe and effective management of their sludge, its cost must be estimated and taken into account in the annual maintenance costs of the processes. Thus, this paper intends to summarise desludging methods and their financial estimation. Even when ponds have been functioning for several years, most of the sediments are stabilised well, the final disposal is an issue in terms of risk due, for example, to their content in nematode eggs. More generally, the pathogen content in sludge from WSP ponds has to be known to define an appropriate management and to safeguard public health. Based on existing data, the rates and distribution of helminth eggs will be presented and practical treatment methods will be suggested. A number of sludge utilisation and disposal pathways will also be summarised. Sludge activity in terms of oxygen consumption is also discussed in order to gather more information to improve pond design and keep an economic and sustainable value of WSP. The objectives of the present review are to advance knowledge and gather scientific and technical information on all aspects of sludge management including production, characterisation, management, agricultural reuse and ultimate disposal.

Serine Hydroxymethyltransferase ShrA (PA2444) Controls Rugose Small-Colony Variant Formation in Pseudomonas aeruginosa

PubMed Central

Pu, Mingming; Sheng, Lili; Song, Sooyeon; Gong, Ting; Wood, Thomas K.

2018-01-01

Pseudomonas aeruginosa causes many biofilm infections, and the rugose small-colony variants (RSCVs) of this bacterium are important for infection. We found here that inactivation of PA2444, which we determined to be a serine hydroxymethyltransferase (SHMT), leads to the RSCV phenotype of P. aeruginosa PA14. In addition, loss of PA2444 increases biofilm formation by two orders of magnitude, increases exopolysaccharide by 45-fold, and abolishes swarming. The RSCV phenotype is related to higher cyclic diguanylate concentrations due to increased activity of the Wsp chemosensory system, including diguanylate cyclase WspR. By characterizing the PA2444 enzyme in vitro, we determined the physiological function of PA2444 protein by relating it to S-adenosylmethionine (SAM) concentrations and methylation of a membrane bound methyl-accepting chemotaxis protein WspA. A whole transcriptome analysis also revealed PA2444 is related to the redox state of the cells, and the altered redox state was demonstrated by an increase in the intracellular NADH/NAD+ ratio. Hence, we provide a mechanism for how an enzyme of central metabolism controls the community behavior of the bacterium, and suggest the PA2444 protein should be named ShrA for serine hydroxymethyltransferase related to rugose colony formation. PMID:29535691

Effects of acute alcohol withdrawal on nest building in mice selectively bred for alcohol withdrawal severity

PubMed Central

Greenberg, Gian D.; Phillips, Tamara J.; Crabbe, John C.

2017-01-01

Nest building has been used to assess thermoregulatory behavior and positive motivational states in mice. There are known genetic influences on ethanol withdrawal severity as well as individual/thermoregulatory nest building. Withdrawal Seizure-Prone (WSP-1, WSP-2) and Withdrawal Seizure-Resistant (WSR-1, WSR-2) mice were selectively bred for high vs low handling-induced convulsion (HIC) severity, respectively, during withdrawal from chronic ethanol vapor inhalation. They also differ in HIC severity during withdrawal from an acute, 4 g/kg ethanol injection. In our initial study, withdrawal from an acute dose of ethanol dose-dependently impaired nest building over the initial 24 h of withdrawal in genetically segregating Withdrawal Seizure Control (WSC) mice. In two further studies, acute ethanol withdrawal suppressed nest building for up to two days in WSP-1 females. Deficits in nest building from ethanol were limited to the initial 10 h of withdrawal in WSR-1 females and to the initial 24 h of withdrawal in WSP-1 and WSR-1 males. Effects of ethanol on nest building for up to two days were found in WSP-2 and WSR-2 mice of both sexes. Nest building deficits in female mice from the first replicate could not be explained by a general decrease in locomotor behavior. These results suggest that nest building is a novel behavioral phenotype for indexing the severity of acute ethanol withdrawal, and that genes contributing to this trait differ from those affecting acute withdrawal HIC severity. PMID:27503811

Operational Evaluation Of Vectomax® WSP (Bacillus thuringiensis Subsp. israelensis+Bacillus sphaericus) Against Larval Culex pipiens in Septic Tanks (1).

PubMed

Cetin, Huseyin; Oz, Emre; Yanikoglu, Atila; Cilek, James E

2015-06-01

The residual effectiveness of VectoMax® WSP (a water-soluble pouch formulation containing a combination of Bacillus thuringiensis subsp. israelensis strain AM65-52 and B. sphaericus strain ABTS 1743) when applied to septic tanks against 3rd- and 4th-stage larvae of Culex pipiens L. was evaluated in this study. This formulation was evaluated at operational application rates of 1 pouch (10 g) and 2 pouches (20 g) per septic tank. Both application rates resulted in >96% control of larvae for 24 days. Operationally, VectoMax WSP has proven to be a useful tool for the nonchemical control of Culex species in septic tank environments.

Effects of acute alcohol withdrawal on nest building in mice selectively bred for alcohol withdrawal severity.

PubMed

Greenberg, Gian D; Phillips, Tamara J; Crabbe, John C

2016-10-15

Nest building has been used to assess thermoregulatory behavior and positive motivational states in mice. There are known genetic influences on ethanol withdrawal severity as well as individual/thermoregulatory nest building. Withdrawal Seizure-Prone (WSP-1, WSP-2) and Withdrawal Seizure-Resistant (WSR-1, WSR-2) mice were selectively bred for high vs low handling-induced convulsion (HIC) severity, respectively, during withdrawal from chronic ethanol vapor inhalation. They also differ in HIC severity during withdrawal from an acute, 4g/kg ethanol injection. In our initial study, withdrawal from an acute dose of ethanol dose-dependently impaired nest building over the initial 24h of withdrawal in genetically segregating Withdrawal Seizure Control (WSC) mice. In two further studies, acute ethanol withdrawal suppressed nest building for up to two days in WSP-1 females. Deficits in nest building from ethanol were limited to the initial 10h of withdrawal in WSR-1 females and to the initial 24h of withdrawal in WSP-1 and WSR-1 males. Effects of ethanol on nest building for up to two days were found in WSP-2 and WSR-2 mice of both sexes. Nest building deficits in female mice from the first replicate could not be explained by a general decrease in locomotor behavior. These results suggest that nest building is a novel behavioral phenotype for indexing the severity of acute ethanol withdrawal, and that genes contributing to this trait differ from those affecting acute withdrawal HIC severity. Published by Elsevier Inc.

Wolbachia in guilds of Anastrepha fruit flies (Tephritidae) and parasitoid wasps (Braconidae)

PubMed Central

Mascarenhas, Rodrigo O; Prezotto, Leandro F; Perondini, André Luiz P; Marino, Celso Luiz; Selivon, Denise

2016-01-01

Abstract The endosymbiont Wolbachia is efficiently transmitted from females to their progenies, but horizontal transmission between different taxa is also known to occur. Aiming to determine if horizontal transmission might have occurred between Anastrepha fruit flies and associated braconid wasps, infection by Wolbachia was screened by amplification of a fragment of the wsp gene. Eight species of the genus Anastrepha were analyzed, from which six species of associated parasitoid wasps were recovered. The endosymbiont was found in seven Anastrepha species and in five species of braconids. The WSP Typing methodology detected eight wsp alleles belonging to Wolbachia supergroup A. Three were already known and five were new ones, among which four were found to be putative recombinant haplotypes. Two samples of Anastrepha obliqua and one sample of Doryctobracon brasiliensis showed multiple infection. Single infection by Wolbachia was found in the majority of samples. The distribution of Wolbachia harboring distinct alleles differed significantly between fruit flies and wasps. However, in nine samples of fruit flies and associated wasps, Wolbachia harbored the same wsp allele. These congruences suggest that horizontal transfer of Wolbachia might have occurred in the communities of fruit flies and their braconid parasitoids. PMID:27648768

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elicio, Andy U.

My ERM 593 applied project will provide guidance for the Los Alamos National Laboratory Waste Stream Profile reviewer (i.e. RCRA reviewer) in regards to Reviewing and Approving a Waste Stream Profile in the Waste Compliance and Tracking System. The Waste Compliance and Tracking system is called WCATS. WCATS is a web-based application that “supports the generation, characterization, processing and shipment of LANL radioactive, hazardous, and industrial waste.” The LANL generator must characterize their waste via electronically by filling out a waste stream profile (WSP) in WCATS. Once this process is completed, the designated waste management coordinator (WMC) will perform amore » review of the waste stream profile to ensure the generator has completed their waste stream characterization in accordance with applicable state, federal and LANL directives particularly P930-1, “LANL Waste Acceptance Criteria,” and the “Waste Compliance and Tracking System User's Manual, MAN-5004, R2,” as applicable. My guidance/applied project will describe the purpose, scope, acronyms, definitions, responsibilities, assumptions and guidance for the WSP reviewer as it pertains to each panel and subpanel of a waste stream profile.« less

Liming Poultry Manures to Kill Pathogens and Decrease Soluble Phosphorus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire,R.; Hesterberg, D.; Gernat, A.

2006-01-01

Received for publication September 9, 2005. Stabilizing phosphorus (P) in poultry waste to reduce P losses from manured soils is important to protect surface waters, while pathogens in manures are an emerging issue. This study was conducted to evaluate CaO and Ca(OH){sub 2} for killing manure bacterial populations (pathogens) and stabilizing P in poultry wastes and to investigate the influence on soils following amendment with the treated wastes. Layer manure and broiler litter varying in moisture content were treated with CaO and Ca(OH){sub 2} at rates of 2.5, 5, 10, and 15% by weight. All treated wastes were analyzed formore » microbial plate counts, pH, and water-soluble phosphorus (WSP), while a few selected layer manures were analyzed by phosphorus X-ray absorption near edge structure (XANES). A loamy sand and a silt loam were amended with broiler litter and layer manure treated with CaO at rates of 0, 2.5, 5, 10, and 15% and soil WSP and pH were measured at times 1, 8, and 29 d. Liming reduced bacterial populations, with greater rates of lime leading to greater reductions; for example 10% CaO applied to 20% solids broiler litter reduced the plate counts from 793 000 to 6500 mL{sup -1}. Liming also reduced the WSP in the manures by over 90% in all cases where at least 10% CaO was added. Liming the manures also reduced WSP in soils immediately following application and raised soil pH. The liming process used successfully reduced plate counts and concerns about P losses in runoff following land application of these limed products due to decreased WSP.« less

Liming poultry manures to decrease soluble phosphorus and suppress the bacteria population.

PubMed

Maguire, R O; Hesterberg, D; Gernat, A; Anderson, K; Wineland, M; Grimes, J

2006-01-01

Stabilizing phosphorus (P) in poultry waste to reduce P losses from manured soils is important to protect surface waters, while pathogens in manures are an emerging issue. This study was conducted to evaluate CaO and Ca(OH)2 for killing manure bacterial populations (pathogens) and stabilizing P in poultry wastes and to investigate the influence on soils following amendment with the treated wastes. Layer manure and broiler litter varying in moisture content were treated with CaO and Ca(OH)2 at rates of 2.5, 5, 10, and 15% by weight. All treated wastes were analyzed for microbial plate counts, pH, and water-soluble phosphorus (WSP), while a few selected layer manures were analyzed by phosphorus X-ray absorption near edge structure (XANES). A loamy sand and a silt loam were amended with broiler litter and layer manure treated with CaO at rates of 0, 2.5, 5, 10, and 15% and soil WSP and pH were measured at times 1, 8, and 29 d. Liming reduced bacterial populations, with greater rates of lime leading to greater reductions; for example 10% CaO applied to 20% solids broiler litter reduced the plate counts from 793,000 to 6500 mL-1. Liming also reduced the WSP in the manures by over 90% in all cases where at least 10% CaO was added. Liming the manures also reduced WSP in soils immediately following application and raised soil pH. The liming process used successfully reduced plate counts and concerns about P losses in runoff following land application of these limed products due to decreased WSP.

Optical fixing the positions of the off-shore objects applying the method of two reference points

NASA Astrophysics Data System (ADS)

Naus, Krzysztof; Szulc, Dariusz

2014-06-01

The Paper presents the optical method of fixing the off-shore objects positions from the land. The method is based on application of two reference points, having the geographical coordinates defined. The first point was situated high on the sea shore, where also the camera was installed. The second point was intended for use to determine the topocentric horizon plane and it was situated at the water-level. The first section of the Paper contains the definition of space and disposed therein reference systems: connected with the Earth, water-level and the camera system. The second section of the Paper provides a description of the survey system model and the principles of the Charge Coupled Device - CCD array pixel's coordinates (plate coordinates) transformation into the geographic coordinates located on the water-level. In the final section there are presented the general rules of using the worked out method in the optical system. W artykule przedstawiono optyczną metodę wyznaczania pozycji obiektów nawodnych z lądu. Oparto ją na dwóch punktach odniesienia o znanych współrzędnych geograficznych. Pierwszy umiejscowiono wysoko na brzegu morza i przeznaczono do zamontowania kamery. Drugi przeznaczono do określania płaszczyzny horyzontu topocentrycznego i umiejscowiono na poziomie lustra wody. W pierwszej części artykułu zdefi niowano przestrzeń i rozmieszczone w niej układy odniesienia: związany z Ziemią, poziomem lustra wody i kamerą. Drugą część artykułu stanowi opis modelu układu pomiarowego oraz zasad transformacji współrzędnych piksela (tłowych) z matrycy CCD na współrzędne geograficzne punktu umiejscowionego na poziomie lustra wody. W części końcowej zaprezentowano ogólne zasady wykorzystywania opracowanej metody w systemie optycznym.

Detection and Phylogenetic Analysis of Wolbachia in the Asiatic Rice Leafroller, Cnaphalocrocis medinalis, in Chinese Populations

PubMed Central

Chai, Huan-Na; Du, Yu-Zhou; Qiu, Bao-Li; Zhai, Bao-Ping

2011-01-01

Wolbachia are a group of intracellular inherited endosymbiontic bacteria infecting a wide range of insects. In this study the infection status of Wolbachia (Rickettsiales: Rickettsiaceae) was measured in the Asiatic rice leafroller, Cnaphalocrocis medinalis (Guenée) (Lepidoptera: Pyralidae), from twenty locations in China by sequencing wsp, ftsZ and 16S rDNA genes. The results showed high infection rates of Wolbachia in C. medinalis populations. Wolbachia was detected in all geographically separate populations; the average infection rate was ∼ 62.5%, and the highest rates were 90% in Wenzhou and Yangzhou populations. The Wolbachia detected in different C. medinalis populations were 100% identical to each other when wsp, ftsZ, and 16S rDNA sequences were compared, with all sequences belonging to the Wolbachia B supergroup. Based on wsp, ftsZ and 16S rDNA sequences of Wolbachia, three phylogenetic trees of similar pattern emerged. This analysis indicated the possibility of inter-species and intra-species horizontal transmission of Wolbachia in different arthropods in related geographical regions. The migration route of C. medinalis in mainland China was also discussed since large differentiation had been found between the wsp sequences of Chinese and Thai populations. PMID:22233324

Effect of Thiobacillus, sulfur, and vermicompost on the water-soluble phosphorus of hard rock phosphate.

PubMed

Aria, Marzieh Mohammady; Lakzian, Amir; Haghnia, Gholam Hosain; Berenji, Ali Reza; Besharati, Hosein; Fotovat, Amir

2010-01-01

Sulfur, organic matter, and inoculation with sulfur-oxidizing bacteria are considered as amendments to increase the availability of phosphorus from rock phosphate. The present study was conducted to evaluate the best combination of sulfur, vermicompost, and Thiobacillus thiooxidans inoculation with rock phosphate from Yazd province for direct application to agricultural lands in Iran. For such study, an experiment was carried out in a completely randomized design with factorial arrangement: Elemental sulfur originated from Sarakhs mine at three rates, 0% (S1), 10% (S2), 20% (S3), vermicompost at two rates, 0% (V1), 15% (V2), and inoculation without (B1) and with (B2) T. thiooxidans, in three replications. The results showed that water-soluble phosphorus (WSP) content was significantly higher in inoculated treatments compared to non-inoculated treatments. Sulfur had a significant effect on WSP. The highest solubility rate of rock phosphate was obtained in 20% of sulfur (S3) treatments and it was 2.4 times more than S1 treatments. Vermicompost also had a significant and positive effect on WSP of rock phosphate dissolution. The results also revealed that the highest concentration of WSP, sulfate and the lowest pH were obtained in treatments with 20% sulfur, 15% vermicompost inoculated with T. thiooxidans (B2S3V2).

The effects of temperature on decomposition and allelopathic phytotoxicity of boneseed litter.

PubMed

Al Harun, Md Abdullah Yousuf; Johnson, Joshua; Uddin, Md Nazim; Robinson, Randall W

2015-07-01

Decomposition of plant litter is a fundamental process in ecosystem function, carbon and nutrient cycling and, by extension, climate change. This study aimed to investigate the role of temperature on the decomposition of water soluble phenolics (WSP), carbon and soil nutrients in conjunction with the phytotoxicity dynamics of Chrysanthemoides monilifera subsp. monilifera (boneseed) litter. Treatments consisted of three factors including decomposition materials (litter alone, litter with soil and soil alone), decomposition periods and temperatures (5-15, 15-25 and 25-35°C (night/day)). Leachates were collected on 0, 5, 10, 20, 40 and 60th days to analyse physico-chemical parameters and phytotoxicity. Water soluble phenolics and dissolved organic carbon (DOC) increased with increasing temperature while nutrients like SO4(-2) and NO3(-1) decreased. Speed of germination, hypocotyl and radical length and weight of Lactuca sativa exposed to leachates were decreased with increasing decomposition temperature. All treatment components had significant effects on these parameters. There had a strong correlation between DOC and WSP, and WSP content of the leachates with radical length of test species. This study identified complex interactivity among temperature, WSP, DOC and soil nutrient dynamics of litter occupied soil and that these factors work together to influence phytotoxicity. Copyright © 2015. Published by Elsevier B.V.

Polysaccharide components from the scape of Musa paradisiaca: main structural features of water-soluble polysaccharide component.

PubMed

Anjaneyalu, Y V; Jagadish, R L; Raju, T S

1997-06-01

Polysaccharide components present in the pseudo-stem (scape) of M. paradisiaca were purified from acetone powder of the scape by delignification followed by extraction with aqueous solvents into water soluble polysaccharide (WSP), EDTA-soluble polysaccharide (EDTA-SP), alkali-soluble polysaccharide (ASP) and alkali-insoluble polysaccharide (AISP) fractions. Sugar compositional analysis showed that WSP and EDTA-SP contained only D-Glc whereas ASP contained D-Glc, L-Ara and D-Xyl in approximately 1:1:10 ratio, respectively, and AISP contained D-Glc, L-Ara and D-Xyl in approximately 10:1:2 ratio, respectively. WSP was further purified by complexation with iso-amylalcohol and characterized by specific rotation, IR spectroscopy, Iodine affinity, ferricyanide number, blue value, hydrolysis with alpha-amylase and glucoamylase, and methylation linkage analysis, and shown to be a amylopectin type alpha-D-glucan.

ALA-based fluorescent diagnosis of malignant oral lesions in the presence of bacterial porphyrin formation

NASA Astrophysics Data System (ADS)

Schleier, P.; Berndt, A.; Zinner, K.; Zenk, W.; Dietel, W.; Pfister, W.

2006-02-01

The aminolevulinic acid (5-ALA) -based fluorescence diagnosis has been found to be promising for an early detection and demarcation of superficial oral squamous cell carcinomas (OSCC). This method has previously demonstrated high sensitivity, however this clinical trial showed a specificity of approximately 62 %. This specificity was mainly restricted by tumor detection in the oral cavity in the presence of bacteria. After topical ALA application in the mouth of patients with previously diagnosed OSSC, red fluorescent areas were observed which did not correlate to confirm histological findings. Swabs and plaque samples were taken from 44 patients and cultivated microbiologically. Fluorescence was investigated (OMA-system) from 32 different bacteria strains found naturally in the oral cavity. After ALA incubation, 30 of 32 strains were found to synthesize fluorescent porphyrins, mainly Protoporphyrin IX. Also multiple fluorescent spectra were obtained having peak wavelengths of 636 nm and around 618 nm - 620 nm indicating synthesis of different porphyrins, such as the lipophylic Protoporphyrin IX (PpIX) and hydrophylic porphyrins (water soluble porphyrins, wsp). Of the 32 fluorescent bacterial strains, 18 produced wsp, often in combination with PpIX, and 5 produced solely wsp. These results clarify that ALA-based fluorescence diagnosis without consideration or suppression of bacteria fluorescence may lead to false-positive findings. It is necessary to suppress bacteria fluorescence with suitable antiseptics before starting the procedure. In this study, when specific antiseptic pre-treatment was performed bacterial associated fluorescence was significantly reduced.

Changes in waste stabilisation pond performance resulting from the retrofit of activated sludge treatment upstream: part II--Management and operating issues.

PubMed

Sweeney, D G; O'Brien, M J; Cromar, N J; Fallowfield, H J

2005-01-01

Bolivar Wastewater Treatment Plant (WWTP) was originally commissioned with trickling filter secondary treatment, followed by waste stabilisation pond (WSP) treatment and marine discharge. In 1999, a dissolved air flotation/filtration (DAFF) plant was commissioned to treat a portion of the WSP effluent for horticultural reuse. In 2001, the trickling filters were replaced with activated sludge treatment. A shift in WSP ecology became evident soon after this time, characterised by a statistically significant reduction in algal counts in the pond effluent, and increased variability in algal counts and occasional population crashes in the ponds. While the photosynthetic capacity of the WSPs has been reduced, the concomitant reduction in organic loading has meant that the WSPs have not become overloaded. As a result of the improvement in water quality leaving the ponds, significant cost savings and improved product water quality have been realised in the subsequent DAFF treatment stage. A number of operating issues have arisen from the change, however, including the re-emergence of a midge fly nuisance at the site. Control of midge flies using chemical spraying has negated the cost savings realised in the DAFF treatment stage. While biomanipulation of the WSP may provide a less aggressive method of midge control, this case demonstrates the difficulty of predicting in advance all ramifications of a retrospective process change.

Characteristics and mechanisms of nickel adsorption on biochars produced from wheat straw pellets and rice husk.

PubMed

Shen, Zhengtao; Zhang, Yunhui; McMillan, Oliver; Jin, Fei; Al-Tabbaa, Abir

2017-05-01

The adsorption characteristics and mechanisms of Ni 2+ on four-standard biochars produced from wheat straw pellets (WSP550, WSP700) and rice husk (RH550, RH700) at 550 and 700 °C, respectively, were investigated. The kinetic results show that the adsorption of Ni 2+ on the biochars reached an equilibrium within 5 min. The increase of the solid to liquid ratio resulted in an increase of Ni 2+ removal percentage but a decrease of the adsorbed amount of Ni 2+ per weight unit of biochar. The Ni 2+ removal percentage increased with the increasing of initial solution pH values at the range of 2-4, was relatively constant at the pH range of 4-8, and significantly increased to ≥98% at pH 9 and stayed constantly at the pH range of 9-10. The calculated maximum adsorption capacities of Ni 2+ for the biochars follow the order of WSP700 > WSP550 > RH700 > RH550. Both cation exchange capacity and pH of biochar can be a good indicator of the maximum adsorption capacity for Ni 2+ showing a positively linear and exponential relationship, respectively. This study also suggests that a carefully controlled standardised production procedure can make it reliable to compare the adsorption capacities between different biochars and investigate the mechanisms involved.

Prevalence of different pain categories based on pain spreading on the bodies of older adults in Sweden: a descriptive-level and multilevel association with demographics, comorbidities, medications, and certain lifestyle factors (PainS65+)

PubMed Central

Dragioti, E; Larsson, B; Bernfort, L; Levin, LÅ; Gerdle, B

2016-01-01

Background and objective There is limited knowledge about the prevalence of pain and its relation to comorbidities, medication, and certain lifestyle factors in older adults. To address this limitation, this cross-sectional study examined the spreading of pain on the body in a sample of 6611 subjects ≥65 years old (mean age = 75.0 years; standard deviation [SD] = 7.7) living in southeastern Sweden. Methods Sex, age, comorbidities, medication, nicotine, alcohol intake, and physical activity were analyzed in relation to the following pain categories: local pain (LP) (24.1%), regional pain medium (RP-Medium) (20.3%), regional pain heavy (RP-Heavy) (5.2%), and widespread pain (WSP) (1.7%). Results RP-Medium, RP-Heavy, and WSP were associated more strongly with women than with men (all p<0.01). RP-Heavy was less likely in the 80–84 and >85 age groups compared to the 65–69 age group (both p<0.01). Traumatic injuries, rheumatoid arthritis/osteoarthritis, and analgesics were associated with all pain categories (all p<0.001). An association with gastrointestinal disorders was found in LP, RP-Medium, and RP-Heavy (all p<0.01). Depressive disorders were associated with all pain categories, except for LP (all p<0.05). Disorders of the central nervous system were associated with both RP-Heavy and WSP (all p<0.05). Medication for peripheral vascular disorders was associated with RP-Medium (p<0.05), and hypnotics were associated with RP-Heavy (p<0.01). Conclusion More than 50% of older adults suffered from different pain spread categories. Women were more likely to experience greater spreading of pain than men. A noteworthy number of common comorbidities and medications were associated with increased likelihood of pain spread from LP to RP-Medium, RP-Heavy, and WSP. Effective management plans should consider these observed associations to improve functional deficiency and decrease spreading of pain-related disability in older adults. PMID:27942232

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G.; Salapura, Valentina

2012-07-24

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

FT-IR and FT-Raman characterization of non-cellulosic polysaccharides fractions isolated from plant cell wall.

PubMed

Chylińska, Monika; Szymańska-Chargot, Monika; Zdunek, Artur

2016-12-10

The purpose of this work was to reveal the structural changes of cell wall polysaccharides' fractions during tomato fruit development by analysis of spectral data. Mature green and red ripe tomato fruit were taken into consideration. The FT-IR spectra of water soluble pectin (WSP), imidazole soluble pectin (ISP) and diluted alkali soluble pectin (DASP) contained bands typical for pectins. Whereas for KOH fraction spectra bands typical for hemicelluloses were present. The FT-IR spectra showed the drop down of esterification degree of WSP and ISP polysaccharides during maturation. The changes in polysaccharides structure revealed by spectra were the most visible in the case of pectic polysaccharides. The WSP and DASP fraction pectins molecules length were shortened during tomato maturation and ripening. Whereas the ISP fraction spectra analysis showed that this fraction contained rhamnogalacturonan I, but also for red ripe was rich in pectic galactan comparing with ISP fraction from mature green. Copyright © 2016 Elsevier Ltd. All rights reserved.

Wolbachia supergroups A and B in natural populations of medically important filth flies (diptera: muscidae, calliphoridae, and sarcophagidae) in Thailand.

PubMed

Mingchay, Pichanon; Sai-Ngam, Arkhom; Phumee, Atchara; Bhakdeenuan, Payu; Lorlertthum, Kittitouch; Thavara, Usavadee; Tawatsin, Apiwat; Choochote, Wej; Siriyasatien, Padet

2014-03-01

Filth flies, belonging to suborder Brachycera (Family; Muscidae, Calliphoridae and Sarcophagidae), are a major cause of nuisance and able to transmit pathogens to humans and animals. These insects are distributed worldwide and their populations are increasing especially in sub-tropical and tropical areas. One strategy for controlling insects employs Wolbachia, which is a group of maternally inherited intracellular bacteria, found in many insect species. The bacteria can cause reproductive abnormalities in their hosts, such as cytoplasmic incompatibility, feminization, parthenogenesis, and male lethality. In this study we determined Wolbachia endosymbionts in natural population of medically important flies (42 females and 9 males) from several geographic regions of Thailand. Wolbachia supergroups A or B were detected in 7 of female flies using PCR specific for wsp. Sequence analysis of wsp showed variations between and within the Wolbachia supergroup. Phylogenetics demonstrated that wsp is able to diverge between Wolbachia supergroups A and B. These data should be useful in future Wolbachia-based programs of fly control.

Methyl de-esterification as a major factor regulating the extent of pectin depolymerization during fruit ripening: a comparison of the action of avocado (Persea americana) and tomato (Lycopersicon esculentum) polygalacturonases.

PubMed

Wakabayashi, Kazuyuki; Hoson, Takayuki; Huber, Donald J

2003-06-01

Pectinmethylesterase (PME, EC 3.2.1.11) and polygalacturonase (PG, EC 3.2.1.15) are known to operate in tandem to degrade methylesterified polyuronides. In this study, PGs purified from tomato and avocado fruit were compared in terms of their capacity to hydrolyze water-soluble polyuronides from avocado before and following enzymic or chemical de-esterification. When assayed using polygalacturonic acid or polyuronides from avocado fruit, the activity of PG from tomato fruit was 3-4 times higher than that from avocado fruit. High molecular mass, low methylesterified (33%) water-soluble polyuronides (WSP) from pre-ripe avocado fruit (day 0) were partially depolymerized upon incubation with purified avocado and tomato PGs. In contrast, middle molecular mass, highly methylesterified (74%) WSP from day 2 fruit were largely resistant to the action of both PGs. PME or weak alkali treatment of highly methylesterified WSP decreased the methylesterification values to 11 and 4.5%, respectively. Treatment of de-esterified WSP with either avocado or tomato PGs caused extensive molecular mass downshifts, paralleling those observed during avocado fruit ripening. Although PME and PG are found in many fruits, the pattern of depolymerization of native polyuronides indicates that the degree of cooperativity between these enzymes in vivo differs dramatically among fruits. The contribution of PME to patterns of polyuronide depolymerization observed during ripening compared with physically compromised fruit tissues is discussed.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Methods and systems for providing reconfigurable and recoverable computing resources

NASA Technical Reports Server (NTRS)

Stange, Kent (Inventor); Hess, Richard (Inventor); Kelley, Gerald B (Inventor); Rogers, Randy (Inventor)

2010-01-01

A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

Coding, testing and documentation of processors for the flight design system

NASA Technical Reports Server (NTRS)

1980-01-01

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

Wolbachia endosymbionts in haplodiploid and diploid scolytine beetles (Coleoptera: Curculionidae: Scolytinae).

PubMed

Kawasaki, Yuuki; Schuler, Hannes; Stauffer, Christian; Lakatos, Ferenc; Kajimura, Hisashi

2016-05-19

Haplodiploidy is a sex determination system in which fertilized diploid eggs develop into females and unfertilized haploid eggs develop into males. The evolutionary explanations for this phenomenon include the possibility that haplodiploidy can be reinforced by infection with endosymbiotic bacteria, such as Wolbachia. The subfamily Scolytinae contains species with haplodiploid and diploid sex determination systems. Thus, we studied the association with Wolbachia in 12 diploid and 11 haplodiploid scolytine beetles by analyzing wsp and multilocus sequence typing (MLST) of five loci in this endosymbiont. Wolbachia genotypes were compared with mitochondrial (COI) and nuclear (EF) genotypes in the scolytines. Eight of the 23 scolytine species were infected with Wolbachia, with haplodiploids at significantly higher rates than diploid species. Cloning and sequencing detected multiple infections with up to six Wolbachia strains in individual species. Phylogenetic analyses of wsp and five MLST genes revealed different Wolbachia strains in scolytines. Comparisons between the beetle and Wolbachia phylogenies revealed that closely related beetles were infected with genetically different Wolbachia strains. These results suggest the horizontal transmission of multiple Wolbachia strains between scolytines. We discuss these results in terms of the evolution of different sex determination systems in scolytine beetles. © 2016 Society for Applied Microbiology and John Wiley & Sons Ltd.

Controlling Legionella and Pseudomonas aeruginosa re-growth in therapeutic spas: implementation of physical disinfection treatments, including UV/ultrafiltration, in a respiratory hydrotherapy system.

PubMed

Leoni, E; Sanna, T; Zanetti, F; Dallolio, L

2015-12-01

The study aimed to assess the efficacy of an integrated water safety plan (WSP) in controlling Legionella re-growth in a respiratory hydrotherapy system located in a spa centre, supplied with sulphurous water, which was initially colonized by Legionella pneumophila. Heterotrophic plate counts, Pseudomonas aeruginosa, Legionella spp. were detected in water samples taken 6-monthly from the hydrotherapy equipment (main circuit, entry to benches, final outlets). On the basis of the results obtained by the continuous monitoring and the changes in conditions, the original WSP, including physical treatments of water and waterlines, environmental surveillance and microbiological monitoring, was integrated introducing a UV/ultrafiltration system. The integrated treatment applied to the sulphurous water (microfiltration/UV irradiation/ultrafiltration), waterlines (superheated stream) and distal outlets (descaling/disinfection of nebulizers and nasal irrigators), ensured the removal of Legionella spp. and P. aeruginosa and a satisfactory microbiological quality over time. The environmental surveillance was successful in evaluating the hazard and identifying the most suitable preventive strategies to avoid Legionella re-growth. Ultrafiltration is a technology to take into account in the control of microbial contamination of therapeutic spas, since it does not modify the chemical composition of the water, thus allowing it to retain its therapeutic properties.

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G; Salapura, Valentina

2014-12-02

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Modeling heterogeneous processor scheduling for real time systems

NASA Technical Reports Server (NTRS)

Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

1994-01-01

A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, R.; Fischler, M.S.; Husby, D.E.

1991-01-15

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured. 11 figures.

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, Robert; Fischler, Mark S.; Husby, Donald E.

1991-01-01

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, Michael S.; Strip, David R.

1996-01-01

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modelling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modelling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modelling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.; Goodman, Joseph W.

1989-01-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

Flight design system level C requirements. Solid rocket booster and external tank impact prediction processors. [space transportation system

NASA Technical Reports Server (NTRS)

Seale, R. H.

1979-01-01

The prediction of the SRB and ET impact areas requires six separate processors. The SRB impact prediction processor computes the impact areas and related trajectory data for each SRB element. Output from this processor is stored on a secure file accessible by the SRB impact plot processor which generates the required plots. Similarly the ET RTLS impact prediction processor and the ET RTLS impact plot processor generates the ET impact footprints for return-to-launch-site (RTLS) profiles. The ET nominal/AOA/ATO impact prediction processor and the ET nominal/AOA/ATO impact plot processor generate the ET impact footprints for non-RTLS profiles. The SRB and ET impact processors compute the size and shape of the impact footprints by tabular lookup in a stored footprint dispersion data base. The location of each footprint is determined by simulating a reference trajectory and computing the reference impact point location. To insure consistency among all flight design system (FDS) users, much input required by these processors will be obtained from the FDS master data base.

Determination of Wolbachia Diversity in Butterflies from Western Ghats, India, by a Multigene Approach

PubMed Central

Salunke, Bipinchandra K.; Salunkhe, Rahul C.; Dhotre, Dhiraj P.; Walujkar, Sandeep A.; Khandagale, Avinash B.; Chaudhari, Rahul; Chandode, Rakesh K.; Ghate, Hemant V.; Patole, Milind S.; Werren, John H.

2012-01-01

Members of the genus Wolbachia are intracellular bacteria that are widespread in arthropods and establish diverse symbiotic associations with their hosts, ranging from mutualism to parasitism. Here we present the first detailed analyses of Wolbachia in butterflies from India with screening of 56 species. Twenty-nine species (52%) representing five families were positive for Wolbachia. This is the first report of Wolbachia infection in 27 of the 29 species; the other two were reported previously. This study also provides the first evidence of infection in the family Papilionidae. A striking diversity was observed among Wolbachia strains in butterfly hosts based on five multilocus sequence typing (MLST) genes, with 15 different sequence types (STs). Thirteen STs are new to the MLST database, whereas ST41 and ST125 were reported earlier. Some of the same host species from this study carried distinctly different Wolbachia strains, whereas the same or different butterfly hosts also harbored closely related Wolbachia strains. Butterfly-associated STs in the Indian sample originated by recombination and point mutation, further supporting the role of both processes in generating Wolbachia diversity. Recombination was detected only among the STs in this study and not in those from the MLST database. Most of the strains were remarkably similar in their wsp genotype, despite divergence in MLST. Only two wsp alleles were found among 25 individuals with complete hypervariable region (HVR) peptide profiles. Although both wsp and MLST show variability, MLST gives better separation between the strains. Completely different STs were characterized for the individuals sharing the same wsp alleles. PMID:22504801

Hot Chips and Hot Interconnects for High End Computing Systems

NASA Technical Reports Server (NTRS)

Saini, Subhash

2005-01-01

I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

Processor architecture for airborne SAR systems

NASA Technical Reports Server (NTRS)

Glass, C. M.

1983-01-01

Digital processors for spaceborne imaging radars and application of the technology developed for airborne SAR systems are considered. Transferring algorithms and implementation techniques from airborne to spaceborne SAR processors offers obvious advantages. The following topics are discussed: (1) a quantification of the differences in processing algorithms for airborne and spaceborne SARs; and (2) an overview of three processors for airborne SAR systems.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, M.S.; Strip, D.R.

1996-01-30

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modeling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modeling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modeling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication. 8 figs.

Association of Wolbachia with heartworm disease in cats and dogs.

PubMed

Dingman, Patricia; Levy, Julie K; Kramer, Laura H; Johnson, Calvin M; Lappin, Michael R; Greiner, Ellis C; Courtney, Charles H; Tucker, Sylvia J; Morchon, Rodrigo

2010-05-28

Although the presence of adult Dirofilaria immitis in the pulmonary arteries and its associated arteritis and thromboembolic disease can explain some of the manifestations of canine and feline heartworm disease, the cause of other findings remains unclear. Cats with D. immitis antibodies but lacking adult parasites in the pulmonary arteries frequently develop histological lesions of the airways, resulting in a condition termed Heartworm-Associated Respiratory Disease. All D. immitis parasites harbor Wolbachia pipientis bacteria and D. immitis-infected animals can have circulating Wolbachia antibodies and pro-inflammatory Wolbachia antigens (WSP) deposited in tissues. Little is known about the role that Wolbachia plays in lung disease of animals naturally infected with D. immitis. The purpose of this study was to determine the contribution of Wolbachia to the pathogenesis of natural heartworm disease in cats and dogs. We hypothesized that animals having sufficient Wolbachia burden to be detected in lung tissue by immunohistochemistry and/or polymerase chain reaction (PCR) would have more severe pulmonary disease than those with bacteria below the limits of detection. We further hypothesized that animals that were immunoreactive to pro-inflammatory WSP would have more severe pulmonary lesions than those that were seronegative for WSP antibodies. Blood and lung tissue samples were collected from cats and dogs representing three different D. immitis infection statuses: heartworm-free, heartworm-exposed, heartworm-infected. There was a positive but weak correlation between the magnitude of D. immitis antibody titers and WSP titers in cats (r=0.57, p<0.001) and in dogs (r=0.39, p<0.001). Pulmonary lesions were more common in HW-infected animals than in HW-free animals. Pulmonary arteriolar occlusion was more common in HW-infected cats (57%; p=0.003) than in HW-infected dogs (17%). Although pulmonary lesions were most common in HW-infected animals, there was no clear additive effect when either Wolbachia DNA/WSP was detected in lung tissue or when circulating Wolbachia antibodies were detected. There were no significant differences in the magnitude of pulmonary lesion scores within each HW-infection status group regardless of whether Wolbachia DNA/WSP or antibodies were detected. The relationship between Wolbachia and lung pathology in heartworm-infected animals remains to be determined. The lack of clear evidence for a role of Wolbachia in heartworm disease creates a dilemma for veterinarians treating animals in D. immitis-endemic areas. Although the indiscriminant use of antibiotics should be avoided, many clinicians prescribe doxycycline based on the favorable responses observed in human filarial diseases and promising results from the first published studies of doxycycline use in D. immitis-infected dogs. (c) 2010 Elsevier B.V. All rights reserved.

Buffered coscheduling for parallel programming and enhanced fault tolerance

DOEpatents

Petrini, Fabrizio [Los Alamos, NM; Feng, Wu-chun [Los Alamos, NM

2006-01-31

A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors

Next Generation Space Telescope Integrated Science Module Data System

NASA Technical Reports Server (NTRS)

Schnurr, Richard G.; Greenhouse, Matthew A.; Jurotich, Matthew M.; Whitley, Raymond; Kalinowski, Keith J.; Love, Bruce W.; Travis, Jeffrey W.; Long, Knox S.

1999-01-01

The Data system for the Next Generation Space Telescope (NGST) Integrated Science Module (ISIM) is the primary data interface between the spacecraft, telescope, and science instrument systems. This poster includes block diagrams of the ISIM data system and its components derived during the pre-phase A Yardstick feasibility study. The poster details the hardware and software components used to acquire and process science data for the Yardstick instrument compliment, and depicts the baseline external interfaces to science instruments and other systems. This baseline data system is a fully redundant, high performance computing system. Each redundant computer contains three 150 MHz power PC processors. All processors execute a commercially available real time multi-tasking operating system supporting, preemptive multi-tasking, file management and network interfaces. These six processors in the system are networked together. The spacecraft interface baseline is an extension of the network, which links the six processors. The final selection for Processor busses, processor chips, network interfaces, and high-speed data interfaces will be made during mid 2002.

Communications Processor Operating System Study. Executive Summary,

DTIC Science & Technology

1980-11-01

AD-A095 b36 ROME AIR DEVELOPMENT CENTER GRIFFISS AFB NY F/e 17/2 COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY. EXECUTIVE SUMM—ETC(U) NOV 80 J...COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY Julian Gitlih SPTIC ELECTE«^ FEfi 2 6 1981^ - E APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED "a O...Subtitle) EXECUTIVE^SUMMARY 0F> COMMUNICATIONS PROCESSOR OPERATING SYSTEM $t - • >X W tdLl - ’•• • 7 AUTHORf«! ! , Julian

LANDSAT-D flight segment operations manual. Appendix B: OBC software operations

NASA Technical Reports Server (NTRS)

Talipsky, R.

1981-01-01

The LANDSAT 4 satellite contains two NASA standard spacecraft computers and 65,536 words of memory. Onboard computer software is divided into flight executive and applications processors. Both applications processors and the flight executive use one or more of 67 system tables to obtain variables, constants, and software flags. Output from the software for monitoring operation is via 49 OBC telemetry reports subcommutated in the spacecraft telemetry. Information is provided about the flight software as it is used to control the various spacecraft operations and interpret operational OBC telemetry. Processor function descriptions, processor operation, software constraints, processor system tables, processor telemetry, and processor flow charts are presented.

Concept of a programmable maintenance processor applicable to multiprocessing systems

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1988-01-01

A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

An examination of the potential added value of water safety plans to the United States national drinking water legislation.

PubMed

Baum, Rachel; Amjad, Urooj; Luh, Jeanne; Bartram, Jamie

2015-11-01

National and sub-national governments develop and enforce regulations to ensure the delivery of safe drinking water in the United States (US) and countries worldwide. However, periodic contamination events, waterborne endemic illness and outbreaks of waterborne disease still occur, illustrating that delivery of safe drinking water is not guaranteed. In this study, we examined the potential added value of a preventive risk management approach, specifically, water safety plans (WSPs), in the US in order to improve drinking water quality. We undertook a comparative analysis between US drinking water regulations and WSP steps to analyze the similarities and differences between them, and identify how WSPs might complement drinking water regulations in the US. Findings show that US drinking water regulations and WSP steps were aligned in the areas of describing the water supply system and defining monitoring and controls. However, gaps exist between US drinking water regulations and WSPs in the areas of team procedures and training, internal risk assessment and prioritization, and management procedures and plans. The study contributes to understanding both required and voluntary drinking water management practices in the US and how implementing water safety plans could benefit water systems to improve drinking water quality and human health. Copyright © 2015 Elsevier GmbH. All rights reserved.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Effects of Cultivating Conditions on the Water Soluble Polysaccharides Content of Ganoderma lucidum Mycelium in Submerged Flask Culture

NASA Astrophysics Data System (ADS)

Rosyida, V. T.; Hayati, S. N.; Apriyana, W.; Darsih, C.; Hernawan; Poeloengasih, C. D.

2017-12-01

The carcinostatic substance in Ganoderma lucidum (Fr.) Karst (Polyporaceae) is a water soluble polysaccharides (WSP) which might be useful in immunotherapy. Attempt to produce effective substances from cultured mycelia is important to carry out since solid cultivation is a time consuming and quality fluctuating. The effects of cultivating conditions on the water soluble polysaccharides content of G. Lucidum mycelium were investigated in submerged flask cultures. Culture from fruiting bodies was maintained on potato dextrose-agar slope. Slopes were inoculated and incubated at 30°C for 7 days, and stored at 4°C. The flask experiments were performed in 100 ml erlenmeyer flasks containing 20 ml of the sterilized media. Actively growing mycelia (1 piece, 5 mm X 5 mm) from a newly prepared slant culture (about 7 days incubation at 30°C) were inoculated into the flask. The pH was measured and adjusted to the desired value by addition of either 4 M HCl or 2.5 M NaOH. Incubation temperature were 20, 25, and 30°C. At the end of inoculation period (14 days) mycelium consisting of individual pellets was harvested and wash for the analysis. WSP content was analysed using phenol-sulfuric acid method. The optimal initial pH for metabolite production would depend on the culture medium. Generally, high values of pH, such as 9, negatively affect both cell growth and WSP production. The optimum temperature range for the high G. lucidum mycelium and WSP production were found to be 25 - 30 °C at pH values 5 - 7 in both of media.

Influence of various metal oxides on mechanical and physical properties of heat-cured polymethyl methacrylate denture base resins.

PubMed

Asar, Neset Volkan; Albayrak, Hamdi; Korkmaz, Turan; Turkyilmaz, Ilser

2013-08-01

To evaluate the effect of various metal oxides on impact strength (IS), fracture toughness (FT), water sorption (WSP) and solubility (WSL) of heat-cured acrylic resin. Fifty acrylic resin specimens were fabricated for each test and divided into five groups. Group 1 was the control group and Group 2, 3, 4 and 5 (test groups) included a mixture of 1% TiO2 and 1% ZrO2, 2% Al2O3, 2% TiO2, and 2% ZrO2 by volume, respectively. Rectangular unnotched specimens (50 mm × 6.0 mm × 4.0 mm) were fabricated and droptower impact testing machine was used to determine IS. For FT, compact test specimens were fabricated and tests were done with a universal testing machine with a cross-head speed of 5 mm/min. For WSP and WSL, discshaped specimens were fabricated and tests were performed in accordance to ISO 1567. ANOVA and Kruskal-Wallis tests were used for statistical analyses. IS and FT values were significantly higher and WSP and WSL values were significantly lower in test groups than in control group (P<.05). Group 5 had significantly higher IS and FT values and significantly lower WSP values than other groups (P<.05) and provided 40% and 30% increase in IS and FT, respectively, compared to control group. Significantly lower WSL values were detected for Group 2 and 5 (P<.05). Modification of heat-cured acrylic resin with metal oxides, especially with ZrO2, may be useful in preventing denture fractures and undesirable physical changes resulting from oral fluids clinically.

A Cambrian mixed carbonate-siliciclastic platform in SW Gondwana: evidence from the Western Sierras Pampeanas (Argentina) and implications for the early Paleozoic paleogeography of the proto-Andean margin

NASA Astrophysics Data System (ADS)

Ramacciotti, Carlos D.; Casquet, César; Baldo, Edgardo G.; Galindo, Carmen; Pankhurst, Robert J.; Verdecchia, Sebastián O.; Rapela, Carlos W.; Fanning, Mark

2018-05-01

The Western Sierras Pampeanas (WSP) of Argentina record a protracted geological history from the Mesoproterozoic assembly of the Rodinia supercontinent to the early Paleozoic tectonic evolution of SW Gondwana. Two well-known orogenies took place at the proto-Andean margin of Gondwana in the Cambrian and the Ordovician, i.e., the Pampean (545-520 Ma) and Famatinian (490-440 Ma) orogenies, respectively. Between them, an extensive continental platform was developed, where mixed carbonate-siliciclastic sedimentation occurred. This platform was later involved in the Famatinian orogeny when it underwent penetrative deformation and metamorphism. The platform apparently extended from Patagonia to northwestern Argentina and the Eastern Sierras Pampeanas, and has probable equivalents in SW Africa, Peru, and Bolivia. The WSP record the outer (deepest) part of the platform, where carbonates were deposited in addition to siliciclastic sediments. Detrital zircon U-Pb SHRIMP ages from clastic metasedimentary successions and Sr-isotope compositions of marbles from the WSP suggest depositional ages between ca. 525 and 490 Ma. The detrital zircon age patterns further suggest that clastic sedimentation took place in two stages. The first was sourced mainly from re-working of the underlying Neoproterozoic metasedimentary rocks and the uplifted core of the early Cambrian Pampean orogen, without input from the Paleoproterozoic Río de la Plata craton. Sediments of the second stage resulted from the erosion of the still emerged Pampean belt and the Neoproterozoic Brasiliano orogen in the NE with some contribution from the Río de la Plata craton. An important conclusion is that the WSP basement was already part of SW Gondwana in the early Cambrian, and not part of the exotic Precordillera/Cuyania terrane, as was previously thought.

Simulink/PARS Integration Support

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, B.; Nakhaee, N.

2013-12-18

The state of the art for signal processor hardware has far out-paced the development tools for placing applications on that hardware. In addition, signal processors are available in a variety of architectures, each uniquely capable of handling specific types of signal processing efficiently. With these processors becoming smaller and demanding less power, it has become possible to group multiple processors, a heterogeneous set of processors, into single systems. Different portions of the desired problem set can be assigned to different processor types as appropriate. As software development tools do not keep pace with these processors, especially when multiple processors ofmore » different types are used, a method is needed to enable software code portability among multiple processors and multiple types of processors along with their respective software environments. Sundance DSP, Inc. has developed a software toolkit called “PARS”, whose objective is to provide a framework that uses suites of tools provided by different vendors, along with modeling tools and a real time operating system, to build an application that spans different processor types. The software language used to express the behavior of the system is a very high level modeling language, “Simulink”, a MathWorks product. ORNL has used this toolkit to effectively implement several deliverables. This CRADA describes this collaboration between ORNL and Sundance DSP, Inc.« less

Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,

DTIC Science & Technology

2006-07-26

is, and the control laws the user implements to control it. The flight control system board will contain the processor selected for this system...Unit (IMU). The IMU contains solid-state gyros and accelerometers and uses these to determine the attitude of the UAV within the three dimensions of...multiple-UAV swarming for combat support operations. The mission processor board will contain the processor selected to execute the mission

Molecular characterization of Wolbachia infection in bed bugs (Cimex lectularius) collected from several localities in France

PubMed Central

Akhoundi, Mohammad; Cannet, Arnaud; Loubatier, Céline; Berenger, Jean-Michel; Izri, Arezki; Marty, Pierre; Delaunay, Pascal

2016-01-01

Wolbachia symbionts are maternally inherited intracellular bacteria that have been detected in numerous insects including bed bugs. The objective of this study, the first epidemiological study in Europe, was to screen Wolbachia infection among Cimex lectularius collected in the field, using PCR targeting the surface protein gene (wsp), and to compare obtained Wolbachia strains with those reported from laboratory colonies of C. lectularius as well as other Wolbachia groups. For this purpose, 284 bed bug specimens were caught and studied from eight different regions of France including the suburbs of Paris, Bouches-du-Rhône, Lot-et-Garonne, and five localities in Alpes-Maritimes. Among the samples, 166 were adults and the remaining 118 were considered nymphs. In all, 47 out of 118 nymphs (40%) and 61 out of 166 adults (37%) were found positive on wsp screening. Among the positive cases, 10 samples were selected randomly for sequencing. The sequences had 100% homology with wsp sequences belonging to the F-supergroup strains of Wolbachia. Therefore, we confirm the similarity of Wolbachia strains detected in this epidemiological study to Wolbachia spp. reported from laboratory colonies of C. lectularius. PMID:27492563

Comorbidities, intensity, frequency and duration of pain, daily functioning and health care seeking in local, regional, and widespread pain - a descriptive population-based survey (SwePain).

PubMed

Grimby-Ekman, Anna; Gerdle, Björn; Björk, Jonas; Larsson, Britt

2015-07-24

The clinical knowledge of factors related to the spread of pain on the body has increased and understanding these factors is essential for effective pain treatment. This population-based study examines local (LP), regional (RP), and widespread pain (WSP) on the body regarding comorbidities, pain aspects, and impact of pain and elucidates how the spread of pain varies over time. A postal questionnaire that addressed pain aspects (intensity, frequency, duration and anatomical spreading on a body manikin), comorbidities and implications of pain (i.e., work situation, physical activity, consumption of health care and experience of hospitality and treatment of health care) was sent to 9000 adults living in southeastern Sweden. Of these, 4774 (53 %) completed and returned the questionnaire. After 9 weeks, a follow-up questionnaire was sent to the 2983 participants who reported pain in the first questionnaire (i.e. 62 % of 4774 subjects). Of these, 1940 completed and returned the questionnaire (i.e. 65 % of 2983 subjects). The follow-up questionnaire included the same items as the first questionnaire. This study found differences in intensity, frequency and duration of pain, comorbidities, aspects of daily functioning and health care seeking in three pain categories based on spreading of pain: LP, RP and WSP. Compared to the participants with RP and LP, the participants with WSP had lower education and worse overall health, including more frequent heart disease and hypertension. In addition, participants with WSP had more intense, frequent, and long-standing pain, required more medical consultations, and experienced more impact on work. The participants with RP constituted an intermediate group regarding frequency and intensity of pain, and impact on work. The participants with LP were the least affected group regarding these factors. A substantial transition to RP had occurred by the 9-week follow-up. This study shows an association between increased spread of pain and prevalence of heart disease, hypertension, more severe pain characteristics (i.e., intensity, frequency and duration), problems with common daily activities and increased health care seeking. The WSP group was the most affected group and the LP group was the least affected group. Regarding these factors, RP was an obvious intermediate group. The transitions between the pain categories warrant research that broadly investigates factors that increase and decrease pain.

Conditional load and store in a shared memory

DOEpatents

Blumrich, Matthias A; Ohmacht, Martin

2015-02-03

A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

Verification of a Proposed Clinical Electroacoustic Test Protocol for Personal Digital Modulation Receivers Coupled to Cochlear Implant Sound Processors.

PubMed

Nair, Erika L; Sousa, Rhonda; Wannagot, Shannon

Guidelines established by the AAA currently recommend behavioral testing when fitting frequency modulated (FM) systems to individuals with cochlear implants (CIs). A protocol for completing electroacoustic measures has not yet been validated for personal FM systems or digital modulation (DM) systems coupled to CI sound processors. In response, some professionals have used or altered the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting FM systems to CI sound processors. More recently steps were outlined in a proposed protocol. The purpose of this research is to review and compare the electroacoustic test measures outlined in a 2013 article by Schafer and colleagues in the Journal of the American Academy of Audiology titled "A Proposed Electroacoustic Test Protocol for Personal FM Receivers Coupled to Cochlear Implant Sound Processors" to the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting DM systems to CI users. Electroacoustic measures were conducted on 71 CI sound processors and Phonak Roger DM systems using a proposed protocol and an adapted AAA protocol. Phonak's recommended default receiver gain setting was used for each CI sound processor manufacturer and adjusted if necessary to achieve transparency. Electroacoustic measures were conducted on Cochlear and Advanced Bionics (AB) sound processors. In this study, 28 Cochlear Nucleus 5/CP810 sound processors, 26 Cochlear Nucleus 6/CP910 sound processors, and 17 AB Naida CI Q70 sound processors were coupled in various combinations to Phonak Roger DM dedicated receivers (25 Phonak Roger 14 receivers-Cochlear dedicated receiver-and 9 Phonak Roger 17 receivers-AB dedicated receiver) and 20 Phonak Roger Inspiro transmitters. Employing both the AAA and the Schafer et al protocols, electroacoustic measurements were conducted with the Audioscan Verifit in a clinical setting on 71 CI sound processors and Phonak Roger DM systems to determine transparency and verify FM advantage, comparing speech inputs (65 dB SPL) in an effort to achieve equal outputs. If transparency was not achieved at Phonak's recommended default receiver gain, adjustments were made to the receiver gain. The integrity of the signal was monitored with the appropriate manufacturer's monitor earphones. Using the AAA hearing aid protocol, 50 of the 71 CI sound processors achieved transparency, and 59 of the 71 CI sound processors achieved transparency when using the proposed protocol at Phonak's recommended default receiver gain. After the receiver gain was adjusted, 3 of 21 CI sound processors still did not meet transparency using the AAA protocol, and 2 of 12 CI sound processors still did not meet transparency using the Schafer et al proposed protocol. Both protocols were shown to be effective in taking reliable electroacoustic measurements and demonstrate transparency. Both protocols are felt to be clinically feasible and to address the needs of populations that are unable to reliably report regarding the integrity of their personal DM systems. American Academy of Audiology

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

NASA Technical Reports Server (NTRS)

Goldberg, J.; Kautz, W. H.; Melliar-Smith, P. M.; Green, M. W.; Levitt, K. N.; Schwartz, R. L.; Weinstock, C. B.

1984-01-01

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness.

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

NASA Technical Reports Server (NTRS)

Strohkorb, G. A.; Noor, A. K.

1983-01-01

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

A universal computer control system for motors

NASA Technical Reports Server (NTRS)

Szakaly, Zoltan F. (Inventor)

1991-01-01

A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor.

Rapid Damage Assessment. Volume II. Development and Testing of Rapid Damage Assessment System.

DTIC Science & Technology

1981-02-01

pixels/s Camera Line Rate 732.4 lines/s Pixels per Line 1728 video 314 blank 4 line number (binary) 2 run number (BCD) 2048 total Pixel Resolution 8 bits...sists of an LSI-ll microprocessor, a VDI -200 video display processor, an FD-2 dual floppy diskette subsystem, an FT-I function key-trackball module...COMPONENT LIST FOR IMAGE PROCESSOR SYSTEM IMAGE PROCESSOR SYSTEM VIEWS I VDI -200 Display Processor Racks, Table FD-2 Dual Floppy Diskette Subsystem FT-l

Future applications of associative processor systems to operational KSC systems for optimizing cost and enhancing performance characteristics

NASA Technical Reports Server (NTRS)

Perkinson, J. A.

1974-01-01

The application of associative memory processor equipment to conventional host processors type systems is discussed. Efforts were made to demonstrate how such application relieves the task burden of conventional systems, and enhance system speed and efficiency. Data cover comparative theoretical performance analysis, demonstration of expanded growth capabilities, and demonstrations of actual hardware in simulated environment.

System Control Facilities: Head-Ends and Central Processors. A Survey of Technical Requirements for Broadband Cable Teleservices; Volume Four.

ERIC Educational Resources Information Center

Smith, Ernest K.; And Others

The system control facilities in broadband communication systems are discussed in this report. These facilities consist of head-ends and central processors. The first section summarizes technical problems and needs, and the second offers a cursory overview of systems, along with an incidental mention of processors. Section 3 looks at the question…

Green Secure Processors: Towards Power-Efficient Secure Processor Design

NASA Astrophysics Data System (ADS)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Contextual classification on a CDC Flexible Processor system. [for photomapped remote sensing data

NASA Technical Reports Server (NTRS)

Smith, B. W.; Siegel, H. J.; Swain, P. H.

1981-01-01

A potential hardware organization for the Flexible Processor Array is presented. An algorithm that implements a contextual classifier for remote sensing data analysis is given, along with uniprocessor classification algorithms. The Flexible Processor algorithm is provided, as are simulated timings for contextual classifiers run on the Flexible Processor Array and another system. The timings are analyzed for context neighborhoods of sizes three and nine.

Reactive oxygen species drive evolution of pro-biofilm variants in pathogens by modulating cyclic-di-GMP levels.

PubMed

Chua, Song Lin; Ding, Yichen; Liu, Yang; Cai, Zhao; Zhou, Jianuan; Swarup, Sanjay; Drautz-Moses, Daniela I; Schuster, Stephan Christoph; Kjelleberg, Staffan; Givskov, Michael; Yang, Liang

2016-11-01

The host immune system offers a hostile environment with antimicrobials and reactive oxygen species (ROS) that are detrimental to bacterial pathogens, forcing them to adapt and evolve for survival. However, the contribution of oxidative stress to pathogen evolution remains elusive. Using an experimental evolution strategy, we show that exposure of the opportunistic pathogen Pseudomonas aeruginosa to sub-lethal hydrogen peroxide (H 2 O 2 ) levels over 120 generations led to the emergence of pro-biofilm rough small colony variants (RSCVs), which could be abrogated by l-glutathione antioxidants. Comparative genomic analysis of the RSCVs revealed that mutations in the wspF gene, which encodes for a repressor of WspR diguanylate cyclase (DGC), were responsible for increased intracellular cyclic-di-GMP content and production of Psl exopolysaccharide. Psl provides the first line of defence against ROS and macrophages, ensuring the survival fitness of RSCVs over wild-type P. aeruginosa Our study demonstrated that ROS is an essential driving force for the selection of pro-biofilm forming pathogenic variants. Understanding the fundamental mechanism of these genotypic and phenotypic adaptations will improve treatment strategies for combating chronic infections. © 2016 The Authors.

The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

NASA Astrophysics Data System (ADS)

Åsman, B.; Achenbach, R.; Allbrooke, B. M. M.; Anders, G.; Andrei, V.; Büscher, V.; Bansil, H. S.; Barnett, B. M.; Bauss, B.; Bendtz, K.; Bohm, C.; Bracinik, J.; Brawn, I. P.; Brock, R.; Buttinger, W.; Caputo, R.; Caughron, S.; Cerrito, L.; Charlton, D. G.; Childers, J. T.; Curtis, C. J.; Daniells, A. C.; Davis, A. O.; Davygora, Y.; Dorn, M.; Eckweiler, S.; Edmunds, D.; Edwards, J. P.; Eisenhandler, E.; Ellis, K.; Ermoline, Y.; Föhlisch, F.; Faulkner, P. J. W.; Fedorko, W.; Fleckner, J.; French, S. T.; Gee, C. N. P.; Gillman, A. R.; Goeringer, C.; Hülsing, T.; Hadley, D. R.; Hanke, P.; Hauser, R.; Heim, S.; Hellman, S.; Hickling, R. S.; Hidvégi, A.; Hillier, S. J.; Hofmann, J. I.; Hristova, I.; Ji, W.; Johansen, M.; Keller, M.; Khomich, A.; Kluge, E.-E.; Koll, J.; Laier, H.; Landon, M. P. J.; Lang, V. S.; Laurens, P.; Lepold, F.; Lilley, J. N.; Linnemann, J. T.; Müller, F.; Müller, T.; Mahboubi, K.; Martin, T. A.; Mass, A.; Meier, K.; Meyer, C.; Middleton, R. P.; Moa, T.; Moritz, S.; Morris, J. D.; Mudd, R. D.; Narayan, R.; zur Nedden, M.; Neusiedl, A.; Newman, P. R.; Nikiforov, A.; Ohm, C. C.; Perera, V. J. O.; Pfeiffer, U.; Plucinski, P.; Poddar, S.; Prieur, D. P. F.; Qian, W.; Rieck, P.; Rizvi, E.; Sankey, D. P. C.; Schäfer, U.; Scharf, V.; Schmitt, K.; Schröder, C.; Schultz-Coulon, H.-C.; Schumacher, C.; Schwienhorst, R.; Silverstein, S. B.; Simioni, E.; Snidero, G.; Staley, R. J.; Stamen, R.; Stock, P.; Stockton, M. C.; Tan, C. L. A.; Tapprogge, S.; Thomas, J. P.; Thompson, P. D.; Thomson, M.; True, P.; Watkins, P. M.; Watson, A. T.; Watson, M. F.; Weber, P.; Wessels, M.; Wiglesworth, C.; Williams, S. L.

2012-12-01

The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

Algal wastewater treatment systems for seasonal climates: application of a simple modelling approach to generate local and regional design guidelines.

PubMed

Heaven, Sonia; Salter, Andrew M; Clarke, Derek; Pak, Lyubov N

2012-05-01

Algal waste stabilisation ponds (WSP) provide a means of treating wastewater, and also a potential source of water for re-use in irrigation, aquaculture or algal biomass cultivation. The quantities of treated water available and the periods in which it is suitable for use or discharge are closely linked to climatic factors. This paper describes the application, at a continent-wide scale, of a modelling approach based on the use of readily available climate datasets to provide WSP design and performance guidelines linked to geographical location. Output is presented in regionally-based contour maps covering a wide area of Russia and central Asia and indicating pond area, earliest discharge date, discharge duration, wastewater inflow:outflow ratio and salinity under user-specified conditions. The results confirm that broad-brush discharge guidelines of the type commonly used in North America can safely be applied; but suggest that a more detailed approach is worthwhile to optimise operating regimes for local conditions. The use of long-series climate data can also permit tailoring of designs to specific sites. The work considers a simple 2-pond system, but other configurations and operating regimes should be investigated, especially for the wide range of locations across the world that are intermediate between the 'one short discharge per year' mode and year-round steady-state operation. Copyright © 2012 Elsevier Ltd. All rights reserved.

Digital system for structural dynamics simulation

NASA Technical Reports Server (NTRS)

Krauter, A. I.; Lagace, L. J.; Wojnar, M. K.; Glor, C.

1982-01-01

State-of-the-art digital hardware and software for the simulation of complex structural dynamic interactions, such as those which occur in rotating structures (engine systems). System were incorporated in a designed to use an array of processors in which the computation for each physical subelement or functional subsystem would be assigned to a single specific processor in the simulator. These node processors are microprogrammed bit-slice microcomputers which function autonomously and can communicate with each other and a central control minicomputer over parallel digital lines. Inter-processor nearest neighbor communications busses pass the constants which represent physical constraints and boundary conditions. The node processors are connected to the six nearest neighbor node processors to simulate the actual physical interface of real substructures. Computer generated finite element mesh and force models can be developed with the aid of the central control minicomputer. The control computer also oversees the animation of a graphics display system, disk-based mass storage along with the individual processing elements.

Poster Presentation: Optical Test of NGST Developmental Mirrors

NASA Technical Reports Server (NTRS)

Hadaway, James B.; Geary, Joseph; Reardon, Patrick; Peters, Bruce; Keidel, John; Chavers, Greg

2000-01-01

An Optical Testing System (OTS) has been developed to measure the figure and radius of curvature of NGST developmental mirrors in the vacuum, cryogenic environment of the X-Ray Calibration Facility (XRCF) at Marshall Space Flight Center (MSFC). The OTS consists of a WaveScope Shack-Hartmann sensor from Adaptive Optics Associates as the main instrument, a Point Diffraction Interferometer (PDI), a Point Spread Function (PSF) imager, an alignment system, a Leica Disto Pro distance measurement instrument, and a laser source palette (632.8 nm wavelength) that is fiber-coupled to the sensor instruments. All of the instruments except the laser source palette are located on a single breadboard known as the Wavefront Sensor Pallet (WSP). The WSP is located on top of a 5-DOF motion system located at the center of curvature of the test mirror. Two PC's are used to control the OTS. The error in the figure measurement is dominated by the WaveScope's measurement error. An analysis using the absolute wavefront gradient error of 1/50 wave P-V (at 0.6328 microns) provided by the manufacturer leads to a total surface figure measurement error of approximately 1/100 wave rms. This easily meets the requirement of 1/10 wave P-V. The error in radius of curvature is dominated by the Leica's absolute measurement error of VI.5 mm and the focus setting error of Vi.4 mm, giving an overall error of V2 mm. The OTS is currently being used to test the NGST Mirror System Demonstrators (NMSD's) and the Subscale Beryllium Mirror Demonstrator (SBNM).

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

DOEpatents

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Image processing for a tactile/vision substitution system using digital CNN.

PubMed

Lin, Chien-Nan; Yu, Sung-Nien; Hu, Jin-Cheng

2006-01-01

In view of the parallel processing and easy implementation properties of CNN, we propose to use digital CNN as the image processor of a tactile/vision substitution system (TVSS). The digital CNN processor is used to execute the wavelet down-sampling filtering and the half-toning operations, aiming to extract important features from the images. A template combination method is used to embed the two image processing functions into a single CNN processor. The digital CNN processor is implemented on an intellectual property (IP) and is implemented on a XILINX VIRTEX II 2000 FPGA board. Experiments are designated to test the capability of the CNN processor in the recognition of characters and human subjects in different environments. The experiments demonstrates impressive results, which proves the proposed digital CNN processor a powerful component in the design of efficient tactile/vision substitution systems for the visually impaired people.

Life sciences flight experiments microcomputer

NASA Technical Reports Server (NTRS)

Bartram, Peter N.

1987-01-01

A promising microcomputer configuration for the Spacelab Life Sciences Lab. Equipment inventory consists of multiple processors. One processor's use is reserved, with additional processors dedicated to real time input and output operations. A simple form of such a configuration, with a processor board for analog to digital conversion and another processor board for digital to analog conversion, was studied. The system used digital parallel data lines between the boards, operating independently of the system bus. Good performance of individual components was demonstrated: the analog to digital converter was at over 10,000 samples per second. The combination of the data transfer between boards with the input or output functions on each board slowed performance, with a maximum throughput of 2800 to 2900 analog samples per second. Any of several techniques, such as use of the system bus for data transfer or the addition of direct memory access hardware to the processor boards, should give significantly improved performance.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

DOEpatents

Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

2013-05-21

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Parallel machine architecture for production rule systems

DOEpatents

Allen, Jr., John D.; Butler, Philip L.

1989-01-01

A parallel processing system for production rule programs utilizes a host processor for storing production rule right hand sides (RHS) and a plurality of rule processors for storing left hand sides (LHS). The rule processors operate in parallel in the recognize phase of the system recognize -Act Cycle to match their respective LHS's against a stored list of working memory elements (WME) in order to find a self consistent set of WME's. The list of WME is dynamically varied during the Act phase of the system in which the host executes or fires rule RHS's for those rules for which a self-consistent set has been found by the rule processors. The host transmits instructions for creating or deleting working memory elements as dictated by the rule firings until the rule processors are unable to find any further self-consistent working memory element sets at which time the production rule system is halted.

Safe and Efficient Support for Embeded Multi-Processors in ADA

NASA Astrophysics Data System (ADS)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

Influence of dimethyl sulfoxide used as a solvent on the physical properties and long-term dentin bonding of hydrophilic resins.

PubMed

Stape, Thiago Henrique Scarabello; Tezvergil-Mutluay, Arzu; Mutluay, Mustafa Murat; Martins, Luís Roberto Marcondes; do Prado, Rosana Leal; Pizi, Eliane Cristina Gava; Tjäderhane, Leo

2016-12-01

To examine the feasibility of dimethyl sulfoxide (DMSO) incorporation into relatively hydrophilic resins as a new potential method to improve the durability of resin-dentin bonds. Six experimental light-curing BisGMA/HEMA resins solvated in ethanol and DMSO with increasing concentrations of DMSO (0, 0.5, 1, 2, 4 and 10wt%) were prepared. The degree of conversion (DC) was evaluated by Fourier Transform Infrared Spectroscopy (n=8); water sorption (Wsp) and water solubility (Wso) were gravimetrically assessed (n=10); and flexural strength (FS) and elastic modulus (E) were determined by a three-point bending flexural test (n=10). Flat dentin surfaces on sound third molars (n=10/group) were bonded with resins containing 0, 2, 4 and 10wt% DMSO used as a two-step etch-and-rinse system. Dentin microtensile bond strength was determined at 24h and after two-year aging in artificial saliva at 37°C. DMSO significantly affected Wsp (p=0.0006), DC, Wso, FS, and E (p<0.0001). In general, the resins' mechanical/physical properties were not affected by 2% or lower DMSO incorporation. Incorporation of 4% or higher DMSO content significantly increased DC, Wsp and Wso, but 2% or higher DMSO concentrations significantly reduced FS and E. No influence on immediate dentin bond strength occurred up to 4% DMSO incorporation. While 4% or higher DMSO concentrations impaired bond strength over time, the resin containing 2% DMSO presented significant higher dentin bond strength compared to the control resin after two year-aging. The use of DMSO as a new solvent in adhesive dentistry improves dentin bonding of relatively hydrophilic resins over time. 2% DMSO incorporation in BisGMA/HEMA resins should be sufficient to reduce bond strength loss without compromising polymer mechanical strength and physical properties. Copyright © 2016 Elsevier Ltd. All rights reserved.

Experimental based experiences with the introduction of a water safety plan for a multi-located university clinic and its efficacy according to WHO recommendations

PubMed Central

Dyck, Alexander; Exner, Martin; Kramer, Axel

2007-01-01

Background Due to the high number of immunosuppressed and other predisposed patients hospitals have to control and ensure the microbiological water quality. The origin for the occurrence of pathogenic microorganisms in water pipes is the formation of biofilm. Methods For the permanent control of water safety a water safety plan (WSP) was realized as recommended by the WHO following the principle "search and destroy". The WSP is based on an established HACCP concept due to the special focus. The most important measures include the concept for sample taking depending on patient risk. 3 different categories) are distinguished: risk area1 (high infection risk), risk 2 (moderate infection risk), and risk area 3 (not increased infection risk). Additionally to the threshold value of the German law for the quality of drinking water (TrinkwV) three more limiting values were defined (warning, alert, and worst case) for immediate risk adapted reaction. Additional attention has to be focussed on lavatory sinks, which are an open bacterial reservoir. Therefore continuous disinfecting siphons were installed as part of the WSP in high risk areas. If extended technical equipment is not available, especially for immunocompromised patients the following measures are easy to realize: boiled (or sun exposed) water for nursing procedures as well alimentary use, no showering. Results Comparing data over 3 years the microbial water quality was significantly improved resulting in no new case of nosocomial Legionella pneumoniae and decrease in neonatal sepsis. Conclusion According to average situations with highly contaminated water system the management must be defined with implementation of water task force, immediate providing of special equipment, information of patients and staff and control of the water quality, an example for successful decontamination of the hospital within 24 hours is given. PMID:17355621

System support software for the Space Ultrareliable Modular Computer (SUMC)

NASA Technical Reports Server (NTRS)

Hill, T. E.; Hintze, G. C.; Hodges, B. C.; Austin, F. A.; Buckles, B. P.; Curran, R. T.; Lackey, J. D.; Payne, R. E.

1974-01-01

The highly transportable programming system designed and implemented to support the development of software for the Space Ultrareliable Modular Computer (SUMC) is described. The SUMC system support software consists of program modules called processors. The initial set of processors consists of the supervisor, the general purpose assembler for SUMC instruction and microcode input, linkage editors, an instruction level simulator, a microcode grid print processor, and user oriented utility programs. A FORTRAN 4 compiler is undergoing development. The design facilitates the addition of new processors with a minimum effort and provides the user quasi host independence on the ground based operational software development computer. Additional capability is provided to accommodate variations in the SUMC architecture without consequent major modifications in the initial processors.

The implementation and use of Ada on distributed systems with reliability requirements

NASA Technical Reports Server (NTRS)

Reynolds, P. F.; Knight, J. C.; Urquhart, J. I. A.

1983-01-01

The issues involved in the use of the programming language Ada on distributed systems are discussed. The effects of Ada programs on hardware failures such as loss of a processor are emphasized. It is shown that many Ada language elements are not well suited to this environment. Processor failure can easily lead to difficulties on those processors which remain. As an example, the calling task in a rendezvous may be suspended forever if the processor executing the serving task fails. A mechanism for detecting failure is proposed and changes to the Ada run time support system are suggested which avoid most of the difficulties. Ada program structures are defined which allow programs to reconfigure and continue to provide service following processor failure.

Conditions for space invariance in optical data processors used with coherent or noncoherent light.

PubMed

Arsenault, H R

1972-10-01

The conditions for space invariance in coherent and noncoherent optical processors are considered. All linear optical processors are shown to belong to one of two types. The conditions for space invariance are more stringent for noncoherent processors than for coherent processors, so that a system that is linear in coherent light may be nonlinear in noncoherent light. However, any processor that is linear in noncoherent light is also linear in the coherent limit.

Variable word length encoder reduces TV bandwith requirements

NASA Technical Reports Server (NTRS)

Sivertson, W. E., Jr.

1965-01-01

Adaptive variable resolution encoding technique provides an adaptive compression pseudo-random noise signal processor for reducing television bandwidth requirements. Complementary processors are required in both the transmitting and receiving systems. The pretransmission processor is analog-to-digital, while the postreception processor is digital-to-analog.

Internal desynchronization in a model of night-work by forced activity in rats.

PubMed

Salgado-Delgado, R; Angeles-Castellanos, M; Buijs, M R; Escobar, C

2008-06-26

Individuals engaged in shift- or night-work show disturbed diurnal rhythms, out of phase with temporal signals associated to the light/dark (LD) cycle, resulting in internal desynchronization. The mechanisms underlying internal desynchrony have been mainly investigated in experimental animals with protocols that induce phase shifts of the LD cycle and thus modify the activity of the suprachiasmatic nucleus (SCN). In this study we developed an animal model of night-work in which the light-day cycle remained stable and rats were required to be active in a rotating wheel for 8 h daily during their sleeping phase (W-SP). This group was compared with rats that were working in the wheel during their activity phase (W-AP) and with undisturbed rats (C). We provide evidence that forced activity during the sleeping phase (W-SP group) alters not only activity, but also the temporal pattern of food intake. In consequence W-SP rats showed a loss of glucose rhythmicity and a reversed rhythm of triacylglycerols. In contrast W-AP rats did not show such changes and exhibited metabolic rhythms similar to those of the controls. The three groups exhibited the nocturnal corticosterone increase, in addition the W-SP and W-AP groups showed increase of plasma corticosterone associated with the start of the working session. Forced activity during the sleep phase did not modify SCN activity characterized by the temporal patterns of PER1 and PER2 proteins, which remained in phase with the LD cycle. These observations indicate that a working regimen during the sleeping period elicits internal desynchronization in which activity combined with feeding uncouples metabolic functions from the biological clock which remains fixed to the LD cycle. The present data suggest that in the night worker the combination of work and eating during working hours may be the cause of internal desynchronization.

Evaluation of a Final Year Work-shadowing Attachment

PubMed Central

McKavanagh, Peter; Boohan, Mairead; Savage, Maurice; McCluskey, David; McKeown, Pascal

2012-01-01

The transition from medical student to junior doctor is well recognised to be a difficult and stressful period. To ease this transition, most UK universities have a work-shadowing period (WSP), during which students can learn practical skills needed for forthcoming employment. The aim of this study was to evaluate the WSP at Queen’s University Belfast, and gain the views of both students and Foundation Programme Supervisors and Directors (FPSDs). The study utilised both qualitative (focus groups) and quantitative (questionnaires) approaches. The FPSDs completed a specific questionnaire designed for this study, while the students completed the university’s internal quality assurance questionnaire. Twenty-eight of the 37 (76%) FPSDs and 106 / 196 (54%) students completed the questionnaires. Focus groups were conducted with up to 10 students in each group in both a regional centre and a district general hospital at the start and the end of the WSP as well as 8 weeks into working life. The transcripts of the focus groups were analysed and themes identified. A number of deficiencies with the current WSP were identified, including concerns about the use of log books, the timing of the attachment and relatively low levels of supervision provided by senior hospital staff members. As a result, students felt unprepared for commencing work, with particular mention given to medical emergencies, prescribing, and the emotional aspects of the job. A number of recommendations are made, including the need for more senior input to ensure better student attendance, participation and clinical interaction. Furthermore, students should be offered additional supervised responsibility for delivery of patient care and more experiential learning with respect to drug prescribing and administration. The study also suggests that more needs to be done to help ease the emotional and psychological stresses of the early FY1 period. These issues have been resolved to a large extent with the introduction of the new final year Student Assistantship module in the academic year 2010-2011. PMID:23526851

What aspect of dietary modification in broilers controls litter water-soluble phosphorus: dietary phosphorus, phytase, or calcium?

PubMed

Leytem, A B; Plumstead, P W; Maguire, R O; Kwanyuen, P; Brake, J

2007-01-01

Environmental concerns about phosphorus (P) losses from animal agriculture have led to interest in dietary strategies to reduce the concentration and solubility of P in manures and litters. To address the effects of dietary available phosphorus (AvP), calcium (Ca), and phytase on P excretion in broilers, 18 dietary treatments were applied in a randomized complete block design to each of four replicate pens of 28 broilers from 18 to 42 d of age. Treatments consisted of three levels of AvP (3.5, 3.0, and 2.5 g kg(-1)) combined with three levels of Ca (8.0, 6.9, and 5.7 g kg(-1)) and two levels of phytase (0 and 600 phytase units [FTU]). Phytase was added at the expense of 1.0 g kg(-1) P from dicalcium phosphate. Fresh litter was collected from pens when the broilers were 41 d of age and analyzed for total P, soluble P, and phytate P as well as P composition by (31)P nuclear magnetic resonance (NMR) spectroscopy. Results indicated that the inclusion of phytase at the expense of inorganic P or reductions in AvP decreased litter total P by 28 to 43%. Litter water-soluble P (WSP) decreased by up to 73% with an increasing dietary Ca/AvP ratio, irrespective of phytase addition. The ratio of WSP/total P in litter decreased as the dietary Ca/AvP ratio increased and was greater in the phytase-amended diets. This study indicated that while feeding reduced AvP diets with phytase decreased litter total P, the ratio of Ca/AvP in the diet was primarily responsible for effects on WSP. This is important from an environmental perspective as the amount of WSP in litter could be related to potential for off-site P losses following land application of litter.

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

PubMed

Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

2013-01-01

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

Effects of input processing and type of personal frequency modulation system on speech-recognition performance of adults with cochlear implants.

PubMed

Wolfe, Jace; Schafer, Erin; Parkinson, Aaron; John, Andrew; Hudson, Mary; Wheeler, Julie; Mucci, Angie

2013-01-01

The objective of this study was to compare speech recognition in quiet and in noise for cochlear implant recipients using two different types of personal frequency modulation (FM) systems (directly coupled [direct auditory input] versus induction neckloop) with each of two sound processors (Cochlear Nucleus Freedom versus Cochlear Nucleus 5). Two different experiments were conducted within this study. In both these experiments, mixing of the FM signal within the Freedom processor was implemented via the same scheme used clinically for the Freedom sound processor. In Experiment 1, the aforementioned comparisons were conducted with the Nucleus 5 programmed so that the microphone and FM signals were mixed and then the mixed signals were subjected to autosensitivity control (ASC). In Experiment 2, comparisons between the two FM systems and processors were conducted again with the Nucleus 5 programmed to provide a more complex multistage implementation of ASC during the preprocessing stage. This study was a within-subject, repeated-measures design. Subjects were recruited from the patient population at the Hearts for Hearing Foundation in Oklahoma City, OK. Fifteen subjects participated in Experiment 1, and 16 subjects participated in Experiment 2. Subjects were adults who had used either unilateral or bilateral cochlear implants for at least 1 year. In this experiment, no differences were found in speech recognition in quiet obtained with the two different FM systems or the various sound-processor conditions. With each sound processor, speech recognition in noise was better with the directly coupled direct auditory input system relative to the neckloop system. The multistage ASC processing of the Nucleus 5 sound processor provided better performance than the single-stage approach for the Nucleus 5 and the Nucleus Freedom sound processor. Speech recognition in noise is substantially affected by the type of sound processor, FM system, and implementation of ASC used by a Cochlear implant recipient.

Simulation of a master-slave event set processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comfort, J.C.

1984-03-01

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. The paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principal processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation program modeling this system was constructed, and was run with tracemore » output taken from two different simulation programs. Output from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and interprocessor communication times). A comparison between actual and simulation run times for a one-processor system was used to assist in the validation of the simulation. 7 references.« less

State recovery and lockstep execution restart in a system with multiprocessor pairing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switchmore » or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.« less

System-wide power management control via clock distribution network

DOEpatents

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

2015-05-19

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Scheduler for multiprocessor system switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael Karl; Salapura, Valentina

2015-01-06

System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

System and method for controlling power consumption in a computer system based on user satisfaction

DOEpatents

Yang, Lei; Dick, Robert P; Chen, Xi; Memik, Gokhan; Dinda, Peter A; Shy, Alex; Ozisikyilmaz, Berkin; Mallik, Arindam; Choudhary, Alok

2014-04-22

Systems and methods for controlling power consumption in a computer system. For each of a plurality of interactive applications, the method changes a frequency at which a processor of the computer system runs, receives an indication of user satisfaction, determines a relationship between the changed frequency and the user satisfaction of the interactive application, and stores the determined relationship information. The determined relationship can distinguish between different users and different interactive applications. A frequency may be selected from the discrete frequencies at which the processor of the computer system runs based on the determined relationship information for a particular user and a particular interactive application running on the processor of the computer system. The processor may be adapted to run at the selected frequency.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

A Trade Study of Two Membrane-Aerated Biological Water Processors

NASA Technical Reports Server (NTRS)

Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

2011-01-01

Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

On board processor development for NASA's spaceborne imaging radar with system-on-chip technology

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

2004-01-01

This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with system-on-chip technology. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.

Hybrid Electro-Optic Processor

DTIC Science & Technology

1991-07-01

This report describes the design of a hybrid electro - optic processor to perform adaptive interference cancellation in radar systems. The processor is...modulator is reported. Included is this report is a discussion of the design, partial fabrication in the laboratory, and partial testing of the hybrid electro ... optic processor. A follow on effort is planned to complete the construction and testing of the processor. The work described in this report is the

FPGA-Based Multiprocessor System for Injection Molding Control

PubMed Central

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

2012-01-01

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

The 3D laser radar vision processor system

NASA Astrophysics Data System (ADS)

Sebok, T. M.

1990-10-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

The 3D laser radar vision processor system

NASA Technical Reports Server (NTRS)

Sebok, T. M.

1990-01-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

A wideband software reconfigurable modem

NASA Astrophysics Data System (ADS)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

A High Performance VLSI Computer Architecture For Computer Graphics

NASA Astrophysics Data System (ADS)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

System on a chip with MPEG-4 capability

NASA Astrophysics Data System (ADS)

Yassa, Fathy; Schonfeld, Dan

2002-12-01

Current products supporting video communication applications rely on existing computer architectures. RISC processors have been used successfully in numerous applications over several decades. DSP processors have become ubiquitous in signal processing and communication applications. Real-time applications such as speech processing in cellular telephony rely extensively on the computational power of these processors. Video processors designed to implement the computationally intensive codec operations have also been used to address the high demands of video communication applications (e.g., cable set-top boxes and DVDs). This paper presents an overview of a system-on-chip (SOC) architecture used for real-time video in wireless communication applications. The SOC specifications answer to the system requirements imposed by the application environment. A CAM-based video processor is used to accelerate data intensive video compression tasks such as motion estimations and filtering. Other components are dedicated to system level data processing and audio processing. A rich set of I/Os allows the SOC to communicate with other system components such as baseband and memory subsystems.

Transient Finite Element Computations on a Variable Transputer System

NASA Technical Reports Server (NTRS)

Smolinski, Patrick J.; Lapczyk, Ireneusz

1993-01-01

A parallel program to analyze transient finite element problems was written and implemented on a system of transputer processors. The program uses the explicit time integration algorithm which eliminates the need for equation solving, making it more suitable for parallel computations. An interprocessor communication scheme was developed for arbitrary two dimensional grid processor configurations. Several 3-D problems were analyzed on a system with a small number of processors.

Next Generation Security for the 10,240 Processor Columbia System

NASA Technical Reports Server (NTRS)

Hinke, Thomas; Kolano, Paul; Shaw, Derek; Keller, Chris; Tweton, Dave; Welch, Todd; Liu, Wen (Betty)

2005-01-01

This presentation includes a discussion of the Columbia 10,240-processor system located at the NASA Advanced Supercomputing (NAS) division at the NASA Ames Research Center which supports each of NASA's four missions: science, exploration systems, aeronautics, and space operations. It is comprised of 20 Silicon Graphics nodes, each consisting of 512 Itanium II processors. A 64 processor Columbia front-end system supports users as they prepare their jobs and then submits them to the PBS system. Columbia nodes and front-end systems use the Linux OS. Prior to SC04, the Columbia system was used to attain a processing speed of 51.87 TeraFlops, which made it number two on the Top 500 list of the world's supercomputers and the world's fastest "operational" supercomputer since it was fully engaged in supporting NASA users.

Efficiency of static core turn-off in a system-on-a-chip with variation

DOEpatents

Cher, Chen-Yong; Coteus, Paul W; Gara, Alan; Kursun, Eren; Paulsen, David P; Schuelke, Brian A; Sheets, II, John E; Tian, Shurong

2013-10-29

A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

Effect of poor control of film processors on mammographic image quality.

PubMed

Kimme-Smith, C; Sun, H; Bassett, L W; Gold, R H

1992-11-01

With the increasingly stringent standards of image quality in mammography, film processor quality control is especially important. Current methods are not sufficient for ensuring good processing. The authors used a sensitometer and densitometer system to evaluate the performance of 22 processors at 16 mammographic facilities. Standard sensitometric values of two films were established, and processor performance was assessed for variations from these standards. Developer chemistry of each processor was analyzed and correlated with its sensitometric values. Ten processors were retested, and nine were found to be out of calibration. The developer components of hydroquinone, sulfites, bromide, and alkalinity varied the most, and low concentrations of hydroquinone were associated with lower average gradients at two facilities. Use of the sensitometer and densitometer system helps identify out-of-calibration processors, but further study is needed to correlate sensitometric values with developer component values. The authors believe that present quality control would be improved if sensitometric or other tests could be used to identify developer components that are out of calibration.

A high-accuracy optical linear algebra processor for finite element applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Effects of different temperature regimes on survival of Diaphorina citri and its endosymbiotic bacterial communities.

PubMed

Hussain, Mubasher; Akutse, Komivi Senyo; Ravindran, Keppanan; Lin, Yongwen; Bamisile, Bamisope Steve; Qasim, Muhammad; Dash, Chandra Kanta; Wang, Liande

2017-09-01

The Asian citrus psyllid, Diaphorina citri, is a major pest of citrus and vector of citrus greening (huanglongbing) in Asian. In our field-collected psyllid samples, we discovered that Fuzhou (China) and Faisalabad (Pakistan), populations harbored an obligate primary endosymbiont Candidatus Carsonella (gen. nov.) with a single species, Candidatus Carsonella ruddii (sp. nov.) and a secondary endosymbiont, Wolbachia surface proteins (WSP) which are intracellular endosymbionts residing in the bacteriomes. Responses of these symbionts to different temperatures were examined and their host survival assessed. Diagnostic PCR assays showed that the endosymbionts infection rates were not significantly reduced in both D. citri populations after 24 h exposure to cold or heat treatments. Although quantitative PCR assays showed significant reduction of WSP relative densities at 40°C for 24 h, a substantial decrease occurred as the exposure duration increased beyond 3 days. Under the same temperature regimes, Ca. C. ruddii density was initially less affected during the first exposure day, but rapidly reduced at 3-5 days compared to WSP. However, the mortality of the psyllids increased rapidly as exposure time to heat treatment increased. The responses of the two symbionts to unfavorable temperature regimes highlight the complex host-symbionts interactions between D. citri and its associated endosymbionts. © 2017 Society for Applied Microbiology and John Wiley & Sons Ltd.

Estimation of the degree of soil P saturation from Brazilian Mehlich-1 P data and field investigations on P losses from agricultural sites in Minas Gerais.

PubMed

Fischer, P; Pöthig, R; Gücker, B; Venohr, M

The degree of phosphorus saturation (DPS) of agricultural soils is studied worldwide for risk assessment of phosphorus (P) losses. In previous studies, DPS could be reliably estimated from water-soluble P (WSP) for European and Brazilian soils. In the present study, we correlated measured WSP and Mehlich-1 P (M1P) from soils of Minas Gerais (MG) and Pernambuco (PE) (R(2) = 0.94, n = 59) to create a DPS map from monitoring data. The resulting DPS map showed high spatial variability and low values of DPS (54 ± 22%, mean and standard deviation; n = 1,827). Measured soil DPS values amounted to 63 ± 14% and resulted in relatively low dissolved P concentrations measured in a surface runoff study in MG. However, fertilizer grains on the soil surface led to high WSP values (>30 mg/kg) indicating high risks of dissolved P losses. We suppose that small Oxisol particles with Fe and Al hydroxides sorbed most of the dissolved fertilizer P in runoff so that P was mainly exported in particulate form. In soils with lower contents of P sorption and binding partners, e.g. Entisols in PE, this effect may be less dominant. Consequently, superficial fertilizer effects have to be considered in addition to DPS in risk assessment of P losses from agricultural areas in Brazil.

The effects of gamma irradiation on the microbiological, physical and sensory qualities of diced tomatoes

NASA Astrophysics Data System (ADS)

Prakash, Anuradha; Manley, Jacqueline; DeCosta, Suresh; Caporaso, Fred; Foley, Denise

2002-03-01

Diced Roma tomatoes were treated with gamma irradiation and evaluated for changes in microbial, physical, chemical and sensory properties. Dosages for Trial 1 were 0.0, 0.39, 0.56 and 1.82 kGy and in Trial 2, 0.0, 0.50, 1.24 and 3.70 kGy. Irradiation at 3.70 kGy resulted in no aerobic populations through day 12 and significantly fewer colonies through day 15 whereas yeast and mold populations experienced a 2 log reduction through day 12. Color, titratable acidity, and °Brix were not significantly affected by irradiation. Tissue firmness decreased with increasing dose but not with storage time. Treatment with 3.7 kGy decreased firmness by 50% and 20% with 0.5 kGy, however, the reduced firmness induced by 0.50 kGy was undetected by a 9 member trained sensory panel. A significant ( p⩽0.05) inverse correlation between changes in texture and water-soluble pectin (WSP) was determined while total pectin remained relatively constant and oxalate soluble pectin content decreased slightly with irradiation dose. The significant inverse correlation between the loss of firmness and WSP indicates that the changes in WSP play an important role in the tissue softening of tomatoes, This study indicates that irradiation at 0.5 kGy can reduce microbial counts substantially to improve microbial shelf life without adverse effects on sensory qualities.

Effects of Inhibitors of [Delta]24(25)-Sterol Methyl Transferase on the Ultrastructure of Epimastigotes of Trypanosoma cruzi

NASA Astrophysics Data System (ADS)

Braga, Marina V.; Magaraci, Filippo; Orenes Lorente, Silvia; Gilbert, Ian; de Souza, Wanderley

2005-12-01

Trypanosoma cruzi is the ethiological agent of Chagas disease. New compounds are being developed based on the biosynthesis and function of sterols, because T. cruzi has a requirement for specific endogenous sterols for growth and survival. Sterol biosynthesis inhibitors (SBIs) are drugs commonly used against fungal diseases. These drugs act by depleting essential and specific membrane components and/or inducing the accumulation of toxic intermediary or lateral products of the biosynthetic pathway. In this work we present the effects of WSP488, WSP501, and WSP561, specific inhibitors of [Delta]24(25)-sterol methyl transferase, on the ultrastructure of T. cruzi epimastigotes. All three drugs inhibited parasite multiplication at low concentrations, with IC50 values of 0.48, 0.44, and 0.48 [mu]M, respectively, and induced marked morphological changes including (a) blockage of cell division; (b) swelling of the mitochondrion, with several projections and depressions; (c) swelling of the perinuclear space; (d) presence of autophagosomes and myelin-like figures; (e) enlargement of the flagellar pocket and of a cytoplasmic vacuole located in close association with the flagellar pocket; (f) detachment of the membrane of the cell body; and (g) formation of a vesicle at the surface of the parasite between the flagellar pocket and the cytostome. Our results show that these drugs are potent in vitro inhibitors of growth of T. cruzi.

Preliminary study on the potential usefulness of array processor techniques for structural synthesis

NASA Technical Reports Server (NTRS)

Feeser, L. J.

1980-01-01

The effects of the use of array processor techniques within the structural analyzer program, SPAR, are simulated in order to evaluate the potential analysis speedups which may result. In particular the connection of a Floating Point System AP120 processor to the PRIME computer is discussed. Measurements of execution, input/output, and data transfer times are given. Using these data estimates are made as to the relative speedups that can be executed in a more complete implementation on an array processor maxi-mini computer system.

Stateless and stateful implementations of faithful execution

DOEpatents

Pierson, Lyndon G; Witzke, Edward L; Tarman, Thomas D; Robertson, Perry J; Eldridge, John M; Campbell, Philip L

2014-12-16

A faithful execution system includes system memory, a target processor, and protection engine. The system memory stores a ciphertext including value fields and integrity fields. The value fields each include an encrypted executable instruction and the integrity fields each include an encrypted integrity value for determining whether a corresponding one of the value fields has been modified. The target processor executes plaintext instructions decoded from the ciphertext while the protection engine is coupled between the system memory and the target processor. The protection engine includes logic to retrieve the ciphertext from the system memory, decrypt the value fields into the plaintext instructions, perform an integrity check based on the integrity fields to determine whether any of the corresponding value fields have been modified, and provide the plaintext instructions to the target processor for execution.

78 FR 21483 - Joint Industry Plan; Order Approving the Third Amendment to the National Market System Plan to...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-10

... the Securities Information Processors (``SIPs'' or ``Processors'') responsible for consolidation of... Plan. \\9\\ 17 CFR 242.603(b). The Plan refers to this entity as the Processor. \\10\\ See Section I(T) of... Euronext, to Elizabeth M. Murphy, Secretary, Commission, dated May 24, 2012. The Processors would also...

Simulating Synchronous Processors

DTIC Science & Technology

1988-06-01

34f Fvtvru m LABORATORY FOR INMASSACHUSETTSFCOMPUTER SCIENCE TECHNOLOGY MIT/LCS/TM-359 SIMULATING SYNCHRONOUS PROCESSORS Jennifer Lundelius Welch...PROJECT TASK WORK UNIT Arlington, VA 22217 ELEMENT NO. NO. NO ACCESSION NO. 11. TITLE Include Security Classification) Simulating Synchronous Processors...necessary and identify by block number) In this paper we show how a distributed system with synchronous processors and asynchro- nous message delays can

Parallel processing in a host plus multiple array processor system for radar

NASA Technical Reports Server (NTRS)

Barkan, B. Z.

1983-01-01

Host plus multiple array processor architecture is demonstrated to yield a modular, fast, and cost-effective system for radar processing. Software methodology for programming such a system is developed. Parallel processing with pipelined data flow among the host, array processors, and discs is implemented. Theoretical analysis of performance is made and experimentally verified. The broad class of problems to which the architecture and methodology can be applied is indicated.

Impact of sludge layer geometry on the hydraulic performance of a waste stabilization pond.

PubMed

Ouedraogo, Faissal R; Zhang, Jie; Cornejo, Pablo K; Zhang, Qiong; Mihelcic, James R; Tejada-Martinez, Andres E

2016-08-01

Improving the hydraulic performance of waste stabilization ponds (WSPs) is an important management strategy to not only ensure protection of public health and the environment, but also to maximize the potential reuse of valuable resources found in the treated effluent. To reuse effluent from WSPs, a better understanding of the factors that impact the hydraulic performance of the system is needed. One major factor determining the hydraulic performance of a WSP is sludge accumulation, which alters the volume of the pond. In this study, computational fluid dynamics (CFD) analysis was applied to investigate the impact of sludge layer geometry on hydraulic performance of a facultative pond, typically used in many small communities throughout the developing world. Four waste stabilization pond cases with different sludge volumes and distributions were investigated. Results indicate that sludge distribution and volume have a significant impact on wastewater treatment efficiency and capacity. Although treatment capacity is reduced with accumulation of sludge, the latter may induce a baffling effect which causes the flow to behave closer to that of plug flow reactor and thus increase treatment efficiency. In addition to sludge accumulation and distribution, the impact of water surface level is also investigated through two additional cases. Findings show that an increase in water level while keeping a constant flow rate can result in a significant decrease in the hydraulic performance by reducing the sludge baffling effect, suggesting a careful monitoring of sludge accumulation and water surface level in WSP systems. Published by Elsevier Ltd.

System and method for memory allocation in a multiclass memory system

DOEpatents

Loh, Gabriel; Meswani, Mitesh; Ignatowski, Michael; Nutter, Mark

2016-06-28

A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

Architectures for reasoning in parallel

NASA Technical Reports Server (NTRS)

Hall, Lawrence O.

1989-01-01

The research conducted has dealt with rule-based expert systems. The algorithms that may lead to effective parallelization of them were investigated. Both the forward and backward chained control paradigms were investigated in the course of this work. The best computer architecture for the developed and investigated algorithms has been researched. Two experimental vehicles were developed to facilitate this research. They are Backpac, a parallel backward chained rule-based reasoning system and Datapac, a parallel forward chained rule-based reasoning system. Both systems have been written in Multilisp, a version of Lisp which contains the parallel construct, future. Applying the future function to a function causes the function to become a task parallel to the spawning task. Additionally, Backpac and Datapac have been run on several disparate parallel processors. The machines are an Encore Multimax with 10 processors, the Concert Multiprocessor with 64 processors, and a 32 processor BBN GP1000. Both the Concert and the GP1000 are switch-based machines. The Multimax has all its processors hung off a common bus. All are shared memory machines, but have different schemes for sharing the memory and different locales for the shared memory. The main results of the investigations come from experiments on the 10 processor Encore and the Concert with partitions of 32 or less processors. Additionally, experiments have been run with a stripped down version of EMYCIN.

Parallel processing data network of master and slave transputers controlled by a serial control network

DOEpatents

Crosetto, D.B.

1996-12-31

The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor to a plurality of slave processors to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor`s status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer, a digital signal processor, a parallel transfer controller, and two three-port memory devices. A communication switch within each node connects it to a fast parallel hardware channel through which all high density data arrives or leaves the node. 6 figs.

A word processor optimized for preparing journal articles and student papers.

PubMed

Wolach, A H; McHale, M A

2001-11-01

A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

An Efficient Solution Method for Multibody Systems with Loops Using Multiple Processors

NASA Technical Reports Server (NTRS)

Ghosh, Tushar K.; Nguyen, Luong A.; Quiocho, Leslie J.

2015-01-01

This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called "branches" at convenient joints called "connection points", and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

Method and system for selecting data sampling phase for self timed interface logic

DOEpatents

Hoke, Joseph Michael; Ferraiolo, Frank D.; Lo, Tin-Chee; Yarolin, John Michael

2005-01-04

An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

Broadcasting collective operation contributions throughout a parallel computer

DOEpatents

Faraj, Ahmad [Rochester, MN

2012-02-21

Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications.

RTEMS SMP and MTAPI for Efficient Multi-Core Space Applications on LEON3/LEON4 Processors

NASA Astrophysics Data System (ADS)

Cederman, Daniel; Hellstrom, Daniel; Sherrill, Joel; Bloom, Gedare; Patte, Mathieu; Zulianello, Marco

2015-09-01

This paper presents the final result of an European Space Agency (ESA) activity aimed at improving the software support for LEON processors used in SMP configurations. One of the benefits of using a multicore system in a SMP configuration is that in many instances it is possible to better utilize the available processing resources by load balancing between cores. This however comes with the cost of having to synchronize operations between cores, leading to increased complexity. While in an AMP system one can use multiple instances of operating systems that are only uni-processor capable, a SMP system requires the operating system to be written to support multicore systems. In this activity we have improved and extended the SMP support of the RTEMS real-time operating system and ensured that it fully supports the multicore capable LEON processors. The targeted hardware in the activity has been the GR712RC, a dual-core core LEON3FT processor, and the functional prototype of ESA's Next Generation Multiprocessor (NGMP), a quad core LEON4 processor. The final version of the NGMP is now available as a product under the name GR740. An implementation of the Multicore Task Management API (MTAPI) has been developed as part of this activity to aid in the parallelization of applications for RTEMS SMP. It allows for simplified development of parallel applications using the task-based programming model. An existing space application, the Gaia Video Processing Unit, has been ported to RTEMS SMP using the MTAPI implementation to demonstrate the feasibility and usefulness of multicore processors for space payload software. The activity is funded by ESA under contract 4000108560/13/NL/JK. Gedare Bloom is supported in part by NSF CNS-0934725.

Interpreter composition issues in the formal verification of a processor-memory module

NASA Technical Reports Server (NTRS)

Fura, David A.; Cohen, Gerald C.

1994-01-01

This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.

The application of charge-coupled device processors in automatic-control systems

NASA Technical Reports Server (NTRS)

Mcvey, E. S.; Parrish, E. A., Jr.

1977-01-01

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

Input data requirements for special processors in the computation system containing the VENTURE neutronics code. [LMFBR

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vondy, D.R.; Fowler, T.B.; Cunningham, G.W.

1979-07-01

User input data requirements are presented for certain special processors in a nuclear reactor computation system. These processors generally read data in formatted form and generate binary interface data files. Some data processing is done to convert from the user oriented form to the interface file forms. The VENTURE diffusion theory neutronics code and other computation modules in this system use the interface data files which are generated.

Software Coherence in Multiprocessor Memory Systems. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Bolosky, William Joseph

1993-01-01

Processors are becoming faster and multiprocessor memory interconnection systems are not keeping up. Therefore, it is necessary to have threads and the memory they access as near one another as possible. Typically, this involves putting memory or caches with the processors, which gives rise to the problem of coherence: if one processor writes an address, any other processor reading that address must see the new value. This coherence can be maintained by the hardware or with software intervention. Systems of both types have been built in the past; the hardware-based systems tended to outperform the software ones. However, the ratio of processor to interconnect speed is now so high that the extra overhead of the software systems may no longer be significant. This issue is explored both by implementing a software maintained system and by introducing and using the technique of offline optimal analysis of memory reference traces. It finds that in properly built systems, software maintained coherence can perform comparably to or even better than hardware maintained coherence. The architectural features necessary for efficient software coherence to be profitable include a small page size, a fast trap mechanism, and the ability to execute instructions while remote memory references are outstanding.

System balance analysis for vector computers

NASA Technical Reports Server (NTRS)

Knight, J. C.; Poole, W. G., Jr.; Voight, R. G.

1975-01-01

The availability of vector processors capable of sustaining computing rates of 10 to the 8th power arithmetic results pers second raised the question of whether peripheral storage devices representing current technology can keep such processors supplied with data. By examining the solution of a large banded linear system on these computers, it was found that even under ideal conditions, the processors will frequently be waiting for problem data.

A microprocessor based high speed packet switch for satellite communications

NASA Technical Reports Server (NTRS)

Arozullah, M.; Crist, S. C.

1980-01-01

The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.

A digital retina-like low-level vision processor.

PubMed

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Design and Analysis of Scheduling Policies for Real-Time Computer Systems

DTIC Science & Technology

1992-01-01

C. M. Krishna, "The Impact of Workload on the Reliability of Real-Time Processor Triads," to appear in Micro . Rel. [17] J.F. Kurose, "Performance... Processor Triads", to appear in Micro . Rel. "* J.F. Kurose. "Performance Analysis of Minimum Laxity Scheduling in Discrete Time Queue- ing Systems", to...exponentially distributed service times and deadlines. A similar model was developed for the ED policy for a single processor system under identical

Backend Control Processor for a Multi-Processor Relational Database Computer System.

DTIC Science & Technology

1984-12-01

SCHOOL OF ENGI. UNCRSIFID MPONTIFF DEC 84 AFXT/GCS/ENG/84D-22 F/O 9/2 L ommhhhhmhhml mhhhommhhhhhm i-2 8 -- U0. 11111= Q. 2 111.8IIII- 1111111..6...THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of Technology Air University In Partial Fulfillment of the...development of a Backend Multi-Processor Relational Database Computer System. This thesis addresses a single component of this system, the Backend Control

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Ordering of guarded and unguarded stores for no-sync I/O

DOEpatents

Gara, Alan; Ohmacht, Martin

2013-06-25

A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.

30/20 GHz communications systems baseband processor development

NASA Astrophysics Data System (ADS)

Brown, L.; Sabourin, D.; Stilwell, J.; McCallister, R.; Borota, M.

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

30/20 GHz communications systems baseband processor development

NASA Technical Reports Server (NTRS)

Brown, L.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

Method for simultaneous overlapped communications between neighboring processors in a multiple

DOEpatents

Benner, Robert E.; Gustafson, John L.; Montry, Gary R.

1991-01-01

A parallel computing system and method having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system.

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

PubMed

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Communications systems and methods for subsea processors

DOEpatents

Gutierrez, Jose; Pereira, Luis

2016-04-26

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

WCATS: Waste Documentation, Course No. 8504

DOE Office of Scientific and Technical Information (OSTI.GOV)

Simpson, Sandy

2016-04-14

This course was developed for individuals at Los Alamos National Laboratory (LANL) who characterize and document waste streams in the Waste Compliance and Tracking System (WCATS) according to Environmental Protection Agency (EPA) Department of Transportation (DOT) regulations, Department of Energy Orders, and other applicable criteria. When you have completed this course, you will be able to recognize how waste documentation enables LANL to characterize and classify hazardous waste for compliant treatment, storage, and disposal, identify the purpose of the waste stream profile (WSP), identify the agencies that provide guidance for waste management, and more.

Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crosetto, Dario B.

1998-10-30

The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelfmore » FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.« less

When emotionality trumps reason: a study of individual processing style and juror bias.

PubMed

Gunnell, Justin J; Ceci, Stephen J

2010-01-01

"Cognitive Experiential Self Theory" (CEST) postulates that information-processing proceeds through two pathways, a rational one and an experiential one. The former is characterized by an emphasis on analysis, fact, and logical argument, whereas the latter is characterized by emotional and personal experience. We examined whether individuals influenced by the experiential system (E-processors) are more susceptible to extralegal biases (e.g. defendant attractiveness) than those influenced by the rational system (R-processors). Participants reviewed a criminal trial transcript and defendant profile and determined verdict, sentencing, and extralegal susceptibility. Although E-processors and R-processors convicted attractive defendants at similar rates, E-processors were more likely to convict less attractive defendants. Whereas R-processors did not sentence attractive and less attractive defendants differently, E-processors gave more lenient sentences to attractive defendants and harsher sentences to less attractive defendants. E-processors were also more likely to report that extralegal factors would change their verdicts. Further, the degree to which emotionality trumped rationality within an individual, as measured by a novel scoring method, linearly correlated with harsher sentences and extralegal influence. In sum, the results support an "unattractive harshness" effect during guilt determination, an attraction leniency effect during sentencing and increased susceptibility to extralegal factors within E-processors. Copyright © 2010 John Wiley & Sons, Ltd. Copyright © 2010 John Wiley & Sons, Ltd.

Soft-core processor study for node-based architectures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James

2008-09-01

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor builtmore » out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.« less

Stencils and problem partitionings: Their influence on the performance of multiple processor systems

NASA Technical Reports Server (NTRS)

Reed, D. A.; Adams, L. M.; Patrick, M. L.

1986-01-01

Given a discretization stencil, partitioning the problem domain is an important first step for the efficient solution of partial differential equations on multiple processor systems. Partitions are derived that minimize interprocessor communication when the number of processors is known a priori and each domain partition is assigned to a different processor. This partitioning technique uses the stencil structure to select appropriate partition shapes. For square problem domains, it is shown that non-standard partitions (e.g., hexagons) are frequently preferable to the standard square partitions for a variety of commonly used stencils. This investigation is concluded with a formalization of the relationship between partition shape, stencil structure, and architecture, allowing selection of optimal partitions for a variety of parallel systems.

The Event Based Language and Its Multiple Processor Implementations.

DTIC Science & Technology

1980-01-01

10 6.1 "Recursive" Linear Fibonacci ................................................ 105 6.2 The Readers Writers Problem...kinds. Examples of such systems are: C.mmp [Wu-72], Pluribus [He-73], Data Flow [ De -75], the boolean n-cube parallel machine [Su-77], and the MuNet [Wa...concurrency within programs; therefore, we hate concentrated on two types of systems which seem suitable: a processor network, and a data flow processor [ De -77

JPRS Report, Science & Technology, China, High-Performance Computer Systems

DTIC Science & Technology

1992-10-28

microprocessor array The microprocessor array in the AP85 system is com- posed of 16 completely identical array element micro - processors . Each array element...microprocessors and capable of host machine reading and writing. The memory capacity of the array element micro - processors as a whole can be expanded...transmission functions to carry out data transmission from array element micro - processor to array element microprocessor, from array element

Design for a Manufacturing Method for Memristor-Based Neuromorphic Computing Processors

DTIC Science & Technology

2013-03-01

DESIGN FOR A MANUFACTURING METHOD FOR MEMRISTOR- BASED NEUROMORPHIC COMPUTING PROCESSORS UNIVERSITY OF PITTSBURGH MARCH 2013...BASED NEUROMORPHIC COMPUTING PROCESSORS 5a. CONTRACT NUMBER FA8750-11-1-0271 5b. GRANT NUMBER N/A 5c. PROGRAM ELEMENT NUMBER 62788F 6. AUTHOR(S...synapses and implemented a neuromorphic computing system based on our proposed synapse designs. The robustness of our system is also evaluated by

Radio astronomy Explorer B antenna aspect processor

NASA Technical Reports Server (NTRS)

Miller, W. H.; Novello, J.; Reeves, C. C.

1972-01-01

The antenna aspect system used on the Radio Astronomy Explorer B spacecraft is described. This system consists of two facsimile cameras, a data encoder, and a data processor. Emphasis is placed on the discussion of the data processor, which contains a data compressor and a source encoder. With this compression scheme a compression ratio of 8 is achieved on a typical line of camera data. These compressed data are then convolutionally encoded.

ELIPS: Toward a Sensor Fusion Processor on a Chip

NASA Technical Reports Server (NTRS)

Daud, Taher; Stoica, Adrian; Tyson, Thomas; Li, Wei-te; Fabunmi, James

1998-01-01

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. The first demonstration of the ELIPS concept targets interceptor functionality; other applications, mainly in robotics and autonomous systems are considered for the future. The main assumption behind ELIPS is that fuzzy, rule-based and neural forms of computation can serve as the main primitives of an "intelligent" processor. Thus, in the same way classic processors are designed to optimize the hardware implementation of a set of fundamental operations, ELIPS is developed as an efficient implementation of computational intelligence primitives, and relies on a set of fuzzy set, fuzzy inference and neural modules, built in programmable analog hardware. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Following software demonstrations on several interceptor data, three important ELIPS building blocks (a fuzzy set preprocessor, a rule-based fuzzy system and a neural network) have been fabricated in analog VLSI hardware and demonstrated microsecond-processing times.

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

DOE PAGES

Mittal, Sparsh; Vetter, Jeffrey S.

2015-04-24

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made `reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. In this study, we provide a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory, GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based onmore » their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. Finally, we believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.« less

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S.

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made `reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. In this study, we provide a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory, GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based onmore » their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. Finally, we believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.« less

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, G. H.

1985-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90 percent for sufficiently large problems.

Multithreading in vector processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, B. H.

1984-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90% for sufficiently large problems.

Holo-Chidi video concentrator card

NASA Astrophysics Data System (ADS)

Nwodoh, Thomas A.; Prabhakar, Aditya; Benton, Stephen A.

2001-12-01

The Holo-Chidi Video Concentrator Card is a frame buffer for the Holo-Chidi holographic video processing system. Holo- Chidi is designed at the MIT Media Laboratory for real-time computation of computer generated holograms and the subsequent display of the holograms at video frame rates. The Holo-Chidi system is made of two sets of cards - the set of Processor cards and the set of Video Concentrator Cards (VCCs). The Processor cards are used for hologram computation, data archival/retrieval from a host system, and for higher-level control of the VCCs. The VCC formats computed holographic data from multiple hologram computing Processor cards, converting the digital data to analog form to feed the acousto-optic-modulators of the Media lab's Mark-II holographic display system. The Video Concentrator card is made of: a High-Speed I/O (HSIO) interface whence data is transferred from the hologram computing Processor cards, a set of FIFOs and video RAM used as buffer for data for the hololines being displayed, a one-chip integrated microprocessor and peripheral combination that handles communication with other VCCs and furnishes the card with a USB port, a co-processor which controls display data formatting, and D-to-A converters that convert digital fringes to analog form. The co-processor is implemented with an SRAM-based FPGA with over 500,000 gates and controls all the signals needed to format the data from the multiple Processor cards into the format required by Mark-II. A VCC has three HSIO ports through which up to 500 Megabytes of computed holographic data can flow from the Processor Cards to the VCC per second. A Holo-Chidi system with three VCCs has enough frame buffering capacity to hold up to thirty two 36Megabyte hologram frames at a time. Pre-computed holograms may also be loaded into the VCC from a host computer through the low- speed USB port. Both the microprocessor and the co- processor in the VCC can access the main system memory used to store control programs and data for the VCC. The Card also generates the control signals used by the scanning mirrors of Mark-II. In this paper we discuss the design of the VCC and its implementation in the Holo-Chidi system.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wickstrom, Gregory Lloyd; Gale, Jason Carl; Ma, Kwok Kee

The Sandia Secure Processor (SSP) is a new native Java processor that has been specifically designed for embedded applications. The SSP's design is a system composed of a core Java processor that directly executes Java bytecodes, on-chip intelligent IO modules, and a suite of software tools for simulation and compiling executable binary files. The SSP is unique in that it provides a way to control real-time IO modules for embedded applications. The system software for the SSP is a 'class loader' that takes Java .class files (created with your favorite Java compiler), links them together, and compiles a binary. Themore » complete SSP system provides very powerful functionality with very light hardware requirements with the potential to be used in a wide variety of small-system embedded applications. This paper gives a detail description of the Sandia Secure Processor and its unique features.« less

Vitamin C degradation products and pathways in the human lens.

PubMed

Nemet, Ina; Monnier, Vincent M

2011-10-28

Vitamin C and its degradation products participate in chemical modifications of proteins in vivo through non-enzymatic glycation (Maillard reaction) and formation of different products called advanced glycation end products. Vitamin C levels are particularly high in selected tissues, such as lens, brain and adrenal gland, and its degradation products can inflict substantial protein damage via formation of advanced glycation end products. However, the pathways of in vivo vitamin C degradation are poorly understood. Here we have determined the levels of vitamin C oxidation and degradation products dehydroascorbic acid, 2,3-diketogulonic acid, 3-deoxythreosone, xylosone, and threosone in the human lens using o-phenylenediamine to trap both free and protein-bound adducts. In the protein-free fraction and water-soluble proteins (WSP), all five listed degradation products were identified. Dehydroascorbic acid, 2,3-diketogulonic acid, and 3-deoxythreosone were the major products in the protein-free fraction, whereas in the WSP, 3-deoxythreosone was the most abundant measured dicarbonyl. In addition, 3-deoxythreosone in WSP showed positive linear correlation with age (p < 0.05). In water-insoluble proteins, only 3-deoxythreosone and threosone were detected, whereby the level of 3-deoxythreosone was ∼20 times higher than the level of threosone. The identification of 3-deoxythreosone as the major degradation product bound to human lens proteins provides in vivo evidence for the non-oxidative pathway of dehydroascorbate degradation into erythrulose as a major pathway for vitamin C degradation in vivo.

A hierarchical, automated target recognition algorithm for a parallel analog processor

NASA Technical Reports Server (NTRS)

Woodward, Gail; Padgett, Curtis

1997-01-01

A hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.

Design of an integrated fuel processor for residential PEMFCs applications

NASA Astrophysics Data System (ADS)

Seo, Yu Taek; Seo, Dong Joo; Jeong, Jin Hyeok; Yoon, Wang Lai

KIER has been developing a novel fuel processing system to provide hydrogen rich gas to residential PEMFCs system. For the effective design of a compact hydrogen production system, each unit process for steam reforming and water gas shift, has a steam generator and internal heat exchangers which are thermally and physically integrated into a single packaged hardware system. The newly designed fuel processor (prototype II) showed a thermal efficiency of 78% as a HHV basis with methane conversion of 89%. The preferential oxidation unit with two staged cascade reactors, reduces, the CO concentration to below 10 ppm without complicated temperature control hardware, which is the prerequisite CO limit for the PEMFC stack. After we achieve the initial performance of the fuel processor, partial load operation was carried out to test the performance and reliability of the fuel processor at various loads. The stability of the fuel processor was also demonstrated for three successive days with a stable composition of product gas and thermal efficiency. The CO concentration remained below 10 ppm during the test period and confirmed the stable performance of the two-stage PrOx reactors.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

The GF-3 SAR Data Processor

PubMed Central

Han, Bing; Ding, Chibiao; Zhong, Lihua; Liu, Jiayin; Qiu, Xiaolan; Hu, Yuxin; Lei, Bin

2018-01-01

The Gaofen-3 (GF-3) data processor was developed as a workstation-based GF-3 synthetic aperture radar (SAR) data processing system. The processor consists of two vital subsystems of the GF-3 ground segment, which are referred to as data ingesting subsystem (DIS) and product generation subsystem (PGS). The primary purpose of DIS is to record and catalogue GF-3 raw data with a transferring format, and PGS is to produce slant range or geocoded imagery from the signal data. This paper presents a brief introduction of the GF-3 data processor, including descriptions of the system architecture, the processing algorithms and its output format. PMID:29534464

Three-wheel air turbocompressor for PEM fuel cell systems

DOEpatents

Rehg, Tim; Gee, Mark; Emerson, Terence P.; Ferrall, Joe; Sokolov, Pavel

2003-08-19

A fuel cell system comprises a compressor and a fuel processor downstream of the compressor. A fuel cell stack is in communication with the fuel processor and compressor. A combustor is downstream of the fuel cell stack. First and second turbines are downstream of the fuel processor and in parallel flow communication with one another. A distribution valve is in communication with the first and second turbines. The first and second turbines are mechanically engaged to the compressor. A bypass valve is intermediate the compressor and the second turbine, with the bypass valve enabling a compressed gas from the compressor to bypass the fuel processor.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

Multiprocessor switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

2014-03-11

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

The LOGO Processor; A Guide for System Programmers.

ERIC Educational Resources Information Center

Weiner, Walter B.; And Others

A detailed specification of the LOGO programing system is given. The level of description is intended to enable system programers to design LOGO processors of their own. The discussion of storage allocation and garbage collection algorithms is virtually complete. An annotated LOGO system listing for the PDP-10 computer system may be obtained on…

A digital video tracking system

NASA Astrophysics Data System (ADS)

Giles, M. K.

1980-01-01

The Real-Time Videotheodolite (RTV) was developed in connection with the requirement to replace film as a recording medium to obtain the real-time location of an object in the field-of-view (FOV) of a long focal length theodolite. Design philosophy called for a system capable of discriminatory judgment in identifying the object to be tracked with 60 independent observations per second, capable of locating the center of mass of the object projection on the image plane within about 2% of the FOV in rapidly changing background/foreground situations, and able to generate a predicted observation angle for the next observation. A description is given of a number of subsystems of the RTV, taking into account the processor configuration, the video processor, the projection processor, the tracker processor, the control processor, and the optics interface and imaging subsystem.

Parallel processor-based raster graphics system architecture

DOEpatents

Littlefield, Richard J.

1990-01-01

An apparatus for generating raster graphics images from the graphics command stream includes a plurality of graphics processors connected in parallel, each adapted to receive any part of the graphics command stream for processing the command stream part into pixel data. The apparatus also includes a frame buffer for mapping the pixel data to pixel locations and an interconnection network for interconnecting the graphics processors to the frame buffer. Through the interconnection network, each graphics processor may access any part of the frame buffer concurrently with another graphics processor accessing any other part of the frame buffer. The plurality of graphics processors can thereby transmit concurrently pixel data to pixel locations in the frame buffer.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

NASA Astrophysics Data System (ADS)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

Method for operating a combustor in a fuel cell system

DOEpatents

Clingerman, Bruce J.; Mowery, Kenneth D.

2002-01-01

In one aspect, the invention provides a method of operating a combustor to heat a fuel processor to a desired temperature in a fuel cell system, wherein the fuel processor generates hydrogen (H.sub.2) from a hydrocarbon for reaction within a fuel cell to generate electricity. More particularly, the invention provides a method and select system design features which cooperate to provide a start up mode of operation and a smooth transition from start-up of the combustor and fuel processor to a running mode.

Multiprocessor shared-memory information exchange

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santoline, L.L.; Bowers, M.D.; Crew, A.W.

1989-02-01

In distributed microprocessor-based instrumentation and control systems, the inter-and intra-subsystem communication requirements ultimately form the basis for the overall system architecture. This paper describes a software protocol which addresses the intra-subsystem communications problem. Specifically the protocol allows for multiple processors to exchange information via a shared-memory interface. The authors primary goal is to provide a reliable means for information to be exchanged between central application processor boards (masters) and dedicated function processor boards (slaves) in a single computer chassis. The resultant Multiprocessor Shared-Memory Information Exchange (MSMIE) protocol, a standard master-slave shared-memory interface suitable for use in nuclear safety systems, ismore » designed to pass unidirectional buffers of information between the processors while providing a minimum, deterministic cycle time for this data exchange.« less

Parallel processing approach to transform-based image coding

NASA Astrophysics Data System (ADS)

Normile, James O.; Wright, Dan; Chu, Ken; Yeh, Chia L.

1991-06-01

This paper describes a flexible parallel processing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each processor has access to a globally shared memory. A multiple bus architecture in combination with a dual ported memory allows communication with a host control processor. The system has been applied to prototyping of video compression and decompression algorithms. The decomposition of transform based algorithms for decompression into a form suitable for parallel processing is described. A technique for automatic load balancing among the processors is developed and discussed, results ar presented with image statistics and data rates. Finally techniques for accelerating the system throughput are analyzed and results from the application of one such modification described.

An investigation of potential applications of OP-SAPS: Operational Sampled Analog Processors

NASA Technical Reports Server (NTRS)

Parrish, E. A.; Mcvey, E. S.

1977-01-01

The application of OP-SAP's (operational sampled analog processors) in pattern recognition system is summarized. Areas investigated include: (1) human face recognition; (2) a high-speed programmable transversal filter system; (3) discrete word (speech) recognition; and (4) a resolution enhancement system.

Multibus-based parallel processor for simulation

NASA Technical Reports Server (NTRS)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

WATERLOPP V2/64: A highly parallel machine for numerical computation

NASA Astrophysics Data System (ADS)

Ostlund, Neil S.

1985-07-01

Current technological trends suggest that the high performance scientific machines of the future are very likely to consist of a large number (greater than 1024) of processors connected and communicating with each other in some as yet undetermined manner. Such an assembly of processors should behave as a single machine in obtaining numerical solutions to scientific problems. However, the appropriate way of organizing both the hardware and software of such an assembly of processors is an unsolved and active area of research. It is particularly important to minimize the organizational overhead of interprocessor comunication, global synchronization, and contention for shared resources if the performance of a large number ( n) of processors is to be anything like the desirable n times the performance of a single processor. In many situations, adding a processor actually decreases the performance of the overall system since the extra organizational overhead is larger than the extra processing power added. The systolic loop architecture is a new multiple processor architecture which attemps at a solution to the problem of how to organize a large number of asynchronous processors into an effective computational system while minimizing the organizational overhead. This paper gives a brief overview of the basic systolic loop architecture, systolic loop algorithms for numerical computation, and a 64-processor implementation of the architecture, WATERLOOP V2/64, that is being used as a testbed for exploring the hardware, software, and algorithmic aspects of the architecture.

PREMAQ: A NEW PRE-PROCESSOR TO CMAQ FOR AIR-QUALITY FORECASTING

EPA Science Inventory

A new pre-processor to CMAQ (PREMAQ) has been developed as part of the national air-quality forecasting system. PREMAQ combines the functionality of MCIP and parts of SMOKE in a single real-time processor. PREMAQ was specifically designed to link NCEP's Eta model with CMAQ, and...

Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

NASA Technical Reports Server (NTRS)

Casasent, D.; Jackson, J.

1986-01-01

A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

NASA Astrophysics Data System (ADS)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Shuttle cryogenics supply system. Optimization study. Volume 5 B-2, part 1: Appendix programmers manual for math model

NASA Technical Reports Server (NTRS)

1973-01-01

An appendix to the programmers manual for the mathematical model pertaining to the design of cryogenic supply systems for spacecraft is presented. The program listing was produced using the EXEC-8 LISTALL processor which lists a file in alphabetical order. Since the processor does not differentiate between subroutines, functions, and procedure definition processors, each subprogram has been relabeled to clearly identify the type of symbolic listing.

Fault tolerance in a supercomputer through dynamic repartitioning

DOEpatents

Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Takken, Todd E.

2007-02-27

A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of processors can be swapped with any group which experiences a hardware failure. This swapping can be under software control, thereby permitting the entire computer to sustain a hardware failure but, after swapping in the standby processors, to still appear to software as a pristine, fully functioning system.

Solving very large, sparse linear systems on mesh-connected parallel computers

NASA Technical Reports Server (NTRS)

Opsahl, Torstein; Reif, John

1987-01-01

The implementation of Pan and Reif's Parallel Nested Dissection (PND) algorithm on mesh connected parallel computers is described. This is the first known algorithm that allows very large, sparse linear systems of equations to be solved efficiently in polylog time using a small number of processors. How the processor bound of PND can be matched to the number of processors available on a given parallel computer by slowing down the algorithm by constant factors is described. Also, for the important class of problems where G(A) is a grid graph, a unique memory mapping that reduces the inter-processor communication requirements of PND to those that can be executed on mesh connected parallel machines is detailed. A description of an implementation on the Goodyear Massively Parallel Processor (MPP), located at Goddard is given. Also, a detailed discussion of data mappings and performance issues is given.

Parallel processing data network of master and slave transputers controlled by a serial control network

DOEpatents

Crosetto, Dario B.

1996-01-01

The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

Methanol Fuel Cell

NASA Technical Reports Server (NTRS)

Voecks, G. E.

1985-01-01

In proposed fuel-cell system, methanol converted to hydrogen in two places. External fuel processor converts only part of methanol. Remaining methanol converted in fuel cell itself, in reaction at anode. As result, size of fuel processor reduced, system efficiency increased, and cost lowered.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

Method and apparatus of parallel computing with simultaneously operating stream prefetching and list prefetching engines

DOEpatents

Boyle, Peter A.; Christ, Norman H.; Gara, Alan; Mawhinney, Robert D.; Ohmacht, Martin; Sugavanam, Krishnan

2012-12-11

A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command.

The MIDAS processor. [Multivariate Interactive Digital Analysis System for multispectral scanner data

NASA Technical Reports Server (NTRS)

Kriegler, F. J.; Gordon, M. F.; Mclaughlin, R. H.; Marshall, R. E.

1975-01-01

The MIDAS (Multivariate Interactive Digital Analysis System) processor is a high-speed processor designed to process multispectral scanner data (from Landsat, EOS, aircraft, etc.) quickly and cost-effectively to meet the requirements of users of remote sensor data, especially from very large areas. MIDAS consists of a fast multipipeline preprocessor and classifier, an interactive color display and color printer, and a medium scale computer system for analysis and control. The system is designed to process data having as many as 16 spectral bands per picture element at rates of 200,000 picture elements per second into as many as 17 classes using a maximum likelihood decision rule.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ringbus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection arid the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ring-bus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection and the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

National Weather Service - Strategic Planning and Policy

Science.gov Websites

Policy ATTN: W/SP 1325 East-West Highway Silver Spring, MD 20910-3283 Phone: (301) 713-0258; Fax: (301 Administration National Weather Service Strategic Planning and Policy Office 1325 East West Highway Silver Spring

Low latency messages on distributed memory multiprocessors

NASA Technical Reports Server (NTRS)

Rosing, Matthew; Saltz, Joel

1993-01-01

Many of the issues in developing an efficient interface for communication on distributed memory machines are described and a portable interface is proposed. Although the hardware component of message latency is less than one microsecond on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 microseconds. The reason for this imbalance is that the software interface does not match the hardware. By changing the interface to match the hardware more closely, applications with fine grained communication can be put on these machines. Based on several tests that were run on the iPSC/860, an interface that will better match current distributed memory machines is proposed. The model used in the proposed interface consists of a computation processor and a communication processor on each node. Communication between these processors and other nodes in the system is done through a buffered network. Information that is transmitted is either data or procedures to be executed on the remote processor. The dual processor system is better suited for efficiently handling asynchronous communications compared to a single processor system. The ability to send data or procedure is very flexible for minimizing message latency, based on the type of communication being performed. The test performed and the proposed interface are described.

Development of compact fuel processor for 2 kW class residential PEMFCs

NASA Astrophysics Data System (ADS)

Seo, Yu Taek; Seo, Dong Joo; Jeong, Jin Hyeok; Yoon, Wang Lai

Korea Institute of Energy Research (KIER) has been developing a novel fuel processing system to provide hydrogen rich gas to residential polymer electrolyte membrane fuel cells (PEMFCs) cogeneration system. For the effective design of a compact hydrogen production system, the unit processes of steam reforming, high and low temperature water gas shift, steam generator and internal heat exchangers are thermally and physically integrated into a packaged hardware system. Several prototypes are under development and the prototype I fuel processor showed thermal efficiency of 73% as a HHV basis with methane conversion of 81%. Recently tested prototype II has been shown the improved performance of thermal efficiency of 76% with methane conversion of 83%. In both prototypes, two-stage PrOx reactors reduce CO concentration less than 10 ppm, which is the prerequisite CO limit condition of product gas for the PEMFCs stack. After confirming the initial performance of prototype I fuel processor, it is coupled with PEMFC single cell to test the durability and demonstrated that the fuel processor is operated for 3 days successfully without any failure of fuel cell voltage. Prototype II fuel processor also showed stable performance during the durability test.

Evaluation of fault-tolerant parallel-processor architectures over long space missions

NASA Technical Reports Server (NTRS)

Johnson, Sally C.

1989-01-01

The impact of a five year space mission environment on fault-tolerant parallel processor architectures is examined. The target application is a Strategic Defense Initiative (SDI) satellite requiring 256 parallel processors to provide the computation throughput. The reliability requirements are that the system still be operational after five years with .99 probability and that the probability of system failure during one-half hour of full operation be less than 10(-7). The fault tolerance features an architecture must possess to meet these reliability requirements are presented, many potential architectures are briefly evaluated, and one candidate architecture, the Charles Stark Draper Laboratory's Fault-Tolerant Parallel Processor (FTPP) is evaluated in detail. A methodology for designing a preliminary system configuration to meet the reliability and performance requirements of the mission is then presented and demonstrated by designing an FTPP configuration.

C-MOS array design techniques: SUMC multiprocessor system study

NASA Technical Reports Server (NTRS)

Clapp, W. A.; Helbig, W. A.; Merriam, A. S.

1972-01-01

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

High Performance Processors for Space Environments: A Subproject of the NASA Exploration Missions Systems Directorate "Radiation Hardened Electronics for Space Environments" Technology Development Program

NASA Technical Reports Server (NTRS)

Johnson, M.; Label, K.; McCabe, J.; Powell, W.; Bolotin, G.; Kolawa, E.; Ng, T.; Hyde, D.

2007-01-01

Implementation of challenging Exploration Systems Missions Directorate objectives and strategies can be constrained by onboard computing capabilities and power efficiencies. The Radiation Hardened Electronics for Space Environments (RHESE) High Performance Processors for Space Environments project will address this challenge by significantly advancing the sustained throughput and processing efficiency of high-per$ormance radiation-hardened processors, targeting delivery of products by the end of FY12.

A VME-based software trigger system using UNIX processors

NASA Astrophysics Data System (ADS)

Atmur, Robert; Connor, David F.; Molzon, William

1997-02-01

We have constructed a distributed computing platform with eight processors to assemble and filter data from digitization crates. The filtered data were transported to a tape-writing UNIX computer via ethernet. Each processor ran a UNIX operating system and was installed in its own VME crate. Each VME crate contained dual-port memories which interfaced with the digitizers. Using standard hardware and software (VME and UNIX) allows us to select from a wide variety of non-proprietary products and makes upgrades simpler, if they are necessary.

PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-08-18

Written Using  Synopsys Processor Designer1  David Whelihan, Ph.D. and Kate Thurmer  MIT Lincoln Laboratory, Lexington, MA, USA    ABSTRACT  Microprocessors ...internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors... microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its

Switch for serial or parallel communication networks

DOEpatents

Crosette, D.B.

1994-07-19

A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination. 9 figs.

Switch for serial or parallel communication networks

DOEpatents

Crosette, Dario B.

1994-01-01

A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems.

PubMed

Shehzad, Danish; Bozkuş, Zeki

2016-01-01

Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models.

Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems

PubMed Central

Bozkuş, Zeki

2016-01-01

Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models. PMID:27413363

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

PubMed

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

System Level RBDO for Military Ground Vehicles using High Performance Computing

DTIC Science & Technology

2008-01-01

platform. Only the analyses that required more than 24 processors were conducted on the Onyx 350 due to the limited number of processors on the...optimization constraints varied. The queues set the number of processors and number of finite element code licenses available to the analyses. sgi ONYX ...3900: unix 24 MIPS R16000 PROCESSORS 4 IR2 GRAPHICS PIPES 4 IR3 GRAPHICS PIPES 24 GBYTES MEMORY 36 GBYTES LOCAL DISK SPACE sgi ONYX 350: unix 32 MIPS

A data base processor semantics specification package

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

Experience in highly parallel processing using DAP

NASA Technical Reports Server (NTRS)

Parkinson, D.

1987-01-01

Distributed Array Processors (DAP) have been in day to day use for ten years and a large amount of user experience has been gained. The profile of user applications is similar to that of the Massively Parallel Processor (MPP) working group. Experience has shown that contrary to expectations, highly parallel systems provide excellent performance on so-called dirty problems such as the physics part of meteorological codes. The reasons for this observation are discussed. The arguments against replacing bit processors with floating point processors are also discussed.

Kellogg Library and Archive Retrieval System (KLARS) Document Capture Manual. Draft Version.

ERIC Educational Resources Information Center

Hugo, Jane

This manual is designed to supply background information for Kellogg Library and Archive Retrieval System (KLARS) processors and others who might work with the system, outline detailed policies and procedures for processors who prepare and enter data into the adult education database on KLARS, and inform general readers about the system. KLARS is…

Fluid leakage detector for vacuum applications

NASA Technical Reports Server (NTRS)

Nguyen, Bich Ngoc (Inventor); Farkas, Tibor (Inventor); Kim, Brian Byungkyu (Inventor)

2002-01-01

A leak detection system for use with a fluid conducting system in a vacuum environment, such as space, is described. The system preferably includes a mesh-like member substantially disposed about the fluid conducting system, and at least one sensor disposed within the mesh-like member. The sensor is capable of detecting a decrease in temperature of the mesh-like member when a leak condition causes the fluid of the fluid conducting system to freeze when exposed to the vacuum environment. Additionally, a signal processor in preferably in communication with the sensor. The sensor transmits an electrical signal to the signal processor such that the signal processor is capable of indicating the location of the fluid leak in the fluid conducting system.

Cargo Movement Operations System (CMOS). Requirements Traceability Matrix Increment II

DTIC Science & Technology

1990-05-17

NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No. Number Comment 1. C-i SS0-3 Change "workstation" to "processor". 2. C-2 SS0009 Change "workstation" to "processor". SS0016 3. C-6 SS0032 Change "workstation" to "processor". SS0035 4. C-9 SS0063 Add comma after "e.g." 5. C-i SS0082 Change "workstation" to "processor". 6. C-17 SS0131 Change "workstation" to "processor". SS0132 7. C-28 SS0242 Change "workstation"

A high performance linear equation solver on the VPP500 parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakanishi, Makoto; Ina, Hiroshi; Miura, Kenichi

1994-12-31

This paper describes the implementation of two high performance linear equation solvers developed for the Fujitsu VPP500, a distributed memory parallel supercomputer system. The solvers take advantage of the key architectural features of VPP500--(1) scalability for an arbitrary number of processors up to 222 processors, (2) flexible data transfer among processors provided by a crossbar interconnection network, (3) vector processing capability on each processor, and (4) overlapped computation and transfer. The general linear equation solver based on the blocked LU decomposition method achieves 120.0 GFLOPS performance with 100 processors in the LIN-PACK Highly Parallel Computing benchmark.

Summer primary productivity and phytoplankton community composition driven by different hydrographic structures in the East/Japan Sea and the Western Subarctic Pacific

NASA Astrophysics Data System (ADS)

Kwak, Jung Hyun; Lee, Sang Heon; Hwang, Jeomshik; Suh, Young-Sang; Je Park, Hyun; Chang, Kyung-Il; Kim, Kyung-Ryul; Kang, Chang-Keun

2014-07-01

The East/Japan Sea (EJS) is a highly productive marginal sea in the northwest Pacific, consisting of three basins (Ulleung Basin: UB, Yamato Basin: YB, and Japan Basin: JB). To find causes of the reportedly high primary productivity in summer in the EJS, especially in the UB, we measured primary productivity, phytoplankton composition, and other environmental variables. The water column was strongly stratified in the EJS compared with the Western Subarctic Pacific (WSP). Integrated primary productivity was two times higher in the EJS (612 mg C m-2 d-1) than in the WSP (291 mg C m-2 d-1). The vertical distributions of physicochemical and biological factors confirmed that production in the subsurface chlorophyll maximum layer in the study regions was an important factor regulating primary productivity within the water column. While picoplankton (<2.7 µm) dominated in the WSP, JB, and YB, micro/nanoplankton (≥2.7 µm) dominated in the UB. Contribution by picoplankton to total biomass and primary productivity in the UB was significantly lower than in the other regions. CHEMTAX analysis using marker pigments showed that diverse phytoplankton groups inhabited the study regions. Cluster and canonical correspondence analyses showed high correlation between the spatial variation in phytoplankton assemblages with the water mass properties mainly represented by water temperature and nitrate concentration. Overall, our results suggest that the hydrographic structure of water column in the study region is an important controlling factor of the biomass and productivity of phytoplankton as well as their diversity in size and taxonomic groups.

Metagenomic Insights Into the Microbial Community and Nutrient Cycling in the Western Subarctic Pacific Ocean.

PubMed

Li, Yingdong; Jing, Hongmei; Xia, Xiaomin; Cheung, Shunyan; Suzuki, Koji; Liu, Hongbin

2018-01-01

The composition and metabolic functions of prokaryotic communities in the western subarctic Pacific (WSP), where strong mixing of waters from the Sea of Okhotsk and the East Kamchatka Current result in transfer to the Oyashio Current, were investigated using a shotgun metagenome sequencing approach. Functional metabolic genes related to nutrient cycling of nitrogen, sulfur, carbohydrates, iron and amino acids were differently distributed between the surface and deep waters of the WSP. Genes related to nitrogen metabolism were mainly found in deep waters, where Thaumarchaeaota, Sphingomonadales , and Pseudomonadales were closely associated and performing important roles in ammonia oxidation, assimilatory nitrate reduction, and dissimilatory nitrate reduction processes, respectively. In addition, orders affiliated to Spingobacteria and Alphaproteobacteria were crucial for sulfate reduction and abundant at 3000 m, whereas orders affiliated to Gammaproteobacteria , which harbored the most sulfate reduction genes, were abundant at 1000 m. Additionally, when compared with the East Kamchatka Current, the prokaryotes in the Oyashio Current were likely to consume more energy for synthesizing cellular components. Also, genes encoding iron transport and siderophore biosynthesis proteins were in low abundance, indicating that the iron was not a limiting factor in the Oyashio current. In contrast, in the East Kamchatka Current, prokaryotes were more likely to directly utilize the amino acids and absorb iron from the environment. Overall, our data indicated that the transformation from the East Kamchatka Current to the Oyashio Current reshapes not only the composition of microbial community, but also the function of the metabolic processes. These results extended our knowledge of the microbial composition and potential metabolism in the WSP.

The concept of incomplete fibromyalgia syndrome: comparison of incomplete fibromyalgia syndrome with fibromyalgia syndrome by 1990 ACR classification criteria and its implications for newer criteria and clinical practice.

PubMed

Yunus, Muhammad B; Aldag, Jean C

2012-03-01

The 1990 American College of Rheumatology (ACR) classification criteria for fibromyalgia/fibromyalgia syndrome (FMS) has 2 components: (a) widespread pain (WSP) and (b) presence of 11 or more tender points (TP) among possible 18 sites. Some clinic patients fulfill 1 component but not the other. We have considered these patients to have incomplete FMS (IFMS). The purpose of this study was to examine the clinical and psychological differences between IFMS and FMS (by 1990 ACR criteria) because such comparison may be helpful to diagnose patients in the clinic. Six hundred consecutive patients referred to our rheumatology clinic with a diagnosis of FMS were examined by a standard protocol to determine whether they fulfilled the 1990 criteria for FMS. Both IFMS and FMS groups were compared in demographic, clinical, and psychological variables using appropriate statistical methods. One hundred twelve (18.7%) patients did not satisfy the 1990 ACR criteria and were classified as IFMS. Symptoms in IFMS and FMS were similar, generally with less frequent and less severe symptoms in the IFMS group. In IFMS, no significant difference was found among the WSP and TP component subgroups. Both TP and WSP were correlated with important features of FMS. Fulfillment of the ACR 1990 criteria is not necessary for a diagnosis of FMS in the clinic. For diagnosis and management of FMS in the clinical setting, IFMS patients, along with consideration of the total clinical picture, may be considered to have FMS, albeit generally mild.

Biofilm formation and cellulose expression among diverse environmental Pseudomonas isolates.

PubMed

Ude, Susanne; Arnold, Dawn L; Moon, Christina D; Timms-Wilson, Tracey; Spiers, Andrew J

2006-11-01

The ability to form biofilms is seen as an increasingly important colonization strategy among both pathogenic and environmental bacteria. A survey of 185 plant-associated, phytopathogenic, soil and river Pseudomonas isolates resulted in 76% producing biofilms at the air-liquid (A-L) interface after selection in static microcosms. Considerable variation in biofilm phenotype was observed, including waxy aggregations, viscous and floccular masses, and physically cohesive biofilms with continuously varying strengths over 1500-fold. Calcofluor epifluorescent microscopy identified cellulose as the matrix component in biofilms produced by Pseudomonas asplenii, Pseudomonas corrugata, Pseudomonas fluorescens, Pseudomonas marginalis, Pseudomonas putida, Pseudomonas savastanoi and Pseudomonas syringae isolates. Cellulose expression and biofilm formation could be induced by the constitutively active WspR19 mutant of the cyclic-di-GMP-associated, GGDEF domain-containing response regulator involved in the P. fluorescens SBW25 wrinkly spreader phenotype and cellular aggregation in Pseudomonas aeruginosa PA01. WspR19 could also induce P. putida KT2440, which otherwise did not produce a biofilm or express cellulose, as well as Escherichia coli K12 and Salmonella typhimurium LT2, both of which express cellulose yet lack WspR homologues. Statistical analysis of biofilm parameters suggest that biofilm development is a more complex process than that simply described by the production of attachment and matrix components and bacterial growth. This complexity was also seen in multivariate analysis as a species-ecological habitat effect, underscoring the fact that in vitro biofilms are abstractions of those surface and volume colonization processes used by bacteria in their natural environments.

Metagenomic Insights Into the Microbial Community and Nutrient Cycling in the Western Subarctic Pacific Ocean

PubMed Central

Li, Yingdong; Jing, Hongmei; Xia, Xiaomin; Cheung, Shunyan; Suzuki, Koji; Liu, Hongbin

2018-01-01

The composition and metabolic functions of prokaryotic communities in the western subarctic Pacific (WSP), where strong mixing of waters from the Sea of Okhotsk and the East Kamchatka Current result in transfer to the Oyashio Current, were investigated using a shotgun metagenome sequencing approach. Functional metabolic genes related to nutrient cycling of nitrogen, sulfur, carbohydrates, iron and amino acids were differently distributed between the surface and deep waters of the WSP. Genes related to nitrogen metabolism were mainly found in deep waters, where Thaumarchaeaota, Sphingomonadales, and Pseudomonadales were closely associated and performing important roles in ammonia oxidation, assimilatory nitrate reduction, and dissimilatory nitrate reduction processes, respectively. In addition, orders affiliated to Spingobacteria and Alphaproteobacteria were crucial for sulfate reduction and abundant at 3000 m, whereas orders affiliated to Gammaproteobacteria, which harbored the most sulfate reduction genes, were abundant at 1000 m. Additionally, when compared with the East Kamchatka Current, the prokaryotes in the Oyashio Current were likely to consume more energy for synthesizing cellular components. Also, genes encoding iron transport and siderophore biosynthesis proteins were in low abundance, indicating that the iron was not a limiting factor in the Oyashio current. In contrast, in the East Kamchatka Current, prokaryotes were more likely to directly utilize the amino acids and absorb iron from the environment. Overall, our data indicated that the transformation from the East Kamchatka Current to the Oyashio Current reshapes not only the composition of microbial community, but also the function of the metabolic processes. These results extended our knowledge of the microbial composition and potential metabolism in the WSP. PMID:29670596

Human factors considerations in the evaluation of processor-based signal and train control systems

DOT National Transportation Integrated Search

2007-06-01

In August 2001, the Federal Railroad Administration issued the notice of proposed rulemaking: Standards for Development and : Use of Processor-Based Signal and Train Control Systems (49 Code of Federal Regulations Part 236). This proposed rule addres...

77 FR 77017 - Initiation of Antidumping and Countervailing Duty Administrative Reviews and Request for...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-31

... Co., Ltd. Wenzhou Juxing Special Steel Co. Ltd. Widesea Industrial Corporation Ltd. Wisco & Crm Wuhan... Corporation Ltd. Wisco & Crm Wuhan Materials & Trade WSP Pipe Co., Ltd. Wuhan Iron & Steel (Group) Corp. Wuxi...

A programmable power processor for a 25-kW power module

NASA Technical Reports Server (NTRS)

Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

1979-01-01

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.

1990-01-01

A ground-based adaptive optics imaging telescope system attempts to improve image quality by detecting and correcting for atmospherically induced wavefront aberrations. The required control computations during each cycle will take a finite amount of time. Longer time delays result in larger values of residual wavefront error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper presents a study of the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for the adaptive optics application. An optimization of the adaptive optics correction algorithm with respect to an optical processor's degree of accuracy is also briefly discussed.

Phosphorus utilization and characterization of ileal digesta and excreta from broiler chickens fed diets varying in cereal grain, phosphorus level, and phytase addition.

PubMed

Leytem, A B; Widyaratne, G P; Thacker, P A

2008-12-01

Both intrinsic and exogenous phytase in poultry feeds can alter phytate utilization and the solubility of P excreted. This experiment determined the effects of feeding diets varying in cereal grain, P concentration and phytase addition on phytate and P utilization and P characterization of ileal digesta and excreta. Twelve treatments, consisting of diets based on corn, wheat, barley, or high fat-low lignin oat and 3 P treatments (low P with 0.30% nonphytate P; low P + 1,000 phytase units of phytase; high P with 0.45% nonphytate P), were fed to 300 broilers using a factorial design. Fresh excreta were collected at 20 and 21 d and ileal digesta was collected at 21 d. Ileal digesta and excreta were analyzed for total P, phytate P and Ca, with P composition determined by solution (31)P nuclear magnetic resonance spectroscopy. Excreta samples were also analyzed for water soluble P (WSP). Apparent ileal digestibility coefficients for phytate P and total P ranged from 0.03 to 0.42 and 0.56 to 0.71, respectively. Diets supplemented with phytase had greater phytate P hydrolysis than unsupplemented diets. Apparent total tract digestibility coefficients for phytate P and total P ranged from 0.10 to 0.73 and 0.43 to 0.61, respectively. Across cereal grains, there was almost a 3-fold increase in total tract phytate P hydrolysis with phytase supplementation. The P composition of ileal digesta was predominantly phytate P (70 to 88% of total P), whereas excreta phytate P ranged from 26 to 76% of total P. Excreta WSP ranged from 3.2 to 7.5 g kg(-1) and was least for the barley diets. There was a 25% reduction in excreta WSP from the high P to the low P + phytase diets and a 37% reduction from the high P to the low P diets. As cereal grain had little influence on phytate digestibility, it is unlikely that intrinsic phytase in grain has much influence on phytate utilization by poultry. Both total P and WSP in excreta were reduced by the low P diet and the low P + phytase diet, irrespective of cereal grain, which reduces the risk of P transfer to water bodies when excreta are applied to land as fertilizer.

Effects of phosphorus level and phytase in broiler breeder rearing and laying diets on live performance and phosphorus excretion.

PubMed

Plumstead, P W; Romero-Sanchez, H; Maguire, R O; Gernat, A G; Brake, J

2007-02-01

The effects of a reduced dietary nonphytate phosphorus (NPP) level and inclusion of phytase on broiler breeder performance and P concentrations in the litter and manure were investigated. Ross 308 broiler breeder pullets and Ross 344 cockerels were placed sex-separate in a blackout growing house and fed standard starter and grower diets to 9 wk of age. At 10 wk of age, 4 treatments (A, B, C, D) were assigned to each of 4 floor pens of 68 pullets and 1 pen of 50 cockerels. From 10 to 21 wk, treatments A to D contained 0.37, 0.27, 0.27, and 0.17% NPP, respectively, with 300 phytase units (FTU)/kg of phytase added to treatments B and D. At 21 wk of age, birds were photostimulated and transferred to a two-thirds slat-litter breeder house with 16 pens of 60 pullets and 6 cockerels. A laying diet was fed from 22 to 64 wk and NPP levels of treatments A to D were adjusted to 0.37, 0.27, 0.19, and 0.09%, respectively, and phytase addition to treatments B and D was increased to 500 FTU/kg. Analysis of the litter from growing pens showed no effect on litter total P when phytase replaced 0.1% of NPP. However, decreasing the dietary NPP by 0.1% without phytase reduced the litter total P by 18%. Water-soluble P (WSP) and the WSP:total P ratio decreased when the grower dietary NPP level was reduced to 0.17% with added phytase and was correlated with litter moisture levels in growing pens. During the laying period, a reduction in NPP from 0.37 to 0.09% with added phytase reduced both the manure total P and WSP by 42%. Hen-day egg production was highest on the lowest NPP diet with phytase, but fertility decreased when the dietary NPP was reduced below 0.37%. Results showed that phytase inclusion in a broiler breeder laying diet at the expense of all added P from dicalcium phosphate reduced the manure total P and WSP concentrations by 42%, with no effect on the number of chicks produced per hen housed.

Implementing the PM Programming Language using MPI and OpenMP - a New Tool for Programming Geophysical Models on Parallel Systems

NASA Astrophysics Data System (ADS)

Bellerby, Tim

2015-04-01

PM (Parallel Models) is a new parallel programming language specifically designed for writing environmental and geophysical models. The language is intended to enable implementers to concentrate on the science behind the model rather than the details of running on parallel hardware. At the same time PM leaves the programmer in control - all parallelisation is explicit and the parallel structure of any given program may be deduced directly from the code. This paper describes a PM implementation based on the Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) standards, looking at issues involved with translating the PM parallelisation model to MPI/OpenMP protocols and considering performance in terms of the competing factors of finer-grained parallelisation and increased communication overhead. In order to maximise portability, the implementation stays within the MPI 1.3 standard as much as possible, with MPI-2 MPI-IO file handling the only significant exception. Moreover, it does not assume a thread-safe implementation of MPI. PM adopts a two-tier abstract representation of parallel hardware. A PM processor is a conceptual unit capable of efficiently executing a set of language tasks, with a complete parallel system consisting of an abstract N-dimensional array of such processors. PM processors may map to single cores executing tasks using cooperative multi-tasking, to multiple cores or even to separate processing nodes, efficiently sharing tasks using algorithms such as work stealing. While tasks may move between hardware elements within a PM processor, they may not move between processors without specific programmer intervention. Tasks are assigned to processors using a nested parallelism approach, building on ideas from Reyes et al. (2009). The main program owns all available processors. When the program enters a parallel statement then either processors are divided out among the newly generated tasks (number of new tasks < number of processors) or tasks are divided out among the available processors (number of tasks > number of processors). Nested parallel statements may further subdivide the processor set owned by a given task. Tasks or processors are distributed evenly by default, but uneven distributions are possible under programmer control. It is also possible to explicitly enable child tasks to migrate within the processor set owned by their parent task, reducing load unbalancing at the potential cost of increased inter-processor message traffic. PM incorporates some programming structures from the earlier MIST language presented at a previous EGU General Assembly, while adopting a significantly different underlying parallelisation model and type system. PM code is available at www.pm-lang.org under an unrestrictive MIT license. Reference Ruymán Reyes, Antonio J. Dorta, Francisco Almeida, Francisco de Sande, 2009. Automatic Hybrid MPI+OpenMP Code Generation with llc, Recent Advances in Parallel Virtual Machine and Message Passing Interface, Lecture Notes in Computer Science Volume 5759, 185-195

SPAR reference manual

NASA Technical Reports Server (NTRS)

Whetstone, W. D.

1976-01-01

The functions and operating rules of the SPAR system, which is a group of computer programs used primarily to perform stress, buckling, and vibrational analyses of linear finite element systems, were given. The following subject areas were discussed: basic information, structure definition, format system matrix processors, utility programs, static solutions, stresses, sparse matrix eigensolver, dynamic response, graphics, and substructure processors.

A modular BLSS simulation model

NASA Technical Reports Server (NTRS)

Rummel, John D.; Volk, Tyler

1987-01-01

A bioregenerative life support system (BLSS) for extraterrestrial use will be faced with coordination problems more acute than those in any ecosystem found on Earth. A related problem in BLSS design is providing an interface between the various life support processors, one that will allow for their coordination while still allowing for system expansion. A modular model is presented of a BLSS that interfaces system processors only with the material storage reservoirs, allowing those reservoirs to act as the principal buffers in the system and thus minimizing difficulties with processor coordination. The modular nature of the model allows independent development of the detailed submodels that exist within the model framework. Using this model, BLSS dynamics were investigated under normal conditions and under various failure modes. Partial and complete failures of various components, such as the waste processors or the plants themselves, drive transient responses in the model system, allowing the examination of the effectiveness of the system reservoirs as buffers. The results from simulations help to determine control strategies and BLSS design requirements. An evolved version could be used as an interactive control aid in a future BLSS.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processor in the form of a hybrid microcircuit

NASA Astrophysics Data System (ADS)

Evtikhiev, N. N.; Esepkina, N. A.; Dolgii, V. A.; Lavrov, A. P.; Khotyanov, B. M.; Chernokozhin, V. V.; Shestak, S. A.

1995-10-01

An optoelectronic processor in the form of a hybrid microcircuit is described. An analysis is made of the feasibility of developing a new class of optoelectronic processors which are hybrid microcircuits and can operate both as self-contained specialised computers and also as functional components of computing systems.

Never Trust Your Word Processor

ERIC Educational Resources Information Center

Linke, Dirk

2009-01-01

In this article, the author talks about the auto correction mode of word processors that leads to a number of problems and describes an example in biochemistry exams that shows how word processors can lead to mistakes in databases and in papers. The author contends that, where this system is applied, spell checking should not be left to a word…

Integrated High-Speed Torque Control System for a Robotic Joint

NASA Technical Reports Server (NTRS)

Davis, Donald R. (Inventor); Radford, Nicolaus A. (Inventor); Permenter, Frank Noble (Inventor); Valvo, Michael C. (Inventor); Askew, R. Scott (Inventor)

2013-01-01

A control system for achieving high-speed torque for a joint of a robot includes a printed circuit board assembly (PCBA) having a collocated joint processor and high-speed communication bus. The PCBA may also include a power inverter module (PIM) and local sensor conditioning electronics (SCE) for processing sensor data from one or more motor position sensors. Torque control of a motor of the joint is provided via the PCBA as a high-speed torque loop. Each joint processor may be embedded within or collocated with the robotic joint being controlled. Collocation of the joint processor, PIM, and high-speed bus may increase noise immunity of the control system, and the localized processing of sensor data from the joint motor at the joint level may minimize bus cabling to and from each control node. The joint processor may include a field programmable gate array (FPGA).

The MasPar MP-1 As a Computer Arithmetic Laboratory

PubMed Central

Anuta, Michael A.; Lozier, Daniel W.; Turner, Peter R.

1996-01-01

This paper is a blueprint for the use of a massively parallel SIMD computer architecture for the simulation of various forms of computer arithmetic. The particular system used is a DEC/MasPar MP-1 with 4096 processors in a square array. This architecture has many advantages for such simulations due largely to the simplicity of the individual processors. Arithmetic operations can be spread across the processor array to simulate a hardware chip. Alternatively they may be performed on individual processors to allow simulation of a massively parallel implementation of the arithmetic. Compromises between these extremes permit speed-area tradeoffs to be examined. The paper includes a description of the architecture and its features. It then summarizes some of the arithmetic systems which have been, or are to be, implemented. The implementation of the level-index and symmetric level-index, LI and SLI, systems is described in some detail. An extensive bibliography is included. PMID:27805123

Practical, redundant, failure-tolerant, self-reconfiguring embedded system architecture

DOEpatents

Klarer, Paul R.; Hayward, David R.; Amai, Wendy A.

2006-10-03

This invention relates to system architectures, specifically failure-tolerant and self-reconfiguring embedded system architectures. The invention provides both a method and architecture for redundancy. There can be redundancy in both software and hardware for multiple levels of redundancy. The invention provides a self-reconfiguring architecture for activating redundant modules whenever other modules fail. The architecture comprises: a communication backbone connected to two or more processors and software modules running on each of the processors. Each software module runs on one processor and resides on one or more of the other processors to be available as a backup module in the event of failure. Each module and backup module reports its status over the communication backbone. If a primary module does not report, its backup module takes over its function. If the primary module becomes available again, the backup module returns to its backup status.

Embedded System Implementation on FPGA System With μCLinux OS

NASA Astrophysics Data System (ADS)

Fairuz Muhd Amin, Ahmad; Aris, Ishak; Syamsul Azmir Raja Abdullah, Raja; Kalos Zakiah Sahbudin, Ratna

2011-02-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Radiation-Hardened Electronics for Advanced Communications Systems

NASA Technical Reports Server (NTRS)

Whitaker, Sterling

2015-01-01

Novel approach enables high-speed special-purpose processors Advanced reconfigurable and reprogrammable communication systems will require sub-130-nanometer electronics. Legacy single event upset (SEU) radiation-tolerant circuits are ineffective at speeds greater than 125 megahertz. In Phase I of this project, ICs, LLC, demonstrated new base-level logic circuits that provide SEU immunity for sub-130-nanometer high-speed circuits. In Phase II, the company developed an innovative self-restoring logic (SRL) circuit and a system approach that provides high-speed, SEU-tolerant solutions that are effective for sub-130-nanometer electronics scalable to at least 22-nanometer processes. The SRL system can be used in the design of NASA's next-generation special-purpose processors, especially reconfigurable communication processors.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

NASA Astrophysics Data System (ADS)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

EGR distribution and fluctuation probe based on CO2 measurements

DOEpatents

Parks, II, James E.; Partridge, Jr., William P.; Yoo, Ji Hyung

2015-06-30

A diagnostic system having a laser, an EGR probe, a detector and a processor. The laser may be a swept-.lamda. laser having a sweep range including a significant CO.sub.2 feature and substantially zero absorption regions. The sweep range may extend from about 2.708 .mu.m to about 2.7085 .mu.m. The processor may determine CO.sub.2 concentration as a function of the detector output signal. The processor may normalize the output signal as a function of the zero absorption regions. The system may include a plurality of EGR probes receiving light from a single laser. The system may include a separate detector for each probe. Alternatively, the system may combine the light returning from the different probes into a composite beam that is measured by a single detector. A unique modulation characteristic may be introduced into each light beam before combination so that the processor can discriminate between them in the composite beam.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Toshiba TDF-500 High Resolution Viewing And Analysis System

NASA Astrophysics Data System (ADS)

Roberts, Barry; Kakegawa, M.; Nishikawa, M.; Oikawa, D.

1988-06-01

A high resolution, operator interactive, medical viewing and analysis system has been developed by Toshiba and Bio-Imaging Research. This system provides many advanced features including high resolution displays, a very large image memory and advanced image processing capability. In particular, the system provides CRT frame buffers capable of update in one frame period, an array processor capable of image processing at operator interactive speeds, and a memory system capable of updating multiple frame buffers at frame rates whilst supporting multiple array processors. The display system provides 1024 x 1536 display resolution at 40Hz frame and 80Hz field rates. In particular, the ability to provide whole or partial update of the screen at the scanning rate is a key feature. This allows multiple viewports or windows in the display buffer with both fixed and cine capability. To support image processing features such as windowing, pan, zoom, minification, filtering, ROI analysis, multiplanar and 3D reconstruction, a high performance CPU is integrated into the system. This CPU is an array processor capable of up to 400 million instructions per second. To support the multiple viewer and array processors' instantaneous high memory bandwidth requirement, an ultra fast memory system is used. This memory system has a bandwidth capability of 400MB/sec and a total capacity of 256MB. This bandwidth is more than adequate to support several high resolution CRT's and also the fast processing unit. This fully integrated approach allows effective real time image processing. The integrated design of viewing system, memory system and array processor are key to the imaging system. It is the intention to describe the architecture of the image system in this paper.

Multi-heuristic dynamic task allocation using genetic algorithms in a heterogeneous distributed system

PubMed Central

Page, Andrew J.; Keane, Thomas M.; Naughton, Thomas J.

2010-01-01

We present a multi-heuristic evolutionary task allocation algorithm to dynamically map tasks to processors in a heterogeneous distributed system. It utilizes a genetic algorithm, combined with eight common heuristics, in an effort to minimize the total execution time. It operates on batches of unmapped tasks and can preemptively remap tasks to processors. The algorithm has been implemented on a Java distributed system and evaluated with a set of six problems from the areas of bioinformatics, biomedical engineering, computer science and cryptography. Experiments using up to 150 heterogeneous processors show that the algorithm achieves better efficiency than other state-of-the-art heuristic algorithms. PMID:20862190

System and Method of Locating Lightning Strikes

NASA Technical Reports Server (NTRS)

Medelius, Pedro J. (Inventor); Starr, Stanley O. (Inventor)

2002-01-01

A system and method of determining locations of lightning strikes has been described. The system includes multiple receivers located around an area of interest, such as a space center or airport. Each receiver monitors both sound and electric fields. The detection of an electric field pulse and a sound wave are used to calculate an area around each receiver in which the lighting is detected. A processor is coupled to the receivers to accurately determine the location of the lighting strike. The processor can manipulate the receiver data to compensate for environmental variables such as wind, temperature, and humidity. Further, each receiver processor can discriminate between distant and local lightning strikes.

Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

2000-01-01

The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

Watchdog activity monitor (WAM) for use wth high coverage processor self-test

NASA Technical Reports Server (NTRS)

Tulpule, Bhalchandra R. (Inventor); Crosset, III, Richard W. (Inventor); Versailles, Richard E. (Inventor)

1988-01-01

A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

NASA Technical Reports Server (NTRS)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

NASA Technical Reports Server (NTRS)

Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

2007-01-01

Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

NASA Technical Reports Server (NTRS)

Bartram, Peter N.

1989-01-01

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

Fault-Tolerant, Real-Time, Multi-Core Computer System

NASA Technical Reports Server (NTRS)

Gostelow, Kim P.

2012-01-01

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

Global synchronization of parallel processors using clock pulse width modulation

DOEpatents

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

System on chip module configured for event-driven architecture

DOEpatents

Robbins, Kevin; Brady, Charles E.; Ashlock, Tad A.

2017-10-17

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

PubMed

Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

2013-09-01

In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

Evaluation of the Washington state target zero teams project : traffic tech.

DOT National Transportation Integrated Search

2015-01-01

In late 2006, the Washington State Patrol (WSP) assembled : a full-time, high-visibility saturation patrol called the Night : Emphasis Enforcement Team (NEET). This pilot program, : based in Snohomish County and funded by the Washington : Traffic Saf...

Optical Associative Processors For Visual Perception"

NASA Astrophysics Data System (ADS)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

Computer Sciences and Data Systems, volume 2

NASA Technical Reports Server (NTRS)

1987-01-01

Topics addressed include: data storage; information network architecture; VHSIC technology; fiber optics; laser applications; distributed processing; spaceborne optical disk controller; massively parallel processors; and advanced digital SAR processors.

A comparison of five methods for monitoring the precision of automated x-ray film processors.

PubMed

Nickoloff, E L; Leo, F; Reese, M

1978-11-01

Five different methods for preparing sensitometric strips used to monitor the precision of automated film processors are compared. A method for determining the sensitivity of each system to processor variations is presented; the observed statistical variability is multiplied by the system response to temperature or chemical changes. Pre-exposed sensitometric strips required the use of accurate densitometers and stringent control limits to be effective. X-ray exposed sensitometric strips demonstrated large variations in the x-ray output (2 omega approximately equal to 8.0%) over a period of one month. Some light sensitometers were capable of detecting +/- 1.0 degrees F (+/- 0.6 degrees C) variations in developer temperature in the processor and/or about 10.0 ml of chemical contamination in the processor. Nevertheless, even the light sensitometers were susceptible to problems, e.g. film emulsion selection, line voltage variations, and latent image fading. Advantages and disadvantages of the various sensitometric methods are discussed.

Asynchronous broadcast for ordered delivery between compute nodes in a parallel computing system where packet header space is limited

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Sameer

Disclosed is a mechanism on receiving processors in a parallel computing system for providing order to data packets received from a broadcast call and to distinguish data packets received at nodes from several incoming asynchronous broadcast messages where header space is limited. In the present invention, processors at lower leafs of a tree do not need to obtain a broadcast message by directly accessing the data in a root processor's buffer. Instead, each subsequent intermediate node's rank id information is squeezed into the software header of packet headers. In turn, the entire broadcast message is not transferred from the rootmore » processor to each processor in a communicator but instead is replicated on several intermediate nodes which then replicated the message to nodes in lower leafs. Hence, the intermediate compute nodes become "virtual root compute nodes" for the purpose of replicating the broadcast message to lower levels of a tree.« less

Performance of a natural gas fuel processor for residential PEFC system using a novel CO preferential oxidation catalyst

NASA Astrophysics Data System (ADS)

Echigo, Mitsuaki; Shinke, Norihisa; Takami, Susumu; Tabata, Takeshi

Natural gas fuel processors have been developed for 500 W and 1 kW class residential polymer electrolyte fuel cell (PEFC) systems. These fuel processors contain all the elements—desulfurizers, steam reformers, CO shift converters, CO preferential oxidation (PROX) reactors, steam generators, burners and heat exchangers—in one package. For the PROX reactor, a single-stage PROX process using a novel PROX catalyst was adopted. In the 1 kW class fuel processor, thermal efficiency of 83% at HHV was achieved at nominal output assuming a H 2 utilization rate in the cell stack of 76%. CO concentration below 1 ppm in the product gas was achieved even under the condition of [O 2]/[CO]=1.5 at the PROX reactor. The long-term durability of the fuel processor was demonstrated with almost no deterioration in thermal efficiency and CO concentration for 10,000 h, 1000 times start and stop cycles, 25,000 cycles of load change.

A proposed microcomputer implementation of an Omega navigation processor

NASA Technical Reports Server (NTRS)

Abel, J. D.

1976-01-01

A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.

A fault-tolerant information processing concept for space vehicles.

NASA Technical Reports Server (NTRS)

Hopkins, A. L., Jr.

1971-01-01

A distributed fault-tolerant information processing system is proposed, comprising a central multiprocessor, dedicated local processors, and multiplexed input-output buses connecting them together. The processors in the multiprocessor are duplicated for error detection, which is felt to be less expensive than using coded redundancy of comparable effectiveness. Error recovery is made possible by a triplicated scratchpad memory in each processor. The main multiprocessor memory uses replicated memory for error detection and correction. Local processors use any of three conventional redundancy techniques: voting, duplex pairs with backup, and duplex pairs in independent subsystems.

78 FR 70888 - Need for Agency Approval of a Railroad's Use of Certain Technology That Has Been Previously...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-11-27

... technologies, namely safety-critical processor-based signal or train control systems, including subsystems and... or train control system (including a subsystem or component thereof) that was in service as of June 6... processor-based signal or train control system, subsystem, or component.'' See 49 CFR 236.903. Under Subpart...

A general multiscroll Lorenz system family and its realization via digital signal processors.

PubMed

Yu, Simin; Lü, Jinhu; Tang, Wallace K S; Chen, Guanrong

2006-09-01

This paper proposes a general multiscroll Lorenz system family by introducing a novel parameterized nth-order polynomial transformation. Some basic dynamical behaviors of this general multiscroll Lorenz system family are then investigated, including bifurcations, maximum Lyapunov exponents, and parameters regions. Furthermore, the general multiscroll Lorenz attractors are physically verified by using digital signal processors.

Towards the formal specification of the requirements and design of a processor interface unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.'

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

PubMed

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

PubMed Central

Cheung, Kit; Schultz, Simon R.; Luk, Wayne

2016-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation. PMID:26834542

Method for prefetching non-contiguous data structures

DOEpatents

Blumrich, Matthias A [Ridgefield, CT; Chen, Dong [Croton On Hudson, NY; Coteus, Paul W [Yorktown Heights, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Heidelberger, Philip [Cortlandt Manor, NY; Hoenicke, Dirk [Ossining, NY; Ohmacht, Martin [Brewster, NY; Steinmacher-Burow, Burkhard D [Mount Kisco, NY; Takken, Todd E [Mount Kisco, NY; Vranas, Pavlos M [Bedford Hills, NY

2009-05-05

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple perfecting for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefect rather than some other predictive algorithm. This enables hardware to effectively prefect memory access patterns that are non-contiguous, but repetitive.

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

NASA Astrophysics Data System (ADS)

Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

2011-01-01

General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

Method for operating a combustor in a fuel cell system

DOEpatents

Chalfant, Robert W.; Clingerman, Bruce J.

2002-01-01

A method of operating a combustor to heat a fuel processor in a fuel cell system, in which the fuel processor generates a hydrogen-rich stream a portion of which is consumed in a fuel cell stack and a portion of which is discharged from the fuel cell stack and supplied to the combustor, and wherein first and second streams are supplied to the combustor, the first stream being a hydrocarbon fuel stream and the second stream consisting of said hydrogen-rich stream, the method comprising the steps of monitoring the temperature of the fuel processor; regulating the quantity of the first stream to the combustor according to the temperature of the fuel processor; and comparing said quantity of said first stream to a predetermined value or range of predetermined values.

Pseudomonas fluorescens F113 Mutant with Enhanced Competitive Colonization Ability and Improved Biocontrol Activity against Fungal Root Pathogens ▿

PubMed Central

Barahona, Emma; Navazo, Ana; Martínez-Granero, Francisco; Zea-Bonilla, Teresa; Pérez-Jiménez, Rosa María; Martín, Marta; Rivilla, Rafael

2011-01-01

Motility is one of the most important traits for efficient rhizosphere colonization by Pseudomonas fluorescens F113rif (F113). In this bacterium, motility is a polygenic trait that is repressed by at least three independent pathways, including the Gac posttranscriptional system, the Wsp chemotaxis-like pathway, and the SadB pathway. Here we show that the kinB gene, which encodes a signal transduction protein that together with AlgB has been implicated in alginate production, participates in swimming motility repression through the Gac pathway, acting downstream of the GacAS two-component system. Gac mutants are impaired in secondary metabolite production and are unsuitable as biocontrol agents. However, the kinB mutant and a triple mutant affected in kinB, sadB, and wspR (KSW) possess a wild-type phenotype for secondary metabolism. The KSW strain is hypermotile and more competitive for rhizosphere colonization than the wild-type strain. We have compared the biocontrol activity of KSW with those of the wild-type strain and a phenotypic variant (F113v35 [V35]) which is hypermotile and hypercompetitive but is affected in secondary metabolism since it harbors a gacS mutation. Biocontrol experiments in the Fusarium oxysporum f. sp. radicis-lycopersici/Lycopersicum esculentum (tomato) and Phytophthora cactorum/Fragaria vesca (strawberry) pathosystems have shown that the three strains possess biocontrol activity. Biocontrol activity was consistently lower for V35, indicating that the production of secondary metabolites was the most important trait for biocontrol. Strain KSW showed improved biocontrol compared with the wild-type strain, indicating that an increase in competitive colonization ability resulted in improved biocontrol and that the rational design of biocontrol agents by mutation is feasible. PMID:21685161

Pseudomonas fluorescens F113 mutant with enhanced competitive colonization ability and improved biocontrol activity against fungal root pathogens.

PubMed

Barahona, Emma; Navazo, Ana; Martínez-Granero, Francisco; Zea-Bonilla, Teresa; Pérez-Jiménez, Rosa María; Martín, Marta; Rivilla, Rafael

2011-08-01

Motility is one of the most important traits for efficient rhizosphere colonization by Pseudomonas fluorescens F113rif (F113). In this bacterium, motility is a polygenic trait that is repressed by at least three independent pathways, including the Gac posttranscriptional system, the Wsp chemotaxis-like pathway, and the SadB pathway. Here we show that the kinB gene, which encodes a signal transduction protein that together with AlgB has been implicated in alginate production, participates in swimming motility repression through the Gac pathway, acting downstream of the GacAS two-component system. Gac mutants are impaired in secondary metabolite production and are unsuitable as biocontrol agents. However, the kinB mutant and a triple mutant affected in kinB, sadB, and wspR (KSW) possess a wild-type phenotype for secondary metabolism. The KSW strain is hypermotile and more competitive for rhizosphere colonization than the wild-type strain. We have compared the biocontrol activity of KSW with those of the wild-type strain and a phenotypic variant (F113v35 [V35]) which is hypermotile and hypercompetitive but is affected in secondary metabolism since it harbors a gacS mutation. Biocontrol experiments in the Fusarium oxysporum f. sp. radicis-lycopersici/Lycopersicum esculentum (tomato) and Phytophthora cactorum/Fragaria vesca (strawberry) pathosystems have shown that the three strains possess biocontrol activity. Biocontrol activity was consistently lower for V35, indicating that the production of secondary metabolites was the most important trait for biocontrol. Strain KSW showed improved biocontrol compared with the wild-type strain, indicating that an increase in competitive colonization ability resulted in improved biocontrol and that the rational design of biocontrol agents by mutation is feasible.

Optimal processor assignment for pipeline computations

NASA Technical Reports Server (NTRS)

Nicol, David M.; Simha, Rahul; Choudhury, Alok N.; Narahari, Bhagirath

1991-01-01

The availability of large scale multitasked parallel architectures introduces the following processor assignment problem for pipelined computations. Given a set of tasks and their precedence constraints, along with their experimentally determined individual responses times for different processor sizes, find an assignment of processor to tasks. Two objectives are of interest: minimal response given a throughput requirement, and maximal throughput given a response time requirement. These assignment problems differ considerably from the classical mapping problem in which several tasks share a processor; instead, it is assumed that a large number of processors are to be assigned to a relatively small number of tasks. Efficient assignment algorithms were developed for different classes of task structures. For a p processor system and a series parallel precedence graph with n constituent tasks, an O(np2) algorithm is provided that finds the optimal assignment for the response time optimization problem; it was found that the assignment optimizing the constrained throughput in O(np2log p) time. Special cases of linear, independent, and tree graphs are also considered.

Energy consumption estimation of an OMAP-based Android operating system

NASA Astrophysics Data System (ADS)

González, Gabriel; Juárez, Eduardo; Castro, Juan José; Sanz, César

2011-05-01

System-level energy optimization of battery-powered multimedia embedded systems has recently become a design goal. The poor operational time of multimedia terminals makes computationally demanding applications impractical in real scenarios. For instance, the so-called smart-phones are currently unable to remain in operation longer than several hours. The OMAP3530 processor basically consists of two processing cores, a General Purpose Processor (GPP) and a Digital Signal Processor (DSP). The former, an ARM Cortex-A8 processor, is aimed to run a generic Operating System (OS) while the latter, a DSP core based on the C64x+, has architecture optimized for video processing. The BeagleBoard, a commercial prototyping board based on the OMAP processor, has been used to test the Android Operating System and measure its performance. The board has 128 MB of SDRAM external memory, 256 MB of Flash external memory and several interfaces. Note that the clock frequency of the ARM and DSP OMAP cores is 600 MHz and 430 MHz, respectively. This paper describes the energy consumption estimation of the processes and multimedia applications of an Android v1.6 (Donut) OS on the OMAP3530-Based BeagleBoard. In addition, tools to communicate the two processing cores have been employed. A test-bench to profile the OS resource usage has been developed. As far as the energy estimates concern, the OMAP processor energy consumption model provided by the manufacturer has been used. The model is basically divided in two energy components. The former, the baseline core energy, describes the energy consumption that is independent of any chip activity. The latter, the module active energy, describes the energy consumed by the active modules depending on resource usage.

The precision-processing subsystem for the Earth Resources Technology Satellite.

NASA Technical Reports Server (NTRS)

Chapelle, W. E.; Bybee, J. E.; Bedross, G. M.

1972-01-01

Description of the precision processor, a subsystem in the image-processing system for the Earth Resources Technology Satellite (ERTS). This processor is a special-purpose image-measurement and printing system, designed to process user-selected bulk images to produce 1:1,000,000-scale film outputs and digital image data, presented in a Universal-Transverse-Mercator (UTM) projection. The system will remove geometric and radiometric errors introduced by the ERTS multispectral sensors and by the bulk-processor electron-beam recorder. The geometric transformations required for each input scene are determined by resection computations based on reseau measurements and image comparisons with a special ground-control base contained within the system; the images are then printed and digitized by electronic image-transfer techniques.

Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

The automatic control system and stand-by facilities of the TDMA-40 equipment

NASA Astrophysics Data System (ADS)

Gudenko, D. V.; Pankov, G. Kh.; Pauk, A. G.; Tsirlin, V. M.

1980-10-01

When a controlling station in a satellite communications system is out of order, a complex algorithm must be carried out for automatic operation of the stand-by equipment. A processor has been developed to perform this algorithm, as well as operations involving the stand-by facilities of the receiving-transmitting equipment of the station. The design principles and solutions to problems in developing the equipment for the monitoring and controlling systems are described. These systems are based on multistation access using time division multiplexing. Algorithms are presented for the operation of the synchronizing processor and the control processor of the equipment. The automatic control system and stand-by facilities make it possible to reduce the service personnel and to design an unattended station.

Evaluation of the Washington State Target Zero teams project.

DOT National Transportation Integrated Search

2015-01-01

As part of its Target Zero strategic highway safety plan that has the goal to reduce traffic fatalities in Washington to zero by the year 2030, the State of Washington established three detachments of Washington State Patrol (WSP) troopers to f...

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

Nitrogen removal in maturation waste stabilisation ponds via biological uptake and sedimentation of dead biomass.

PubMed

Camargo Valero, M A; Mara, D D; Newton, R J

2010-01-01

In this work a set of experiments was undertaken in a pilot-scale WSP system to determine the importance of organic nitrogen sedimentation on ammonium and total nitrogen removals in maturation ponds and its seasonal variation under British weather conditions, from September 2004 to May 2007. The nitrogen content in collected sediment samples varied from 4.17% to 6.78% (dry weight) and calculated nitrogen sedimentation rates ranged from 273 to 2868 g N/ha d. High ammonium removals were observed together with high concentrations of chlorophyll-a in the pond effluent. Moreover, chlorophyll-a had a very good correlation with the corresponding increment of VSS (algal biomass) and suspended organic nitrogen (biological nitrogen uptake) in the maturation pond effluents. Therefore, when ammonium removal reached its maximum, total nitrogen removal was very poor as most of the ammonia taken up by algae was washed out in the pond effluent in the form of suspended solids. After sedimentation of the dead algal biomass, it was clear that algal-cell nitrogen was recycled from the sludge layer into the pond water column. Recycled nitrogen can either be taken up by algae or washed out in the pond effluent. Biological (mainly algal) uptake of inorganic nitrogen species and further sedimentation of dead biomass (together with its subsequent mineralization) is one of the major mechanisms controlling in-pond nitrogen recycling in maturation WSP, particularly when environmental and operational conditions are favourable for algal growth.

Circuitry, systems and methods for detecting magnetic fields

DOEpatents

Kotter, Dale K [Shelley, ID; Spencer, David F [Idaho Falls, ID; Roybal, Lyle G [Idaho Falls, ID; Rohrbaugh, David T [Idaho Falls, ID

2010-09-14

Circuitry for detecting magnetic fields includes a first magnetoresistive sensor and a second magnetoresistive sensor configured to form a gradiometer. The circuitry includes a digital signal processor and a first feedback loop coupled between the first magnetoresistive sensor and the digital signal processor. A second feedback loop which is discrete from the first feedback loop is coupled between the second magnetoresistive sensor and the digital signal processor.

Picoradio: Communication/Computation Piconodes for Sensor Networks

DTIC Science & Technology

2003-01-02

diagram of PicoNode III, or Quark node. It is made from two custom chips, Strange RF and Charm digital processor , and is complemented by a set of...the chipset comprising of Strange (analog OOK transceiver) and Charm (digital processor ) chips. 44 Figure 33: System block diagram of the Quark node...19 2.B PICONODE II - TWO-CHIP PICONODE IMPLEMENTATION ......................................... 21 2.B.1 Baseband processor (BBP

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

Implementation and Assessment of Advanced Analog Vector-Matrix Processor

NASA Technical Reports Server (NTRS)

Gary, Charles K.; Bualat, Maria G.; Lum, Henry, Jr. (Technical Monitor)

1994-01-01

This paper discusses the design and implementation of an analog optical vecto-rmatrix coprocessor with a throughput of 128 Mops for a personal computer. Vector matrix calculations are inherently parallel, providing a promising domain for the use of optical calculators. However, to date, digital optical systems have proven too cumbersome to replace electronics, and analog processors have not demonstrated sufficient accuracy in large scale systems. The goal of the work described in this paper is to demonstrate a viable optical coprocessor for linear operations. The analog optical processor presented has been integrated with a personal computer to provide full functionality and is the first demonstration of an optical linear algebra processor with a throughput greater than 100 Mops. The optical vector matrix processor consists of a laser diode source, an acoustooptical modulator array to input the vector information, a liquid crystal spatial light modulator to input the matrix information, an avalanche photodiode array to read out the result vector of the vector matrix multiplication, as well as transport optics and the electronics necessary to drive the optical modulators and interface to the computer. The intent of this research is to provide a low cost, highly energy efficient coprocessor for linear operations. Measurements of the analog accuracy of the processor performing 128 Mops are presented along with an assessment of the implications for future systems. A range of noise sources, including cross-talk, source amplitude fluctuations, shot noise at the detector, and non-linearities of the optoelectronic components are measured and compared to determine the most significant source of error. The possibilities for reducing these sources of error are discussed. Also, the total error is compared with that expected from a statistical analysis of the individual components and their relation to the vector-matrix operation. The sufficiency of the measured accuracy of the processor is compared with that required for a range of typical problems. Calculations resolving alloy concentrations from spectral plume data of rocket engines are implemented on the optical processor, demonstrating its sufficiency for this problem. We also show how this technology can be easily extended to a 100 x 100 10 MHz (200 Cops) processor.

Web surveillance system using platform-based design

NASA Astrophysics Data System (ADS)

Lin, Shin-Yo; Tsai, Tsung-Han

2004-04-01

A revolutionary methodology of SOPC platform-based design environment for multimedia communications will be developed. We embed a softcore processor to perform the image compression in FPGA. Then, we plug-in an Ethernet daughter board in the SOPC development platform system. Afterward, a web surveillance platform system is presented. The web surveillance system consists of three parts: image capture, web server and JPEG compression. In this architecture, user can control the surveillance system by remote. By the IP address configures to Ethernet daughter board, the user can access the surveillance system via browser. When user access the surveillance system, the CMOS sensor presently capture the remote image. After that, it will feed the captured image with the embedded processor. The embedded processor immediately performs the JPEG compression. Afterward, the user receives the compressed data via Ethernet. To sum up of the above mentioned, the all system will be implemented on APEX20K200E484-2X device.

Status of the Regenerative ECLS Water Recovery System

NASA Technical Reports Server (NTRS)

Carter, Donald Layne

2010-01-01

The regenerative Water Recovery System (WRS) has completed its first full year of operation on the International Space Station (ISS). The major assemblies included in this system are the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2010, and describes the technical challenges encountered and lessons learned over the past year.

JPRS Report, Science & Technology, USSR: Computers, Control Systems and Machines

DTIC Science & Technology

1989-03-14

optimizatsii slozhnykh sistem (Coding Theory and Complex System Optimization ). Alma-Ata, Nauka Press, 1977, pp. 8-16. 11. Author’s certificate number...Interpreter Specifics [0. I. Amvrosova] ............................................. 141 Creation of Modern Computer Systems for Complex Ecological...processor can be designed to decrease degradation upon failure and assure more reliable processor operation, without requiring more complex software or

VENTURE/PC manual: A multidimensional multigroup neutron diffusion code system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shapiro, A.; Huria, H.C.; Cho, K.W.

1991-12-01

VENTURE/PC is a recompilation of part of the Oak Ridge BOLD VENTURE code system, which will operate on an IBM PC or compatible computer. Neutron diffusion theory solutions are obtained for multidimensional, multigroup problems. This manual contains information associated with operating the code system. The purpose of the various modules used in the code system, and the input for these modules are discussed. The PC code structure is also given. Version 2 included several enhancements not given in the original version of the code. In particular, flux iterations can be done in core rather than by reading and writing tomore » disk, for problems which allow sufficient memory for such in-core iterations. This speeds up the iteration process. Version 3 does not include any of the special processors used in the previous versions. These special processors utilized formatted input for various elements of the code system. All such input data is now entered through the Input Processor, which produces standard interface files for the various modules in the code system. In addition, a Standard Interface File Handbook is included in the documentation which is distributed with the code, to assist in developing the input for the Input Processor.« less

Compute Server Performance Results

NASA Technical Reports Server (NTRS)

Stockdale, I. E.; Barton, John; Woodrow, Thomas (Technical Monitor)

1994-01-01

Parallel-vector supercomputers have been the workhorses of high performance computing. As expectations of future computing needs have risen faster than projected vector supercomputer performance, much work has been done investigating the feasibility of using Massively Parallel Processor systems as supercomputers. An even more recent development is the availability of high performance workstations which have the potential, when clustered together, to replace parallel-vector systems. We present a systematic comparison of floating point performance and price-performance for various compute server systems. A suite of highly vectorized programs was run on systems including traditional vector systems such as the Cray C90, and RISC workstations such as the IBM RS/6000 590 and the SGI R8000. The C90 system delivers 460 million floating point operations per second (FLOPS), the highest single processor rate of any vendor. However, if the price-performance ration (PPR) is considered to be most important, then the IBM and SGI processors are superior to the C90 processors. Even without code tuning, the IBM and SGI PPR's of 260 and 220 FLOPS per dollar exceed the C90 PPR of 160 FLOPS per dollar when running our highly vectorized suite,

An optical/digital processor - Hardware and applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Sterling, W. M.

1975-01-01

A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD2PO4) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased-array radar data processing, synthetic-aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Methods and Apparatus for Aggregation of Multiple Pulse Code Modulation Channels into a Signal Time Division Multiplexing Stream

NASA Technical Reports Server (NTRS)

Chang, Chen J. (Inventor); Liaghati, Jr., Amir L. (Inventor); Liaghati, Mahsa L. (Inventor)

2018-01-01

Methods and apparatus are provided for telemetry processing using a telemetry processor. The telemetry processor can include a plurality of communications interfaces, a computer processor, and data storage. The telemetry processor can buffer sensor data by: receiving a frame of sensor data using a first communications interface and clock data using a second communications interface, receiving an end of frame signal using a third communications interface, and storing the received frame of sensor data in the data storage. After buffering the sensor data, the telemetry processor can generate an encapsulated data packet including a single encapsulated data packet header, the buffered sensor data, and identifiers identifying telemetry devices that provided the sensor data. A format of the encapsulated data packet can comply with a Consultative Committee for Space Data Systems (CCSDS) standard. The telemetry processor can send the encapsulated data packet using a fourth and a fifth communications interfaces.

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

NASA Technical Reports Server (NTRS)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

Job-mix modeling and system analysis of an aerospace multiprocessor.

NASA Technical Reports Server (NTRS)

Mallach, E. G.

1972-01-01

An aerospace guidance computer organization, consisting of multiple processors and memory units attached to a central time-multiplexed data bus, is described. A job mix for this type of computer is obtained by analysis of Apollo mission programs. Multiprocessor performance is then analyzed using: 1) queuing theory, under certain 'limiting case' assumptions; 2) Markov process methods; and 3) system simulation. Results of the analyses indicate: 1) Markov process analysis is a useful and efficient predictor of simulation results; 2) efficient job execution is not seriously impaired even when the system is so overloaded that new jobs are inordinately delayed in starting; 3) job scheduling is significant in determining system performance; and 4) a system having many slow processors may or may not perform better than a system of equal power having few fast processors, but will not perform significantly worse.

Global genetic variation in the Asian citrus psyllid, Diaphorina citri (Hemiptera: Liviidae) and the endosymbiont Wolbachia: links between Iran and the USA detected.

PubMed

Lashkari, Mohammadreza; Manzari, Shahab; Sahragard, Ahad; Malagnini, Valeria; Boykin, Laura M; Hosseini, Reza

2014-07-01

The Asian citrus psyllid, Diaphorina citri Kuwayama (Hemiptera: Liviidae), is one of the most serious pests of citrus in the world, because it transmits the pathogen that causes citrus greening disease. To determine genetic variation among geographic populations of D. citri, microsatellite markers, mitochondrial gene cytochrome oxidase I (mtCOI) and the Wolbachia-Diaphorina, wDi, gene wsp sequence data were used to characterize Iranian and Pakistani populations. Also, a Bayesian phylogenetic technique was utilized to elucidate the relationships among the sequences data in this study and all mtCOI and wsp sequence data available in GenBank and the Wolbachia database. Microsatellite markers revealed significant genetic differentiation among Iranian populations, as well as between Iranian and Pakistani populations (FST  = 0.0428, p < 0.01). Within Iran, the Sistan-Baluchestan population is significantly different from the Hormozgan (Fareghan) and Fars populations. By contrast, mtCOI data revealed two polymorphic sites separating the sequences from Iran and Pakistan. Global phylogenetic analyses showed that D. citri populations in Iran, India, Saudi Arabia, Brazil, Mexico, Florida and Texas (USA) are similar. Wolbachia, wDi, wsp sequences were similar among Iranian populations, but different between Iranian and Pakistani populations. The South West Asia (SWA) group is the most likely source of the introduced Iranian populations of D. citri. This assertion is also supported by the sequence similarity of the Wolbachia, wDi, strains from the Florida, USA and Iranian D. citri. These results should be considered when looking for biological controls in either country. © 2013 Society of Chemical Industry.

Nutrient excretion, phosphorus characterization, and phosphorus solubility in excreta from broiler chicks fed diets containing graded levels of wheat distillers grains with solubles.

PubMed

Leytem, A B; Kwanyuen, P; Thacker, P

2008-12-01

Increased interest in ethanol production in North America has led to increased production of distillers dried grains with solubles (DDGS), the majority of which are fed to livestock. To determine the impact of including wheat DDGS in broiler diets on nutrient excretion and P characterization and solubility, 125 one-day-old male broiler chicks were fed wheat- and soybean meal-based diets containing 0, 5, 10, 15, or 20% wheat DDGS. There were 5 replicate pens per treatment, with 5 birds per pen arranged in a randomized block design. Apparent retention of both N and P were determined by using the indicator method. Nutrients excreted per kilogram of DM intake were also calculated. Characterization of excreta P was determined by (31)P-solution nuclear magnetic resonance spectroscopy, and water-soluble P (WSP) was determined by extraction of excreta with deionized water. The apparent retention of both N (P < 0.001) and P (P < 0.008) decreased linearly with increasing inclusion rates of DDGS from 0 to 20%. The nutrient output per kilogram of DM intake increased linearly with increased DDGS inclusion rate for N (P < 0.04), P (P < 0.0001), and WSP (P < 0.0003). As the inclusion rate of DDGS increased, the P concentration in excreta increased (P < 0.008), whereas excreta phytate P concentrations decreased (P < 0.01), which led to an increase in WSP and the fraction of total P that was soluble. Because the inclusion of DDGS in poultry diets increased N and P output, as well as the solubility of P excreted, care should be taken when including high levels of DDGS in poultry diets, because increases in N and P excretion are a concern from an environmental standpoint.

Localization of brain 5α-reductase messenger RNA in mice selectively bred for high chronic alcohol withdrawal severity.

PubMed

Roselli, Charles E; Finn, Timothy J; Ronnekleiv-Kelly, Sean M; Tanchuck, Michelle A; Kaufman, Katherine R; Finn, Deborah A

2011-12-01

Several lines of evidence suggest that fluctuations in endogenous levels of the γ-aminobutyric acid (GABA)ergic neurosteroid allopregnanolone (ALLO) represent one mechanism for regulation of GABAergic inhibitory tone in the brain, with an ultimate impact on behavior. Consistent with this idea, there was an inverse relationship between ALLO levels and symptoms of anxiety and depression in humans and convulsive activity in rodents during alcohol withdrawal. Our recent studies examined the activity and expression of 5α-reductase (Srd5a1), the rate-limiting enzyme in the biosynthesis of ALLO, during alcohol withdrawal in mice selectively bred for high chronic alcohol withdrawal (Withdrawal Seizure-Prone [WSP]) and found that Srd5a1 was downregulated in the cortex and hippocampus over the time course of dependence and withdrawal. The purpose of the present studies was to extend these findings and more discretely map the regions of Srd5a1 expression in mouse brain using radioactive in situ hybridization in WSP mice that were ethanol naïve, following exposure to 72h ethanol vapor (dependent) or during peak withdrawal. In naïve animals, expression of Srd5a1 was widely distributed throughout the mouse brain, with highest expression in specific regions of the cerebral cortex, hippocampus, thalamus, hypothalamus, and amygdala. In dependent animals and during withdrawal, there was no change in Srd5a1 expression in cortex or hippocampus, which differed from our recent findings in dissected tissues. These results suggest that local Srd5a1 mRNA expression in WSP brain may not change in parallel with local ALLO content or withdrawal severity. Published by Elsevier Inc.

Localization of Brain 5α-Reductase Messenger RNA in Mice Selectively Bred for High Chronic Alcohol Withdrawal Severity

PubMed Central

Roselli, Charles E.; Finn, Tim J.; Ronnekleiv-Kelly, Sean M.; Tanchuck, Michelle A.; Kaufman, Katherine R.; Finn, Deborah A.

2011-01-01

Several lines of evidence suggest that fluctuations in endogenous levels of the γ-aminobutyric acid (GABA)ergic neurosteroid allopregnanolone (ALLO) represent one mechanism for regulation of GABAergic inhibitory tone in the brain, with an ultimate impact on behavior. Consistent with this idea, there was an inverse relationship between ALLO levels and symptoms of anxiety and depression in humans and convulsive activity in rodents during alcohol withdrawal. Our recent studies examined activity and expression of 5α-reductase (Srd5a1), the rate-limiting enzyme in the biosynthesis of ALLO, during alcohol withdrawal in mice selectively bred for high chronic alcohol withdrawal (Withdrawal Seizure-Prone, WSP) and found that Srd5a1 was down-regulated in the cortex and hippocampus over the time course of dependence and withdrawal. The purpose of the present studies was to extend these findings and more discretely map the regions of Srd5a1 expression in mouse brain using radioactive in situ hybridization in WSP mice that were ethanol naïve, following exposure to 72 h ethanol vapor (dependent) or during peak withdrawal. In naïve animals, expression of Srd5a1 was widely distributed throughout the mouse brain, with highest expression in specific regions of the cerebral cortex, hippocampus, thalamus, hypothalamus, and amygdala. In dependent animals and during withdrawal, there was no change in Srd5a1 expression in cortex or hippocampus, which differed from our recent findings in dissected tissues. These results suggest that local Srd5a1 mRNA expression in WSP brain may not change in parallel with local ALLO content or withdrawal severity. PMID:21917407

Role of psl Genes in Antibiotic Tolerance of Adherent Pseudomonas aeruginosa.

PubMed

Murakami, Keiji; Ono, Tsuneko; Viducic, Darija; Somiya, Yoko; Kariyama, Reiko; Hori, Kenji; Amoh, Takashi; Hirota, Katsuhiko; Kumon, Hiromi; Parsek, Matthew R; Miyake, Yoichiro

2017-07-01

Bacteria attached to a surface are generally more tolerant to antibiotics than their planktonic counterparts, even without the formation of a biofilm. The mechanism of antibiotic tolerance in biofilm communities is multifactorial, and the genetic background underlying this antibiotic tolerance has not yet been fully elucidated. Using transposon mutagenesis, we isolated a mutant with reduced tolerance to biapenem (relative to that of the wild type) from adherent cells. Sequencing analysis revealed a mutation in the pslL gene, which is part of the polysaccharide biosynthesis operon. The Pseudomonas aeruginosa PAO1Δ pslBCD mutant demonstrated a 100-fold-lower survival rate during the exposure of planktonic and biofilm cells to biapenem; a similar phenotype was observed in a mouse infection model and in clinical strains. Transcriptional analysis of adherent cells revealed increased expression of both pslA and pelA , which are directly regulated by bis-(3',5')-cyclic dimeric GMP (c-di-GMP). Inactivation of wspF resulted in significantly increased tolerance to biapenem due to increased production of c-di-GMP. The loss of pslBCD in the Δ wspF mutant background abolished the biapenem-tolerant phenotype of the Δ wspF mutant, underscoring the importance of psl in biapenem tolerance. Overexpression of PA2133, which can catalyze the degradation of c-di-GMP, led to a significant reduction in biapenem tolerance in adherent cells, indicating that c-di-GMP is essential in mediating the tolerance effect. The effect of pslBCD on antibiotic tolerance was evident, with 50- and 200-fold-lower survival in the presence of ofloxacin and tobramycin, respectively. We speculate that the psl genes, which are activated by surface adherence through elevated intracellular c-di-GMP levels, confer tolerance to antimicrobials. Copyright © 2017 American Society for Microbiology.

A hybrid algorithm for parallel molecular dynamics simulations

NASA Astrophysics Data System (ADS)

Mangiardi, Chris M.; Meyer, R.

2017-10-01

This article describes algorithms for the hybrid parallelization and SIMD vectorization of molecular dynamics simulations with short-range forces. The parallelization method combines domain decomposition with a thread-based parallelization approach. The goal of the work is to enable efficient simulations of very large (tens of millions of atoms) and inhomogeneous systems on many-core processors with hundreds or thousands of cores and SIMD units with large vector sizes. In order to test the efficiency of the method, simulations of a variety of configurations with up to 74 million atoms have been performed. Results are shown that were obtained on multi-core systems with Sandy Bridge and Haswell processors as well as systems with Xeon Phi many-core processors.

Communication System and Method

NASA Technical Reports Server (NTRS)

Sanders, Adam M. (Inventor); Strawser, Philip A. (Inventor)

2014-01-01

A communication system for communicating over high-latency, low bandwidth networks includes a communications processor configured to receive a collection of data from a local system, and a transceiver in communication with the communications processor. The transceiver is configured to transmit and receive data over a network according to a plurality of communication parameters. The communications processor is configured to divide the collection of data into a plurality of data streams; assign a priority level to each of the respective data streams, where the priority level reflects the criticality of the respective data stream; and modify a communication parameter of at least one of the plurality of data streams according to the priority of the at least one data stream.

Ssip-a processor interconnection simulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Navaux, P.; Weber, R.; Prezzi, J.

1982-01-01

Recent growing interest in multiple processor architectures has given rise to the study of procesor-memory interconnections for the determination of better architectures. This paper concerns the development of the SSIP-sistema simulador de interconexao de processadores (processor interconnection simulating system) which allows the evaluation of different interconnection structures comparing its performance in order to provide parameters which would help the designer to define an architcture. A wide spectrum of systems may be evaluated, and their behaviour observed due to the features incorporated into the simulator program. The system modelling and the simulator program implementation are described. Some results that can bemore » obtained are shown, along with the discussion of their usefulness. 12 references.« less

The DISCUS Hardware System,

DTIC Science & Technology

1982-07-01

blocks. DISCUS has no form of hardware synchronisation between the processors. The only synchronisation is at an operating system level. ;ach processor is... operations in global store so that semaphoring on global objects can be done correctly. Write Protect is used by the operating system for read-only...the appropriate operating system program. String Handling primitives . The Z8000 has a rich set of string primitives . However as we saw before if a

Embedded Data Processor and Portable Computer Technology testbeds

NASA Technical Reports Server (NTRS)

Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

1993-01-01

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Advanced Avionics and Processor Systems for Space and Lunar Exploration

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Ray, Robert E.; Johnson, Michael A.; Cressler, John D.

2009-01-01

NASA's newly named Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to mature and develop the avionic and processor technologies required to fulfill NASA's goals for future space and lunar exploration. Over the past year, multiple advancements have been made within each of the individual AAPS technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of the project's recent technology advancements, discusses their application to Constellation projects, and addresses the project's plans for the coming year.

Parallel object-oriented, denoising system using wavelet multiresolution analysis

DOEpatents

Kamath, Chandrika; Baldwin, Chuck H.; Fodor, Imola K.; Tang, Nu A.

2005-04-12

The present invention provides a data de-noising system utilizing processors and wavelet denoising techniques. Data is read and displayed in different formats. The data is partitioned into regions and the regions are distributed onto the processors. Communication requirements are determined among the processors according to the wavelet denoising technique and the partitioning of the data. The data is transforming onto different multiresolution levels with the wavelet transform according to the wavelet denoising technique, the communication requirements, and the transformed data containing wavelet coefficients. The denoised data is then transformed into its original reading and displaying data format.

A distributed fault-tolerant signal processor /FTSP/

NASA Astrophysics Data System (ADS)

Bonneau, R. J.; Evett, R. C.; Young, M. J.

1980-01-01

A digital fault-tolerant signal processor (FTSP), an example of a self-repairing programmable system is analyzed. The design configuration is discussed in terms of fault tolerance, system-level fault detection, isolation and common memory. Special attention is given to the FDIR (fault detection isolation and reconfiguration) logic, noting that the reconfiguration decisions are based on configuration, summary status, end-around tests, and north marker/synchro data. Several mechanisms of fault detection are described which initiate reconfiguration at different levels. It is concluded that the reliability of a signal processor can be significantly enhanced by the use of fault-tolerant techniques.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems.

PubMed

Downie, J D; Goodman, J W

1989-10-15

A ground-based adaptive optics imaging telescope system attempts to improve image quality by measuring and correcting for atmospherically induced wavefront aberrations. The necessary control computations during each cycle will take a finite amount of time, which adds to the residual error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper investigates this possibility by studying the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for adaptive optics use.

Applications considerations in the system design of highly concurrent multiprocessors

NASA Technical Reports Server (NTRS)

Lundstrom, Stephen F.

1987-01-01

A flow model processor approach to parallel processing is described, using very-high-performance individual processors, high-speed circuit switched interconnection networks, and a high-speed synchronization capability to minimize the effect of the inherently serial portions of applications on performance. Design studies related to the determination of the number of processors, the memory organization, and the structure of the networks used to interconnect the processor and memory resources are discussed. Simulations indicate that applications centered on the large shared data memory should be able to sustain over 500 million floating point operations per second.

Data acquisition using the 168/E. [CERN ISR

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, J.T.; Cittolin, S.; Demoulin, M.

1983-03-01

Event sizes and data rates at the CERN anti p p collider compose a formidable environment for a high level trigger. A system using three 168/E processors for experiment UA1 real-time event selection is described. With 168/E data memory expanded to 512K bytes, each processor holds a complete event allowing a FORTRAN trigger algorithm access to data from the entire detector. A smart CAMAC interface reads five Remus branches in parallel transferring one word to the target processor every 0.5 ..mu..s. The NORD host computer can simultaneously read an accepted event from another processor.

An architecture for real-time vision processing

NASA Technical Reports Server (NTRS)

Chien, Chiun-Hong

1994-01-01

To study the feasibility of developing an architecture for real time vision processing, a task queue server and parallel algorithms for two vision operations were designed and implemented on an i860-based Mercury Computing System 860VS array processor. The proposed architecture treats each vision function as a task or set of tasks which may be recursively divided into subtasks and processed by multiple processors coordinated by a task queue server accessible by all processors. Each idle processor subsequently fetches a task and associated data from the task queue server for processing and posts the result to shared memory for later use. Load balancing can be carried out within the processing system without the requirement for a centralized controller. The author concludes that real time vision processing cannot be achieved without both sequential and parallel vision algorithms and a good parallel vision architecture.

Parallel solution of closely coupled systems

NASA Technical Reports Server (NTRS)

Utku, S.; Salama, M.

1986-01-01

The odd-even permutation and associated unitary transformations for reordering the matrix coefficient A are employed as means of breaking the strong seriality which is characteristic of closely coupled systems. The nested dissection technique is also reviewed, and the equivalence between reordering A and dissecting its network is established. The effect of transforming A with odd-even permutation on its topology and the topology of its Cholesky factors is discussed. This leads to the construction of directed graphs showing the computational steps required for factoring A, their precedence relationships and their sequential and concurrent assignment to the available processors. Expressions for the speed-up and efficiency of using N processors in parallel relative to the sequential use of a single processor are derived from the directed graph. Similar expressions are also derived when the number of available processors is fewer than required.

Towards the formal verification of the requirements and design of a processor interface unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

The formal verification of the design and partial requirements for a Processor Interface Unit (PIU) using the Higher Order Logic (HOL) theorem-proving system is described. The processor interface unit is a single-chip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. It provides the opportunity to investigate the specification and verification of a real-world subsystem within a commercially-developed fault-tolerant computer. An overview of the PIU verification effort is given. The actual HOL listing from the verification effort are documented in a companion NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings' including the general-purpose HOL theories and definitions that support the PIU verification as well as tactics used in the proofs.

47 CFR 36.123 - Operator systems equipment-Category 1.

Code of Federal Regulations, 2014 CFR

2014-10-01

... apportioned on the basis of the relative processor real time (i.e., actual seconds) required to process TSPS... relative processor real time (i.e., actual seconds) for the entire TSPS complex. [52 FR 17229, May 6, 1987... 47 Telecommunication 2 2014-10-01 2014-10-01 false Operator systems equipment-Category 1. 36.123...

47 CFR 36.123 - Operator systems equipment-Category 1.

Code of Federal Regulations, 2013 CFR

2013-10-01

... apportioned on the basis of the relative processor real time (i.e., actual seconds) required to process TSPS... relative processor real time (i.e., actual seconds) for the entire TSPS complex. [52 FR 17229, May 6, 1987... 47 Telecommunication 2 2013-10-01 2013-10-01 false Operator systems equipment-Category 1. 36.123...

47 CFR 36.123 - Operator systems equipment-Category 1.

Code of Federal Regulations, 2012 CFR

2012-10-01

... apportioned on the basis of the relative processor real time (i.e., actual seconds) required to process TSPS... relative processor real time (i.e., actual seconds) for the entire TSPS complex. [52 FR 17229, May 6, 1987... 47 Telecommunication 2 2012-10-01 2012-10-01 false Operator systems equipment-Category 1. 36.123...

47 CFR 36.123 - Operator systems equipment-Category 1.

Code of Federal Regulations, 2011 CFR

2011-10-01

... apportioned on the basis of the relative processor real time (i.e., actual seconds) required to process TSPS... relative processor real time (i.e., actual seconds) for the entire TSPS complex. [52 FR 17229, May 6, 1987... 47 Telecommunication 2 2011-10-01 2011-10-01 false Operator systems equipment-Category 1. 36.123...

47 CFR 36.123 - Operator systems equipment-Category 1.

Code of Federal Regulations, 2010 CFR

2010-10-01

... apportioned on the basis of the relative processor real time (i.e., actual seconds) required to process TSPS... relative processor real time (i.e., actual seconds) for the entire TSPS complex. [52 FR 17229, May 6, 1987... 47 Telecommunication 2 2010-10-01 2010-10-01 false Operator systems equipment-Category 1. 36.123...

A Framework for a Quality Control System for Vendor/Processor Contracts.

ERIC Educational Resources Information Center

Advanced Technology, Inc., Reston, VA.

A framework for monitoring quality control (QC) of processor contracts administered by the Department of Education's Office of Student Financial Assistance (OSFA) is presented and applied to the Pell Grant program. Guidelines for establishing QC measures and standards are included, and the uses of a sampling procedure in the QC system are…

Software design and implementation of ship heave motion monitoring system based on MBD method

NASA Astrophysics Data System (ADS)

Yu, Yan; Li, Yuhan; Zhang, Chunwei; Kang, Won-Hee; Ou, Jinping

2015-03-01

Marine transportation plays a significant role in the modern transport sector due to its advantage of low cost, large capacity. It is being attached enormous importance to all over the world. Nowadays the related areas of product development have become an existing hot spot. DSP signal processors feature micro volume, low cost, high precision, fast processing speed, which has been widely used in all kinds of monitoring systems. But traditional DSP code development process is time-consuming, inefficiency, costly and difficult. MathWorks company proposed Model-based Design (MBD) to overcome these defects. By calling the target board modules in simulink library to compile and generate the corresponding code for the target processor. And then automatically call DSP integrated development environment CCS for algorithm validation on the target processor. This paper uses the MDB to design the algorithm for the ship heave motion monitoring system. It proves the effectiveness of the MBD run successfully on the processor.

a Real-Time Computer Music Synthesis System

NASA Astrophysics Data System (ADS)

Lent, Keith Henry

A real time sound synthesis system has been developed at the Computer Music Center of The University of Texas at Austin. This system consists of several stand alone processors that were constructed jointly with White Instruments in Austin. These processors can be programmed as general purpose computers, but are provided with a number of specialized interfaces including: MIDI, 8 bit parallel, high speed serial, 2 channels analog input (18 bit A/Ds, 48kHz sample rate), and 4 channels analog output (18 bit D/As). In addition, a basic music synthesis language (Music56000) has been written in assembly code. On top of this, a symbolic compiler (PatchWork) has been developed to enable algorithms which run in these processors to be created graphically. And finally, a number of efficient time domain numerical models have been developed to enable the construction, simulation, control, and synthesis of many musical acoustics systems in real time on these processors. Specifically, assembly language models for cylindrical and conical horn sections, dissipative losses, tone holes, bells, and a number of linear and nonlinear boundary conditions have been developed.

Landsat image registration for agricultural applications

NASA Technical Reports Server (NTRS)

Wolfe, R. H., Jr.; Juday, R. D.; Wacker, A. G.; Kaneko, T.

1982-01-01

An image registration system has been developed at the NASA Johnson Space Center (JSC) to spatially align multi-temporal Landsat acquisitions for use in agriculture and forestry research. Working in conjunction with the Master Data Processor (MDP) at the Goddard Space Flight Center, it functionally replaces the long-standing LACIE Registration Processor as JSC's data supplier. The system represents an expansion of the techniques developed for the MDP and LACIE Registration Processor, and it utilizes the experience gained in an IBM/JSC effort evaluating the performance of the latter. These techniques are discussed in detail. Several tests were developed to evaluate the registration performance of the system. The results indicate that 1/15-pixel accuracy (about 4m for Landsat MSS) is achievable in ideal circumstances, sub-pixel accuracy (often to 0.2 pixel or better) was attained on a representative set of U.S. acquisitions, and a success rate commensurate with the LACIE Registration Processor was realized. The system has been employed in a production mode on U.S. and foreign data, and a performance similar to the earlier tests has been noted.

Assessment of spray deposition with water-sensitive paper cards

USDA-ARS?s Scientific Manuscript database

Spatial distributions of spray droplets discharged from an airblast sprayer, were sampled on pairs of absorbent paper (AP) and water-sensitive paper (WSP) targets at several distances from the sprayer. Spray solutions, containing a fluorescent tracer, were discharged from two size nozzles to achiev...

Software dependability in the Tandem GUARDIAN system

NASA Technical Reports Server (NTRS)

Lee, Inhwan; Iyer, Ravishankar K.

1995-01-01

Based on extensive field failure data for Tandem's GUARDIAN operating system this paper discusses evaluation of the dependability of operational software. Software faults considered are major defects that result in processor failures and invoke backup processes to take over. The paper categorizes the underlying causes of software failures and evaluates the effectiveness of the process pair technique in tolerating software faults. A model to describe the impact of software faults on the reliability of an overall system is proposed. The model is used to evaluate the significance of key factors that determine software dependability and to identify areas for improvement. An analysis of the data shows that about 77% of processor failures that are initially considered due to software are confirmed as software problems. The analysis shows that the use of process pairs to provide checkpointing and restart (originally intended for tolerating hardware faults) allows the system to tolerate about 75% of reported software faults that result in processor failures. The loose coupling between processors, which results in the backup execution (the processor state and the sequence of events) being different from the original execution, is a major reason for the measured software fault tolerance. Over two-thirds (72%) of measured software failures are recurrences of previously reported faults. Modeling, based on the data, shows that, in addition to reducing the number of software faults, software dependability can be enhanced by reducing the recurrence rate.

Onboard processor technology review

NASA Technical Reports Server (NTRS)

Benz, Harry F.

1990-01-01

The general need and requirements for the onboard embedded processors necessary to control and manipulate data in spacecraft systems are discussed. The current known requirements are reviewed from a user perspective, based on current practices in the spacecraft development process. The current capabilities of available processor technologies are then discussed, and these are projected to the generation of spacecraft computers currently under identified, funded development. An appraisal is provided for the current national developmental effort.

Accuracy-energy configurable sensor processor and IoT device for long-term activity monitoring in rare-event sensing applications.

PubMed

Park, Daejin; Cho, Jeonghun

2014-01-01

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error.

Clinical Validation of a Sound Processor Upgrade in Direct Acoustic Cochlear Implant Subjects

PubMed Central

Kludt, Eugen; D’hondt, Christiane; Lenarz, Thomas; Maier, Hannes

2017-01-01

Objective: The objectives of the investigation were to evaluate the effect of a sound processor upgrade on the speech reception threshold in noise and to collect long-term safety and efficacy data after 2½ to 5 years of device use of direct acoustic cochlear implant (DACI) recipients. Study Design: The study was designed as a mono-centric, prospective clinical trial. Setting: Tertiary referral center. Patients: Fifteen patients implanted with a direct acoustic cochlear implant. Intervention: Upgrade with a newer generation of sound processor. Main Outcome Measures: Speech recognition test in quiet and in noise, pure tone thresholds, subject-reported outcome measures. Results: The speech recognition in quiet and in noise is superior after the sound processor upgrade and stable after long-term use of the direct acoustic cochlear implant. The bone conduction thresholds did not decrease significantly after long-term high level stimulation. Conclusions: The new sound processor for the DACI system provides significant benefits for DACI users for speech recognition in both quiet and noise. Especially the noise program with the use of directional microphones (Zoom) allows DACI patients to have much less difficulty when having conversations in noisy environments. Furthermore, the study confirms that the benefits of the sound processor upgrade are available to the DACI recipients even after several years of experience with a legacy sound processor. Finally, our study demonstrates that the DACI system is a safe and effective long-term therapy. PMID:28406848

Software Acquisition Manager’s Workstation (SAM/WS) System Design.

DTIC Science & Technology

1984-04-30

3. Tactical Digital System Requirements ..................... 31General...pspc t14 3. Tactical Digital System Requirements pspc-tiS 3.1 General pspc-t16 3.2 Program Description pspc-t17 3.2.1 General...pspc-t22 3.3.2 Digital Processor Input/Output Utilization Table pspc t23 3.3.3 Digital Processor Interface Block Diagram pspc-t24 3.3.4 Program

Software for embedded processors: Problems and solutions

NASA Astrophysics Data System (ADS)

Bogaerts, J. A. C.

1990-08-01

Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I/O bandwidth, the traditional key parameters of a HEP data acquisition system. Software engineering and real time system simulation tools are becoming indispensible for the design of future data acquisition systems.

A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

PubMed

Izumi, Shintaro; Yamashita, Ken; Nakano, Masanao; Kawaguchi, Hiroshi; Kimura, Hiromitsu; Marumoto, Kyoji; Fuchikami, Takaaki; Fujimori, Yoshikazu; Nakajima, Hiroshi; Shiga, Toshikazu; Yoshimoto, Masahiko

2015-10-01

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

Cache Energy Optimization Techniques For Modern Processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

2013-01-01

Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In thismore » book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both newcomers and veterans in the field of cache power management. It will help graduate students, CAD tool developers and designers in understanding the need of energy efficiency in modern computing systems. Further, it will be useful for researchers in gaining insights into algorithms and techniques for micro-architectural and system-level energy optimization using dynamic cache reconfiguration. We sincerely believe that the ``food for thought'' presented in this book will inspire the readers to develop even better ideas for designing ``green'' processors of tomorrow.« less

Design and implementation of highly parallel pipelined VLSI systems

NASA Astrophysics Data System (ADS)

Delange, Alphonsus Anthonius Jozef

A methodology and its realization as a prototype CAD (Computer Aided Design) system for the design and analysis of complex multiprocessor systems is presented. The design is an iterative process in which the behavioral specifications of the system components are refined into structural descriptions consisting of interconnections and lower level components etc. A model for the representation and analysis of multiprocessor systems at several levels of abstraction and an implementation of a CAD system based on this model are described. A high level design language, an object oriented development kit for tool design, a design data management system, and design and analysis tools such as a high level simulator and graphics design interface which are integrated into the prototype system and graphics interface are described. Procedures for the synthesis of semiregular processor arrays, and to compute the switching of input/output signals, memory management and control of processor array, and sequencing and segmentation of input/output data streams due to partitioning and clustering of the processor array during the subsequent synthesis steps, are described. The architecture and control of a parallel system is designed and each component mapped to a module or module generator in a symbolic layout library, compacted for design rules of VLSI (Very Large Scale Integration) technology. An example of the design of a processor that is a useful building block for highly parallel pipelined systems in the signal/image processing domains is given.

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

The computational structural mechanics testbed architecture. Volume 2: The interface

NASA Technical Reports Server (NTRS)

Felippa, Carlos A.

1988-01-01

This is the third set of five volumes which describe the software architecture for the Computational Structural Mechanics Testbed. Derived from NICE, an integrated software system developed at Lockheed Palo Alto Research Laboratory, the architecture is composed of the command language CLAMP, the command language interpreter CLIP, and the data manager GAL. Volumes 1, 2, and 3 (NASA CR's 178384, 178385, and 178386, respectively) describe CLAMP and CLIP and the CLIP-processor interface. Volumes 4 and 5 (NASA CR's 178387 and 178388, respectively) describe GAL and its low-level I/O. CLAMP, an acronym for Command Language for Applied Mechanics Processors, is designed to control the flow of execution of processors written for NICE. Volume 3 describes the CLIP-Processor interface and related topics. It is intended only for processor developers.

Accelerated convergence for synchronous approximate agreement

NASA Technical Reports Server (NTRS)

Kearns, J. P.; Park, S. K.; Sjogren, J. A.

1988-01-01

The protocol for synchronous approximate agreement presented by Dolev et. al. exhibits the undesirable property that a faulty processor, by the dissemination of a value arbitrarily far removed from the values held by good processors, may delay the termination of the protocol by an arbitrary amount of time. Such behavior is clearly undesirable in a fault tolerant dynamic system subject to hard real-time constraints. A mechanism is presented by which editing data suspected of being from Byzantine-failed processors can lead to quicker, predictable, convergence to an agreement value. Under specific assumptions about the nature of values transmitted by failed processors relative to those transmitted by good processors, a Monte Carlo simulation is presented whose qualitative results illustrate the trade-off between accelerated convergence and the accuracy of the value agreed upon.

Fuel processors for fuel cell APU applications

NASA Astrophysics Data System (ADS)

Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

Optical Potential Field Mapping System

NASA Technical Reports Server (NTRS)

Reid, Max B. (Inventor)

1996-01-01

The present invention relates to an optical system for creating a potential field map of a bounded two dimensional region containing a goal location and an arbitrary number of obstacles. The potential field mapping system has an imaging device and a processor. Two image writing modes are used by the imaging device, electron deposition and electron depletion. Patterns written in electron deposition mode appear black and expand. Patterns written in electron depletion mode are sharp and appear white. The generated image represents a robot's workspace. The imaging device under processor control then writes a goal location in the work-space using the electron deposition mode. The black image of the goal expands in the workspace. The processor stores the generated images, and uses them to generate a feedback pattern. The feedback pattern is written in the workspace by the imaging device in the electron deposition mode to enhance the expansion of the original goal pattern. After the feedback pattern is written, an obstacle pattern is written by the imaging device in the electron depletion mode to represent the obstacles in the robot's workspace. The processor compares a stored image to a previously stored image to determine a change therebetween. When no change occurs, the processor averages the stored images to produce the potential field map.

Performance evaluation of a newly developed variable rate sprayer for nursery liner applications

USDA-ARS?s Scientific Manuscript database

An experimental variable-rate sprayer designed for liner applications was tested by comparing its spray deposit, coverage, and droplet density inside canopies of six nursery liner varieties with constant-rate applications. Spray samplers, including water sensitive papers (WSP) and nylon screens, wer...

System and method for cognitive processing for data fusion

NASA Technical Reports Server (NTRS)

Duong, Tuan A. (Inventor); Duong, Vu A. (Inventor)

2012-01-01

A system and method for cognitive processing of sensor data. A processor array receiving analog sensor data and having programmable interconnects, multiplication weights, and filters provides for adaptive learning in real-time. A static random access memory contains the programmable data for the processor array and the stored data is modified to provide for adaptive learning.

Tailoring Software for Multiple Processor Systems

DTIC Science & Technology

1982-10-01

resource management decisions . Despite the lack of programming support, the use of multiple processor systems has grown sub- -stantially. Software has...making resource management decisions . Specifically, program- 1 mers need not allocate specific hardware resources to individual program components...Instead, such allocation decisions are automatically made based on high-level resource directives stated by ap- plication programmers, where each directive

Closing the Gap: Cybersecurity for U.S. Forces and Commands

DTIC Science & Technology

2017-03-30

Dickson, Ph.D. Professor of Military Studies , JAWS Thesis Advisor Kevin Therrien, Col, USAF Committee Member Stephen Rogers, Colonel, USA Director...infrastructures, and includes the Internet, telecommunications networks, computer systems, and embedded processors and controllers in critical industries.”5...of information technology infrastructures, including the Internet, telecommunications networks, computer systems, and embedded processors and

The Minerva Multi-Microprocessor.

DTIC Science & Technology

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.

Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

NASA Astrophysics Data System (ADS)

Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

2007-04-01

In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

A natural-gas fuel processor for a residential fuel cell system

NASA Astrophysics Data System (ADS)

Adachi, H.; Ahmed, S.; Lee, S. H. D.; Papadias, D.; Ahluwalia, R. K.; Bendert, J. C.; Kanner, S. A.; Yamazaki, Y.

A system model was used to develop an autothermal reforming fuel processor to meet the targets of 80% efficiency (higher heating value) and start-up energy consumption of less than 500 kJ when operated as part of a 1-kWe natural-gas fueled fuel cell system for cogeneration of heat and power. The key catalytic reactors of the fuel processor - namely the autothermal reformer, a two-stage water gas shift reactor and a preferential oxidation reactor - were configured and tested in a breadboard apparatus. Experimental results demonstrated a reformate containing ∼48% hydrogen (on a dry basis and with pure methane as fuel) and less than 5 ppm CO. The effects of steam-to-carbon and part load operations were explored.

ARTS III/Parallel Processor Design Study

DOT National Transportation Integrated Search

1975-04-01

It was the purpose of this design study to investigate the feasibility, suitability, and cost-effectiveness of augmenting the ARTS III failsafe/failsoft multiprocessor system with a form of parallel processor to accomodate a large growth in air traff...

Extraction of Volatiles from Regolith or Soil on Mars, the Moon, and Asteroids

NASA Technical Reports Server (NTRS)

Linne, Diane; Kleinhenz, Julie; Trunek, Andrew; Hoffman, Stephen; Collins, Jacob

2017-01-01

NASA's Advanced Exploration Systems ISRU Technology Project is evaluating concepts to extract water from all resource types Near-term objectives: Produce high-fidelity mass, power, and volume estimates for mining and processing systems Identify critical challenges for development focus Begin demonstration of component and subsystem technologies in relevant environment Several processor types: Closed processors either partially or completely sealed during processing Open air processors operates at Mars ambient conditions In-situ processors Extract product directly without excavation of raw resource Design features Elimination of sweep gas reduces dust particles in water condensate Pressure maintained by height of soil in hopper Model developed to evaluate key design parameters Geometry: conveyor diameter, screw diameter, shaft diameter, flight spacing and pitch Operational: screw speed vs. screw length (residence time) Thermal: Heat flux, heat transfer to soil Testing to demonstrate feasibility and performance Agglomeration, clogging Pressure rise forced flow to condenser.

Systems and Methods for Automated Vessel Navigation Using Sea State Prediction

NASA Technical Reports Server (NTRS)

Huntsberger, Terrance L. (Inventor); Howard, Andrew B. (Inventor); Reinhart, Rene Felix (Inventor); Aghazarian, Hrand (Inventor); Rankin, Arturo (Inventor)

2017-01-01

Systems and methods for sea state prediction and autonomous navigation in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes a method of predicting a future sea state including generating a sequence of at least two 3D images of a sea surface using at least two image sensors, detecting peaks and troughs in the 3D images using a processor, identifying at least one wavefront in each 3D image based upon the detected peaks and troughs using the processor, characterizing at least one propagating wave based upon the propagation of wavefronts detected in the sequence of 3D images using the processor, and predicting a future sea state using at least one propagating wave characterizing the propagation of wavefronts in the sequence of 3D images using the processor. Another embodiment includes a method of autonomous vessel navigation based upon a predicted sea state and target location.

Systems and Methods for Automated Vessel Navigation Using Sea State Prediction

NASA Technical Reports Server (NTRS)

Aghazarian, Hrand (Inventor); Reinhart, Rene Felix (Inventor); Huntsberger, Terrance L. (Inventor); Rankin, Arturo (Inventor); Howard, Andrew B. (Inventor)

2015-01-01

Systems and methods for sea state prediction and autonomous navigation in accordance with embodiments of the invention are disclosed. One embodiment of the invention includes a method of predicting a future sea state including generating a sequence of at least two 3D images of a sea surface using at least two image sensors, detecting peaks and troughs in the 3D images using a processor, identifying at least one wavefront in each 3D image based upon the detected peaks and troughs using the processor, characterizing at least one propagating wave based upon the propagation of wavefronts detected in the sequence of 3D images using the processor, and predicting a future sea state using at least one propagating wave characterizing the propagation of wavefronts in the sequence of 3D images using the processor. Another embodiment includes a method of autonomous vessel navigation based upon a predicted sea state and target location.

System Architecture For High Speed Sorting Of Potatoes

NASA Astrophysics Data System (ADS)

Marchant, J. A.; Onyango, C. M.; Street, M. J.

1989-03-01

This paper illustrates an industrial application of vision processing in which potatoes are sorted according to their size and shape at speeds of up to 40 objects per second. The result is a multi-processing approach built around the VME bus. A hardware unit has been designed and constructed to encode the boundary of the potatoes, to reducing the amount of data to be processed. A master 68000 processor is used to control this unit and to handle data transfers along the bus. Boundary data is passed to one of three 68010 slave processors each responsible for a line of potatoes across a conveyor belt. The slave processors calculate attributes such as shape, size and estimated weight of each potato and the master processor uses this data to operate the sorting mechanism. The system has been interfaced with a commercial grading machine and performance trials are now in progress.

Interconnect Performance Evaluation of SGI Altix 3700 BX2, Cray X1, Cray Opteron Cluster, and Dell PowerEdge

NASA Technical Reports Server (NTRS)

Fatoohi, Rod; Saini, Subbash; Ciotti, Robert

2006-01-01

We study the performance of inter-process communication on four high-speed multiprocessor systems using a set of communication benchmarks. The goal is to identify certain limiting factors and bottlenecks with the interconnect of these systems as well as to compare these interconnects. We measured network bandwidth using different number of communicating processors and communication patterns, such as point-to-point communication, collective communication, and dense communication patterns. The four platforms are: a 512-processor SGI Altix 3700 BX2 shared-memory machine with 3.2 GB/s links; a 64-processor (single-streaming) Cray XI shared-memory machine with 32 1.6 GB/s links; a 128-processor Cray Opteron cluster using a Myrinet network; and a 1280-node Dell PowerEdge cluster with an InfiniBand network. Our, results show the impact of the network bandwidth and topology on the overall performance of each interconnect.

Apparatus, system, and method for synchronizing a timer key

DOEpatents

Condit, Reston A; Daniels, Michael A; Clemens, Gregory P; Tomberlin, Eric S; Johnson, Joel A

2014-04-22

A timer key relating to monitoring a countdown time of a countdown routine of an electronic device is disclosed. The timer key comprises a processor configured to respond to a countdown time associated with operation of the electronic device, a display operably coupled with the processor, and a housing configured to house at least the processor. The housing has an associated structure configured to engage with the electronic device to share the countdown time between the electronic device and the timer key. The processor is configured to begin a countdown routine based at least in part on the countdown time, wherein the countdown routine is at least substantially synchronized with a countdown routine of the electronic device when the timer key is removed from the electronic device. A system and method for synchronizing countdown routines of a timer key and an electronic device are also disclosed.

Asynchronous Communication Scheme For Hypercube Computer

NASA Technical Reports Server (NTRS)

Madan, Herb S.

1988-01-01

Scheme devised for asynchronous-message communication system for Mark III hypercube concurrent-processor network. Network consists of up to 1,024 processing elements connected electrically as though were at corners of 10-dimensional cube. Each node contains two Motorola 68020 processors along with Motorola 68881 floating-point processor utilizing up to 4 megabytes of shared dynamic random-access memory. Scheme intended to support applications requiring passage of both polled or solicited and unsolicited messages.

Tactical Operations Analysis Support Facility.

DTIC Science & Technology

1981-05-01

Punch/Reader 2 DMC-11AR DDCMP Micro Processor 2 DMC-11DA Network Link Line Unit 2 DL-11E Async Serial Line Interface 4 Intel IN-1670 448K Words MOS Memory...86 5.3 VIRTUAL PROCESSORS - VAX-11/750 ........................... 89 5.4 A RELATIONAL DATA MANAGEMENT SYSTEM - ORACLE...Central Processing Unit (CPU) is a 16 bit processor for high-speed, real time applications, and for large multi-user, multi- task, time shared

Application of Prognostic Health Management in Digital Electronic Systems

DTIC Science & Technology

2007-01-01

variable external supply applied the necessary core power to the processor while the motherboard continued to source power from the ATX supply. By...isolating the processor power from the motherboard power , control over the aging profile of the processor was achieved. Once nominal operating...Physics-of-failure RISC – Reduced Instruction Set Computer RUL – Remaining Useful Life 1 1-4244-0525-4/07/$20.00 ©2007 IEEE. Paper 1326

Through-the-earth radio

DOEpatents

Reagor, David; Vasquez-Dominguez, Jose

2006-12-12

A through-the-earth communication system that includes a digital signal input device; a transmitter operating at a predetermined frequency sufficiently low to effectively penetrate useful distances through-the earth; a data compression circuit that is connected to an encoding processor; an amplifier that receives encoded output from the encoding processor for amplifying the output and transmitting the data to an antenna; and a receiver with an antenna, a band pass filter, a decoding processor, and a data decompressor.

Design of an Ada expert system shell for the VHSIC avionic modular flight processor

NASA Technical Reports Server (NTRS)

Fanning, F. Jesse

1992-01-01

The Embedded Computer System Expert System Shell (ES Shell) is an Ada-based expert system shell developed at the Avionics Laboratory for use on the VHSIC Avionic Modular Processor (VAMP) running under the Ada Avionics Real-Time Software (AARTS) Operating System. The ES Shell provides the interface between the expert system and the avionics environment, and controls execution of the expert system. Testing of the ES Shell in the Avionics Laboratory's Integrated Test Bed (ITB) has demonstrated its ability to control a non-deterministic software application executing on the VAMP's which can control the ITB's real-time closed-loop aircraft simulation. The results of these tests and the conclusions reached in the design and development of the ES Shell have played an important role in the formulation of the requirements for a production-quality expert system inference engine, an ingredient necessary for the successful use of expert systems on the VAMP embedded avionic flight processor.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Method of implementation of optoelectronic multiparametric signal processing systems based on multivalued-logic principles

NASA Astrophysics Data System (ADS)

Arestova, M. L.; Bykovskii, A. Yu

1995-10-01

An architecture is proposed for a specialised optoelectronic multivalued logic processor based on the Allen—Givone algebra. The processor is intended for multiparametric processing of data arriving from a large number of sensors or for tackling spectral analysis tasks. The processor architecture makes it possible to obtain an approximate general estimate of the state of an object being diagnosed on a p-level scale. Optoelectronic systems are proposed for MAXIMUM, MINIMUM, and LITERAL logic gates, based on optical-frequency encoding of logic levels. Corresponding logic gates form a complete set of logic functions in the Allen—Givone algebra.

Frequency-multiplexed and pipelined iterative optical systolic array processors

NASA Technical Reports Server (NTRS)

Casasent, D.; Jackson, J.; Neuman, C.

1983-01-01

Optical matrix processors using acoustooptic transducers are described, with emphasis on new systolic array architectures using frequency multiplexing in addition to space and time multiplexing. A Kalman filtering application is considered in a case study from which the operations required on such a system can be defined. This also serves as a new and powerful application for iterative optical processors. The importance of pipelining the data flow and the ordering of the operations performed in a specific application of such a system are also noted. Several examples of how to effectively achieve this are included. A new technique for handling bipolar data on such architectures is also described.

EMCS Installation Follow-Up Study. Volume 2.

DTIC Science & Technology

1984-03-01

softwaLe is currently being developed by Power;. 4. The system includc;s an equation processor which p~ovi,.’ arithmetic, logicaL, and timing...packages are actually written using the equation processor. 5. The system colorgraphics capability was demonstrated. The system can be operated...extremely important. The AsteroAI drawings were reviewed by the Navy only on a cursory basis. This proved to be inad- equate . 15. The specifications

High-Speed Computation of the Kleene Star in Max-Plus Algebraic System Using a Cell Broadband Engine

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki

This research addresses a high-speed computation method for the Kleene star of the weighted adjacency matrix in a max-plus algebraic system. We focus on systems whose precedence constraints are represented by a directed acyclic graph and implement it on a Cell Broadband Engine™ (CBE) processor. Since the resulting matrix gives the longest travel times between two adjacent nodes, it is often utilized in scheduling problem solvers for a class of discrete event systems. This research, in particular, attempts to achieve a speedup by using two approaches: parallelization and SIMDization (Single Instruction, Multiple Data), both of which can be accomplished by a CBE processor. The former refers to a parallel computation using multiple cores, while the latter is a method whereby multiple elements are computed by a single instruction. Using the implementation on a Sony PlayStation 3™ equipped with a CBE processor, we found that the SIMDization is effective regardless of the system's size and the number of processor cores used. We also found that the scalability of using multiple cores is remarkable especially for systems with a large number of nodes. In a numerical experiment where the number of nodes is 2000, we achieved a speedup of 20 times compared with the method without the above techniques.

VENTURE/PC manual: A multidimensional multigroup neutron diffusion code system. Version 3

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shapiro, A.; Huria, H.C.; Cho, K.W.

1991-12-01

VENTURE/PC is a recompilation of part of the Oak Ridge BOLD VENTURE code system, which will operate on an IBM PC or compatible computer. Neutron diffusion theory solutions are obtained for multidimensional, multigroup problems. This manual contains information associated with operating the code system. The purpose of the various modules used in the code system, and the input for these modules are discussed. The PC code structure is also given. Version 2 included several enhancements not given in the original version of the code. In particular, flux iterations can be done in core rather than by reading and writing tomore » disk, for problems which allow sufficient memory for such in-core iterations. This speeds up the iteration process. Version 3 does not include any of the special processors used in the previous versions. These special processors utilized formatted input for various elements of the code system. All such input data is now entered through the Input Processor, which produces standard interface files for the various modules in the code system. In addition, a Standard Interface File Handbook is included in the documentation which is distributed with the code, to assist in developing the input for the Input Processor.« less

Investigation into the Use of Texturing for Real-Time Computer Animation.

DTIC Science & Technology

1987-12-01

produce a rough polygon surface [7]. Research in the area of real time texturing has also been conducted. Using a specially designed multi-processor system ...Oka, Tsutsui, Ohba, Kurauchi and Tago have introduced real-time manipulation of texture mapped surfaces [8]. Using multi- processors, systems will...a call to the system function defpattern(n,size,mask) short n,size; short *mask, which takes as input an index to a system table of patterns, a

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1997-11-04

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a ``hardwired`` processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer. 19 figs.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1997-01-01

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a "hardwired" processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer.

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

NASA Technical Reports Server (NTRS)

Srivas, Mandayam; Bickford, Mark

1991-01-01

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

NASA Technical Reports Server (NTRS)

Bickford, Mark; Srivas, Mandayam

1991-01-01

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Quantitative Assessment of Spray Deposition with Water-Sensitive Paper

USDA-ARS?s Scientific Manuscript database

Spray droplets, discharged from the lower six nozzles of an airblast sprayer, were sampled on pairs of absorbent filter and water-sensitive papers at nine distances from sprayer. Spray deposition on filter targets were measured by fluorometry and spray distribution on WSP targets were assessed by t...

Influence of travel speed on spray deposition uniformity from an air-assisted variable-rate sprayer

USDA-ARS?s Scientific Manuscript database

A newly developed LiDAR-guided air-assisted variable-rate sprayer for nursery and orchard applications was tested at various travel speeds to compare its spray deposition and coverage uniformity with constant-rate applications. Spray samplers, including nylon screens and water-sensitive papers (WSP)...

Multi-processing on supercomputers for computational aerodynamics

NASA Technical Reports Server (NTRS)

Yarrow, Maurice; Mehta, Unmeel B.

1990-01-01

The MIMD concept is applied, through multitasking, with relatively minor modifications to an existing code for a single processor. This approach maps the available memory to multiple processors, exploiting the C-FORTRAN-Unix interface. An existing single processor algorithm is mapped without the need for developing a new algorithm. The procedure of designing a code utilizing this approach is automated with the Unix stream editor. A Multiple Processor Multiple Grid (MPMG) code is developed as a demonstration of this approach. This code solves the three-dimensional, Reynolds-averaged, thin-layer and slender-layer Navier-Stokes equations with an implicit, approximately factored and diagonalized method. This solver is applied to a generic, oblique-wing aircraft problem on a four-processor computer using one process for data management and nonparallel computations and three processes for pseudotime advance on three different grid systems.

Optical systolic array processor using residue arithmetic

NASA Technical Reports Server (NTRS)

Jackson, J.; Casasent, D.

1983-01-01

The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.

Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications

PubMed Central

2014-01-01

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error. PMID:25580458

Noise Analysis of Spatial Phase coding in analog Acoustooptic Processors

NASA Technical Reports Server (NTRS)

Gary, Charles K.; Lum, Henry, Jr. (Technical Monitor)

1994-01-01

Optical beams can carry information in their amplitude and phase; however, optical analog numerical calculators such as an optical matrix processor use incoherent light to achieve linear operation. Thus, the phase information is lost and only the magnitude can be used. This limits such processors to the representation of positive real numbers. Many systems have been devised to overcome this deficit through the use of digital number representations, but they all operate at a greatly reduced efficiency in contrast to analog systems. The most widely accepted method to achieve sign coding in analog optical systems has been the use of an offset for the zero level. Unfortunately, this results in increased noise sensitivity for small numbers. In this paper, we examine the use of spatially coherent sign coding in acoustooptical processors, a method first developed for digital calculations by D. V. Tigin. This coding technique uses spatial coherence for the representation of signed numbers, while temporal incoherence allows for linear analog processing of the optical information. We show how spatial phase coding reduces noise sensitivity for signed analog calculations.

Processor tradeoffs in distributed real-time systems

NASA Technical Reports Server (NTRS)

Krishna, C. M.; Shin, Kang G.; Bhandari, Inderpal S.

1987-01-01

The problem of the optimization of the design of real-time distributed systems is examined with reference to a class of computer architectures similar to the continuously reconfigurable multiprocessor flight control system structure, CM2FCS. Particular attention is given to the impact of processor replacement and the burn-in time on the probability of dynamic failure and mean cost. The solution is obtained numerically and interpreted in the context of real-time applications.

Modeling Large Scale Circuits Using Massively Parallel Descrete-Event Simulation

DTIC Science & Technology

2013-06-01

exascale levels of performance, the smallest elements of a single processor can greatly affect the entire computer system (e.g. its power consumption...grow to exascale levels of performance, the smallest elements of a single processor can greatly affect the entire computer system (e.g. its power...Warp Speed 10.0. 2.0 INTRODUCTION As supercomputer systems approach exascale , the core count will exceed 1024 and number of transistors used in

Status of a Power Processor for the Prometheus-1 Electric Propulsion System

NASA Technical Reports Server (NTRS)

Pinero, Luis R.; Hill, Gerald M.; Aulisio, Michael; Gerber, Scott; Griebeler, Elmer; Hewitt, Frank; Scina, Joseph

2006-01-01

NASA is developing technologies for nuclear electric propulsion for proposed deep space missions in support of the Exploration initiative under Project Prometheus. Electrical power produced by the combination of a fission-based power source and a Brayton power conversion and distribution system is used by a high specific impulse ion propulsion system to propel the spaceship. The ion propulsion system include the thruster, power processor and propellant feed system. A power processor technology development effort was initiated under Project Prometheus to develop high performance and lightweight power-processing technologies suitable for the application. This effort faces multiple challenges including developing radiation hardened power modules and converters with very high power capability and efficiency to minimize the impact on the power conversion and distribution system as well as the heat rejection system. This paper documents the design and test results of the first version of the beam supply, the design of a second version of the beam supply and the design and test results of the ancillary supplies.

Development of a soldier-portable fuel cell power system. Part I: A bread-board methanol fuel processor

NASA Astrophysics Data System (ADS)

Palo, Daniel R.; Holladay, Jamie D.; Rozmiarek, Robert T.; Guzman-Leong, Consuelo E.; Wang, Yong; Hu, Jianli; Chin, Ya-Huei; Dagle, Robert A.; Baker, Eddie G.

A 15-W e portable power system is being developed for the US Army that consists of a hydrogen-generating fuel reformer coupled to a proton-exchange membrane fuel cell. In the first phase of this project, a methanol steam reformer system was developed and demonstrated. The reformer system included a combustor, two vaporizers, and a steam reforming reactor. The device was demonstrated as a thermally independent unit over the range of 14-80 W t output. Assuming a 14-day mission life and an ultimate 1-kg fuel processor/fuel cell assembly, a base case was chosen to illustrate the expected system performance. Operating at 13 W e, the system yielded a fuel processor efficiency of 45% (LHV of H 2 out/LHV of fuel in) and an estimated net efficiency of 22% (assuming a fuel cell efficiency of 48%). The resulting energy density of 720 Wh/kg is several times the energy density of the best lithium-ion batteries. Some immediate areas of improvement in thermal management also have been identified, and an integrated fuel processor is under development. The final system will be a hybrid, containing a fuel reformer, a fuel cell, and a rechargeable battery. The battery will provide power for start-up and added capacity for times of peak power demand.

RAMA: A file system for massively parallel computers

NASA Technical Reports Server (NTRS)

Miller, Ethan L.; Katz, Randy H.

1993-01-01

This paper describes a file system design for massively parallel computers which makes very efficient use of a few disks per processor. This overcomes the traditional I/O bottleneck of massively parallel machines by storing the data on disks within the high-speed interconnection network. In addition, the file system, called RAMA, requires little inter-node synchronization, removing another common bottleneck in parallel processor file systems. Support for a large tertiary storage system can easily be integrated in lo the file system; in fact, RAMA runs most efficiently when tertiary storage is used.

A High-Throughput Processor for Flight Control Research Using Small UAVs

NASA Technical Reports Server (NTRS)

Klenke, Robert H.; Sleeman, W. C., IV; Motter, Mark A.

2006-01-01

There are numerous autopilot systems that are commercially available for small (<100 lbs) UAVs. However, they all share several key disadvantages for conducting aerodynamic research, chief amongst which is the fact that most utilize older, slower, 8- or 16-bit microcontroller technologies. This paper describes the development and testing of a flight control system (FCS) for small UAV s based on a modern, high throughput, embedded processor. In addition, this FCS platform contains user-configurable hardware resources in the form of a Field Programmable Gate Array (FPGA) that can be used to implement custom, application-specific hardware. This hardware can be used to off-load routine tasks such as sensor data collection, from the FCS processor thereby further increasing the computational throughput of the system.

Advances in optical information processing IV; Proceedings of the Meeting, Orlando, FL, Apr. 18-20, 1990

NASA Astrophysics Data System (ADS)

Pape, Dennis R.

1990-09-01

The present conference discusses topics in optical image processing, optical signal processing, acoustooptic spectrum analyzer systems and components, and optical computing. Attention is given to tradeoffs in nonlinearly recorded matched filters, miniature spatial light modulators, detection and classification using higher-order statistics of optical matched filters, rapid traversal of an image data base using binary synthetic discriminant filters, wideband signal processing for emitter location, an acoustooptic processor for autonomous SAR guidance, and sampling of Fresnel transforms. Also discussed are an acoustooptic RF signal-acquisition system, scanning acoustooptic spectrum analyzers, the effects of aberrations on acoustooptic systems, fast optical digital arithmetic processors, information utilization in analog and digital processing, optical processors for smart structures, and a self-organizing neural network for unsupervised learning.

Database interfaces on NASA's heterogeneous distributed database system

NASA Technical Reports Server (NTRS)

Huang, Shou-Hsuan Stephen

1987-01-01

The purpose of Distributed Access View Integrated Database (DAVID) interface module (Module 9: Resident Primitive Processing Package) is to provide data transfer between local DAVID systems and resident Data Base Management Systems (DBMSs). The result of current research is summarized. A detailed description of the interface module is provided. Several Pascal templates were constructed. The Resident Processor program was also developed. Even though it is designed for the Pascal templates, it can be modified for templates in other languages, such as C, without much difficulty. The Resident Processor itself can be written in any programming language. Since Module 5 routines are not ready yet, there is no way to test the interface module. However, simulation shows that the data base access programs produced by the Resident Processor do work according to the specifications.

Formal design and verification of a reliable computing platform for real-time control. Phase 1: Results

NASA Technical Reports Server (NTRS)

Divito, Ben L.; Butler, Ricky W.; Caldwell, James L.

1990-01-01

A high-level design is presented for a reliable computing platform for real-time control applications. Design tradeoffs and analyses related to the development of the fault-tolerant computing platform are discussed. The architecture is formalized and shown to satisfy a key correctness property. The reliable computing platform uses replicated processors and majority voting to achieve fault tolerance. Under the assumption of a majority of processors working in each frame, it is shown that the replicated system computes the same results as a single processor system not subject to failures. Sufficient conditions are obtained to establish that the replicated system recovers from transient faults within a bounded amount of time. Three different voting schemes are examined and proved to satisfy the bounded recovery time conditions.

System and method for bearing fault detection using stator current noise cancellation

DOEpatents

Zhou, Wei; Lu, Bin; Habetler, Thomas G.; Harley, Ronald G.; Theisen, Peter J.

2010-08-17

A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to repeatedly receive real-time operating current data from the operating motor and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components.

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

Developing infrared array controller with software real time operating system

NASA Astrophysics Data System (ADS)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

Low latency memory access and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

Low latency memory access and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

High-Level Data-Abstraction System

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1986-01-01

Communication with data-base processor flexible and efficient. High Level Data Abstraction (HILDA) system is three-layer system supporting data-abstraction features of Intel data-base processor (DBP). Purpose of HILDA establishment of flexible method of efficiently communicating with DBP. Power of HILDA lies in its extensibility with regard to syntax and semantic changes. HILDA's high-level query language readily modified. Offers powerful potential to computer sites where DBP attached to DEC VAX-series computer. HILDA system written in Pascal and FORTRAN 77 for interactive execution.

Evaluating the operations capability of Freedom's Data Management System

NASA Technical Reports Server (NTRS)

Sowizral, Henry A.

1990-01-01

Three areas of Data Management System (DMS) performance are examined: raw processor speed, the subjective speed of the Lynx OS X-Window system, and the operational capacity of the Runtime Object Database (RODB). It is concluded that the proposed processor will operate at its specified rate of speed and that the X-Window system operates within users' subjective needs. It is also concluded that the RODB cannot provide the required level of service, even with a two-order of magnitude (100 fold) improvement in speed.

Visualization Co-Processing of a CFD Simulation

NASA Technical Reports Server (NTRS)

Vaziri, Arsi

1999-01-01

OVERFLOW, a widely used CFD simulation code, is combined with a visualization system, pV3, to experiment with an environment for simulation/visualization co-processing on a SGI Origin 2000 computer(O2K) system. The shared memory version of the solver is used with the O2K 'pfa' preprocessor invoked to automatically discover parallelism in the source code. No other explicit parallelism is enabled. In order to study the scaling and performance of the visualization co-processing system, sample runs are made with different processor groups in the range of 1 to 254 processors. The data exchange between the visualization system and the simulation system is rapid enough for user interactivity when the problem size is small. This shared memory version of OVERFLOW, with minimal parallelization, does not scale well to an increasing number of available processors. The visualization task takes about 18 to 30% of the total processing time and does not appear to be a major contributor to the poor scaling. Improper load balancing and inter-processor communication overhead are contributors to this poor performance. Work is in progress which is aimed at obtaining improved parallel performance of the solver and removing the limitations of serial data transfer to pV3 by examining various parallelization/communication strategies, including the use of the explicit message passing.

Parallel computing on Unix workstation arrays

NASA Astrophysics Data System (ADS)

Reale, F.; Bocchino, F.; Sciortino, S.

1994-12-01

We have tested arrays of general-purpose Unix workstations used as MIMD systems for massive parallel computations. In particular we have solved numerically a demanding test problem with a 2D hydrodynamic code, generally developed to study astrophysical flows, by exucuting it on arrays either of DECstations 5000/200 on Ethernet LAN, or of DECstations 3000/400, equipped with powerful Alpha processors, on FDDI LAN. The code is appropriate for data-domain decomposition, and we have used a library for parallelization previously developed in our Institute, and easily extended to work on Unix workstation arrays by using the PVM software toolset. We have compared the parallel efficiencies obtained on arrays of several processors to those obtained on a dedicated MIMD parallel system, namely a Meiko Computing Surface (CS-1), equipped with Intel i860 processors. We discuss the feasibility of using non-dedicated parallel systems and conclude that the convenience depends essentially on the size of the computational domain as compared to the relative processor power and network bandwidth. We point out that for future perspectives a parallel development of processor and network technology is important, and that the software still offers great opportunities of improvement, especially in terms of latency times in the message-passing protocols. In conditions of significant gain in terms of speedup, such workstation arrays represent a cost-effective approach to massive parallel computations.

Optimal partitioning of random programs across two processors

NASA Technical Reports Server (NTRS)

Nicol, D. M.

1986-01-01

The optimal partitioning of random distributed programs is discussed. It is concluded that the optimal partitioning of a homogeneous random program over a homogeneous distributed system either assigns all modules to a single processor, or distributes the modules as evenly as possible among all processors. The analysis rests heavily on the approximation which equates the expected maximum of a set of independent random variables with the set's maximum expectation. The results are strengthened by providing an approximation-free proof of this result for two processors under general conditions on the module execution time distribution. It is also shown that use of this approximation causes two of the previous central results to be false.

First Results of an “Artificial Retina” Processor Prototype

DOE PAGES

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; ...

2016-11-15

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. Also, the prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHzmore » crossing rate.« less

First Results of an “Artificial Retina” Processor Prototype

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. Also, the prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHzmore » crossing rate.« less

HEP - A semaphore-synchronized multiprocessor with central control. [Heterogeneous Element Processor

NASA Technical Reports Server (NTRS)

Gilliland, M. C.; Smith, B. J.; Calvert, W.

1976-01-01

The paper describes the design concept of the Heterogeneous Element Processor (HEP), a system tailored to the special needs of scientific simulation. In order to achieve high-speed computation required by simulation, HEP features a hierarchy of processes executing in parallel on a number of processors, with synchronization being largely accomplished by hardware. A full-empty-reserve scheme of synchronization is realized by zero-one-valued hardware semaphores. A typical system has, besides the control computer and the scheduler, an algebraic module, a memory module, a first-in first-out (FIFO) module, an integrator module, and an I/O module. The architecture of the scheduler and the algebraic module is examined in detail.

Vascular system modeling in parallel environment - distributed and shared memory approaches

PubMed Central

Jurczuk, Krzysztof; Kretowski, Marek; Bezy-Wendling, Johanne

2011-01-01

The paper presents two approaches in parallel modeling of vascular system development in internal organs. In the first approach, new parts of tissue are distributed among processors and each processor is responsible for perfusing its assigned parts of tissue to all vascular trees. Communication between processors is accomplished by passing messages and therefore this algorithm is perfectly suited for distributed memory architectures. The second approach is designed for shared memory machines. It parallelizes the perfusion process during which individual processing units perform calculations concerning different vascular trees. The experimental results, performed on a computing cluster and multi-core machines, show that both algorithms provide a significant speedup. PMID:21550891

Systems and methods for reconfiguring input devices

NASA Technical Reports Server (NTRS)

Lancaster, Jeff (Inventor); De Mers, Robert E. (Inventor)

2012-01-01

A system includes an input device having first and second input members configured to be activated by a user. The input device is configured to generate activation signals associated with activation of the first and second input members, and each of the first and second input members are associated with an input function. A processor is coupled to the input device and configured to receive the activation signals. A memory coupled to the processor, and includes a reconfiguration module configured to store the input functions assigned to the first and second input members and, upon execution of the processor, to reconfigure the input functions assigned to the input members when the first input member is inoperable.

Optical computing using optical flip-flops in Fourier processors: use in matrix multiplication and discrete linear transforms.

PubMed

Ando, S; Sekine, S; Mita, M; Katsuo, S

1989-12-15

An architecture and the algorithms for matrix multiplication using optical flip-flops (OFFs) in optical processors are proposed based on residue arithmetic. The proposed system is capable of processing all elements of matrices in parallel utilizing the information retrieving ability of optical Fourier processors. The employment of OFFs enables bidirectional data flow leading to a simpler architecture and the burden of residue-to-decimal (or residue-to-binary) conversion to operation time can be largely reduced by processing all elements in parallel. The calculated characteristics of operation time suggest a promising use of the system in a real time 2-D linear transform.

Systems and methods for process and user driven dynamic voltage and frequency scaling

DOEpatents

Mallik, Arindam [Evanston, IL; Lin, Bin [Hillsboro, OR; Memik, Gokhan [Evanston, IL; Dinda, Peter [Evanston, IL; Dick, Robert [Evanston, IL

2011-03-22

Certain embodiments of the present invention provide a method for power management including determining at least one of an operating frequency and an operating voltage for a processor and configuring the processor based on the determined at least one of the operating frequency and the operating voltage. The operating frequency is determined based at least in part on direct user input. The operating voltage is determined based at least in part on an individual profile for processor.

Comparison of the CENTRM resonance processor to the NITAWL resonance processor in SCALE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hollenbach, D.F.; Petrie, L.M.

1998-01-01

This report compares the MTAWL and CENTRM resonance processors in the SCALE code system. The cases examined consist of the International OECD/NEA Criticality Working Group Benchmark 20 problem. These cases represent fuel pellets partially dissolved in a borated solution. The assumptions inherent to the Nordheim Integral Treatment, used in MTAWL, are not valid for these problems. CENTRM resolves this limitation by explicitly calculating a problem dependent point flux from point cross sections, which is then used to create group cross sections.

Single bus star connected reluctance drive and method

DOEpatents

Fahimi, Babak; Shamsi, Pourya

2016-05-10

A system and methods for operating a switched reluctance machine includes a controller, an inverter connected to the controller and to the switched reluctance machine, a hysteresis control connected to the controller and to the inverter, a set of sensors connected to the switched reluctance machine and to the controller, the switched reluctance machine further including a set of phases the controller further comprising a processor and a memory connected to the processor, wherein the processor programmed to execute a control process and a generation process.

Systems and methods for performing wireless financial transactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCown, Steven Harvey

2012-07-03

A secure computing module (SCM) is configured for connection with a host device. The SCM includes a processor for performing secure processing operations, a host interface for coupling the processor to the host device, and a memory connected to the processor wherein the processor logically isolates at least some of the memory from access by the host device. The SCM also includes a proximate-field wireless communicator connected to the processor to communicate with another SCM associated with another host device. The SCM generates a secure digital signature for a financial transaction package and communicates the package and the signature tomore » the other SCM using the proximate-field wireless communicator. Financial transactions are performed from person to person using the secure digital signature of each person's SCM and possibly message encryption. The digital signatures and transaction details are communicated to appropriate financial organizations to authenticate the transaction parties and complete the transaction.« less

Reconfigurable L-Band Radar

NASA Technical Reports Server (NTRS)

Rincon, Rafael F.

2008-01-01

The reconfigurable L-Band radar is an ongoing development at NASA/GSFC that exploits the capability inherently in phased array radar systems with a state-of-the-art data acquisition and real-time processor in order to enable multi-mode measurement techniques in a single radar architecture. The development leverages on the L-Band Imaging Scatterometer, a radar system designed for the development and testing of new radar techniques; and the custom-built DBSAR processor, a highly reconfigurable, high speed data acquisition and processing system. The radar modes currently implemented include scatterometer, synthetic aperture radar, and altimetry; and plans to add new modes such as radiometry and bi-static GNSS signals are being formulated. This development is aimed at enhancing the radar remote sensing capabilities for airborne and spaceborne applications in support of Earth Science and planetary exploration This paper describes the design of the radar and processor systems, explains the operational modes, and discusses preliminary measurements and future plans.

Fuel Processor Development for a Soldier-Portable Fuel Cell System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palo, Daniel R.; Holladay, Jamie D.; Rozmiarek, Robert T.

2002-01-01

Battelle is currently developing a soldier-portable power system for the U.S. Army that will continuously provide 15 W (25 W peak) of base load electric power for weeks or months using a micro technology-based fuel processor. The fuel processing train consists of a combustor, two vaporizers, and a steam-reforming reactor. This paper describes the concept and experimental progress to date.

Dormancy and Recovery Testing for Biological Wastewater Processors

NASA Technical Reports Server (NTRS)

Hummerick, Mary F.; Coutts, Janelle L.; Lunn, Griffin M.; Spencer, LaShelle; Khodadad, Christina L.; Birmele, Michele N.; Frances, Someliz; Wheeler, Raymond

2015-01-01

Resource recovery and recycling waste streams to usable water via biological water processors is a plausible component of an integrated water purification system. Biological processing as a pretreatment can reduce the load of organic carbon and nitrogen compounds entering physiochemical systems downstream. Aerated hollow fiber membrane bioreactors, have been proposed and studied for a number of years as an approach for treating wastewater streams for space exploration.

NCC Simulation Model: Simulating the operations of the network control center, phase 2

NASA Technical Reports Server (NTRS)

Benjamin, Norman M.; Paul, Arthur S.; Gill, Tepper L.

1992-01-01

The simulation of the network control center (NCC) is in the second phase of development. This phase seeks to further develop the work performed in phase one. Phase one concentrated on the computer systems and interconnecting network. The focus of phase two will be the implementation of the network message dialogues and the resources controlled by the NCC. These resources are requested, initiated, monitored and analyzed via network messages. In the NCC network messages are presented in the form of packets that are routed across the network. These packets are generated, encoded, decoded and processed by the network host processors that generate and service the message traffic on the network that connects these hosts. As a result, the message traffic is used to characterize the work done by the NCC and the connected network. Phase one of the model development represented the NCC as a network of bi-directional single server queues and message generating sources. The generators represented the external segment processors. The served based queues represented the host processors. The NCC model consists of the internal and external processors which generate message traffic on the network that links these hosts. To fully realize the objective of phase two it is necessary to identify and model the processes in each internal processor. These processes live in the operating system of the internal host computers and handle tasks such as high speed message exchanging, ISN and NFE interface, event monitoring, network monitoring, and message logging. Inter process communication is achieved through the operating system facilities. The overall performance of the host is determined by its ability to service messages generated by both internal and external processors.

Status of the Regenerative ECLSS Water Recovery System

NASA Technical Reports Server (NTRS)

Carter, Donald Layne

2009-01-01

NASA has completed the delivery of the regenerative Water Recovery System (WRS) for the International Space Station (ISS). The major assemblies included in this system are the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the final effort to deliver the hardware to the Kennedy Space Center for launch on STS-126, the on-orbit status as of April 2009, and describes some of the technical challenges encountered and lessons learned over the past year.

A Methodolgy, Based on Analytical Modeling, for the Design of Parallel and Distributed Architectures for Relational Database Query Processors.

DTIC Science & Technology

1987-12-01

Application Programs Intelligent Disk Database Controller Manangement System Operating System Host .1’ I% Figure 2. Intelligent Disk Controller Application...8217. /- - • Database Control -% Manangement System Disk Data Controller Application Programs Operating Host I"" Figure 5. Processor-Per- Head data. Therefore, the...However. these ad- ditional properties have been proven in classical set and relation theory [75]. These additional properties are described here

Flight design system-1 system design. Volume 5: Data management and data base documentation support system. [for shuttle flight planning

NASA Technical Reports Server (NTRS)

1979-01-01

Application software intended to reduce the man-hours required per flight design cycle by producing major flight design documents with little or no manual typing is described. The documentation support software is divided into two separately executable processors. However, since both processors support the same overall functions, and most of the software contained in one is also contained in the other, both are collectively presented.

Development of a Soldier-Portable Fuel Cell Power System, Part I: A Bread-Board Methanol Fuel Processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palo, Daniel R.; Holladay, Jamelyn D.; Rozmiarek, Robert T.

A 15-We portable power system is being developed for the US Army, comprised of a hydrogen-generating fuel reformer coupled to a hydrogen-converting fuel cell. As a first phase of this project, a methanol steam reformer system was developed and demonstrated. The reformer system included a combustor, two vaporizers, and a steam-reforming reactor. The device was demonstrated as a thermally independent unit over the range of 14 to 80 Wt output. Assuming a 14-day mission life and an ultimate 1-kg fuel processor/fuel cell assembly, a base case was chosen to illustrate the expected system performance. Operating at 13 We, the systemmore » yielded a fuel processor efficiency of 45% (LHV of H2 out/LHV of fuel in) and an estimated net efficiency of 22% (assuming a fuel cell efficiency of 48%). The resulting energy density of 720 W-hr/kg is several times the energy density of the best lithium-ion batteries. Some immediate areas of improvement in thermal management also have been identified and an integrated fuel processor is under development. The final system will be a hybrid, containing a fuel reformer, fuel cell, and rechargeable battery. The battery will provide power for startup and added capacity for times of peak power demand.« less

A network control concept for the 30/20 GHz communication system baseband processor

NASA Technical Reports Server (NTRS)

Sabourin, D. J.; Hay, R. E.

1982-01-01

The architecture and system design for a satellite-switched TDMA communication system employing on-board processing was developed by Motorola for NASA's Lewis Research Center. The system design is based on distributed processing techniques that provide extreme flexibility in the selection of a network control protocol without impacting the satellite or ground terminal hardware. A network control concept that includes system synchronization and allows burst synchronization to occur within the system operational requirement is described. This concept integrates the tracking and control links with the communication links via the baseband processor, resulting in an autonomous system operational approach.

Realization of a single image haze removal system based on DaVinci DM6467T processor

NASA Astrophysics Data System (ADS)

Liu, Zhuang

2014-10-01

Video monitoring system (VMS) has been extensively applied in domains of target recognition, traffic management, remote sensing, auto navigation and national defence. However the VMS has a strong dependence on the weather, for instance, in foggy weather, the quality of images received by the VMS are distinct degraded and the effective range of VMS is also decreased. All in all, the VMS performs terribly in bad weather. Thus the research of fog degraded images enhancement has very high theoretical and practical application value. A design scheme of a fog degraded images enhancement system based on the TI DaVinci processor is presented in this paper. The main function of the referred system is to extract and digital cameras capture images and execute image enhancement processing to obtain a clear image. The processor used in this system is the dual core TI DaVinci DM6467T - ARM@500MHz+DSP@1GH. A MontaVista Linux operating system is running on the ARM subsystem which handles I/O and application processing. The DSP handles signal processing and the results are available to the ARM subsystem in shared memory.The system benefits from the DaVinci processor so that, with lower power cost and smaller volume, it provides the equivalent image processing capability of a X86 computer. The outcome shows that the system in this paper can process images at 25 frames per second on D1 resolution.

Satellite on-board real-time SAR processor prototype

NASA Astrophysics Data System (ADS)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and size are reviewed.

PATCH image processor user's manual

NASA Technical Reports Server (NTRS)

Nieves, M. J. (Principal Investigator)

1980-01-01

The patch image processor extracts patches in various size (32 x 32, 64 x 64, 128 x 128, and 256 x 256 pixels) from full frame LANDSAT imagery data. With the patches that are extracted, a patch image mosaic is created in the image processing system, IMDACS, format.

A Course on Reconfigurable Processors

ERIC Educational Resources Information Center

Shoufan, Abdulhadi; Huss, Sorin A.

2010-01-01

Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universitat Darmstadt,…

A self-sustained, complete and miniaturized methanol fuel processor for proton exchange membrane fuel cell

NASA Astrophysics Data System (ADS)

Yang, Mei; Jiao, Fengjun; Li, Shulian; Li, Hengqiang; Chen, Guangwen

2015-08-01

A self-sustained, complete and miniaturized methanol fuel processor has been developed based on modular integration and microreactor technology. The fuel processor is comprised of one methanol oxidative reformer, one methanol combustor and one two-stage CO preferential oxidation unit. Microchannel heat exchanger is employed to recover heat from hot stream, miniaturize system size and thus achieve high energy utilization efficiency. By optimized thermal management and proper operation parameter control, the fuel processor can start up in 10 min at room temperature without external heating. A self-sustained state is achieved with H2 production rate of 0.99 Nm3 h-1 and extremely low CO content below 25 ppm. This amount of H2 is sufficient to supply a 1 kWe proton exchange membrane fuel cell. The corresponding thermal efficiency of whole processor is higher than 86%. The size and weight of the assembled reactors integrated with microchannel heat exchangers are 1.4 L and 5.3 kg, respectively, demonstrating a very compact construction of the fuel processor.

Multimode power processor

DOEpatents

O'Sullivan, G.A.; O'Sullivan, J.A.

1999-07-27

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources. 31 figs.

Multimode power processor

DOEpatents

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

Implementing An Image Understanding System Architecture Using Pipe

NASA Astrophysics Data System (ADS)

Luck, Randall L.

1988-03-01

This paper will describe PIPE and how it can be used to implement an image understanding system. Image understanding is the process of developing a description of an image in order to make decisions about its contents. The tasks of image understanding are generally split into low level vision and high level vision. Low level vision is performed by PIPE -a high performance parallel processor with an architecture specifically designed for processing video images at up to 60 fields per second. High level vision is performed by one of several types of serial or parallel computers - depending on the application. An additional processor called ISMAP performs the conversion from iconic image space to symbolic feature space. ISMAP plugs into one of PIPE's slots and is memory mapped into the high level processor. Thus it forms the high speed link between the low and high level vision processors. The mechanisms for bottom-up, data driven processing and top-down, model driven processing are discussed.

Embedded Palmprint Recognition System Using OMAP 3530

PubMed Central

Shen, Linlin; Wu, Shipei; Zheng, Songhao; Ji, Zhen

2012-01-01

We have proposed in this paper an embedded palmprint recognition system using the dual-core OMAP 3530 platform. An improved algorithm based on palm code was proposed first. In this method, a Gabor wavelet is first convolved with the palmprint image to produce a response image, where local binary patterns are then applied to code the relation among the magnitude of wavelet response at the ccentral pixel with that of its neighbors. The method is fully tested using the public PolyU palmprint database. While palm code achieves only about 89% accuracy, over 96% accuracy is achieved by the proposed G-LBP approach. The proposed algorithm was then deployed to the DSP processor of OMAP 3530 and work together with the ARM processor for feature extraction. When complicated algorithms run on the DSP processor, the ARM processor can focus on image capture, user interface and peripheral control. Integrated with an image sensing module and central processing board, the designed device can achieve accurate and real time performance. PMID:22438721

Embedded palmprint recognition system using OMAP 3530.

PubMed

Shen, Linlin; Wu, Shipei; Zheng, Songhao; Ji, Zhen

2012-01-01

We have proposed in this paper an embedded palmprint recognition system using the dual-core OMAP 3530 platform. An improved algorithm based on palm code was proposed first. In this method, a Gabor wavelet is first convolved with the palmprint image to produce a response image, where local binary patterns are then applied to code the relation among the magnitude of wavelet response at the central pixel with that of its neighbors. The method is fully tested using the public PolyU palmprint database. While palm code achieves only about 89% accuracy, over 96% accuracy is achieved by the proposed G-LBP approach. The proposed algorithm was then deployed to the DSP processor of OMAP 3530 and work together with the ARM processor for feature extraction. When complicated algorithms run on the DSP processor, the ARM processor can focus on image capture, user interface and peripheral control. Integrated with an image sensing module and central processing board, the designed device can achieve accurate and real time performance.

Multi-petascale highly efficient parallel supercomputer

DOEpatents

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.; Blumrich, Matthias A.; Boyle, Peter; Brunheroto, Jose R.; Chen, Dong; Cher, Chen -Yong; Chiu, George L.; Christ, Norman; Coteus, Paul W.; Davis, Kristan D.; Dozsa, Gabor J.; Eichenberger, Alexandre E.; Eisley, Noel A.; Ellavsky, Matthew R.; Evans, Kahn C.; Fleischer, Bruce M.; Fox, Thomas W.; Gara, Alan; Giampapa, Mark E.; Gooding, Thomas M.; Gschwind, Michael K.; Gunnels, John A.; Hall, Shawn A.; Haring, Rudolf A.; Heidelberger, Philip; Inglett, Todd A.; Knudson, Brant L.; Kopcsay, Gerard V.; Kumar, Sameer; Mamidala, Amith R.; Marcella, James A.; Megerian, Mark G.; Miller, Douglas R.; Miller, Samuel J.; Muff, Adam J.; Mundy, Michael B.; O'Brien, John K.; O'Brien, Kathryn M.; Ohmacht, Martin; Parker, Jeffrey J.; Poole, Ruth J.; Ratterman, Joseph D.; Salapura, Valentina; Satterfield, David L.; Senger, Robert M.; Smith, Brian; Steinmacher-Burow, Burkhard; Stockdell, William M.; Stunkel, Craig B.; Sugavanam, Krishnan; Sugawara, Yutaka; Takken, Todd E.; Trager, Barry M.; Van Oosten, James L.; Wait, Charles D.; Walkup, Robert E.; Watson, Alfred T.; Wisniewski, Robert W.; Wu, Peng

2015-07-14

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

76 FR 1971 - Drill Pipe From the People's Republic of China: Final Affirmative Countervailing Duty...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-11

... Group). Xigang Seamless Steel Tube Co., Ltd. (Xigang) and Wuxi Seamless Pipe Co., Ltd. (WSP) were also.... (SPM), Jiangyin Liangda Drill Pipe Co., Ltd. (Liangda), Jiangyin Sanliang Steel Pipe Trading Co., Ltd... investigation are VAM Drilling USA, Inc., Texas Steel Conversion, Inc., Rotary Drilling Tools, TMK IPSCO, and...

78 FR 18629 - Agency Information Collection Activities; Submission for OMB Review; Comment Request; Work-Study...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-03-27

... for OMB Review; Comment Request; Work-Study Program of the Child Labor Regulations ACTION: Notice... information collection request (ICR) titled, ``Work-Study Program of the Child Labor Regulations,'' to the... school-supervised and school-administered Work-Study Program (WSP) of the Child Labor Regulations. This...

76 FR 44907 - Cancellation of Pesticides for Non-Payment of Year 2011 Registration Maintenance Fees

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-27

.... 082542-00012 Abamectin 0.15ec T&o Insecticide/ miticide. 082542-00016 Technical Imidacloprid. 082542-00023 Solera Imidacloprid 2f Greenhouse/nursery Insecticide. 082542-00024 Solera Imidacloprid 2f T&O... MUP. 086722-00002 Syncide SCP. 086869-00001 Imidacloprid 75 WSP Select. 087099-00001 Greenstar Ag...

Extraction methods determine the antioxidant capacity and induction of quinone reductase by soy products in vitro

USDA-ARS?s Scientific Manuscript database

Gastrointestinal mimic (GI) and organic solvent extracts of whole soybean powder (WSP), soy protein concentrate (SPC), and soy protein isolate (SPI) as well as soy isoflavone concentrate (SIC) were analyzed for total phenols; quinone reductase (QR) induction in hepa1c1c7 cells; antioxidant scavengi...

Suspensions Plasma Spraying of Ceramics with Hybrid Water-Stabilized Plasma Technology

NASA Astrophysics Data System (ADS)

Musalek, Radek; Medricky, Jan; Tesar, Tomas; Kotlan, Jiri; Pala, Zdenek; Lukac, Frantisek; Chraska, Tomas; Curry, Nicholas

2017-01-01

Technology of water-stabilized plasma torch was recently substantially updated through introduction of a so-called hybrid concept that combines benefits of water stabilization and gas stabilization principles. The high-enthalpy plasma provided by the WSP-H ("hybrid") torch may be used for thermal spraying of powders as well as liquid feedstocks with high feed rates. In this study, results from three selected experiments with suspension plasma spraying with WSP-H technology are presented. Possibility of deposition of coatings with controlled microstructures was demonstrated for three different ceramics (YSZ—yttria-stabilized zirconia, YAG—yttrium aluminum garnet and Al2O3) introduced into ethanol-based suspensions. Shadowgraphy was used for optimization of suspension injection and visualization of the liquid fragmentation in the plasma jet. Coatings were deposited onto substrates attached to the rotating carousel with integrated temperature monitoring and air cooling, which provided an excellent reproducibility of the deposition process. Deposition of columnar-like YSZ and dense YAG and Al2O3 coatings was successfully achieved. Deposition efficiency reached more than 50%, as evaluated according to EN ISO 17 836 standard.

High humidity hot air impingement blanching (HHAIB) enhances drying rate and softens texture of apricot via cell wall pectin polysaccharides degradation and ultrastructure modification.

PubMed

Deng, Li-Zhen; Mujumdar, A S; Yang, Xu-Hai; Wang, Jun; Zhang, Qian; Zheng, Zhi-An; Gao, Zhen-Jiang; Xiao, Hong-Wei

2018-09-30

The effects of high humidity hot air impingement blanching (HHAIB) over a range of application times (30, 60, 90, and 120 s) on drying characteristics, hardness, cell wall pectin fractions contents and nanostructure, as well ultrastructure of apricot were investigated. Results showed that HHAIB reduced drying time and decreased the hardness of apricot by 20.7%-34.5% and 46.57%-71.89%, respectively. The water-soluble pectin (WSP) contents increased after blanching, while the contents of chelate-soluble pectin (CSP) and sodium-carbonate-soluble pectin (NSP) decreased significantly (P < 0.05). The hardness and drying time were found to correlate inversely with the WSP content, but positively with CSP and NSP contents. Atomic force microscopy (AFM) detection showed the decomposition and degradation of pectin fractions during blanching. Additionally, transmission electron microscopy (TEM) observation indicated that the cell wall structure was degraded and middle lamella integrity was destroyed by blanching. Copyright © 2018 Elsevier Ltd. All rights reserved.

PANDA: A distributed multiprocessor operating system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubb, P.

1989-01-01

PANDA is a design for a distributed multiprocessor and an operating system. PANDA is designed to allow easy expansion of both hardware and software. As such, the PANDA kernel provides only message passing and memory and process management. The other features needed for the system (device drivers, secondary storage management, etc.) are provided as replaceable user tasks. The thesis presents PANDA's design and implementation, both hardware and software. PANDA uses multiple 68010 processors sharing memory on a VME bus, each such node potentially connected to others via a high speed network. The machine is completely homogeneous: there are no differencesmore » between processors that are detectable by programs running on the machine. A single two-processor node has been constructed. Each processor contains memory management circuits designed to allow processors to share page tables safely. PANDA presents a programmers' model similar to the hardware model: a job is divided into multiple tasks, each having its own address space. Within each task, multiple processes share code and data. Tasks can send messages to each other, and set up virtual circuits between themselves. Peripheral devices such as disc drives are represented within PANDA by tasks. PANDA divides secondary storage into volumes, each volume being accessed by a volume access task, or VAT. All knowledge about the way that data is stored on a disc is kept in its volume's VAT. The design is such that PANDA should provide a useful testbed for file systems and device drivers, as these can be installed without recompiling PANDA itself, and without rebooting the machine.« less

Compact propane fuel processor for auxiliary power unit application

NASA Astrophysics Data System (ADS)

Dokupil, M.; Spitta, C.; Mathiak, J.; Beckhaus, P.; Heinzel, A.

With focus on mobile applications a fuel cell auxiliary power unit (APU) using liquefied petroleum gas (LPG) is currently being developed at the Centre for Fuel Cell Technology (Zentrum für BrennstoffzellenTechnik, ZBT gGmbH). The system is consisting of an integrated compact and lightweight fuel processor and a low temperature PEM fuel cell for an electric power output of 300 W. This article is presenting the current status of development of the fuel processor which is designed for a nominal hydrogen output of 1 k Wth,H2 within a load range from 50 to 120%. A modular setup was chosen defining a reformer/burner module and a CO-purification module. Based on the performance specifications, thermodynamic simulations, benchmarking and selection of catalysts the modules have been developed and characterised simultaneously and then assembled to the complete fuel processor. Automated operation results in a cold startup time of about 25 min for nominal load and carbon monoxide output concentrations below 50 ppm for steady state and dynamic operation. Also fast transient response of the fuel processor at load changes with low fluctuations of the reformate gas composition have been achieved. Beside the development of the main reactors the transfer of the fuel processor to an autonomous system is of major concern. Hence, concepts for packaging have been developed resulting in a volume of 7 l and a weight of 3 kg. Further a selection of peripheral components has been tested and evaluated regarding to the substitution of the laboratory equipment.

Special purpose parallel computer architecture for real-time control and simulation in robotic applications

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1993-01-01

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call.

Performance Models for Split-execution Computing Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Humble, Travis S; McCaskey, Alex; Schrock, Jonathan

Split-execution computing leverages the capabilities of multiple computational models to solve problems, but splitting program execution across different computational models incurs costs associated with the translation between domains. We analyze the performance of a split-execution computing system developed from conventional and quantum processing units (QPUs) by using behavioral models that track resource usage. We focus on asymmetric processing models built using conventional CPUs and a family of special-purpose QPUs that employ quantum computing principles. Our performance models account for the translation of a classical optimization problem into the physical representation required by the quantum processor while also accounting for hardwaremore » limitations and conventional processor speed and memory. We conclude that the bottleneck in this split-execution computing system lies at the quantum-classical interface and that the primary time cost is independent of quantum processor behavior.« less

System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees

DOEpatents

Faber, Vance; Moore, James W.

1992-01-01

A network of interconnected processors is formed from a vertex symmetric graph selected from graphs .GAMMA..sub.d (k) with degree d, diameter k, and (d+1)!/(d-k+1)! processors for each d.gtoreq.k and .GAMMA..sub.d (k,-1) with degree 3-1, diameter k+1, and (d+1)!/(d-k+1)! processors for each d.gtoreq.k.gtoreq.4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network .GAMMA..sub.d (k,-1) is provided, no processor has a channel connected to form an edge in a direction .delta..sub.1. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations.

Fault-tolerant battery system employing intra-battery network architecture

DOEpatents

Hagen, Ronald A.; Chen, Kenneth W.; Comte, Christophe; Knudson, Orlin B.; Rouillard, Jean

2000-01-01

A distributed energy storing system employing a communications network is disclosed. A distributed battery system includes a number of energy storing modules, each of which includes a processor and communications interface. In a network mode of operation, a battery computer communicates with each of the module processors over an intra-battery network and cooperates with individual module processors to coordinate module monitoring and control operations. The battery computer monitors a number of battery and module conditions, including the potential and current state of the battery and individual modules, and the conditions of the battery's thermal management system. An over-discharge protection system, equalization adjustment system, and communications system are also controlled by the battery computer. The battery computer logs and reports various status data on battery level conditions which may be reported to a separate system platform computer. A module transitions to a stand-alone mode of operation if the module detects an absence of communication connectivity with the battery computer. A module which operates in a stand-alone mode performs various monitoring and control functions locally within the module to ensure safe and continued operation.

Methods for operating parallel computing systems employing sequenced communications

DOEpatents

Benner, R.E.; Gustafson, J.L.; Montry, G.R.

1999-08-10

A parallel computing system and method are disclosed having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system. 15 figs.

Methods for operating parallel computing systems employing sequenced communications

DOEpatents

Benner, Robert E.; Gustafson, John L.; Montry, Gary R.

1999-01-01

A parallel computing system and method having improved performance where a program is concurrently run on a plurality of nodes for reducing total processing time, each node having a processor, a memory, and a predetermined number of communication channels connected to the node and independently connected directly to other nodes. The present invention improves performance of performance of the parallel computing system by providing a system which can provide efficient communication between the processors and between the system and input and output devices. A method is also disclosed which can locate defective nodes with the computing system.

Parallel discrete event simulation: A shared memory approach

NASA Technical Reports Server (NTRS)

Reed, Daniel A.; Malony, Allen D.; Mccredie, Bradley D.

1987-01-01

With traditional event list techniques, evaluating a detailed discrete event simulation model can often require hours or even days of computation time. Parallel simulation mimics the interacting servers and queues of a real system by assigning each simulated entity to a processor. By eliminating the event list and maintaining only sufficient synchronization to insure causality, parallel simulation can potentially provide speedups that are linear in the number of processors. A set of shared memory experiments is presented using the Chandy-Misra distributed simulation algorithm to simulate networks of queues. Parameters include queueing network topology and routing probabilities, number of processors, and assignment of network nodes to processors. These experiments show that Chandy-Misra distributed simulation is a questionable alternative to sequential simulation of most queueing network models.

Power processor for a 30cm ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.

1974-01-01

A thermal vacuum power processor for the NASA Lewis 30cm Mercury Ion Engine was designed, fabricated and tested to determine compliance with electrical specifications. The power processor breadboard used the silicon controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to an ion engine. The power processor includes a digital interface unit to process all input commands and internal telemetry signals so that operation is compatible with a central computer system. The breadboard was tested in a thermal vacuum environment. Integration tests were performed with the ion engine and demonstrate operational compatibility and reliable operation without any component failures. Electromagnetic interference data were also recorded on the design to provide information on the interaction with total spacecraft.

Embedded processor extensions for image processing

NASA Astrophysics Data System (ADS)

Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

2008-04-01

The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

Programmable DNA-Mediated Multitasking Processor.

PubMed

Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

2015-04-30

Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition

DOEpatents

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2007-07-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Set processing in a network environment. [data bases and magnetic disks and tapes

NASA Technical Reports Server (NTRS)

Hardgrave, W. T.

1975-01-01

A combination of a local network, a mass storage system, and an autonomous set processor serving as a data/storage management machine is described. Its characteristics include: content-accessible data bases usable from all connected devices; efficient storage/access of large data bases; simple and direct programming with data manipulation and storage management handled by the set processor; simple data base design and entry from source representation to set processor representation with no predefinition necessary; capability available for user sort/order specification; significant reduction in tape/disk pack storage and mounts; flexible environment that allows upgrading hardware/software configuration without causing major interruptions in service; minimal traffic on data communications network; and improved central memory usage on large processors.

Development for SSV on a parallel processing system (PARAGON)

NASA Astrophysics Data System (ADS)

Gothard, Benny M.; Allmen, Mark; Carroll, Michael J.; Rich, Dan

1995-12-01

A goal of the surrogate semi-autonomous vehicle (SSV) program is to have multiple vehicles navigate autonomously and cooperatively with other vehicles. This paper describes the process and tools used in porting UGV/SSV (unmanned ground vehicle) autonomous mobility and target recognition algorithms from a SISD (single instruction single data) processor architecture (i.e., a Sun SPARC workstation running C/UNIX) to a MIMD (multiple instruction multiple data) parallel processor architecture (i.e., PARAGON-a parallel set of i860 processors running C/UNIX). It discusses the gains in performance and the pitfalls of such a venture. It also examines the merits of this processor architecture (based on this conceptual prototyping effort) and programming paradigm to meet the final SSV demonstration requirements.

A Parallel Algorithm for Contact in a Finite Element Hydrocode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pierce, Timothy G.

A parallel algorithm is developed for contact/impact of multiple three dimensional bodies undergoing large deformation. As time progresses the relative positions of contact between the multiple bodies changes as collision and sliding occurs. The parallel algorithm is capable of tracking these changes and enforcing an impenetrability constraint and momentum transfer across the surfaces in contact. Portions of the various surfaces of the bodies are assigned to the processors of a distributed-memory parallel machine in an arbitrary fashion, known as the primary decomposition. A secondary, dynamic decomposition is utilized to bring opposing sections of the contacting surfaces together on the samemore » processors, so that opposing forces may be balanced and the resultant deformation of the bodies calculated. The secondary decomposition is accomplished and updated using only local communication with a limited subset of neighbor processors. Each processor represents both a domain of the primary decomposition and a domain of the secondary, or contact, decomposition. Thus each processor has four sets of neighbor processors: (a) those processors which represent regions adjacent to it in the primary decomposition, (b) those processors which represent regions adjacent to it in the contact decomposition, (c) those processors which send it the data from which it constructs its contact domain, and (d) those processors to which it sends its primary domain data, from which they construct their contact domains. The latter three of these neighbor sets change dynamically as the simulation progresses. By constraining all communication to these sets of neighbors, all global communication, with its attendant nonscalable performance, is avoided. A set of tests are provided to measure the degree of scalability achieved by this algorithm on up to 1024 processors. Issues related to the operating system of the test platform which lead to some degradation of the results are analyzed. This algorithm has been implemented as the contact capability of the ALE3D multiphysics code, and is currently in production use.« less

WHAT'S NEW IN MCIP2?

EPA Science Inventory

An update to CMAQ's Meteorology/Chemistry Interface Processor Version 2 (MCIP2) will be released in August 2004 in conjunction with the next public release of the CMAQ model. MCIP2 is the pre-processor in the CMAQ system that is typically used to perform off-line linkage between...

DEMONSTRATION BULLETIN: AOSTRA-SOILTECH ANAEROBIC THERMAL PROCESSOR: WIDE BEACH DEVELOPMENT SITE

EPA Science Inventory

The anaerobic thermal processor (ATP) was developed by UMATAC Industrial Processes under the sponsorship of the Alberta Oil Sands Technology and Research Authority (AOSTRA) and is licensed by SoilTech ATP Systems, Inc., a U.S. corporation. The ATP technology involves a physi...

Benchmarking hypercube hardware and software

NASA Technical Reports Server (NTRS)

Grunwald, Dirk C.; Reed, Daniel A.

1986-01-01

It was long a truism in computer systems design that balanced systems achieve the best performance. Message passing parallel processors are no different. To quantify the balance of a hypercube design, an experimental methodology was developed and the associated suite of benchmarks was applied to several existing hypercubes. The benchmark suite includes tests of both processor speed in the absence of internode communication and message transmission speed as a function of communication patterns.

Large liquid rocket engine transient performance simulation system

NASA Technical Reports Server (NTRS)

Mason, J. R.; Southwick, R. D.

1989-01-01

Phase 1 of the Rocket Engine Transient Simulation (ROCETS) program consists of seven technical tasks: architecture; system requirements; component and submodel requirements; submodel implementation; component implementation; submodel testing and verification; and subsystem testing and verification. These tasks were completed. Phase 2 of ROCETS consists of two technical tasks: Technology Test Bed Engine (TTBE) model data generation; and system testing verification. During this period specific coding of the system processors was begun and the engineering representations of Phase 1 were expanded to produce a simple model of the TTBE. As the code was completed, some minor modifications to the system architecture centering on the global variable common, GLOBVAR, were necessary to increase processor efficiency. The engineering modules completed during Phase 2 are listed: INJTOO - main injector; MCHBOO - main chamber; NOZLOO - nozzle thrust calculations; PBRNOO - preburner; PIPE02 - compressible flow without inertia; PUMPOO - polytropic pump; ROTROO - rotor torque balance/speed derivative; and TURBOO - turbine. Detailed documentation of these modules is in the Appendix. In addition to the engineering modules, several submodules were also completed. These submodules include combustion properties, component performance characteristics (maps), and specific utilities. Specific coding was begun on the system configuration processor. All functions necessary for multiple module operation were completed but the SOLVER implementation is still under development. This system, the Verification Checkout Facility (VCF) allows interactive comparison of module results to store data as well as provides an intermediate checkout of the processor code. After validation using the VCF, the engineering modules and submodules were used to build a simple TTBE.

The Effects of High-Altitude Electromagnetic Pulse (HEMP) on Telecommunications Assets

DTIC Science & Technology

1988-06-01

common to a whole class of switches. 5ESS switch software controls the operating system, call processing, and system administration andgmaintenance...LEVEL (ky/rn)3 (a). Mean Fraction of Preset Calls Dropped Due to Induced Transients3 1.0 W -o35kVhM (36 EVENTS) 5-40 kV/M (13 EVENTS) IAUTOMATIC ...eel PERIPHRAL UNIT BUS,IMNA The entire 4ESS system is controlled by the 1A processor. The processor monitors and controls the operation of the

Baseband processor development/test performance for 30/20 GHz SS-TDMA communication system

NASA Technical Reports Server (NTRS)

Brown, L.; Sabourin, D.; Attwood, S.

1984-01-01

The baseband processor (BBP) development for the 30/20 GHz Satellite Communication System is described. The SS-TDMA concept for future satellite communications is reviewed, describing the overall system, the satellite payload, and the frequency plan. A brief general description of the BBP is given, and the proof-of-concept model of the BBP is summarized. Key technologies and custom LSI developed for the BBP are listed. Finally, key technology developments and test data are reported for the BBP.

Free-Electron Laser Driven by the NBS (National Bureau of Standards) CW Microtron

DTIC Science & Technology

1988-03-31

planned over several years. This will begin with the purchase of a 32-bit dual processor system for the yet to be constructed primary station wire scanner ...display subsystem. This 32-bit dual processor system will not only form the wire scanner display system, but has sufficient processing power to...7th hit. Coiif. on FELs, eds., E.T. Scharlemann and D. Prosnitz (North- Holland, Amsterdam, 1986) p. 278. 121 X.K Maruyania and S. Penner, C.M. Tang

Control apparatus and method for efficiently heating a fuel processor in a fuel cell system

DOEpatents

Doan, Tien M.; Clingerman, Bruce J.

2003-08-05

A control apparatus and method for efficiently controlling the amount of heat generated by a fuel cell processor in a fuel cell system by determining a temperature error between actual and desired fuel processor temperatures. The temperature error is converted to a combustor fuel injector command signal or a heat dump valve position command signal depending upon the type of temperature error. Logic controls are responsive to the combustor fuel injector command signals and the heat dump valve position command signal to prevent the combustor fuel injector command signal from being generated if the heat dump valve is opened or, alternately, from preventing the heat dump valve position command signal from being generated if the combustor fuel injector is opened.

Biological Water Processor and Forward Osmosis Secondary Treatment

NASA Technical Reports Server (NTRS)

Shull, Sarah; Meyer, Caitlin

2014-01-01

The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

Exact diagonalization of quantum lattice models on coprocessors

NASA Astrophysics Data System (ADS)

Siro, T.; Harju, A.

2016-10-01

We implement the Lanczos algorithm on an Intel Xeon Phi coprocessor and compare its performance to a multi-core Intel Xeon CPU and an NVIDIA graphics processor. The Xeon and the Xeon Phi are parallelized with OpenMP and the graphics processor is programmed with CUDA. The performance is evaluated by measuring the execution time of a single step in the Lanczos algorithm. We study two quantum lattice models with different particle numbers, and conclude that for small systems, the multi-core CPU is the fastest platform, while for large systems, the graphics processor is the clear winner, reaching speedups of up to 7.6 compared to the CPU. The Xeon Phi outperforms the CPU with sufficiently large particle number, reaching a speedup of 2.5.

The role of neuroimaging in the discovery of processing stages. A review.

PubMed

Mulder, G; Wijers, A A; Lange, J J; Buijink, B M; Mulder, L J; Willemsen, A T; Paans, A M

1995-11-01

In this contribution we show how neuroimaging methods can augment behavioural methods to discover processing stages. Event Related Brain Potentials (ERPs), Brain Electrical Source Analysis (BESA) and regional changes in cerebral blood flow (rCBF) do not necessarily require behavioural responses. With the aid of rCBF we are able to discover several cortical and subcortical brain systems (processors) active in selective attention and memory search tasks. BESA describes cortical activity with high temporal resolution in terms of a limited number of neural generators within these brain systems. The combination of behavioural methods and neuroimaging provides a picture of the functional architecture of the brain. The review is organized around three processors: the Visual, Cognitive and Manual Motor Processors.

Interactive high-resolution isosurface ray casting on multicore processors.

PubMed

Wang, Qin; JaJa, Joseph

2008-01-01

We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

Scheduling time-critical graphics on multiple processors

NASA Technical Reports Server (NTRS)

Meyer, Tom W.; Hughes, John F.

1995-01-01

This paper describes an algorithm for the scheduling of time-critical rendering and computation tasks on single- and multiple-processor architectures, with minimal pipelining. It was developed to manage scientific visualization scenes consisting of hundreds of objects, each of which can be computed and displayed at thousands of possible resolution levels. The algorithm generates the time-critical schedule using progressive-refinement techniques; it always returns a feasible schedule and, when allowed to run to completion, produces a near-optimal schedule which takes advantage of almost the entire multiple-processor system.

Formulation of consumables management models: Mission planning processor payload interface definition

NASA Technical Reports Server (NTRS)

Torian, J. G.

1977-01-01

Consumables models required for the mission planning and scheduling function are formulated. The relation of the models to prelaunch, onboard, ground support, and postmission functions for the space transportation systems is established. Analytical models consisting of an orbiter planning processor with consumables data base is developed. A method of recognizing potential constraint violations in both the planning and flight operations functions, and a flight data file storage/retrieval of information over an extended period which interfaces with a flight operations processor for monitoring of the actual flights is presented.

Development of flame resistant treatment for nomex fibrous structures

NASA Technical Reports Server (NTRS)

Toy, M. S.

1978-01-01

Technology which renders aramid fibrous structures flame resistant through chemical modification was developed. The project scaled up flame resistant treatment from laboratory fabric swatches of a few inches to efficiently producing ten yards of commercial width (41 inches) aromatic polyamide. The radiation intensity problem of the processor was resolved. Further improvement of the processor cooling system was recommended for two reasons: (1) To advance current technology of flame proofing Nomex fabric to higher oxygen enriched atmospheres; and (2) To adapt the processor for direct applicability to low cost commercial fabrics.

MBASIC batch processor architectural overview

NASA Technical Reports Server (NTRS)

Reynolds, S. M.

1978-01-01

The MBASIC (TM) batch processor, a language translator designed to operate in the MBASIC (TM) environment is described. Features include: (1) a CONVERT TO BATCH command, usable from the ready mode; and (2) translation of the users program in stages through several levels of intermediate language and optimization. The processor is to be designed and implemented in both machine-independent and machine-dependent sections. The architecture is planned so that optimization processes are transparent to the rest of the system and need not be included in the first design implementation cycle.

Compact gasoline fuel processor for passenger vehicle APU

NASA Astrophysics Data System (ADS)

Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those component volumes. Therefore, the packaging utilizes rectangular catalyst bricks and integrates flow ducts into the heat exchangers. A concept is presented with a 25 l fuel processor volume including thermal isolation for a 3 kW el auxiliary power unit. The overall size of the system, i.e. including stack, air supply and auxiliaries can be estimated to 44 l.

77 FR 47371 - Proposed Information Collection; Comment Request; Alaska Interagency Electronic Reporting System...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-08-08

... application, shoreside processors report groundfish, crab, Pacific halibut, and sablefish production and landings data ( http://www.elandings.alaska.gov ). Processors with no Web access, such as the at-sea fleet... attachments. The vessels use satellite communications which may or may not include telephone, Internet, text...

21 CFR 120.25 - Process verification for certain processors.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 2 2011-04-01 2011-04-01 false Process verification for certain processors. 120.25 Section 120.25 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) FOOD FOR HUMAN CONSUMPTION HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) SYSTEMS...

21 CFR 120.25 - Process verification for certain processors.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 2 2012-04-01 2012-04-01 false Process verification for certain processors. 120.25 Section 120.25 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) FOOD FOR HUMAN CONSUMPTION HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) SYSTEMS...

21 CFR 120.25 - Process verification for certain processors.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 2 2014-04-01 2014-04-01 false Process verification for certain processors. 120.25 Section 120.25 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) FOOD FOR HUMAN CONSUMPTION HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) SYSTEMS...

Optical linear algebra processors: noise and error-source modeling.

PubMed

Casasent, D; Ghosh, A

1985-06-01

The modeling of system and component noise and error sources in optical linear algebra processors (OLAP's) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

Optical linear algebra processors - Noise and error-source modeling

NASA Technical Reports Server (NTRS)

Casasent, D.; Ghosh, A.

1985-01-01

The modeling of system and component noise and error sources in optical linear algebra processors (OLAPs) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

Gyro and Accelerometer Based Navigation System for a Mobile Autonomous Robot.

DTIC Science & Technology

1985-12-02

special thanks goes to our thesis advisor Dr. Matthew Kabrisky for having the confidence to turn us loose on this project. Additionally, we would...Wordmaster Word Processor 1 Wordstar Word Processor 1 Virtual Devices Robo A 6802 Cross Assembler 1 Modem 720 Communication Program 1 CP/M Operating