Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nayak, Pradipta K.; Wang, Zhenwei; Anjum, D. H.

We report highly stable gate-bias stress performance of thin film transistors (TFTs) using zinc oxide (ZnO)/hafnium oxide (HfO{sub 2}) multilayer structure as the channel layer. Positive and negative gate-bias stress stability of the TFTs was measured at room temperature and at 60 °C. A tremendous improvement in gate-bias stress stability was obtained in case of the TFT with multiple layers of ZnO embedded between HfO{sub 2} layers compared to the TFT with a single layer of ZnO as the semiconductor. The ultra-thin HfO{sub 2} layers act as passivation layers, which prevent the adsorption of oxygen and water molecules in the ZnOmore » layer and hence significantly improve the gate-bias stress stability of ZnO TFTs.« less

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

Ion Sensitive Transparent-Gate Transistor for Visible Cell Sensing.

PubMed

Sakata, Toshiya; Nishimura, Kotaro; Miyazawa, Yuuya; Saito, Akiko; Abe, Hiroyuki; Kajisa, Taira

2017-04-04

In this study, we developed an ion-sensitive transparent-gate transistor (IS-TGT) for visible cell sensing. The gate sensing surface of the IS-TGT is transparent in a solution because a transparent amorphous oxide semiconductor composed of amorphous In-Ga-Zn-oxide (a-IGZO) with a thin SiO 2 film gate that includes an indium tin oxide (ITO) film as the source and drain electrodes is utilized. The pH response of the IS-TGT was found to be about 56 mV/pH, indicating approximately Nernstian response. Moreover, the potential signals of the IS-TGT for sodium and potassium ions, which are usually included in biological environments, were evaluated. The optical and electrical properties of the IS-TGT enable cell functions to be monitored simultaneously with microscopic observation and electrical measurement. A platform based on the IS-TGT can be used as a simple and cost-effective plate-cell-sensing system based on thin-film fabrication technology in the research field of life science.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Permanent and Transient Radiation Effects on Thin-Oxide (200-A) MOS Transistors

DTIC Science & Technology

1976-06-01

n-channel technology using a SiO, gate-oxide thickness ol ’ 200 A and a %hallow phiosphorus diffusion of 0.5 pin on a 0.7-ohm)-cmn 8-doped > Si...substrate. The thickness of the sell-aligned it polysilicon gate was kept at 3500 A. The oxide was grown in dry 0, at a temperature ot 1000C, followed...semiconductor work function difference (equal to 0 V for the polysilicon gates’ studied here). The effect of the ionizing radiation is to introduce

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

PubMed Central

Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-01-01

The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

PubMed

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Unusual instability mode of transparent all oxide thin film transistor under dynamic bias condition

NASA Astrophysics Data System (ADS)

Oh, Himchan; Hwang, Chi-Sun; Pi, Jae-Eun; Ki Ryu, Min; Ko Park, Sang-Hee; Yong Chu, Hye

2013-09-01

We report a degradation behavior of fully transparent oxide thin film transistor under dynamic bias stress which is the condition similar to actual pixel switching operation in active matrix display. After the stress test, drain current increased while the threshold voltage was almost unchanged. We found that shortening of effective channel length is leading cause of increase in drain current. Electrons activate the neutral donor defects by colliding with them during short gate-on period. These ionized donors are stabilized during the subsequent gate-off period due to electron depletion. This local increase in doping density reduces the channel length.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-mobility low-temperature ZnO transistors with low-voltage operation

NASA Astrophysics Data System (ADS)

Bong, Hyojin; Lee, Wi Hyoung; Lee, Dong Yun; Kim, Beom Joon; Cho, Jeong Ho; Cho, Kilwon

2010-05-01

Low voltage high mobility n-type thin film transistors (TFTs) based on sol-gel processed zinc oxide (ZnO) were fabricated using a high capacitance ion gel gate dielectric. The ion gel gated solution-processed ZnO TFTs were found to exhibit excellent electrical properties. TFT carrier mobilities were 13 cm2/V s, ON/OFF current ratios were 105, regardless of the sintering temperature used for the preparation of the ZnO thin films. Ion gel gated ZnO TFTs are successfully demonstrated on plastic substrates for the large area flexible electronics.

High-Resolution Inkjet-Printed Oxide Thin-Film Transistors with a Self-Aligned Fine Channel Bank Structure.

PubMed

Zhang, Qing; Shao, Shuangshuang; Chen, Zheng; Pecunia, Vincenzo; Xia, Kai; Zhao, Jianwen; Cui, Zheng

2018-05-09

A self-aligned inkjet printing process has been developed to construct small channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gates on transparent glass substrates. Poly(methylsilsesquioxane) was used to pattern hydrophobic banks on the transparent substrate instead of commonly used self-assembled octadecyltrichlorosilane. Photolithographic exposure from backside using bottom-gate electrodes as mask formed hydrophilic channel areas for the TFTs. IGZO ink was selectively deposited by an inkjet printer in the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. Inkjet-printed IGZO TFTs with independent gate electrodes of 10 μm width have been demonstrated, avoiding completely printed channel beyond the broad of the gate electrodes. The TFTs showed on/off ratios of 10 8 , maximum mobility of 3.3 cm 2 V -1 s -1 , negligible hysteresis, and good uniformity. This method is conductive to minimizing the area of printed TFTs so as to the development of high-resolution printing displays.

Multi-oxide active layer deposition using Applied Materials Pivot array coater for high-mobility metal oxide TFT

NASA Astrophysics Data System (ADS)

Park, Hyun Chan; Scheer, Evelyn; Witting, Karin; Hanika, Markus; Bender, Marcus; Hsu, Hao Chien; Yim, Dong Kil

2015-11-01

By controlling a thin indium tin oxide (ITO), indium zinc oxide interface layer between gate insulator and indium gallium zinc oxide (IGZO), the thin-film transistor (TFT) performance can reach higher mobility as conventional IGZO as well as superior stability. For large-area display application, Applied Materials static PVD array coater (Applied Materials GmbH & Co. KG, Alzenau, Germany) using rotary targets has been developed to enable uniform thin layer deposition in display industry. Unique magnet motion parameter optimization in Pivot sputtering coater is shown to provide very uniform thin ITO layer to reach TFT performance with high mobility, not only on small scale, but also on Gen8.5 (2500 × 2200 mm glass size) production system.

Drying Temperature Dependence of Sol-gel Spin Coated Bilayer Composite ZnO/TiO2 Thin Films for Extended Gate Field Effect Transistor pH Sensor

NASA Astrophysics Data System (ADS)

Rahman, R. A.; Zulkefle, M. A.; Yusoff, K. A.; Abdullah, W. F. H.; Rusop, M.; Herman, S. H.

2018-03-01

This study presents an investigation on zinc oxide (ZnO) and titanium dioxide (TiO2) bilayer film applied as the sensing membrane for extended-gate field effect transistor (EGFET) for pH sensing application. The influences of the drying temperatures on the pH sensing capability of ZnO/TiO2 were investigated. The sensing performance of the thin films were measured by connecting the thin film to a commercial MOSFET to form the extended gates. By varying the drying temperature, we found that the ZnO/TiO2 thin film dried at 150°C gave the highest sensitivity compared to other drying conditions, with the sensitivity value of 48.80 mV/pH.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Kawamura, Yumi; Tani, Mai; Hattori, Nozomu; Miyatake, Naomasa; Horita, Masahiro; Ishikawa, Yasuaki; Uraoka, Yukiharu

2012-02-01

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2 V-1 s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3 thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3 gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3 film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

Solution-processed flexible fluorine-doped indium zinc oxide thin-film transistors fabricated on plastic film at low temperature.

PubMed

Seo, Jin-Suk; Jeon, Jun-Hyuck; Hwang, Young Hwan; Park, Hyungjin; Ryu, Minki; Park, Sang-Hee Ko; Bae, Byeong-Soo

2013-01-01

Transparent flexible fluorine-doped indium zinc oxide (IZO:F) thin-film transistors (TFTs) were demonstrated using the spin-coating method of the metal fluoride precursor aqueous solution with annealing at 200°C for 2 hrs on polyethylene naphthalate films. The proposed thermal evolution mechanism of metal fluoride aqueous precursor solution examined by thermogravimetric analysis and Raman spectroscopy can easily explain oxide formation. The chemical composition analysed by XPS confirms that the fluorine was doped in the thin films annealed below 250°C. In the IZO:F thin films, a doped fluorine atom substitutes for an oxygen atom generating a free electron or occupies an oxygen vacancy site eliminating an electron trap site. These dual roles of the doped fluorine can enhance the mobility and improve the gate bias stability of the TFTs. Therefore, the transparent flexible IZO:F TFT shows a high mobility of up to 4.1 cm(2)/V·s and stable characteristics under the various gate bias and temperature stresses.

Solution-Processed Flexible Fluorine-doped Indium Zinc Oxide Thin-Film Transistors Fabricated on Plastic Film at Low Temperature

PubMed Central

Seo, Jin-Suk; Jeon, Jun-Hyuck; Hwang, Young Hwan; Park, Hyungjin; Ryu, Minki; Park, Sang-Hee Ko; Bae, Byeong-Soo

2013-01-01

Transparent flexible fluorine-doped indium zinc oxide (IZO:F) thin-film transistors (TFTs) were demonstrated using the spin-coating method of the metal fluoride precursor aqueous solution with annealing at 200°C for 2 hrs on polyethylene naphthalate films. The proposed thermal evolution mechanism of metal fluoride aqueous precursor solution examined by thermogravimetric analysis and Raman spectroscopy can easily explain oxide formation. The chemical composition analysed by XPS confirms that the fluorine was doped in the thin films annealed below 250°C. In the IZO:F thin films, a doped fluorine atom substitutes for an oxygen atom generating a free electron or occupies an oxygen vacancy site eliminating an electron trap site. These dual roles of the doped fluorine can enhance the mobility and improve the gate bias stability of the TFTs. Therefore, the transparent flexible IZO:F TFT shows a high mobility of up to 4.1 cm2/V·s and stable characteristics under the various gate bias and temperature stresses. PMID:23803977

Ionic liquid gating reveals trap-filled limit mobility in low temperature amorphous zinc oxide

NASA Astrophysics Data System (ADS)

Bubel, S.; Meyer, S.; Kunze, F.; Chabinyc, M. L.

2013-10-01

In low-temperature solution processed amorphous zinc oxide (a-ZnO) thin films, we show the thin film transistor (TFT) characteristics for the trap-filled limit (TFL), when the quasi Fermi energy exceeds the conduction band edge and all tail-states are filled. In order to apply gate fields that are high enough to reach the TFL, we use an ionic liquid tape gate. Performing capacitance voltage measurements to determine the accumulated charge during TFT operation, we find the TFL at biases higher than predicted by the electronic structure of crystalline ZnO. We conclude that the density of states in the conduction band of a-ZnO is higher than in its crystalline state. Furthermore, we find no indication of percolative transport in the conduction band but trap assisted transport in the tail-states of the band.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

PubMed

Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

2016-01-27

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

Trap States of the Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Yuh, Jin Tae; Park, Sang Hee Ko; Ryu, Min Ki; Yun, Eui Jung; Bae, Byung Seong

2013-10-01

We investigated the temperature dependent recovery of the threshold voltage shift observed in both ZnO and indium gallium zinc oxide (IGZO) thin film transistors (TFTs) after application of gate bias and light illumination. Two types of recovery were observed for both the ZnO and IGZO TFTs; low temperature recovery (below 110 °C) which is attributed to the trapped charge and high temperature recovery (over 110 °C) which is related to the annihilation of trap states generated during stresses. From a comparison study of the recovery rate with the analysis of hydrogen diffusion isochronal annealing, a similar behavior was observed for both TFT recovery and hydrogen diffusion. This result suggests that hydrogen plays an important role in the generation and annihilation of trap states in oxide TFTs under gate bias or light illumination stresses.

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

Characteristics of high-k gate dielectric formed by the oxidation of sputtered Hf/Zr/Hf thin films on the Si substrate

NASA Astrophysics Data System (ADS)

Kim, H. D.; Roh, Y.; Lee, J. E.; Kang, H.-B.; Yang, C.-W.; Lee, N.-E.

2004-07-01

We have investigated the effects of high temperature annealing on the physical and electrical properties of multilayered high-k gate oxide [HfSixOy/HfO2/intermixed-layer(IL)/ZrO2/intermixed-layer(IL)/HfO2] in metal-oxide-semiconductor device. The multilayered high-k films were formed after oxidizing the Hf/Zr/Hf films deposited directly on the Si substrate. The subsequent N2 annealing at high temperature (>= 700 °C) not only results in the polycrystallization of the multilayered high-k films, but also causes the diffusion of Zr. The latter transforms the HfSixOy/HfO2/IL/ZrO2/IL/HfO2 film into the Zr-doped HfO2 film, and improves electrical properties in general. However, the thin SiOx interfacial layer starts to form if annealing temperature increases over 700 °C, deteriorating the equivalent oxide thickness. .

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

PubMed

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Bio-sorbable, liquid electrolyte gated thin-film transistor based on a solution-processed zinc oxide layer.

PubMed

Singh, Mandeep; Palazzo, Gerardo; Romanazzi, Giuseppe; Suranna, Gian Paolo; Ditaranto, Nicoletta; Di Franco, Cinzia; Santacroce, Maria Vittoria; Mulla, Mohammad Yusuf; Magliulo, Maria; Manoli, Kyriaki; Torsi, Luisa

2014-01-01

Among the metal oxide semiconductors, ZnO has been widely investigated as a channel material in thin-film transistors (TFTs) due to its excellent electrical properties, optical transparency and simple fabrication via solution-processed techniques. Herein, we report a solution-processable ZnO-based thin-film transistor gated through a liquid electrolyte with an ionic strength comparable to that of a physiological fluid. The surface morphology and chemical composition of the ZnO films upon exposure to water and phosphate-buffered saline (PBS) are discussed in terms of the operation stability and electrical performance of the ZnO TFT devices. The improved device characteristics upon exposure to PBS are associated with the enhancement of the oxygen vacancies in the ZnO lattice due to Na(+) doping. Moreover, the dissolution kinetics of the ZnO thin film in a liquid electrolyte opens the possible applicability of these devices as an active element in "transient" implantable systems.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasingmore » temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.« less

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

PubMed

Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

2017-06-14

We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

A study on the high temperature-dependence of the electrical properties in a solution-deposited zinc-tin-oxide thin-film transistor operated in the saturation region

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Bae, Byung Seong; Jung, Myunghee; Yun, Eui-Jung

2016-06-01

We investigate the effects of high temperatures in the range of 292 - 393 K on the electrical properties of solution-processed amorphous zinc-tin-oxide (a-ZTO) thin-film transistors (TFTs) operated in the saturation region. The fabricated a-ZTO TFTs have a non-patterned bottom gate and top contact structure, and they use a heavily-doped Si wafer and SiO2 as a gate electrode and a gate insulator layer, respectively. In a-ZTO TFTs, the trap release energy ( E TR ) was deduced by using Maxwell-Boltzmann statistics. The decreasing E TR toward zero with increasing gate voltage (the density of trap states ( n s )) in the a-ZTO active layer can be attributed to a shift of the Fermi level toward the mobility edge with increasing gate voltage. The TFTs with low gate voltage (low n s ) exhibit multiple trap and release characteristics and show thermally-activated behavior. In TFTs with a high gate voltage (high n s ), however, we observe decreasing mobility and conductivity with increasing temperature at temperatures ranging from 303 to 363 K. This confirms that the E TR can drop to zero, indicating a shift of the Fermi level beyond the mobility edge. Hence, the mobility edge is detected at the cusp between thermally-activated transport and band transport.

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

NASA Astrophysics Data System (ADS)

Kiani, Ahmed; Hasko, David G.; Milne, William I.; Flewitt, Andrew J.

2013-04-01

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation.

Aerosol jet printed p- and n-type electrolyte-gated transistors with a variety of electrode materials: exploring practical routes to printed electronics.

PubMed

Hong, Kihyon; Kim, Se Hyun; Mahajan, Ankit; Frisbie, C Daniel

2014-11-12

Printing electrically functional liquid inks is a promising approach for achieving low-cost, large-area, additive manufacturing of flexible electronic circuits. To print thin-film transistors, a basic building block of thin-film electronics, it is important to have several options for printable electrode materials that exhibit high conductivity, high stability, and low-cost. Here we report completely aerosol jet printed (AJP) p- and n-type electrolyte-gated transistors (EGTs) using a variety of different electrode materials including highly conductive metal nanoparticles (Ag), conducting polymers (polystyrenesulfonate doped poly(3,4-ethylendedioxythiophene, PEDOT:PSS), transparent conducting oxides (indium tin oxide), and carbon-based materials (reduced graphene oxide). Using these source-drain electrode materials and a PEDOT:PSS/ion gel gate stack, we demonstrated all-printed p- and n-type EGTs in combination with poly(3-hexythiophene) and ZnO semiconductors. All transistor components (including electrodes, semiconductors, and gate insulators) were printed by AJP. Both kinds of devices showed typical p- and n-type transistor characteristics, and exhibited both low-threshold voltages (<2 V) and high hole and electron mobilities. Our assessment suggests Ag electrodes may be the best option in terms of overall performance for both types of EGTs.

Temporal and voltage stress stability of high performance indium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Song, Yang; Katsman, Alexander; Butcher, Amy L.; Paine, David C.; Zaslavsky, Alexander

2017-10-01

Thin film transistors (TFTs) based on transparent oxide semiconductors, such as indium zinc oxide (IZO), are of interest due to their improved characteristics compared to traditional a-Si TFTs. Previously, we reported on top-gated IZO TFTs with an in-situ formed HfO2 gate insulator and IZO active channel, showing high performance: on/off ratio of ∼107, threshold voltage VT near zero, extracted low-field mobility μ0 = 95 cm2/V·s, and near-perfect subthreshold slope at 62 mV/decade. Since device stability is essential for technological applications, in this paper we report on the temporal and voltage stress stability of IZO TFTs. Our devices exhibit a small negative VT shift as they age, consistent with an increasing carrier density resulting from an increasing oxygen vacancy concentration in the channel. Under gate bias stress, freshly annealed TFTs show a negative VT shift during negative VG gate bias stress, while aged (>1 week) TFTs show a positive VT shift during negative VG stress. This indicates two competing mechanisms, which we identify as the field-enhanced generation of oxygen vacancies and the field-assisted migration of oxygen vacancies, respectively. A simplified kinetic model of the vacancy concentration evolution in the IZO channel under electrical stress is provided.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Effect of gate voltage polarity on the ionic liquid gating behavior of NdNiO 3/NdGaO 3 heterostructures

DOE PAGES

Dong, Yongqi; Xu, Haoran; Luo, Zhenlin; ...

2017-05-16

The effect of gate voltage polarity on the behavior of NdNiO 3 epitaxial thin films during ionic liquid gating is studied using in situ synchrotron X-ray techniques. We show that while negative biases have no discernible effect on the structure or composition of the films, large positive gate voltages result in the injection of a large concentration of oxygen vacancies (similar to 3%) and pronounced lattice expansion (0.17%) in addition to a 1000-fold increase in sheet resistance at room temperature. Despite the creation of large defect densities, the heterostructures exhibit a largely reversible switching behavior when sufficient time is providedmore » for the vacancies to migrate in and out of the thin film surface. The results confirm that electrostatic gating takes place at negative gate voltages for p-type complex oxides while positive voltages favor the electrochemical reduction of Ni 3+. Switching between positive and negative gate voltages therefore involves a combination of electronic and ionic doping processes that may be utilized in future electrochemical transistors.« less

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Kwang-Won; Cho, Won-Ju, E-mail: chowj@kw.ac.kr

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristicmore » trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.« less

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Niang, K. M.; Flewitt, A. J., E-mail: ajf@eng.cam.ac.uk; Barquinha, P. M. C.

Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys.more » 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.« less

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

NASA Astrophysics Data System (ADS)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Effect of Al-diffusion-induced positive flatband voltage shift on the electrical characteristics of Al-incorporated high-k metal-oxide-semiconductor field-effective transistor

NASA Astrophysics Data System (ADS)

Wang, Wenwu; Akiyama, Koji; Mizubayashi, Wataru; Nabatame, Toshihide; Ota, Hiroyuki; Toriumi, Akira

2009-03-01

We systematically studied what effect Al diffusion from high-k dielectrics had on the flatband voltage (Vfb) of Al-incorporated high-k gate stacks. An anomalous positive shift fin Vfb with the decreasing equivalent oxide thickness (EOT) of high-k gate stacks is reported. As the SiO2 interfacial layer is aggressively thinned in Al-incorporated HfxAl1-xOy gate stacks with a metal-gate electrode, the Vfb first lies on the well known linear Vfb-EOT plot and deviates toward the positive-voltage direction (Vfb roll-up), followed by shifting toward negative voltage (Vfb roll-off). We demonstrated that the Vfb roll-up behavior remarkably decreases the threshold voltage (Vth) of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs), and does not cause severe degradation in the characteristics of hole mobility. The Vfb roll-up behavior, which is independent of gate materials but strongly dependent on high-k dielectrics, was ascribed to variations in fixed charges near the SiO2/Si interface, which are caused by Al diffusion from HfxAl1-xOy through SiO2 to the SiO2/Si interface. These results indicate that anomalous positive shift in Vfb, i.e., Vfb roll-up, should be taken into consideration in quantitatively adjusting Vfb in thin EOT regions and that it could be used to further tune Vth in p-MOSFETs.

Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor.

PubMed

Nomura, Kenji; Ohta, Hiromichi; Ueda, Kazushige; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

2003-05-23

We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO3(ZnO)5, as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of approximately 106 and a field-effect mobility of approximately 80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

PubMed Central

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Modification of FN tunneling provoking gate-leakage current in ZTO (zinc-tin oxide) TFT by regulating the ZTO/SiO2 area ratio

NASA Astrophysics Data System (ADS)

Li, Jeng-Ting; Tsai, Ho-Lin; Lai, Wei-Yao; Hwang, Weng-Sing; Chen, In-Gann; Chen, Jen-Sue

2018-04-01

This study addresses the variation in gate-leakage current due to the Fowler-Nordheim (FN) tunneling of electrons through a SiO2 dielectric layer in zinc-tin oxide (ZTO) thin film transistors. It is shown that the gate-leakage current is not related to the absolute area of the ZTO active layer, but it is reduced by reducing the ZTO/SiO2 area ratio. The ZTO/SiO2 area ratio modulates the ZTO-SiO2 interface dipole strength as well as the ZTO-SiO2 conduction band offset and subsequently affects the FN tunneling current through the SiO2 layer, which provides a route that modifies the gate-leakage current.

Complex oxide thin films for microelectronics

NASA Astrophysics Data System (ADS)

Suvorova, Natalya

The rapid scaling of the device dimensions, namely in metal oxide semiconductor field effect transistor (MOSFET), is reaching its fundamental limit which includes the increase in allowable leakage current due to direct tunneling with decrease of physical thickness of SiO2 gate dielectric. The significantly higher relative dielectric constant (in the range 9--25) of the gate dielectric beyond the 3.9 value of silicon dioxide will allow increasing the physical thickness. Among the choices for the high dielectric constant (K) materials for future generation MOSFET application, barium strontium titanate (BST) and strontium titanate (STO) possess one of the highest attainable K values making them the promising candidates for alternative gate oxide. However, the gate stack engineering does not imply the simple replacement of the SiO2 with the new dielectric. Several requirements should be met for successful integration of a new material. The major one is a production of high level of interface states (Dit) compared to that of SiO 2 on Si. An insertion of a thin SiO2 layer prior the growth of high-K thin film is a simple solution that helps to limit reaction with Si substrate and attains a high quality interface. However, the combination of two thin films reduces the overall K of the dielectric stack. An optimization of the SiO2 underlayer in order to maintain the interface quality yet minimize the effect on K is the focus of this work. The results from our study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST and STO films sputter deposited on thermally oxidized Si substrates spectroscopic ellipsometry in combination with time of flight ion scattering and recoil spectrometry have been employed. Studies of material properties have been complemented with analytical electron microscopy. To evaluate the interface quality the electrical characterization has been employed using capacitance-voltage and conductance-voltage measurements. Special attention was given to the extraction of static dielectric constant of BST and STO from the multiple film stack. The K value was found to be sensitive to the input parameters such as dielectric constant and thickness of interface layers.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

NASA Astrophysics Data System (ADS)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizingmore » controllable high-performance stable transistors.« less

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

NASA Astrophysics Data System (ADS)

Yun, Ho-Jin; Kim, Young-Su; Jeong, Kwang-Seok; Kim, Yu-Mi; Yang, Seung-dong; Lee, Hi-Deok; Lee, Ga-Won

2014-01-01

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = -20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

Oxide-based materials by atomic layer deposition

NASA Astrophysics Data System (ADS)

Godlewski, Marek; Pietruszka, Rafał; Kaszewski, Jarosław; Witkowski, Bartłomiej S.; Gierałtowska, Sylwia; Wachnicki, Łukasz; Godlewski, Michał M.; Slonska, Anna; Gajewski, Zdzisław

2017-02-01

Thin films of wide band-gap oxides grown by Atomic Layer Deposition (ALD) are suitable for a range of applications. Some of these applications will be presented. First of all, ALD-grown high-k HfO2 is used as a gate oxide in the electronic devices. Moreover, ALD-grown oxides can be used in memory devices, in transparent transistors, or as elements of solar cells. Regarding photovoltaics (PV), ALD-grown thin films of Al2O3 are already used as anti-reflection layers. In addition, thin films of ZnO are tested as replacement of ITO in PV devices. New applications in organic photovoltaics, electronics and optoelectronics are also demonstrated Considering new applications, the same layers, as used in electronics, can also find applications in biology, medicine and in a food industry. This is because layers of high-k oxides show antibacterial activity, as discussed in this work.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakhri, M.; Theisen, M.; Behrendt, A.

Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices withmore » encapsulation.« less

Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors

NASA Astrophysics Data System (ADS)

Tsao, Yu-Ching; Chang, Ting-Chang; Chen, Hua-Mao; Chen, Bo-Wei; Chiang, Hsiao-Cheng; Chen, Guan-Fu; Chien, Yu-Chieh; Tai, Ya-Hsiang; Hung, Yu-Ju; Huang, Shin-Ping; Yang, Chung-Yi; Chou, Wu-Ching

2017-01-01

This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software.

Crystalline-like temperature dependence of the electrical characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors

NASA Astrophysics Data System (ADS)

Estrada, M.; Hernandez-Barrios, Y.; Cerdeira, A.; Ávila-Herrera, F.; Tinoco, J.; Moldovan, O.; Lime, F.; Iñiguez, B.

2017-09-01

A crystalline-like temperature dependence of the electrical characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) is reported, in which the drain current reduces as the temperature is increased. This behavior appears for values of drain and gate voltages above which a change in the predominant conduction mechanism occurs. After studying the possible conduction mechanisms, it was determined that, for gate and drain voltages below these values, hopping is the predominant mechanism with the current increasing with temperature, while for values above, the predominant conduction mechanism becomes percolation in the conduction band or band conduction and IDS reduces as the temperature increases. It was determined that this behavior appears, when the effect of trapping is reduced, either by varying the density of states, their characteristic energy or both. Simulations were used to further confirm the causes of the observed behavior.

Influences of Gate Bias and Light Stresses on Device Characteristics of High-Energy Electron-Beam-Irradiated Indium Gallium Zinc Oxide Based Thin Film Transistors

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Moon, Hye Ji; Ryu, Min Ki; Cho, Kyoung Ik; Yun, Eui-Jung; Bae, Byung Seong

2012-09-01

Under white light illumination, amorphous indium-gallium-zinc oxide (a-IGZO)-based thin-film transistors (TFTs) showed a large negative shift of threshold voltage of more than -15 V depending on the process conditions. We investigated the influences of both gate bias and white light illumination on device properties of IGZO-based TFTs untreated and treated with high-energy electron beam irradiation (HEEBI). The TFTs were treated with HEEBI in air at room temperature (RT), electron beam energy of 0.8 MeV, and a dose of 1×1014 electrons/cm2. The HEEBI-treated TFTs showed an improved stability under negative bias illumination stress (NBIS) and positive bias illumination stress (PBIS) compared with non-HEEBI-treated TFTs, suggesting that the acceptor-like defects might be generated by HEEBI treatment near the valence band edge.

Oxide Semiconductor-Based Flexible Organic/Inorganic Hybrid Thin-Film Transistors Fabricated on Polydimethylsiloxane Elastomer.

PubMed

Jung, Soon-Won; Choi, Jeong-Seon; Park, Jung Ho; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lim, Sang Chul; Lee, Sang Seok; Chu, Hye Yong

2016-03-01

We demonstrate flexible organic/inorganic hybrid thin-film transistors (TFTs) on a polydimethysilox- ane (PDMS) elastomer substrate. The active channel and gate insulator of the hybrid TFT are composed of In-Ga-Zn-O (IGZO) and blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF- TrFE)] with poly(methyl methacrylate) (PMMA), respectively. It has been confirmed that the fabri- cated TFT display excellent characteristics: the recorded field-effect mobility, sub-threshold voltage swing, and I(on)/I(off) ratio were approximately 0.35 cm2 V(-1) s(-1), 1.5 V/decade, and 10(4), respectively. These characteristics did not experience any degradation at a bending radius of 15 mm. These results correspond to the first demonstration of a hybrid-type TFT using an organic gate insulator/oxide semiconducting active channel structure fabricated on PDMS elastomer, and demonstrate the feasibility of a promising device in a flexible electronic system.

Fabrication of Stretchable Organic-Inorganic Hybrid Thin-Film Transistors on Polyimide Stiff-Island Structures.

PubMed

Jung, Soon-Won; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lee, Sang Seok

2015-10-01

In this study, stretchable organic-inorganic hybrid thin-film transistors (TFTs) are fabricated on a polyimide (PI) stiff-island/elastomer substrate using blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) and oxide semiconductor In-Ga-Zn-O as the gate dielectric and semiconducting layer, respectively. Carrier mobility, Ion/Ioff ratio, and subthreshold swing (SS) values of 6.1 cm2 V(-1) s(-1), 10(7), and 0.2 V/decade, respectively, were achieved. For the hybrid TFTs, the endurable maximum strain without degradation of electrical properties was approximately 49%. These results correspond to those obtained in the first study on fabrication of stretchable hybrid-type TFTs on elastomer substrate using an organic gate insulator and oxide semiconducting active channel structure, thus indicating the feasibility of a promising device for stretchable electronic systems.

Defect generation in amorphous-indium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2014-04-07

We report on the generation and characterization of a hump in the transfer characteristics of amorphous indium gallium zinc-oxide thin-film transistors by positive bias temperature stress. The hump depends strongly on the gate bias stress at 100 °C. Due to the hump, the positive shift of the transfer characteristic in deep depletion is always smaller that in accumulation. Since, the latter shift is twice the former, with very good correlation, we conclude that the effect is due to creation of a double acceptor, likely to be a cation vacancy. Our results indicate that these defects are located near the gate insulator/activemore » layer interface, rather than in the bulk. Migration of donor defects from the interface towards the bulk may also occur under PBST at 100 °C.« less

Light-induced hysteresis and recovery behaviors in photochemically activated solution-processed metal-oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Jeong-Wan; Park, Sung Kyu, E-mail: yhkim76@skku.edu, E-mail: skpark@cau.ac.kr; Kim, Yong-Hoon, E-mail: yhkim76@skku.edu, E-mail: skpark@cau.ac.kr

2014-07-28

In this report, photo-induced hysteresis, threshold voltage (V{sub T}) shift, and recovery behaviors in photochemically activated solution-processed indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are investigated. It was observed that a white light illumination caused negative V{sub T} shift along with creation of clockwise hysteresis in electrical characteristics which can be attributed to photo-generated doubly ionized oxygen vacancies at the semiconductor/gate dielectric interface. More importantly, the photochemically activated IGZO TFTs showed much reduced overall V{sub T} shift compared to thermally annealed TFTs. Reduced number of donor-like interface states creation under light illumination and more facile neutralization of ionized oxygen vacancies bymore » electron capture under positive gate potential are claimed to be the origin of the less V{sub T} shift in photochemically activated TFTs.« less

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

NASA Astrophysics Data System (ADS)

Chen, Ya-Yi; Liu, Yuan; Wu, Zhao-Hui; Wang, Li; Li, Bin; En, Yun-Fei; Chen, Yi-Qiang

2018-04-01

Not Available Supported by the National Natural Science Foundation of China under Grant No 61574048, the Science and Technology Research Project of Guangdong Province under Grant Nos 2015B090912002 and 2015B090901048, and the Pearl River S&T Nova Program of Guangzhou under Grant No 201710010172.

Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

NASA Astrophysics Data System (ADS)

Mativenga, Mallory; Kang, Dong Han; Lee, Ung Gi; Jang, Jin

2012-09-01

Bias instability of top-gate amorphous-indium-gallium-zinc-oxide thin-film transistors with source- and drain-offsets is reported. Positive and negative gate bias-stress (VG_STRESS) respectively induce reversible negative threshold-voltage shift (ΔVTH) and reduction in on-current. Migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in the abnormal negative ΔVTH under positive VG_STRESS. The reduction in on-current under negative VG_STRESS is due to increase in resistance of the offsets when positive charges migrate away from the offsets. Appropriate drain and source bias-stresses applied simultaneously with VG_STRESS either suppress or enhance the instability, verifying lateral ion migration to be the instability mechanism.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Precursor-route ZnO films from a mixed casting solvent for high performance aqueous electrolyte-gated transistors.

PubMed

Althagafi, Talal M; Algarni, Saud A; Al Naim, Abdullah; Mazher, Javed; Grell, Martin

2015-12-14

We significantly improved the performance of precursor-route semiconducting zinc oxide (ZnO) films in electrolyte-gated thin film transistors (TFTs). We find that the organic precursor to ZnO, zinc acetate (ZnAc), dissolves more readily in a 1 : 1 mixture of ethanol (EtOH) and acetone than in pure EtOH, pure acetone, or pure isopropanol. XPS and SEM characterisation show improved morphology of ZnO films converted from a mixed solvent cast ZnAc precursor compared to the EtOH cast precursor. When gated with a biocompatible electrolyte, phosphate buffered saline (PBS), ZnO thin film transistors (TFTs) derived from mixed solvent cast ZnAc give 4 times larger field effect current than similar films derived from ZnAc cast from pure EtOH. The sheet resistance at VG = VD = 1 V is 30 kΩ □(-1), lower than for any organic TFT, and lower than for any electrolyte-gated ZnO TFT reported to date.

Pronounced photogating effect in atomically thin WSe2 with a self-limiting surface oxide layer

NASA Astrophysics Data System (ADS)

Yamamoto, Mahito; Ueno, Keiji; Tsukagoshi, Kazuhito

2018-04-01

The photogating effect is a photocurrent generation mechanism that leads to marked responsivity in two-dimensional (2D) semiconductor-based devices. A key step to promote the photogating effect in a 2D semiconductor is to integrate it with a high density of charge traps. Here, we show that self-limiting surface oxides on atomically thin WSe2 can serve as effective electron traps to facilitate p-type photogating. By examining the gate-bias-induced threshold voltage shift of a p-type transistor based on single-layer WSe2 with surface oxide, the electron trap density and the trap rate of the oxide are determined to be >1012 cm-2 and >1010 cm-2 s-1, respectively. White-light illumination on an oxide-covered 4-layer WSe2 transistor leads to the generation of photocurrent, the magnitude of which increases with the hole mobility. During illumination, the photocurrent evolves on a timescale of seconds, and a portion of the current persists even after illumination. These observations indicate that the photogenerated electrons are trapped deeply in the surface oxide and effectively gate the underlying WSe2. Owing to the pronounced photogating effect, the responsivity of the oxide-covered WSe2 transistor is observed to exceed 3000 A/W at an incident optical power of 1.1 nW, suggesting the effectiveness of surface oxidation in facilitating the photogating effect in 2D semiconductors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori

We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{submore » 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.« less

Improvement of Self-Heating of Indium Gallium Zinc Aluminum Oxide Thin-Film Transistors Using Al2O3 Barrier Layer

NASA Astrophysics Data System (ADS)

Jian, Li-Yi; Lee, Hsin-Ying; Lin, Yung-Hao; Lee, Ching-Ting

2018-02-01

To study the self-heating effect, aluminum oxide (Al2O3) barrier layers of various thicknesses have been inserted between the channel layer and insulator layer in bottom-gate-type indium gallium zinc aluminum oxide (IGZAO) thin-film transistors (TFTs). Each IGZAO channel layer was deposited on indium tin oxide (ITO)-coated glass substrate by using a magnetron radiofrequency cosputtering system with dual targets composed of indium gallium zinc oxide (IGZO) and Al. The 3 s orbital of Al cation provided an extra transport pathway and widened the conduction-band bottom, thus increasing the electron mobility of the IGZAO films. The Al-O bonds were able to sustain the oxygen stability of the IGZAO films. The self-heating behavior of the resulting IGZAO TFTs was studied by Hall measurements on the IGZAO films as well as the electrical performance of the IGZAO TFTs with Al2O3 barrier layers of various thicknesses at different temperatures. IGZAO TFTs with 50-nm-thick Al2O3 barrier layer were stressed by positive gate bias stress (PGBS, at gate-source voltage V GS = 5 V and drain-source voltage V DS = 0 V); at V GS = 5 V and V DS = 10 V, the threshold voltage shifts were 0.04 V and 0.2 V, respectively, much smaller than for the other IGZAO TFTs without Al2O3 barrier layer, which shifted by 0.2 V and 1.0 V when stressed under the same conditions.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Thermal oxidation of silicon in a residual oxygen atmosphere—the RESOX process—for self-limiting growth of thin silicon dioxide films

NASA Astrophysics Data System (ADS)

Wright, Jason T.; Carbaugh, Daniel J.; Haggerty, Morgan E.; Richard, Andrea L.; Ingram, David C.; Kaya, Savas; Jadwisienczak, Wojciech M.; Rahman, Faiz

2016-10-01

We describe in detail the growth procedures and properties of thermal silicon dioxide grown in a limited and dilute oxygen atmosphere. Thin thermal oxide films have become increasingly important in recent years due to the continuing down-scaling of ultra large scale integration metal oxide silicon field effect transistors. Such films are also of importance for organic transistors where back-gating is needed. The technique described here is novel and allows self-limited formation of high quality thin oxide films on silicon surfaces. This technique is easy to implement in both research laboratory and industrial settings. Growth conditions and their effects on film growth have been described. Properties of the resulting oxide films, relevant for microelectronic device applications, have also been investigated and reported here. Overall, our findings are that thin, high quality, dense silicon dioxide films of thicknesses up to 100 nm can be easily grown in a depleted oxygen environment at temperatures similar to that used for usual silicon dioxide thermal growth in flowing dry oxygen.

ZnO thin film transistor immunosensor with high sensitivity and selectivity

NASA Astrophysics Data System (ADS)

Reyes, Pavel Ivanoff; Ku, Chieh-Jen; Duan, Ziqing; Lu, Yicheng; Solanki, Aniruddh; Lee, Ki-Bum

2011-04-01

A zinc oxide thin film transistor-based immunosensor (ZnO-bioTFT) is presented. The back-gate TFT has an on-off ratio of 108 and a threshold voltage of 4.25 V. The ZnO channel surface is biofunctionalized with primary monoclonal antibodies that selectively bind with epidermal growth factor receptor (EGFR). Detection of the antibody-antigen reaction is achieved through channel carrier modulation via pseudo double-gating field effect caused by the biochemical reaction. The sensitivity of 10 fM detection of pure EGFR proteins is achieved. The ZnO-bioTFT immunosensor also enables selectively detecting 10 fM of EGFR in a 5 mg/ml goat serum solution containing various other proteins.

Single crystal functional oxides on silicon

PubMed Central

Bakaul, Saidur Rahman; Serrao, Claudy Rayan; Lee, Michelle; Yeung, Chun Wing; Sarker, Asis; Hsu, Shang-Lin; Yadav, Ajay Kumar; Dedon, Liv; You, Long; Khan, Asif Islam; Clarkson, James David; Hu, Chenming; Ramesh, Ramamoorthy; Salahuddin, Sayeef

2016-01-01

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon. PMID:26853112

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors.

PubMed

Singh, Shaivalini; Chakrabarti, P

2014-05-01

ZnO based bottom-gate thin film transistor (TFT) with SiO2 as insulating layer has been fabricated with two different structures. The effect of formation of mesa structure on the electrical characteristics of the TFTs has been studied. The formation of mesa structure of ZnO channel region can definitely result in better control over channel region and enhance value of channel mobility of ZnO TFT. As a result, by fabricating a mesa structured TFT, a better value of mobility and on-state current are achieved at low voltages. A typical saturation current of 1.85 x 10(-7) A under a gate bias of 50 V is obtained for non mesa structure TFT while for mesa structured TFT saturation current of 5 x 10(-5) A can be obtained at comparatively very low gate bias of 6.4 V.

Control of magnetism by electrical charge doping or redox reactions in a surface-oxidized Co thin film with a solid-state capacitor structure

NASA Astrophysics Data System (ADS)

Hirai, T.; Koyama, T.; Chiba, D.

2018-03-01

We have investigated the electric field (EF) effect on magnetism in a Co thin film with a naturally oxidized surface. The EF was applied to the oxidized Co surface through a gate insulator layer made of HfO2, which was formed using atomic layer deposition (ALD). The efficiency of the EF effect on the magnetic anisotropy in the sample with the HfO2 layer deposited at the appropriate temperature for the ALD process was relatively large compared to the previously reported values with an unoxidized Co film. The coercivity promptly and reversibly followed the variation in gate voltage. The modulation of the channel resistance was at most ˜0.02%. In contrast, a dramatic change in the magnetic properties including the large change in the saturation magnetic moment and a much larger EF-induced modulation of the channel resistance (˜10%) were observed in the sample with a HfO2 layer deposited at a temperature far below the appropriate temperature range. The response of these properties to the gate voltage was very slow, suggesting that a redox reaction dominated the EF effect on the magnetism in this sample. The frequency response for the capacitive properties was examined to discuss the difference in the mechanism of the EF effect observed here.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

High Mobility Thin Film Transistors Based on Amorphous Indium Zinc Tin Oxide

PubMed Central

Noviyana, Imas; Lestari, Annisa Dwi; Putri, Maryane; Won, Mi-Sook; Bae, Jong-Seong; Heo, Young-Woo; Lee, Hee Young

2017-01-01

Top-contact bottom-gate thin film transistors (TFTs) with zinc-rich indium zinc tin oxide (IZTO) active layer were prepared at room temperature by radio frequency magnetron sputtering. Sintered ceramic target was prepared and used for deposition from oxide powder mixture having the molar ratio of In2O3:ZnO:SnO2 = 2:5:1. Annealing treatment was carried out for as-deposited films at various temperatures to investigate its effect on TFT performances. It was found that annealing treatment at 350 °C for 30 min in air atmosphere yielded the best result, with the high field effect mobility value of 34 cm2/Vs and the minimum subthreshold swing value of 0.12 V/dec. All IZTO thin films were amorphous, even after annealing treatment of up to 350 °C. PMID:28773058

Insulator to metal transition in WO 3 induced by electrolyte gating

DOE PAGES

Leng, X.; Pereiro, J.; Strle, J.; ...

2017-07-03

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Investigation of Gate-Stacked In-Ga-Zn-O TFTs with Ga-Zn-O Source/Drain Electrodes by Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition.

PubMed

Wu, Chien-Hung; Chang, Kow-Ming; Chen, Yi-Ming; Huang, Bo-Wen; Zhang, Yu-Xin; Wang, Shui-Jinn; Hsu, Jui-Mei

2018-03-01

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) was employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO TFTs) with high transparent gallium zinc oxide (GZO) source/drain electrodes. The influence of post-deposition annealing (PDA) temperature on GZO source/drain and device performance was studied. Device with a 300 °C annealing demonstrated excellent electrical characteristics with on/off current ratio of 2.13 × 108, saturation mobility of 10 cm2/V-s, and low subthreshold swing of 0.2 V/dec. The gate stacked LaAlO3/ZrO2 of AP-IGZO TFTs with highly transparent and conductive AP-GZO source/drain electrode show excellent gate control ability at a low operating voltage.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Achieving high carrier mobility exceeding 70 cm2/Vs in amorphous zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Tae; Shin, Yeonwoo; Yun, Pil Sang; Bae, Jong Uk; Chung, In Jae; Jeong, Jae Kyeong

2017-09-01

This paper proposes a new defect engineering concept for low-cost In- and Ga-free zinc tin oxide (ZTO) thin-film transistors (TFTs). This concept is comprised of capping ZTO films with tantalum (Ta) and a subsequent modest thermal annealing treatment at 200 °C. The Ta-capped ZTO TFTs exhibited a remarkably high carrier mobility of 70.8 cm2/Vs, low subthreshold gate swing of 0.18 V/decade, threshold voltage of -1.3 V, and excellent ION/OFF ratio of 2 × 108. The improvement (> two-fold) in the carrier mobility compared to the uncapped ZTO TFT can be attributed to the effective reduction of the number of adverse tailing trap states, such as hydroxyl groups or oxygen interstitial defects, which stems from the scavenging effect of the Ta capping layer on the ZTO channel layer. Furthermore, the Ta-capped ZTO TFTs showed excellent positive and negative gate bias stress stabilities. [Figure not available: see fulltext.

Analytical drain current model for symmetric dual-gate amorphous indium gallium zinc oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Qin, Ting; Liao, Congwei; Huang, Shengxiang; Yu, Tianbao; Deng, Lianwen

2018-01-01

An analytical drain current model based on the surface potential is proposed for amorphous indium gallium zinc oxide (a-InGaZnO) thin-film transistors (TFTs) with a synchronized symmetric dual-gate (DG) structure. Solving the electric field, surface potential (φS), and central potential (φ0) of the InGaZnO film using the Poisson equation with the Gaussian method and Lambert function is demonstrated in detail. The compact analytical model of current-voltage behavior, which consists of drift and diffusion components, is investigated by regional integration, and voltage-dependent effective mobility is taken into account. Comparison results demonstrate that the calculation results obtained using the derived models match well with the simulation results obtained using a technology computer-aided design (TCAD) tool. Furthermore, the proposed model is incorporated into SPICE simulations using Verilog-A to verify the feasibility of using DG InGaZnO TFTs for high-performance circuit designs.

Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

NASA Astrophysics Data System (ADS)

Konwar, K.; Baishya, B.

2010-12-01

Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La2O3, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07×10-3 cm2V-1s-1 for the devices annealed in vacuum at 90° C for 5 hours.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Direct imprinting of indium-tin-oxide precursor gel and simultaneous formation of channel and source/drain in thin-film transistor

NASA Astrophysics Data System (ADS)

Haga, Ken-ichi; Kamiya, Yuusuke; Tokumitsu, Eisuke

2018-02-01

We report on a new fabrication process for thin-film transistors (TFTs) with a new structure and a new operation principle. In this process, both the channel and electrode (source/drain) are formed simultaneously, using the same oxide material, using a single nano-rheology printing (n-RP) process, without any conventional lithography process. N-RP is a direct thermal imprint technique and deforms oxide precursor gel. To reduce the source/drain resistance, the material common to the channel and electrode is conductive indium-tin-oxide (ITO). The gate insulator is made of a ferroelectric material, whose high charge density can deplete the channel of the thin ITO film, which realizes the proposed operation principle. First, we have examined the n-RP conditions required for the channel and source/drain patterning, and found that the patterning properties are strongly affected by the cooling rate before separating the mold. Second, we have fabricated the TFTs as proposed and confirmed their TFT operation.

Cyclical Annealing Technique To Enhance Reliability of Amorphous Metal Oxide Thin Film Transistors.

PubMed

Chen, Hong-Chih; Chang, Ting-Chang; Lai, Wei-Chih; Chen, Guan-Fu; Chen, Bo-Wei; Hung, Yu-Ju; Chang, Kuo-Jui; Cheng, Kai-Chung; Huang, Chen-Shuo; Chen, Kuo-Kuang; Lu, Hsueh-Hsing; Lin, Yu-Hsin

2018-02-26

This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional long-term annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

PubMed

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

The ZnO-FET Biosensor for Cardiac Troponin I

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md; Nuzaihan, M. N. M.; Gopinath, Subash C. B.; Ruslinda, A. R.; Hashim, U.

2018-03-01

This paper investigates the influence of substrate-gate coupling on the ZnO-FET biosensor’s sensitivity for detection of cardiac troponin I (cTnI), a ‘gold standard’ biomarker for acute myocardial infarction (AMI). The FET-based device with introduction of substrate-gate coupling on p-type silicon-on-insulator (SOI) substrate is fabricated using conventional lithography processes. An n-type zinc oxide (ZnO) thin film deposited via electron-beam evaporator is used as transducer for bridging the source and drain regions. Surface modifications via functionalization with 3-aminopropyltriethoxysilane (APTES) and glutaraldehyde (GA) as chemical linkers, followed by immobilization of cTnI monoclonal antibody (MAb-cTnI) as bio-receptor on the ZnO thin film allow different concentration of cTnI detection with high selectivity. The device’s sensitivity increases up to 9 %·(g/ml)-1 with the increase of the substrate-gate voltage (VSG) up to -10 V at very low limit of detection (LOD) down to 1.6 fg/ml.

Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

PubMed Central

Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

2015-01-01

Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

Deposition and characterization of vanadium oxide based thin films for MOS device applications

NASA Astrophysics Data System (ADS)

Rakshit, Abhishek; Biswas, Debaleen; Chakraborty, Supratic

2018-04-01

Vanadium Oxide films are deposited on Si (100) substrate by reactive RF-sputtering of a pure Vanadium metallic target in an Argon-Oxygen plasma environment. The ratio of partial pressures of Argon to Oxygen in the sputtering-chamber is varied by controlling their respective flow rates and the resultant oxide films are obtained. MOS Capacitor based devices are then fabricated using the deposited oxide films. High frequency Capacitance-Voltage (C-V) and gate current-gate voltage (I-V) measurements reveal a significant dependence of electrical characteristics of the deposited films on their sputtering deposition parameters mainly, the relative content of Argon/Oxygen in the plasma chamber. A noteworthy change in the electrical properties is observed for the films deposited under higher relative oxygen content in the plasma atmosphere. Our results show that reactive sputtering serves as an indispensable deposition-setup for fabricating vanadium oxide based MOS devices tailor-made for Non-Volatile Memory (NVM) applications.

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction

NASA Astrophysics Data System (ADS)

Mohamad, B.; Leroux, C.; Reimbold, G.; Ghibaudo, G.

2018-01-01

For advanced gate stacks, effective work function (WFeff) and equivalent oxide thickness (EOT) are fundamental parameters for technology optimization. On FDSOI transistors, and contrary to the bulk technologies, while EOT can still be extracted at strong inversion from the typical gate-to-channel capacitance (Cgc), it is no longer the case for WFeff due to the disappearance of an observable flat band condition on capacitance characteristics. In this work, a new experimental method, the Cbg(VBG) characteristic, is proposed in order to extract the well flat band condition (VFB, W). This characteristic enables an accurate and direct evaluation of WFeff. Moreover, using the previous extraction of the gate oxide (tfox), and buried oxide (tbox) from typical capacitance characteristics (Cgc and Cbc), it allows the extraction of the channel thickness (tch). Furthermore, the measurement of the well flat band condition on Cbg(VBG) characteristics for two different Si and SiGe channel also proves the existence of a dipole at the SiGe/SiO2 interface.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Jong Woo; Nathan, Arokia, E-mail: an299@cam.ac.uk; Barquinha, Pedro

2016-08-15

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (V{sub TH}) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarizationmore » density. The second type of anomaly is negative V{sub TH} shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H{sub 2}O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.« less

Bi-layer channel structure-based oxide thin-film transistors consisting of ZnO and Al-doped ZnO with different Al compositions and stacking sequences

NASA Astrophysics Data System (ADS)

Cho, Sung Woon; Yun, Myeong Gu; Ahn, Cheol Hyoun; Kim, So Hee; Cho, Hyung Koun

2015-03-01

Zinc oxide (ZnO)-based bi-layers, consisting of ZnO and Al-doped ZnO (AZO) layers grown by atomic layer deposition, were utilized as the channels of oxide thin-film transistors (TFTs). Thin AZO layers (5 nm) with different Al compositions (5 and 14 at. %) were deposited on top of and beneath the ZnO layers in a bi-layer channel structure. All of the bi-layer channel TFTs that included the AZO layers showed enhanced stability (Δ V Th ≤ 3.2 V) under a positive bias stress compared to the ZnO single-layer channel TFT (Δ V Th = 4.0 V). However, the AZO/ZnO bi-layer channel TFTs with an AZO interlayer between the gate dielectric and the ZnO showed a degraded field effect mobility (0.3 cm2/V·s for 5 at. % and 1.8 cm2/V·s for 14 at. %) compared to the ZnO single-layer channel TFT (5.5 cm2/V·s) due to increased scattering caused by Al-related impurities near the gate dielectric/channel interface. In contrast, the ZnO/AZO bi-layer channel TFTs with an AZO layer on top of the ZnO layer exhibited an improved field effect mobility (7.8 cm2/V·s for 14 at. %) and better stability. [Figure not available: see fulltext.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ao; Liu, Guoxia, E-mail: gxliu@qdu.edu.cn, E-mail: fukaishan@yahoo.com; Zhu, Huihui

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiO{sub x}) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiO{sub x} TFTs, together with the characteristics of NiO{sub x} thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric, the electrical performance of NiO{sub x} TFT was improved significantly compared with those based on SiO{submore » 2} dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm{sup 2}/V s, which is mainly beneficial from the high areal capacitance of the Al{sub 2}O{sub 3} dielectric and high-quality NiO{sub x}/Al{sub 2}O{sub 3} interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.« less

Coaxially gated in-wire thin-film transistors made by template assembly.

PubMed

Kovtyukhova, Nina I; Kelley, Brian K; Mallouk, Thomas E

2004-10-13

Nanowire field effect transistors were prepared by a wet chemical template replication method using anodic aluminum oxide membranes. The membrane pores were first lined with a thin SiO2 layer by the surface sol-gel method. Au, CdS (or CdSe), and Au wire segments were then sequentially electrodeposited within the pores, and the resulting nanowires were released by dissolution of the membrane. Electrofluidic alignment of these nanowires between source and drain leads and evaporation of gold over the central CdS (CdSe) stripe affords a "wrap-around gate" structure. At VDS = -2 V, the Au/CdS/Au devices had an ON/OFF current ratio of 103, a threshold voltage of 2.4 V, and a subthreshold slope of 2.2 V/decade. A 3-fold decrease in the subthreshold slope relative to that of planar nanocrystalline CdSe devices can be attributed to coaxial gating. The control of dimensions afforded by template synthesis should make it possible to reduce the gate dielectric thickness, channel length, and diameter of the semiconductor segment to sublithographic dimensions while retaining the simplicity of the wet chemical synthetic method.

A Survey of Solid-State Microwave Power Devices

DTIC Science & Technology

1977-04-29

from the channel by a thin oxide layer (insulated gate FET or IGFET), it may be a diffused junction at the top of the channel (junction FET or JFET...greater than 100 GHz. YIG-tuned units are finding increasing use as extremely stable sources, whereas varactor tuning is used where tuning speed is

Stability study of solution-processed zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Zhang, Xue; Ndabakuranye, Jean Pierre; Kim, Dong Wook; Choi, Jong Sun; Park, Jaehoon

2015-11-01

In this study, the environmental dependence of the electrical stability of solution-processed n-channel zinc tin oxide (ZTO) thin-film transistors (TFTs) is reported. Under a prolonged negative gate bias stress, a negative shift in threshold voltage occurs in atmospheric air, whereas a negligible positive shift in threshold voltage occurs under vacuum. In the positive bias-stress experiments, a positive shift in threshold voltage was invariably observed both in atmospheric air and under vacuum. In this study, the negative gate-bias-stress-induced instability in atmospheric air is explained through an internal potential in the ZTO semiconductor, which can be generated owing to the interplay between H2O molecules and majority carrier electrons at the surface of the ZTO film. The positive bias-stress-induced instability is ascribed to electron-trapping phenomenon in and around the TFT channel region, which can be further augmented in the presence of air O2 molecules. These results suggest that the interaction between majority carriers and air molecules will have crucial implications for a reliable operation of solution-processed ZTO TFTs. [Figure not available: see fulltext.

Characterizing the structure of topological insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Richardella, Anthony; Kandala, Abhinav; Lee, Joon Sue

2015-08-01

We describe the characterization of structural defects that occur during molecular beam epitaxy of topological insulator thin films on commonly used substrates. Twinned domains are ubiquitous but can be reduced by growth on smooth InP (111)A substrates, depending on details of the oxide desorption. Even with a low density of twins, the lattice mismatch between (Bi, Sb){sub 2}Te{sub 3} and InP can cause tilts in the film with respect to the substrate. We also briefly discuss transport in simultaneously top and back electrically gated devices using SrTiO{sub 3} and the use of capping layers to protect topological insulator films frommore » oxidation and exposure.« less

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Ultra-thin Oxide Membranes: Synthesis and Carrier Transport

NASA Astrophysics Data System (ADS)

Sim, Jai Sung

Self-supported freestanding membranes are films that are devoid of any underlying supporting layers. The key advantage of such structures is that, due to the lack of substrate effects - both mechanical and chemical, the true native properties of the material can be probed. This is crucial since many of the studies done on materials that are used as freestanding membranes are done as films clamped to substrates or in the bulk form. This thesis focuses on the synthesis and fabrication as well as electrical studies of free standing ultrathin < 40nm oxide membranes. It also is one of the first demonstrations for electrically probing nanoscale freestanding oxide membranes. Fabrication of such membranes is non-trivial as oxide materials are often brittle and difficult to handle. Therefore, it requires an understanding of thin plate mechanics coupled with controllable thin film deposition process. Taking things a step further, to electrically probe these membranes required design of complex device architecture and extensive optimization of nano-fabrication processes. The challenges and optimized fabrication method of such membranes are demonstrated. Three materials are probed in this study, VO2, TiO2, and CeO2. VO2 for understanding structural considerations for electronic phase change and nature of ionic liquid gating, TiO2 and CeO2 for understanding surface conduction properties and surface chemistry. The VO2 study shows shift in metal-insulator transition (MIT) temperature arising from stress relaxation and opening of the hysteresis. The ionic liquid gating studies showed reversible modulation of channel resistance and allowed distinguishing bulk process from the surface effects. Comparing the ionic liquid gating experiments to hydrogen doping experiments illustrated that ionic liquid gating can be a surface limited electrostatic effect, if the critical voltage threshold is not exceeded. TiO2 study shows creation of non-stoichiometric forms under ion milling. Utilizing focused ion beam milling, thin membranes of Ti xOy of 100-300 nm thickness have been created. TEM studies indicated polycrystallinity and presence of twins in the FIB-milled nanowalls. Compositional analysis in the transmission electron microscope also showed reduced content of oxygen, confirming non-stoichiometry. Temperature dependence of the electrical resistivity of the nanowall showed semiconducting behavior with an activation energy different from that of TiO2 single crystals and was attributed to formation of TinO2n-1 phases after FIB processing. The CeO2 study involved high temperature conductivity studies on substrate-free self-supported nano-crystalline ceria membranes up to 800 K. Increasing conductivity with oxygen partial pressure directly opposing the behavior of thin film devices 'clamped' by substrate has been observed. This illustrate that the relaxed nature of free standing membranes, and increased surface to volume ratio enables more sensitive electrical response to oxygen adsorption which could have implications for their use in oxygen storage devices, solid oxide fuel cells, and chemical sensors. The work in this thesis advances the understanding of materials in freestanding membrane form and advances fabrication techniques that have not been explored before, having implications for sensors, actuators, SOFC, memristors, and physics of quasi-2D materials.

Restorative effect of oxygen annealing on device performance in HfIZO thin-film transistors

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2015-03-01

Metal-oxide based thin-film transistors (oxide-TFTs) are very promising for use in next generation electronics such as transparent displays requiring high switching and driving performance. In this study, we demonstrate an optimized process to secure excellent device performance with a favorable shift of the threshold voltage toward 0V in amorphous hafnium-indium-zinc-oxide (a-HfIZO) TFTs by using post-treatment with oxygen annealing. This enhancement results from the improved interfacial characteristics between gate dielectric and semiconductor layers due to the reduction in the density of interfacial states related to oxygen vacancies afforded by oxygen annealing. The device statistics confirm the improvement in the device-to-device and run-to-run uniformity. We also report on the photo-induced stability in such oxide-TFTs against long-term UV irradiation, which is significant for transparent displays.

Polydiacetylene as an all-optical picosecond Switch

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin A.; Frazier, D. O.; Paley, M. S.; Whitaker, Ann F. (Technical Monitor)

2001-01-01

Polydiacetylene derivative of 2-methyl-4-nitroaniline (PDAMNA) shows a picosecond switching property, which illustrated a partial all-optical picosecond NAND logic gate. The switching phenomenon was demonstrated by waveguiding two collinear beams at 633 nm and 532 nm through a hollow fiber of 50 micrometers diameter, coated from inside with a thin film of PDAMNA. A Z-scan investigations of a PDAMNA thin film on quartz substrate revealed that the switching effect was attributed to an excited state absorption in the systems. The studies also showed that the polymer suffers a photo-oxidation beyond an intensity level of 2.9 x 10(exp 6) w/square cm. The photo-oxidized film has different physical properties that are different from the original film before oxidation. The life time of both excited states before and after oxidation as well as their absorption coefficients were estimated by fitting a three level system model to the experimental results.

Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

DTIC Science & Technology

1993-04-01

CLASSIFICATION 18. SECURITY CLASSIFICATION 19. SECURIlY CLASSIFICATION 20. UMITATION OF ABSTRACT OF REPORT OF THIS PAGE OF ABSTRACT UNCLASSIFIED UNCLASSIFIED...with the silicon underneath, growing a thin nitride layer. This layer of Si 3 N 4 , if not completely removed, will retard oxidation in the area...C. Shatas, K. C. Saraswat and J. D. Meindl, "Interfacial and Breakdown Characteristics of MOS Devices with Rapidly Grown Ultrathin SiO Gate

Fabrication of one-transistor-capacitor structure of nonvolatile TFT ferroelectric RAM devices using Ba(Zr0.1Ti0.9)O3 gated oxide film.

PubMed

Yang, Cheng-Fu; Chen, Kai-Huang; Chen, Ying-Chung; Chang, Ting-Chang

2007-09-01

In this study, the Ba(Zr0.1Ti0.9)O3 (BZ1T9) thin films have been well deposited on the Pt/Ti/SiO2/Si substrate. The optimum radio frequency (RF) deposition parameters are developed, and the BZ1T9 thin films deposition at the optimum parameters have the maximum capacitance and dielectric constant of 4.4 nF and 190. As the applied voltage is increased to 8 V, the remnant polarization and coercive field of BZ1T9 thin films are about 4.5 microC/cm2 and 80 kV/cm. The counterclockwise current hysteresis and memory window of n-channel thin-film transistor property are observed, and that can be used to indicate the switching of ferroelectric polarization of BZ1T9 thin films. One-transistor-capacitor (1TC) structure of BZ1T9 ferroelectric random access memory device using bottom-gate amorphous silicon thin-film transistor was desirable because of the smaller size and better sensitivity. The BZ1T9 ferroelectric RAM devices with channel width = 40 microm and channel length = 8 microm has been successfully fabricated and the ID-VG transfer characteristics also are investigated in this study.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

NASA Astrophysics Data System (ADS)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p-channel MOSFETs. Band engineering, strain induced valence band splitting and quantum confinement is used to improve channel hole mobility. Experimental results on the Hall hole mobility is presented for InxGa1-xAs channels with varying In content, thickness of the quantum well and temperature. Then, high mobility InxGa 1-xAs heterostructure thus obtained are integrated with in-situ deposited high-k gate oxide required for high performance p-MOSFET and discuss the challenges associated with the gated structure and draw conclusions on this material system. Antimonide based channel materials such as GaSb and InxGa 1-xSb are explored for III-V based p-MOSFETs in last two chapters. Options for Sb based strained QW channels to obtain maximum hole mobility by varying the strain, channel and barrier material, thickness of the layers etc. is discussed followed by the growth of these Sb channels on GaAs and InP substrates using molecular beam epitaxy. The physical properties of the structures such as the heterostructure quality, alloy content and surface roughness are examined via TEM, XRD and AFM. Following this, electrical measurement results on Hall hole mobility is presented. The effect of strain, alloy content, temperature and thickness on channel mobility and concentration is reported. Development of GaSb n- and p-MOS capacitor structures with in-situ deposited HfO2 gate oxide dielectric using in-situ deposited amorphous Si (a-Si) interface passivation layer (IPL) to improve the interface quality of high-k oxide and (In)GaSb surface is presented. In-situ deposited gate oxides such as Al2O3 and combination oxide of Al 2O3 and HfO2 with and without the a-Si IPL are also explored as alternate gate dielectrics. Subsequently, MOS capacitor structures using buried InGaSb QWs are demonstrated. Development of an inversion type bulk GaSb with implanted source-drain contacts and in-situ deposited gate oxide HfO2 gate oxide is discussed. The merits of biaxial compressive strain is demonstrated on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

Zinc Oxide Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fortunato, E.; Barquinha, P.; Pimentel, A.; Gonçalves, A.; Marques, A.; Pereira, L.; Martins, R.

ZnO thin film transistors (ZnO-TFT) have been fabricated by rf magnetron sputtering at room temperature with a bottom-gate configuration. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 21 V, a field effect mobility of 20 cm2/Vs, a gate voltage swing of 1.24 V/decade and an on/off ratio of 2×105. The ZnO-TFT present an average optical transmission (including the glass substrate) of 80 % in the visible part of the spectrum. The combination of transparency, high channel mobility and room temperature processing makes the ZnO-TFT a very promising low cost optoelectronic device for the next generation of invisible and flexible electronics. Moreover, the processing technology used to fabricate this device is relatively simple and it is compatible with inexpensive plastic/flexible substrate technology.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Leakage current conduction and reliability assessment of passivating thin silicon dioxide films on n-4H-SiC

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2016-09-01

We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO2) films grown on (0 0 0 1) silicon (Si) face of n-type 4H-SiC (silicon carbide). It was observed that the experimentally measured gate current density in metal-oxide-silicon carbide (MOSiC) structures under positive gate bias at an oxide field Eox above 5 MV/cm is comprised of Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps in the SiO2 gap, IFN and IPF, respectively at temperatures between 27 and 200 °C. In MOSiC structures, PF mechanism dominates FN tunneling of electrons from the accumulation layer of n-4H-SiC due to high density (up to 1013 cm-2) of carbon-related acceptor-like traps located at about 2.5 eV below the SiO2 conduction band (CB). These current conduction mechanisms were taken into account in studying hole injection/trapping into 10 nm-thick tunnel oxide on the Si face of 4H-SiC during electron injection from n-4H-SiC under high-field electrical stress with positive bias on the heavily doped n-type polysilicon (n+-polySi) gate at a wide range of temperatures between 27 and 200 °C. Holes were generated in the n+-polySi anode material by the hot-electrons during their transport through thin oxide films at oxide electric fields Eox from 5.6 to 8.0 MV/cm (prior to the intrinsic oxide breakdown field). Time-to-breakdown tBD of the gate dielectric was found to follow reciprocal field (1/E) model irrespective of stress temperatures. Despite the significant amount of process-induced interfacial electron traps contributing to a large amount of leakage current via PF emission in thermally grown SiO2 on the Si-face of n-4H-SiC, MOSiC devices having a 10 nm-thick SiO2 film can be safely used in 5 V TTL logic circuits over a period of 10 years.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leng, X.; Pereiro, J.; Strle, J.

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Atomic Layer Deposition of HfO2 and Si Nitride on Ge Substrates

NASA Astrophysics Data System (ADS)

Zhu, Shiyang; Nakajima, Anri

2007-12-01

Hafnium oxide (HfO2) thin films were deposited on Ge substrates at 300 °C using atomic layer deposition (ALD) with tetrakis(diethylamino)hafnium (termed as TDEAH) as a precursor and water as an oxidant. The deposition rate was estimated to be 0.09 nm/cycle and the deposited HfO2 films have a smooth surface and an almost stoichiometric composition, indicating that the growth follows a layer-by-layer kinetics, similarly to that on Si substrates. Si nitride thin films were also deposited on Ge by ALD using SiCl4 as a precursor and NH3 as an oxidant. Si nitride has a smaller deposition rate of about 0.055 nm/cycle and a larger gate leakage current than HfO2 deposited on Ge by ALD.

Low voltage-driven oxide phototransistors with fast recovery, high signal-to-noise ratio, and high responsivity fabricated via a simple defect-generating process

PubMed Central

Yun, Myeong Gu; Kim, Ye Kyun; Ahn, Cheol Hyoun; Cho, Sung Woon; Kang, Won Jun; Cho, Hyung Koun; Kim, Yong-Hoon

2016-01-01

We have demonstrated that photo-thin film transistors (photo-TFTs) fabricated via a simple defect-generating process could achieve fast recovery, a high signal to noise (S/N) ratio, and high sensitivity. The photo-TFTs are inverted-staggered bottom-gate type indium-gallium-zinc-oxide (IGZO) TFTs fabricated using atomic layer deposition (ALD)-derived Al2O3 gate insulators. The surfaces of the Al2O3 gate insulators are damaged by ion bombardment during the deposition of the IGZO channel layers by sputtering and the damage results in the hysteresis behavior of the photo-TFTs. The hysteresis loops broaden as the deposition power density increases. This implies that we can easily control the amount of the interface trap sites and/or trap sites in the gate insulator near the interface. The photo-TFTs with large hysteresis-related defects have high S/N ratio and fast recovery in spite of the low operation voltages including a drain voltage of 1 V, positive gate bias pulse voltage of 3 V, and gate voltage pulse width of 3 V (0 to 3 V). In addition, through the hysteresis-related defect-generating process, we have achieved a high responsivity since the bulk defects that can be photo-excited and eject electrons also increase with increasing deposition power density. PMID:27553518

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Solution-processed high-mobility neodymium-substituted indium oxide thin-film transistors formed by facile patterning based on aqueous precursors

NASA Astrophysics Data System (ADS)

Lin, Zhenguo; Lan, Linfeng; Sun, Sheng; Li, Yuzhi; Song, Wei; Gao, Peixiong; Song, Erlong; Zhang, Peng; Li, Meiling; Wang, Lei; Peng, Junbiao

2017-03-01

Solution-processed neodymium-substituted indium oxide (InNdO) thin-film transistors (TFTs) based on gel-like aqueous precursors were fabricated with a surface-selective deposition technique associated with ultraviolet irradiation. The Nd concentration can be easily tuned by changing the ratio of Nd2O3 to In2O3 precursors. It was found that Nd played roles of suppressing grain growth, suppressing oxygen vacancy formation, and increasing the electrical stability of TFTs. The InNdO TFT with a Nd:In ratio of 0.02:1 exhibited a mobility of as high as 15.6 cm2 V-1 s-1 with improved stability under gate-bias stress.

Low-Voltage InGaZnO Thin Film Transistors with Small Sub-Threshold Swing.

PubMed

Cheng, C H; Chou, K I; Hsu, H H

2015-02-01

We demonstrate a low-voltage driven, indium-gallium-zinc oxide thin-film transistor using high-κ LaAlO3 gate dielectric. A low VT of 0.42 V, very small sub-threshold swing of 68 mV/dec, field-effect mobility of 4.1 cm2/Ns and low operation voltage of 1.4 V were reached simultaneously in LaAlO3/IGZO TFT device. This low-power and small SS TFT has the potential for fast switching speed and low power applications.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Characterization of ultrathin SOI film and application to short channel MOSFETs.

PubMed

Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

2008-04-23

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

High Responsivity MgZnO Ultraviolet Thin-Film Phototransistor Developed Using Radio Frequency Sputtering

PubMed Central

Li, Jyun-Yi; Chang, Sheng-Po; Hsu, Ming-Hung; Chang, Shoou-Jinn

2017-01-01

We investigated the electrical and optoelectronic properties of a magnesium zinc oxide thin-film phototransistor. We fabricate an ultraviolet phototransistor by using a wide-bandgap MgZnO thin film as the active layer material of the thin film transistor (TFT). The fabricated device demonstrated a threshold voltage of 3.1 V, on–off current ratio of 105, subthreshold swing of 0.8 V/decade, and mobility of 5 cm2/V·s in a dark environment. As a UV photodetector, the responsivity of the device was 3.12 A/W, and the rejection ratio was 6.55 × 105 at a gate bias of −5 V under 290 nm illumination. PMID:28772487

High Responsivity MgZnO Ultraviolet Thin-Film Phototransistor Developed Using Radio Frequency Sputtering.

PubMed

Li, Jyun-Yi; Chang, Sheng-Po; Hsu, Ming-Hung; Chang, Shoou-Jinn

2017-02-04

We investigated the electrical and optoelectronic properties of a magnesium zinc oxide thin-film phototransistor. We fabricate an ultraviolet phototransistor by using a wide-bandgap MgZnO thin film as the active layer material of the thin film transistor (TFT). The fabricated device demonstrated a threshold voltage of 3.1 V, on-off current ratio of 10⁵, subthreshold swing of 0.8 V/decade, and mobility of 5 cm²/V·s in a dark environment. As a UV photodetector, the responsivity of the device was 3.12 A/W, and the rejection ratio was 6.55 × 10⁵ at a gate bias of -5 V under 290 nm illumination.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

PubMed

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

NASA Astrophysics Data System (ADS)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-05-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W /L=10μm/50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2/Vs, a subthreshold gate swing value of 0.59V/decade, a thrseshold voltage of 5.9V, and an Ion/off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun

We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al{sub 2}O{sub 3}, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔV{sub th}) was 0 V even after a PBS time (t{sub stress}) of 3000 s under a gate voltage (V{submore » G}) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔV{sub th} value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔV{sub th} values resulting from PBS quantitatively, the average oxide charge trap density (N{sub T}) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N{sub T} resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N{sub T} near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.« less

Electronic Devices Based on Oxide Thin Films Fabricated by Fiber-to-Film Process.

PubMed

Meng, You; Liu, Ao; Guo, Zidong; Liu, Guoxia; Shin, Byoungchul; Noh, Yong-Young; Fortunato, Elvira; Martins, Rodrigo; Shan, Fukai

2018-05-30

Technical development for thin-film fabrication is essential for emerging metal-oxide (MO) electronics. Although impressive progress has been achieved in fabricating MO thin films, the challenges still remain. Here, we report a versatile and general thermal-induced nanomelting technique for fabricating MO thin films from the fiber networks, briefly called fiber-to-film (FTF) process. The high quality of the FTF-processed MO thin films was confirmed by various investigations. The FTF process is generally applicable to numerous technologically relevant MO thin films, including semiconducting thin films (e.g., In 2 O 3 , InZnO, and InZrZnO), conducting thin films (e.g., InSnO), and insulating thin films (e.g., AlO x ). By optimizing the fabrication process, In 2 O 3 /AlO x thin-film transistors (TFTs) were successfully integrated by fully FTF processes. High-performance TFT was achieved with an average mobility of ∼25 cm 2 /(Vs), an on/off current ratio of ∼10 7 , a threshold voltage of ∼1 V, and a device yield of 100%. As a proof of concept, one-transistor-driven pixel circuit was constructed, which exhibited high controllability over the light-emitting diodes. Logic gates based on fully FTF-processed In 2 O 3 /AlO x TFTs were further realized, which exhibited good dynamic logic responses and voltage amplification by a factor of ∼4. The FTF technique presented here offers great potential in large-area and low-cost manufacturing for flexible oxide electronics.

Sputtered Thin Film Research

DTIC Science & Technology

1974-11-01

yield (100) oriented wafers, which were lapped and chemi-mechanically polished in sulf uric-peroxide or sodium hypochlorite etches. Prior to mounting...This material will viot oxidize, melt, or diffuse during the subsequent high temperature processing. Platinum silicide contacts are used because...formation of the platinum silicide contacts, the gate region was opened and the wafer was placed in the sput- tering chamber. The same deposition

Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang

We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{submore » O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.« less

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Correlation of film morphology and defect content with the charge-carrier transport in thin-film transistors based on ZnO nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Polster, S.; Jank, M. P. M.; Frey, L.

2016-01-14

The correlation of defect content and film morphology with the charge-carrier transport in field-effect devices based on zinc oxide nanoparticles was investigated. Changes in the defect content and the morphology were realized by annealing and sintering of the nanoparticle thin films. Temperature-dependent electrical measurements reveal that the carrier transport is thermally activated for both the unsintered and sintered thin films. Reduced energetic barrier heights between the particles have been determined after sintering. Additionally, the energetic barrier heights between the particles can be reduced by increasing the drain-to-source voltage and the gate-to-source voltage. The changes in the barrier height are discussedmore » with respect to information obtained by scanning electron microscopy and photoluminescence measurements. It is found that a reduction of surface states and a lower roughness at the interface between the particle layer and the gate dielectric lead to lower barrier heights. Both surface termination and layer morphology at the interface affect the barrier height and thus are the main criteria for mobility improvement and device optimization.« less

Operational stability of solution-processed indium-oxide thin-film transistors: Environmental condition and electrical stress

NASA Astrophysics Data System (ADS)

Baang, Sungkeun; Lee, Hyeonju; Zhang, Xue; Park, Jaehoon; Kim, Won-Pyo; Ko, Young-Woong; Piao, Shang Hao; Choi, Hyoung Jin; Kwon, Jin-Hyuk; Bae, Jin-Hyuk

2018-01-01

We investigate the operational stability of bottom-gate/top-contact-structured indium-oxide (In2O3) thin-film transistors (TFTs) in atmospheric air and under vacuum. Based on the thermogravimetric analysis of the In2O3 precursor solution, we utilize a thermal annealing process at 400 °C for 40 min to prepare the In2O3 films. The results of X-ray photoemission spectroscopy and field-emission scanning electron microscopy show that the electron is the majority carrier in the In2O3 semiconductor film prepared by a spin-coating method and that the film has a polycrystalline morphology with grain boundaries. The fabricated In2O3 TFTs operate in an n-type enhancement mode. When constant drain and gate voltages are applied, these TFTs in atmospheric air exhibit a more acute decay in the drain currents with time compared to that observed under vacuum. In the positive gate-bias stress experiments, a decrease in the field-effect mobility and a positive shift in the threshold voltage are invariably observed both in atmospheric air and under vacuum, but such characteristic variations are also found to be more pronounced for the atmospheric-air case. These results are explained in terms of the electron-trapping phenomenon at the grain boundaries in the In2O3 semiconductor, as well as the electrostatic interactions between electrons and polar water molecules.

PREFACE: Proceedings Symposium G of E-MRS Spring Meeting on Fundamentals and Technology of Multifunctional Oxide Thin Films

NASA Astrophysics Data System (ADS)

2010-07-01

Oxide materials exhibit a large variety of functional properties that are useful in a plethora of applications. Symposium G focused on oxide thin films that include dielectric or switching properties. Its program mirrored very well the strong worldwide search for high-K thin films for gate, memory, and on-chip capacitors, as well as the emerging field of functional thin films for MEMS. A complete session was devoted to the colossal effect of dielectric response in (Ca,Cu)TiO3, representing the major European research groups in this field. A comprehensive overview on this phenomenon was given by D Sinclair J Wolfman presented the latest results on CCTO thin films obtained by wafer scale pulsed laser deposition. A Loidl showed the analytical power of dielectric spectroscopy when covering the complete frequency range from 1-1012 Hz, i.e. from space charge to phonon contributions at the example of CCTO. Another session was devoted to applications in non-volatile memories, covering various effects including ferroelectric and resistive switching, the complex behavior of oxide tunnel junctions (H Kohlstedt), the possibility to manipulate the magnetic state of a 2d-electron gas by the polarization of an adjacent ferroelectric gate (I Stolitchnov). Latest advancements in ALD processing for high-K thin films in dynamic RAM were reported by S Ramanathan. The advancement of piezoelectric PZT thin film MEMS devices was well documented by outstanding talks on their developments in industry (M Klee, F Tyholdt), new possibilities in GHz filters (T Matshushima), advancements in sol-gel processing (B Tuttle, H Suzuki), and low temperature integration approaches by UV light curing (S Trolier-McKinstry). Recent advances in incipient ferroelectric thin films and nano composites for tunable capacitors in microwave applications were present by A Vorobiev and T Yamada. Integrated electro-optics is another field to be conquered by thin film structures. The impressive progress made in this field was highlighted by P Günter. Many contributions were devoted to processing techniques, showing the increasing importance of CVD techniques to deposit for instance perovskite thin films (G Malandrino). Nevertheless, stunning results were obtained by a sophisticated MBE tool allowing for precise compositional control of individual oxide monolayers and thus enabling High-Tc supraconductivity in individual monolayers to be addressed (I Bosovic). Oxides do not only gleam with giant dielectric properties, giant electronic conduction (superconductivity), there is also a giant electro-caloric effect, as explained by Z Kutnjak. The symposium could take advantage of the EU projects NUOTO and CAMELIA that organized a joint session on giant K dielectrics to present their project results to the scientific and industrial community. The symposium organizers Paul Muralt, EPFL, Lausanne, Switzerland Marija Kosec, Josef Stefan Institute, Ljubljana, Slovenia Vito Raineri, IMM-CNR, Catania, Italy Sebastiano Ravesi, STMicroelectronics, Catania, Italy Scientific Committee Robert Blinc (Josef Stefan Inst., Slovenia) Wolfgang Kleemann (Univ. Duisburg, Germany) Raffaella Lo Nigro (IMM-CNR, Italy) Ian M Reaney (Univ. Sheffield, Great Britain) T Metzger (EPCOS, Germany) Rainer Waser (TH Aachen, Germany)

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Producing CCD imaging sensor with flashed backside metal film

NASA Technical Reports Server (NTRS)

Janesick, James R. (Inventor)

1988-01-01

A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning. This metal film (flash gate), which improves and stabilizes the quantum efficiency of a CCD imaging sensor, will also improve the QE of any p-n junction photodetector.

CCD imaging sensor with flashed backside metal film

NASA Technical Reports Server (NTRS)

Janesick, James R. (Inventor)

1991-01-01

A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning. This metal film (flash gate), which improves and stabilizes the quantum efficiency of a CCD imaging sensor, will also improve the QE of any p-n junction photodetector.

Fabrication and Characterization of Fully Transparent ZnO Thin-Film Transistors and Self-Switching Nano-Diodes

NASA Astrophysics Data System (ADS)

Sun, Y.; Ashida, K.; Sasaki, S.; Koyama, M.; Maemoto, T.; Sasa, S.; Kasai, S.; Iñiguez-de-la-Torre, I.; González, T.

2015-10-01

Fully transparent zinc oxide (ZnO) based thin-film transistors (TFTs) and a new type of rectifiers calls self-switching nano-diodes (SSDs) were fabricated on glass substrates at room temperature by using low resistivity and transparent conducting Al- doped ZnO (AZO) thin-films. The deposition conditions of AZO thin-films were optimized with pulsed laser deposition (PLD). AZO thin-films on glass substrates were characterized and the transparency of 80% and resistivity with 1.6*10-3 Ωcm were obtained of 50 nm thickness. Transparent ZnO-TFTs were fabricated on glass substrates by using AZO thin-films as electrodes. A ZnO-TFT with 2 μm long gate device exhibits a transconductance of 400 μS/mm and an ON/OFF ratio of 2.8*107. Transparent ZnO-SSDs were also fabricated by using ZnO based materials and clear diode-like characteristics were observed.

Summary and Evaluation of NRC-Sponsored Stellite 6 Aging and Friction Tests

DOE Office of Scientific and Technical Information (OSTI.GOV)

J. C. Watkins; K. G. DeWall; D. Bramwell

1999-04-01

This report describes four sets of tests sponsored by the U.S. Nuclear Regulatory Commission and conducted by the Idaho National Engineering and Environmental Laboratory. The tests support research addressing the need to provide assurance that motor-operated valves are able to perform their intended safety function, usually to open or close against specified (design basis) flow and pressure loads. One of the parameters that affects a gate valve's operability is the friction between the disc seats and the valve body seats. In most gate valves, these surfaces are hardfaced with Stellite 6, a cobalt-based alloy. The tests described in this reportmore » investigate the changes that occur in the friction as the Stellite 6 surfaces develop an oxide film as they age. Stellite 6 specimens were aged in a corrosion autoclave, the oxide films were examined and characterized, and the specimens were subjected to friction testing in a friction autoclave. A very thin oxide film formed after only a fe w days of natural aging. Even a very thin oxide film caused an increase in friction. The surface structure of the oxide film was dominated by a hard crystalline structure, such that the friction response was analogous to rubbing two pieces of sandpaper together. In the limited data provided by naturally aged specimens (78 days maximum exposure, very thin oxide films), the friction increased with greater aging time, approaching an as-yet-undetermined plateau. Although the thickness of the oxide film increased with greater aging time, the mechanical properties of the oxide film (larger granules with greater aging time) appeared to play a greater role in the friction response. Friction testing of specimens subjected to simulated in-service testing strokes at intervals during the aging process showed only a slight decrease in friction, compared to other specimens. Results from specimens subjected to accelerated aging were inconclusive, because of differences in the structure and comp osition of the oxide films, compared to naturally aged specimens. For the naturally aged specimens, the highest friction occurred on the first stroke. The first stroke smeared the oxide film and dislodged some of the granules, so that subsequent strokes saw lower friction values and less variation in the friction. This result underscores the importance of planning in-plant tests so that data are collected from the first stroke following a period of inactivity.« less

Low-cost label-free electrical detection of artificial DNA nanostructures using solution-processed oxide thin-film transistors.

PubMed

Kim, Si Joon; Jung, Joohye; Lee, Keun Woo; Yoon, Doo Hyun; Jung, Tae Soo; Dugasani, Sreekantha Reddy; Park, Sung Ha; Kim, Hyun Jae

2013-11-13

A high-sensitivity, label-free method for detecting deoxyribonucleic acid (DNA) using solution-processed oxide thin-film transistors (TFTs) was developed. Double-crossover (DX) DNA nanostructures with different concentrations of divalent Cu ion (Cu(2+)) were immobilized on an In-Ga-Zn-O (IGZO) back-channel surface, which changed the electrical performance of the IGZO TFTs. The detection mechanism of the IGZO TFT-based DNA biosensor is attributed to electron trapping and electrostatic interactions caused by negatively charged phosphate groups on the DNA backbone. Furthermore, Cu(2+) in DX DNA nanostructures generates a current path when a gate bias is applied. The direct effect on the electrical response implies that solution-processed IGZO TFTs could be used to realize low-cost and high-sensitivity DNA biosensors.

Using KrF ELA to Improve Gate-Stacked LaAlO₃/ZrO₂ Indium Gallium Zinc Oxide Thin-Film Transistors with Novel Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition Technique.

PubMed

Wu, Chien-Hung; Chang, Kow-Ming; Chen, Yi-Ming; Huang, Bo-Wen; Zhang, Yu-Xin; Wang, Shui-Jinn

2018-03-01

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique and KrF excimer laser annealing (ELA) were employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO-TFTs). Device with a 150 mJ/cm2 laser annealing densities demonstrated excellent electrical characteristics with improved on/off current ratio of 4.7×107, high channel mobility of 10 cm2/V-s, and low subthreshold swing of 0.15 V/dec. The improvements are attributed to the adjustment of oxygen vacancies in the IGZO channel to an appropriate range of around 28.3% and the reduction of traps at the high-k/IGZO interface.

The Electrochemical Behavior of Mo-Ta Alloy in Phosphoric Acid Solution for TFT-LCD Application.

PubMed

Lee, Sang-Hyuk; Kim, Byoung O; Seo, Jong Hyun

2015-10-01

Molybdenum-tantalum alloy thin film is a suitable material for the higher corrosion resistance and low resistivity for gate and data metal lines. In this study, Mo-Ta alloy thin films were prepared by using a DC magnetron co-sputtering system on a glass substrate. An abrupt increase in the etching rates of low Mo-Ta alloys was observed. From the observed impedance analysis, the defect densities in the MoTa oxide films increased from 5.4 x 10(21) (cm(-3)) to 8.02 x 10(21) (cm(-3)) up to the 6 at% of tantalum level; and above the 6 at% of tantalum level, the defect densities decreased. This electrochemical behavior is explained by the mechanical instability of the MoTa oxide film.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

NASA Astrophysics Data System (ADS)

Ye, Fan; Xiaorong, Luo; Kun, Zhou; Yuanhang, Fan; Yongheng, Jiang; Qi, Wang; Pei, Wang; Yinchun, Luo; Bo, Zhang

2014-03-01

A low specific on-resistance (Ron,sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron,sp. Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron,sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron,sp by 80% at the same BV.

Comparison of the agglomeration behavior of thin metallic films on SiO2

NASA Astrophysics Data System (ADS)

Gadkari, P. R.; Warren, A. P.; Todi, R. M.; Petrova, R. V.; Coffey, K. R.

2005-07-01

The stability of continuous metallic thin films on insulating oxide surfaces is of interest to applications such as semiconductor interconnections and gate engineering. In this work, we report the study of the formation of voids and agglomeration of initially continuous Cu, Au, Ru and Pt thin films deposited on amorphous thermally grown SiO2 surfaces. Polycrystalline thin films having thicknesses in the range of 10-100 nm were ultrahigh vacuum sputter deposited on thermally grown SiO2 surfaces. The films were annealed at temperatures in the range of 150-800 °C in argon and argon+3% hydrogen gases. Scanning electron microscopy was used to investigate the agglomeration behavior, and transmission electron microscopy was used to characterize the microstructure of the as-deposited and annealed films. The agglomeration sequence in all of the films is found to follow a two step process of void nucleation and void growth. However, void growth in Au and Pt thin films is different from Cu and Ru thin films. Residual stress and adhesion were observed to play an important part in deciding the mode of void growth in Au and Pt thin films. Last, it is also observed that the tendency for agglomeration can be reduced by encapsulating the metal film with an oxide overlayer.

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Priyanka; Sahu, P. K.

2016-01-01

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

PubMed Central

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-01-01

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials. PMID:28772579

Characterisation of Nd2O3 thick gate dielectric for silicon

NASA Astrophysics Data System (ADS)

Dakhel, A. A.

2004-03-01

Thin neodymium films were prepared by the reactive synthesis method on Si (P) substrates to form MOS devices. The oxide films were characterised by UV absorption spectroscopy, X-ray fluorescence (EDXRF) and X-ray diffraction (XRD). The ac conductance and capacitance of the devices were studied as a function of frequency in the range 100 Hz-100 kHz, of temperature in the range 293-473 K and of gate voltage. It was proved that a suitable formalism to explain the frequency dependence of the ac conductivity and capacitance of the insulator is controlled by a universal power law based on the relaxation processes of the hopping or tunnelling of the current carriers between equilibrium sites. The temperature dependence of the ac conductance at the accumulation state shows a small activation energy of about 0.07 eV for a MOS device with amorphous neodymium oxide. The temperature dependence of the accumulation capacitance for a MOS structure with crystalline neodymium oxide shows a maximum at about 390 K; such a maximum was not observed for the structure with amorphous neodymium oxide. The method of capacitance-gate voltage (C-Vg) measurements was used to investigate the effect of annealing in air and in vacuum on the surface density of states (Nss) at the insulator/semiconductor (I/S) interface. It was concluded that the density of surface states in the mid-gap increases by about five times while the density of the trapped charges in the oxide layer decreases by about eight times when the oxide crystallises into a polycrystalline structure.

Analysis of indium zinc oxide thin films by laser-induced breakdown spectroscopy

NASA Astrophysics Data System (ADS)

Popescu, A. C.; Beldjilali, S.; Socol, G.; Craciun, V.; Mihailescu, I. N.; Hermann, J.

2011-10-01

We have performed spectroscopic analysis of the plasma generated by Nd:YAG (λ = 266 nm) laser irradiation of thin indium zinc oxide films with variable In content deposited by combinatorial pulsed laser deposition on glass substrates. The samples were irradiated in 5 × 104 Pa argon using laser pulses of 5 ns duration and 10 mJ energy. The plasma emission spectra were recorded with an Echelle spectrometer coupled to a gated detector with different delays with respect to the laser pulse. The relative concentrations of indium and zinc were evaluated by comparing the measured spectra to the spectral radiance computed for a plasma in local thermal equilibrium. Plasma temperature and electron density were deduced from the relative intensities and Stark broadening of spectral lines of atomic zinc. Analyses at different locations on the deposited thin films revealed that the In/(In + Zn) concentration ratio significantly varies over the sample surface, from 0.4 at the borders to about 0.5 in the center of the film. The results demonstrate that laser-induced breakdown spectroscopy allows for precise and fast characterization of thin films with variable composition.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

NASA Astrophysics Data System (ADS)

Carl, D. A.; Hess, D. W.; Lieberman, M. A.; Nguyen, T. D.; Gronsky, R.

1991-09-01

Thin (3-300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O-, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5-60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K. High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4-30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm-2) and interface traps (≳1012 cm-2 eV-1). The fixed charge level could be reduced to ≊4×1010 cm-2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1-2)×1011 cm-2 eV-1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm-1. Electrical properties of the 5.4-8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.

STIR: Novel Electronic States by Gating Strongly Correlated Materials

DTIC Science & Technology

2016-03-01

plan built on my group’s recent demonstration of electrolyte gating in Strontium Titanate, using an atomically thin hexagonal Boron Nitride barrier to...demonstration of electrolyte gating in Strontium Titanate, using an atomically thin hexagonal Boron Nitride barrier to prevent disorder and chemical...techniques and learned to apply thin hexagonal Boron Nitride to single crystals of materials expected to show some of the most exciting correlated

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo

2016-03-01

In order to improve the reliability of TFT, an Al2O3 insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al2O3 layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V o2+ toward the interface between the gate insulator and the semiconductor. The inserted Al2O3 triple layer exhibits a noticeably low turn on voltage shift of -0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm2/V ṡ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.

Scanning probes for lithography: Manipulation and devices

NASA Astrophysics Data System (ADS)

Rolandi, Marco

2005-11-01

Scanning probes are relatively low cost equipment that can push the limit of lithography in the nanometer range, with the advantages of high resolution, accuracy in the positioning of the overlayers and no proximity aberrations. We have developed three novel scanning probe lithography (SPL) resists based on thin films of Titanium, Molybdenum and Tungsten and we have manipulated single walled carbon nanotubes using the sharp tip of an atomic force microscope (AFM) for the fabrication of nanostructures. A dendrimer-passivated Ti film was imaged in the positive and the negative tone using SPL. This is the first example of SPL imaging in both tones using a unique resist. Positive tone patterning was obtained by locally scribing the dendrimer molecules and subsequent acid etch of the deprotected Ti film. Local anodic oxidation transforms Ti into TiO2 and deposits a thin layer of amorphous carbon on the patterned areas. This is very resistive to base etch and affords negative tone imaging of the Ti surface. Molybdenum and Tungsten were patterned using local anodic oxidation. This scheme is particularly flexible thanks to the solubility in water of the fully oxidized states of the two metals. We will present the facile fabrication of several nanostructures such as of trenches, dots wires and nanoelectrodes and show the potential of this scheme for competing with conventional lithographic techniques based on radiation. Quasi one dimensional electrodes for molecular electronics applications were also fabricated by creating nanogaps in single walled carbon nanotubes. The tubes, connected to microscopic contacts, were controllably cut via local anodic oxidation using the tip of the AFM. This technique leads to nanoscopic carboxyl terminated wires to which organic molecules can be linked using covalent chemistry. This geometry is particularly useful for the high gate efficiency without the need of a thin gate dielectric and the stability of the junction. Room temperature and low temperature measurements were performed and show single electron transistor behavior for the molecular junction.

Extended-gate-type IGZO electric-double-layer TFT immunosensor with high sensitivity and low operation voltage

NASA Astrophysics Data System (ADS)

Liang, Lingyan; Zhang, Shengnan; Wu, Weihua; Zhu, Liqiang; Xiao, Hui; Liu, Yanghui; Zhang, Hongliang; Javaid, Kashif; Cao, Hongtao

2016-10-01

An immunosensor is proposed based on the indium-gallium-zinc-oxide (IGZO) electric-double-layer thin-film transistor (EDL TFT) with a separating extended gate. The IGZO EDL TFT has a field-effect mobility of 24.5 cm2 V-1 s-1 and an operation voltage less than 1.5 V. The sensors exhibit the linear current response to label-free target immune molecule in the concentrations ranging from 1.6 to 368 × 10-15 g/ml with a detection limit of 1.6 × 10-15 g/ml (0.01 fM) under an ultralow operation voltage of 0.5 V. The IGZO TFT component demonstrates a consecutive assay stability and recyclability due to the unique structure with the separating extended gate. With the excellent electrical properties and the potential for plug-in-card-type multifunctional sensing, extended-gate-type IGZO EDL TFTs can be promising candidates for the development of a label-free biosensor for public health applications.

Experimental investigation on On-Off current ratio behavior near onset voltage for a pentacene based organic thin film transistor

NASA Astrophysics Data System (ADS)

Amrani, Aumeur El; Es-saghiri, Abdeljabbar; Boufounas, El-Mahjoub; Lucas, Bruno

2018-06-01

The performance of a pentacene based organic thin film transistor (OTFT) with polymethylmethacrylate as a dielectric insulator and indium tin oxide based electrical gate is investigated. On the one hand, we showed that the threshold voltage increases with gate voltage, and on the other hand that it decreases with drain voltage. Thus, we noticed that the onset voltage shifts toward positive voltage values with the drain voltage increase. In addition, threshold-onset differential voltage (TODV) is proposed as an original approach to estimate an averaged carrier density in pentacene. Indeed, a value of about 4.5 × 1016 cm-3 is reached at relatively high gate voltage of -50 V; this value is in good agreement with that reported in literature with other technique measurements. However, at a low applied gate voltage, the averaged pentacene carrier density remains two orders of magnitude lower; it is of about 2.8 × 1014 cm-3 and remains similar to that obtained from space charge limited current approach for low applied bias voltage of about 2.2 × 1014 cm-3. Furthermore, high IOn/IOff and IOn/IOnset current ratios of 5 × 106 and 7.5 × 107 are reported for lower drain voltage, respectively. The investigated OTFTs also showed good electrical performance including carrier mobility increasing with gate voltage; mobility values of 4.5 × 10-2 cm2 V-1 s-1 and of 4.25 × 10-2 cm2 V-1 s-1 are reached for linear and saturation regimes, respectively. These results remain enough interesting since current modulation ratio exceeds a value of 107 that is a quite important requirement than high mobility for some particular logic gate applications.

Effect of organic buffer layer in the electrical properties of amorphous-indium gallium zinc oxide thin film transistor.

PubMed

Wang, Jian-Xun; Hyung, Gun Woo; Li, Zhao-Hui; Son, Sung-Yong; Kwon, Sang Jik; Kim, Young Kwan; Cho, Eou Sik

2012-07-01

In this research, we reported on the fabrication of top-contact amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with an organic buffer layer between inorganic gate dielectric and active layer in order to improve the electrical properties of devices. By inserting an organic buffer layer, it was possible to make an affirmation of the improvements in the electrical characteristics of a-IGZO TFTs such as subthreshold slope (SS), on/off current ratio (I(ON/OFF)), off-state current, and saturation field-effect mobility (muFE). The a-IGZO TFTs with the cross-linked polyvinyl alcohol (c-PVA) buffer layer exhibited the pronounced improvements of the muFE (17.4 cm2/Vs), SS (0.9 V/decade), and I(ON/OFF) (8.9 x 10(6)).

Effects of structure and oxygen flow rate on the photo-response of amorphous IGZO-based photodetector devices

NASA Astrophysics Data System (ADS)

Jang, Jun Tae; Ko, Daehyun; Choi, Sungju; Kang, Hara; Kim, Jae-Young; Yu, Hye Ri; Ahn, Geumho; Jung, Haesun; Rhee, Jihyun; Lee, Heesung; Choi, Sung-Jin; Kim, Dong Myong; Kim, Dae Hwan

2018-02-01

In this study, we investigated how the structure and oxygen flow rate (OFR) during the sputter-deposition affects the photo-responses of amorphous indium-gallium-zinc-oxide (a-IGZO)-based photodetector devices. As the result of comparing three types of device structures with one another, which are a global Schottky diode, local Schottky diode, and thin-film transistor (TFT), the IGZO TFT with the gate pulse technique suppressing the persistent photoconductivity (PPC) is the most promising photodetector in terms of a high photo-sensitivity and uniform sensing characteristic. In order to analyze the IGZO TFT-based photodetectors more quantitatively, the time-evolution of sub-gap density-of-states (DOS) was directly observed under photo-illumination and consecutively during the PPC-compensating period with applying the gate pulse. It shows that the increased ionized oxygen vacancy (VO2+) defects under photo-illumination was fully recovered by the positive gate pulse and even overcompensated by additional electron trapping. Based on experimentally extracted sub-gap DOS, the origin on PPC was successfully decomposed into the hole trapping and the VO ionization. Although the VO ionization is enhanced in lower OFR (O-poor) device, the PPC becomes more severe in high OFR (O-rich) device because the hole trapping dominates the PPC in IGZO TFT under photo-illumination rather than the VO ionization and more abundant holes are trapped into gate insulator and/or interface in O-rich TFTs. Similarly, the electron trapping during the PPC-compensating period with applying the positive gate pulse becomes more prominent in O-rich TFTs. It is attributed to more hole/electron traps in the gate insulator and/or interface, which is associated with oxygen interstitials, or originates from the ion bombardment-related lower quality gate oxide in O-rich devices.

Self-aligned top-gate amorphous indium zinc oxide thin-film transistors exceeding low-temperature poly-Si transistor performance.

PubMed

Park, Jae Chul; Lee, Ho-Nyeon; Im, Seongil

2013-08-14

Thin-film transistor (TFT) is a key component of active-matrix flat-panel displays (AMFPDs). These days, the low-temperature poly silicon (LTPS) TFTs are to match with advanced AMFPDs such as the active matrix organic light-emitting diode (AMOLED) display, because of their high mobility for fast pixel switching. However, the manufacturing process of LTPS TFT is quite complicated, costly, and scale-limited. Amorphous oxide semiconductor (AOS) TFT technology is another candidate, which is as simple as that of conventioanl amorphous (a)-Si TFTs in fabrication but provides much superior device performances to those of a-Si TFTs. Hence, various AOSs have been compared with LTPS for active channel layer of the advanced TFTs, but have always been found to be relatively inferior to LTPS. In the present work, we clear the persistent inferiority, innovating the device performaces of a-IZO TFT by adopting a self-aligned coplanar top-gate structure and modifying the surface of a-IZO material. Herein, we demonstrate a high-performance simple-processed a-IZO TFT with mobility of ∼157 cm(2) V(-1) s(-1), SS of ∼190 mV dec(-1), and good bias/photostabilities, which overall surpass the performances of high-cost LTPS TFTs.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Biegel, Bryan A. (Technical Monitor)

2002-01-01

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

PubMed Central

Oh, Young Jun; Noh, Hyeon-Kyun; Chang, Kee Joo

2015-01-01

Oxygen vacancies have been considered as the origin of threshold voltage instability under negative bias illumination stress in amorphous oxide thin film transistors. Here we report the results of first-principles molecular dynamics simulations for the drift motion of oxygen vacancies. We show that oxygen vacancies, which are initially ionized by trapping photoexcited hole carriers, can easily migrate under an external electric field. Thus, accumulated hole traps near the channel/dielectric interface cause negative shift of the threshold voltage, supporting the oxygen vacancy model. In addition, we find that ionized oxygen vacancies easily recover their neutral defect configurations by capturing electrons when the Fermi level increases. Our results are in good agreement with the experimental observation that applying a positive gate bias pulse of short duration eliminates hole traps and thus leads to the recovery of device stability from persistent photoconductivity. PMID:27877799

Suspended sub-50 nm vanadium dioxide membrane transistors: fabrication and ionic liquid gating studies

NASA Astrophysics Data System (ADS)

Sim, Jai S.; Zhou, You; Ramanathan, Shriram

2012-10-01

We demonstrate a robust lithographic patterning method to fabricate self-supported sub-50 nm VO2 membranes that undergo a phase transition. Utilizing such self-supported membranes, we directly observed a shift in the metal-insulator transition temperature arising from stress relaxation and consistent opening of the hysteresis. Electric double layer transistors were then fabricated with the membranes and compared to thin film devices. The ionic liquid allowed reversible modulation of channel resistance and distinguishing bulk processes from the surface effects. From the shift in the metal-insulator transition temperature, the carrier density doped through electrolyte gating is estimated to be 1 × 1020 cm-3. Hydrogen annealing studies showed little difference in resistivity between the film and the membrane indicating rapid diffusion of hydrogen in the vanadium oxide rutile lattice consistent with previous observations. The ability to fabricate electrically-wired, suspended VO2 ultra-thin membranes creates new opportunities to study mesoscopic size effects on phase transitions and may also be of interest in sensor devices.

Directed-Assembly of Carbon Nanotubes on Soft Substrates for Flexible Biosensor Array

NASA Astrophysics Data System (ADS)

Lee, Hyoung Woo; Koh, Juntae; Lee, Byung Yang; Kim, Tae Hyun; Lee, Joohyung; Hong, Seunghun; Yi, Mihye; Jhon, Young Min

2009-03-01

We developed a method to selectively assemble and align carbon nanotubes (CNTs) on soft substrates for flexible biosensors. In this strategy, thin oxide layer was deposited on soft substrates via low temperature plasma enhanced chemical vapor deposition, and linker-free assembly process was applied onto the oxide surface where the assembly of carbon nanotubes was guided by methyl-terminated molecular patterns on the oxide surface. The electrical characterization of the fabricated CNT devices exhibited typical p-type gating effect and 1/f noise behavior. The bare oxide regions near CNTs were functionalized with glutamate oxidase to fabricate selective biosensors to detect two forms of glutamate substances existing in different situations: L-glutamic acid, a neuro-transmitting material, and monosodium glutamate, a food additive.

High-performance single-crystalline arsenic-doped indium oxide nanowires for transparent thin-film transistors and active matrix organic light-emitting diode displays.

PubMed

Chen, Po-Chiang; Shen, Guozhen; Chen, Haitian; Ha, Young-geun; Wu, Chao; Sukcharoenchoke, Saowalak; Fu, Yue; Liu, Jun; Facchetti, Antonio; Marks, Tobin J; Thompson, Mark E; Zhou, Chongwu

2009-11-24

We report high-performance arsenic (As)-doped indium oxide (In(2)O(3)) nanowires for transparent electronics, including their implementation in transparent thin-film transistors (TTFTs) and transparent active-matrix organic light-emitting diode (AMOLED) displays. The As-doped In(2)O(3) nanowires were synthesized using a laser ablation process and then fabricated into TTFTs with indium-tin oxide (ITO) as the source, drain, and gate electrodes. The nanowire TTFTs on glass substrates exhibit very high device mobilities (approximately 1490 cm(2) V(-1) s(-1)), current on/off ratios (5.7 x 10(6)), steep subthreshold slopes (88 mV/dec), and a saturation current of 60 microA for a single nanowire. By using a self-assembled nanodielectric (SAND) as the gate dielectric, the device mobilities and saturation current can be further improved up to 2560 cm(2) V(-1) s(-1) and 160 microA, respectively. All devices exhibit good optical transparency (approximately 81% on average) in the visible spectral range. In addition, the nanowire TTFTs were utilized to control green OLEDs with varied intensities. Furthermore, a fully integrated seven-segment AMOLED display was fabricated with a good transparency of 40% and with each pixel controlled by two nanowire transistors. This work demonstrates that the performance enhancement possible by combining nanowire doping and self-assembled nanodielectrics enables silicon-free electronic circuitry for low power consumption, optically transparent, high-frequency devices assembled near room temperature.

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

NASA Astrophysics Data System (ADS)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Transfer printing of thermoreversible ion gels for flexible electronics.

PubMed

Lee, Keun Hyung; Zhang, Sipei; Gu, Yuanyan; Lodge, Timothy P; Frisbie, C Daniel

2013-10-09

Thermally assisted transfer printing was employed to pattern thin films of high capacitance ion gels on polyimide, poly(ethylene terephthalate), and SiO2 substrates. The ion gels consisted of 20 wt % block copolymer poly(styrene-b-ethylene oxide-b-styrene and 80 wt % ionic liquid 1-ethyl-3-methylimidazolium bis(trifluoromethyl sulfonyl)amide. Patterning resolution was on the order of 10 μm. Importantly, ion gels containing the block polymer with short PS end blocks (3.4 kg/mol) could be transfer-printed because of thermoreversible gelation that enabled intimate gel-substrate contact at 100 °C, while gels with long PS blocks (11 kg/mol) were not printable at the same temperature due to poor wetting contact between the gel and substrates. By using printed ion gels as high-capacitance gate insulators, electrolyte-gated thin-film transistors were fabricated that operated at low voltages (<1 V) with high on/off current ratios (∼10(5)). Statistical analysis of carrier mobility, turn-on voltage, and on/off ratio for an array of printed transistors demonstrated the excellent reproducibility of the printing technique. The results show that transfer printing is an attractive route to pattern high-capacitance ion gels for flexible thin-film devices.

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Highly stable field emission from ZnO nanowire field emitters controlled by an amorphous indium–gallium–zinc-oxide thin film transistor

NASA Astrophysics Data System (ADS)

Li, Xiaojie; Wang, Ying; Zhang, Zhipeng; Ou, Hai; She, Juncong; Deng, Shaozhi; Xu, Ningsheng; Chen, Jun

2018-04-01

Lowering the driving voltage and improving the stability of nanowire field emitters are essential for them to be applied in devices. In this study the characteristics of zinc oxide (ZnO) nanowire field emitter arrays (FEAs) controlled by an amorphous indium–gallium–zinc-oxide thin film transistor (a-IGZO TFT) were studied. A low driving voltage along with stabilization of the field emission current were achieved. Modulation of field emission currents up to three orders of magnitude was achieved at a gate voltage of 0–32 V for a constant anode voltage. Additionally, a-IGZO TFT control can dramatically reduce the emission current fluctuation (i.e., from 46.11 to 1.79% at an emission current of ∼3.7 µA). Both the a-IGZO TFT and ZnO nanowire FEAs were prepared on glass substrates in our research, demonstrating the feasibility of realizing large area a-IGZO TFT-controlled ZnO nanowire FEAs.

Thin-Film Transistors Fabricated Using Sputter Deposition of Zinc Oxide

NASA Astrophysics Data System (ADS)

Xiao, Nan

2013-01-01

Development of thin film transistors (TFTs) with conventional channel layer materials, such as amorphous silicon (a-Si) and polysilicon (poly-Si), has been extensively investigated. A-Si TFT currently serves the large flat panel industry; however advanced display products are demanding better TFT performance because of the associated low electron mobility of a-Si. This has motivated interest in semiconducting metal oxides, such as Zinc Oxide (ZnO), for TFT backplanes. This work involves the fabrication and characterization of TFTs using ZnO deposited by sputtering. An overview of the process details and results from recently fabricated TFTs following a full-factorial designed experiment will be presented. Material characterization and analysis of electrical results will be described. The investigated process variables were the gate dielectric and ZnO sputtering process parameters including power density and oxygen partial pressure. Electrical results showed clear differences in treatment combinations, with certain I-V characteristics demonstrating superior performance to preliminary work. A study of device stability will also be discussed.

3.4-Inch Quarter High Definition Flexible Active Matrix Organic Light Emitting Display with Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Hatano, Kaoru; Chida, Akihiro; Okano, Tatsuya; Sugisawa, Nozomu; Inoue, Tatsunori; Seo, Satoshi; Suzuki, Kunihiko; Oikawa, Yoshiaki; Miyake, Hiroyuki; Koyama, Jun; Yamazaki, Shunpei; Eguchi, Shingo; Katayama, Masahiro; Sakakura, Masayuki

2011-03-01

In this paper, we report a 3.4-in. flexible active matrix organic light emitting display (AMOLED) display with remarkably high definition (quarter high definition: QHD) in which oxide thin film transistors (TFTs) are used. We have developed a transfer technology in which a TFT array formed on a glass substrate is separated from the substrate by physical force and then attached to a flexible plastic substrate. Unlike a normal process in which a TFT array is directly fabricated on a thin plastic substrate, our transfer technology permits a high integration of high performance TFTs, such as low-temperature polycrystalline silicon TFTs (LTPS TFTs) and oxide TFTs, on a plastic substrate, because a flat, rigid, and thermally-stable glass substrate can be used in the TFT fabrication process in our transfer technology. As a result, this technology realized an oxide TFT array for an AMOLED on a plastic substrate. Furthermore, in order to achieve a high-definition AMOLED, color filters were incorporated in the TFT array and a white organic light-emitting diode (OLED) was combined. One of the features of this device is that the whole body of the device can be bent freely because a source driver and a gate driver can be integrated on the substrate due to the high mobility of an oxide TFT. This feature means “true” flexibility.

Low-temperature sol-gel oxide TFT with a fluoropolymer dielectric to enhance the effective mobility at low operation voltage

NASA Astrophysics Data System (ADS)

Yu, Shang-Yu; Wang, Kuan-Hsun; Zan, Hsiao-Wen; Soppera, Olivier

2017-06-01

In this article, we propose a solution-processed high-performance amorphous indium-zinc oxide (a-IZO) thin-film transistor (TFT) gated with a fluoropolymer dielectric. Compared with a conventional IZO TFT with a silicon nitride dielectric, a fluoropolymer dielectric effectively reduces the operation voltage to less than 3 V and greatly increases the effective mobility 40-fold. We suggest that the dipole layer formed at the dielectric surface facilitates electron accumulation and induces the electric double-layer effect. The dipole-induced hysteresis effect is also investigated.

Development of a radiation-hard CMOS process

NASA Technical Reports Server (NTRS)

Power, W. L.

1983-01-01

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samanta, Piyas, E-mail: piyas@vcfw.org; Mandal, Krishna C., E-mail: mandalk@cec.sc.edu

2016-08-14

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV belowmore » the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Epitaxial pentacene films grown on the surface of ion-beam-processed gate dielectric layer

NASA Astrophysics Data System (ADS)

Chou, W. Y.; Kuo, C. W.; Cheng, H. L.; Mai, Y. S.; Tang, F. C.; Lin, S. T.; Yeh, C. Y.; Horng, J. B.; Chia, C. T.; Liao, C. C.; Shu, D. Y.

2006-06-01

The following research describes the process of fabrication of pentacene films with submicron thickness, deposited by thermal evaporation in high vacuum. The films were fabricated with the aforementioned conditions and their characteristics were analyzed using x-ray diffraction, scanning electron microscopy, polarized Raman spectroscopy, and photoluminescence. Organic thin-film transistors (OTFTs) were fabricated on an indium tin oxide coated glass substrate, using an active layer of ordered pentacene molecules, which were grown at room temperature. Pentacene film was aligned using the ion-beam aligned method, which is typically employed to align liquid crystals. Electrical measurements taken on a thin-film transistor indicated an increase in the saturation current by a factor of 15. Pentacene-based OTFTs with argon ion-beam-processed gate dielectric layers of silicon dioxide, in which the direction of the ion beam was perpendicular to the current flow, exhibited a mobility that was up to an order of magnitude greater than that of the controlled device without ion-beam process; current on/off ratios of approximately 106 were obtained. Polarized Raman spectroscopy investigation indicated that the surface of the gate dielectric layer, treated with argon ion beam, enhanced the intermolecular coupling of pentacene molecules. The study also proposes the explanation for the mechanism of carrier transportation in pentacene films.

Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lai, Hsin-Cheng; Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw; Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan

In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100 °C. The a-IGZO TFT exhibit a mobility of 5.13 cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4 mm (strain = 1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10 V for 1500 s. Thus, this technology ismore » suitable for use in flexible displays.« less

Numerical simulation of offset-drain amorphous oxide-based thin-film transistors

NASA Astrophysics Data System (ADS)

Jeong, Jaewook

2016-11-01

In this study, we analyzed the electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with an offset-drain structure by technology computer aided design (TCAD) simulation. When operating in a linear region, an enhancement-type TFT shows poor field-effect mobility because most conduction electrons are trapped in acceptor-like defects in an offset region when the offset length (L off) exceeds 0.5 µm, whereas a depletion-type TFT shows superior field-effect mobility owing to the high free electron density in the offset region compared with the trapped electron density. When operating in the saturation region, both types of TFTs show good field-effect mobility comparable to that of a reference TFT with a large gate overlap. The underlying physics of the depletion and enhancement types of offset-drain TFTs are systematically analyzed.

Fabrication and Characteristics of High Mobility InSnZnO Thin Film Transistors.

PubMed

Choi, Pyungho; Lee, Junki; Park, Hyoungsun; Baek, Dohyun; Lee, Jaehyeong; Yi, Junsin; Kim, Sangsoo; Choi, Byoungdeog

2016-05-01

In this paper, we describe the fabrication of thin film transistors (TFTs) with amorphous indium-tin-zinc-oxide (ITZO) as the active material. A transparent ITZO channel layer was formed under an optimized oxygen partial pressure (OPP (%) = O2/(Ar + O2)) and subsequent annealing process. The electrical properties exhibited by this device include field-effect mobility (μ(eff)), sub-threshold swing (SS), and on/off current ratio (I(ON/OFF)) values of 28.97 cm2/V x s, 0.2 V/decade, and 2.64 x 10(7), respectively. The average transmittance values for each OPP condition in the visible range were greater than 80%. The positive gate bias stress resulted in a positive threshold voltage (V(th)) shift in the transfer curves and degraded the parameters μ(eff) and SS. These phenomena originated from electron trapping from the ITZO channel layer into the oxide/ITZO interface trap sites.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate.

PubMed

Han, Dedong; Zhang, Yi; Cong, Yingying; Yu, Wen; Zhang, Xing; Wang, Yi

2016-12-12

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O 2 /Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O 2 /Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (I off ) of 3 pA, a high on/off current ratio of 2 × 10 7 , a high saturation mobility (μ sat ) of 66.7 cm 2 /V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (V th ) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate

NASA Astrophysics Data System (ADS)

Han, Dedong; Zhang, Yi; Cong, Yingying; Yu, Wen; Zhang, Xing; Wang, Yi

2016-12-01

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O2/Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O2/Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (Ioff) of 3 pA, a high on/off current ratio of 2 × 107, a high saturation mobility (μsat) of 66.7 cm2/V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (Vth) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

High transconductance zinc oxide thin-film transistors on flexible plastic substrates

NASA Astrophysics Data System (ADS)

Kimura, Yuta; Higaki, Tomohiro; Maemoto, Toshihiko; Sasa, Shigehiko; Inoue, Masataka

2012-02-01

We report the fabrication and characterization on high-performance ZnO based TFTs on unheated plastic substrate. ZnO films were grown by pulsed laser deposition (PLD) on polyethylene napthalate (PEN) substrates. Top-gate ZnO-TFTs were fabricated by photolithography and wet chemical etching. The source and drain contacts were formed by lift-off of e-beam deposited Ti(20 nm)/Au(200 nm). An HfO2 with thickness 100 nm was selected as the gate insulator, and top gate electrode Ti(20 nm)/Au(200 nm) was deposited by e-beam evaporation. We prepared a set of the structure with SiO2/TiO2 to investigate the characteristic changes that appear in the film characteristics in response to bending. From the ID-VDS and the transfer characteristics which are affected by bending and return for the ZnO-TFT with SiO2/TiO2 buffers, the TFTs were bent to a curvature radius of 8.5 mm. The transconductance, gm is obtained 1.7 mS/mm on flat, 1.4 mS/mm on bending and 1.3 mS/mm on returning the film, respectively. The ID-VDS characteristics were therefore not changed by bending. All of the devices exhibited a clear pinch-off behavior and a high on/off current ratio of ˜10^6. The threshold voltages, Vth were not changed drastically. Furthermore, TFT structures were changed from a conventional top-gate type to a bottom-gate type. A high transconductance of 95.8 mS/mm was achieved in the bottom-gate type TFT by using Al2O3 oxide buffer.

Directed assembly of carbon nanotubes on soft substrates for use as a flexible biosensor array.

PubMed

Koh, Juntae; Yi, Mihye; Yang Lee, Byung; Kim, Tae Hyun; Lee, Joohyung; Jhon, Young Min; Hong, Seunghun

2008-12-17

We have developed a method to selectively assemble and align carbon nanotubes (CNTs) on soft substrates for use as flexible biosensors. In this strategy, a thin oxide layer was deposited on soft substrates via low temperature plasma enhanced chemical vapor deposition, and a linker-free assembly process was applied on the oxide surface where the assembly of carbon nanotubes was guided by methyl-terminated molecular patterns on the oxide surface. The electrical characterization of the fabricated CNT devices exhibited a typical p-type gating effect and 1/f noise behavior. The bare oxide regions near CNTs were functionalized with glutamate oxidase to fabricate selective biosensors to detect two forms of glutamate substances existing in different situations: L-glutamic acid, a neurotransmitting material, and monosodium glutamate, a food additive.

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Choi, Woo Young

2017-04-01

The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Scaling behavior of fully spin-coated TFT

NASA Astrophysics Data System (ADS)

Mondal, Sandip; Kumar, Arvind; Rao, K. S. R. Koteswara; Venkataraman, V.

2017-05-01

We studied channel scaling behavior of fully spin coated, low temperature solution processed thin film transistor (TFT) fabricated on p++ - Si (˜1021 cm-3) as bottom gate. The solution processed, spin coated 40 nm thick amorphous Indium Gallium Zinc Oxide (a-IGZO) and 50 nm thick amorphous zirconium di-oxide (a-ZrO2) has been used as channel and low leakage dielectric at 350°C respectively. The channel scaling effect of the TFT with different width/length ratio (W/L= 2.5, 5 and 15) for same channel length (L = 10 μm) has been demonstrated. The lowest threshold voltage (Vth) is 6.25 V for the W/L=50/10. The maximum field effect mobility (μFE) has been found to be 0.123 cm2/Vs from W/L of 50/10 with the drain to source voltage (VD) of 10V and 20V gate to source voltage (VG). We also demonstrated that there is no contact resistance effect on the mobility of the fully sol-gel spin coated TFT.

Threshold voltage tuning in AlGaN/GaN HFETs with p-type Cu2O gate synthesized by magnetron reactive sputtering

NASA Astrophysics Data System (ADS)

Wang, Lei; Li, Liuan; Xie, Tian; Wang, Xinzhi; Liu, Xinke; Ao, Jin-Ping

2018-04-01

In present study, copper oxide films were prepared at different sputtering powers (10-100 W) using magnetron reactive sputtering. The crystalline structure, surface morphologies, composition, and optical band gap of the as-grown films are dependent on sputtering power. As the sputtering power decreasing from 100 to 10 W, the composition of films changed from CuO to quasi Cu2O domination. Moreover, when the sputtering power is 10 W, a relative high hole carrier density and high-surface-quality quasi Cu2O thin film can be achieved. AlGaN/GaN HFETs were fabricated with the optimized p-type quasi Cu2O film as gate electrode, the threshold voltage of the device shows a 0.55 V positive shift, meanwhile, a lower gate leakage current, a higher ON/OFF drain current ratio of ∼108, a higher electron mobility (1465 cm2/Vs), and a lower subthreshold slope of 74 mV/dec are also achieved, compared with the typical Ni/Au-gated HFETs. Therefore, Cu2O have a great potential to develop high performance p-type gate AlGaN/GaN HFETs.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Fabrication of high-performance InGaZnOx thin film transistors based on control of oxidation using a low-temperature plasma

NASA Astrophysics Data System (ADS)

Takenaka, Kosuke; Endo, Masashi; Uchida, Giichiro; Setsuhara, Yuichi

2018-04-01

This work demonstrated the low-temperature control of the oxidation of Amorphous InGaZnOx (a-IGZO) films using inductively coupled plasma as a means of precisely tuning the properties of thin film transistors (TFTs) and as an alternative to post-deposition annealing at high temperatures. The effects of the plasma treatment of the as-deposited a-IGZO films were investigated by assessing the electrical properties of TFTs incorporating these films. A TFT fabricated using an a-IGZO film exposed to an Ar-H2-O2 plasma at substrate temperatures as low as 300 °C exhibited the best performance, with a field effect mobility as high as 42.2 cm2 V-1 s-1, a subthreshold gate voltage swing of 1.2 V decade-1, and a threshold voltage of 2.8 V. The improved transfer characteristics of TFTs fabricated with a-IGZO thin films treated using an Ar-H2-O2 plasma are attributed to the termination of oxygen vacancies around Ga and Zn atoms by OH radicals in the gas phase.

Evolution of zirconyl-stearate Langmuir monolayers and the synthesized ZrO2 thin films with pH

NASA Astrophysics Data System (ADS)

Choudhary, Raveena; Sharma, Rajni; Brar, Loveleen K.

2018-04-01

ZrO2 thin films have a wide range of applications ranging from photonics, antireflection coatings, and resistive oxygen gas sensors, as a gate dielectric and in high temperature fuel cells. We have used the deposition of zirconyl stearate monolayers followed by their oxidation as a method for the synthesis of zirconium oxide thin films. The zirconyl stearate films have been studied and deposited for first time to the best of our knowledge. The Langmuir monolayers are studied using pressure-Area (π-A) isotherms and oscillatory barrier method. The morphology of the films for limited number of layers was studied with FE-SEM to determine the effect of pH on the final ZrO2 film. The 200 layer deposition films show pure monoclinic phase. The films have a band gap ˜6.0eV with a strong PL emission peak is at 490 nm and a weak peak is at 423 nm. So the films formed by this deposition method are suitable for luminescent applications

Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique

NASA Astrophysics Data System (ADS)

Qiang, Lei; Liang, Xiaoci; Cai, Guangshuo; Pei, Yanli; Yao, Ruohe; Wang, Gang

2018-06-01

Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: EC - EF > 3kT and EC - EF ≤ 3kT, where kT is the thermal energy, EF and EC represent the Fermi level and the conduction band edge, respectively. Additionally, in order to describe conduction mechanisms more accurately, the extended mobility edge model is conjoined, which can also get rid of the complicated and lengthy computations. The good agreement between measured and calculated results confirms the efficiency of this model for the design of integrated large-area thin film circuits.

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo, E-mail: bsbae@kaist.ac.kr

In order to improve the reliability of TFT, an Al{sub 2}O{sub 3} insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al{sub 2}O{sub 3} layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V {sub o}{sup 2+} toward the interface between the gate insulator and the semiconductor. The inserted Al{sub 2}O{sub 3} triple layer exhibits amore » noticeably low turn on voltage shift of −0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm{sup 2}/V ⋅ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.« less

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Highly flexible electronics from scalable vertical thin film transistors.

PubMed

Liu, Yuan; Zhou, Hailong; Cheng, Rui; Yu, Woojong; Huang, Yu; Duan, Xiangfeng

2014-03-12

Flexible thin-film transistors (TFTs) are of central importance for diverse electronic and particularly macroelectronic applications. The current TFTs using organic or inorganic thin film semiconductors are usually limited by either poor electrical performance or insufficient mechanical flexibility. Here, we report a new design of highly flexible vertical TFTs (VTFTs) with superior electrical performance and mechanical robustness. By using the graphene as a work-function tunable contact for amorphous indium gallium zinc oxide (IGZO) thin film, the vertical current flow across the graphene-IGZO junction can be effectively modulated by an external gate potential to enable VTFTs with a highest on-off ratio exceeding 10(5). The unique vertical transistor architecture can readily enable ultrashort channel devices with very high delivering current and exceptional mechanical flexibility. With large area graphene and IGZO thin film available, our strategy is intrinsically scalable for large scale integration of VTFT arrays and logic circuits, opening up a new pathway to highly flexible macroelectronics.

Fusion of Night Vision and Thermal Images

DTIC Science & Technology

2006-12-01

with the walls of the MCP channels. Thus, a thin metal oxide coating commonly known as an ion barrier film is added to the input side of the MCP to...with film ion barrier to filmless gated tubes. An important improvement for Gen 4 products is a greater target identification range and higher target...Metal Seals with S-25 Cathode Mircro-channel plate Ceramic/Metal Seals with GaAS Cathode Mircro-channel plate with ion barrier film Ceramic

Effect of Rapid Thermal Annealing on the Electrical Characteristics of ZnO Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Remashan, Kariyadan; Hwang, Dae-Kue; Park, Seong-Ju; Jang, Jae-Hyung

2008-04-01

Thin-film transistors (TFTs) with a bottom-gate configuration were fabricated with an RF magnetron sputtered undoped zinc oxide (ZnO) channel layer and plasma-enhanced chemical vapor deposition (PECVD) grown silicon nitride as a gate dielectric. Postfabrication rapid thermal annealing (RTA) and subsequent nitrous oxide (N2O) plasma treatment were employed to improve the performance of ZnO TFTs in terms of on-current and on/off current ratio. The RTA treatment increases the on-current of the TFT significantly, but it also increases its off-current. The off-current of 2×10-8 A and on/off current ratio of 3×103 obtained after the RTA treatment were improved to 10-10 A and 105, respectively, by the subsequent N2O plasma treatment. The better device performance can be attributed to the reduction of oxygen vacancies at the top region of the channel due to oxygen incorporation from the N2O plasma. X-ray photoelectron spectroscopy (XPS) analysis of the TFT samples showed that the RTA-treated ZnO surface has more oxygen vacancies than as-deposited samples, which results in the increased drain current. The XPS study also showed that the subsequent N2O plasma treatment reduces oxygen vacancies only at the surface of ZnO so that the better off-current and on/off current ratio can be obtained.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Detection of saliva-range glucose concentrations using organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elkington, D.; Belcher, W. J.; Dastoor, P. C.

We describe the development of a glucose sensor through direct incorporation of an enzyme (glucose oxidase) into the gate of an organic thin film transistor (OTFT). We show that glucose diffusion is the key determinant of the device response time and present a mechanism of glucose sensing in these devices that involves protonic doping of the transistor channel via enzymatic oxidation of glucose. The integrated OTFT sensor is sensitive across 4 decades of glucose concentration; a range that encompasses both the blood and salivary glucose concentration levels. As such, this work acts as a proof-of-concept for low-cost printed biosensors formore » salivary glucose.« less

Wireless thin film transistor based on micro magnetic induction coupling antenna.

PubMed

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-12-22

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the 'internet of things' (IoT).

Wireless thin film transistor based on micro magnetic induction coupling antenna

PubMed Central

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-01-01

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the ‘internet of things’ (IoT). PMID:26691929

Wireless thin film transistor based on micro magnetic induction coupling antenna

NASA Astrophysics Data System (ADS)

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-12-01

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the ‘internet of things’ (IoT).

Fabrication and characterization of high mobility spin-coated zinc oxide thin film transistors

NASA Astrophysics Data System (ADS)

Singh, Shaivalini; Chakrabarti, P.

2012-10-01

A ZnO based thin film transistor (TFT) with bottom-gate configuration and SiO2 as insulating layer has been fabricated and characterized. The ZnO thin film was prepared by spin coating the sol-gel solution on the p-type Si wafers. The optical and structural properties of ZnO films were investigated using UV measurements and scanning electron microscope (SEM). The result of UV-visible study confirms that the films have a good absorbance in UV region and relatively low absorbance in the visible region. The TFT exhibited an off-current of 2.5×10-7 A. The values of field effect channel mobility and on/off current ratio extracted for the device, measured 11 cm2/V.s and ~102 respectively. The value of threshold voltage was found to be 1.3 V.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

NASA Astrophysics Data System (ADS)

Chaisantikulwat, W.; Mouis, M.; Ghibaudo, G.; Cristoloveanu, S.; Widiez, J.; Vinet, M.; Deleonibus, S.

2007-11-01

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Optically transparent thin-film transistors based on 2D multilayer MoS₂ and indium zinc oxide electrodes.

PubMed

Kwon, Junyeon; Hong, Young Ki; Kwon, Hyuk-Jun; Park, Yu Jin; Yoo, Byungwook; Kim, Jiwan; Grigoropoulos, Costas P; Oh, Min Suk; Kim, Sunkook

2015-01-21

We report on optically transparent thin film transistors (TFTs) fabricated using multilayered molybdenum disulfide (MoS2) as the active channel, indium tin oxide (ITO) for the back-gated electrode and indium zinc oxide (IZO) for the source/drain electrodes, respectively, which showed more than 81% transmittance in the visible wavelength. In spite of a relatively large Schottky barrier between MoS2 and IZO, the n-type behavior with a field-effect mobility (μ(eff)) of 1.4 cm(2) V(-1) s(-1) was observed in as-fabricated transparent MoS2 TFT. In order to enhance the performances of transparent MoS2 TFTs, a picosecond pulsed laser was selectively irradiated onto the contact region of the IZO electrodes. Following laser annealing, μ(eff) increased to 4.5 cm(2) V(-1) s(-1), and the on-off current ratio (I(on)/I(off)) increased to 10(4), which were attributed to the reduction of the contact resistance between MoS2 and IZO.

All 2D, high mobility, flexible, transparent thin film transistor

DOEpatents

Das, Saptarshi; Sumant, Anirudha V.; Roelofs, Andreas

2017-01-17

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

Away from silicon era: the paper electronics

NASA Astrophysics Data System (ADS)

Martins, R.; Brás, B.; Ferreira, I.; Pereira, L.; Barquinha, P.; Correia, N.; Costa, R.; Busani, T.; Gonçalves, A.; Pimentel, A.; Fortunato, E.

2011-02-01

Today there is a strong interest in the scientific and industrial community concerning the use of biopolymers for electronic applications, mainly driven by low-cost and disposable applications. Adding to this interest, we must recognize the importance of the wireless auto sustained and low energy consumption electronics dream. This dream can be fulfilled by cellulose paper, the lightest and the cheapest known substrate material, as well as the Earth's major biopolymer and of tremendous global economic importance. The recent developments of oxide thin film transistors and in particular the production of paper transistors at room temperature had contributed, as a first step, for the development of disposable, low cost and flexible electronic devices. To fulfil the wireless demand, it is necessary to prove the concept of self powered devices. In the case of paper electronics, this implies demonstrating the idea of self regenerated thin film paper batteries and its integration with other electronic components. Here we demonstrate this possibility by actuating the gate of paper transistors by paper batteries. We found that when a sheet of cellulose paper is covered in both faces with thin layers of opposite electrochemical potential materials, a voltage appears between both electrodes -paper battery, which is also self-regenerated. The value of the potential depends upon the materials used for anode and cathode. An open circuit voltage of 0.5V and a short-circuit current density of 1μA/cm2 were obtained in the simplest structure produced (Cu/paper/Al). For actuating the gate of the paper transistor, seven paper batteries were integrated in the same substrate in series, supplying a voltage of 3.4V. This allows proper ON/OFF control of the paper transistor. Apart from that transparent conductive oxides can be also used as cathode/anode materials allowing so the production of thin film batteries with transparent electrodes compatible with flexible, invisible, self powered and wireless electronics.

Tunneling contact IGZO TFTs with reduced saturation voltages

NASA Astrophysics Data System (ADS)

Wang, Longyan; Sun, Yin; Zhang, Xintong; Zhang, Lining; Zhang, Shengdong; Chan, Mansun

2017-04-01

We report a tunneling contact indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with a graphene interlayer technique in this paper. A Schottky junction is realized between a metal and IGZO with a graphene interlayer, leading to a quantum tunneling of the TFT transport in saturation regions. This tunneling contact enables a significant reduction in the saturation drain voltage Vdsat compared to that of the thermionic emission TFTs, which is usually equal to the gate voltage minus their threshold voltages. Measured temperature independences of the subthreshold swing confirm a transition from the thermionic emission to quantum tunneling transports depending on the gate bias voltages in the proposed device. The tunneling contact TFTs with the graphene interlayer have implications to reduce the power consumptions of certain applications such as the active matrix OLED display.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Hyun-Sik; Jeon, Sanghun, E-mail: jeonsh@korea.ac.kr

Upon light exposure, an indium-zinc-oxide (IZO) thin-film transistor (TFT) presents higher photoconductivity by several orders of magnitude at the negative gate bias region. Among various device geometrical factors, scaling down the channel length of the photo-transistor results in an anomalous increase in photoconductivity. To probe the origin of this high photoconductivity in short-channel device, we measured transient current, current–voltage, and capacitance–voltage characteristics of IZO–TFTs with various channel lengths and widths before and after illumination. Under the illumination, the equilibrium potential region which lies far from front interface exists only in short-channel devices, forming the un-depleted conducting back channel. This regionmore » plays an important role in carrier transport under the illumination, leading to high photoconductivity in short-channel devices. Photon exposure coupled with gate-modulated band bending for short-channel devices leads to the accumulation of V{sub o}{sup ++} at the front channel and screening negative gate bias, thereby generating high current flow in the un-depleted back-channel region.« less

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk; Mazzocco, R.

2015-05-18

We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currentsmore » (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.« less

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

NASA Technical Reports Server (NTRS)

Rafferty, Connor S.; Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario G.; Bude, J.; Dutton, Robert W.; Saini, Subhash (Technical Monitor)

1998-01-01

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Large electron concentration modulation using capacitance enhancement in SrTiO{sub 3}/SmTiO{sub 3} Fin-field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Verma, Amit, E-mail: averma@cornell.edu; Nomoto, Kazuki; School of Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853

2016-05-02

Solid-state modulation of 2-dimensional electron gases (2DEGs) with extreme (∼3.3 × 10{sup 14 }cm{sup −2}) densities corresponding to 1/2 electron per interface unit cell at complex oxide heterointerfaces (such as SrTiO{sub 3}/GdTiO{sub 3} or SrTiO{sub 3}/SmTiO{sub 3}) is challenging because it requires enormous gate capacitances. One way to achieve large gate capacitances is by geometrical capacitance enhancement in fin structures. In this work, we fabricate both Au-gated planar field effect transistors (FETs) and Fin-FETs with varying fin-widths on 60 nm SrTiO{sub 3}/5 nm SmTiO{sub 3} thin films grown by hybrid molecular beam epitaxy. We find that the FinFETs exhibit higher gate capacitance comparedmore » to planar FETs. By scaling down the SrTiO{sub 3}/SmTiO{sub 3} fin widths, we demonstrate further gate capacitance enhancement, almost twice compared to the planar FETs. In the FinFETs with narrowest fin-widths, we demonstrate a record 2DEG electron concentration modulation of ∼2.4 × 10{sup 14 }cm{sup −2}.« less

Selective UV–O3 treatment for indium zinc oxide thin film transistors with solution-based multiple active layer

NASA Astrophysics Data System (ADS)

Kim, Yu-Jung; Jeong, Jun-Kyo; Park, Jung-Hyun; Jeong, Byung-Jun; Lee, Hi-Deok; Lee, Ga-Won

2018-06-01

In this study, a method to control the electrical performance of solution-based indium zinc oxide (IZO) thin film transistors (TFTs) is proposed by ultraviolet–ozone (UV–O3) treatment on the selective layer during multiple IZO active layer depositions. The IZO film is composed of triple layers formed by spin coating and UV–O3 treatment only on the first layer or last layer. The IZO films are compared by X-ray photoelectron spectroscopy, and the results show that the atomic ratio of oxygen vacancy (VO) increases in the UV–O3 treatment on the first layer, while it decreases on last layer. The device characteristics of the bottom gated structure are also improved in the UV–O3 treatment on the first layer. This indicates that the selective UV–O3 treatment in a multi-stacking active layer is an effective method to optimize TFT properties by controlling the amount of VO in the IZO interface and surface independently.

Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Faber, Hendrik; Anthopoulos, Thomas D., E-mail: t.anthopoulos@imperial.ac.uk

2015-03-02

Indium oxide (In{sub 2}O{sub 3}) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm{sup 2}V{sup −1}s{sup −1} and 16 cm{sup 2}V{sup −1}s{sup −1} for coplanar and staggered architectures, respectively. Integration of In{sub 2}O{sub 3} transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (≤250 °C) of In{sub 2}O{sub 3} also allowed transistor fabrication on free-standing 50 μm-thick polyimide foils. The resulting flexible In{sub 2}O{sub 3} transistors exhibit good characteristics and remain fully functional even whenmore » bent to tensile radii of 4 mm.« less

Crystallization behavior of amorphous indium-gallium-zinc-oxide films and its effects on thin-film transistor performance

NASA Astrophysics Data System (ADS)

Suko, Ayaka; Jia, JunJun; Nakamura, Shin-ichi; Kawashima, Emi; Utsuno, Futoshi; Yano, Koki; Shigesato, Yuzo

2016-03-01

Amorphous indium-gallium-zinc oxide (a-IGZO) films were deposited by DC magnetron sputtering and post-annealed in air at 300-1000 °C for 1 h to investigate the crystallization behavior in detail. X-ray diffraction, electron beam diffraction, and high-resolution electron microscopy revealed that the IGZO films showed an amorphous structure after post-annealing at 300 °C. At 600 °C, the films started to crystallize from the surface with c-axis preferred orientation. At 700-1000 °C, the films totally crystallized into polycrystalline structures, wherein the grains showed c-axis preferred orientation close to the surface and random orientation inside the films. The current-gate voltage (Id-Vg) characteristics of the IGZO thin-film transistor (TFT) showed that the threshold voltage (Vth) and subthreshold swing decreased markedly after the post-annealing at 300 °C. The TFT using the totally crystallized films also showed the decrease in Vth, whereas the field-effect mobility decreased considerably.

P-channel thin film transistors using reduced graphene oxide

NASA Astrophysics Data System (ADS)

Chakraborty, S.; Resmi, A. N.; Renuka Devi, P.; Jinesh, K. B.

2017-04-01

Chemically reduced graphene oxide (rGO) samples with various degrees of reduction were prepared using hydrazine hydrate as the reducing agent. Scanning tunnelling microscope imaging shows that rGO contains rows of randomly distributed patches of epoxy groups. The local density of states of the rGO samples were mapped with scanning tunnelling spectroscopy, which shows that the bandgap in rGO originates from the epoxide regions itself. The Fermi level of the epoxide regions is shifted towards the valence band, making rGO locally p-type and a range of bandgaps from 0-2.2 eV was observed in these regions. Thin film transistors were fabricated using rGO as the channel layer. The devices show excellent output characteristics with clear saturation and gate dependence. The transfer characteristics show that rGO behaves as a p-type semiconductor; the devices exhibit an on/off ratio of 104, with a low-bias hole mobility of 3.9 cm2 V-1 s-1.

Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

PubMed Central

Rolin, Cedric; Kang, Enpu; Lee, Jeong-Hwan; Borghs, Gustaaf; Heremans, Paul; Genoe, Jan

2017-01-01

Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects. PMID:28397852

Effect of Gallium Doping on the Characteristic Properties of Polycrystalline Cadmium Telluride Thin Film

NASA Astrophysics Data System (ADS)

Ojo, A. A.; Dharmadasa, I. M.

2017-08-01

Ga-doped CdTe polycrystalline thin films were successfully electrodeposited on glass/fluorine doped tin oxide substrates from aqueous electrolytes containing cadmium nitrate (Cd(NO3)2·4H2O) and tellurium oxide (TeO2). The effects of different Ga-doping concentrations on the CdTe:Ga coupled with different post-growth treatments were studied by analysing the structural, optical, morphological and electronic properties of the deposited layers using x-ray diffraction (XRD), ultraviolet-visible spectrophotometry, scanning electron microscopy, photoelectrochemical cell measurement and direct-current conductivity test respectively. XRD results show diminishing (111)C CdTe peak above 20 ppm Ga-doping and the appearance of (301)M GaTe diffraction above 50 ppm Ga-doping indicating the formation of two phases; CdTe and GaTe. Although, reductions in the absorption edge slopes were observed above 20 ppm Ga-doping for the as-deposited CdTe:Ga layer, no obvious influence on the energy gap of CdTe films with Ga-doping were detected. Morphologically, reductions in grain size were observed at 50 ppm Ga-doping and above with high pinhole density within the layer. For the as-deposited CdTe:Ga layers, conduction type change from n- to p- were observed at 50 ppm, while the n-type conductivity were retained after post-growth treatment. Highest conductivity was observed at 20 ppm Ga-doping of CdTe. These results are systematically reported in this paper.

Organic Field Effect Transistor Using Amorphous Fluoropolymer as Gate Insulating Film

NASA Astrophysics Data System (ADS)

Kitajima, Yosuke; Kojima, Kenzo; Mizutani, Teruyoshi; Ochiai, Shizuyasu

Organic field effect transistors are fabricated by the active layer of Regioregular poly (3-hexylthiophene-2,5-diy)(P3HT) thin film. CYTOP thin film made from Amorphous Fluoropolymer and fabricated by spin-coating is adopted to a gate dielectric layer on Polyethylenenaphthalate (PEN) thin film that is the substrate of an organic field effect transistor. The surface morphology and molecular orientation of P3HT thin films is observed by atomic force microscope (AFM) and X-Ray diffractometer (XRD). Grains are observed on the CYTOP thin film via an AFM image and the P3HT molecule is oriented perpendicularly on the CYTOP thin film. Based on the performance of the organic field effect transistor, the carrier mobility is 0.092 cm2/Vs, the ON/OFF ratio is 7, and the threshold voltage is -12 V. The ON/OFF ratio is relatively low and to improve On/Off ratio, the CYTOP/Polyimide double gate insulating layer is adopted to OFET.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

High-frequency electromechanical resonators based on thin GaTe

NASA Astrophysics Data System (ADS)

Chitara, Basant; Ya'akobovitz, Assaf

2017-10-01

Gallium telluride (GaTe) is a layered material, which exhibits a direct bandgap (˜1.65 eV) regardless of its thickness and therefore holds great potential for integration as a core element in stretchable optomechanical and optoelectronic devices. Here, we characterize and demonstrate the elastic properties and electromechanical resonators of suspended thin GaTe nanodrums. We used atomic force microscopy to extract the Young’s modulus of GaTe (average value ˜39 GPa) and to predict the resonance frequencies of suspended GaTe nanodrums of various geometries. Electromechanical resonators fabricated from suspended GaTe revealed fundamental resonance frequencies in the range of 10-25 MHz, which closely match predicted values. Therefore, this study paves the way for creating a new generation of GaTe based nanoelectromechanical devices with a direct bandgap vibrating element, which can serve as optomechanical sensors and actuators.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

Three dimensional graphene transistor for ultra-sensitive pH sensing directly in biological media.

PubMed

Ameri, Shideh Kabiri; Singh, Pramod K; Sonkusale, Sameer R

2016-08-31

In this work, pH sensing directly in biological media using three dimensional liquid gated graphene transistors is presented. The sensor is made of suspended network of graphene coated all around with thin layer of hafnium oxide (HfO2), showing high sensitivity and sensing beyond the Debye-screening limit. The performance of the pH sensor is validated by measuring the pH of isotonic buffered, Dulbecco's phosphate buffered saline (DPBS) solution, and of blood serum derived from Sprague-Dawley rat. The pH sensor shows high sensitivity of 71 ± 7 mV/pH even in high ionic strength media with molarities as high as 289 ± 1 mM. High sensitivity of this device is owing to suspension of three dimensional graphene in electrolyte which provides all around liquid gating of graphene, leading to higher electrostatic coupling efficiency of electrolyte to the channel and higher gating control of transistor channel by ions in the electrolyte. Coating graphene with hafnium oxide film (HfO2) provides binding sites for hydrogen ions, which results in higher sensitivity and sensing beyond the Debye-screening limit. The 3D graphene transistor offers the possibility of real-time pH measurement in biological media without the need for desaltation or sample preparation. Copyright © 2016 Elsevier B.V. All rights reserved.

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

NASA Astrophysics Data System (ADS)

Pereira, A. S. N.; de Streel, G.; Planes, N.; Haond, M.; Giacomini, R.; Flandre, D.; Kilchytska, V.

2017-02-01

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis' model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.

Hot-Carrier Immunity of Polycrystalline Silicon Thin Film Transistors Using Silicon Oxynitride Gate Dielectric Formed with Plasma-Enhanced Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Kunii, Masafumi

2009-11-01

An analysis is presented of the hot-carrier degradation in a polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon oxynitride gate dielectric formed with plasma-enhanced chemical vapor deposition. An introduction of silicon oxynitride into a gate dielectric significantly improves hot-carrier immunity even under the severe stressing mode of drain avalanche hot carriers. To compensate the initial negative shift of threshold voltage for TFTs with a silicon oxynitride gate dielectric, high-pressure water vapor annealing (HWA) is applied. A comparison of TFTs with and without HWA reveals that the improvement in hot-carrier immunity is mainly attributed to the introduction of Si≡N bonds into a gate dielectric.

Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

2018-04-01

A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

High Performance 50 nm InAlAs/In0.75GaAs Metamorphic High Electron Mobility Transistors with Si3N4 Passivation on Thin InGaAs Layer

NASA Astrophysics Data System (ADS)

Yeon, Seongjin; Seo, Kwangseok

2008-04-01

We fabricated 50 nm InAlAs/InGaAs metamorphic high electron mobility transistors (HEMTs) with a very thin barrier. Through the reduction of the gate-channel distance (dGC) in the epitaxial structure, a channel aspect ratio (ARC) of over three was achieved when Lg was 50 nm. We inserted a thin InGaAs layer as a protective layer, and tested various gate structures to reduce surface problems induced by barrier shrinkage and to optimize the device characteristics. Through the optimization of the gate structure with the thin InGaAs layer, the fabricated 50 nm metamorphic HEMT exhibited high DC and RF characteristics, Gm of 1.5 S/mm, and fT of 490 GHz.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

An All Oxide-Based Imperceptible Thin-Film Transistor with Humidity Sensing Properties

PubMed Central

Kim, Kyung Su; Ahn, Cheol Hyoun; Kang, Won Jun; Cho, Sung Woon; Jung, Sung Hyeon; Yoon, Dae Ho; Cho, Hyung Koun

2017-01-01

We have examined the effects of oxygen content and thickness in sputtered InSnO (ITO) electrodes, especially for the application of imperceptible amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs) in humidity sensors. The imperceptible a-IGZO TFT with 50-nm ITO electrodes deposited at Ar:O2 = 29:0.3 exhibited good electrical performances with Vth of −0.23 V, SS of 0.34 V/dec, µFE of 7.86 cm2/V∙s, on/off ratio of 8.8 × 107, and has no degradation for bending stress up to a 3.5-mm curvature. The imperceptible oxide TFT sensors showed the highest sensitivity for the low and wide gate bias of −1~2 V under a wide range of relative humidity (40–90%) at drain voltage 1 V, resulting in low power consumption by the sensors. Exposure to water vapor led to a negative shift in the threshold voltage (or current enhancement), and an increase in relative humidity induced continuous threshold voltage shift. In particular, compared to conventional resistor-type sensors, the imperceptible oxide TFT sensors exhibited extremely high sensitivity from a current amplification of >103. PMID:28772888

An All Oxide-Based Imperceptible Thin-Film Transistor with Humidity Sensing Properties.

PubMed

Kim, Kyung Su; Ahn, Cheol Hyoun; Kang, Won Jun; Cho, Sung Woon; Jung, Sung Hyeon; Yoon, Dae Ho; Cho, Hyung Koun

2017-05-13

We have examined the effects of oxygen content and thickness in sputtered InSnO (ITO) electrodes, especially for the application of imperceptible amorphous-InGaZnO ( a -IGZO) thin-film transistors (TFTs) in humidity sensors. The imperceptible a -IGZO TFT with 50-nm ITO electrodes deposited at Ar:O₂ = 29:0.3 exhibited good electrical performances with V th of -0.23 V, SS of 0.34 V/dec, µ FE of 7.86 cm²/V∙s, on/off ratio of 8.8 × 10⁷, and has no degradation for bending stress up to a 3.5-mm curvature. The imperceptible oxide TFT sensors showed the highest sensitivity for the low and wide gate bias of -1~2 V under a wide range of relative humidity (40-90%) at drain voltage 1 V, resulting in low power consumption by the sensors. Exposure to water vapor led to a negative shift in the threshold voltage (or current enhancement), and an increase in relative humidity induced continuous threshold voltage shift. In particular, compared to conventional resistor-type sensors, the imperceptible oxide TFT sensors exhibited extremely high sensitivity from a current amplification of >10³.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Effects of vacuum rapid thermal annealing on the electrical characteristics of amorphous indium gallium zinc oxide thin films

NASA Astrophysics Data System (ADS)

Lee, Hyun-Woo; Cho, Won-Ju

2018-01-01

We investigated the effects of vacuum rapid thermal annealing (RTA) on the electrical characteristics of amorphous indium gallium zinc oxide (a-IGZO) thin films. The a-IGZO films deposited by radiofrequency sputtering were subjected to vacuum annealing under various temperature and pressure conditions with the RTA system. The carrier concentration was evaluated by Hall measurement; the electron concentration of the a-IGZO film increased and the resistivity decreased as the RTA temperature increased under vacuum conditions. In a-IGZO thin-film transistors (TFTs) with a bottom-gate top-contact structure, the threshold voltage decreased and the leakage current increased as the vacuum RTA temperature increased. As the annealing pressure decreased, the threshold voltage decreased, and the leakage current increased. X-ray photoelectron spectroscopy indicated changes in the lattice oxygen and oxygen vacancies of the a-IGZO films after vacuum RTA. At higher annealing temperatures, the lattice oxygen decreased and oxygen vacancies increased, which suggests that oxygen was diffused out in a reduced pressure atmosphere. The formation of oxygen vacancies increased the electron concentration, which consequently increased the conductivity of the a-IGZO films and reduced the threshold voltage of the TFTs. The results showed that the oxygen vacancies and electron concentrations of the a-IGZO thin films changed with the vacuum RTA conditions and that high-temperature RTA treatment at low pressure converted the IGZO thin film to a conductor.

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

NASA Astrophysics Data System (ADS)

Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

2016-02-01

A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Synergistic approach to high-performance oxide thin film transistors using a bilayer channel architecture.

PubMed

Yu, Xinge; Zhou, Nanjia; Smith, Jeremy; Lin, Hui; Stallings, Katie; Yu, Junsheng; Marks, Tobin J; Facchetti, Antonio

2013-08-28

We report here a bilayer metal oxide thin film transistor concept (bMO TFT) where the channel has the structure: dielectric/semiconducting indium oxide (In2O3) layer/semiconducting indium gallium oxide (IGO) layer. Both semiconducting layers are grown from solution via a low-temperature combustion process. The TFT mobilities of bottom-gate/top-contact bMO TFTs processed at T = 250 °C are ~5tmex larger (~2.6 cm(2)/(V s)) than those of single-layer IGO TFTs (~0.5 cm(2)/(V s)), reaching values comparable to single-layer combustion-processed In2O3 TFTs (~3.2 cm(2)/(V s)). More importantly, and unlike single-layer In2O3 TFTs, the threshold voltage of the bMO TFTs is ~0.0 V, and the current on/off ratio is significantly enhanced to ~1 × 10(8) (vs ~1 × 10(4) for In2O3). The microstructure and morphology of the In2O3/IGO bilayers are analyzed by X-ray diffraction, atomic force microscopy, X-ray photoelectron spectroscopy, and transmission electron microscopy, revealing the polycrystalline nature of the In2O3 layer and the amorphous nature of the IGO layer. This work demonstrates that solution-processed metal oxides can be implemented in bilayer TFT architectures with significantly enhanced performance.

Fabrication and characterization of oxide-based thin film transistors, and process development for oxide heterostructures

NASA Astrophysics Data System (ADS)

Lim, Wantae

2009-12-01

This dissertation is focused on the development of thin film transistors (TFTs) using oxide materials composed of post-transitional cations with (n-1)d 10ns0 (n≥4). The goal is to achieve high performance oxide-based TFTs fabricated at low processing temperature on either glass or flexible substrates for next generation display applications. In addition, etching mechanism and Ohmic contact formation for oxide heterostructure (ZnO/CuCrO 2) system is demonstrated. The deposition and characterization of oxide semiconductors (In 2O3-ZnO, and InGaZnO4) using a RF-magnetron sputtering system are studied. The main influence on the resistivity of the films is found to be the oxygen partial pressure in the sputtering ambient. The films remained amorphous and transparent (> 70%) at all process conditions. These films showed good transmittance at suitable conductivity for transistor fabrication. The electrical characteristics of both top- and bottom-gate type Indium Zinc Oxide (InZnO) and Indium Gallium Zinc Oxide (InGaZnO4)-based TFTs are reported. The InZnO films were favorable for depletion-mode TFTs due to their tendency to form oxygen vacancies, while enhancement-mode devices were realized with InGaZnO4 films. The InGaZnO4-based TFTs fabricated on either glass or plastic substrates at low temperature (<100°C) exhibit good electrical properties: the saturation mobility of 5--12 cm2.V-1.s-1 and threshold voltage of 0.5--2.5V. The devices are also examined as a function of aging time in order to verify long-term stability in air. The effect of gate dielectric materials on electrical properties of InGaZnO 4-based TFTs was investigated. The use of SiNx film as a gate dielectric reduces the trap density and the roughness at the channel/gate dielectric interface compared to SiO2 gate dielectric, resulting in an improvement of device parameters by reducing scattering of trapped charges at the interface. The quality of interface is shown to have large effect on TFT performance. Plasma etching process of ZnO was carried out using a variety of plasma chemistries: CH4/H2-, C2H6/H 2-, Cl2-, IBr-, ICl-, BI3- and BBr3/Ar. High fidelity pattern transfer can be achieved with practical etch rate and very smooth surface in methane-based chemistries, although the sidewall is not completely vertical. Threshold energy as low as 60 +/- 20 eV for all plasma chemistries was achieved, confirming that etching is driven by ion-assisted mechanism over the whole range of ion energy. Ohmic contacts to p-CuCrO2 are examined using borides (CrB2 and W2B5), nitrides (TaN and ZrN) and a high temperature metal (Ir). These materials are used as a diffusion barrier in Ni/Au based contacts, i.e., Ni/Au/X/Ti/Au metallization scheme, where X is the refractory material. A minimum specific contact resistance of ˜ 5x10 -4 O.cm2 was achieved for the Ir-containing contacts after annealing at temperature of 500--800°C for 60s in O2 ambient. The presence of Ir diffusion barrier increase the thermal stability of the contacts by ˜ 200 °C compared to conventional Ni/Au contacts. By sharp contrast, the use of other refractory materials led to the poorer thermal stability, with the contact resistance increasing sharply above 400°C.

Effect of growth rate on crystallization of HfO{sub 2} thin films deposited by RF magnetron sputtering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dhanunjaya, M.; Manikanthababu, N.; Pathak, A. P.

2016-05-23

Hafnium oxide (HfO{sub 2}) is the potentially useful dielectric material in both; electronics to replace the conventional SiO{sub 2} as gate dielectric and in Optics as anti-reflection coating material. In this present work we have synthesized polycrystalline HfO{sub 2} thin films by RF magnetron sputtering deposition technique with varying target to substrate distance. The deposited films were characterized by X-ray Diffraction, Rutherford Backscattering Spectrometry (RBS) and transmission and Reflection (T&R) measurements to study the growth behavior, microstructure and optical properties. XRD measurement shows that the samples having mixed phase of monoclinic, cubic and tetragonal crystal structure. RBS measurements suggest themore » formation of Inter Layer (IL) in between Substrate and film.« less

Gate-Induced Interfacial Superconductivity in 1T-SnSe2.

PubMed

Zeng, Junwen; Liu, Erfu; Fu, Yajun; Chen, Zhuoyu; Pan, Chen; Wang, Chenyu; Wang, Miao; Wang, Yaojia; Xu, Kang; Cai, Songhua; Yan, Xingxu; Wang, Yu; Liu, Xiaowei; Wang, Peng; Liang, Shi-Jun; Cui, Yi; Hwang, Harold Y; Yuan, Hongtao; Miao, Feng

2018-02-14

Layered metal chalcogenide materials provide a versatile platform to investigate emergent phenomena and two-dimensional (2D) superconductivity at/near the atomically thin limit. In particular, gate-induced interfacial superconductivity realized by the use of an electric-double-layer transistor (EDLT) has greatly extended the capability to electrically induce superconductivity in oxides, nitrides, and transition metal chalcogenides and enable one to explore new physics, such as the Ising pairing mechanism. Exploiting gate-induced superconductivity in various materials can provide us with additional platforms to understand emergent interfacial superconductivity. Here, we report the discovery of gate-induced 2D superconductivity in layered 1T-SnSe 2 , a typical member of the main-group metal dichalcogenide (MDC) family, using an EDLT gating geometry. A superconducting transition temperature T c ≈ 3.9 K was demonstrated at the EDL interface. The 2D nature of the superconductivity therein was further confirmed based on (1) a 2D Tinkham description of the angle-dependent upper critical field B c2 , (2) the existence of a quantum creep state as well as a large ratio of the coherence length to the thickness of superconductivity. Interestingly, the in-plane B c2 approaching zero temperature was found to be 2-3 times higher than the Pauli limit, which might be related to an electric field-modulated spin-orbit interaction. Such results provide a new perspective to expand the material matrix available for gate-induced 2D superconductivity and the fundamental understanding of interfacial superconductivity.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

PubMed

Nair, Aswathi; Bhattacharya, Prasenjit; Sambandan, Sanjiv

2017-12-20

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Dopant distributions in n-MOSFET structure observed by atom probe tomography.

PubMed

Inoue, K; Yano, F; Nishida, A; Takamizawa, H; Tsunomura, T; Nagai, Y; Hasegawa, M

2009-11-01

The dopant distributions in an n-type metal-oxide-semiconductor field effect transistor (MOSFET) structure were analyzed by atom probe tomography. The dopant distributions of As, P, and B atoms in a MOSFET structure (gate, gate oxide, channel, source/drain extension, and halo) were obtained. P atoms were segregated at the interface between the poly-Si gate and the gate oxide, and on the grain boundaries of the poly-Si gate, which had an elongated grain structure along the gate height direction. The concentration of B atoms was enriched near the edge of the source/drain extension where the As atoms were implanted.

Low leakage current gate dielectrics prepared by ion beam assisted deposition for organic thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Chang Su; Jo, Sung Jin; Kim, Jong Bok; Ryu, Seung Yoon; Noh, Joo Hyon; Baik, Hong Koo; Lee, Se Jong; Kim, Youn Sang

2007-12-01

This communication reports on the fabrication of low operating voltage pentacene thin-film transistors with high-k gate dielectrics by ion beam assisted deposition (IBAD). These densely packed dielectric layers by IBAD show a much lower level of leakage current than those created by e-beam evaporation. These results, from the fact that those thin films deposited with low adatom mobility, have an open structure, consisting of spherical grains with pores in between, that acts as a significant path for leakage current. By contrast, our results demonstrate the potential to limit this leakage. The field effect mobility, on/off current ratio, and subthreshold slope obtained from pentacene thin-film transistors (TFTs) were 1.14 cm2/V s, 105, and 0.41 V/dec, respectively. Thus, the high-k gate dielectrics obtained by IBAD show promise in realizing low leakage current, low voltage, and high mobility pentacene TFTs.

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Photo-induced persistent inversion of germanium in a 200-nm-deep surface region.

PubMed

Prokscha, T; Chow, K H; Stilp, E; Suter, A; Luetkens, H; Morenzoni, E; Nieuwenhuys, G J; Salman, Z; Scheuermann, R

2013-01-01

The controlled manipulation of the charge carrier concentration in nanometer thin layers is the basis of current semiconductor technology and of fundamental importance for device applications. Here we show that it is possible to induce a persistent inversion from n- to p-type in a 200-nm-thick surface layer of a germanium wafer by illumination with white and blue light. We induce the inversion with a half-life of ~12 hours at a temperature of 220 K which disappears above 280 K. The photo-induced inversion is absent for a sample with a 20-nm-thick gold capping layer providing a Schottky barrier at the interface. This indicates that charge accumulation at the surface is essential to explain the observed inversion. The contactless change of carrier concentration is potentially interesting for device applications in opto-electronics where the gate electrode and gate oxide could be replaced by the semiconductor surface.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Gating geometry studies of thin-walled 17-4PH investment castings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire, M.C.; Zanner, F.J.

1992-11-01

The ability to design gating systems that reliably feed and support investment castings is often the result of ``cut-and-try`` methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channelmore » thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.« less

Gating geometry studies of thin-walled 17-4PH investment castings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire, M.C.; Zanner, F.J.

1992-01-01

The ability to design gating systems that reliably feed and support investment castings is often the result of cut-and-try'' methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channelmore » thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.« less

Solution processable semiconductor thin films: Correlation between morphological, structural, optical and charge transport properties

NASA Astrophysics Data System (ADS)

Isik, Dilek

This Ph.D. thesis is a result of multidisciplinary research bringing together fundamental concepts in thin film engineering, materials science, materials processing and characterization, electrochemistry, microfabrication, and device physics. Experiments were conducted by tackling scientific problems in the field of thin films and interfaces, with the aim to correlate the morphology, crystalline structure, electronic structure of thin films with the functional properties of the films and the performances of electronic devices based thereon. Furthermore, novel strategies based on interfacial phenomena at electrolyte/thin film interfaces were explored and exploited to control the electrical conductivity of the thin films. Three main chemical systems were the object of the studies performed during this Ph.D., two types of organic semiconductors (azomethine-based oligomers and polymers and soluble pentacene derivatives) and one metal oxide semiconductor (tungsten trioxide, WO3). To explore the morphological properties of the thin films, atomic force microscopy was employed. The morphological properties were further investigated by hyperspectral fluorescence microscopy and tentatively correlated to the charge transport properties of the films. X-ray diffraction (Grazing incidence XRD, GIXRD) was used to investigate the crystallinity of the film and the effect of the heat treatment on such crystallinity, as well as to understand the molecular arrangement of the organic molecules in the thin film. The charge transport properties of the films were evaluated in thin film transistor configuration. For electrolyte gated thin film transistors, time dependent transient measurements were conducted, in parallel to more conventional transistor characterizations, to explore the specific effects played on the gating by the anion and cation constituting the electrolyte. The capacitances of the electrical double layers at the electrolyte/WO3 interface were obtained from electrochemical impedance spectroscopy. In the context of ARTICLE 1, thin film transistors based on soluble pentacene derivatives (prepared by the research group directed by Professor J. Anthony, at the University of Kentucky) were fabricated and characterized. GIXRD results performed on the thin films suggested a molecular arrangement favorable to charge transport in the source-drain direction, with the pi-pi stacking direction perpendicular to the channel. In ARTICLE 1, HMDS-treated SiO 2 substrates were used, to improve the surface coverage and to limit charge trapping at the dielectric surface. AFM showed good film coverage. The transistors showed ambipolar characteristics, attributed to the good matching between Au electrode work function and highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) of the pentacene derivative. The work reported in ARTICLE 2 deals with pi-conjugated thiopheno-azomethines (both in oligomer and polymer form) and oligothiophene analogues. In the former case, couplings in the polymer are based on azomethine (-N=C-) moieties whereas in the latter case they are based on more conventional protocols (-C=C-). The effect of the coupling protocols on the corresponding thin film transistors behavior was studied. The key conclusion of this study was that thiopheno-azomethines thin films can be effectively incorporated into organic transistors: thin films of oligothiopheno-azomethines and the oligothiophenes exhibit p-type behavior whereas thin films of polythiopheno-azomethine exhibit an ambipolar behavior. The hole mobility of the heat-treated thin films of oligothiopheno-azomethines was three orders of magnitude higher compared to its oligothiophene analogue. AFM, coupled with hyperspectral fluorescence imaging, were used to investigate the micro- and nano-scale surface coverage. For the oligothiopheno-azomethine we were able to quantitatively deduce the surface coverage. To contribute to the exploration of innovative strategies for low power consuming solution based electronics and capitalizing on the expertise of the group in the synthesis of solution deposited WO3 films the electrolyte gating approach was explored in ARTICLE 3. Ionic liquids, that are molten salts at room temperature, were employed as the electrolyte. Ionic liquids are attractive for their low volatility, non-flammability, ionic conductivity and thermal and electrochemical stability. Thin films of WO3 were deposited onto pre-patterned ITO substrates (source-drain interelectrode distance, 1 mm) prepared by wet chemical etching. SEM and AFM showed an interconnected film nanostructure. Electrolyte gated WO3 thin film transistors making use of 1-butyl-3-methyl imidazolium bis(trifluoromethylsulfonyl)imide ([BMIM][TFSI]), 1-butyl-3-methyl imidazolium hexafluoro phosphate ([BMIM][PF6]), and 1-ethyl-3-methyl imidazolium bis(trifluoromethylsulfonyl)imide ([EMIM][TFSI]) showed an n-type transistor behavior. The possibility to obtain WO3 electrolyte gated transistors represents an opportunity to fabricate electronic devices working at relatively low operating voltages (about 1 V) by using simple fabrication techniques.

Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

NASA Astrophysics Data System (ADS)

Fan, Wei

To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers, compared with pure TiO2. A modified 3-element model was adopted to extract the true C-V behavior of the TiAlOx-based MOS capacitor. Extremely small equivalent oxide thickness (EOT) less than 0.5 nm with dielectric leakage 4˜5 magnitude lower than that for SiO2 has been achieved on TiAlOx layer as a result of its excellent dielectric properties.

Flexible CMOS-Like Circuits Based on Printed P-Type and N-Type Carbon Nanotube Thin-Film Transistors.

PubMed

Zhang, Xiang; Zhao, Jianwen; Dou, Junyan; Tange, Masayoshi; Xu, Weiwei; Mo, Lixin; Xie, Jianjun; Xu, Wenya; Ma, Changqi; Okazaki, Toshiya; Cui, Zheng

2016-09-01

P-type and n-type top-gate carbon nanotube thin-film transistors (TFTs) can be selectively and simultaneously fabricated on the same polyethylene terephthalate (PET) substrate by tuning the types of polymer-sorted semiconducting single-walled carbon nanotube (sc-SWCNT) inks, along with low temperature growth of HfO 2 thin films as shared dielectric layers. Both the p-type and n-type TFTs show good electrical properties with on/off ratio of ≈10 5 , mobility of ≈15 cm 2 V -1 s -1 , and small hysteresis. Complementary metal oxide semiconductor (CMOS)-like logic gates and circuits based on as-prepared p-type and n-type TFTs have been achieved. Flexible CMOS-like inverters exhibit large noise margin of 84% at low voltage (1/2 V dd = 1.5 V) and maximum voltage gain of 30 at V dd of 1.5 V and low power consumption of 0.1 μW. Both of the noise margin and voltage gain are one of the best values reported for flexible CMOS-like inverters at V dd less than 2 V. The printed CMOS-like inverters work well at 10 kHz with 2% voltage loss and delay time of ≈15 μs. A 3-stage ring oscillator has also been demonstrated on PET substrates and the oscillation frequency of 3.3 kHz at V dd of 1 V is achieved. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Heterogeneous integration of low-temperature metal-oxide TFTs

NASA Astrophysics Data System (ADS)

Schuette, Michael L.; Green, Andrew J.; Leedy, Kevin D.; McCandless, Jonathan P.; Jessen, Gregg H.

2017-02-01

The breadth of circuit fabrication opportunities enabled by metal-oxide thin-film transistors (MO-TFTs) is unprecedented. Large-area deposition techniques and high electron mobility are behind their adoption in the display industry, and substrate agnosticism and low process temperatures enabled the present wave of flexible electronics research. Reports of circuits involving complementaryMO-TFTs, oxide-organic hybrid combinations, and even MO-TFTs integrated onto Si LSI back end of line interconnects demonstrate this technology's utility in 2D and 3D monolithic heterogeneous integration (HI). In addition to a brief literature review focused on functional HI between MO-TFTs and a variety of dissimilar active devices, we share progress toward integrating MO-TFTs with compound semiconductor devices, namely GaN HEMTs. A monolithically integrated cascode topology was used to couple a HEMT's >200 V breakdown characteristic with the gate driving characteristic of an IGZO TFT, effectively shifting the HEMT threshold voltage from -3 V to +1 V.

Solution-processed zinc oxide nanoparticles/single-walled carbon nanotubes hybrid thin-film transistors

NASA Astrophysics Data System (ADS)

Liu, Fangmei; Sun, Jia; Qian, Chuan; Hu, Xiaotao; Wu, Han; Huang, Yulan; Yang, Junliang

2016-09-01

Solution-processed thin-film transistors (TFTs) are the essential building blocks for manufacturing the low-cost and large-area consumptive electronics. Herein, solution-processed TFTs based on the composites of zinc oxide (ZnO) nanoparticles and single-walled carbon nanotubes (SWCNTs) were fabricated by the methods of spin-coating and doctor-blading. Through controlling the weight of SWCNTs, the ZnO/SWCNTs TFTs fabricated by spin-coating demonstrated a field-effect mobility of 4.7 cm2/Vs and a low threshold voltage of 0.8 V, while the TFTs devices fabricated by doctor-blading technique showed reasonable electrical performance with a mobility of 0.22 cm2/Vs. Furthermore, the ion-gel was used as an efficient electrochemical gate dielectric because of its large electric double-layer capacitance. The operating voltage of all the TFTs devices is as low as 4.0 V. The research suggests that ZnO/SWCNTs TFTs have the potential applications in low-cost, large-area and flexible consumptive electronics, such as chemical-biological sensors and smart label.

Fabrication of Zinc Oxide-Based Thin-Film Transistors by Radio Frequency Sputtering for Ultraviolet Sensing Applications.

PubMed

Hsu, Ming-Hung; Chang, Sheng-Po; Chang, Shoou-Jinn; Li, Chih-Wei; Li, Jyun-Yi; Lin, Chih-Chien

2018-05-01

In this study, zinc indium tin oxide thin-film transistors (ZITO TFTs) were fabricated by the radio frequency (RF) sputtering deposition method. Adding indium cations to ZnO by co-sputtering allows the development of ZITO TFTs with improved performance. Material characterization revealed that ZITO TFTs have a threshold voltage of 0.9 V, a subthreshold swing of 0.294 V/decade, a field-effect mobility of 5.32 cm2/Vs, and an on-off ratio of 4.7 × 105. Furthermore, an investigation of the photosensitivity of the fabricated devices was conducted by an illumination test. The responsivity of ZITO TFTs was 26 mA/W, with 330-nm illumination and a gate bias of -1 V. The UV-to-visible rejection ratio for ZITO TFTs was 2706. ZITO TFTs were observed to have greater UV light sensitivity than that of ZnO TFTs. We believe that these results suggest a significant step toward achieving high photosensitivity. In addition, the ZITO semiconductor system could be a promising candidate for use in high performance transparent TFTs, as well as further sensing applications.

Conduction mechanism of leakage current due to the traps in ZrO2 thin film

NASA Astrophysics Data System (ADS)

Seo, Yohan; Lee, Sangyouk; An, Ilsin; Song, Chulgi; Jeong, Heejun

2009-11-01

In this work, a metal-oxide-semiconductor capacitor with zirconium oxide (ZrO2) gate dielectric was fabricated by an atomic layer deposition (ALD) technique and the leakage current characteristics under negative bias were studied. From the result of current-voltage curves there are two possible conduction mechanisms to explain the leakage current in the ZrO2 thin film. The dominant mechanism is the space charge limited conduction in the high-electric field region (1.5-5.0 MV cm-1) while the trap-assisted tunneling due to the existence of traps is prevailed in the low-electric field region (0.8-1.5 MV cm-1). Conduction caused by the trap-assisted tunneling is found from the experimental results of a weak temperature dependence of current, and the trap barrier height is obtained. The space charge limited conduction is evidenced, for different temperatures, by Child's law dependence of current density versus voltage. Child's law dependence can be explained by considering a single discrete trapping level and we can obtain the activation energy of 0.22 eV.

Effects of various oxygen partial pressures on Ti-doped ZnO thin film transistors fabricated on flexible plastic substrate

NASA Astrophysics Data System (ADS)

Cui, Guodong; Han, Dedong; Yu, Wen; Shi, Pan; Zhang, Yi; Huang, Lingling; Cong, Yingying; Zhou, Xiaoliang; Zhang, Xiaomi; Zhang, Shengdong; Zhang, Xing; Wang, Yi

2016-04-01

By applying a novel active layer of titanium zinc oxide (TiZO), we have successfully fabricated fully transparent thin-film transistors (TFTs) with a bottom gate structure fabricated on a flexible plastic substrate at low temperatures. The effects of various oxygen partial pressures during channel deposition were studied to improve the device performance. We found that the oxygen partial pressure during channel deposition has a significant impact on the performance of TiZO TFTs, and that the TFT developed under 10% oxygen partial pressure exhibits superior performance with a low threshold voltage (V th) of 2.37 V, a high saturation mobility (μsat) of 125.4 cm2 V-1 s-1, a steep subthreshold swing (SS) of 195 mV/decade and a high I on/I off ratio of 3.05 × 108. These results suggest that TiZO thin films are promising for high-performance fully transparent flexible TFTs and displays.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition.

PubMed

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-12-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al 2 O 3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a , which can explain the experimental observation. A high-field effect mobility of 9.4 cm 2 /Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 10 7 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

The Influence of Hafnium Doping on Density of States in Zinc Oxide Thin-Film Transistors Deposited via Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Ding, Xingwei; Qin, Cunping; Song, Jiantao; Zhang, Jianhua; Jiang, Xueyin; Zhang, Zhilin

2017-01-01

Thin-film transistors (TFTs) with atomic layer deposition (ALD) HfZnO (HZO) as channel layer and Al2O3 as gate insulator were successfully fabricated. Compared with ZnO-TFT, the stability of HZO-TFT was obviously improved as Hf doping can suppress the generation of oxygen related defects. The transfer characteristics of TFTs at different temperatures were also investigated, and temperature stability enhancement was observed for the TFT with Hf doping. The density of states (DOS) was calculated based on the experimentally obtained E a, which can explain the experimental observation. A high-field effect mobility of 9.4 cm2/Vs, a suitable turn-on voltage of 0.26 V, a high on/off ratio of over 107 and a steep sub-threshold swing of 0.3 V/decade were obtained in HZO-TFT. The results showed that temperature stability enhancement in HfZnO thin-film transistors are attributed to the smaller DOS.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

PubMed

Lee, Han Sol; Choi, Kyunghee; Kim, Jin Sung; Yu, Sanghyuck; Ko, Kyeong Rok; Im, Seongil

2017-05-10

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe 2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 10 4 . Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

An LOD with improved breakdown voltage in full-frame CCD devices

NASA Astrophysics Data System (ADS)

Banghart, Edmund K.; Stevens, Eric G.; Doan, Hung Q.; Shepherd, John P.; Meisenzahl, Eric J.

2005-02-01

In full-frame image sensors, lateral overflow drain (LOD) structures are typically formed along the vertical CCD shift registers to provide a means for preventing charge blooming in the imager pixels. In a conventional LOD structure, the n-type LOD implant is made through the thin gate dielectric stack in the device active area and adjacent to the thick field oxidation that isolates the vertical CCD columns of the imager. In this paper, a novel LOD structure is described in which the n-type LOD impurities are placed directly under the field oxidation and are, therefore, electrically isolated from the gate electrodes. By reducing the electrical fields that cause breakdown at the silicon surface, this new structure permits a larger amount of n-type impurities to be implanted for the purpose of increasing the LOD conductivity. As a consequence of the improved conductance, the LOD width can be significantly reduced, enabling the design of higher resolution imaging arrays without sacrificing charge capacity in the pixels. Numerical simulations with MEDICI of the LOD leakage current are presented that identify the breakdown mechanism, while three-dimensional solutions to Poisson's equation are used to determine the charge capacity as a function of pixel dimension.

Efficient Multi-Dimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Ancona, Mario G.; Rafferty, Conor S.; Yu, Zhiping

2000-01-01

We investigate the density-gradient (DG) transport model for efficient multi-dimensional simulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction ot the classical drift-diffusion model. Quantum confinement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capacitors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum confinement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-gradient model, and short channel effects (in particular, drain-induced barrier lowering) are noticeably increased.

A Direct Method to Extract Transient Sub-Gap Density of State (DOS) Based on Dual Gate Pulse Spectroscopy

NASA Astrophysics Data System (ADS)

Dai, Mingzhi; Khan, Karim; Zhang, Shengnan; Jiang, Kemin; Zhang, Xingye; Wang, Weiliang; Liang, Lingyan; Cao, Hongtao; Wang, Pengjun; Wang, Peng; Miao, Lijing; Qin, Haiming; Jiang, Jun; Xue, Lixin; Chu, Junhao

2016-06-01

Sub-gap density of states (DOS) is a key parameter to impact the electrical characteristics of semiconductor materials-based transistors in integrated circuits. Previously, spectroscopy methodologies for DOS extractions include the static methods, temperature dependent spectroscopy and photonic spectroscopy. However, they might involve lots of assumptions, calculations, temperature or optical impacts into the intrinsic distribution of DOS along the bandgap of the materials. A direct and simpler method is developed to extract the DOS distribution from amorphous oxide-based thin-film transistors (TFTs) based on Dual gate pulse spectroscopy (GPS), introducing less extrinsic factors such as temperature and laborious numerical mathematical analysis than conventional methods. From this direct measurement, the sub-gap DOS distribution shows a peak value on the band-gap edge and in the order of 1017-1021/(cm3·eV), which is consistent with the previous results. The results could be described with the model involving both Gaussian and exponential components. This tool is useful as a diagnostics for the electrical properties of oxide materials and this study will benefit their modeling and improvement of the electrical properties and thus broaden their applications.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors

NASA Astrophysics Data System (ADS)

Krishnan, Anand Thiruvengadathan

2000-10-01

The proliferation of devices with built-in displays, such as personal digital assistants and cellular phones has created a demand for rugged light-weight displays. Polymeric substrates could be suited for these applications, and they offer the possibility of flexible displays also. However, driver circuitry needs to be integrated in the display if the cost is to be reduced. Low temperature (<350°C) polycrystalline silicon (poly-Si) thin film transistors, if developed, offer driver circuitry integration during pixel transistor fabrication on top of flexible substrates. This thesis addresses several issues related to the fabrication of thin film transistors at low temperatures on glass substrates. A high-density plasma (electron cyclotron resonance (ECR)) based approach was adopted for deposition of thin films. A process for deposition of n-type doped silicon (n-type doped Si) at T < 350°C and having resistivity <1 ohm/cm has been developed. Intrinsic poly-Si was deposited under different conditions of microwave power, RF bias and deposition times. The properties of n-type doped Si and intrinsic poly-Si were correlated with the structure and the deposition conditions. A novel TFT structure has been proposed and implemented in this work. This top gate TFT structure uses n-type doped Si and utilizes only two masks and one alignment step. There are no critical etch steps and good interface quality could be obtained even without post-processing hydrogenation as the poly-Si surface was not exposed to air before deposition of the gate dielectric. TFTs using this top gate structure were fabricated with no process step exceeding 340°C electrode temperature (surface temperature <300°C). These TFTs show ON/OFF ratios in excess of 105. Their sub-threshold swing is ˜0.5 V/decade and mobility is 1--10 cm2/V-s. Several TFTs were also fabricated using alternative dielectrics such as oxide deposited from tetramethyl silane in an RFPECVD chamber and silicon nitride deposited in the ECR and these TFTs also show reasonable device characteristics. TFTs processed using this high-density plasma based approach show great potential for use in applications such as driver circuitry integration on low temperature substrates.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Real-time photoelectron spectroscopy study of the oxidation reaction kinetics on p-type and n-type Si (001) surfaces

NASA Astrophysics Data System (ADS)

Yu, Zhou

Silicon oxides thermally grown on Si surface are the core gate materials of metal-oxide-semiconductor field effect transistor (MOSFET). This thin oxide layer insulates the gate terminals and the transistors substrate which make MOSFET has certain advantages over those conventional junctions, such as field-effect transistor (FET) and junction field effect transistor (JFET). With an oxide insulating layer, MOSFET is able to sustain higher input impedance and the corresponding gate leakage current can be minimized. Today, though the oxidation process on Si substrate is popular in industry, there are still some uncertainties about its oxidation kinetics. On a path to clarify and modeling the oxidation kinetics, a study of initial oxidation kinetics on Si (001) surface has attracted attentions due to having a relatively low surface electron density and few adsorption channels compared with other Si surface direction. Based on previous studies, there are two oxidation models of Si (001) that extensively accepted, which are dual oxide species mode and autocatalytic reaction model. These models suggest the oxidation kinetics on Si (001) mainly relies on the metastable oxygen atom on the surface and the kinetic is temperature dependent. Professor Yuji Takakuwa's group, Surface Physics laboratory, Institute of Multidisciplinary Research for Advanced Materials, Tohoku University, observed surface strain existed during the oxidation kinetics on Si (001) and this is the first time that strain was discovered during Si oxidation. Therefore, it is necessary to explain where the strain comes from since none of previous model research included the surface strain (defects generation) into considerations. Moreover, recent developing of complementary metal-oxide-semiconductor (CMOS) requires a simultaneous oxidation process on p- and n-type Si substrate. However, none of those previous models included the dopant factor into the oxidation kinetic modeling. All of these points that further work is necessary to update and modify the traditional Si (001) oxidation models that had been accepted for several decades. To update and complement the Si (001) oxidation kinetics, an understanding of the temperature and dopant factor during initial oxidation kinetics on Si (001) is our first step. In this study, real-time photoelectron spectroscopy is applied to characterize the oxidized (001) surface and surface information was collected by ultraviolet photoelectron spectroscopy technique. By analyzing parameters such as O 2p spectra uptake, change of work function and the surface state in respect of p- and n- type Si (001) substrate under different temperature, the oxygen adsorption structure and the dopant factor can be determined. In this study, experiments with temperature gradients on p-type Si (001) were conducted and this aims to clarify the temperature dependent characteristic of Si (001) surface oxidation. A comparison of the O 2p uptake, change of work function and surface state between p-and n-type Si (001) is made under a normal temperature and these provides with the data to explain how the dopant factor impacts the oxygen adsorption structure on the surface. In the future, the study of the oxygen adsorption structure will lead to an explanation of the surface strain that discovered; therefore, fundamental of the initial oxidation on Si (001) would be updated and complemented, which would contribute to the future gate technology in MOSFET and CMOS.

Improvement of the GaSb/Al2O3 interface using a thin InAs surface layer

NASA Astrophysics Data System (ADS)

Greene, Andrew; Madisetti, Shailesh; Nagaiah, Padmaja; Yakimov, Michael; Tokranov, Vadim; Moore, Richard; Oktyabrsky, Serge

2012-12-01

The highly reactive GaSb surface was passivated with a thin InAs layer to limit interface trap state density (Dit) at the III-V/high-k oxide interface. This InAs surface was subjected to various cleaning processes to effectively reduce native oxides before atomic layer deposition (ALD). Ammonium sulfide pre-cleaning and trimethylaluminum/water ALD were used in conjunction to provide a clean interface and annealing in forming gas (FG) at 350 °C resulted in an optimized fabrication for n-GaSb/InAs/high-k gate stacks. Interface trap density, Dit ≈ 2-3 × 1012 cm-2eV-1 resided near the n-GaSb conductance band which was extracted and compared with three different methods. Conductance-voltage-frequency plots showed efficient Fermi level movement and a sub-threshold slope of 200 mV/dec. A composite high-k oxide process was also developed using ALD of Al2O3 and HfO2 resulting in a Dit ≈ 6-7 × 1012 cm-2eV-1. Subjecting these samples to a higher (450 °C) processing temperature results in increased oxidation and a thermally unstable interface. p-GaSb displayed very fast minority carrier generation/recombination likely due to a high density of bulk traps in GaSb.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors: II—Numerical modeling of dc characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

A numerical procedure to calculate the drain-current (ID) vs. gate-voltage (VG) characteristics from numerical solutions of the Poisson equation for organic Thin-Film Transistors (TFTs) is presented. Polaron transport is modeled as two-dimensional charge transport in a semiconductor having free-carrier density of states proportional to the density of molecules and traps with energy equal to the polaron-hopping barrier. The simulated ID-VG curves are proportional to the product of the density of free carriers, calculated as a function of VG, and the intrinsic mobility, assumed to be a constant independent of temperature. The presence of traps in the oxide was also taken into account in the model, which was applied to a TFT made with six monolayers of pentacene grown on an oxide substrate. The polaron-hopping barrier determines the temperature dependence of the simulated ID-VG curves, trapping in the oxide is responsible for current reduction at high bias and the slope of the characteristics near threshold is related to the metal-semiconductor work-function difference. The values of the model parameters yielding the best match between calculations and experiments are consistent with previous experimental results and theoretical predictions. Therefore, this model enables to extract both physical and technological properties of thin-film devices from the temperature-dependent dc characteristics.

Looking for Speed!! Go Optical Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin; Frazier, Donald O.; Penn, Benjamin; Paley, Mark S.

2003-01-01

Recently, we developed two ultra-fast all-optical switches in the nanosecond and picosecond regimes. The picosecond switch is made of a polydiacetylene thin film coated on the interior wall of a hollow capillary of approximately 50 micron diameter by a photo-polymerization process. In the setup a picosecond Nd:YAG laser at 10 Hz and at 532 nm with a pulse duration of approximately 40 ps was sent collinearly along a cw He-Ne laser beam and both were waveguided through the hollow capillary. The setup functioned as an Exclusive OR gate. On the other hand, the material used in the nanosecond switch is a phthalocyanine thin film, deposited on a glass substrate by a vapor deposition technique. In the setup a nanosecond, 10 Hz, Nd:YAG laser of 8 ns pulse duration was sent collinearly along a cw He-Ne laser beam and both were wave-guided through the phthalocyanine thin film. The setup in this case functioned as an all-optical AND logic gate. The characteristic table of the ExOR gate in polydiacetylene film was attributed to an excited state absorption process, while that of the AND gate was attributed to a saturation process of the first excited state. Both mechanisms were thoroughly investigated theoretically and found to agree remarkably well with the experimental results. An all-optical inverter gate has been designed but has not yet been demonstrated. The combination of all these three gates form the foundation for building all the necessary gates needed to build a prototype of an all-optical system.

Hafnium germanosilicate thin films for gate and capacitor dielectric applications: thermal stability studies

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

The use of SiO_2-GeO2 mixtures in gate and capacitor dielectric applications is hampered by the inherent thermodynamic instability of germanium oxide. Studies to date have confirmed that germanium oxide is readily converted to elemental germanium [1,2]. In sharp contrast, germanium oxide is known to form stable compounds with transition metal oxides such as hafnium oxide (hafnium germanate, HfGeO_4) [3]. Thus, the incorporation of hafnium in SiO_2-GeO2 may be expected to enhance the thermal stability of germanium oxide via Hf-O-Ge bond formation. In addition, the introduction of a transition metal would simultaneously enhance the capacitance of the dielectric thereby permitting a thicker dielectric which reduces leakage current [4]. In this study, the thermal stability of PVD-grown hafnium germanosilicate (HfGeSiO) films was investigated. XPS, HR-TEM, C-V and I-V results of films after deposition and subsequent annealing treatments will be presented. The results indicate that the presence or formation of elemental germanium drastically affects the stability of the HfGeSiO films. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [2] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995) [3] P. M. Lambert, Inorganic Chemistry, 37, 1352 (1998) [4] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001)

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rajachidambaram, Meena Suhanya; Pandey, Archana; Vilayur Ganapathy, Subramanian

The role of back channel surface chemistry on amorphous zinc tin oxide (ZTO) bottom gate thin film transistors (TFT) have been characterized by positive bias-stress measurements and x-ray photoelectron spectroscopy. Positive bias-stress turn-on voltage shifts for ZTO-TFTs were significantly reduced by passivation of back channel surfaces with self-assembled monolayers of n-hexylphosphonic acid (n-HPA) when compared to ZTO-TFTs with no passivation. These results indicate that adsorption of molecular species on exposed back channel of ZTO-TFTs strongly influence observed turn-on voltage shifts, as opposed to charge injection into the dielectric or trapping due to oxygen vacancies.

Low-damage high-throughput grazing-angle sputter deposition on graphene

NASA Astrophysics Data System (ADS)

Chen, C.-T.; Casu, E. A.; Gajek, M.; Raoux, S.

2013-07-01

Despite the prevalence of sputter deposition in the microelectronics industry, it has seen very limited applications for graphene electronics. In this letter, we report systematic investigation of the sputtering induced damages in graphene and identify the energetic sputtering gas neutrals as the primary cause of graphene disorder. We further demonstrate a grazing-incidence sputtering configuration that strongly suppresses fast neutral bombardment and retains graphene structure integrity, creating considerably lower damage than electron-beam evaporation. Such sputtering technique yields fully covered, smooth thin dielectric films, highlighting its potential for contact metals, gate oxides, and tunnel barriers fabrication in graphene device applications.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Low-temperature electron cyclotron resonance plasma-enhanced chemical-vapor deposition silicon dioxide as gate insulator for polycrystalline silicon thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maiolo, L.; Pecora, A.; Fortunato, G.

2006-03-15

Silicon dioxide films have been deposited at temperatures below 270 deg. C in an electron cyclotron resonance (ECR) plasma reactor from O{sub 2}, SiH{sub 4}, and He gas mixture. Pinhole density analysis as a function of substrate temperature for different microwave powers was carried out. Films deposited at higher microwave power and at room temperature show defect densities (<7 pinhole/mm{sup 2}), ensuring low-temperature process integration on large area. From Fourier transform infrared analysis and thermal desorption spectrometry we also evaluated very low hydrogen content if compared to conventional rf-plasma-enhanced chemical-vapor-deposited (PECVD) SiO{sub 2} deposited at 350 deg. C. Electrical propertiesmore » have been measured in metal-oxide-semiconductor (MOS) capacitors, depositing SiO{sub 2} at RT as gate dielectric; breakdown electric fields >10 MV/cm and charge trapping at fields >6 MV/cm have been evaluated. From the study of interface quality in MOS capacitors, we found that even for low annealing temperature (200 deg. C), it is possible to considerably reduce the interface state density down to 5x10{sup 11} cm{sup -2} eV{sup -1}. To fully validate the ECR-PECVD silicon dioxide we fabricated polycrystalline silicon thin-film transistors using RT-deposited SiO{sub 2} as gate insulator. Different postdeposition thermal treatments have been studied and good device characteristics were obtained even for annealing temperature as low as 200 deg. C.« less

Lanthanum aluminum oxide thin-film dielectrics from aqueous solution.

PubMed

Plassmeyer, Paul N; Archila, Kevin; Wager, John F; Page, Catherine J

2015-01-28

Amorphous LaAlO3 dielectric thin films were fabricated via solution processing from inorganic nitrate precursors. Precursor solutions contained soluble oligomeric metal-hydroxyl and/or -oxo species as evidenced by dynamic light scattering (DLS) and Raman spectroscopy. Thin-film formation was characterized as a function of annealing temperature using Fourier transform infrared (FTIR), X-ray diffraction (XRD), X-ray reflectivity (XRR), scanning electron microscopy (SEM), and an array of electrical measurements. Annealing temperatures ≥500 °C result in thin films with low leakage-current densities (∼1 × 10(-8) A·cm(-2)) and dielectric constants ranging from 11.0 to 11.5. When incorporated as the gate dielectric layer in a-IGZO thin-film transistors (TFTs), LaAlO3 thin films annealed at 600 °C in air yielded TFTs with relatively low average mobilities (∼4.5 cm(2)·V(-1)·s(-1)) and high turn-on voltages (∼26 V). Interestingly, reannealing the LaAlO3 in 5%H2/95%N2 at 300 °C before deposition of a-IGZO channel layers resulted in TFTs with increased average mobilities (11.1 cm(2)·V(-1)·s(-1)) and lower turn-on voltages (∼6 V).

Printed indium gallium zinc oxide transistors. Self-assembled nanodielectric effects on low-temperature combustion growth and carrier mobility.

PubMed

Everaerts, Ken; Zeng, Li; Hennek, Jonathan W; Camacho, Diana I; Jariwala, Deep; Bedzyk, Michael J; Hersam, Mark C; Marks, Tobin J

2013-11-27

Solution-processed amorphous oxide semiconductors (AOSs) are emerging as important electronic materials for displays and transparent electronics. We report here on the fabrication, microstructure, and performance characteristics of inkjet-printed, low-temperature combustion-processed, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) grown on solution-processed hafnia self-assembled nanodielectrics (Hf-SANDs). TFT performance for devices processed below 300 °C includes >4× enhancement in electron mobility (μFE) on Hf-SAND versus SiO2 or ALD-HfO2 gate dielectrics, while other metrics such as subthreshold swing (SS), current on:off ratio (ION:IOFF), threshold voltage (Vth), and gate leakage current (Ig) are unchanged or enhanced. Thus, low voltage IGZO/SAND TFT operation (<2 V) is possible with ION:IOFF = 10(7), SS = 125 mV/dec, near-zero Vth, and large electron mobility, μFE(avg) = 20.6 ± 4.3 cm(2) V(-1) s(-1), μFE(max) = 50 cm(2) V(-1) s(-1). Furthermore, X-ray diffraction analysis indicates that the 300 °C IGZO combustion processing leaves the underlying Hf-SAND microstructure and capacitance intact. This work establishes the compatibility and advantages of all-solution, low-temperature fabrication of inkjet-printed, combustion-derived high-mobility IGZO TFTs integrated with self-assembled hybrid organic-inorganic nanodielectrics.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Solution-processed lithium-doped zinc oxide thin-film transistors at low temperatures between 100 and 300 °C

NASA Astrophysics Data System (ADS)

Liu, Fangmei; Qian, Chuan; Sun, Jia; Liu, Peng; Huang, Yulan; Gao, Yongli; Yang, Junliang

2016-04-01

Lithium-doped zinc oxide (Li-ZnO) thin-film transistors (TFTs) were fabricated by solution process at the low temperatures ranged from 100 to 300 °C. Li-ZnO TFTs fabricated at 300 °C under nitrogen condition showed a mobility of 1.2 cm2/Vs. Most importantly, the mobility of Li-ZnO TFT devices fabricated at 100 °C could be increased significantly from 0.08 to 0.4 cm2/Vs by using double spin-coated and UV irradiation-treated Li-ZnO film, and the on-/off-current ratio is in the order of 106. Notably, the XPS analyses proved that the performance improvement was originated from the chemical composition or stoichiometry evolution, in which the hydroxide was converted into metal oxide and accelerated the formation of the oxygen vacancies. Furthermore, low-voltage operating Li-ZnO TFTs were demonstrated by using a high-capacitance ion gel gate dielectrics. The Li-ZnO TFTs with an operating voltage as low as 2 V exhibited the carrier mobilities of 2.1 and 0.65 cm2/Vs for the devices treated at 300 and 100 °C, respectively. The low-temperature, solution-processed Li-ZnO TFTs showed greatly potential applications in flexible displays, smart label, and sensors.

Low-Concentration Indium Doping in Solution-Processed Zinc Oxide Films for Thin-Film Transistors.

PubMed

Zhang, Xue; Lee, Hyeonju; Kwon, Jung-Hyok; Kim, Eui-Jik; Park, Jaehoon

2017-07-31

We investigated the influence of low-concentration indium (In) doping on the chemical and structural properties of solution-processed zinc oxide (ZnO) films and the electrical characteristics of bottom-gate/top-contact In-doped ZnO thin-film transistors (TFTs). The thermogravimetry and differential scanning calorimetry analysis results showed that thermal annealing at 400 °C for 40 min produces In-doped ZnO films. As the In content of ZnO films was increased from 1% to 9%, the metal-oxygen bonding increased from 5.56% to 71.33%, while the metal-hydroxyl bonding decreased from 72.03% to 9.63%. The X-ray diffraction peaks and field-emission scanning microscope images of the ZnO films with different In concentrations revealed a better crystalline quality and reduced grain size of the solution-processed ZnO thin films. The thickness of the In-doped ZnO films also increased when the In content was increased up to 5%; however, the thickness decreased on further increasing the In content. The field-effect mobility and on/off current ratio of In-doped ZnO TFTs were notably affected by any change in the In concentration. Considering the overall TFT performance, the optimal In doping concentration in the solution-processed ZnO semiconductor was determined to be 5% in this study. These results suggest that low-concentration In incorporation is crucial for modulating the morphological characteristics of solution-processed ZnO thin films and the TFT performance.

Low-Concentration Indium Doping in Solution-Processed Zinc Oxide Films for Thin-Film Transistors

PubMed Central

Zhang, Xue; Lee, Hyeonju; Kim, Eui-Jik; Park, Jaehoon

2017-01-01

We investigated the influence of low-concentration indium (In) doping on the chemical and structural properties of solution-processed zinc oxide (ZnO) films and the electrical characteristics of bottom-gate/top-contact In-doped ZnO thin-film transistors (TFTs). The thermogravimetry and differential scanning calorimetry analysis results showed that thermal annealing at 400 °C for 40 min produces In-doped ZnO films. As the In content of ZnO films was increased from 1% to 9%, the metal-oxygen bonding increased from 5.56% to 71.33%, while the metal-hydroxyl bonding decreased from 72.03% to 9.63%. The X-ray diffraction peaks and field-emission scanning microscope images of the ZnO films with different In concentrations revealed a better crystalline quality and reduced grain size of the solution-processed ZnO thin films. The thickness of the In-doped ZnO films also increased when the In content was increased up to 5%; however, the thickness decreased on further increasing the In content. The field-effect mobility and on/off current ratio of In-doped ZnO TFTs were notably affected by any change in the In concentration. Considering the overall TFT performance, the optimal In doping concentration in the solution-processed ZnO semiconductor was determined to be 5% in this study. These results suggest that low-concentration In incorporation is crucial for modulating the morphological characteristics of solution-processed ZnO thin films and the TFT performance. PMID:28773242

A study of trap-limited conduction influenced by plasma damage on the source/drain regions of amorphous InGaZnO TFTs

NASA Astrophysics Data System (ADS)

Hsu, Chih-Chieh; Sun, Jhen-Kai; Wu, Chien-Hsun

2015-11-01

This study investigated electrical characteristics and stability variations of amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) with plasma damage on their source/drain (S/D) regions. The influence of the plasma damage on the TFT performance is absent as the channel length is 36-100 μm. When the channel length is decreased to 3-5 μm, the mobility (μ ) of the bottom gate TFT (BG TFT) with plasma damage is significantly degraded to 0.6 cm2 (V s)-1, which is much lower than 4.3 cm2 (V s)-1 of a damage-free BG TFT. We utilized the TFT passivation layer and the indium tin oxide (ITO), which was used as the pixel electrode material in the TFT backplane, to be the top gate insulator and top gate electrode of the defective BG TFT to obtain the defective dual-gate TFT. The mobility can be restored to 5.1 cm2 (V s)-1. Additional process steps are not required. Besides, this method is easily implemented and is fully compatible with TFT backplane fabrication process. The transfer curves, hysteresis characteristics, stabilities under constant voltage stress and constant current stress tests were measured to give evidences that the traps created by the plasma damage on the S/D regions indeed can affect electron transport. This trap-limited conduction can be improved by using the top gate. It was proven that the top gate was not for contributing an observably additional current. It was for inducing electrons to electrically passivate the plasma-induced defects near the back channel. Thus, the trapping/detrapping of the electrons transporting in the front channel can be reduced. The trap density near the Fermi level, hopping distance and hopping energy are 1.1  ×  1018 cm-3 eV-1, 162 Å, and 52 meV for the BG TFT with plasma damage on the S/D regions.

Understanding the Structure of High-K Gate Oxides - Oral Presentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miranda, Andre

2015-08-25

Hafnium Oxide (HfO 2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO 2 thin films which hasn’t been done with the technique of this study. In this study, two HfO 2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer.more » Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO 2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO 2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO 2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.« less

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Influence of gating design on microstructure and fluidity of thin sections AA320.0 cast hypo-eutectic Al-Si alloy

NASA Astrophysics Data System (ADS)

Ramadan, Mohamed

2018-05-01

Influence of gating design especially number of ingrates on microstructure and fluidity of thin sections of 2, 4, 6 mm AA320.0 cast hypo-eutectic Al-Si alloy was evaluated for sand casting molding technique. Increasing the number of ingates improves the microstructe to be fine and more globular. About 87 μm of α-Al grain size, 0.6 α-Al grain sphericity and 37 μm dendrite arm spacing DAS are achieved by using 4 ingates in gating system. Increasing the number of ingates up to 3 increases hardness, filling area and related fluditiy of all cast samples. The minimum thickness of 2.5 mm for each ingate should be considered in order to successfully production of high quality light weight thin sections castings in sand mold.

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

DOEpatents

Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

2016-03-29

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Electric-field driven insulator-metal transition and tunable magnetoresistance in ZnO thin film

NASA Astrophysics Data System (ADS)

Zhang, Le; Chen, Shanshan; Chen, Xiangyang; Ye, Zhizhen; Zhu, Liping

2018-04-01

Electrical control of the multistate phase in semiconductors offers the promise of nonvolatile functionality in the future semiconductor spintronics. Here, by applying an external electric field, we have observed a gate-induced insulator-metal transition (MIT) with the temperature dependence of resistivity in ZnO thin films. Due to a high-density carrier accumulation, we have shown the ability to inverse change magnetoresistance in ZnO by ionic liquid gating from 10% to -2.5%. The evolution of photoluminescence under gate voltage was also consistent with the MIT, which is due to the reduction of dislocation. Our in-situ gate-controlled photoluminescence, insulator-metal transition, and the conversion of magnetoresistance open up opportunities in searching for quantum materials and ZnO based photoelectric devices.

High fluence swift heavy ion structure modification of the SiO2/Si interface and gate insulator in 65 nm MOSFETs

NASA Astrophysics Data System (ADS)

Ma, Yao; Gao, Bo; Gong, Min; Willis, Maureen; Yang, Zhimei; Guan, Mingyue; Li, Yun

2017-04-01

In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO2/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO2 and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

Enhancement of electrical transport modulation in epitaxial VO2 nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Tanaka, Hidekazu; Chikanari, Masashi; Kanki, Teruo

Strongly correlated system vanadium dioxide VO2 has attracted widespread concerns from researchers as an exciting electronic material, due to the many intriguing features, especially metal-insulator transition (MIT) in vicinity of room temperature. In this work, we report a diverse geometry for high sensitivity in the transport modulation. By taking advantage of nanometer scale channel, instead of thin film channels, we demonstrated the enhancement of resistance modulation by applying gate voltage. Also we designed the insulating gate, consisting of high-k material Ta2O5/organic polymer parylene-C hybrid insulator. Such as this hybrid gate dielectric would effectively reduce interface deterioration of active channel oxide and provide sufficient carrier density. Moreover, benefited from the nanometer scale channel, the VO2 nanowire-based transistor could deliver a resistance modulation ratio over 8.5%, which are about 10 folds higher than that of the film case. Furthermore, this result is explained that in spite of the stronger field distribution in the edge parts of VO2 nanowire channel yielded little carrier density, the generated mobility modulation would biquadratic increase according to Brinkman-Rice picture as new finding.

Multilayer ZnO/Pd/ZnO Structure as Sensing Membrane for Extended-Gate Field-Effect Transistor (EGFET) with High pH Sensitivity

NASA Astrophysics Data System (ADS)

Rasheed, Hiba S.; Ahmed, Naser M.; Matjafri, M. Z.; Al-Hardan, Naif H.; Almessiere, Munirah Abdullah; Sabah, Fayroz A.; Al-Hazeem, Nabeel Z.

2017-10-01

Metal oxide nanostructures have attracted considerable attention as pH-sensitive membranes because of their unique advantages. Specifically, the special properties of ZnO thin film, including high surface-to-volume ratio, nontoxicity, thermal stability, chemical stability, electrochemical activity, and high mechanical strength, have attracted massive interest. ZnO exhibits wide bandgap of 3.37 eV, good biocompatibility, high reactivity, robustness, and environmental stability. These unique properties explain why ZnO has the most applications among all nanostructured metal oxides based on its structure and properties. Moreover, ZnO has excellent electrical characteristics, enabling its use in accurate sensors with rapid response. ZnO nanostructures can be used in novel pH and biomedical sensing applications. However, ZnO thin film exhibits large sheet resistance and low conductivity. Increasing the conductivity or reducing the resistivity of ZnO sensing membranes is important to achieve low impedance. We propose herein a new design using a multilayer ZnO/Pd/ZnO structure as a pH-sensing membrane. Multiple layers were deposited by radio frequency (RF) sputtering for ZnO and direct current (DC) sputtering for Pd to achieve low sheet resistance. These multilayers with low sheet resistance of 15.8 Ω/sq were then successfully used to control the conductivity in extended-gate field-effect transistors (EGFETs). The resulting multilayered EGFET pH-sensor demonstrated improved sensing performance. The measured sensitivity of the pH sensor was 40 μA/pH and 52 mV/pH within the pH range from 2 to 12, rendering this structure suitable for use in various applications, including pH sensors and biosensors.

Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

PubMed

Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

2017-04-12

The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10 6 , effective mobility up to 30 cm 2 V -1 s -1 , small hysteresis, and small subthreshold swing (90-140 mV dec -1 ), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 V dd = 1 V) and a voltage gain as high as 30 (at V dd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at V dd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air.

PubMed

Esro, Mazran; Kolosov, Oleg; Jones, Peter J; Milne, William I; Adamopoulos, George

2017-01-11

Silicon dioxide (SiO 2 ) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO 2 by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO 2 thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl 4 . SiO 2 dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (R RMS < 1 nm) amorphous films with a dielectric constant of about 3.8, an optical band gap of ≈8.1 eV, leakage current densities in the order of ≈10 -7 A/cm 2 at 1 MV/cm, and high dielectric strength in excess of 5 MV/cm. XPS measurements confirm the SiO 2 stoichiometry and FTIR spectra reveal features related to SiO 2 only. Thin film transistors implementing spray-coated SiO 2 gate dielectrics and C 60 and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10 6 , and high carrier mobility.

Oxidative Modulation of Voltage-Gated Potassium Channels

PubMed Central

Sahoo, Nirakar; Hoshi, Toshinori

2014-01-01

Abstract Significance: Voltage-gated K+ channels are a large family of K+-selective ion channel protein complexes that open on membrane depolarization. These K+ channels are expressed in diverse tissues and their function is vital for numerous physiological processes, in particular of neurons and muscle cells. Potentially reversible oxidative regulation of voltage-gated K+ channels by reactive species such as reactive oxygen species (ROS) represents a contributing mechanism of normal cellular plasticity and may play important roles in diverse pathologies including neurodegenerative diseases. Recent Advances: Studies using various protocols of oxidative modification, site-directed mutagenesis, and structural and kinetic modeling provide a broader phenomenology and emerging mechanistic insights. Critical Issues: Physicochemical mechanisms of the functional consequences of oxidative modifications of voltage-gated K+ channels are only beginning to be revealed. In vivo documentation of oxidative modifications of specific amino-acid residues of various voltage-gated K+ channel proteins, including the target specificity issue, is largely absent. Future Directions: High-resolution chemical and proteomic analysis of ion channel proteins with respect to oxidative modification combined with ongoing studies on channel structure and function will provide a better understanding of how the function of voltage-gated K+ channels is tuned by ROS and the corresponding reducing enzymes to meet cellular needs. Antioxid. Redox Signal. 21, 933–952. PMID:24040918

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.

2001-06-11

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSGmore » oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. {copyright} 2001 American Institute of Physics.« less

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Electrostatic potential profiles of molecular conductors

NASA Astrophysics Data System (ADS)

Liang, G. C.; Ghosh, A. W.; Paulsson, M.; Datta, S.

2004-03-01

The electrostatic potential across a short ballistic molecular conductor depends sensitively on the geometry of its environment, and can affect its conduction significantly by influencing its energy levels and wave functions. We illustrate some of the issues involved by evaluating the potential profiles for a conducting gold wire and an aromatic phenyl dithiol molecule in various geometries. The potential profile is obtained by solving Poisson’s equation with boundary conditions set by the contact electrochemical potentials and coupling the result self-consistently with a nonequilibrium Green’s function formulation of transport. The overall shape of the potential profile (ramp versus flat) depends on the feasibility of transverse screening of electric fields. Accordingly, the screening is better for a thick wire, a multiwalled nanotube, or a close-packed self-assembled monolayer, in comparison to a thin wire, a single-walled nanotube, or an isolated molecular conductor. The electrostatic potential further governs the alignment or misalignment of intramolecular levels, which can strongly influence the molecular current voltage (I V) characteristic. An external gate voltage can modify the overall potential profile, changing the I V characteristic from a resonant conducting to a saturating one. The degree of saturation and gate modulation depends on the availability of metal-induced-gap states and on the electrostatic gate control parameter set by the ratio of the gate oxide thickness to the channel length.

Effect of substrate thinning on the electronic transport characteristics of AlGaN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Zhu, Hui; Meng, Xiao; Zheng, Xiang; Yang, Ying; Feng, Shiwei; Zhang, Yamin; Guo, Chunsheng

2018-07-01

We studied how substrate thinning affected the electronic transport characteristics of AlGaN/GaN HEMTs. By thinning their sapphire substrate from 460 μm to 80 μm, we varied the residual stress in these HEMTs. The thinned sample showed decreased drain-source current and occurrence of kink effect. Furthermore, shown by current transient measurements and time constant analysis, the detrapping behaviors of trap states shifted toward a larger time constant, and the detrapping behavior under the gate and in the gate-drain access region showed increased amplitude. By using pulsed current-voltage measurements, the thinned sample showed a positive shift of the threshold voltage, a decrease in peak transconductance, and an aggravation in current collapse, as compared with the thick one. The degradation of electrical behavior were associated with the structural degradation, as confirmed by the increase of pit density on the thinned sample surface.

Origin of Degradation Phenomenon under Drain Bias Stress for Oxide Thin Film Transistors using IGZO and IGO Channel Layers

PubMed Central

Bak, Jun Yong; Kang, Youngho; Yang, Shinhyuk; Ryu, Ho-Jun; Hwang, Chi-Sun; Han, Seungwu; Yoon, Sung-Min

2015-01-01

Top-gate structured thin film transistors (TFTs) using In-Ga-Zn-O (IGZO) and In-Ga-O (IGO) channel compositions were investigated to reveal a feasible origin for degradation phenomenon under drain bias stress (DBS). DBS-driven instability in terms of VTH shift, deviation of the SS value, and increase in the on-state current were detected only for the IGZO-TFT, in contrast to the IGO-TFT, which did not demonstrate VTH shift. These behaviors were visually confirmed via nanoscale transmission electron microscopy and energy-dispersive x-ray spectroscopy observations. To understand the degradation mechanism, we performed ab initio molecular dynamic simulations on the liquid phases of IGZO and IGO. The diffusivities of Ga and In atoms were enhanced in IGZO, confirming the degradation mechanism to be increased atomic diffusion. PMID:25601183

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics

DOE PAGES

Hong, Wen-Chiang; Ku, Chieh-Jen; Li, Rui; ...

2016-10-10

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. But, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. We designed devices with unique ring-type structures andmore » use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass.« less

Origin of degradation phenomenon under drain bias stress for oxide thin film transistors using IGZO and IGO channel layers.

PubMed

Bak, Jun Yong; Kang, Youngho; Yang, Shinhyuk; Ryu, Ho-Jun; Hwang, Chi-Sun; Han, Seungwu; Yoon, Sung-Min

2015-01-20

Top-gate structured thin film transistors (TFTs) using In-Ga-Zn-O (IGZO) and In-Ga-O (IGO) channel compositions were investigated to reveal a feasible origin for degradation phenomenon under drain bias stress (DBS). DBS-driven instability in terms of V(TH) shift, deviation of the SS value, and increase in the on-state current were detected only for the IGZO-TFT, in contrast to the IGO-TFT, which did not demonstrate V(TH) shift. These behaviors were visually confirmed via nanoscale transmission electron microscopy and energy-dispersive x-ray spectroscopy observations. To understand the degradation mechanism, we performed ab initio molecular dynamic simulations on the liquid phases of IGZO and IGO. The diffusivities of Ga and In atoms were enhanced in IGZO, confirming the degradation mechanism to be increased atomic diffusion.

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics.

PubMed

Hong, Wen-Chiang; Ku, Chieh-Jen; Li, Rui; Abbaslou, Siamak; Reyes, Pavel; Wang, Szu-Ying; Li, Guangyuan; Lu, Ming; Sheng, Kuang; Lu, Yicheng

2016-10-10

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. However, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. The devices are designed with unique ring-type structures and use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass.

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics

PubMed Central

Hong, Wen-Chiang; Ku, Chieh-Jen; Li, Rui; Abbaslou, Siamak; Reyes, Pavel; Wang, Szu-Ying; Li, Guangyuan; Lu, Ming; Sheng, Kuang; Lu, Yicheng

2016-01-01

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. However, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. The devices are designed with unique ring-type structures and use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass. PMID:27721484

Fredkin and Toffoli Gates Implemented in Oregonator Model of Belousov-Zhabotinsky Medium

NASA Astrophysics Data System (ADS)

Adamatzky, Andrew

A thin-layer Belousov-Zhabotinsky (BZ) medium is a powerful computing device capable for implementing logical circuits, memory, image processors, robot controllers, and neuromorphic architectures. We design the reversible logical gates — Fredkin gate and Toffoli gate — in a BZ medium network of excitable channels with subexcitable junctions. Local control of the BZ medium excitability is an important feature of the gates’ design. An excitable thin-layer BZ medium responds to a localized perturbation with omnidirectional target or spiral excitation waves. A subexcitable BZ medium responds to an asymmetric perturbation by producing traveling localized excitation wave-fragments similar to dissipative solitons. We employ interactions between excitation wave-fragments to perform the computation. We interpret the wave-fragments as values of Boolean variables. The presence of a wave-fragment at a given site of a circuit represents the logical truth, absence of the wave-fragment — logically false. Fredkin gate consists of ten excitable channels intersecting at 11 junctions, eight of which are subexcitable. Toffoli gate consists of six excitable channels intersecting at six junctions, four of which are subexcitable. The designs of the gates are verified using numerical integration of two-variable Oregonator equations.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

NASA Astrophysics Data System (ADS)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a negative flat band voltage shift and larger hysteresis relative to the HF-dipped samples. The IL EOT reduction by mtridation increases with increasing HE Surface nitridation also induces extra charge, more considerable at the Si/IL interface. The leakage current is reduced in the Hf-rich samples with a nitride layer. Electron mobility degradation by surface nitridation was also observed.

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

A low-frequency noise model with carrier generation-recombination process for pentacene organic thin-film transistor

NASA Astrophysics Data System (ADS)

Han, C. Y.; Qian, L. X.; Leung, C. H.; Che, C. M.; Lai, P. T.

2013-07-01

By including the generation-recombination process of charge carriers in conduction channel, a model for low-frequency noise in pentacene organic thin-film transistors (OTFTs) is proposed. In this model, the slope and magnitude of power spectral density for low-frequency noise are related to the traps in the gate dielectric and accumulation layer of the OTFT for the first time. The model can well fit the measured low-frequency noise data of pentacene OTFTs with HfO2 or HfLaO gate dielectric, which validates this model, thus providing an estimate on the densities of traps in the gate dielectric and accumulation layer. It is revealed that the traps in the accumulation layer are much more than those in the gate dielectric, and so dominate the low-frequency noise of pentacene OTFTs.

Comparison of structural and electrical properties of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for α-InGaZnO thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw; Chen, Ching-Hung; Her, Jim-Long

We compared the structural properties and electrical characteristics of high-κ Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for amorphous indium-gallium-zinc oxide (α-InGaZnO) thin-film transistor (TFT) applications. The Lu{sub 2}O{sub 3} film has a strong Lu{sub 2}O{sub 3} (400) peak in the X-ray diffraction pattern, while the Lu{sub 2}TiO{sub 5} sample shows a relatively weak Lu{sub 2}TiO{sub 5} (102) peak. Atomic force microscopy reveals that the Lu{sub 2}O{sub 3} dielectric exhibits a rougher surface (about three times) than Lu{sub 2}TiO{sub 5} one. In X-ray photoelectron spectroscopy analysis, we found that the intensity of the O 1s peak corresponding tomore » Lu(OH){sub x} for Lu{sub 2}O{sub 3} film was higher than that of Lu{sub 2}TiO{sub 5} film. Furthermore, compared with the Lu{sub 2}O{sub 3} dielectric, the α-InGaZnO TFT using the Lu{sub 2}TiO{sub 5} gate dielectric exhibited a lower threshold voltage (from 0.43 to 0.25 V), a higher I{sub on}/I{sub off} current ratio (from 3.5 × 10{sup 6} to 1.3 × 10{sup 8}), a smaller subthreshold swing (from 276 to 130 mV/decade), and a larger field-effect mobility (from 14.5 to 24.4 cm{sup 2}/V s). These results are probably due to the incorporation of TiO{sub x} into the Lu{sub 2}O{sub 3} film to form a Lu{sub 2}TiO{sub 5} structure featuring a smooth surface, a low moisture absorption, a high dielectric constant, and a low interface state density at the oxide/channel interface. Furthermore, the stability of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} α-InGaZnO TFTs was investigated under positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS). The threshold voltage of the TFT performed under NGBS is more degradation than that under PGBS. This behavior may be attributed to the electron charge trapping at the dielectric–channel interface under PGBS, whereas the oxygen vacancies occurred in the InGaZnO under NGBS.« less

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

NASA Astrophysics Data System (ADS)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

Low-voltage organic strain sensor on plastic using polymer/high- K inorganic hybrid gate dielectrics

NASA Astrophysics Data System (ADS)

Jung, Soyoun; Ji, Taeksoo; Varadan, Vijay K.

2007-12-01

In this paper, gate-induced pentacene semiconductor strain sensors based on hybrid-gate dielectrics using poly-vinylphenol (PVP) and high-K inorganic, Ta IIO 5 are fabricated on flexible substrates, polyethylene naphthalate (PEN). The Ta IIO 5 gate dielectric layer is combined with a thin PVP layer to obtain very smooth and hydrophobic surfaces which improve the molecular structures of pentacene films. The PVP-Ta IIO 5 hybrid-gate dielectric films exhibit a high dielectric capacitance and low leakage current. The sensors adopting thin film transistor (TFT)-like structures show a significantly reduced operating voltage (~6V), and good device characteristics with a field-effect mobility of 1.89 cm2/V•s, a threshold voltage of -0.5 V, and an on/off ratio of 10 3. The strain sensor, one of the practical applications in large-area organic electronics, was characterized with different bending radii of 50, 40, 30, and 20 mm. The sensor output signals were significantly improved with low-operating voltages.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

NASA Technical Reports Server (NTRS)

Jones, C. W. (Editor)

1985-01-01

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Extraction of sub-gap density of states via capacitance-voltage measurement for the erasing process in a TFT charge-trapping memory

NASA Astrophysics Data System (ADS)

Chiang, Yen-Chang; Hsiao, Yang-Hsuan; Li, Jeng-Ting; Chen, Jen-Sue

2018-02-01

Charge-trapping memories (CTMs) based on zinc tin oxide (ZTO) semiconductor thin-film transistors (TFTs) can be programmed by a positive gate voltage and erased by a negative gate voltage in conjunction with light illumination. To understand the mechanism involved, the sub-gap density of states associated with ionized oxygen vacancies in the ZTO active layer is extracted from optical response capacitance-voltage (C-V) measurements. The corresponding energy states of ionized oxygen vacancies are observed below the conduction band minimum at approximately 0.5-1.0 eV. From a comparison of the fitted oxygen vacancy concentration in the CTM-TFT after the light-bias erasing operation, it is found that the pristine-erased device contains more oxygen vacancies than the program-erased device because the trapped electrons in the programmed device are pulled into the active layer and neutralized by the oxygen vacancies that are present there.

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

NASA Astrophysics Data System (ADS)

Jones, C. W.

1985-12-01

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Flexible, Low-Power Thin-Film Transistors Made of Vapor-Phase Synthesized High-k, Ultrathin Polymer Gate Dielectrics.

PubMed

Choi, Junhwan; Joo, Munkyu; Seong, Hyejeong; Pak, Kwanyong; Park, Hongkeun; Park, Chan Woo; Im, Sung Gap

2017-06-21

A series of high-k, ultrathin copolymer gate dielectrics were synthesized from 2-cyanoethyl acrylate (CEA) and di(ethylene glycol) divinyl ether (DEGDVE) monomers by a free radical polymerization via a one-step, vapor-phase, initiated chemical vapor deposition (iCVD) method. The chemical composition of the copolymers was systematically optimized by tuning the input ratio of the vaporized CEA and DEGDVE monomers to achieve a high dielectric constant (k) as well as excellent dielectric strength. Interestingly, DEGDVE was nonhomopolymerizable but it was able to form a copolymer with other kinds of monomers. Utilizing this interesting property of the DEGDVE cross-linker, the dielectric constant of the copolymer film could be maximized with minimum incorporation of the cross-linker moiety. To our knowledge, this is the first report on the synthesis of a cyanide-containing polymer in the vapor phase, where a high-purity polymer film with a maximized dielectric constant was achieved. The dielectric film with the optimized composition showed a dielectric constant greater than 6 and extremely low leakage current densities (<3 × 10 -8 A/cm 2 in the range of ±2 MV/cm), with a thickness of only 20 nm, which is an outstanding thickness for down-scalable cyanide polymer dielectrics. With this high-k dielectric layer, organic thin-film transistors (OTFTs) and oxide TFTs were fabricated, which showed hysteresis-free transfer characteristics with an operating voltage of less than 3 V. Furthermore, the flexible OTFTs retained their low gate leakage current and ideal TFT characteristics even under 2% applied tensile strain, which makes them some of the most flexible OTFTs reported to date. We believe that these ultrathin, high-k organic dielectric films with excellent mechanical flexibility will play a crucial role in future soft electronics.

Rapid synthesis and decoration of reduced graphene oxide with gold nanoparticles by thermostable peptides for memory device and photothermal applications.

PubMed

Otari, Sachin V; Kumar, Manoj; Anwar, Muhammad Zahid; Thorat, Nanasaheb D; Patel, Sanjay K S; Lee, Dongjin; Lee, Jai Hyo; Lee, Jung-Kul; Kang, Yun Chan; Zhang, Liaoyuan

2017-09-08

This article presents novel, rapid, and environmentally benign synthesis method for one-step reduction and decoration of graphene oxide with gold nanoparticles (NAuNPs) by using thermostable antimicrobial nisin peptides to form a gold-nanoparticles-reduced graphene oxide (NAu-rGO) nanocomposite. The formed composite material was characterized by UV/Vis spectroscopy, X-ray diffraction, Raman spectroscopy, X-ray photoelectron spectroscopy, field emission scanning electron microscopy, and high-resolution transmission electron microscopy (HR-TEM). HR-TEM analysis revealed the formation of spherical AuNPs of 5-30 nm in size on reduced graphene oxide (rGO) nanosheets. A non-volatile-memory device was prepared based on a solution-processed ZnO thin-film transistor fabricated by inserting the NAu-rGO nanocomposite in the gate dielectric stack as a charge trapping medium. The transfer characteristic of the ZnO thin-film transistor memory device showed large clockwise hysteresis behaviour because of charge carrier trapping in the NAu-rGO nanocomposite. Under positive and negative bias conditions, clear positive and negative threshold voltage shifts occurred, which were attributed to charge carrier trapping and de-trapping in the ZnO/NAu-rGO/SiO 2 structure. Also, the photothermal effect of the NAu-rGO nanocomposites on MCF7 breast cancer cells caused inhibition of ~80% cells after irradiation with infrared light (0.5 W cm -2 ) for 5 min.

Electrical Properties and Interfacial Studies of HfxTi1–xO2 High Permittivity Gate Insulators Deposited on Germanium Substrates

PubMed Central

Lu, Qifeng; Mu, Yifei; Roberts, Joseph W.; Althobaiti, Mohammed; Dhanak, Vinod R.; Wu, Jingjin; Zhao, Chun; Zhao, Ce Zhou; Zhang, Qian; Yang, Li; Mitrovic, Ivona Z.; Taylor, Stephen; Chalker, Paul R.

2015-01-01

In this research, the hafnium titanate oxide thin films, TixHf1–xO2, with titanium contents of x = 0, 0.25, 0.9, and 1 were deposited on germanium substrates by atomic layer deposition (ALD) at 300 °C. The approximate deposition rates of 0.2 Å and 0.17 Å per cycle were obtained for titanium oxide and hafnium oxide, respectively. X-ray Photoelectron Spectroscopy (XPS) indicates the formation of GeOx and germanate at the interface. X-ray diffraction (XRD) indicates that all the thin films remain amorphous for this deposition condition. The surface roughness was analyzed using an atomic force microscope (AFM) for each sample. The electrical characterization shows very low hysteresis between ramp up and ramp down of the Capacitance-Voltage (CV) and the curves are indicative of low trap densities. A relatively large leakage current is observed and the lowest leakage current among the four samples is about 1 mA/cm2 at a bias of 0.5 V for a Ti0.9Hf0.1O2 sample. The large leakage current is partially attributed to the deterioration of the interface between Ge and TixHf1–xO2 caused by the oxidation source from HfO2. Consideration of the energy band diagrams for the different materials systems also provides a possible explanation for the observed leakage current behavior. PMID:28793705

Prototype of IGZO-TFT preamplifier and analog counter for pixel detector

NASA Astrophysics Data System (ADS)

Shimazoe, K.; Koyama, A.; Takahashi, H.; Shindoh, T.; Miyoshi, H.

2017-02-01

IGZO-TFT (Indium Galium Zinc Oxide-Thin Film Transistor) is a promising technology for controlling large display areas and large area sensors because of its very low leakage current in the off state and relatively low cost. IGZO has been used as a switching gate for a large area flat-panel detector. The photon counting capability for X-ray medical imaging has been investigated and expected for low-dose exposure and material determination. Here the design and fabrication of a charge sensitive preamplifier and analog counter using IGZO-TFT processes and its performance are reported for the first time to be used for radiation photon counting applications.

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor

NASA Astrophysics Data System (ADS)

Yang, Paul; Kim, Hyung Jun; Zheng, Hong; Beom, Geon Won; Park, Jong-Sung; Kang, Chi Jung; Yoon, Tae-Sik

2017-06-01

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor.

PubMed

Yang, Paul; Jun Kim, Hyung; Zheng, Hong; Won Beom, Geon; Park, Jong-Sung; Jung Kang, Chi; Yoon, Tae-Sik

2017-06-02

A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

Steep-slope hysteresis-free negative capacitance MoS2 transistors

NASA Astrophysics Data System (ADS)

Si, Mengwei; Su, Chun-Jung; Jiang, Chunsheng; Conrad, Nathan J.; Zhou, Hong; Maize, Kerry D.; Qiu, Gang; Wu, Chien-Ting; Shakouri, Ali; Alam, Muhammad A.; Ye, Peide D.

2018-01-01

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption1,2. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier3. Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel4-12. Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

NASA Astrophysics Data System (ADS)

Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

2018-01-01

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

Solution based zinc tin oxide TFTs: the dual role of the organic solvent

NASA Astrophysics Data System (ADS)

Salgueiro, Daniela; Kiazadeh, Asal; Branquinho, Rita; Santos, Lídia; Barquinha, Pedro; Martins, Rodrigo; Fortunato, Elvira

2017-02-01

Chemical solution deposition is a low cost, scalable and high performance technique to obtain metal oxide thin films. Recently, solution combustion synthesis has been introduced as a chemical route to reduce the processing temperature. This synthesis method takes advantage of the chemistry of the precursors as a source of energy for localized heating. According to the combustion chemistry some organic solvents can have a dual role in the reaction, acting both as solvent and fuel. In this work, we studied the role of 2-methoxyethanol in solution based synthesis of ZTO thin films and its influence on the performance of ZTO TFTs. The thermal behaviour of ZTO precursor solutions confirmed that 2-methoxyethanol acts simultaneously as a solvent and fuel, replacing the fuel function of urea. The electrical characterization of the solution based ZTO TFTs showed a slightly better performance and lower variability under positive gate bias stress when urea was not used as fuel, confirming that the excess fuel contributes negatively to the device operation and stability. Solution based ZTO TFTs demonstrated a low hysteresis (ΔV  =  -0.3 V) and a saturation mobility of 4-5 cm2 V-1 s-1.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Xu, Wangying; Dai, Mingzhi; Liang, Lingyan; Liu, Zhimin; Sun, Xilian; Wan, Qing; Cao, Hongtao

2012-05-01

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

NASA Astrophysics Data System (ADS)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

Carbohydrate-Assisted Combustion Synthesis To Realize High-Performance Oxide Transistors.

PubMed

Wang, Binghao; Zeng, Li; Huang, Wei; Melkonyan, Ferdinand S; Sheets, William C; Chi, Lifeng; Bedzyk, Michael J; Marks, Tobin J; Facchetti, Antonio

2016-06-08

Owing to high carrier mobilities, good environmental/thermal stability, excellent optical transparency, and compatibility with solution processing, thin-film transistors (TFTs) based on amorphous metal oxide semiconductors (AOSs) are promising alternatives to those based on amorphous silicon (a-Si:H) and low-temperature (<600 °C) poly-silicon (LTPS). However, solution-processed display-relevant indium-gallium-tin-oxide (IGZO) TFTs suffer from low carrier mobilities and/or inferior bias-stress stability versus their sputtered counterparts. Here we report that three types of environmentally benign carbohydrates (sorbitol, sucrose, and glucose) serve as especially efficient fuels for IGZO film combustion synthesis to yield high-performance TFTs. The results indicate that these carbohydrates assist the combustion process by lowering the ignition threshold temperature and, for optimal stoichiometries, enhancing the reaction enthalpy. IGZO TFT mobilities are increased to >8 cm(2) V(-1) s(-1) on SiO2/Si gate dielectrics with significantly improved bias-stress stability. The first correlations between precursor combustion enthalpy and a-MO densification/charge transport are established.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Electron-beam irradiation-induced gate oxide degradation

NASA Astrophysics Data System (ADS)

Cho, Byung Jin; Chong, Pei Fen; Chor, Eng Fong; Joo, Moon Sig; Yeo, In Seok

2000-12-01

Gate oxide degradation induced by electron-beam irradiation has been studied. A large increase in the low-field excess leakage current was observed on irradiated oxides and this was very similar to electrical stress-induced leakage currents. Unlike conventional electrical stress-induced leakage currents, however, electron-beam induced leakage currents exhibit a power law relationship with fluency without any signs of saturation. It has also been found that the electron-beam neither accelerates nor initiates quasibreakdown of the ultrathin gate oxide. Therefore, the traps generated by electron-beam irradiation do not contribute to quasibreakdown, only to the leakage current.

Drain Current Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors with Different Active Layer Thicknesses

PubMed Central

Zhao, Wenjing; Li, Hua; Furuta, Mamoru

2018-01-01

In this study, the initial electrical properties, positive gate bias stress (PBS), and drain current stress (DCS)-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with various active layer thicknesses (TIGZO) are investigated. As the TIGZO increased, the turn-on voltage (Von) decreased, while the subthreshold swing slightly increased. Furthermore, the mobility of over 13 cm2·V−1·s−1 and the negligible hysteresis of ~0.5 V are obtained in all of the a-IGZO TFTs, regardless of the TIGZO. The PBS results exhibit that the Von shift is aggravated as the TIGZO decreases. In addition, the DCS-induced instability in the a-IGZO TFTs with various TIGZO values is revealed using current–voltage and capacitance–voltage (C–V) measurements. An anomalous hump phenomenon is only observed in the off state of the gate-to-source (Cgs) curve for all of the a-IGZO TFTs. This is due to the impact ionization that occurs near the drain side of the channel and the generated holes that flow towards the source side along the back-channel interface under the lateral electric field, which cause a lowered potential barrier near the source side. As the TIGZO value increased, the hump in the off state of the Cgs curve was gradually weakened. PMID:29621154

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Kwon, Jin-Hyuk; Bae, Jin-Hyuk; Lee, Hyeonju; Park, Jaehoon

2018-03-01

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

Ionic Liquid Activation of Amorphous Metal-Oxide Semiconductors for Flexible Transparent Electronic Devices

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2016-02-09

To begin this abstract, amorphous metal-oxide semiconductors offer the high carrier mobilities and excellent large-area uniformity required for high performance, transparent, flexible electronic devices; however, a critical bottleneck to their widespread implementation is the need to activate these materials at high temperatures which are not compatible with flexible polymer substrates. The highly controllable activation of amorphous indium gallium zinc oxide semiconductor channels using ionic liquid gating at room temperature is reported. Activation is controlled by electric field-induced oxygen migration across the ionic liquid-semiconductor interface. In addition to activation of unannealed devices, it is shown that threshold voltages of a transistormore » can be linearly tuned between the enhancement and depletion modes. Finally, the first ever example of transparent flexible thin film metal oxide transistor on a polyamide substrate created using this simple technique is demonstrated. Finally, this study demonstrates the potential of field-induced activation as a promising alternative to traditional postdeposition thermal annealing which opens the door to wide scale implementation into flexible electronic applications.« less

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{supmore » 11} cm{sup −2}).« less

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

EDITORIAL: Flexible OLEDs and organic electronics Flexible OLEDs and organic electronics

NASA Astrophysics Data System (ADS)

Kim, Jang-Joo; Han, Min-Koo; Noh, Yong-Young

2011-03-01

Following the great discovery of the electrically conducting polymer, doped polyacetylene, which was honorably recognized in 2000 with the Nobel Prize in chemistry, conjugated molecules, i.e. organic semiconductors, have become an attractive class of active elements for various electronic or opto-electronic applications. Significant effort has been made in both academia and industry to investigate π-conjugated molecules for their unique electrical or opto-electrical properties over the last three decades. The discovery of electroluminescence in conjugated small molecules in 1982 and in polymers in 1989 was a major breakthrough, bringing those molecules to commercial applications within reach for the first time in (opto-)electronic devices, such as organic light-emitting diodes (OLEDs), photovoltaic cells (OPVs), and field-effect transistors (OFETs). Nowadays, we use OLED displays in everyday life in mobile devices. The potential of these devices, which have been fabricated with conjugated molecules, lies in the possibility to combine the advantages of solution processability, chemical tunability and material strength of polymers with the typical properties of plastics, to realize low-cost, large-area electronic devices on flexible substrates by solution deposition and direct-write graphic art printing techniques. The articles in the flexible OLEDs and organic electronics special issue in Semiconductor Science and Technology deal with a diversity of topics and effectively reflect the current status of research from all over the world on various organic electronic devices, including OLEDs, OPVs, and OFETs. Firstly, S Park et al describe the recent progress in thin-film encapsulation techniques for flexible AM-OLED and large-area OLED lightings, and their applications are discussed by J-W Park et al. Flexible active-matrix OLEDs on plastics require stable and flexible thin-film transistors processed at low temperature. Metal oxide thin-film transistors are proposed as one of the best candidates for the purpose, and J K Jeong discusses their status and perspectives. Next, several excellent research articles on OFETs follow. In particular, Y-Y Noh et al introduce an interesting method to control charge injection in top-gated OFETs by insertion of various self-assembled monolayers in their paper entitled 'Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering'. We would like to thank all the authors for their contributions, which combine new results and profound overviews of the state of the art in flexible OLEDs and organic electronics areas; it is this combination that most often adds to the value of topical issues. Special thanks also go to the staff of IOP Publishing, particularly Ms Alice Malhador, for contributing to the success of this effort. In this special issue, many wonderful reviews and research articles provide a detailed overview of recent progress in OLEDs, OPVs and OFETs as well as a scientific understanding of the device physics with these materials. We sincerely believe this special issue is a timely publication and will give productive information to a broad range of readers. Flexible OLEDs and organic electronics Contents Thin film encapsulation for flexible AM-OLED: a review Jin-Seong Park, Heeyeop Chae, Ho Kyoon Chung and Sang In Lee Large-area OLED lightings and their applications J W Park, D C Shin and S H Park Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering Yong-Young Noh, Xiaoyang Cheng, Marta Tello, Mi-Jung Lee and Henning Sirringhaus Branched polythiophene as a new amorphous semiconducting polymer for an organic field-effect transistor Makoto Karakawa, Yutaka Ie and Yoshio Aso Influence of mechanical strain on the electrical properties of flexible organic thin-film transistors Fang-Chung Chen, Tzung-Da Chen, Bing-Ruei Zeng and Ya-Wei Chung Frequency operation of low-voltage, solution-processed organic field-effect transistors M Caironi, Y-Y Noh and H Sirringhaus Nonvolatile memory thin-film transistors using an organic ferroelectric gate insulator and an oxide semiconducting channel Sung-Min Yoon, Shinhyuk Yang, Chun-Won Byun, Soon-Won Jung, Min-Ki Ryu, Sang-Hee Ko Park, ByeongHoon Kim, Himchan Oh, Chi-Sun Hwang and Byoung-Gon Yu The status and perspectives of metal oxide thin-film transistors for active matrix flexible displays Jae Kyeong Jeong Vertical phase segregation of hybrid poly(3-hexylthiophene) and fullerene derivative composites controlled via velocity of solvent drying Tao Song, Zhongwei Wu, Yingfen Tu, Yizheng Jin and Baoquan Sun Variations of cell performance in ITO-free organic solar cells with increasing cell areas Jun-Seok Yeo, Jin-Mun Yun, Seok-Soon Kim, Dong-Yu Kim, Junkyung Kim and Seok-In Na

Scanning gate study of organic thin-film field-effect transistor

NASA Astrophysics Data System (ADS)

Aoki, N.; Sudou, K.; Matsusaki, K.; Okamoto, K.; Ochiai, Y.

2008-03-01

Scanning gate microscopy (SGM) has been applied for a study of organic thin-film field effect transistor (OFET). In contrast to one-dimensional nano-material such a carbon nanonube or nano-structure such a quantum point contact, visualization a transport characteristic of OFET channel is basically rather difficult since the channel width is much larger than the size of the SGM tip. Nevertheless, Schottky barriers are successfully visualized at the boundary between the metal electrodes and the OFET channel at ambient atmosphere.

Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide

NASA Astrophysics Data System (ADS)

Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

2015-04-01

Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs.Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs. Electronic supplementary information (ESI) available: All experimental details, Part S1-3, Fig. S1-6 and Table S1. See DOI: 10.1039/c4nr07620f

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Metal Oxide Thin Film Transistors on Paper Substrate: Fabrication, Characterization, and Printing Process

NASA Astrophysics Data System (ADS)

Choi, Nack-Bong

Flexible electronics is an emerging next-generation technology that offers many advantages such as light weight, durability, comfort, and flexibility. These unique features enable many new applications such as flexible display, flexible sensors, conformable electronics, and so forth. For decades, a variety of flexible substrates have been demonstrated for the application of flexible electronics. Most of them are plastic films and metal foils so far. For the fundamental device of flexible circuits, thin film transistors (TFTs) using poly silicon, amorphous silicon, metal oxide and organic semiconductor have been successfully demonstrated. Depending on application, low-cost and disposable flexible electronics will be required for convenience. Therefore it is important to study inexpensive substrates and to explore simple processes such as printing technology. In this thesis, paper is introduced as a new possible substrate for flexible electronics due to its low-cost and renewable property, and amorphous indium gallium zinc oxide (a-IGZO) TFTs are realized as the promising device on the paper substrate. The fabrication process and characterization of a-IGZO TFT on the paper substrate are discussed. a-IGZO TFTs using a polymer gate dielectric on the paper substrate demonstrate excellent performances with field effect mobility of ˜20 cm2 V-1 s-1, on/off current ratio of ˜106, and low leakage current, which show the enormous potential for flexible electronics application. In order to complement the n-channel a-IGZO TFTs and then enable complementary metal-oxide semiconductor (CMOS) circuit architectures, cuprous oxide is studied as a candidate material of p-channel oxide TFTs. In this thesis, a printing process is investigated as an alternative method for the fabrication of low-cost and disposable electronics. Among several printing methods, a modified offset roll printing that prints high resolution patterns is presented. A new method to fabricate a high resolution printing plate is investigated and the most favorable condition to transfer ink from a blanket to a cliche is studied. Consequently, a high resolution cliche is demonstrated and the printed patterns of 10mum width and 6mum line spacing are presented. In addition, the top gate a-IGZO TFTs with channel width/length of 12/6mum is successfully demonstrated by printing etch-resists. This work validates the compatibility of a-IGZO TFT on paper substrate for the disposable microelectronics application and presents the potential of low-cost and high resolution printing technology.

Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics

NASA Astrophysics Data System (ADS)

Kyoung, Sinsu; Hong, Young-sung; Lee, Myung-hwan; Nam, Tae-jin

2018-02-01

In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

Upgrading non-oxidized carbon nanotubes by thermally decomposed hydrazine

NASA Astrophysics Data System (ADS)

Wang, Pen-Cheng; Liao, Yu-Chun; Liu, Li-Hung; Lai, Yu-Ling; Lin, Ying-Chang; Hsu, Yao-Jane

2014-06-01

We found that the electrical properties of conductive thin films based on non-oxidized carbon nanotubes (CNTs) could be further improved when the CNTs consecutively underwent a mild hydrazine adsorption treatment and then a sufficiently effective thermal desorption treatment. We also found that, after several rounds of vapor-phase hydrazine treatments and baking treatments were applied to an inferior single-CNT field-effect transistor device, the device showed improvement in Ion/Ioff ratio and reduction in the extent of gate-sweeping hysteresis. Our experimental results indicate that, even though hydrazine is a well-known reducing agent, the characteristics of our hydrazine-exposed CNT samples subject to certain treatment conditions could become more graphenic than graphanic, suggesting that the improvement in the electrical and electronic properties of CNT samples could be related to the transient bonding and chemical scavenging of thermally decomposed hydrazine on the surface of CNTs.

Characteristics of TiO2/ZnO bilayer film towards pH sensitivity prepared by different spin coating deposition process

NASA Astrophysics Data System (ADS)

Rahman, Rohanieza Abdul; Zulkefle, Muhammad Al Hadi; Abdullah, Wan Fazlida Hanim; Rusop, M.; Herman, Sukreen Hana

2016-07-01

In this study, titanium dioxide (TiO2) and zinc oxide (ZnO) bilayer film for pH sensing application will be presented. TiO2/ZnO bilayer film with different speed of spin-coating process was deposited on Indium Tin Oxide (ITO), prepared by sol-gel method. This fabricated bilayer film was used as sensing membrane for Extended Gate Field-Effect Transistor (EGFET) for pH sensing application. Experimental results indicated that the sensor is able to detect the sensitivity towards pH buffer solution. In order to obtained the result, sensitivity measurement was done by using the EGFET setup equipment with constant-current (100 µA) and constant-voltage (0.3 V) biasing interfacing circuit. TiO2/ZnO bilayer film which the working electrode, act as the pH-sensitive membrane was connected to a commercial metal-oxide semiconductor FET (MOSFET). This MOSFET then was connected to the interfacing circuit. The sensitivity of the TiO2 thin film towards pH buffer solution was measured by dipping the sensing membrane in pH4, pH7 and pH10 buffer solution. These thin films were characterized by using Field Emission Scanning Electron Microscope (FESEM) to obtain the surface morphology of the composite bilayer films. In addition, I-V measurement was done in order to determine the electrical properties of the bilayer films. According to the result obtained in this experiment, bilayer film that spin at 4000 rpm, gave highest sensitivity which is 52.1 mV/pH. Relating the I-V characteristic of the thin films and sensitivity, the sensing membrane with higher conductivity gave better sensitivity.

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Zhao, Gao-Wei; Lai, Pai-To; Yao, Ruo-He

2016-08-01

Si-doped zinc oxide (SZO) thin films are deposited by using a co-sputtering method, and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures. The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated. Moreover, the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure. The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm, and the optical band gap of the SZO film gradually increases with increasing Si content. The Si-doping can effectively suppress the grain growth of ZnO, revealed by atomic force microscope analysis. Compared with that of the undoped ZnO TFT, the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10-12 A, and thus the on/off current ratio is increased by more than two orders of magnitude. In summary, the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 106 and superior stability under gate-bias and drain-bias stress. Projected supported by the National Natural Science Foundation of China (Grant Nos. 61076113 and 61274085), the Natural Science Foundation of Guangdong Province (Grant No. 2016A030313474), and the University Development Fund (Nanotechnology Research Institute, Grant No. 00600009) of the University of Hong Kong, China.

Characteristics of TiO{sub 2}/ZnO bilayer film towards pH sensitivity prepared by different spin coating deposition process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rahman, Rohanieza Abdul, E-mail: rohanieza.abdrahman@gmail.com; Zulkefle, Muhammad Al Hadi, E-mail: alhadizulkefle@gmail.com; Abdullah, Wan Fazlida Hanim, E-mail: wanfaz@salam.uitm.edu.my

In this study, titanium dioxide (TiO{sub 2}) and zinc oxide (ZnO) bilayer film for pH sensing application will be presented. TiO{sub 2}/ZnO bilayer film with different speed of spin-coating process was deposited on Indium Tin Oxide (ITO), prepared by sol-gel method. This fabricated bilayer film was used as sensing membrane for Extended Gate Field-Effect Transistor (EGFET) for pH sensing application. Experimental results indicated that the sensor is able to detect the sensitivity towards pH buffer solution. In order to obtained the result, sensitivity measurement was done by using the EGFET setup equipment with constant-current (100 µA) and constant-voltage (0.3 V)more » biasing interfacing circuit. TiO{sub 2}/ZnO bilayer film which the working electrode, act as the pH-sensitive membrane was connected to a commercial metal-oxide semiconductor FET (MOSFET). This MOSFET then was connected to the interfacing circuit. The sensitivity of the TiO2 thin film towards pH buffer solution was measured by dipping the sensing membrane in pH4, pH7 and pH10 buffer solution. These thin films were characterized by using Field Emission Scanning Electron Microscope (FESEM) to obtain the surface morphology of the composite bilayer films. In addition, I-V measurement was done in order to determine the electrical properties of the bilayer films. According to the result obtained in this experiment, bilayer film that spin at 4000 rpm, gave highest sensitivity which is 52.1 mV/pH. Relating the I-V characteristic of the thin films and sensitivity, the sensing membrane with higher conductivity gave better sensitivity.« less

An ionic liquid-gated polymer thin film transistor with exceptionally low "on" resistance

NASA Astrophysics Data System (ADS)

Algarni, Saud A.; Althagafi, Talal M.; Smith, Patrick J.; Grell, Martin

2014-05-01

We report the ionic liquid (IL) gating of a solution processed semiconducting polymer, poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT). IL gating relies on the poor solubility of PBTTT, which requires hot chlorinated benzenes for solution processing. PBTTT, thus, resists dissolution even in IL, which otherwise rapidly dissolves semiconducting polymers. The resulting organic thin film transistors (OTFTs) display low threshold, very high carrier mobility (>3 cm2/Vs), and deliver high currents (in the order of 1 mA) at low operational voltages. Such OTFTs are interesting both practically, for the addressing of current-driven devices (e.g., organic LEDs), and for the study of charge transport in semiconducting polymers at very high carrier density.

Nitrogen anion doping as a strategy to suppress negative gate-bias illumination instability of ZnSnO thin film transistor

NASA Astrophysics Data System (ADS)

Li, Jun; Fu, Yi-Zhou; Huang, Chuan-Xin; Zhang, Jian-Hua; Jiang, Xue-Yin; Zhang, Zhi-Lin

2016-04-01

This work presents a strategy of nitrogen anion doping to suppress negative gate-bias illumination instability. The electrical performance and negative gate-bias illumination stability of the ZnSnON thin film transistors (TFTs) are investigated. Compared with ZnSnO-TFT, ZnSnON-TFT has a 53% decrease in the threshold voltage shift under negative bias illumination stress and electrical performance also progresses obviously. The stability improvement of ZnSnON-TFT is attributed to the reduction in ionized oxygen vacancy defects and the photodesorption of oxygen-related molecules. It suggests that anion doping can provide an effective solution to the adverse tradeoff between field effect mobility and negative bias illumination stability.

Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistor by using Focused Ion Beam

NASA Astrophysics Data System (ADS)

Zhu, Wencong

Compared with other transparent semiconductors, amorphous indium gallium zinc oxide (a-IGZO) has both good uniformity and high electron mobility, which make it as a good candidate for displays or large-scale transparent circuit. The goal of this research is to fabricate alpha-IGZO thin film transistor (TFT) with channel milled by focused ion beam (FIB). TFTs with different channel geometries can be achieved by applying different milling strategies, which facilitate modifying complex circuit. Technology Computer-Aided Design (TCAD) was also introduced to understand the effect of trapped charges on the device performance. The investigation of the trapped charge at IGZO/SiO2 interface was performed on the IGZO TFT on p-Silicon substrate with thermally grown SiO2 as dielectric. The subgap density-of-state model was used for the simulation, which includes conduction band-tail trap states and donor-like state in the subgap. The result shows that the de-trapping and donor-state ionization determine the interface trapped charge density at various gate biases. Simulation of IGZO TFT with FIB defined channel on the same substrate was also applied. The drain and source were connected intentionally during metal deposition and separated by FIB milling. Based on the simulation, the Ga ions in SiO2 introduced by the ion beam was drifted by gate bias and affects the saturation drain current. Both side channel and direct channel transparent IGZO TFTs were fabricated on the glass substrate with coated ITO. Higher ion energy (30 keV) was used to etch through the substrate between drain and source and form side channels at the corner of milled trench. Lower ion energy (16 keV) was applied to stop the milling inside IGZO thin film and direct channel between drain and source was created. Annealing after FIB milling removed the residual Ga ions and the devices show switch feature. Direct channel shows higher saturation drain current (~10-6 A) compared with side channel (~10-7 A) because of its shorter channel length and wider width, however, it also exhibit higher gate leakage current (>10-7 A) than side channel (<10-7 A) due to larger Ga ion implantation and diffusion region in SiO2 after annealing. Hysteresis window increase and positive VON shift were also observed due to the interface trap density increase and carrier density suppression both by Ga ions. Laser interference lithography was applied to define the IGZO active region, which gives more flexibility on TFT channel dimension and circuit modification. He-Cd laser with 325 nm wavelength was used to define 2D array of IGZO islands with period of 2.5 im. Logic gate array was designed and fabricated by combining this 2D array of IGZO islands and FIB direct channel milling. After annealing, device shows on-off feature, but high temperature (400 °C) release more free carrier and results in negative shift of VON. The row selection voltage was also introduced in the design of logic gate array to act as switch of input signals to each row separately. However, due to the long input signal sweeping time, the leakage current cannot be overlooked. The idea can be verified by AC or short pulse input signal.

Dual-Input AND Gate From Single-Channel Thin-Film FET

NASA Technical Reports Server (NTRS)

Miranda, F. A.; Pinto, N. J.; Perez, R.; Mueller, C. H.

2008-01-01

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

NASA Astrophysics Data System (ADS)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable insights into the electrolyte-redox systems. In summary, this work provides fundamental insights into the interaction of redox-energy states with silicon substrate and realistic approaches for exploiting the unique properties of the molecules that may enable solutions for nanoscale high density, low-voltage, long retention and multiple bit memory applications.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

NASA Astrophysics Data System (ADS)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Dual-gated MoS2/WSe2 van der Waals tunnel diodes and transistors.

PubMed

Roy, Tania; Tosun, Mahmut; Cao, Xi; Fang, Hui; Lien, Der-Hsien; Zhao, Peida; Chen, Yu-Ze; Chueh, Yu-Lun; Guo, Jing; Javey, Ali

2015-02-24

Two-dimensional layered semiconductors present a promising material platform for band-to-band-tunneling devices given their homogeneous band edge steepness due to their atomically flat thickness. Here, we experimentally demonstrate interlayer band-to-band tunneling in vertical MoS2/WSe2 van der Waals (vdW) heterostructures using a dual-gate device architecture. The electric potential and carrier concentration of MoS2 and WSe2 layers are independently controlled by the two symmetric gates. The same device can be gate modulated to behave as either an Esaki diode with negative differential resistance, a backward diode with large reverse bias tunneling current, or a forward rectifying diode with low reverse bias current. Notably, a high gate coupling efficiency of ∼80% is obtained for tuning the interlayer band alignments, arising from weak electrostatic screening by the atomically thin layers. This work presents an advance in the fundamental understanding of the interlayer coupling and electron tunneling in semiconductor vdW heterostructures with important implications toward the design of atomically thin tunnel transistors.

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Pulsed direct flame deposition and thermal annealing of transparent amorphous indium zinc oxide films as active layers in field effect transistors.

PubMed

Kilian, Daniel; Polster, Sebastian; Vogeler, Isabell; Jank, Michael P M; Frey, Lothar; Peukert, Wolfgang

2014-08-13

Indium-zinc oxide (IZO) films were deposited via flame spray pyrolysis (FSP) by pulsewise shooting a Si/SiO2 substrate directly into the combustion area of the flame. Based on UV-vis measurements of thin-films deposited on glass substrates, the optimal deposition parameters with respect to low haze values and film thicknesses of around 100 nm were determined. Thermal annealing of the deposited films at temperatures between 300 and 700 °C was carried out and staggered bottom gate thin-film transistors (TFT) were fabricated. The thin films were investigated by scanning electron microscopy, atomic force microscopy, X-ray diffraction, Fourier transformed infrared spectroscopy, and room-temperature photoluminescence measurements. The outcome of these investigations lead to two major requirements in order to implement a working TFT: (i) organic residues from the deposition process need to be removed and (ii) the net free charge carrier concentration has to be minimized by controlling the trap states in the semiconductor. The optimal annealing temperature was 300 °C as both requirements are fulfilled best in this case. This leads to field effect transistors with a low hysteresis, a saturation mobility of μSat = 0.1 cm(2)/(V s), a threshold voltage of Vth = -18.9 V, and an Ion/Ioff ratio on the order of 10(7). Depending on thermal treatment, the defect density changes significantly strongly influencing the transfer characteristics of the device.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

PubMed Central

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-01-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process. PMID:27184121

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

NASA Astrophysics Data System (ADS)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

High quality factor graphene varactors for wireless sensing applications

NASA Astrophysics Data System (ADS)

Koester, Steven J.

2011-10-01

A graphene wireless sensor concept is described. By utilizing thin gate dielectrics, the capacitance in a metal-insulator-graphene structure varies with charge concentration through the quantum capacitance effect. Simulations using realistic structural and transport parameters predict quality factors, Q, >60 at 1 GHz. When placed in series with an ideal inductor, a resonant frequency tuning ratio of 25% (54%) is predicted for sense charge densities ranging from 0.32 to 1.6 μC/cm2 at an equivalent oxide thickness of 2.0 nm (0.5 nm). The resonant frequency has a temperature sensitivity, df/dT, less than 0.025%/K for sense charge densities >0.32 μC/cm2.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down tomore » the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.« less

Investigation on the negative bias illumination stress-induced instability of amorphous indium-tin-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Jang, Jaeman; Kim, Dae Geun; Kim, Dong Myong; Choi, Sung-Jin; Lim, Jun-Hyung; Lee, Je-Hun; Kim, Yong-Sung; Ahn, Byung Du; Kim, Dae Hwan

2014-10-01

The quantitative analysis of mechanism on negative bias illumination stress (NBIS)-induced instability of amorphous indium-tin-zinc-oxide thin-film transistor (TFT) was suggested along with the effect of equivalent oxide thickness (EOT) of gate insulator. The analysis was implemented through combining the experimentally extracted density of subgap states and the device simulation. During NBIS, it was observed that the thicker EOT causes increase in both the shift of threshold voltage and the variation of subthreshold swing as well as the hump-like feature in a transfer curve. We found that the EOT-dependence of NBIS instability can be clearly explicated with the donor creation model, in which a larger amount of valence band tail states is transformed into either the ionized oxygen vacancy VO2+ or peroxide O22- with the increase of EOT. It was also found that the VO2+-related extrinsic factor accounts for 80%-92% of the total donor creation taking place in the valence band tail states while the rest is taken by the O22- related intrinsic factor. The ratio of extrinsic factor compared to the total donor creation also increased with the increase of EOT, which could be explained by more prominent oxygen deficiency. The key founding of our work certainly represents that the established model should be considered very effective for analyzing the instability of the post-indium-gallium-zinc-oxide (IGZO) ZnO-based compound semiconductor TFTs with the mobility, which is much higher than those of a-IGZO TFTs.

Observations on the Presumed LET Dependence of SEGR

NASA Technical Reports Server (NTRS)

Selva, L.; Swift, G.; Taylor, W.; Edmonds, L.

1998-01-01

Single-event gate rupture (SEGR)in vertical power MOSFETs is induced by charge deposited in the epitaxial region (below the gate oxide) in concert with the weakening of the oxide, both are a result of the ion passage.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Morphology and electronic transport of polycrystalline pentacene thin-film transistors

NASA Astrophysics Data System (ADS)

Knipp, D.; Street, R. A.; Völkel, A. R.

2003-06-01

Temperature-dependent measurements of thin-film transistors were performed to gain insight in the electronic transport of polycrystalline pentacene. Devices were fabricated with plasma-enhanced chemical vapor deposited silicon nitride gate dielectrics. The influence of the dielectric roughness and the deposition temperature of the thermally evaporated pentacene films were studied. Although films on rougher gate dielectrics and films prepared at low deposition temperatures exhibit similar grain size, the electronic properties are different. Increasing the dielectric roughness reduces the free carrier mobility, while low substrate temperature leads to more and deeper hole traps.

Observation of electric potential in organic thin-film transistor by bias-applied hard X-ray photoemission spectroscopy

NASA Astrophysics Data System (ADS)

Watanabe, Takeshi; Tada, Keisuke; Yasuno, Satoshi; Oji, Hiroshi; Yoshimoto, Noriyuki; Hirosawa, Ichiro

2016-03-01

The effect of gate voltage on electric potential in a pentacene (PEN) layer was studied by hard X-ray photoelectron spectroscopy under a bias voltage. It was observed that applying a negative gate voltage substantially increases the width of a C 1s peak. This suggested that injected and accumulated carriers in an organic thin film transistor channel modified the potential depth profile in PEN. It was also observed that the C 1s kinetic energy tends to increase monotonically with threshold voltage.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

NASA Astrophysics Data System (ADS)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

Properties of slow traps of ALD Al{sub 2}O{sub 3}/GeO{sub x}/Ge nMOSFETs with plasma post oxidation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ke, M., E-mail: kiramn@mosfet.t.u-tokyo.ac.jp; Yu, X.; Chang, C.

2016-07-18

The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (D{sub it}) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge and HfO{sub 2}/Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al{sub 2}O{sub 3} and HfO{sub 2}/Al{sub 2}O{sub 3} combined with plasma post oxidation. It is found that the slow traps can locatemore » in the GeO{sub x} interfacial layer, not in the ALD Al{sub 2}O{sub 3} layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stacks, with changing the thickness of GeO{sub x}, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeO{sub x}, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeO{sub x}.« less

Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics

NASA Astrophysics Data System (ADS)

Wu, Li-Fan; Zhang, Yu-Ming; Lv, Hong-Liang; Zhang, Yi-Men

2016-10-01

Al2O3 and HfO2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition (ALD). The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy (AR-XPS). It is demonstrated that the Al2O3 layer can reduce interfacial oxidation and trap charge formation. The gate leakage current densities are 1.37 × 10-6 A/cm2 and 3.22 × 10-6 A/cm2 at +1 V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively. Compared with the HfO2/InAlAs metal-oxide-semiconductor (MOS) capacitor, the Al2O3/InAlAs MOS capacitor exhibits good electrical properties in reducing gate leakage current, narrowing down the hysteresis loop, shrinking stretch-out of the C-V characteristics, and significantly reducing the oxide trapped charge (Q ot) value and the interface state density (D it). Project supported by the National Basic Research Program of China (Grant No. 2010CB327505), the Advanced Research Foundation of China (Grant No. 914xxx803-051xxx111), the National Defense Advance Research Project, China (Grant No. 513xxxxx306), the National Natural Science Foundation of China (Grant No. 51302215), the Scientific Research Program Funded by Shaanxi Provincial Education Department, China (Grant No. 14JK1656), and the Science and Technology Project of Shaanxi Province, China (Grant No. 2016KRM029).

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Melanin as an active layer in biosensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Piacenti da Silva, Marina, E-mail: marinaness@yahoo.com; Congiu, Mirko, E-mail: congiumat@gmail.com; Oliveira Graeff, Carlos Frederico de, E-mail: graeff@fc.unesp.br

2014-03-15

The development of pH sensors is of great interest due to its extensive application in several areas such as industrial processes, biochemistry and particularly medical diagnostics. In this study, the pH sensing properties of an extended gate field effect transistor (EGFET) based on melanin thin films as active layer are investigated and the physical mechanisms related to the device operation are discussed. Thin films were produced from different melanin precursors on indium tin oxide (ITO) and gold substrates and were investigated by Atomic Force Microscopy and Electrochemical Impedance Spectroscopy. Experiments were performed in the pH range from 2 to 12.more » EGFETs with melanin deposited on ITO and on gold substrates showed sensitivities ranging from 31.3 mV/pH to 48.9 mV/pH, depending on the melanin precursor and the substrate used. The pH detection is associated with specific binding sites in its structure, hydroxyl groups and quinone imine.« less

Enhanced performance of amorphous In-Ga-Zn-O thin-film transistors using different metals for source/drain electrodes

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-09-01

In this paper, we propose an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with off-planed source/drain electrodes. We applied different metals for the source/drain electrodes with Ni and Ti to control the work function as high and low. When we measured the configuration of Ni to drain and source to Ti, the a-IGZO TFT showed increased driving current, decreased leakage current, a high on/off current ratio, low subthreshold swing, and high mobility. In addition, we conducted a reliability test with a gate bias stress test at various temperatures. The results of the reliability test showed the Ni drain and Ti drain had an equivalent effective energy barrier height. Thus, we confirmed that the proposed off-planed structure improved the electrical characteristics of the fabricated devices without any degradation of characteristics. Through the a-IGZO TFT with different source/drain electrode metal engineering, we realized high-performance TFTs for next-generation display devices.

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE PAGES

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja; ...

2014-11-26

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Technology and characterization of Thin-Film Transistors (TFTs) with a-IGZO semiconductor and high-k dielectric layer

NASA Astrophysics Data System (ADS)

Mroczyński, R.; Wachnicki, Ł.; Gierałtowska, S.

2016-12-01

In this work, we present the design of the technology and fabrication of TFTs with amorphous IGZO semiconductor and high-k gate dielectric layer in the form of hafnium oxide (HfOx). In the course of this work, the IGZO fabrication was optimized by means of Taguchi orthogonal tables approach in order to obtain an active semiconductor with reasonable high concentration of charge carriers, low roughness and relatively high mobility. The obtained Thin-Film Transistors can be characterized by very good electrical parameters, i.e., the effective mobility (μeff ≍ 12.8 cm2V-1s-1) significantly higher than that for a-Si TFTs (μeff ≍ 1 cm2V-1s-1). However, the value of sub-threshold swing (i.e., 640 mV/dec) points that the interfacial properties of IGZO/HfOx stack is characterized by high value of interface states density (Dit) which, in turn, demands further optimization for future applications of the demonstrated TFT structures.

Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs

NASA Astrophysics Data System (ADS)

Pi-Ho Hu, Vita; Chiu, Pin-Chieh

2018-04-01

The impact of device parameters on the switching characteristics of negative capacitance ultra-thin-body (UTB) germanium-on-insulator (NC-GeOI) MOSFETs is analyzed. NC-GeOI MOSFETs with smaller gate length (L g), EOT, and buried oxide thickness (T box) and thicker ferroelectric layer thickness (T FE) exhibit larger subthreshold swing improvements over GeOI MOSFETs due to better capacitance matching. Compared with GeOI MOSFETs, NC-GeOI MOSFETs exhibit better switching time due to improvements in effective drive current (I eff) and subthreshold swing. NC-GeOI MOSFET exhibits larger ST improvements at V dd = 0.3 V (-82.9%) than at V dd = 0.86 V (-9.7%), because NC-GeOI MOSFET shows 18.2 times higher I eff than the GeOI MOSFET at V dd = 0.3 V, while 2.5 times higher I eff at V dd = 0.86 V. This work provides the device design guideline of NC-GeOI MOSFETs for ultra-low power applications.

Atomic layer deposition of Nb-doped ZnO for thin film transistors

NASA Astrophysics Data System (ADS)

Shaw, A.; Wrench, J. S.; Jin, J. D.; Whittles, T. J.; Mitrovic, I. Z.; Raja, M.; Dhanak, V. R.; Chalker, P. R.; Hall, S.

2016-11-01

We present physical and electrical characterization of niobium-doped zinc oxide (NbZnO) for thin film transistor (TFT) applications. The NbZnO films were deposited using atomic layer deposition. X-ray diffraction measurements indicate that the crystallinity of the NbZnO films reduces with an increase in the Nb content and lower deposition temperature. It was confirmed using X-ray photoelectron spectroscopy that Nb5+ is present within the NbZnO matrix. Furthermore, photoluminescence indicates that the band gap of the ZnO increases with a higher Nb content, which is explained by the Burstein-Moss effect. For TFT applications, a growth temperature of 175 °C for 3.8% NbZnO provided the best TFT characteristics with a saturation mobility of 7.9 cm2/Vs, the current On/Off ratio of 1 × 108, and the subthreshold swing of 0.34 V/decade. The transport is seen to follow a multiple-trap and release mechanism at lower gate voltages and percolation thereafter.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

Transparent Thin-Film Transistors Based on Sputtered Electric Double Layer

PubMed Central

Cai, Wensi; Ma, Xiaochen; Zhang, Jiawei; Song, Aimin

2017-01-01

Electric-double-layer (EDL) thin-film transistors (TFTs) have attracted much attention due to their low operation voltages. Recently, EDL TFTs gated with radio frequency (RF) magnetron sputtered SiO2 have been developed which is compatible to large-area electronics fabrication. In this work, fully transparent Indium-Gallium-Zinc-Oxide-based EDL TFTs on glass substrates have been fabricated at room temperature for the first time. A maximum transmittance of about 80% has been achieved in the visible light range. The transparent TFTs show a low operation voltage of 1.5 V due to the large EDL capacitance (0.3 µF/cm2 at 20 Hz). The devices exhibit a good performance with a low subthreshold swing of 130 mV/dec and a high on-off ratio > 105. Several tests have also been done to investigate the influences of light irradiation and bias stress. Our results suggest that such transistors might have potential applications in battery-powered transparent electron devices. PMID:28772789

Transparent Thin-Film Transistors Based on Sputtered Electric Double Layer.

PubMed

Cai, Wensi; Ma, Xiaochen; Zhang, Jiawei; Song, Aimin

2017-04-20

Electric-double-layer (EDL) thin-film transistors (TFTs) have attracted much attention due to their low operation voltages. Recently, EDL TFTs gated with radio frequency (RF) magnetron sputtered SiO₂ have been developed which is compatible to large-area electronics fabrication. In this work, fully transparent Indium-Gallium-Zinc-Oxide-based EDL TFTs on glass substrates have been fabricated at room temperature for the first time. A maximum transmittance of about 80% has been achieved in the visible light range. The transparent TFTs show a low operation voltage of 1.5 V due to the large EDL capacitance (0.3 µF/cm² at 20 Hz). The devices exhibit a good performance with a low subthreshold swing of 130 mV/dec and a high on-off ratio > 10⁵. Several tests have also been done to investigate the influences of light irradiation and bias stress. Our results suggest that such transistors might have potential applications in battery-powered transparent electron devices.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

NASA Astrophysics Data System (ADS)

Petti, Luisa; Pattanasattayavong, Pichaya; Lin, Yen-Hung; Münzenrieder, Niko; Cantarella, Giuseppe; Yaacobi-Gross, Nir; Yan, Feng; Tröster, Gerhard; Anthopoulos, Thomas D.

2017-03-01

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V-1 s-1 and 0.013 cm2 V-1 s-1, respectively, current on/off ratio in the range 102-104, and maximum operating voltages between -3.5 and -10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as -3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

Voltage Scaling of Graphene Device on SrTiO3 Epitaxial Thin Film.

PubMed

Park, Jeongmin; Kang, Haeyong; Kang, Kyeong Tae; Yun, Yoojoo; Lee, Young Hee; Choi, Woo Seok; Suh, Dongseok

2016-03-09

Electrical transport in monolayer graphene on SrTiO3 (STO) thin film is examined in order to promote gate-voltage scaling using a high-k dielectric material. The atomically flat surface of thin STO layer epitaxially grown on Nb-doped STO single-crystal substrate offers good adhesion between the high-k film and graphene, resulting in nonhysteretic conductance as a function of gate voltage at all temperatures down to 2 K. The two-terminal conductance quantization under magnetic fields corresponding to quantum Hall states survives up to 200 K at a magnetic field of 14 T. In addition, the substantial shift of charge neutrality point in graphene seems to correlate with the temperature-dependent dielectric constant of the STO thin film, and its effective dielectric properties could be deduced from the universality of quantum phenomena in graphene. Our experimental data prove that the operating voltage reduction can be successfully realized due to the underlying high-k STO thin film, without any noticeable degradation of graphene device performance.

Aluminum Gallium Nitride (GaN)/GaN High Electron Mobility Transistor-Based Sensors for Glucose Detection in Exhaled Breath Condensate

PubMed Central

Chu, Byung Hwan; Kang, Byoung Sam; Hung, Sheng Chun; Chen, Ke Hung; Ren, Fan; Sciullo, Andrew; Gila, Brent P.; Pearton, Stephen J.

2010-01-01

Background Immobilized aluminum gallium nitride (AlGaN)/GaN high electron mobility transistors (HEMTs) have shown great potential in the areas of pH, chloride ion, and glucose detection in exhaled breath condensate (EBC). HEMT sensors can be integrated into a wireless data transmission system that allows for remote monitoring. This technology offers the possibility of using AlGaN/GaN HEMTs for extended investigations of airway pathology of detecting glucose in EBC without the need for clinical visits. Methods HEMT structures, consisting of a 3-μm-thick undoped GaN buffer, 30-Å-thick Al0.3Ga0.7N spacer, and 220-Å-thick silicon-doped Al0.3Ga0.7N cap layer, were used for fabricating the HEMT sensors. The gate area of the pH, chloride ion, and glucose detection was immobilized with scandium oxide (Sc2O3), silver chloride (AgCl) thin film, and zinc oxide (ZnO) nanorods, respectively. Results The Sc2O3-gated sensor could detect the pH of solutions ranging from 3 to 10 with a resolution of ∼0.1 pH. A chloride ion detection limit of 10-8 M was achievedt with a HEMT sensor immobilized with the AgCl thin film. The drain–source current of the ZnO nanorod-gated AlGaN/GaN HEMT sensor immobilized with glucose oxidase showed a rapid response of less than 5 seconds when the sensor was exposed to the target glucose in a buffer with a pH value of 7.4. The sensor could detect a wide range of concentrations from 0.5 nM to 125 μM. Conclusion There is great promise for using HEMT-based sensors to enhance the detection sensitivity for glucose detection in EBC. Depending on the immobilized material, HEMT-based sensors can be used for sensingt different materials. These electronic detection approaches with rapid response and good repeatability show potential for the investigation of airway pathology. The devices can also be integrated into a wireless data transmission system for remote monitoring applications. This sensor technology could use the exhaled breath condensate to measure the glucose concentration for diabetic applications. PMID:20167182

Aluminum gallium nitride (GaN)/GaN high electron mobility transistor-based sensors for glucose detection in exhaled breath condensate.

PubMed

Chu, Byung Hwan; Kang, Byoung Sam; Hung, Sheng Chun; Chen, Ke Hung; Ren, Fan; Sciullo, Andrew; Gila, Brent P; Pearton, Stephen J

2010-01-01

Immobilized aluminum gallium nitride (AlGaN)/GaN high electron mobility transistors (HEMTs) have shown great potential in the areas of pH, chloride ion, and glucose detection in exhaled breath condensate (EBC). HEMT sensors can be integrated into a wireless data transmission system that allows for remote monitoring. This technology offers the possibility of using AlGaN/GaN HEMTs for extended investigations of airway pathology of detecting glucose in EBC without the need for clinical visits. HEMT structures, consisting of a 3-microm-thick undoped GaN buffer, 30-A-thick Al(0.3)Ga(0.7)N spacer, and 220-A-thick silicon-doped Al(0.3)Ga(0.7)N cap layer, were used for fabricating the HEMT sensors. The gate area of the pH, chloride ion, and glucose detection was immobilized with scandium oxide (Sc(2)O(3)), silver chloride (AgCl) thin film, and zinc oxide (ZnO) nanorods, respectively. The Sc(2)O(3)-gated sensor could detect the pH of solutions ranging from 3 to 10 with a resolution of approximately 0.1 pH. A chloride ion detection limit of 10(-8) M was achieved with a HEMT sensor immobilized with the AgCl thin film. The drain-source current of the ZnO nanorod-gated AlGaN/GaN HEMT sensor immobilized with glucose oxidase showed a rapid response of less than 5 seconds when the sensor was exposed to the target glucose in a buffer with a pH value of 7.4. The sensor could detect a wide range of concentrations from 0.5 nM to 125 microM. There is great promise for using HEMT-based sensors to enhance the detection sensitivity for glucose detection in EBC. Depending on the immobilized material, HEMT-based sensors can be used for sensing different materials. These electronic detection approaches with rapid response and good repeatability show potential for the investigation of airway pathology. The devices can also be integrated into a wireless data transmission system for remote monitoring applications. This sensor technology could use the exhaled breath condensate to measure the glucose concentration for diabetic applications. 2010 Diabetes Technology Society.

Photo-Patternable ZnO Thin Films Based on Cross-Linked Zinc Acrylate for Organic/Inorganic Hybrid Complementary Inverters.

PubMed

Jeong, Yong Jin; An, Tae Kyu; Yun, Dong-Jin; Kim, Lae Ho; Park, Seonuk; Kim, Yebyeol; Nam, Sooji; Lee, Keun Hyung; Kim, Se Hyun; Jang, Jaeyoung; Park, Chan Eon

2016-03-02

Complementary inverters consisting of p-type organic and n-type metal oxide semiconductors have received considerable attention as key elements for realizing low-cost and large-area future electronics. Solution-processed ZnO thin-film transistors (TFTs) have great potential for use in hybrid complementary inverters as n-type load transistors because of the low cost of their fabrication process and natural abundance of active materials. The integration of a single ZnO TFT into an inverter requires the development of a simple patterning method as an alternative to conventional time-consuming and complicated photolithography techniques. In this study, we used a photocurable polymer precursor, zinc acrylate (or zinc diacrylate, ZDA), to conveniently fabricate photopatternable ZnO thin films for use as the active layers of n-type ZnO TFTs. UV-irradiated ZDA thin films became insoluble in developing solvent as the acrylate moiety photo-cross-linked; therefore, we were able to successfully photopattern solution-processed ZDA thin films using UV light. We studied the effects of addition of a tiny amount of indium dopant on the transistor characteristics of the photopatterned ZnO thin films and demonstrated low-voltage operation of the ZnO TFTs within ±3 V by utilizing Al2O3/TiO2 laminate thin films or ion-gels as gate dielectrics. By combining the ZnO TFTs with p-type pentacene TFTs, we successfully fabricated organic/inorganic hybrid complementary inverters using solution-processed and photopatterned ZnO TFTs.

Drain Current Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors with Different Active Layer Thicknesses.

PubMed

Wang, Dapeng; Zhao, Wenjing; Li, Hua; Furuta, Mamoru

2018-04-05

In this study, the initial electrical properties, positive gate bias stress (PBS), and drain current stress (DCS)-induced instabilities of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with various active layer thicknesses ( T IGZO ) are investigated. As the T IGZO increased, the turn-on voltage ( V on ) decreased, while the subthreshold swing slightly increased. Furthermore, the mobility of over 13 cm²·V −1 ·s −1 and the negligible hysteresis of ~0.5 V are obtained in all of the a-IGZO TFTs, regardless of the T IGZO . The PBS results exhibit that the V on shift is aggravated as the T IGZO decreases. In addition, the DCS-induced instability in the a-IGZO TFTs with various T IGZO values is revealed using current–voltage and capacitance–voltage ( C – V ) measurements. An anomalous hump phenomenon is only observed in the off state of the gate-to-source ( C gs ) curve for all of the a-IGZO TFTs. This is due to the impact ionization that occurs near the drain side of the channel and the generated holes that flow towards the source side along the back-channel interface under the lateral electric field, which cause a lowered potential barrier near the source side. As the T IGZO value increased, the hump in the off state of the C gs curve was gradually weakened.

Self-Healing Polymer Dielectric for a High Capacitance Gate Insulator.

PubMed

Ko, Jieun; Kim, Young-Jae; Kim, Youn Sang

2016-09-14

Self-healing materials are required for development of various flexible electronic devices to repair cracks and ruptures caused by repetitive bending or folding. Specifically, a self-healing dielectric layer has huge potential to achieve healing electronics without mechanical breakdown in flexible operations. Here, we developed a high performance self-healing dielectric layer with an ionic liquid and catechol-functionalized polymer which exhibited a self-healing ability for both bulk and film states under mild self-healing conditions at 55 °C for 30 min. Due to the sufficient ion mobility of the ionic liquid in the polymer matrix, it had a high capacitance value above 1 μF/cm(2) at 20 Hz. Moreover, zinc oxide (ZnO) thin-film transistors (TFTs) with a self-healing dielectric layer exhibited a high field-effect mobility of 16.1 ± 3.07 cm(2) V(-1) s(-1) at a gate bias of 3 V. Even after repetitive self-healing of the dielectric layer from mechanical breaking, the electrical performance of the TFTs was well-maintained.

Chemical shift and surface characteristics of Al-doped ZnO thin film on SiOC dielectrics.

PubMed

Oh, Teresa; Lee, Sang Yeol

2013-10-01

Aluminum doped zinc oxide (AZO) films were fabricated on SiOC/p-Si wafer and SiOC film was prepared on a p-type Si substrate with the SiC target at oxygen ambient with the gas flow rate of 5-30 sccm by a RF magnetron sputter. C-V curve of SiOC/Si wafer was measured to observe the relationship between the polarity of SiOC dielectrics and the change of capacitance depending on oxygen gas flow rate. The SiOC film could be controlled to be polar or nonpolar, and their surface energy was changed depending on the polarity. Smooth surface is essential to improve the TFT performance. AZO-TFTs used smooth SiOC film with low polarity as a gate insulator was observed to show low leakage current (IL) and low subthreshold voltage swing. It is proposed that SiOC film with high degree amorphous structure as a gate insulator between AZO and Si wafer could solve problems of the mismatched interfaces, which was originated from the electron scattering due to the grain boundary.

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Rafferty, Conor S.; Yu, Zhiping; Dutton, Robert W.; Ancona, Mario G.; Saini, Subhash (Technical Monitor)

1998-01-01

We describe an electronic transport model and an implementation approach that respond to the challenges of device modeling for gigascale integration. We use the density-gradient (DG) transport model, which adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We present the current implementation of the DG model in PROPHET, a partial differential equation solver developed by Lucent Technologies. This implementation approach permits rapid development and enhancement of models, as well as run-time modifications and model switching. We show that even in typical bulk transport devices such as P-N diodes and BJTs, DG quantum effects can significantly modify the I-V characteristics. Quantum effects are shown to be even more significant in small, surface transport devices, such as sub-0.1 micron MOSFETs. In thin-oxide MOS capacitors, we find that quantum effects may reduce gate capacitance by 25% or more. The inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements. Significant quantum corrections also occur in the I-V characteristics of short-channel MOSFETs due to the gate capacitance correction.

Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS2

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Kim, In Soo; Chen, Kan-Sheng; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2015-05-01

Continued progress in high-speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two-terminal device with internal resistance that depends on the history of the external bias voltage. State-of-the-art memristors, based on metal-insulator-metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to ˜103 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.

High-performance thin-film transistors with solution-processed ScInO channel layer based on environmental friendly precursor

NASA Astrophysics Data System (ADS)

Song, Wei; Lan, Linfeng; Li, Meiling; Wang, Lei; Lin, Zhenguo; Sun, Sheng; Li, Yuzhi; Song, Erlong; Gao, Peixiong; Li, Yan; Peng, Junbiao

2017-09-01

Thin-film transistors (TFTs) with solution-processed scandium (Sc) substituted indium oxide (Sc x In1-x O3, ScInO) thin films based on environmental friendly water-induced precursor were fabricated. As the Sc concentration increases from 0% to 10%, the mobility decreases from 23.7 cm2 V-1 s-1 to 6.4 cm2 V-1 s-1, which is attributed to the non-overlapping of the Sc3+ electron orbit. However, the off current decreases and the turn-ON voltage (V ON) shifts towards the positive direction as the Sc content increases, which indicates lower carrier density after incorporation of Sc into In2O3. More interestingly, the incorporation of Sc into In2O3 can effectively improve the electrical stability of the TFT devices under gate bias stress, which is attributed to the reduction of the number of oxygen vacancies due to the relatively low standard electrode potential (-2.36) of Sc and strong bonding strength of Sc-O (680 kJ mol-1). The reduction of oxygen vacancies is confirmed by the x-ray photoelectron spectroscopy (XPS) experiments.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al{sub 2}O{sub 3} gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, Takeshi, E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, Noboru; Osada, Takenori

2015-08-15

This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al{sub 2}O{sub 3} gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al{sub 2}O{sub 3} in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al{sub 2}O{sub 3} layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resultingmore » MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (D{sub it}) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce D{sub it} to below 2 × 10{sup 12} cm{sup −2} eV{sup −1}. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.« less

Critical current enhancement driven by suppression of superconducting fluctuation in ion-gated ultrathin FeSe

NASA Astrophysics Data System (ADS)

Harada, T.; Shiogai, J.; Miyakawa, T.; Nojima, T.; Tsukazaki, A.

2018-05-01

The framework of phase transition, such as superconducting transition, occasionally depends on the dimensionality of materials. Superconductivity is often weakened in the experimental conditions of two-dimensional thin films due to the fragile superconducting state against defects and interfacial effects. In contrast to this general trend, superconductivity in the thin limit of FeSe exhibits an opposite trend, such as an increase in critical temperature (T c) and the superconducting gap exceeding the bulk values; however, the dominant mechanism is still under debate. Here, we measured thickness-dependent electrical transport properties of the ion-gated FeSe thin films to evaluate the superconducting critical current (I c) in the ultrathin FeSe. Upon systematically decreasing the FeSe thickness by the electrochemical etching technique in the Hall bar-shaped electric double-layer transistors, we observed a dramatic enhancement of I c reaching about 10 mA and corresponding to about 107 A cm‑2 in the thinnest condition. By analyzing the transition behavior, we clarify that the suppressed superconducting fluctuation is one of the origins of the large I c in the ion-gated ultrathin FeSe films. These results indicate the existence of a robust superconducting state possibly with dense Cooper pairs at the thin limit of FeSe.

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario; Rafferty, Conor; Saini, Subhash (Technical Monitor)

1999-01-01

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Vacuum ultraviolet radiation effects on two-dimensional MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

McMorrow, Julian J.; Cress, Cory D.; Arnold, Heather N.; Sangwan, Vinod K.; Jariwala, Deep; Schmucker, Scott W.; Marks, Tobin J.; Hersam, Mark C.

2017-02-01

Atomically thin MoS2 has generated intense interest for emerging electronics applications. Its two-dimensional nature and potential for low-power electronics are particularly appealing for space-bound electronics, motivating the need for a fundamental understanding of MoS2 electronic device response to the space radiation environment. In this letter, we quantify the response of MoS2 field-effect transistors (FETs) to vacuum ultraviolet (VUV) total ionizing dose radiation. Single-layer (SL) and multilayer (ML) MoS2 FETs are compared to identify differences that arise from thickness and band structure variations. The measured evolution of the FET transport properties is leveraged to identify the nature of VUV-induced trapped charge, isolating the effects of the interface and bulk oxide dielectric. In both the SL and ML cases, oxide trapped holes compete with interface trapped electrons, exhibiting an overall shift toward negative gate bias. Raman spectroscopy shows no variation in the MoS2 signatures as a result of VUV exposure, eliminating significant crystalline damage or oxidation as possible radiation degradation mechanisms. Overall, this work presents avenues for achieving radiation-hard MoS2 devices through dielectric engineering that reduces oxide and interface trapped charge.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulationmore » by the gate and pinch off.« less

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

p-Type Transparent Electronics

DTIC Science & Technology

2003-09-25

thin - film transistors (TTFTs) reported to date in the literature are summarized. 2.2.1 Thin - Film Transistor Structure and Fabrication A TFT ...is incapable of controlling the TFT regardless of gate voltage, as described in Sec. 2.2.3.1. 2.2.4 Transparent Thin - Film Transistors (TTFTs...Transparent thin - film transistors (TTFTs) described in the literature to date are all n-channel devices. Several n-channel TTFTs (n-TTFTs) based on

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

PubMed

Park, Rebecca S; Hills, Gage; Sohn, Joon; Mitra, Subhasish; Shulaker, Max M; Wong, H-S Philip

2017-05-23

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors. I. Analytical modeling of time-dependent characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Cramer, T.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

Metal-oxide-semiconductor (MOS) transistors fabricated with pentacene thin films were characterized by temperature-dependent current-voltage (I-V) characteristics, time-dependent current measurements, and admittance spectroscopy. The channel mobility shows almost linear variation with temperature, suggesting that only shallow traps are present in the semiconductor and at the oxide/semiconductor interface. The admittance spectra feature a broad peak, which can be modeled as the sum of a continuous distribution of relaxation times. The activation energy of this peak is comparable to the polaron binding energy in pentacene. The absence of trap signals in the admittance spectra confirmed that both the semiconductor and the oxide/semiconductor interface have negligible density of deep traps, likely owing to the passivation of SiO2 before pentacene growth. Nevertheless, current instabilities were observed in time-dependent current measurements following the application of gate-voltage pulses. The corresponding activation energy matches the energy of a hole trap in SiO2. We show that hole trapping in the oxide can explain both the temperature and the time dependences of the current instabilities observed in pentacene MOS transistors. The combination of these experimental techniques allows us to derive a comprehensive model for charge transport in hybrid architectures where trapping processes occur at various time and length scales.

Synthesis, integration, and characterization of metal oxide films as alternative gate dielectric materials

NASA Astrophysics Data System (ADS)

Lin, You-Sheng

ZrO2 and HfO2 were investigated in this study to replace SiO2 as the potential gate dielectric materials in metal-oxide-semiconductor field effect transistors. ZrO2 and HfO2 films were deposited on p-type Si (100) wafers by an atomic layer chemical vapor deposition (ALCVD) process using zirconium (IV) t-butoxide and hafnium (IV) t-butoxide as the metal precursors, respectively. Oxygen was used alternatively with these metal alkoxide precursors into the reactor with purging and evacuation in between. The as-deposited ZrO2 and HfO2 films were stoichiometric and uniform based on X-ray photoemission spectroscopy and ellipsometry measurements. X-ray diffraction analysis indicated that the deposited films were amorphous, however, the high-resolution transmission electron microscopy showed an interfacial layer formation on the silicon substrate. Time-of-flight secondary ion mass spectrometry and medium energy ion scattering analysis showed significant intermixing between metal oxides and Si, indicating the formation of metal silicates, which were confirmed by their chemical etching resistance in HF solutions. The thermal stability of ZrO2 and HfO2 thin films on silicon was examined by monitoring their decomposition temperatures in ultra-high vacuum, using in-situ synchrotron radiation ultra-violet photoemission spectroscopy. The as-deposited ZrO2 and HfO2 thin films were thermally stable up to 880°C and 950°C in vacuum, respectively. The highest achieveable dielectric constants of as-deposited ZrO 2 and HfO2 were 21 and 24, respectively, which were slightly lower than the reported dielectric constants of bulk ZrO2 and HfO 2. These slight reductions in dielectric constants were attributed to the formation of the interfacial metal silicate layers. Very small hysteresis and interface state density were observed for both metal oxide films. Their leakage currents were a few orders of magnitude lower than that of SiO 2 at the same equivalent oxide thickness. NMOSFETs were also fabricated with the as-deposited metal oxide films, and reasonable ID-V D and IG-VG results were obtained. The electron mobilities were high from devices built using a plasma etching process to pattern the metal oxide films. However, they can be degraded if an HF wet etching process was used due to the large contact resistences. Upon oxygen annealing, the formation of SiOx at the interface improved the thermal stability of the as-deposited metal oxide films, however, lower overall dielectric constant and higher leakage current were observed. Upon ammonia annealing, the formation of SiOxNy improved not only the thermal stability but also reduced the leakage current. However, the overall dielectric constant of the film was still reduced due to the formation of the additional interfacial layer.

Temperature dependence of negative bias under illumination stress and recovery in amorphous indium gallium zinc oxide thin film transistors

NASA Astrophysics Data System (ADS)

Hossain Chowdhury, Md Delwar; Migliorato, Piero; Jang, Jin

2013-04-01

We have investigated the temperature dependence of negative bias under illumination stress and recovery. The transfer characteristics exhibits a non-rigid shift towards negative gate voltages. For both stress and recovery, the voltage shift in deep depletion is twice that in accumulation. The results support the mechanism we previously proposed, which is creation and annealing of a double donor, likely to be an oxygen vacancy. The time dependence of stress and recovery can be fitted to stretched exponentials. Both processes are thermally activated with activation energies 1.06 eV and 1.25 eV for stress and recovery, respectively. A potential energy diagram is proposed to explain the results.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Transparent Oxide Thin-Film Transistors: Production, Characterization and Integration

NASA Astrophysics Data System (ADS)

Barquinha, Pedro Miguel Candido

This dissertation is devoted to the study of the emerging area of transparent electronics, summarizing research work regarding the development of n-type thin-film transistors (TFTs) based on sputtered oxide semiconductors. All the materials are produced without intentional substrate heating, with annealing temperatures of only 150-200 °C being used to optimize transistor performance. The work is based on the study and optimization of active semiconductors from the gallium-indium-zinc oxide system, including both the binary compounds Ga2O3, In2O3 and ZnO, as well as ternary and quaternary oxides based on mixtures of those, such as IZO and GIZO with different atomic ratios. Several topics are explored, including the study and optimization of the oxide semiconductor thin films, their application as channel layers on TFTs and finally the implementation of the optimized processes to fabricate active matrix backplanes to be integrated in liquid crystal display (LCD) prototypes. Sputtered amorphous dielectrics with high dielectric constant (high-kappa) based on mixtures of tantalum-silicon or tantalum-aluminum oxides are also studied and used as the dielectric layers on fully transparent TFTs. These devices also include transparent and highly conducting IZO thin films as source, drain and gate electrodes. Given the flexibility of the sputtering technique, oxide semiconductors are analyzed regarding several deposition parameters, such as oxygen partial pressure and deposition pressure, as well as target composition. One of the most interesting features of multicomponent oxides such as IZO and GIZO is that, due to their unique electronic configuration and carrier transport mechanism, they allow to obtain amorphous structures with remarkable electrical properties, such as high hall-effect mobility that exceeds 60 cm2 V -1 s-1 for IZO. These properties can be easily tuned by changing the processing conditions and the atomic ratios of the multicomponent oxides, allowing to have amorphous oxides suitable to be used either as transparent semiconductors or as highly conducting electrodes. The amorphous structure, which is maintained even if the thin films are annealed at 500 °C, brings great advantages concerning interface quality and uniformity in large areas. A complete study comprising different deposition conditions of the semiconductor layer is also made regarding TFT electrical performance. Optimized devices present outstanding electrical performance, such as field-effect mobility (muFE) exceeding 20 cm2 V -1 s-1, turn-on voltage (Von) between -1 and 1 V, subthreshold slope (S) lower than 0.25 V dec-1 and On-Off ratio above 107 . Devices employing amorphous multicomponent oxides present largely improved properties when compared with the ones based on polycrystalline ZnO, mostly in terms of muFE. Within the compositional range where IZO and GIZO films are amorphous, TFT performance can be largely adjusted: for instance, high indium contents favor large mu FE but also highly negative Von, which can be compensated by proper amounts of zinc and gallium. Large oxygen concentrations during oxide semiconductor sputtering are found to be deleterious, decreasing muFE, shifting Von towards high values and turning the devices electrically unstable. It is also shown that semiconductor thickness (ds) has a very important role: for instance, by reducing ds to 10 nm it is possible to produce TFTs with Von≈0 V even using deposition conditions and/or target compositions that normally yield highly conducting films. Given the low ds of the films, this behavior is mostly related with surface states existent at the oxide semiconductor air-exposed back-surface, where depletion layers that can extend towards the dielectric/semiconductor interface are created due to the interaction with atmospheric oxygen. Different passivation layers on top of this air-exposed surface are studied, with SU-8 revealing to be to most effective one. Other important topics are source-drain contact resistance assessment and the effect of different annealing temperatures ( TA), being the properties of the TFTs dominated by TA rather than by the deposition conditions as TA increases. Fully transparent TFTs employing sputtered amorphous multicomponent dielectrics produced without intentional substrate heating present excellent electrical properties, that approach those exhibited by devices using PECVD SiO2 produced at 400 °C. Gate leakage current can be greatly reduced by using tantalum-silicon or tantalum-aluminum oxides rather than Ta2O5. A section of this dissertation is also devoted to the analysis of current stress stability and aging effects of the TFTs, being found that optimal devices exhibit recoverable threshold voltage shifts lower than 0.50 V after 24 h stress with constant drain current of 10 muA, as well as negligible aging effects during 18 months. The research work of this dissertation culminates in the fabrication of a backplane employing transparent TFTs and subsequent integration with a LCD frontplane by Hewlett-Packard. The successful operation of this initial 2.8h prototype with 128x128 pixels provides a solid demonstration that oxide semiconductor-based TFTs have the potential to largely contribute to a novel electronics era, where semiconductor materials away from conventional silicon are used to create fascinating applications, such as transparent electronic products.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

NASA Astrophysics Data System (ADS)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate.

PubMed

Lee, Jae-Kyu; Choi, Duck-Kyun

2012-07-01

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

Eco-Friendly and Biodegradable Biopolymer Chitosan/Y₂O₃ Composite Materials in Flexible Organic Thin-Film Transistors.

PubMed

Du, Bo-Wei; Hu, Shao-Ying; Singh, Ranjodh; Tsai, Tsung-Tso; Lin, Ching-Chang; Ko, Fu-Hsiang

2017-09-03

The waste from semiconductor manufacturing processes causes serious pollution to the environment. In this work, a non-toxic material was developed under room temperature conditions for the fabrication of green electronics. Flexible organic thin-film transistors (OTFTs) on plastic substrates are increasingly in demand due to their high visible transmission and small size for use as displays and wearable devices. This work investigates and analyzes the structured formation of aqueous solutions of the non-toxic and biodegradable biopolymer, chitosan, blended with high-k-value, non-toxic, and biocompatible Y₂O₃ nanoparticles. Chitosan thin films blended with Y₂O₃ nanoparticles were adopted as the gate dielectric thin film in OTFTs, and an improvement in the dielectric properties and pinholes was observed. Meanwhile, the on/off current ratio was increased by 100 times, and a low leakage current was observed. In general, the blended chitosan/Y₂O₃ thin films used as the gate dielectric of OTFTs are non-toxic, environmentally friendly, and operate at low voltages. These OTFTs can be used on surfaces with different curvature radii because of their flexibility.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.