Advanced p-MOSFET Ionizing-Radiation Dosimeter

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.

1994-01-01

Circuit measures total dose of ionizing radiation in terms of shift in threshold gate voltage of doped-channel metal oxide/semiconductor field-effect transistor (p-MOSFET). Drain current set at temperature-independent point to increase accuracy in determination of radiation dose.

A Subthreshold Digital Library Using a Dynamic-Threshold Metal-Oxide Semiconductor (DTMOS) and Transmission Gate Logic

DTIC Science & Technology

2014-09-01

electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG) applications that operate using thermoelectrically generated energy...semiconductor ECG electrocardiography EEG electroencephalography EMG electromyography FY15 fiscal year 2015 IC integrated circuit MOSFETs

Rapidly reconfigurable all-optical universal logic gate

DOEpatents

Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.

2010-09-07

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

Adiabatic gate teleportation.

PubMed

Bacon, Dave; Flammia, Steven T

2009-09-18

The difficulty in producing precisely timed and controlled quantum gates is a significant source of error in many physical implementations of quantum computers. Here we introduce a simple universal primitive, adiabatic gate teleportation, which is robust to timing errors and many control errors and maintains a constant energy gap throughout the computation above a degenerate ground state space. This construction allows for geometric robustness based upon the control of two independent qubit interactions. Further, our piecewise adiabatic evolution easily relates to the quantum circuit model, enabling the use of standard methods from fault-tolerance theory for establishing thresholds.

High-Threshold Low-Overhead Fault-Tolerant Classical Computation and the Replacement of Measurements with Unitary Quantum Gates.

PubMed

Cruikshank, Benjamin; Jacobs, Kurt

2017-07-21

von Neumann's classic "multiplexing" method is unique in achieving high-threshold fault-tolerant classical computation (FTCC), but has several significant barriers to implementation: (i) the extremely complex circuits required by randomized connections, (ii) the difficulty of calculating its performance in practical regimes of both code size and logical error rate, and (iii) the (perceived) need for large code sizes. Here we present numerical results indicating that the third assertion is false, and introduce a novel scheme that eliminates the two remaining problems while retaining a threshold very close to von Neumann's ideal of 1/6. We present a simple, highly ordered wiring structure that vastly reduces the circuit complexity, demonstrates that randomization is unnecessary, and provides a feasible method to calculate the performance. This in turn allows us to show that the scheme requires only moderate code sizes, vastly outperforms concatenation schemes, and under a standard error model a unitary implementation realizes universal FTCC with an accuracy threshold of p<5.5%, in which p is the error probability for 3-qubit gates. FTCC is a key component in realizing measurement-free protocols for quantum information processing. In view of this, we use our scheme to show that all-unitary quantum circuits can reproduce any measurement-based feedback process in which the asymptotic error probabilities for the measurement and feedback are (32/63)p≈0.51p and 1.51p, respectively.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

Integrated Circuit Immunity

NASA Technical Reports Server (NTRS)

Sketoe, J. G.; Clark, Anthony

2000-01-01

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Fault tolerance with noisy and slow measurements and preparation.

PubMed

Paz-Silva, Gerardo A; Brennen, Gavin K; Twamley, Jason

2010-09-03

It is not so well known that measurement-free quantum error correction protocols can be designed to achieve fault-tolerant quantum computing. Despite their potential advantages in terms of the relaxation of accuracy, speed, and addressing requirements, they have usually been overlooked since they are expected to yield a very bad threshold. We show that this is not the case. We design fault-tolerant circuits for the 9-qubit Bacon-Shor code and find an error threshold for unitary gates and preparation of p((p,g)thresh)=3.76×10(-5) (30% of the best known result for the same code using measurement) while admitting up to 1/3 error rates for measurements and allocating no constraints on measurement speed. We further show that demanding gate error rates sufficiently below the threshold pushes the preparation threshold up to p((p)thresh)=1/3.

Demonstration of Qubit Operations Below a Rigorous Fault Tolerance Threshold With Gate Set Tomography (Open Access, Publisher’s Version)

DTIC Science & Technology

2017-02-15

Maunz2 Quantum information processors promise fast algorithms for problems inaccessible to classical computers. But since qubits are noisy and error-prone...information processors have been demonstrated experimentally using superconducting circuits1–3, electrons in semiconductors4–6, trapped atoms and...qubit quantum information processor has been realized14, and single- qubit gates have demonstrated randomized benchmarking (RB) infidelities as low as 10

Light sensing in a photoresponsive, organic-based complementary inverter.

PubMed

Kim, Sungyoung; Lim, Taehoon; Sim, Kyoseung; Kim, Hyojoong; Choi, Youngill; Park, Keechan; Pyo, Seungmoon

2011-05-01

A photoresponsive organic complementary inverter was fabricated and its light sensing characteristics was studied. An organic circuit was fabricated by integrating p-channel pentacene and n-channel copper hexadecafluorophthalocyanine (F16CuPc) organic thin-film transistors (OTFTs) with a polymeric gate dielectric. The F16CuPc OTFT showed typical n-type characteristics and a strong photoresponse under illumination. Whereas under illumination, the pentacene OTFT showed a relatively weak photoresponse with typical p-type characteristics. The characteristics of the organic electro-optical circuit could be controlled by the incident light intensity, a gate bias, or both. The logic threshold (V(M), when V(IN) = V(OUT)) was reduced from 28.6 V without illumination to 19.9 V at 6.94 mW/cm². By using solely optical or a combination of optical and electrical pulse signals, light sensing was demonstrated in this type of organic circuit, suggesting that the circuit can be potentially used in various optoelectronic applications, including optical sensors, photodetectors and electro-optical transceivers.

Error suppression via complementary gauge choices in Reed-Muller codes

NASA Astrophysics Data System (ADS)

Chamberland, Christopher; Jochym-O'Connor, Tomas

2017-09-01

Concatenation of two quantum error-correcting codes with complementary sets of transversal gates can provide a means toward universal fault-tolerant quantum computation. We first show that it is generally preferable to choose the inner code with the higher pseudo-threshold to achieve lower logical failure rates. We then explore the threshold properties of a wide range of concatenation schemes. Notably, we demonstrate that the concatenation of complementary sets of Reed-Muller codes can increase the code capacity threshold under depolarizing noise when compared to extensions of previously proposed concatenation models. We also analyze the properties of logical errors under circuit-level noise, showing that smaller codes perform better for all sampled physical error rates. Our work provides new insights into the performance of universal concatenated quantum codes for both code capacity and circuit-level noise.

Interfacial fields in organic field-effect transistors and sensors

NASA Astrophysics Data System (ADS)

Dawidczyk, Thomas J.

Organic electronics are currently being commercialized and present a viable alternative to conventional electronics. These organic materials offer the ability to chemically manipulate the molecule, allowing for more facile mass processing techniques, which in turn reduces the cost. One application where organic semiconductors (OSCs) are being investigated is sensors. This work evaluates an assortment of n- and p-channel semiconductors as organic field-effect transistor (OFET) sensors. The sensor responses to dinitrotoluene (DNT) vapor and solid along with trinitrotoluene (TNT) solid were studied. Different semiconductor materials give different magnitude and direction of electrical current response upon exposure to DNT. Additional OFET parameters---mobility and threshold voltage---further refine the response to the DNT with each OFET sensor requiring a certain gate voltage for an optimized response to the vapor. The pattern of responses has sufficient diversity to distinguish DNT from other vapors. To effectively use these OFET sensors in a circuit, the threshold voltage needs to be tuned for each transistor to increase the efficiency of the circuit and maximize the sensor response. The threshold voltage can be altered by embedding charges into the dielectric layer of the OFET. To study the quantity and energy of charges needed to alter the threshold voltage, charge carriers were injected into polystyrene (PS) and investigated with scanning Kelvin probe microscopy (SKPM) and thermally stimulated discharge current (TSDC). Lateral heterojunctions of pentacene/PS were scanned using SKPM, effectively observing polarization along a side view of a lateral nonvolatile organic field-effect transistor dielectric interface. TSDC was used to observe charge migration out of PS films and to estimate the trap energy level inside the PS, using the initial rise method. The process was further refined to create lateral heterojunctions that were actual working OFETs, consisting of a PS or poly (3-trifluoro)styrene (F-PS) gate dielectric and a pentacene OSC. The charge storage inside the dielectric was visualized with SKPM, correlated to a threshold voltage shift in the transistor operation, and related to bias stress as well. The SKPM method allows the dielectric/OSC interface of the OFET to be visualized without any alteration of the OFET. Furthermore, this technique allows for the observation of charge distribution between the two dielectric interfaces, PS and F-PS. The SKPM is used to visualize the charge from conventional gate biasing and also as a result of embedding charges deliberately into the dielectric to shift the threshold voltage. Conventional gate biasing shows considerable residual charge in the PS dielectric, which results in gate bias stress. Gate bias stress is one of the major hurdles left in the commercialization of OFETs. To prevent this bias stress, additives of different energy levels were inserted into the dielectric to limit the gate bias stress. Additionally, the dielectrics were pre-charged to try and prevent further bias stress. Neither pre-charging the dielectric or the addition of additive has been used in gate bias prevention, but both methods offer improved resistance to gate bias stress, and help to further refine the dielectric design.

ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-12-01

rows and columns should be minimized. There are two methodologies for achieving this objective, namely, logic minimization to I I I 15 I A B C D E T...type and N-type polysilicon (Figure 2.5( b )) and interconnecting the gates with metal at a later I processing step. The two layers of aluminum available...polysiliconI ...... .. ... .. .. . .. ... .. ... .. I N polysilicon Iii~~iiiiiiii~~iiiiii (a) ( b ) 3 Figure 2.5. Controlling the Threshold Voltage in

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

PubMed

Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki

2016-07-20

We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Demonstration of a Sub-Millimeter Wave Integrated Circuit (S-MMIC) using InP HEMT with a 35-nm Gate

NASA Technical Reports Server (NTRS)

Deal, W. R.; Din, S.; Padilla, J.; Radisic, V.; Mei, G.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Gaier, T.;

Room temperature high-fidelity holonomic single-qubit gate on a solid-state spin.

PubMed

Arroyo-Camejo, Silvia; Lazariev, Andrii; Hell, Stefan W; Balasubramanian, Gopalakrishnan

2014-09-12

At its most fundamental level, circuit-based quantum computation relies on the application of controlled phase shift operations on quantum registers. While these operations are generally compromised by noise and imperfections, quantum gates based on geometric phase shifts can provide intrinsically fault-tolerant quantum computing. Here we demonstrate the high-fidelity realization of a recently proposed fast (non-adiabatic) and universal (non-Abelian) holonomic single-qubit gate, using an individual solid-state spin qubit under ambient conditions. This fault-tolerant quantum gate provides an elegant means for achieving the fidelity threshold indispensable for implementing quantum error correction protocols. Since we employ a spin qubit associated with a nitrogen-vacancy colour centre in diamond, this system is based on integrable and scalable hardware exhibiting strong analogy to current silicon technology. This quantum gate realization is a promising step towards viable, fault-tolerant quantum computing under ambient conditions.

Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2011-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2012-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Step buffer layer of Al0.25Ga0.75N/Al0.08Ga0.92N on P-InAlN gate normally-off high electron mobility transistors

NASA Astrophysics Data System (ADS)

Shrestha, Niraj M.; Li, Yiming; Chang, E. Y.

2016-07-01

Normally-off AlGaN/GaN high electron mobility transistors (HEMTs) are indispensable devices for power electronics as they can greatly simplify circuit designs in a cost-effective way. In this work, the electrical characteristics of p-type InAlN gate normally-off AlGaN/GaN HEMTs with a step buffer layer of Al0.25Ga0.75N/Al0.1Ga0.9N is studied numerically. Our device simulation shows that a p-InAlN gate with a step buffer layer allows the transistor to possess normally-off behavior with high drain current and high breakdown voltage simultaneously. The gate modulation by the p-InAlN gate and the induced holes appearing beneath the gate at the GaN/Al0.25Ga0.75N interface is because a hole appearing in the p-InAlN layer can effectively vary the threshold voltage positively. The estimated threshold voltage of the normally-off HEMTs explored is 2.5 V at a drain bias of 25 V, which is 220% higher than the conventional p-AlGaN normally-off AlGaN/GaN gate injection transistor (GIT). Concurrently, the maximum current density of the explored HEMT at a drain bias of 10 V slightly decreases by about 7% (from 240 to 223 mA mm-1). At a drain bias of 15 V, the current density reached 263 mA mm-1. The explored structure is promising owing to tunable positive threshold voltage and the maintenance of similar current density; notably, its breakdown voltage significantly increases by 36% (from 800 V, GIT, to 1086 V). The engineering findings of this study indicate that novel p-InAlN for both the gate and the step buffer layer can feature a high threshold voltage, large current density and high operating voltage for advanced AlGaN/GaN HEMT devices.

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Arai, Yukiko; Aoki, Hitoshi; Abe, Fumitaka; Todoroki, Shunichiro; Khatami, Ramin; Kazumi, Masaki; Totsuka, Takuya; Wang, Taifeng; Kobayashi, Haruo

2015-04-01

1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

PubMed Central

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

A Substrate Bias Effect on Recovery of the Threshold Voltage Shift of Amorphous Silicon Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Han, Chang-Wook; Han, Min-Koo; Choi, Nack-Bong; Kim, Chang-Dong; Kim, Ki-Yong; Chung, In-Jae

2007-07-01

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated on a flexible stainless-steel (SS) substrate. The stability of the a-Si:H TFT is a key issue for active matrix organic light-emitting diodes (AMOLEDs). The drain current decreases because of the threshold voltage shift (Δ VTH) during OLED driving. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and the gate electrode without additional circuits. The negative voltage biased at the SS substrate can recover Δ VTH and reduced drain current of the driving TFT. The VTH of the TFT increased by 2.3 V under a gate bias of +15 V and a drain bias of +15 V at 65 °C applied for 3,500 s. The VTH decreased by -2.3 V and the drain current recovered 97% of its initial value under a substrate bias of -23 V at 65 °C applied for 3,500 s.

Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vedam, S.; Archambault, L.; Starkschall, G.

2007-11-15

Four-dimensional (4D) computed tomography (CT) imaging has found increasing importance in the localization of tumor and surrounding normal structures throughout the respiratory cycle. Based on such tumor motion information, it is possible to identify the appropriate phase interval for respiratory gated treatment planning and delivery. Such a gating phase interval is determined retrospectively based on tumor motion from internal tumor displacement. However, respiratory-gated treatment is delivered prospectively based on motion determined predominantly from an external monitor. Therefore, the simulation gate threshold determined from the retrospective phase interval selected for gating at 4D CT simulation may not correspond to the deliverymore » gate threshold that is determined from the prospective external monitor displacement at treatment delivery. The purpose of the present work is to establish a relationship between the thresholds for respiratory gating determined at CT simulation and treatment delivery, respectively. One hundred fifty external respiratory motion traces, from 90 patients, with and without audio-visual biofeedback, are analyzed. Two respiratory phase intervals, 40%-60% and 30%-70%, are chosen for respiratory gating from the 4D CT-derived tumor motion trajectory. From residual tumor displacements within each such gating phase interval, a simulation gate threshold is defined based on (a) the average and (b) the maximum respiratory displacement within the phase interval. The duty cycle for prospective gated delivery is estimated from the proportion of external monitor displacement data points within both the selected phase interval and the simulation gate threshold. The delivery gate threshold is then determined iteratively to match the above determined duty cycle. The magnitude of the difference between such gate thresholds determined at simulation and treatment delivery is quantified in each case. Phantom motion tests yielded coincidence of simulation and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8{+-}11% and 14{+-}21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4{+-}7% and 8{+-}15% with and without audio-visual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.« less

Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation.

PubMed

Vedam, S; Archambault, L; Starkschall, G; Mohan, R; Beddar, S

2007-11-01

Four-dimensional (4D) computed tomography (CT) imaging has found increasing importance in the localization of tumor and surrounding normal structures throughout the respiratory cycle. Based on such tumor motion information, it is possible to identify the appropriate phase interval for respiratory gated treatment planning and delivery. Such a gating phase interval is determined retrospectively based on tumor motion from internal tumor displacement. However, respiratory-gated treatment is delivered prospectively based on motion determined predominantly from an external monitor. Therefore, the simulation gate threshold determined from the retrospective phase interval selected for gating at 4D CT simulation may not correspond to the delivery gate threshold that is determined from the prospective external monitor displacement at treatment delivery. The purpose of the present work is to establish a relationship between the thresholds for respiratory gating determined at CT simulation and treatment delivery, respectively. One hundred fifty external respiratory motion traces, from 90 patients, with and without audio-visual biofeedback, are analyzed. Two respiratory phase intervals, 40%-60% and 30%-70%, are chosen for respiratory gating from the 4D CT-derived tumor motion trajectory. From residual tumor displacements within each such gating phase interval, a simulation gate threshold is defined based on (a) the average and (b) the maximum respiratory displacement within the phase interval. The duty cycle for prospective gated delivery is estimated from the proportion of external monitor displacement data points within both the selected phase interval and the simulation gate threshold. The delivery gate threshold is then determined iteratively to match the above determined duty cycle. The magnitude of the difference between such gate thresholds determined at simulation and treatment delivery is quantified in each case. Phantom motion tests yielded coincidence of simulation and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8 +/- 11% and 14 +/- 21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4 +/- 7% and 8 +/- 15% with and without audiovisual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.

Placement of clock gates in time-of-flight optoelectronic circuits

NASA Astrophysics Data System (ADS)

Feehrer, John R.; Jordan, Harry F.

1995-12-01

Time-of-flight synchronized optoelectronic circuits capitalize on the highly controllable delays of optical waveguides. Circuits have no latches; synchronization is achieved by adjustment of the lengths of waveguides that connect circuit elements. Clock gating and pulse stretching are used to restore timing and power. A functional circuit requires that every feedback loop contain at least one clock gate to prevent cumulative timing drift and power loss. A designer specifies an ideal circuit, which contains no or very few clock gates. To make the circuit functional, we must identify locations in which to place clock gates. Because clock gates are expensive, add area, and increase delay, a minimal set of locations is desired. We cast this problem in graph-theoretical form as the minimum feedback edge set problem and solve it by using an adaptation of an algorithm proposed in 1966 [IEEE Trans. Circuit Theory CT-13, 399 (1966)]. We discuss a computer-aided-design implementation of the algorithm that reduces computational complexity and demonstrate it on a set of circuits.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

A two-qubit logic gate in silicon.

PubMed

Veldhorst, M; Yang, C H; Hwang, J C C; Huang, W; Dehollain, J P; Muhonen, J T; Simmons, S; Laucht, A; Hudson, F E; Itoh, K M; Morello, A; Dzurak, A S

2015-10-15

Quantum computation requires qubits that can be coupled in a scalable manner, together with universal and high-fidelity one- and two-qubit logic gates. Many physical realizations of qubits exist, including single photons, trapped ions, superconducting circuits, single defects or atoms in diamond and silicon, and semiconductor quantum dots, with single-qubit fidelities that exceed the stringent thresholds required for fault-tolerant quantum computing. Despite this, high-fidelity two-qubit gates in the solid state that can be manufactured using standard lithographic techniques have so far been limited to superconducting qubits, owing to the difficulties of coupling qubits and dephasing in semiconductor systems. Here we present a two-qubit logic gate, which uses single spins in isotopically enriched silicon and is realized by performing single- and two-qubit operations in a quantum dot system using the exchange interaction, as envisaged in the Loss-DiVincenzo proposal. We realize CNOT gates via controlled-phase operations combined with single-qubit operations. Direct gate-voltage control provides single-qubit addressability, together with a switchable exchange interaction that is used in the two-qubit controlled-phase gate. By independently reading out both qubits, we measure clear anticorrelations in the two-spin probabilities of the CNOT gate.

Fault-tolerance thresholds for the surface code with fabrication errors

NASA Astrophysics Data System (ADS)

Auger, James M.; Anwar, Hussain; Gimeno-Segovia, Mercedes; Stace, Thomas M.; Browne, Dan E.

2017-10-01

The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors—permanent faulty components such as missing physical qubits or failed entangling gates—introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive swap gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of swap gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of 8 % qubit fabrication errors, the surface code can still tolerate a computational error rate of up to 0.1 % .

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

PubMed

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

Mapping from multiple-control Toffoli circuits to linear nearest neighbor quantum circuits

NASA Astrophysics Data System (ADS)

Cheng, Xueyun; Guan, Zhijin; Ding, Weiping

2018-07-01

In recent years, quantum computing research has been attracting more and more attention, but few studies on the limited interaction distance between quantum bits (qubit) are deeply carried out. This paper presents a mapping method for transforming multiple-control Toffoli (MCT) circuits into linear nearest neighbor (LNN) quantum circuits instead of traditional decomposition-based methods. In order to reduce the number of inserted SWAP gates, a novel type of gate with the optimal LNN quantum realization was constructed, namely NNTS gate. The MCT gate with multiple control bits could be better cascaded by the NNTS gates, in which the arrangement of the input lines was LNN arrangement of the MCT gate. Then, the communication overhead measurement model on inserted SWAP gate count from the original arrangement to the new arrangement was put forward, and we selected one of the LNN arrangements with the minimum SWAP gate count. Moreover, the LNN arrangement-based mapping algorithm was given, and it dealt with the MCT gates in turn and mapped each MCT gate into its LNN form by inserting the minimum number of SWAP gates. Finally, some simplification rules were used, which can further reduce the final quantum cost of the LNN quantum circuit. Experiments on some benchmark MCT circuits indicate that the direct mapping algorithm results in fewer additional SWAP gates in about 50%, while the average improvement rate in quantum cost is 16.95% compared to the decomposition-based method. In addition, it has been verified that the proposed method has greater superiority for reversible circuits cascaded by MCT gates with more control bits.

High voltage MOSFET switching circuit

DOEpatents

McEwan, Thomas E.

1994-01-01

The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Digital logic circuits in yeast with CRISPR-dCas9 NOR gates

PubMed Central

Gander, Miles W.; Vrana, Justin D.; Voje, William E.; Carothers, James M.; Klavins, Eric

2017-01-01

Natural genetic circuits enable cells to make sophisticated digital decisions. Building equally complex synthetic circuits in eukaryotes remains difficult, however, because commonly used components leak transcriptionally, do not arbitrarily interconnect or do not have digital responses. Here, we designed dCas9-Mxi1-based NOR gates in Saccharomyces cerevisiae that allow arbitrary connectivity and large genetic circuits. Because we used the chromatin remodeller Mxi1, our gates showed minimal leak and digital responses. We built a combinatorial library of NOR gates that directly convert guide RNA (gRNA) inputs into gRNA outputs, enabling the gates to be ‘wired' together. We constructed logic circuits with up to seven gRNAs, including repression cascades with up to seven layers. Modelling predicted the NOR gates have effectively zero transcriptional leak explaining the limited signal degradation in the circuits. Our approach enabled the largest, eukaryotic gene circuits to date and will form the basis for large, synthetic, cellular decision-making systems. PMID:28541304

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

Clock gating is a leading technique used for power saving. Full adders is one of the basic circuit that can be found in maximum VLSI circuits. In this paper clock gated multiplexer based full adder cell is implemented on 28 nm technology. We have designed a full adder cell using a multiplexer with a gated clock without degrading its performance of the cell. We have negative latch circuit for generating gated clock. This gated clock is used to control the multiplexer based full adder cell. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. The total power of the circuit has been reduced by 7.41% without degrading the performance of original circuit. The power has been calculated using XPower Analyzer tool of XILINX ISE DESIGN SUITE 14.3.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause tile voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Wide operating window spin-torque majority gate towards large-scale integration of logic circuits

NASA Astrophysics Data System (ADS)

Vaysset, Adrien; Zografos, Odysseas; Manfrini, Mauricio; Mocuta, Dan; Radu, Iuliana P.

2018-05-01

Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sadowski, Greg

A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

High voltage MOSFET switching circuit

DOEpatents

McEwan, T.E.

1994-07-26

The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET. 2 figs.

Genetic programs constructed from layered logic gates in single cells

PubMed Central

Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.

2014-01-01

Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931

Light-Triggered Ternary Device and Inverter Based on Heterojunction of van der Waals Materials.

PubMed

Shim, Jaewoo; Jo, Seo-Hyeon; Kim, Minwoo; Song, Young Jae; Kim, Jeehwan; Park, Jin-Hong

2017-06-27

Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metal-oxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (V TH s). Here, we report a finding: the photoinduced drain current in graphene/WSe 2 heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the light-induced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe 2 junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe 2 -based MVL logic circuits by using the I D -V G characteristics with two distinctive V TH s. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔV out of each state <0.05 V). Our study offers the pathway to substantialize MVL systems.

Quantum gates with controlled adiabatic evolutions

NASA Astrophysics Data System (ADS)

Hen, Itay

2015-02-01

We introduce a class of quantum adiabatic evolutions that we claim may be interpreted as the equivalents of the unitary gates of the quantum gate model. We argue that these gates form a universal set and may therefore be used as building blocks in the construction of arbitrary "adiabatic circuits," analogously to the manner in which gates are used in the circuit model. One implication of the above construction is that arbitrary classical boolean circuits as well as gate model circuits may be directly translated to adiabatic algorithms with no additional resources or complexities. We show that while these adiabatic algorithms fail to exhibit certain aspects of the inherent fault tolerance of traditional quantum adiabatic algorithms, they may have certain other experimental advantages acting as quantum gates.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Sub-Circuit Selection and Replacement Algorithms Modeled as Term Rewriting Systems

DTIC Science & Technology

2008-12-16

424, 389, 084, 160 2 In. - 4 Out. 8 , 534, 800, 742, 400 1, 692, 393, 846 , 681, 600 2 In. - 5 Out. 12, 142, 363, 968, 000 2, 661, 320, 479, 104, 000 3...57 A.2 The number of sub-circuits containing 5 and 6 gates . . . . . . 59 A.3 The number of sub-circuits containing 7 and 8 gates . . . . . . 61 A.4...number of sub-circuits containing 7 and 8 gates . . . . . . 68 B.1 Circuit Transformation Rules . . . . . . . . . . . . . . . . . . . 71 x Sub-circuit

Stability of amorphous silicon thin film transistors and circuits

NASA Astrophysics Data System (ADS)

Liu, Ting

Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used for the active-matrix addressing of flat panel displays, optical scanners and sensors. Extending the application of the a-Si TFTs from switches to current sources, which requires continuous operation such as for active-matrix organic light-emitting-diode (AMOLED) pixels, makes stability a critical issue. This thesis first presents a two-stage model for the stability characterization and reliable lifetime prediction for highly stable a-Si TFTs under low gate-field stress. Two stages of the threshold voltage shift are identified from the decrease of the drain saturation current under low-gate field. The first initial stage dominates up to hours or days near room temperature. It can be characterized with a stretched-exponential model, with the underlying physical mechanism of charge trapping in the gate dielectric. The second stage dominates in the long term and then saturates. It corresponds to the breaking of weak bonds in the amorphous silicon. It can be modeled with a "unified stretched exponential fit," in which a thermalization energy is used to unify experimental measurements of drain current decay at different temperatures into a single curve. Two groups of experiments were conducted to reduce the drain current instability of a-Si TFTs under prolonged gate bias. Deposition conditions for the silicon nitride (SiNx) gate insulator and the a-Si channel layer were varied, and TFTs were fabricated with all reactive ion etching steps, or with all wet etching steps, the latter in a new process. The two-stage model that unites charge trapping in the SiNx gate dielectric and defect generation in the a-Si channel was used to interpret the experimental results. We identified the optimal substrate temperature, gas flow ratios, and RF deposition power densities. The stability of the a-Si channel depends also on the deposition conditions for the underlying SiNx gate insulator. TFTs made with wet etching are more stable than TFTs made with reactive ion etching. Combining the various improvements raised the extrapolated 50% decay time of the drain current of back channel passivated dry-etched TFTs under continuous operation at 20°C from 3.3 x 104 sec (9.2 hours) to 4.4 x 107 sec (1.4 years). The 50% lifetime can be further improved by ˜2 times through wet etching process. Two assumptions in the two-stage model were revisited. First, the distribution of the gap state density in a-Si was obtained with the field-effect technique. The redistribution of the gap state density after low-gate field stress supports the idea that defect creation in a-Si dominates in the long term. Second, the drain-bias dependence of drain current degradation was measured and modeled. The unified stretched exponential was validated for a-Si TFTs operating in saturation. Finally, a new 3-TFT voltage-programmed pixel circuit with an in-pixel current source is presented. This circuit is largely insensitive to the TFT threshold voltage shift. The fabricated pixel circuit provides organic light-emitting diode (OLED) currents ranging from 25 nA to 2.9 microA, an on/off ratio of 116 at typical quarter graphics display resolution (QVGA) display timing. The overall conclusion of this thesis research is that the operating life of a-Si TFTs can be quite long, and that these transistors can expect to find yet more applications in large area electronics.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

NASA Astrophysics Data System (ADS)

Panda, D. K.; Lenka, T. R.

2017-06-01

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d-V ds, I d-V gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Electrical Hyperexcitation of Lateral Ventral Pacemaker Neurons Desynchronizes Downstream Circadian Oscillators in the Fly Circadian Circuit and Induces Multiple Behavioral Periods

PubMed Central

Nitabach, Michael N.; Wu, Ying; Sheeba, Vasu; Lemon, William C.; Strumbos, John; Zelensky, Paul K.; White, Benjamin H.; Holmes, Todd C.

2008-01-01

Coupling of autonomous cellular oscillators is an essential aspect of circadian clock function but little is known about its circuit requirements. Functional ablation of the pigment-dispersing factor-expressing lateral ventral subset (LNV ) of Drosophila clock neurons abolishes circadian rhythms of locomotor activity. The hypothesis that LNVs synchronize oscillations in downstream clock neurons was tested by rendering the LNVs hyperexcitable via transgenic expression of a low activation threshold voltage-gated sodium channel. When the LNVs are made hyperexcitable, free-running behavioral rhythms decompose into multiple independent superimposed oscillations and the clock protein oscillations in the dorsal neuron 1 and 2 subgroups of clock neurons are phase-shifted. Thus, regulated electrical activity of the LNVs synchronize multiple oscillators in the fly circadian pacemaker circuit. PMID:16407545

Electronic gating circuit and ultraviolet laser excitation permit improved dosimeter sensitivity

NASA Technical Reports Server (NTRS)

Eggenberger, D.; King, D.; Longnecker, A.; Schutt, D.

1968-01-01

Standard dosimeter reader, modified by adding an electronic gating circuit to trigger the intensity level photomultiplier, increases readout sensitivity of photoluminescent dosimeter systems. The gating circuit is controlled by a second photomultiplier which senses a short ultraviolet pulse from a laser used to excite the dosimeter.

An efficient quantum circuit analyser on qubits and qudits

NASA Astrophysics Data System (ADS)

Loke, T.; Wang, J. B.

2011-10-01

This paper presents a highly efficient decomposition scheme and its associated Mathematica notebook for the analysis of complicated quantum circuits comprised of single/multiple qubit and qudit quantum gates. In particular, this scheme reduces the evaluation of multiple unitary gate operations with many conditionals to just two matrix additions, regardless of the number of conditionals or gate dimensions. This improves significantly the capability of a quantum circuit analyser implemented in a classical computer. This is also the first efficient quantum circuit analyser to include qudit quantum logic gates.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

LOGIC NETS, THEIR CHARACTERIZATION, RELIABILITY, AND EFFICIENT SYNTHESIS.

DTIC Science & Technology

The report consists of two parts. The first discusses a problem in the dual-support approach to network synthesis using threshold gates, gives new...asymptotic results on the number of threshold gates and the size of threshold gate networks, and summarizes the work in threshold logic supported by...this contract, including programs to facilitate experimentation in the design of networks of threshold gates. The second summarizes CDL1 - Computer

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Feedback circuit design of an auto-gating power supply for low-light-level image intensifier

NASA Astrophysics Data System (ADS)

Yang, Ye; Yan, Bo; Zhi, Qiang; Ni, Xiao-bing; Li, Jun-guo; Wang, Yu; Yao, Ze

2015-11-01

This paper introduces the basic principle of auto-gating power supply which using a hybrid automatic brightness control scheme. By the analysis of current as image intensifier to special requirements of auto-gating power supply, a feedback circuit of the auto-gating power supply is analyzed. Find out the reason of the screen flash after the auto-gating power supply assembled image intensifier. This paper designed a feedback circuit which can shorten the response time of auto-gating power supply and improve screen slight flicker phenomenon which the human eye can distinguish under the high intensity of illumination.

A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices

NASA Technical Reports Server (NTRS)

Kulkarni, Shriram; Mazumder, Pinaki; Haddad, George I.

1995-01-01

An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

GaAs-based optoelectronic neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H. (Inventor); Kim, Jae H. (Inventor); Psaltis, Demetri (Inventor)

1993-01-01

An integrated, optoelectronic, variable thresholding neuron implemented monolithically in GaAs integrated circuit and exhibiting high differential optical gain and low power consumption is presented. Two alternative embodiments each comprise an LED monolithically integrated with a detector and two transistors. One of the transistors is responsive to a bias voltage applied to its gate for varying the threshold of the neuron. One embodiment is implemented as an LED monolithically integrated with a double heterojunction bipolar phototransistor (detector) and two metal semiconductor field effect transistors (MESFET's) on a single GaAs substrate and another embodiment is implemented as an LED monolithically integrated with three MESFET's (one of which is an optical FET detector) on a single GaAs substrate. The first noted embodiment exhibits a differential optical gain of 6 and an optical switching energy of 10 pJ. The second embodiment has a differential optical gain of 80 and an optical switching energy of 38 pJ. Power consumption is 2.4 and 1.8 mW, respectively. Input 'light' power needed to turn on the LED is 2 micro-W and 54 nW, respectively. In both embodiments the detector is in series with a biasing MESFET and saturates the other MESFET upon detecting light above a threshold level. The saturated MESFET turns on the LED. Voltage applied to the biasing MESFET gate controls the threshold.

niSWAP and NTCP gates realized in a circuit QED system

NASA Astrophysics Data System (ADS)

Essammouni, K.; Chouikh, A.; Said, T.; Bennai, M.

Based on superconducting qubit coupled to a resonator driven by a strong microwave field, we propose a method to implement two quantum logic gates (niSWAP and NTCP gates) of one qubit simultaneously controlling n qubits selected from N qubits in a circuit QED (1 < n < N) by introducing qubit-qubit interaction. The interaction between the qubits and the circuit QED can be achieved by tuning the gate voltage and the external flux. The operation times of the logic gates are much smaller than the decoherence time and dephasing time. Moreover, the numerical simulation under the influence of the gates operations shows that the scheme could be achieved efficiently with presently available techniques.

Compact quantum gates on electron-spin qubits assisted by diamond nitrogen-vacancy centers inside cavities

NASA Astrophysics Data System (ADS)

Wei, Hai-Rui; Deng, Fu-Guo

2013-10-01

Constructing compact quantum circuits for universal quantum gates on solid-state systems is crucial for quantum computing. We present some compact quantum circuits for a deterministic solid-state quantum computing, including the cnot, Toffoli, and Fredkin gates on the diamond NV centers confined inside cavities, achieved by some input-output processes of a single photon. Our quantum circuits for these universal quantum gates are simple and economic. Moreover, additional electron qubits are not employed, but only a single-photon medium. These gates have a long coherent time. We discuss the feasibility of these universal solid-state quantum gates, concluding that they are feasible with current technology.

Protective circuit for thyristor controlled systems and thyristor converter embodying such protective circuit

DOEpatents

Downhower, Jr., Francis H.; Finlayson, Paul T.

1984-04-10

A snubber circuit coupled across each thyristor to be gated in a chain of thyristors determines the critical output of a NOR LATCH whenever one snubber circuit could not be charged and discharged under normal gating conditions because of a short failure.

A fluorescent combinatorial logic gate with Na+, H+-enabled OR and H+-driven low-medium-high ternary logic functions.

PubMed

Spiteri, Jasmine M A; Mallia, Carl J; Scerri, Glenn J; Magri, David C

2017-12-06

A novel fluorescent molecular logic gate with a 'fluorophore-spacer 1 -receptor 1 -spacer 2 -receptor 2 ' format is demonstrated in 1 : 1 (v/v) methanol/water. The molecule consists of an anthracene fluorophore, and tertiary alkyl amine and N-(2-methoxyphenyl)aza-15-crown-5 ether receptors. In the presence of threshold concentrations of H + and Na + , the molecule switches 'on' as an AND logic gate with a fluorescence quantum yield of 0.21 with proton and sodium binding constants of log β H+ = 9.0 and log β Na+ = 3.2, respectively. At higher proton levels, protonation also occurs at the anilinic nitrogen atom ether with a log β H+ = 4.2, which allows for Na + , H + -enabled OR (OR + AND circuit) and H + -driven ternary logic functions. The reported molecule is compared and contrasted to classic anthracene-based Na + and H + logic gates. We propose that such logic-based molecules could be useful tools for probing the vicinity of Na + , H + antiporters in biological systems.

Hot-Electron-Induced Device Degradation during Gate-Induced Drain Leakage Stress

NASA Astrophysics Data System (ADS)

Kim, Kwang-Soo; Han, Chang-Hoon; Lee, Jun-Ki; Kim, Dong-Soo; Kim, Hyong-Joon; Shin, Joong-Shik; Lee, Hea-Beoum; Choi, Byoung-Deog

2012-11-01

We studied the interface state generation and electron trapping by hot electrons under gate-induced drain leakage (GIDL) stress in p-type metal oxide semiconductor field-effect transistors (P-MOSFETs), which are used as the high-voltage core circuit of flash memory devices. When negative voltage was applied to a drain in the off-state, a GIDL current was generated, but when high voltage was applied to the drain, electrons had a high energy. The hot electrons produced the interface state and electron trapping. As a result, the threshold voltage shifted and the off-state leakage current (trap-assisted drain junction leakage current) increased. On the other hand, electron trapping mitigated the energy band bending near the drain and thus suppressed the GIDL current generation.

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.

2006-01-01

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Hybrid circuit achieves pulse regeneration with low power drain

NASA Technical Reports Server (NTRS)

Cancro, C. A.

1965-01-01

Hybrid tunnel diode-transistor circuit provides a solid-state, low power drain pulse regenerator, frequency limiter, or gated oscillator. When the feedback voltage exceeds the input voltage, the circuit functions as a pulse normalizer or a frequency limiter. If the circuit is direct coupled, it functions as a gated oscillator.

Neighborhood comparison operator

NASA Technical Reports Server (NTRS)

Gennery, D. B. (Inventor)

1985-01-01

Digital values in a moving window are compared by an operator having nine comparators connected to line buffers for receiving a succession of central pixels together with eight neighborhood pixels. A single bit of program control determines whether the neighborhood pixels are to be compared with the central pixel or a threshold value. The central pixel is always compared with the threshold. The omparator output plus 2 bits indicating odd-even pixel/line information about the central pixel addresses a lookup table to provide 14 bits of information, including 2 bits which control a selector to pass either the central pixel value, the other 12 bits of table information, or the bit-wise logical OR of all nine pixels through circuit that implements a very wide OR gate.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Catalytic nucleic acids (DNAzymes) as functional units for logic gates and computing circuits: from basic principles to practical applications.

PubMed

Orbach, Ron; Willner, Bilha; Willner, Itamar

2015-03-11

This feature article addresses the implementation of catalytic nucleic acids as functional units for the construction of logic gates and computing circuits, and discusses the future applications of these systems. The assembly of computational modules composed of DNAzymes has led to the operation of a universal set of logic gates, to field programmable logic gates and computing circuits, to the development of multiplexers/demultiplexers, and to full-adder systems. Also, DNAzyme cascades operating as logic gates and computing circuits were demonstrated. DNAzyme logic systems find important practical applications. These include the use of DNAzyme-based systems for sensing and multiplexed analyses, for the development of controlled release and drug delivery systems, for regulating intracellular biosynthetic pathways, and for the programmed synthesis and operation of cascades.

Experimental investigation of a four-qubit linear-optical quantum logic circuit

NASA Astrophysics Data System (ADS)

Stárek, R.; Mičuda, M.; Miková, M.; Straka, I.; Dušek, M.; Ježek, M.; Fiurášek, J.

2016-09-01

We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C3Z gate and several two-qubit and single-qubit gates. The C3Z gate introduces a sign flip if and only if all four qubits are in the computational state |1>. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.

Experimental investigation of a four-qubit linear-optical quantum logic circuit.

PubMed

Stárek, R; Mičuda, M; Miková, M; Straka, I; Dušek, M; Ježek, M; Fiurášek, J

2016-09-20

We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C(3)Z gate and several two-qubit and single-qubit gates. The C(3)Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.

Electrical Characterization of Semiconductor and Dielectric Materials with a Non-Damaging FastGateTM Probe

NASA Astrophysics Data System (ADS)

Robert, Hillard; William, Howland; Bryan, Snyder

2002-03-01

Determination of the electrical properties of semiconductor materials and dielectrics is highly desirable since these correlate best to final device performance. The properties of SiO2 and high k dielectrics such as Equivalent Oxide Thickness(EOT), Interface Trap Density(Dit), Oxide Effective Charge(Neff), Flatband Voltage Hysteresis(Delta Vfb), Threshold Voltage(VT) and, bulk properties such as carrier density profile and channel dose are all important parameters that require monitoring during front end processing. Conventional methods for determining these parameters involve the manufacturing of polysilicon or metal gate MOS capacitors and subsequent measurements of capacitance-voltage(CV) and/or current-voltage(IV). These conventional techniques are time consuming and can introduce changes to the materials being monitored. Also, equivalent circuit effects resulting from excessive leakage current, series resistance and stray inductance can introduce large errors in the measured results. In this paper, a new method is discussed that provides rapid determination of these critical parameters and is robust against equivalent circuit errors. This technique uses a small diameter(30 micron), elastically deformed probe to form a gate for MOSCAP CV and IV and can be used to measure either monitor wafers or test areas within scribe lines on product wafers. It allows for measurements of dielectrics thinner than 10 Angstroms. A detailed description and applications such as high k dielectrics, will be presented.

Solid state circuit controls direction, speed, and braking of dc motor

NASA Technical Reports Server (NTRS)

Hanna, M. F.

1966-01-01

Full-wave bridge rectifier circuit controls the direction, speed, and braking of a dc motor. Gating in the circuit of Silicon Controlled Rectifiers /SCRS/ controls output polarity and braking is provided by an SCR that is gated to short circuit the reverse voltage generated by reversal of motor rotation.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Rapid disinhibition by adjustment of PV intrinsic excitability during whisker map plasticity in mouse S1.

PubMed

Gainey, Melanie A; Aman, Joseph W; Feldman, Daniel E

2018-04-20

Rapid plasticity of layer (L) 2/3 inhibitory circuits is an early step in sensory cortical map plasticity, but its cellular basis is unclear. We show that, in mice of either sex, 1 day whisker deprivation drives rapid loss of L4-evoked feedforward inhibition and more modest loss of feedforward excitation in L2/3 pyramidal (PYR) cells, increasing E-I conductance ratio. Rapid disinhibition was due to reduced L4-evoked spiking by L2/3 parvalbumin (PV) interneurons, caused by reduced PV intrinsic excitability. This included elevated PV spike threshold, associated with an increase in low-threshold, voltage activated delayed rectifier (presumed Kv1) and A-type potassium currents. Excitatory synaptic input and unitary inhibitory output of PV cells were unaffected. Functionally, the loss of feedforward inhibition and excitation were precisely coordinated in L2/3 PYR cells, so that peak feedforward synaptic depolarization remained stable. Thus, rapid plasticity of PV intrinsic excitability offsets early weakening of excitatory circuits to homeostatically stabilize synaptic potentials in PYR cells of sensory cortex. SIGNIFICANCE STATEMENT Inhibitory circuits in cerebral cortex are highly plastic, but the cellular mechanisms and functional importance of this plasticity are incompletely understood. We show that brief (1-day) sensory deprivation rapidly weakens parvalbumin (PV) inhibitory circuits by reducing the intrinsic excitability of PV neurons. This involved a rapid increase in voltage-gated potassium conductances that control near-threshold spiking excitability. Functionally, the loss of PV-mediated feedforward inhibition in L2/3 pyramidal cells was precisely balanced with the separate loss of feedforward excitation, resulting in a net homeostatic stabilization of synaptic potentials. Thus, rapid plasticity of PV intrinsic excitability implements network-level homeostasis to stabilize synaptic potentials in sensory cortex. Copyright © 2018 the authors.

Geometric dependence of the parasitic components and thermal properties of HEMTs

NASA Astrophysics Data System (ADS)

Vun, Peter V.; Parker, Anthony E.; Mahon, Simon J.; Fattorini, Anthony

2007-12-01

For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Genetic Circuit Performance under Conditions Relevant for Industrial Bioreactors

PubMed Central

Moser, Felix; Broers, Nicolette J.; Hartmans, Sybe; Tamsir, Alvin; Kerkman, Richard; Roubos, Johannes A.; Bovenberg, Roel; Voigt, Christopher A.

2014-01-01

Synthetic genetic programs promise to enable novel applications in industrial processes. For such applications, the genetic circuits that compose programs will require fidelity in varying and complex environments. In this work, we report the performance of two synthetic circuits in Escherichia coli under industrially relevant conditions, including the selection of media, strain, and growth rate. We test and compare two transcriptional circuits: an AND and a NOR gate. In E. coli DH10B, the AND gate is inactive in minimal media; activity can be rescued by supplementing the media and transferring the gate into the industrial strain E. coli DS68637 where normal function is observed in minimal media. In contrast, the NOR gate is robust to media composition and functions similarly in both strains. The AND gate is evaluated at three stages of early scale-up: 100 ml shake-flask experiments, a 1 ml MTP microreactor, and a 10 L bioreactor. A reference plasmid that constitutively produces a GFP reporter is used to make comparisons of circuit performance across conditions. The AND gate function is quantitatively different at each scale. The output deteriorates late in fermentation after the shift from exponential to constant feed rates, which induces rapid resource depletion and changes in growth rate. In addition, one of the output states of the AND gate failed in the bioreactor, effectively making it only responsive to a single input. Finally, cells carrying the AND gate show considerably less accumulation of biomass. Overall, these results highlight challenges and suggest modified strategies for developing and characterizing genetic circuits that function reliably during fermentation. PMID:23656232

Noise-margin limitations on gallium-arsenide VLSI

NASA Technical Reports Server (NTRS)

Long, Stephen I.; Sundaram, Mani

1988-01-01

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.

2009-01-01

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Gate drive latching circuit for an auxiliary resonant commutation circuit

NASA Technical Reports Server (NTRS)

Delgado, Eladio Clemente (Inventor); Kheraluwala, Mustansir Hussainy (Inventor)

1999-01-01

A gate drive latching circuit for an auxiliary resonant commutation circuit for a power switching inverter includes a current monitor circuit providing a current signal to a pair of analog comparators to implement latching of one of a pair of auxiliary switching devices which are used to provide commutation current for commutating switching inverters in the circuit. Each of the pair of comparators feeds a latching circuit which responds to an active one of the comparators for latching the associated gate drive circuit for one of the pair of auxiliary commutating switches. An initial firing signal is applied to each of the commutating switches to gate each into conduction and the resulting current is monitored to determine current direction and therefore the one of the switches which is carrying current. The comparator provides a latching signal to the one of the auxiliary power switches which is actually conducting current and latches that particular power switch into an on state for the duration of current through the device. The latching circuit is so designed that the only time one of the auxiliary switching devices can be latched on is during the duration of an initial firing command signal.

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE PAGES

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred; ...

2017-01-19

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Experimental investigation of a four-qubit linear-optical quantum logic circuit

PubMed Central

Stárek, R.; Mičuda, M.; Miková, M.; Straka, I.; Dušek, M.; Ježek, M.; Fiurášek, J.

2016-01-01

We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C3Z gate and several two-qubit and single-qubit gates. The C3Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses. PMID:27647176

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Dual amplitude pulse generator for radiation detectors

DOEpatents

Hoggan, Jerry M.; Kynaston, Ronnie L.; Johnson, Larry O.

2001-01-01

A pulsing circuit for producing an output signal having a high amplitude pulse and a low amplitude pulse may comprise a current source for providing a high current signal and a low current signal. A gate circuit connected to the current source includes a trigger signal input that is responsive to a first trigger signal and a second trigger signal. The first trigger signal causes the gate circuit to connect the high current signal to a pulse output terminal whereas the second trigger signal causes the gate circuit to connect the low current signal to the pulse output terminal.

Implementation of a quantum controlled-SWAP gate with photonic circuits

NASA Astrophysics Data System (ADS)

Ono, Takafumi; Okamoto, Ryo; Tanida, Masato; Hofmann, Holger F.; Takeuchi, Shigeki

2017-03-01

Quantum information science addresses how the processing and transmission of information are affected by uniquely quantum mechanical phenomena. Combination of two-qubit gates has been used to realize quantum circuits, however, scalability is becoming a critical problem. The use of three-qubit gates may simplify the structure of quantum circuits dramatically. Among them, the controlled-SWAP (Fredkin) gates are essential since they can be directly applied to important protocols, e.g., error correction, fingerprinting, and optimal cloning. Here we report a realization of the Fredkin gate for photonic qubits. We achieve a fidelity of 0.85 in the computational basis and an output state fidelity of 0.81 for a 3-photon Greenberger-Horne-Zeilinger state. The estimated process fidelity of 0.77 indicates that our Fredkin gate can be applied to various quantum tasks.

Device and material characterization and analytic modeling of amorphous silicon thin film transistors

NASA Astrophysics Data System (ADS)

Slade, Holly Claudia

Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be modeled using a transmission line model, which is implemented using a small signal circuit with access resistors in series with the source and drain capacitances. This correctly reproduces the frequency dispersion in the TFT. Automatic parameter extraction routines are provided and are used to test the robustness of the model on a variety of devices from different research laboratories. The results demonstrate excellent agreement, showing that the model is suitable for device design, scaling, and implementation in the manufacturing process.

A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

NASA Astrophysics Data System (ADS)

Fulkerson, David E.

2010-02-01

This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

Reprogrammable Logic Gate and Logic Circuit Based on Multistimuli-Responsive Raspberry-like Micromotors.

PubMed

Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin

2016-06-22

In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Fast-synchronizing high-fidelity spread-spectrum receiver

DOEpatents

Moore, Michael Roy; Smith, Stephen Fulton; Emery, Michael Steven

2004-06-01

A fast-synchronizing receiver having a circuit including an equalizer configured for manipulating an analog signal; a detector in communication with the equalizer; a filter in communication with the detector; an oscillator in communication with the filter; a gate for receiving the manipulated signal; a circuit portion for synchronizing and tracking the manipulated signal; a summing circuit in communication with the circuit portion; and an output gate.

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistors

NASA Technical Reports Server (NTRS)

Yamada, Toshishige; Biegel, Bryan (Technical Monitor)

2002-01-01

The threshold voltages of a carbon nanotube (CNT) field-effect transistor (FET) are derived and compared with those of the metal oxide-semiconductor (MOS) FETs. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, which is the CNT diameter direction, and this makes the CNTFET characteristics quite different from those in MOSFETs. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and it is shown that the familiar relations are still valid because of the macroscopic number of states available in the CNTs. This is in sharp contrast to the cases of quantum dots. Using these relations, we derive an inversion threshold voltage V(sub Ti) and an accumulation threshold voltage V(sub Ta) as a function of the Fermi level E(sub F) in the channel, where E(sub F) is a measure of channel doping. V(sub Ti) of the CNTFETs has a much stronger dependence than that of MOSFETs, while V(sub Ta)s of both CNTFETs and MOSFETs depend quite weakly on E(sub F) with the same functional form. This means the transition from normally-off mode to normally-on mode is much sharper in CNTFETs as the doping increases, and this property has to be taken into account in circuit design.

Comparative Study of Fault Diagnostic Methods in Voltage Source Inverter Fed Three Phase Induction Motor Drive

NASA Astrophysics Data System (ADS)

Dhumale, R. B.; Lokhande, S. D.

2017-05-01

Three phase Pulse Width Modulation inverter plays vital role in industrial applications. The performance of inverter demeans as several types of faults take place in it. The widely used switching devices in power electronics are Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Field Effect Transistors (MOSFET). The IGBTs faults are broadly classified as base or collector open circuit fault, misfiring fault and short circuit fault. To develop consistency and performance of inverter, knowledge of fault mode is extremely important. This paper presents the comparative study of IGBTs fault diagnosis. Experimental set up is implemented for data acquisition under various faulty and healthy conditions. Recent methods are executed using MATLAB-Simulink and compared using key parameters like average accuracy, fault detection time, implementation efforts, threshold dependency, and detection parameter, resistivity against noise and load dependency.

Orthogonality and Burdens of Heterologous AND Gate Gene Circuits in E. coli

PubMed Central

2017-01-01

Synthetic biology approaches commonly introduce heterologous gene networks into a host to predictably program cells, with the expectation of the synthetic network being orthogonal to the host background. However, introduced circuits may interfere with the host’s physiology, either indirectly by posing a metabolic burden and/or through unintended direct interactions between parts of the circuit with those of the host, affecting functionality. Here we used RNA-Seq transcriptome analysis to quantify the interactions between a representative heterologous AND gate circuit and the host Escherichia coli under various conditions including circuit designs and plasmid copy numbers. We show that the circuit plasmid copy number outweighs circuit composition for their effect on host gene expression with medium-copy number plasmid showing more prominent interference than its low-copy number counterpart. In contrast, the circuits have a stronger influence on the host growth with a metabolic load increasing with the copy number of the circuits. Notably, we show that variation of copy number, an increase from low to medium copy, caused different types of change observed in the behavior of components in the AND gate circuit leading to the unbalance of the two gate-inputs and thus counterintuitive output attenuation. The study demonstrates the circuit plasmid copy number is a key factor that can dramatically affect the orthogonality, burden and functionality of the heterologous circuits in the host chassis. The results provide important guidance for future efforts to design orthogonal and robust gene circuits with minimal unwanted interaction and burden to their host. PMID:29240998

Benchmarking gate-based quantum computers

NASA Astrophysics Data System (ADS)

Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans

2017-11-01

With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.

Ultra-Low-Energy Sub-Threshold Circuits: Program Overview

DTIC Science & Technology

2007-04-10

with global > 0.1 corner, but so does VUL, VIH 0 .0 5 -_ "or ni n a Global Variatlion 0.0a 0•,lN& 0.24.. 7 Mir" Output Swing Metrics " Need a... VIH . lines plot the VTCs when random local VT mismatch is ap- In Figure 1(b), a NAND gate has sufficient output swing plied to the inverter. One case...the VTC is input-dependent, all inputs are varied simultaneously to >P 1 0 SNM side of largest obtain the worst case ViH and VIL. > 0 ins0nbedsquare

Analog and RF performance of a multigate FinFET at nano scale

NASA Astrophysics Data System (ADS)

Kumar, Abhishek

2016-12-01

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.

Enabling complex genetic circuits to respond to extrinsic environmental signals.

PubMed

Hoynes-O'Connor, Allison; Shopera, Tatenda; Hinman, Kristina; Creamer, John Philip; Moon, Tae Seok

2017-07-01

Genetic circuits have the potential to improve a broad range of metabolic engineering processes and address a variety of medical and environmental challenges. However, in order to engineer genetic circuits that can meet the needs of these real-world applications, genetic sensors that respond to relevant extrinsic and intrinsic signals must be implemented in complex genetic circuits. In this work, we construct the first AND and NAND gates that respond to temperature and pH, two signals that have relevance in a variety of real-world applications. A previously identified pH-responsive promoter and a temperature-responsive promoter were extracted from the E. coli genome, characterized, and modified to suit the needs of the genetic circuits. These promoters were combined with components of the type III secretion system in Salmonella typhimurium and used to construct a set of AND gates with up to 23-fold change. Next, an antisense RNA was integrated into the circuit architecture to invert the logic of the AND gate and generate a set of NAND gates with up to 1168-fold change. These circuits provide the first demonstration of complex pH- and temperature-responsive genetic circuits, and lay the groundwork for the use of similar circuits in real-world applications. Biotechnol. Bioeng. 2017;114: 1626-1631. © 2017 Wiley Periodicals, Inc. © 2017 Wiley Periodicals, Inc.

Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2018-04-01

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

Graphene barristor, a triode device with a gate-controlled Schottky barrier.

PubMed

Yang, Heejun; Heo, Jinseong; Park, Seongjun; Song, Hyun Jae; Seo, David H; Byun, Kyung-Eun; Kim, Philip; Yoo, InKyeong; Chung, Hyun-Jong; Kim, Kinam

2012-06-01

Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

ADAPTIVE THRESHOLD LOGIC.

DTIC Science & Technology

The design and construction of a 16 variable threshold logic gate with adaptable weights is described. The operating characteristics of tape wound...and sizes as well as for the 16 input adaptive threshold logic gate. (Author)

Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata.

PubMed

Bahar, Ali Newaz; Waheed, Sajjad

2016-01-01

The fundamental logical element of a quantum-dot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer five-input majority voter gate (MV5). The structure of proposed MV5 is very simple and easy to implement in any logical circuit. This proposed MV5 reduce number of cells and use conventional QCA cells. However, using MV5 a multilayer 1-bit full-adder (FA) is designed. The functional accuracy of the proposed MV5 and FA are confirmed by QCADesigner a well-known QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2017-05-01

Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.

Designable DNA-binding domains enable construction of logic circuits in mammalian cells.

PubMed

Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman

2014-03-01

Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Y.; Zhong, Y. P.; Deng, Y. F.

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

p53 activated by AND gate genetic circuit under radiation and hypoxia for targeted cancer gene therapy

PubMed Central

Ding, Miao; Li, Rong; He, Rong; Wang, Xingyong; Yi, Qijian; Wang, Weidong

2015-01-01

Radio-activated gene therapy has been developed as a novel therapeutic strategy against cancer; however, expression of therapeutic gene in peritumoral tissues will result in unacceptable toxicity to normal cells. To restrict gene expression in targeted tumor mass, we used hypoxia and radiation tolerance features of tumor cells to develop a synthetic AND gate genetic circuit through connecting radiation sensitivity promoter cArG6, heat shock response elements SNF1, HSF1 and HSE4 with retroviral vector plxsn. Their construction and dynamic activity process were identified through downstream enhanced green fluorescent protein and wtp53 expression in non-small cell lung cancer A549 cells and in a nude mice model. The result showed that AND gate genetic circuit could be activated by lower required radiation dose (6 Gy) and after activated, AND gate could induce significant apoptosis effects and growth inhibition of cancer cells in vitro and in vivo. The radiation- and hypoxia-activated AND gate genetic circuit, which could lead to more powerful target tumoricidal activity represented a promising strategy for both targeted and effective gene therapy of human lung adenocarcinoma and low dose activation character of the AND gate genetic circuit implied that this model could be further exploited to decrease side-effects of clinical radiation therapy. PMID:26177264

The Development of III-V Semiconductor MOSFETs for Future CMOS Applications

NASA Astrophysics Data System (ADS)

Greene, Andrew M.

Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance source/drain contacts and growth on lattice mismatched substrates. Non-planar In0.53Ga0.47As FinFETs were developed using both "gate-first" and "gate-last" fabrication methods for n-channel MOSFETs. Electron beam lithography and anisotropic plasma etching processes were optimized to create highly scaled fins with near vertical sidewalls. Plasma damage was removed using a wet etch process and improvements in gate efficiency were characterized on MOS capacitor structures. A two-step, selective removal of the pre-grown n+ contact layer was developed for "gate-last" recess etching. The final In0.53Ga 0.47As FinFET devices demonstrated an ION = 70 mA/mm, I ON/IOFF ratio = 15,700 and sub-threshold swing = 210 mV/dec. Bulk GaSb and strained In0.36Ga0.64Sb quantum well (QW) heterostructures were developed for p-channel MOSFETs. Dit was reduced to 2 - 3 x 1012 cm-2eV-1 using an InAs surface layer, (NH4)2S passivation and atomic layer deposition (ALD) of Al2O3. A self-aligned "gate-first" In0.36Ga0.64Sb MOSFET fabrication process was invented using a "T-shaped" electron beam resist patterning stack and intermetallic source/drain contacts. Ni contacts annealed at 300°C demonstrated an ION = 166 mA/mm, ION/IOFF ratio = 1,500 and sub-threshold swing = 340 mV/dec. Split C-V measurements were used to extract an effective channel mobility of muh* = 300 cm2/Vs at Ns = 2 x 1012 cm -2. "Gate-last" MOSFETs grown with an epitaxial p + contact layer were fabricated using selective gate-recess etching techniques. A parasitic "n-channel" limited ION/I OFF ratio and sub-threshold swing, most likely due to effects from the InAs surface layer.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Nonlinear distortion analysis for single heterojunction GaAs HEMT with frequency and temperature

NASA Astrophysics Data System (ADS)

Alim, Mohammad A.; Ali, Mayahsa M.; Rezazadeh, Ali A.

2018-07-01

Nonlinearity analysis using two-tone intermodulation distortion (IMD) technique for 0.5 μm gate-length AlGaAs/GaAs based high electron mobility transistor have been investigated based on biasing conditions, input power, frequency and temperature. The outcomes indicate a significant modification on the output IMD power and as well as the minimum distortion level. The input IMD power effects the output current and subsequently the threshold voltage reduces, resulting to an increment in the output IMD power. Both frequency and temperature reduces the magnitude of the output IMDs. In addition, the threshold voltage response with temperature alters the notch point of the nonlinear output IMD’s accordingly. The aforementioned investigation will help the circuit designers to evaluate the best biasing option in terms of minimum distortion, maximum gain for future design optimizations.

The development of an interim generalized gate logic software simulator

NASA Technical Reports Server (NTRS)

Mcgough, J. G.; Nemeroff, S.

1985-01-01

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

PubMed

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Versatile and Programmable DNA Logic Gates on Universal and Label-Free Homogeneous Electrochemical Platform.

PubMed

Ge, Lei; Wang, Wenxiao; Sun, Ximei; Hou, Ting; Li, Feng

2016-10-04

Herein, a novel universal and label-free homogeneous electrochemical platform is demonstrated, on which a complete set of DNA-based two-input Boolean logic gates (OR, NAND, AND, NOR, INHIBIT, IMPLICATION, XOR, and XNOR) is constructed by simply and rationally deploying the designed DNA polymerization/nicking machines without complicated sequence modulation. Single-stranded DNA is employed as the proof-of-concept target/input to initiate or prevent the DNA polymerization/nicking cyclic reactions on these DNA machines to synthesize numerous intact G-quadruplex sequences or binary G-quadruplex subunits as the output. The generated output strands then self-assemble into G-quadruplexes that render remarkable decrease to the diffusion current response of methylene blue and, thus, provide the amplified homogeneous electrochemical readout signal not only for the logic gate operations but also for the ultrasensitive detection of the target/input. This system represents the first example of homogeneous electrochemical logic operation. Importantly, the proposed homogeneous electrochemical logic gates possess the input/output homogeneity and share a constant output threshold value. Moreover, the modular design of DNA polymerization/nicking machines enables the adaptation of these homogeneous electrochemical logic gates to various input and output sequences. The results of this study demonstrate the versatility and universality of the label-free homogeneous electrochemical platform in the design of biomolecular logic gates and provide a potential platform for the further development of large-scale DNA-based biocomputing circuits and advanced biosensors for multiple molecular targets.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Compact high voltage solid state switch

DOEpatents

Glidden, Steven C.

2003-09-23

A compact, solid state, high voltage switch capable of high conduction current with a high rate of current risetime (high di/dt) that can be used to replace thyratrons in existing and new applications. The switch has multiple thyristors packaged in a single enclosure. Each thyristor has its own gate drive circuit that circuit obtains its energy from the energy that is being switched in the main circuit. The gate drives are triggered with a low voltage, low current pulse isolated by a small inexpensive transformer. The gate circuits can also be triggered with an optical signal, eliminating the trigger transformer altogether. This approach makes it easier to connect many thyristors in series to obtain the hold off voltages of greater than 80 kV.

Heterogeneous integration of low-temperature metal-oxide TFTs

NASA Astrophysics Data System (ADS)

Schuette, Michael L.; Green, Andrew J.; Leedy, Kevin D.; McCandless, Jonathan P.; Jessen, Gregg H.

2017-02-01

The breadth of circuit fabrication opportunities enabled by metal-oxide thin-film transistors (MO-TFTs) is unprecedented. Large-area deposition techniques and high electron mobility are behind their adoption in the display industry, and substrate agnosticism and low process temperatures enabled the present wave of flexible electronics research. Reports of circuits involving complementaryMO-TFTs, oxide-organic hybrid combinations, and even MO-TFTs integrated onto Si LSI back end of line interconnects demonstrate this technology's utility in 2D and 3D monolithic heterogeneous integration (HI). In addition to a brief literature review focused on functional HI between MO-TFTs and a variety of dissimilar active devices, we share progress toward integrating MO-TFTs with compound semiconductor devices, namely GaN HEMTs. A monolithically integrated cascode topology was used to couple a HEMT's >200 V breakdown characteristic with the gate driving characteristic of an IGZO TFT, effectively shifting the HEMT threshold voltage from -3 V to +1 V.

A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology.

PubMed

Zhao, Hong-Quan; Kasai, Seiya; Shiratori, Yuta; Hashizume, Tamotsu

2009-06-17

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.

ONE SHAKE GATE FORMER

DOEpatents

Kalibjian, R.; Perez-Mendez, V.

1957-08-20

An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

p53 activated by AND gate genetic circuit under radiation and hypoxia for targeted cancer gene therapy.

PubMed

Ding, Miao; Li, Rong; He, Rong; Wang, Xingyong; Yi, Qijian; Wang, Weidong

2015-09-01

Radio-activated gene therapy has been developed as a novel therapeutic strategy against cancer; however, expression of therapeutic gene in peritumoral tissues will result in unacceptable toxicity to normal cells. To restrict gene expression in targeted tumor mass, we used hypoxia and radiation tolerance features of tumor cells to develop a synthetic AND gate genetic circuit through connecting radiation sensitivity promoter cArG6 , heat shock response elements SNF1, HSF1 and HSE4 with retroviral vector plxsn. Their construction and dynamic activity process were identified through downstream enhanced green fluorescent protein and wtp53 expression in non-small cell lung cancer A549 cells and in a nude mice model. The result showed that AND gate genetic circuit could be activated by lower required radiation dose (6 Gy) and after activated, AND gate could induce significant apoptosis effects and growth inhibition of cancer cells in vitro and in vivo. The radiation- and hypoxia-activated AND gate genetic circuit, which could lead to more powerful target tumoricidal activity represented a promising strategy for both targeted and effective gene therapy of human lung adenocarcinoma and low dose activation character of the AND gate genetic circuit implied that this model could be further exploited to decrease side-effects of clinical radiation therapy. © 2015 The Authors. Cancer Science published by Wiley Publishing Asia Pty Ltd on behalf of Japanese Cancer Association.

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

NASA Astrophysics Data System (ADS)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Aerosol jet printed p- and n-type electrolyte-gated transistors with a variety of electrode materials: exploring practical routes to printed electronics.

PubMed

Hong, Kihyon; Kim, Se Hyun; Mahajan, Ankit; Frisbie, C Daniel

2014-11-12

Printing electrically functional liquid inks is a promising approach for achieving low-cost, large-area, additive manufacturing of flexible electronic circuits. To print thin-film transistors, a basic building block of thin-film electronics, it is important to have several options for printable electrode materials that exhibit high conductivity, high stability, and low-cost. Here we report completely aerosol jet printed (AJP) p- and n-type electrolyte-gated transistors (EGTs) using a variety of different electrode materials including highly conductive metal nanoparticles (Ag), conducting polymers (polystyrenesulfonate doped poly(3,4-ethylendedioxythiophene, PEDOT:PSS), transparent conducting oxides (indium tin oxide), and carbon-based materials (reduced graphene oxide). Using these source-drain electrode materials and a PEDOT:PSS/ion gel gate stack, we demonstrated all-printed p- and n-type EGTs in combination with poly(3-hexythiophene) and ZnO semiconductors. All transistor components (including electrodes, semiconductors, and gate insulators) were printed by AJP. Both kinds of devices showed typical p- and n-type transistor characteristics, and exhibited both low-threshold voltages (<2 V) and high hole and electron mobilities. Our assessment suggests Ag electrodes may be the best option in terms of overall performance for both types of EGTs.

Ripple gate drive circuit for fast operation of series connected IGBTs

DOEpatents

Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

2005-09-20

A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

Compiling quantum circuits to realistic hardware architectures using temporal planners

NASA Astrophysics Data System (ADS)

Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

2018-04-01

To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

THRESHOLD LOGIC.

DTIC Science & Technology

synthesis procedures; a ’best’ method is definitely established. (2) ’Symmetry Types for Threshold Logic’ is a tutorial expositon including a careful...development of the Goto-Takahasi self-dual type ideas. (3) ’Best Threshold Gate Decisions’ reports a comparison, on the 2470 7-argument threshold ...interpretation is shown best. (4) ’ Threshold Gate Networks’ reviews the previously discussed 2-algorithm in geometric terms, describes our FORTRAN

Genomic Mining of Prokaryotic Repressors for Orthogonal Logic Gates

PubMed Central

Stanton, Brynne C.; Nielsen, Alec A.K.; Tamsir, Alvin; Clancy, Kevin; Peterson, Todd; Voigt, Christopher A.

2014-01-01

Genetic circuits perform computational operations based on interactions between freely diffusing molecules within a cell. When transcription factors are combined to build a circuit, unintended interactions can disrupt its function. Here, we apply “part mining” to build a library of 73 TetR-family repressors gleaned from prokaryotic genomes. The operators of a subset were determined using an in vitro method and this information was used to build synthetic promoters. The promoters and repressors were screened for cross-reactions. Of these, 16 were identified that both strongly repress their cognate promoter (5- to 207-fold) and do not interact with other promoters. Each repressor:promoter pair was converted to a NOT gate and characterized. Used as a set of 16 NOR gates, there are >1054 circuits that could be built by changing the pattern of input and output promoters. This represents a large set of compatible gates that can be used to construct user-defined circuits. PMID:24316737

Fault-tolerant logical gates in quantum error-correcting codes

NASA Astrophysics Data System (ADS)

Pastawski, Fernando; Yoshida, Beni

2015-01-01

Recently, S. Bravyi and R. König [Phys. Rev. Lett. 110, 170503 (2013), 10.1103/PhysRevLett.110.170503] have shown that there is a trade-off between fault-tolerantly implementable logical gates and geometric locality of stabilizer codes. They consider locality-preserving operations which are implemented by a constant-depth geometrically local circuit and are thus fault tolerant by construction. In particular, they show that, for local stabilizer codes in D spatial dimensions, locality-preserving gates are restricted to a set of unitary gates known as the D th level of the Clifford hierarchy. In this paper, we explore this idea further by providing several extensions and applications of their characterization to qubit stabilizer and subsystem codes. First, we present a no-go theorem for self-correcting quantum memory. Namely, we prove that a three-dimensional stabilizer Hamiltonian with a locality-preserving implementation of a non-Clifford gate cannot have a macroscopic energy barrier. This result implies that non-Clifford gates do not admit such implementations in Haah's cubic code and Michnicki's welded code. Second, we prove that the code distance of a D -dimensional local stabilizer code with a nontrivial locality-preserving m th -level Clifford logical gate is upper bounded by O (LD +1 -m) . For codes with non-Clifford gates (m >2 ), this improves the previous best bound by S. Bravyi and B. Terhal [New. J. Phys. 11, 043029 (2009), 10.1088/1367-2630/11/4/043029]. Topological color codes, introduced by H. Bombin and M. A. Martin-Delgado [Phys. Rev. Lett. 97, 180501 (2006), 10.1103/PhysRevLett.97.180501; Phys. Rev. Lett. 98, 160502 (2007), 10.1103/PhysRevLett.98.160502; Phys. Rev. B 75, 075103 (2007), 10.1103/PhysRevB.75.075103], saturate the bound for m =D . Third, we prove that the qubit erasure threshold for codes with a nontrivial transversal m th -level Clifford logical gate is upper bounded by 1 /m . This implies that no family of fault-tolerant codes with transversal gates in increasing level of the Clifford hierarchy may exist. This result applies to arbitrary stabilizer and subsystem codes and is not restricted to geometrically local codes. Fourth, we extend the result of Bravyi and König to subsystem codes. Unlike stabilizer codes, the so-called union lemma does not apply to subsystem codes. This problem is avoided by assuming the presence of an error threshold in a subsystem code, and a conclusion analogous to that of Bravyi and König is recovered.

Hybrid architecture for encoded measurement-based quantum computation

PubMed Central

Zwerger, M.; Briegel, H. J.; Dür, W.

2014-01-01

We present a hybrid scheme for quantum computation that combines the modular structure of elementary building blocks used in the circuit model with the advantages of a measurement-based approach to quantum computation. We show how to construct optimal resource states of minimal size to implement elementary building blocks for encoded quantum computation in a measurement-based way, including states for error correction and encoded gates. The performance of the scheme is determined by the quality of the resource states, where within the considered error model a threshold of the order of 10% local noise per particle for fault-tolerant quantum computation and quantum communication. PMID:24946906

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Synthesis of energy-efficient FSMs implemented in PLD circuits

NASA Astrophysics Data System (ADS)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Effects of plasma-induced charging damage on random telegraph noise in metal-oxide-semiconductor field-effect transistors with SiO2 and high-k gate dielectrics

NASA Astrophysics Data System (ADS)

Kamei, Masayuki; Takao, Yoshinori; Eriguchi, Koji; Ono, Kouichi

2014-01-01

We clarified in this study how plasma-induced charging damage (PCD) affects the so-called “random telegraph noise (RTN)” — a principal concern in designing ultimately scaled large-scale integrated circuits (LSIs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiO2 and high-k gate dielectric were exposed to an inductively coupled plasma (ICP) with Ar gas. Drain current vs gate voltage (Ids-Vg) characteristics were obtained before and after the ICP plasma exposure for the same device. Then, the time evolution of Ids fluctuation defined as Ids/μIds was measured, where μIds is the mean Ids. This value corresponds to an RTN feature, and RTN was obtained under various gate voltages (Vg) by a customized measurement technique. We focused on the statistical distribution width of (Ids/μIds), δ(Ids/μIds), in order to clarify the effects of PCD on RTN. δ(Ids/μIds) was increased by PCD for both MOSFETs with the SiO2 and high-k gate dielectrics, suggesting that RTN can be used as a measure of PCD, i.e., a distribution width increase directly indicates the presence of PCD. The dependence of δ(Ids/μIds) on the overdrive voltage Vg-Vth, where Vth is the threshold voltage, was investigated by the present technique. It was confirmed that δ(Ids/μIds) increased with a decrease in the overdrive voltage for MOSFETs with the SiO2 and high-k gate dielectrics. The presence of created carrier trap sites with PCD was characterized by the time constants for carrier capture and emission. The threshold voltage shift (ΔVth) induced by PCD was also evaluated and compared with the RTN change, to correlate the RTN increase with ΔVth induced by PCD. Although the estimated time constants exhibited complex behaviors due to the nature of trap sites created by PCD, δ(Ids/μIds) showed a straightforward tendency in accordance with the amount of PCD. These findings provide an in-depth understanding of plasma-induced RTN characteristic changes in future MOSFETs.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

A positive feedback at the cellular level promotes robustness and modulation at the circuit level

PubMed Central

Dethier, Julie; Drion, Guillaume; Franci, Alessio

2015-01-01

This article highlights the role of a positive feedback gating mechanism at the cellular level in the robustness and modulation properties of rhythmic activities at the circuit level. The results are presented in the context of half-center oscillators, which are simple rhythmic circuits composed of two reciprocally connected inhibitory neuronal populations. Specifically, we focus on rhythms that rely on a particular excitability property, the postinhibitory rebound, an intrinsic cellular property that elicits transient membrane depolarization when released from hyperpolarization. Two distinct ionic currents can evoke this transient depolarization: a hyperpolarization-activated cation current and a low-threshold T-type calcium current. The presence of a slow activation is specific to the T-type calcium current and provides a slow positive feedback at the cellular level that is absent in the cation current. We show that this slow positive feedback is required to endow the network rhythm with physiological modulation and robustness properties. This study thereby identifies an essential cellular property to be retained at the network level in modeling network robustness and modulation. PMID:26311181

Voltage-Boosting Driver For Switching Regulator

NASA Technical Reports Server (NTRS)

Trump, Ronald C.

1990-01-01

Driver circuit assures availability of 10- to 15-V gate-to-source voltage needed to turn on n-channel metal oxide/semiconductor field-effect transistor (MOSFET) acting as switch in switching voltage regulator. Includes voltage-boosting circuit efficiently providing gate voltage 10 to 15 V above supply voltage. Contains no exotic parts and does not require additional power supply. Consists of NAND gate and dual voltage booster operating in conjunction with pulse-width modulator part of regulator.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

PubMed

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Systematic Transfer of Prokaryotic Sensors and Circuits to Mammalian Cells

PubMed Central

2015-01-01

Prokaryotic regulatory proteins respond to diverse signals and represent a rich resource for building synthetic sensors and circuits. The TetR family contains >105 members that use a simple mechanism to respond to stimuli and bind distinct DNA operators. We present a platform that enables the transfer of these regulators to mammalian cells, which is demonstrated using human embryonic kidney (HEK293) and Chinese hamster ovary (CHO) cells. The repressors are modified to include nuclear localization signals (NLS) and responsive promoters are built by incorporating multiple operators. Activators are also constructed by modifying the protein to include a VP16 domain. Together, this approach yields 15 new regulators that demonstrate 19- to 551-fold induction and retain both the low levels of crosstalk in DNA binding specificity observed between the parent regulators in Escherichia coli, as well as their dynamic range of activity. By taking advantage of the DAPG small molecule sensing mediated by the PhlF repressor, we introduce a new inducible system with 50-fold induction and a threshold of 0.9 μM DAPG, which is comparable to the classic Dox-induced TetR system. A set of NOT gates is constructed from the new repressors and their response function quantified. Finally, the Dox- and DAPG- inducible systems and two new activators are used to build a synthetic enhancer (fuzzy AND gate), requiring the coordination of 5 transcription factors organized into two layers. This work introduces a generic approach for the development of mammalian genetic sensors and circuits to populate a toolbox that can be applied to diverse applications from biomanufacturing to living therapeutics. PMID:25360681

Systematic transfer of prokaryotic sensors and circuits to mammalian cells.

PubMed

Stanton, Brynne C; Siciliano, Velia; Ghodasara, Amar; Wroblewska, Liliana; Clancy, Kevin; Trefzer, Axel C; Chesnut, Jonathan D; Weiss, Ron; Voigt, Christopher A

2014-12-19

Prokaryotic regulatory proteins respond to diverse signals and represent a rich resource for building synthetic sensors and circuits. The TetR family contains >10(5) members that use a simple mechanism to respond to stimuli and bind distinct DNA operators. We present a platform that enables the transfer of these regulators to mammalian cells, which is demonstrated using human embryonic kidney (HEK293) and Chinese hamster ovary (CHO) cells. The repressors are modified to include nuclear localization signals (NLS) and responsive promoters are built by incorporating multiple operators. Activators are also constructed by modifying the protein to include a VP16 domain. Together, this approach yields 15 new regulators that demonstrate 19- to 551-fold induction and retain both the low levels of crosstalk in DNA binding specificity observed between the parent regulators in Escherichia coli, as well as their dynamic range of activity. By taking advantage of the DAPG small molecule sensing mediated by the PhlF repressor, we introduce a new inducible system with 50-fold induction and a threshold of 0.9 μM DAPG, which is comparable to the classic Dox-induced TetR system. A set of NOT gates is constructed from the new repressors and their response function quantified. Finally, the Dox- and DAPG- inducible systems and two new activators are used to build a synthetic enhancer (fuzzy AND gate), requiring the coordination of 5 transcription factors organized into two layers. This work introduces a generic approach for the development of mammalian genetic sensors and circuits to populate a toolbox that can be applied to diverse applications from biomanufacturing to living therapeutics.

Scalable randomized benchmarking of non-Clifford gates

NASA Astrophysics Data System (ADS)

Cross, Andrew; Magesan, Easwar; Bishop, Lev; Smolin, John; Gambetta, Jay

Randomized benchmarking is a widely used experimental technique to characterize the average error of quantum operations. Benchmarking procedures that scale to enable characterization of n-qubit circuits rely on efficient procedures for manipulating those circuits and, as such, have been limited to subgroups of the Clifford group. However, universal quantum computers require additional, non-Clifford gates to approximate arbitrary unitary transformations. We define a scalable randomized benchmarking procedure over n-qubit unitary matrices that correspond to protected non-Clifford gates for a class of stabilizer codes. We present efficient methods for representing and composing group elements, sampling them uniformly, and synthesizing corresponding poly (n) -sized circuits. The procedure provides experimental access to two independent parameters that together characterize the average gate fidelity of a group element. We acknowledge support from ARO under Contract W911NF-14-1-0124.

Implementation of a three-qubit refined Deutsch Jozsa algorithm using SFG quantum logic gates

NASA Astrophysics Data System (ADS)

DelDuce, A.; Savory, S.; Bayvel, P.

2006-05-01

In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Logic gate system with three outputs and three inputs based on switchable electrocatalysis of glucose by glucose oxidase entrapped in chitosan films.

PubMed

Liu, Shuang; Wang, Lei; Lian, Wenjing; Liu, Hongyun; Li, Chen-Zhong

2015-01-01

A logic-gate system with three outputs and three inputs was developed based on the bioelectrocatalysis of glucose by glucose oxidase (GOx) entrapped in chitosan films on the electrode surface by means of ferrocenedicarboxylic acid (Fc(COOH)2 ). Cyclic voltammetric (CV) signals of Fc(COOH)2 exhibited pH-triggered on/off behavior owing to electrostatic interactions between the film and the probe at different pH levels. The addition of glucose greatly increased the oxidation peak current (Ipa ) through the electrocatalytic reaction. pH and glucose were selected as two inputs. As a reversible inhibitor of GOx, Cu(2+) was chosen as the third input. The combination of three inputs led to Ipa with different values according to different mechanisms, which were defined as three outputs with two thresholds. The logic gate with three outputs by using one type of enzyme provided a novel model to build logic circuits based on biomacromolecules, which might be applied to the intelligent medical diagnostics as smart biosensors in the future. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Measurand transient signal suppressor

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr. (Inventor)

1994-01-01

A transient signal suppressor for use in a controls system which is adapted to respond to a change in a physical parameter whenever it crosses a predetermined threshold value in a selected direction of increasing or decreasing values with respect to the threshold value and is sustained for a selected discrete time interval is presented. The suppressor includes a sensor transducer for sensing the physical parameter and generating an electrical input signal whenever the sensed physical parameter crosses the threshold level in the selected direction. A manually operated switch is provided for adapting the suppressor to produce an output drive signal whenever the physical parameter crosses the threshold value in the selected direction of increasing or decreasing values. A time delay circuit is selectively adjustable for suppressing the transducer input signal for a preselected one of a plurality of available discrete suppression time and producing an output signal only if the input signal is sustained for a time greater than the selected suppression time. An electronic gate is coupled to receive the transducer input signal and the timer output signal and produce an output drive signal for energizing a control relay whenever the transducer input is a non-transient signal which is sustained beyond the selected time interval.

Quantum circuit dynamics via path integrals: Is there a classical action for discrete-time paths?

NASA Astrophysics Data System (ADS)

Penney, Mark D.; Enshan Koh, Dax; Spekkens, Robert W.

2017-07-01

It is straightforward to compute the transition amplitudes of a quantum circuit using the sum-over-paths methodology when the gates in the circuit are balanced, where a balanced gate is one for which all non-zero transition amplitudes are of equal magnitude. Here we consider the question of whether, for such circuits, the relative phases of different discrete-time paths through the configuration space can be defined in terms of a classical action, as they are for continuous-time paths. We show how to do so for certain kinds of quantum circuits, namely, Clifford circuits where the elementary systems are continuous-variable systems or discrete systems of odd-prime dimension. These types of circuit are distinguished by having phase-space representations that serve to define their classical counterparts. For discrete systems, the phase-space coordinates are also discrete variables. We show that for each gate in the generating set, one can associate a symplectomorphism on the phase-space and to each of these one can associate a generating function, defined on two copies of the configuration space. For discrete systems, the latter association is achieved using tools from algebraic geometry. Finally, we show that if the action functional for a discrete-time path through a sequence of gates is defined using the sum of the corresponding generating functions, then it yields the correct relative phases for the path-sum expression. These results are likely to be relevant for quantizing physical theories where time is fundamentally discrete, characterizing the classical limit of discrete-time quantum dynamics, and proving complexity results for quantum circuits.

Universal programmable quantum circuit schemes to emulate an operator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantummore » complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.« less

A microwave field-driven transistor-like skyrmionic device with the microwave current-assisted skyrmion creation

NASA Astrophysics Data System (ADS)

Xia, Jing; Huang, Yangqi; Zhang, Xichao; Kang, Wang; Zheng, Chentian; Liu, Xiaoxi; Zhao, Weisheng; Zhou, Yan

2017-10-01

Magnetic skyrmion is a topologically protected domain-wall structure at nanoscale, which could serve as a basic building block for advanced spintronic devices. Here, we propose a microwave field-driven skyrmionic device with the transistor-like function, where the motion of a skyrmion in a voltage-gated ferromagnetic nanotrack is studied by micromagnetic simulations. It is demonstrated that the microwave field can drive the motion of a skyrmion by exciting the propagating spin waves, and the skyrmion motion can be governed by a gate voltage. We also investigate the microwave current-assisted creation of a skyrmion to facilitate the operation of the transistor-like skyrmionic device on the source terminal. It is found that the microwave current with an appropriate frequency can reduce the threshold current density required for the creation of a skyrmion from the ferromagnetic background. The proposed transistor-like skyrmionic device operated with the microwave field and current could be useful for building future skyrmion-based circuits.

Giant nonlinear interaction between two optical beams via a quantum dot embedded in a photonic wire

NASA Astrophysics Data System (ADS)

Nguyen, H. A.; Grange, T.; Reznychenko, B.; Yeo, I.; de Assis, P.-L.; Tumanov, D.; Fratini, F.; Malik, N. S.; Dupuy, E.; Gregersen, N.; Auffèves, A.; Gérard, J.-M.; Claudon, J.; Poizat, J.-Ph.

2018-05-01

Optical nonlinearities usually appear for large intensities, but discrete transitions allow for giant nonlinearities operating at the single-photon level. This has been demonstrated in the last decade for a single optical mode with cold atomic gases, or single two-level systems coupled to light via a tailored photonic environment. Here, we demonstrate a two-mode giant nonlinearity with a single semiconductor quantum dot (QD) embedded in a photonic wire antenna. We exploit two detuned optical transitions associated with the exciton-biexciton QD level scheme. Owing to the broadband waveguide antenna, the two transitions are efficiently interfaced with two free-space laser beams. The reflection of one laser beam is then controlled by the other beam, with a threshold power as low as 10 photons per exciton lifetime (1.6 nW ). Such a two-color nonlinearity opens appealing perspectives for the realization of ultralow-power logical gates and optical quantum gates, and could also be implemented in an integrated photonic circuit based on planar waveguides.

Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

NASA Astrophysics Data System (ADS)

Akkala, Arun Goud

Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A lifetime projection is carried out assuming that HCI is the major degradation mechanism and it is shown that a 3.4x improvement in device lifetime is possible over symmetric underlapped n-FinFET.

FLOW GATING

DOEpatents

Poppelbaum, W.J.

1962-12-01

BS>This invention is a fast gating system for eiectronic flipflop circuits. Diodes connect the output of one circuit to the input of another, and the voltage supply for the receiving flip-flop has two alternate levels. When the supply is at its upper level, no current can flow through the diodes, but when the supply is at its lower level, current can flow to set the receiving flip- flop to the same state as that of the circuit to which it is connected. (AEC)

Continuous-variable gate decomposition for the Bose-Hubbard model

NASA Astrophysics Data System (ADS)

Kalajdzievski, Timjan; Weedbrook, Christian; Rebentrost, Patrick

2018-06-01

In this work, we decompose the time evolution of the Bose-Hubbard model into a sequence of logic gates that can be implemented on a continuous-variable photonic quantum computer. We examine the structure of the circuit that represents this time evolution for one-dimensional and two-dimensional lattices. The elementary gates needed for the implementation are counted as a function of lattice size. We also include the contribution of the leading dipole interaction term which may be added to the Hamiltonian and its corresponding circuit.

Multi-strategy based quantum cost reduction of linear nearest-neighbor quantum circuit

NASA Astrophysics Data System (ADS)

Tan, Ying-ying; Cheng, Xue-yun; Guan, Zhi-jin; Liu, Yang; Ma, Haiying

2018-03-01

With the development of reversible and quantum computing, study of reversible and quantum circuits has also developed rapidly. Due to physical constraints, most quantum circuits require quantum gates to interact on adjacent quantum bits. However, many existing quantum circuits nearest-neighbor have large quantum cost. Therefore, how to effectively reduce quantum cost is becoming a popular research topic. In this paper, we proposed multiple optimization strategies to reduce the quantum cost of the circuit, that is, we reduce quantum cost from MCT gates decomposition, nearest neighbor and circuit simplification, respectively. The experimental results show that the proposed strategies can effectively reduce the quantum cost, and the maximum optimization rate is 30.61% compared to the corresponding results.

Implementing conventional logic unconventionally: photochromic molecular populations as registers and logic gates.

PubMed

Chaplin, J C; Russell, N A; Krasnogor, N

2012-07-01

In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

A quantum Fredkin gate.

PubMed

Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

2016-03-01

Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

Use of laser drilling in the manufacture of organic inverter circuits.

PubMed

Iba, Shingo; Kato, Yusaku; Sekitani, Tsuyoshi; Kawaguchi, Hiroshi; Sakurai, Takayasu; Someya, Takao

2006-01-01

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

Experimental Demonstration of a Resonator-Induced Phase Gate in a Multiqubit Circuit-QED System.

PubMed

Paik, Hanhee; Mezzacapo, A; Sandberg, Martin; McClure, D T; Abdo, B; Córcoles, A D; Dial, O; Bogorin, D F; Plourde, B L T; Steffen, M; Cross, A W; Gambetta, J M; Chow, Jerry M

2016-12-16

The resonator-induced phase (RIP) gate is an all-microwave multiqubit entangling gate that allows a high degree of flexibility in qubit frequencies, making it attractive for quantum operations in large-scale architectures. We experimentally realize the RIP gate with four superconducting qubits in a three-dimensional circuit-QED architecture, demonstrating high-fidelity controlled-z (cz) gates between all possible pairs of qubits from two different 4-qubit devices in pair subspaces. These qubits are arranged within a wide range of frequency detunings, up to as large as 1.8 GHz. We further show a dynamical multiqubit refocusing scheme in order to isolate out 2-qubit interactions, and combine them to generate a 4-qubit Greenberger-Horne-Zeilinger state.

Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

DOEpatents

Passmore, Brandon; Cole, Zach; Whitaker, Bret; Barkley, Adam; McNutt, Ty; Lostetter, Alexander

2016-08-02

A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

A parallel algorithm for multi-level logic synthesis using the transduction method. M.S. Thesis

NASA Technical Reports Server (NTRS)

Lim, Chieng-Fai

1991-01-01

The Transduction Method has been shown to be a powerful tool in the optimization of multilevel networks. Many tools such as the SYLON synthesis system (X90), (CM89), (LM90) have been developed based on this method. A parallel implementation is presented of SYLON-XTRANS (XM89) on an eight processor Encore Multimax shared memory multiprocessor. It minimizes multilevel networks consisting of simple gates through parallel pruning, gate substitution, gate merging, generalized gate substitution, and gate input reduction. This implementation, called Parallel TRANSduction (PTRANS), also uses partitioning to break large circuits up and performs inter- and intra-partition dynamic load balancing. With this, good speedups and high processor efficiencies are achievable without sacrificing the resulting circuit quality.

Implementing N-quantum phase gate via circuit QED with qubit-qubit interaction

NASA Astrophysics Data System (ADS)

Said, T.; Chouikh, A.; Essammouni, K.; Bennai, M.

2016-02-01

We propose a method for realizing a quantum phase gate of one qubit simultaneously controlling N target qubits based on the qubit-qubit interaction. We show how to implement the proposed gate with one transmon qubit simultaneously controlling N transmon qubits in a circuit QED driven by a strong microwave field. In our scheme, the operation time of this phase gate is independent of the number N of qubits. On the other hand, this gate can be realized in a time of nanosecond-scale much smaller than the decoherence time and dephasing time both being the time of microsecond-scale. Numerical simulation of the occupation probabilities of the second excited lever shows that the scheme could be achieved efficiently within current technology.

Experimental Demonstration of a Resonator-Induced Phase Gate in a Multiqubit Circuit-QED System

NASA Astrophysics Data System (ADS)

Paik, Hanhee; Mezzacapo, A.; Sandberg, Martin; McClure, D. T.; Abdo, B.; Córcoles, A. D.; Dial, O.; Bogorin, D. F.; Plourde, B. L. T.; Steffen, M.; Cross, A. W.; Gambetta, J. M.; Chow, Jerry M.

2016-12-01

The resonator-induced phase (RIP) gate is an all-microwave multiqubit entangling gate that allows a high degree of flexibility in qubit frequencies, making it attractive for quantum operations in large-scale architectures. We experimentally realize the RIP gate with four superconducting qubits in a three-dimensional circuit-QED architecture, demonstrating high-fidelity controlled-z (cz) gates between all possible pairs of qubits from two different 4-qubit devices in pair subspaces. These qubits are arranged within a wide range of frequency detunings, up to as large as 1.8 GHz. We further show a dynamical multiqubit refocusing scheme in order to isolate out 2-qubit interactions, and combine them to generate a 4-qubit Greenberger-Horne-Zeilinger state.

MULTIPLIER CIRCUIT

DOEpatents

Thomas, R.E.

1959-01-20

An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

NASA Astrophysics Data System (ADS)

Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Investigation of short-circuit failure mechanisms of SiC MOSFETs by varying DC bus voltage

NASA Astrophysics Data System (ADS)

Namai, Masaki; An, Junjie; Yano, Hiroshi; Iwamuro, Noriyuki

2018-07-01

In this study, the experimental evaluation and numerical analysis of short-circuit mechanisms of 1200 V SiC planar and trench MOSFETs were conducted at various DC bus voltages from 400 to 800 V. Investigation of the impact of DC bus voltage on short-circuit capability yielded results that are extremely useful for many existing power electronics applications. Three failure mechanisms were identified in this study: thermal runaway, MOS channel current following device turn-off, and rupture of the gate oxide layer (gate oxide layer damage). The SiC MOSFETs experienced lattice temperatures exceeding 1000 K during the short-circuit transient; as Si insulated gate bipolar transistors (IGBTs) are not typically subject to such temperatures, the MOSFETs experienced distinct failure modes, and the mode experienced was significantly influenced by the DC bus voltage. In conclusion, suggestions regarding the SiC MOSFET design and operation methods that would enhance device robustness are proposed.

An Extension to the Multilevel Logic Simulator for Microcomputers.

DTIC Science & Technology

1987-06-01

gates .............................. 61 3. Add or delete inputs ............................... 61 4. Add or delete outputs...the gates affected by the deletion. 61 4. Add or delete outputs The only modification that will be done in the circuit is the insertion (deletion) of...recompilation of the circuit. P 105 -Z -- % % 9,m "N , " " " " " ’ ’-"" " " " " " " " - -" , " " -- -" - .’ TABLE 25 THE DELINP CASE FOR THE ALU CIRCUIT JI

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fast-responding short circuit protection system with self-reset for use in circuit supplied by DC power

NASA Technical Reports Server (NTRS)

Burns, Bradley M. (Inventor); Blalock, Norman N. (Inventor)

2011-01-01

A short circuit protection system includes an inductor, a switch, a voltage sensing circuit, and a controller. The switch and inductor are electrically coupled to be in series with one another. A voltage sensing circuit is coupled across the switch and the inductor. A controller, coupled to the voltage sensing circuit and the switch, opens the switch when a voltage at the output terminal of the inductor transitions from above a threshold voltage to below the threshold voltage. The controller closes the switch when the voltage at the output terminal of the inductor transitions from below the threshold voltage to above the threshold voltage.

Reversible logic gates on Physarum Polycephalum

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schumann, Andrew

2015-03-10

In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

NASA Astrophysics Data System (ADS)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

PubMed

Nair, Aswathi; Bhattacharya, Prasenjit; Sambandan, Sanjiv

2017-12-20

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

Simulation and parametric analysis of graphene p-n junctions with two rectangular top gates and a single back gate

NASA Astrophysics Data System (ADS)

Nikiforidis, Ioannis; Karafyllidis, Ioannis G.; Dimitrakis, Panagiotis

2018-02-01

Graphene p-n junctions could be the building blocks of future nanoelectronic circuits. While the conductance modulation of graphene p-n junctions formed in devices with one bottom and one top gate have received much attention, there is comparatively little work done on devices with two top gates. Here, we employ tight-bind Hamiltonians and non-equilibrium Green function method to compute in a systematic way the dependence of the conductance of graphene p-n junctions, formed in a device with two top gates, on the device parameters. We present our results in a compact and systematic way, so that the effect of each parameter is clearly shown. Our results show that the device conductance can be effectively modulated, and that graphene devices with two top gates may be used as basic elements in future carbon-based nanoelectronic circuits.

Hybrid quantum gates between flying photon and diamond nitrogen-vacancy centers assisted by optical microcavities

PubMed Central

Wei, Hai-Rui; Lu Long, Gui

2015-01-01

Hybrid quantum gates hold great promise for quantum information processing since they preserve the advantages of different quantum systems. Here we present compact quantum circuits to deterministically implement controlled-NOT, Toffoli, and Fredkin gates between a flying photon qubit and diamond nitrogen-vacancy (NV) centers assisted by microcavities. The target qubits of these universal quantum gates are encoded on the spins of the electrons associated with the diamond NV centers and they have long coherence time for storing information, and the control qubit is encoded on the polarizations of the flying photon and can be easily manipulated. Our quantum circuits are compact, economic, and simple. Moreover, they do not require additional qubits. The complexity of our schemes for universal three-qubit gates is much reduced, compared to the synthesis with two-qubit entangling gates. These schemes have high fidelities and efficiencies, and they are feasible in experiment. PMID:26271899

Universal quantum gates on electron-spin qubits with quantum dots inside single-side optical microcavities.

PubMed

Wei, Hai-Rui; Deng, Fu-Guo

2014-01-13

We present some compact quantum circuits for a deterministic quantum computing on electron-spin qubits assisted by quantum dots inside single-side optical microcavities, including the CNOT, Toffoli, and Fredkin gates. They are constructed by exploiting the giant optical Faraday rotation induced by a single-electron spin in a quantum dot inside a single-side optical microcavity as a result of cavity quantum electrodynamics. Our universal quantum gates have some advantages. First, all the gates are accomplished with a success probability of 100% in principle. Second, our schemes require no additional electron-spin qubits and they are achieved by some input-output processes of a single photon. Third, our circuits for these gates are simple and economic. Moreover, our devices for these gates work in both the weak coupling and the strong coupling regimes, and they are feasible in experiment.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Superconducting flux flow digital circuits

DOEpatents

Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

1995-01-01

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

From Anxious to Reckless: A Control Systems Approach Unifies Prefrontal-Limbic Regulation Across the Spectrum of Threat Detection.

PubMed

Mujica-Parodi, Lilianne R; Cha, Jiook; Gao, Jonathan

2017-01-01

Here we provide an integrative review of basic control circuits, and introduce techniques by which their regulation can be quantitatively measured using human neuroimaging. We illustrate the utility of the control systems approach using four human neuroimaging threat detection studies ( N = 226), to which we applied circuit-wide analyses in order to identify the key mechanism underlying individual variation. In so doing, we build upon the canonical prefrontal-limbic control system to integrate circuit-wide influence from the inferior frontal gyrus (IFG). These were incorporated into a computational control systems model constrained by neuroanatomy and designed to replicate our experimental data. In this model, the IFG acts as an informational set point, gating signals between the primary prefrontal-limbic negative feedback loop and its cortical information-gathering loop. Along the cortical route, if the sensory cortex provides sufficient information to make a threat assessment, the signal passes to the ventromedial prefrontal cortex (vmPFC), whose threat-detection threshold subsequently modulates amygdala outputs. However, if signal outputs from the sensory cortex do not provide sufficient information during the first pass, the signal loops back to the sensory cortex, with each cycle providing increasingly fine-grained processing of sensory data. Simulations replicate IFG (chaotic) dynamics experimentally observed at both ends at the threat-detection spectrum. As such, they identify distinct types of IFG disconnection from the circuit, with associated clinical outcomes. If IFG thresholds are too high, the IFG and sensory cortex cycle for too long; in the meantime the coarse-grained (excitatory) pathway will dominate, biasing ambiguous stimuli as false positives. On the other hand, if cortical IFG thresholds are too low, the inhibitory pathway will suppress the amygdala without cycling back to the sensory cortex for much-needed fine-grained sensory cortical data, biasing ambiguous stimuli as false negatives. Thus, the control systems model provides a consistent mechanism for IFG regulation, capable of producing results consistent with our data for the full spectrum of threat-detection: from fearful to optimal to reckless. More generally, it illustrates how quantitative characterization of circuit dynamics can be used to unify a fundamental dimension across psychiatric affective symptoms, with implications for populations that range from anxiety disorders to addiction.

Genetic circuit design automation.

PubMed

Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A

2016-04-01

Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization. Copyright © 2016, American Association for the Advancement of Science.

A spatially localized architecture for fast and modular DNA computing

NASA Astrophysics Data System (ADS)

Chatterjee, Gourab; Dalchau, Neil; Muscat, Richard A.; Phillips, Andrew; Seelig, Georg

2017-09-01

Cells use spatial constraints to control and accelerate the flow of information in enzyme cascades and signalling networks. Synthetic silicon-based circuitry similarly relies on spatial constraints to process information. Here, we show that spatial organization can be a similarly powerful design principle for overcoming limitations of speed and modularity in engineered molecular circuits. We create logic gates and signal transmission lines by spatially arranging reactive DNA hairpins on a DNA origami. Signal propagation is demonstrated across transmission lines of different lengths and orientations and logic gates are modularly combined into circuits that establish the universality of our approach. Because reactions preferentially occur between neighbours, identical DNA hairpins can be reused across circuits. Co-localization of circuit elements decreases computation time from hours to minutes compared to circuits with diffusible components. Detailed computational models enable predictive circuit design. We anticipate our approach will motivate using spatial constraints for future molecular control circuit designs.

Superconducting flux flow digital circuits

DOEpatents

Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

1995-02-14

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

A quantum Fredkin gate

PubMed Central

Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

2016-01-01

Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

GaAs circuits for monolithic optical controller

NASA Technical Reports Server (NTRS)

Gustafson, G.; Bendett, M.; Carney, J.; Mactaggart, R.; Palmquist, S.

1988-01-01

GaAs circuits for use in a fully monolithic 1 Gb/s optical controller have been developed and tested. The circuits include photodetectors, transimpedance amplifiers and 1:16 demultiplexers that can directly control the phase of MMIC phase shifters. The entire chip contains approximately 300 self-aligned gate E/D-mode MESFETs. The MESFETs have one micron-wide gate and the E-mode FETs typically have transconductance of 200 ms/mm. Results of simulations and tests are reported. Also, the design and layout of the fully monolithic chip is discussed.

Analysis and Modeling of Fullerene Single Electron Transistor Based on Quantum Dot Arrays at Room Temperature

NASA Astrophysics Data System (ADS)

Khadem Hosseini, Vahideh; Ahmadi, Mohammad Taghi; Ismail, Razali

2018-05-01

The single electron transistor (SET) as a fast electronic device is a candidate for future nanoscale circuits because of its low energy consumption, small size and simplified circuit. It consists of source and drain electrodes with a quantum dot (QD) located between them. Moreover, it operates based on the Coulomb blockade (CB) effect. It occurs when the charging energy is greater than the thermal energy. Consequently, this condition limits SET operation at cryogenic temperatures. Hence, using QD arrays can overcome this temperature limitation in SET which can therefore work at room temperature but QD arrays increase the threshold voltage with is an undesirable effect. In this research, fullerene as a zero-dimensional material with unique properties such as quantum capacitance and high critical temperature has been selected for the material of the QDs. Moreover, the current of a fullerene QD array SET has been modeled and its threshold voltage is also compared with a silicon QD array SET. The results show that the threshold voltage of fullerene SET is lower than the silicon one. Furthermore, the comparison study shows that homogeneous linear QD arrays have a lower CB range and better operation than a ring QD array SET. Moreover, the effect of the number of QDs in a QD array SET is investigated. The result confirms that the number of QDs can directly affect the CB range. Moreover, the desired current can be achieved by controlling the applied gate voltage and island diameters in a QD array SET.

Divide and control: split design of multi-input DNA logic gates.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2015-01-18

Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct.

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

NASA Astrophysics Data System (ADS)

Bilal, Bisma; Ahmed, Suhaib; Kakkar, Vipan

2018-02-01

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.

Ionizing radiation detector

DOEpatents

Thacker, Louis H.

1990-01-01

An ionizing radiation detector is provided which is based on the principle of analog electronic integration of radiation sensor currents in the sub-pico to nano ampere range between fixed voltage switching thresholds with automatic voltage reversal each time the appropriate threshold is reached. The thresholds are provided by a first NAND gate Schmitt trigger which is coupled with a second NAND gate Schmitt trigger operating in an alternate switching state from the first gate to turn either a visible or audible indicating device on and off in response to the gate switching rate which is indicative of the level of radiation being sensed. The detector can be configured as a small, personal radiation dosimeter which is simple to operate and responsive over a dynamic range of at least 0.01 to 1000 R/hr.

Inrush Current Suppression Circuit and Method for Controlling When a Load May Be Fully Energized

NASA Technical Reports Server (NTRS)

Schwerman, Paul (Inventor)

2017-01-01

A circuit and method for controlling when a load may be fully energized includes directing electrical current through a current limiting resistor that has a first terminal connected to a source terminal of a field effect transistor (FET), and a second terminal connected to a drain terminal of the FET. The gate voltage magnitude on a gate terminal of the FET is varied, whereby current flow through the FET is increased while current flow through the current limiting resistor is simultaneously decreased. A determination is made as to when the gate voltage magnitude on the gate terminal is equal to or exceeds a predetermined reference voltage magnitude, and the load is enabled to be fully energized when the gate voltage magnitude is equal to or exceeds the predetermined reference voltage magnitude.

High voltage and current, gate assisted, turn-off thyristor development

NASA Technical Reports Server (NTRS)

Nowalk, T. P.; Brewster, J. B.; Kao, Y. C.

1972-01-01

An improved high speed power switch with unique turn-off capability was developed. This gate assisted turn-off thyristor (GATT) was rated 1000 volts and 100 amperes with turn-off times of 2 microseconds. Fifty units were delivered for evaluation. In addition, test circuits designed to relate to the series inverter application were built and demonstrated. In the course of this work it was determined that the basic device design is adequate to meet the static characteristics and dynamic turn-off specification. It was further determined that the turn-on specification is critically dependent on the gate drive circuit due to the distributive nature of the cathode-gate geometry. Future work should emphasize design modifications which reduce the gate current required for fast turn-on, thereby opening the way to higher power (current) devices.

Dynamics of action potential initiation in the GABAergic thalamic reticular nucleus in vivo.

PubMed

Muñoz, Fabián; Fuentealba, Pablo

2012-01-01

Understanding the neural mechanisms of action potential generation is critical to establish the way neural circuits generate and coordinate activity. Accordingly, we investigated the dynamics of action potential initiation in the GABAergic thalamic reticular nucleus (TRN) using in vivo intracellular recordings in cats in order to preserve anatomically-intact axo-dendritic distributions and naturally-occurring spatiotemporal patterns of synaptic activity in this structure that regulates the thalamic relay to neocortex. We found a wide operational range of voltage thresholds for action potentials, mostly due to intrinsic voltage-gated conductances and not synaptic activity driven by network oscillations. Varying levels of synchronous synaptic inputs produced fast rates of membrane potential depolarization preceding the action potential onset that were associated with lower thresholds and increased excitability, consistent with TRN neurons performing as coincidence detectors. On the other hand the presence of action potentials preceding any given spike was associated with more depolarized thresholds. The phase-plane trajectory of the action potential showed somato-dendritic propagation, but no obvious axon initial segment component, prominent in other neuronal classes and allegedly responsible for the high onset speed. Overall, our results suggest that TRN neurons could flexibly integrate synaptic inputs to discharge action potentials over wide voltage ranges, and perform as coincidence detectors and temporal integrators, supported by a dynamic action potential threshold.

Active-Matrix Organic Light Emission Diode Pixel Circuit for Suppressing and Compensating for the Threshold Voltage Degradation of Hydrogenated Amorphous Silicon Thin Film Transistors

NASA Astrophysics Data System (ADS)

Shin, Hee-Sun; Lee, Won-Kyu; Park, Sang-Guen; Kuk, Seung-Hee; Han, Min-Koo

2009-03-01

A new hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) pixel circuit for active-matrix organic light emission diodes (AM-OLEDs), which significantly compensates the OLED current degradation by memorizing the threshold voltage of driving TFT and suppresses the threshold voltage shift of a-Si:H TFTs by negative bias annealing, is proposed and fabricated. During the first half of each frame, the driving TFT of the proposed pixel circuit supplies current to the OLED, which is determined by modified data voltage in the compensation scheme. The proposed pixel circuit was able to compensate the threshold voltage shift of the driving TFT as well as the OLED. During the remaining half of each frame, the proposed pixel circuit induces the recovery of the threshold voltage degradation of a-Si:H TFTs owing to the negative bias annealing. The experimental results show that the proposed pixel circuit was able to successfully compensate for the OLED current degradation and suppress the threshold voltage degradation of the driving TFT.

Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full adder cell. We have designed a 64-bit ALU with a gated clock. We have used negative latch based circuit for generating gated clock. This gated clock is used to control the multiplexer based 64-bit ALU. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. We have achieved 74.07%, 92. 93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

NASA Astrophysics Data System (ADS)

Ogiwara, Akifumi; Maekawa, Hikaru; Watanabe, Minoru; Moriwaki, Retsu

2014-02-01

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme

NASA Astrophysics Data System (ADS)

Shinya, A.; Ishihara, T.; Inoue, K.; Nozaki, K.; Kita, S.; Notomi, M.

2018-02-01

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

NASA Astrophysics Data System (ADS)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology. Electronic supplementary information (ESI) available: Additional figures (Table S1, Fig. S1-S5). See DOI: 10.1039/c4nr01676a

Four-gate transistor analog multiplier circuit

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

2011-01-01

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Proctor, Timothy; Rudinger, Kenneth; Young, Kevin

Randomized benchmarking (RB) is widely used to measure an error rate of a set of quantum gates, by performing random circuits that would do nothing if the gates were perfect. In the limit of no finite-sampling error, the exponential decay rate of the observable survival probabilities, versus circuit length, yields a single error metric r. For Clifford gates with arbitrary small errors described by process matrices, r was believed to reliably correspond to the mean, over all Clifford gates, of the average gate infidelity between the imperfect gates and their ideal counterparts. We show that this quantity is not amore » well-defined property of a physical gate set. It depends on the representations used for the imperfect and ideal gates, and the variant typically computed in the literature can differ from r by orders of magnitude. We present new theories of the RB decay that are accurate for all small errors describable by process matrices, and show that the RB decay curve is a simple exponential for all such errors. Here, these theories allow explicit computation of the error rate that RB measures (r), but as far as we can tell it does not correspond to the infidelity of a physically allowed (completely positive) representation of the imperfect gates.« less

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Monitoring Digital Closed-Loop Feedback Systems

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

Quantum realization of the nearest-neighbor interpolation method for FRQI and NEQR

NASA Astrophysics Data System (ADS)

Sang, Jianzhi; Wang, Shen; Niu, Xiamu

2016-01-01

This paper is concerned with the feasibility of the classical nearest-neighbor interpolation based on flexible representation of quantum images (FRQI) and novel enhanced quantum representation (NEQR). Firstly, the feasibility of the classical image nearest-neighbor interpolation for quantum images of FRQI and NEQR is proven. Then, by defining the halving operation and by making use of quantum rotation gates, the concrete quantum circuit of the nearest-neighbor interpolation for FRQI is designed for the first time. Furthermore, quantum circuit of the nearest-neighbor interpolation for NEQR is given. The merit of the proposed NEQR circuit lies in their low complexity, which is achieved by utilizing the halving operation and the quantum oracle operator. Finally, in order to further improve the performance of the former circuits, new interpolation circuits for FRQI and NEQR are presented by using Control-NOT gates instead of a halving operation. Simulation results show the effectiveness of the proposed circuits.

Designing Novel Quaternary Quantum Reversible Subtractor Circuits

NASA Astrophysics Data System (ADS)

Haghparast, Majid; Monfared, Asma Taheri

2018-01-01

Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack (TMGS) DG-MOSFET

NASA Astrophysics Data System (ADS)

Tripathi, Shweta

2016-10-01

In the present work, a two-dimensional (2D) analytical framework of triple material symmetrical gate stack (TMGS) DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS™ device simulator to affirm and formalize the proposed device structure.

A Rhizobium radiobacter Histidine Kinase Can Employ Both Boolean AND and OR Logic Gates to Initiate Pathogenesis.

PubMed

Fang, Fang; Lin, Yi-Han; Pierce, B Daniel; Lynn, David G

2015-10-12

The molecular logic gates that regulate gene circuits are necessarily intricate and highly regulated, particularly in the critical commitments necessary for pathogenesis. We now report simple AND and OR logic gates to be accessible within a single protein receptor. Pathogenesis by the bacterium Rhizobium radiobacter is mediated by a single histidine kinase, VirA, which processes multiple small molecule host signals (phenol and sugar). Mutagenesis analyses converged on a single signal integration node, and finer functional analyses revealed that a single residue could switch VirA from a functional AND logic gate to an OR gate where each of two signals activate independently. Host range preferences among natural strains of R. radiobacter correlate with these gate logic strategies. Although the precise mechanism for the signal integration node requires further analyses, long-range signal transmission through this histidine kinase can now be exploited for synthetic signaling circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Implementing universal nonadiabatic holonomic quantum gates with transmons

NASA Astrophysics Data System (ADS)

Hong, Zhuo-Ping; Liu, Bao-Jie; Cai, Jia-Qi; Zhang, Xin-Ding; Hu, Yong; Wang, Z. D.; Xue, Zheng-Yuan

2018-02-01

Geometric phases are well known to be noise resilient in quantum evolutions and operations. Holonomic quantum gates provide us with a robust way towards universal quantum computation, as these quantum gates are actually induced by non-Abelian geometric phases. Here we propose and elaborate how to efficiently implement universal nonadiabatic holonomic quantum gates on simpler superconducting circuits, with a single transmon serving as a qubit. In our proposal, an arbitrary single-qubit holonomic gate can be realized in a single-loop scenario by varying the amplitudes and phase difference of two microwave fields resonantly coupled to a transmon, while nontrivial two-qubit holonomic gates may be generated with a transmission-line resonator being simultaneously coupled to the two target transmons in an effective resonant way. Moreover, our scenario may readily be scaled up to a two-dimensional lattice configuration, which is able to support large scalable quantum computation, paving the way for practically implementing universal nonadiabatic holonomic quantum computation with superconducting circuits.

Relieved kink effects in symmetrically graded In0.45Al0.55As/InxGa1-xAs metamorphic high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Sung; Liao, Chen-Hsian

2007-12-01

Kink effects in an In-rich InxGa1-xAs (x=0.53-0.63) linearly graded channel of an In0.45Al0.55As/InxGa1-xAs metamorphic high-electron-mobility transistor have been effectively relieved by depositing a high-barrier Ni /Au gate with the silicon nitride passivation. Complete physical investigations for the relieved kink effects have been made by comparing identical devices with/without a high-barrier Schottky gate or the surface passivation. After successfully suppressing the kink effects, the proposed device has shown a superior voltage gain of 173.8, low output conductance of 2.09mS/mm, and excellent power-added efficiency of 54.1% with high output power (power gain) of 14.87dBm (14.53dB). Improved linearity and excellent thermal threshold coefficient (∂Vth/∂T) of -0.14mV/K have also been achieved. The proposed design provides good potential for high-gain and high-linearity circuit applications.

Total Ionizing Dose Effects in MOS Oxides and Devices

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; McLean, F. B.

2003-01-01

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

NASA Astrophysics Data System (ADS)

Priydarshi, A.; Chattopadhyay, M. K.

2016-10-01

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;

Turning Oscillations Into Opportunities: Lessons from a Bacterial Decision Gate

NASA Astrophysics Data System (ADS)

Schultz, Daniel; Lu, Mingyang; Stavropoulos, Trevor; Onuchic, Jose'; Ben-Jacob, Eshel

2013-04-01

Sporulation vs. competence provides a prototypic example of collective cell fate determination. The decision is performed by the action of three modules: 1) A stochastic competence switch whose transition probability is regulated by population density, population stress and cell stress. 2) A sporulation timer whose clock rate is regulated by cell stress and population stress. 3) A decision gate that is coupled to the timer via a special repressilator-like loop. We show that the distinct circuit architecture of this gate leads to special dynamics and noise management characteristics: The gate opens a time-window of opportunity for competence transitions during which it generates oscillations that are turned into a chain of transition opportunities - each oscillation opens a short interval with high transition probability. The special architecture of the gate also leads to filtering of external noise and robustness against internal noise and variations in the circuit parameters.

Combining dynamical decoupling with fault-tolerant quantum computation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ng, Hui Khoon; Preskill, John; Lidar, Daniel A.

2011-07-15

We study how dynamical decoupling (DD) pulse sequences can improve the reliability of quantum computers. We prove upper bounds on the accuracy of DD-protected quantum gates and derive sufficient conditions for DD-protected gates to outperform unprotected gates. Under suitable conditions, fault-tolerant quantum circuits constructed from DD-protected gates can tolerate stronger noise and have a lower overhead cost than fault-tolerant circuits constructed from unprotected gates. Our accuracy estimates depend on the dynamics of the bath that couples to the quantum computer and can be expressed either in terms of the operator norm of the bath's Hamiltonian or in terms of themore » power spectrum of bath correlations; we explain in particular how the performance of recursively generated concatenated pulse sequences can be analyzed from either viewpoint. Our results apply to Hamiltonian noise models with limited spatial correlations.« less

FPGA-based gating and logic for multichannel single photon counting

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G

2012-01-01

We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidencemore » measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)« less

Turning Oscillations Into Opportunities: Lessons from a Bacterial Decision Gate

PubMed Central

Schultz, Daniel; Lu, Mingyang; Stavropoulos, Trevor; Onuchic, Jose'; Ben-Jacob, Eshel

2013-01-01

Sporulation vs. competence provides a prototypic example of collective cell fate determination. The decision is performed by the action of three modules: 1) A stochastic competence switch whose transition probability is regulated by population density, population stress and cell stress. 2) A sporulation timer whose clock rate is regulated by cell stress and population stress. 3) A decision gate that is coupled to the timer via a special repressilator-like loop. We show that the distinct circuit architecture of this gate leads to special dynamics and noise management characteristics: The gate opens a time-window of opportunity for competence transitions during which it generates oscillations that are turned into a chain of transition opportunities – each oscillation opens a short interval with high transition probability. The special architecture of the gate also leads to filtering of external noise and robustness against internal noise and variations in the circuit parameters. PMID:23591544

Continuous-variable geometric phase and its manipulation for quantum computation in a superconducting circuit.

PubMed

Song, Chao; Zheng, Shi-Biao; Zhang, Pengfei; Xu, Kai; Zhang, Libo; Guo, Qiujiang; Liu, Wuxin; Xu, Da; Deng, Hui; Huang, Keqiang; Zheng, Dongning; Zhu, Xiaobo; Wang, H

2017-10-20

Geometric phase, associated with holonomy transformation in quantum state space, is an important quantum-mechanical effect. Besides fundamental interest, this effect has practical applications, among which geometric quantum computation is a paradigm, where quantum logic operations are realized through geometric phase manipulation that has some intrinsic noise-resilient advantages and may enable simplified implementation of multi-qubit gates compared to the dynamical approach. Here we report observation of a continuous-variable geometric phase and demonstrate a quantum gate protocol based on this phase in a superconducting circuit, where five qubits are controllably coupled to a resonator. Our geometric approach allows for one-step implementation of n-qubit controlled-phase gates, which represents a remarkable advantage compared to gate decomposition methods, where the number of required steps dramatically increases with n. Following this approach, we realize these gates with n up to 4, verifying the high efficiency of this geometric manipulation for quantum computation.

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Frequency control circuit for all-digital phase-lock loops

NASA Technical Reports Server (NTRS)

Anderson, T. O.

1973-01-01

Phase-lock loop references all its operations to fixed high-frequency service clock operating at highest speed which digital circuits permit. Wide-range control circuit provides linear control of frequency of reference signal. It requires only two counters in combination with control circuit consisting only of flip-flop and gate.

Lower-upper-threshold correlation for underwater range-gated imaging self-adaptive enhancement.

PubMed

Sun, Liang; Wang, Xinwei; Liu, Xiaoquan; Ren, Pengdao; Lei, Pingshun; He, Jun; Fan, Songtao; Zhou, Yan; Liu, Yuliang

2016-10-10

In underwater range-gated imaging (URGI), enhancement of low-brightness and low-contrast images is critical for human observation. Traditional histogram equalizations over-enhance images, with the result of details being lost. To compress over-enhancement, a lower-upper-threshold correlation method is proposed for underwater range-gated imaging self-adaptive enhancement based on double-plateau histogram equalization. The lower threshold determines image details and compresses over-enhancement. It is correlated with the upper threshold. First, the upper threshold is updated by searching for the local maximum in real time, and then the lower threshold is calculated by the upper threshold and the number of nonzero units selected from a filtered histogram. With this method, the backgrounds of underwater images are constrained with enhanced details. Finally, the proof experiments are performed. Peak signal-to-noise-ratio, variance, contrast, and human visual properties are used to evaluate the objective quality of the global and regions of interest images. The evaluation results demonstrate that the proposed method adaptively selects the proper upper and lower thresholds under different conditions. The proposed method contributes to URGI with effective image enhancement for human eyes.

Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration

NASA Astrophysics Data System (ADS)

Zainudin, M. F.; Hussin, H.; Halim, A. K.; Karim, J.

2018-03-01

A mechanism known as Negative-bias Temperature Instability (NBTI) degrades a main electrical parameters of a circuit especially in terms of performance. So far, the circuit design available at present are only focussed on high performance circuit without considering the circuit reliability and robustness. In this paper, the main circuit performances of high performance FinFET flip-flop such as delay time, and power were studied with the presence of the NBTI degradation. The aging analysis was verified using a 16nm High Performance Predictive Technology Model (PTM) based on different commands available at Synopsys HSPICE. The results shown that the circuit under the longer dynamic NBTI simulation produces the highest impact in the increasing of gate delay and decrease in the average power reduction from a fresh simulation until the aged stress time under a nominal condition. In addition, the circuit performance under a varied stress condition such as temperature and negative stress gate bias were also studied.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Superior model for fault tolerance computation in designing nano-sized circuit systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, N. S. S., E-mail: narinderjit@petronas.com.my; Muthuvalu, M. S., E-mail: msmuthuvalu@gmail.com; Asirvadam, V. S., E-mail: vijanth-sagayan@petronas.com.my

2014-10-24

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalizationmore » of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.« less

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

GaAs digital dynamic IC's for applications up to 10 GHz

NASA Astrophysics Data System (ADS)

Rocchi, M.; Gabillard, B.

1983-06-01

To evaluate the potentiality of GaAs MESFET's as transmitting gates, dynamic TT-bar flip-flops have been fabricated using a self-aligned planar process. The maximum operating frequency is 10.2 GHz, which is the best speed performance ever reported for a digital circuit. The performance of the transmitting gates within the circuits are discussed in detail. Speed improvement and topological simplification of fully static LSI subsystems are investigated.

Design, processing, and testing of LSI arrays for space station

NASA Technical Reports Server (NTRS)

Schneider, W. C.

1974-01-01

At wafer probe, units of the TA6567 circuit, a beam leaded COS/MOS/SOS 256-bit RAM, were demonstrated to be functionally perfect. An aluminum gate current-sense version and a silicon-gate voltage-sense version of this memory were developed. Initial base line data for the beam lead SOS process using the TA5388 circuit show the stability of the dc device characteristics through the beam lead processing.

Intelligent layered nanoflare: "lab-on-a-nanoparticle" for multiple DNA logic gate operations and efficient intracellular delivery.

PubMed

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-08-07

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a "lab-on-a-nanoparticle", the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.

What Randomized Benchmarking Actually Measures

DOE PAGES

Proctor, Timothy; Rudinger, Kenneth; Young, Kevin; ...

2017-09-28

Randomized benchmarking (RB) is widely used to measure an error rate of a set of quantum gates, by performing random circuits that would do nothing if the gates were perfect. In the limit of no finite-sampling error, the exponential decay rate of the observable survival probabilities, versus circuit length, yields a single error metric r. For Clifford gates with arbitrary small errors described by process matrices, r was believed to reliably correspond to the mean, over all Clifford gates, of the average gate infidelity between the imperfect gates and their ideal counterparts. We show that this quantity is not amore » well-defined property of a physical gate set. It depends on the representations used for the imperfect and ideal gates, and the variant typically computed in the literature can differ from r by orders of magnitude. We present new theories of the RB decay that are accurate for all small errors describable by process matrices, and show that the RB decay curve is a simple exponential for all such errors. Here, these theories allow explicit computation of the error rate that RB measures (r), but as far as we can tell it does not correspond to the infidelity of a physically allowed (completely positive) representation of the imperfect gates.« less

Fabrication of quantum dots in undoped Si/Si 0.8Ge 0.2 heterostructures using a single metal-gate layer

DOE PAGES

Lu, T. M.; Gamble, J. K.; Muller, R. P.; ...

2016-08-01

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here, we report the fabrication and low-temperature characterization of quantum dots in the Si/Si 0.8Ge 0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 μm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratiomore » used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. Furthermore, the device uses only a single metal-gate layer, greatly simplifying device design and fabrication.« less

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2016-10-01

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/- LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal-semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

A programming language for composable DNA circuits

PubMed Central

Phillips, Andrew; Cardelli, Luca

2009-01-01

Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing. PMID:19535415

A programming language for composable DNA circuits.

PubMed

Phillips, Andrew; Cardelli, Luca

2009-08-06

Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.

Optimal thresholds for the estimation of area rain-rate moments by the threshold method

NASA Technical Reports Server (NTRS)

Short, David A.; Shimizu, Kunio; Kedem, Benjamin

1993-01-01

Optimization of the threshold method, achieved by determination of the threshold that maximizes the correlation between an area-average rain-rate moment and the area coverage of rain rates exceeding the threshold, is demonstrated empirically and theoretically. Empirical results for a sequence of GATE radar snapshots show optimal thresholds of 5 and 27 mm/h for the first and second moments, respectively. Theoretical optimization of the threshold method by the maximum-likelihood approach of Kedem and Pavlopoulos (1991) predicts optimal thresholds near 5 and 26 mm/h for lognormally distributed rain rates with GATE-like parameters. The agreement between theory and observations suggests that the optimal threshold can be understood as arising due to sampling variations, from snapshot to snapshot, of a parent rain-rate distribution. Optimal thresholds for gamma and inverse Gaussian distributions are also derived and compared.

Effects of passive and active movement on vibrotactile detection thresholds of the Pacinian channel and forward masking.

PubMed

Yıldız, Mustafa Z; Toker, İpek; Özkan, Fatma B; Güçlü, Burak

2015-01-01

We investigated the gating effect of passive and active movement on the vibrotactile detection thresholds of the Pacinian (P) psychophysical channel and forward masking. Previous work on gating mostly used electrocutaneous stimulation and did not allow focusing on tactile submodalities. Ten healthy adults participated in our study. Passive movement was achieved by swinging a platform, on which the participant's stimulated hand was attached, manually by a trained operator. The root-mean-square value of the movement speed was kept in a narrow range (slow: 10-20 cm/s, fast: 50-60 cm/s). Active movement was performed by the participant him-/herself using the same apparatus. The tactile stimuli consisted of 250-Hz sinusoidal mechanical vibrations, which were generated by a shaker mounted on the movement platform and applied to the middle fingertip. In the forward-masking experiments, a high-level masking stimulus preceded the test stimulus. Each movement condition was tested separately in a two-interval forced-choice detection task. Both passive and active movement caused a robust gating effect, that is, elevation of thresholds, in the fast speed range. Statistically significant change of thresholds was not found in slow movement conditions. Passive movement yielded higher thresholds than those measured during active movement, but this could not be confirmed statistically. On the other hand, the effect of forward masking was approximately constant as the movement condition varied. These results imply that gating depends on both peripheral and central factors in the P channel. Active movement may have some facilitatory role and produce less gating. Additionally, the results support the hypothesis regarding a critical speed for gating, which may be relevant for daily situations involving vibrations transmitted through grasped objects and for manual exploration.

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

NASA Technical Reports Server (NTRS)

Russinoff, David M.

1995-01-01

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

A low-cost universal cumulative gating circuit for small and large animal clinical imaging

NASA Astrophysics Data System (ADS)

Gioux, Sylvain; Frangioni, John V.

2008-02-01

Image-assisted diagnosis and therapy is becoming more commonplace in medicine. However, most imaging techniques suffer from voluntary or involuntary motion artifacts, especially cardiac and respiratory motions, which degrade image quality. Current software solutions either induce computational overhead or reject out-of-focus images after acquisition. In this study we demonstrate a hardware-only gating circuit that accepts multiple, pseudo-periodic signals and produces a single TTL (0-5 V) imaging window of accurate phase and period. The electronic circuit Gerber files described in this article and the list of components are available online at www.frangionilab.org.

An X-Band SOS Resistive Gate-Insulator-Semiconductor /RIS/ switch

NASA Astrophysics Data System (ADS)

Kwok, S. P.

1980-02-01

The new X-Band Resistive Gate-Insulator-Semiconductor (RIS) switch has been fabricated on silicon-on-sapphire, and its equivalent circuit model characterized. An RIS SPST switch with 20-dB on/off isolation, 1.2-dB insertion loss, and power handling capacity in excess of 20-W peak has been achieved at X band. The device switching time is on the order of 600 ns, and it requires negligible control holding current in both on and off states. The device is compatible with monolithic integrated-circuit technology and thus is suitable for integration into low-cost monolithic phase shifters or other microwave integrated circuits.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Design of synthetic biological logic circuits based on evolutionary algorithm.

PubMed

Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei

2013-08-01

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.

TOFPET2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

NASA Astrophysics Data System (ADS)

Di Francesco, A.; Bugalho, R.; Oliveira, L.; Pacher, L.; Rivetti, A.; Rolo, M.; Silva, J. C.; Silva, R.; Varela, J.

2016-03-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with 320 pF capacitance the circuit has 24 (30) dB SNR, 75(39) ps r.m.s. resolution, and 4(8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Role of AlGaN/GaN interface traps on negative threshold voltage shift in AlGaN/GaN HEMT

NASA Astrophysics Data System (ADS)

Malik, Amit; Sharma, Chandan; Laishram, Robert; Bag, Rajesh Kumar; Rawal, Dipendra Singh; Vinayak, Seema; Sharma, Rajesh Kumar

2018-04-01

This article reports negative shift in the threshold-voltage in AlGaN/GaN high electron mobility transistor (HEMT) with application of reverse gate bias stress. The device is biased in strong pinch-off and low drain to source voltage condition for a fixed time duration (reverse gate bias stress), followed by measurement of transfer characteristics. Negative threshold voltage shift after application of reverse gate bias stress indicates the presence of more carriers in channel as compared to the unstressed condition. We propose the presence of AlGaN/GaN interface states to be the reason of negative threshold voltage shift, and developed a process to electrically characterize AlGaN/GaN interface states. We verified the results with Technology Computer Aided Design (TCAD) ATLAS simulation and got a good match with experimental measurements.

Monolayer semiconductor nanocavity lasers with ultralow thresholds.

PubMed

Wu, Sanfeng; Buckley, Sonia; Schaibley, John R; Feng, Liefeng; Yan, Jiaqiang; Mandrus, David G; Hatami, Fariba; Yao, Wang; Vučković, Jelena; Majumdar, Arka; Xu, Xiaodong

2015-04-02

Engineering the electromagnetic environment of a nanometre-scale light emitter by use of a photonic cavity can significantly enhance its spontaneous emission rate, through cavity quantum electrodynamics in the Purcell regime. This effect can greatly reduce the lasing threshold of the emitter, providing a low-threshold laser system with small footprint, low power consumption and ultrafast modulation. An ultralow-threshold nanoscale laser has been successfully developed by embedding quantum dots into a photonic crystal cavity (PCC). However, several challenges impede the practical application of this architecture, including the random positions and compositional fluctuations of the dots, extreme difficulty in current injection, and lack of compatibility with electronic circuits. Here we report a new lasing strategy: an atomically thin crystalline semiconductor--that is, a tungsten diselenide monolayer--is non-destructively and deterministically introduced as a gain medium at the surface of a pre-fabricated PCC. A continuous-wave nanolaser operating in the visible regime is thereby achieved with an optical pumping threshold as low as 27 nanowatts at 130 kelvin, similar to the value achieved in quantum-dot PCC lasers. The key to the lasing action lies in the monolayer nature of the gain medium, which confines direct-gap excitons to within one nanometre of the PCC surface. The surface-gain geometry gives unprecedented accessibility and hence the ability to tailor gain properties via external controls such as electrostatic gating and current injection, enabling electrically pumped operation. Our scheme is scalable and compatible with integrated photonics for on-chip optical communication technologies.

Monolayer semiconductor nanocavity lasers with ultralow thresholds

NASA Astrophysics Data System (ADS)

Wu, Sanfeng; Buckley, Sonia; Schaibley, John R.; Feng, Liefeng; Yan, Jiaqiang; Mandrus, David G.; Hatami, Fariba; Yao, Wang; Vučković, Jelena; Majumdar, Arka; Xu, Xiaodong

2015-04-01

Engineering the electromagnetic environment of a nanometre-scale light emitter by use of a photonic cavity can significantly enhance its spontaneous emission rate, through cavity quantum electrodynamics in the Purcell regime. This effect can greatly reduce the lasing threshold of the emitter, providing a low-threshold laser system with small footprint, low power consumption and ultrafast modulation. An ultralow-threshold nanoscale laser has been successfully developed by embedding quantum dots into a photonic crystal cavity (PCC). However, several challenges impede the practical application of this architecture, including the random positions and compositional fluctuations of the dots, extreme difficulty in current injection, and lack of compatibility with electronic circuits. Here we report a new lasing strategy: an atomically thin crystalline semiconductor--that is, a tungsten diselenide monolayer--is non-destructively and deterministically introduced as a gain medium at the surface of a pre-fabricated PCC. A continuous-wave nanolaser operating in the visible regime is thereby achieved with an optical pumping threshold as low as 27 nanowatts at 130 kelvin, similar to the value achieved in quantum-dot PCC lasers. The key to the lasing action lies in the monolayer nature of the gain medium, which confines direct-gap excitons to within one nanometre of the PCC surface. The surface-gain geometry gives unprecedented accessibility and hence the ability to tailor gain properties via external controls such as electrostatic gating and current injection, enabling electrically pumped operation. Our scheme is scalable and compatible with integrated photonics for on-chip optical communication technologies.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

Molecular electronics in pinnae of Mimosa pudica

PubMed Central

Foster, Justin C; Markin, Vladislav S

2010-01-01

Bioelectrochemical circuits operate in all plants including the sensitive plant Mimosa pudica Linn. The activation of biologically closed circuits with voltage gated ion channels can lead to various mechanical, hydrodynamical, physiological, biochemical and biophysical responses. Here the biologically closed electrochemical circuit in pinnae of Mimosa pudica is analyzed using the charged capacitor method for electrostimulation at different voltages. Also the equivalent electrical scheme of electrical signal transduction inside the plant's pinna is evaluated. These circuits remain linear at small potentials not exceeding 0.5 V. At higher potentials the circuits become strongly non-linear pointing to the opening of ion channels in plant tissues. Changing the polarity of electrodes leads to a strong rectification effect and to different kinetics of a capacitor. These effects can be caused by a redistribution of K+, Cl−, Ca2+ and H+ ions through voltage gated ion channels. The electrical properties of Mimosa pudica were investigated and equivalent electrical circuits within the pinnae were proposed to explain the experimental data. PMID:20448476

Molecular electronics in pinnae of Mimosa pudica.

PubMed

Volkov, Alexander G; Foster, Justin C; Markin, Vladislav S

2010-07-01

Bioelectrochemical circuits operate in all plants including the sensitive plant Mimosa pudica Linn. The activation of biologically closed circuits with voltage gated ion channels can lead to various mechanical, hydrodynamical, physiological, biochemical, and biophysical responses. Here the biologically closed electrochemical circuit in pinnae of Mimosa pudica is analyzed using the charged capacitor method for electrostimulation at different voltages. Also the equivalent electrical scheme of electrical signal transduction inside the plant's pinna is evaluated. These circuits remain linear at small potentials not exceeding 0.5 V. At higher potentials the circuits become strongly non-linear pointing to the opening of ion channels in plant tissues. Changing the polarity of electrodes leads to a strong rectification effect and to different kinetics of a capacitor. These effects can be caused by a redistribution of K(+), Cl(-), Ca(2+), and H(+) ions through voltage gated ion channels. The electrical properties of Mimosa pudica were investigated and equivalent electrical circuits within the pinnae were proposed to explain the experimental data.

Compact, Intelligent, Digitally Controlled IGBT Gate Drivers for a PEBB-Based ILC Marx Modulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nguyen, M.N.; Burkhart, C.; Olsen, J.J.

2010-06-07

SLAC National Accelerator Laboratory has built and is currently operating a first generation prototype Marx klystron modulator to meet ILC specifications. Under development is a second generation prototype, aimed at improving overall performance, serviceability, and manufacturability as compared to its predecessor. It is designed around 32 cells, each operating at 3.75 kV and correcting for its own capacitor droop. Due to the uniqueness of this application, high voltage gate drivers needed to be developed for the main 6.5 kV and droop correction 1.7 kV IGBTs. The gate driver provides vital functions such as protection of the IGBT from over-voltage andmore » over-current, detection of gate-emitter open and short circuit conditions, and monitoring of IGBT degradation (based on collector-emitter saturation voltage). Gate drive control, diagnostic processing capabilities, and communication are digitally implemented using an FPGA. This paper details the design of the gate driver circuitry, component selection, and construction layout. In addition, experimental results are included to illustrate the effectiveness of the protection circuit.« less

Mechanisms of Hierarchical Reinforcement Learning in Corticostriatal Circuits 1: Computational Analysis

PubMed Central

Badre, David

2012-01-01

Growing evidence suggests that the prefrontal cortex (PFC) is organized hierarchically, with more anterior regions having increasingly abstract representations. How does this organization support hierarchical cognitive control and the rapid discovery of abstract action rules? We present computational models at different levels of description. A neural circuit model simulates interacting corticostriatal circuits organized hierarchically. In each circuit, the basal ganglia gate frontal actions, with some striatal units gating the inputs to PFC and others gating the outputs to influence response selection. Learning at all of these levels is accomplished via dopaminergic reward prediction error signals in each corticostriatal circuit. This functionality allows the system to exhibit conditional if–then hypothesis testing and to learn rapidly in environments with hierarchical structure. We also develop a hybrid Bayesian-reinforcement learning mixture of experts (MoE) model, which can estimate the most likely hypothesis state of individual participants based on their observed sequence of choices and rewards. This model yields accurate probabilistic estimates about which hypotheses are attended by manipulating attentional states in the generative neural model and recovering them with the MoE model. This 2-pronged modeling approach leads to multiple quantitative predictions that are tested with functional magnetic resonance imaging in the companion paper. PMID:21693490

Dynamics of Action Potential Initiation in the GABAergic Thalamic Reticular Nucleus In Vivo

PubMed Central

Muñoz, Fabián; Fuentealba, Pablo

2012-01-01

Understanding the neural mechanisms of action potential generation is critical to establish the way neural circuits generate and coordinate activity. Accordingly, we investigated the dynamics of action potential initiation in the GABAergic thalamic reticular nucleus (TRN) using in vivo intracellular recordings in cats in order to preserve anatomically-intact axo-dendritic distributions and naturally-occurring spatiotemporal patterns of synaptic activity in this structure that regulates the thalamic relay to neocortex. We found a wide operational range of voltage thresholds for action potentials, mostly due to intrinsic voltage-gated conductances and not synaptic activity driven by network oscillations. Varying levels of synchronous synaptic inputs produced fast rates of membrane potential depolarization preceding the action potential onset that were associated with lower thresholds and increased excitability, consistent with TRN neurons performing as coincidence detectors. On the other hand the presence of action potentials preceding any given spike was associated with more depolarized thresholds. The phase-plane trajectory of the action potential showed somato-dendritic propagation, but no obvious axon initial segment component, prominent in other neuronal classes and allegedly responsible for the high onset speed. Overall, our results suggest that TRN neurons could flexibly integrate synaptic inputs to discharge action potentials over wide voltage ranges, and perform as coincidence detectors and temporal integrators, supported by a dynamic action potential threshold. PMID:22279567

Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops

NASA Astrophysics Data System (ADS)

Rahman, Aminur; Jordan, Ian; Blackmore, Denis

2018-01-01

It has been observed through experiments and SPICE simulations that logical circuits based upon Chua's circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some discrete dynamical models have been developed using various simplifying assumptions. To create a robust modelling framework for chaotic logical circuits, we developed both deterministic and stochastic discrete dynamical models, which exploit the natural recurrence behaviour, for two chaotic NOR gates and a chaotic set/reset flip-flop. This work presents a complete applied mathematical investigation of logical circuits. Experiments on our own designs of the above circuits are modelled and the models are rigorously analysed and simulated showing surprisingly close qualitative agreement with the experiments. Furthermore, the models are designed to accommodate dynamics of similarly designed circuits. This will allow researchers to develop ever more complex chaotic logical circuits with a simple modelling framework.

Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops.

PubMed

Rahman, Aminur; Jordan, Ian; Blackmore, Denis

2018-01-01

It has been observed through experiments and SPICE simulations that logical circuits based upon Chua's circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some discrete dynamical models have been developed using various simplifying assumptions. To create a robust modelling framework for chaotic logical circuits, we developed both deterministic and stochastic discrete dynamical models, which exploit the natural recurrence behaviour, for two chaotic NOR gates and a chaotic set/reset flip-flop. This work presents a complete applied mathematical investigation of logical circuits. Experiments on our own designs of the above circuits are modelled and the models are rigorously analysed and simulated showing surprisingly close qualitative agreement with the experiments. Furthermore, the models are designed to accommodate dynamics of similarly designed circuits. This will allow researchers to develop ever more complex chaotic logical circuits with a simple modelling framework.

Fredkin and Toffoli Gates Implemented in Oregonator Model of Belousov-Zhabotinsky Medium

NASA Astrophysics Data System (ADS)

Adamatzky, Andrew

A thin-layer Belousov-Zhabotinsky (BZ) medium is a powerful computing device capable for implementing logical circuits, memory, image processors, robot controllers, and neuromorphic architectures. We design the reversible logical gates — Fredkin gate and Toffoli gate — in a BZ medium network of excitable channels with subexcitable junctions. Local control of the BZ medium excitability is an important feature of the gates’ design. An excitable thin-layer BZ medium responds to a localized perturbation with omnidirectional target or spiral excitation waves. A subexcitable BZ medium responds to an asymmetric perturbation by producing traveling localized excitation wave-fragments similar to dissipative solitons. We employ interactions between excitation wave-fragments to perform the computation. We interpret the wave-fragments as values of Boolean variables. The presence of a wave-fragment at a given site of a circuit represents the logical truth, absence of the wave-fragment — logically false. Fredkin gate consists of ten excitable channels intersecting at 11 junctions, eight of which are subexcitable. Toffoli gate consists of six excitable channels intersecting at six junctions, four of which are subexcitable. The designs of the gates are verified using numerical integration of two-variable Oregonator equations.

Mesoscopic Field-Effect-Induced Devices in Depleted Two-Dimensional Electron Systems

NASA Astrophysics Data System (ADS)

Bachsoliani, N.; Platonov, S.; Wieck, A. D.; Ludwig, S.

2017-12-01

Nanoelectronic devices embedded in the two-dimensional electron system (2DES) of a GaAs /(Al ,Ga )As heterostructure enable a large variety of applications ranging from fundamental research to high-speed transistors. Electrical circuits are thereby commonly defined by creating barriers for carriers by the selective depletion of a preexisting 2DES. We explore an alternative approach: we deplete the 2DES globally by applying a negative voltage to a global top gate and screen the electric field of the top gate only locally using nanoscale gates placed on the wafer surface between the plane of the 2DES and the top gate. Free carriers are located beneath the screen gates, and their properties can be controlled by means of geometry and applied voltages. This method promises considerable advantages for the definition of complex circuits by the electric-field effect, as it allows us to reduce the number of gates and simplify gate geometries. Examples are carrier systems with ring topology or large arrays of quantum dots. We present a first exploration of this method pursuing field effect, Hall effect, and Aharonov-Bohm measurements to study electrostatic, dynamic, and coherent properties.

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

PubMed Central

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-01-01

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits. PMID:27491391

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

NASA Astrophysics Data System (ADS)

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-08-01

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal.

PubMed

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-08-05

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature 'prototype' PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

Signal conditioner circuit for photomultiplier tube

NASA Technical Reports Server (NTRS)

Cellier, A.; Hoover, W. M.

1970-01-01

Miniaturized circuit improves measurement of radiation dose absorbed in a scintillation crystal. The temperature coefficient of the field-effect transistor gate-source voltage in the isolation amplifier can be readily controlled.

Logic computation in phase change materials by threshold and memory switching.

PubMed

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

PubMed

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

PubMed Central

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

NASA Astrophysics Data System (ADS)

Chen, Meng; Lei, Jiefeng; Huang, Shengxiang; Liao, Congwei; Deng, Lianwen

2017-06-01

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive {V}{TH} shift within 0.4 V and negative {V}{TH} shift within -1.2 V and it is robust and promising for high-resolution display. Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Adaptive gain and filtering circuit for a sound reproduction system

NASA Technical Reports Server (NTRS)

Engebretson, A. Maynard (Inventor); O'Connell, Michael P. (Inventor)

1998-01-01

Adaptive compressive gain and level dependent spectral shaping circuitry for a hearing aid include a microphone to produce an input signal and a plurality of channels connected to a common circuit output. Each channel has a preset frequency response. Each channel includes a filter with a preset frequency response to receive the input signal and to produce a filtered signal, a channel amplifier to amplify the filtered signal to produce a channel output signal, a threshold register to establish a channel threshold level, and a gain circuit. The gain circuit increases the gain of the channel amplifier when the channel output signal falls below the channel threshold level and decreases the gain of the channel amplifier when the channel output signal rises above the channel threshold level. A transducer produces sound in response to the signal passed by the common circuit output.

Ultrafast quantum computation in ultrastrongly coupled circuit QED systems.

PubMed

Wang, Yimin; Guo, Chu; Zhang, Guo-Qiang; Wang, Gangcheng; Wu, Chunfeng

2017-03-10

The latest technological progress of achieving the ultrastrong-coupling regime in circuit quantum electrodynamics (QED) systems has greatly promoted the developments of quantum physics, where novel quantum optics phenomena and potential computational benefits have been predicted. Here, we propose a scheme to accelerate the nontrivial two-qubit phase gate in a circuit QED system, where superconducting flux qubits are ultrastrongly coupled to a transmission line resonator (TLR), and two more TLRs are coupled to the ultrastrongly-coupled system for assistant. The nontrivial unconventional geometric phase gate between the two flux qubits is achieved based on close-loop displacements of the three-mode intracavity fields. Moreover, as there are three resonators contributing to the phase accumulation, the requirement of the coupling strength to realize the two-qubit gate can be reduced. Further reduction in the coupling strength to achieve a specific controlled-phase gate can be realized by adding more auxiliary resonators to the ultrastrongly-coupled system through superconducting quantum interference devices. We also present a study of our scheme with realistic parameters considering imperfect controls and noisy environment. Our scheme possesses the merits of ultrafastness and noise-tolerance due to the advantages of geometric phases.

Ultrafast quantum computation in ultrastrongly coupled circuit QED systems

PubMed Central

Wang, Yimin; Guo, Chu; Zhang, Guo-Qiang; Wang, Gangcheng; Wu, Chunfeng

2017-01-01

The latest technological progress of achieving the ultrastrong-coupling regime in circuit quantum electrodynamics (QED) systems has greatly promoted the developments of quantum physics, where novel quantum optics phenomena and potential computational benefits have been predicted. Here, we propose a scheme to accelerate the nontrivial two-qubit phase gate in a circuit QED system, where superconducting flux qubits are ultrastrongly coupled to a transmission line resonator (TLR), and two more TLRs are coupled to the ultrastrongly-coupled system for assistant. The nontrivial unconventional geometric phase gate between the two flux qubits is achieved based on close-loop displacements of the three-mode intracavity fields. Moreover, as there are three resonators contributing to the phase accumulation, the requirement of the coupling strength to realize the two-qubit gate can be reduced. Further reduction in the coupling strength to achieve a specific controlled-phase gate can be realized by adding more auxiliary resonators to the ultrastrongly-coupled system through superconducting quantum interference devices. We also present a study of our scheme with realistic parameters considering imperfect controls and noisy environment. Our scheme possesses the merits of ultrafastness and noise-tolerance due to the advantages of geometric phases. PMID:28281654

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Materials-Process Interactions in Ternary Alloy Semiconductors.

DTIC Science & Technology

1984-08-01

high, the surface potential can be * modulated . PECVD SiO. appears to be a viable candidate as a gate dielectric for * Irf ,fO-4A)s MISFETs...it is desirable to integrate the detectors with circuits capable of performing signal processing functions. These circuits can either be fabricated in...to be a major problem in In0. 5 3Ga 0.* 47 s. 25 S. . . . . 13821 -1 R I (a) CROSS SECTION KEYBOARD 210M ANNEALING CHAMBER GATE TRIGG TRIAC

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

ESSDERC (European Solid State Device Research Conference) 17th Held in Bologna, Italy on 14-17 September 1987

DTIC Science & Technology

1987-09-17

T. J. Watson Research Center, Yorktown Heights, N.Y. 10598 Processing, design , and characterization issues are discussed for advanced field-effect...Graded-gate FET (GFET) Jan. 1969. designed to overcome these problems, was presented. The differential gate bias allows control [3] D. Misra, T.R...structure, the degree of freedom in zation [7) of the partially restricted active circuit or system design circuit layout, and area is to control the

Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique

NASA Astrophysics Data System (ADS)

Qiang, Lei; Liang, Xiaoci; Cai, Guangshuo; Pei, Yanli; Yao, Ruohe; Wang, Gang

2018-06-01

Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: EC - EF > 3kT and EC - EF ≤ 3kT, where kT is the thermal energy, EF and EC represent the Fermi level and the conduction band edge, respectively. Additionally, in order to describe conduction mechanisms more accurately, the extended mobility edge model is conjoined, which can also get rid of the complicated and lengthy computations. The good agreement between measured and calculated results confirms the efficiency of this model for the design of integrated large-area thin film circuits.

Modeling and analysis of energy quantization effects on single electron inverter performance

NASA Astrophysics Data System (ADS)

Dan, Surya Shankar; Mahapatra, Santanu

2009-08-01

In this paper, for the first time, the effects of energy quantization on single electron transistor (SET) inverter performance are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly changes the Coulomb blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET inverter. A new analytical model for the noise margin of SET inverter is proposed which includes the energy quantization effects. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. A compact expression is developed for a novel parameter quantization threshold which is introduced for the first time in this paper. Quantization threshold explicitly defines the maximum energy quantization that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT:CG=1/3 (where CT and CG are tunnel junction and gate capacitances, respectively) offers maximum robustness against energy quantization.

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

Field Effect Transistor /FET/ circuit for variable gin amplifiers

NASA Technical Reports Server (NTRS)

Spaid, G. H.

1969-01-01

Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

Transversal Clifford gates on folded surface codes

DOE PAGES

Moussa, Jonathan E.

2016-10-12

Surface and color codes are two forms of topological quantum error correction in two spatial dimensions with complementary properties. Surface codes have lower-depth error detection circuits and well-developed decoders to interpret and correct errors, while color codes have transversal Clifford gates and better code efficiency in the number of physical qubits needed to achieve a given code distance. A formal equivalence exists between color codes and folded surface codes, but it does not guarantee the transferability of any of these favorable properties. However, the equivalence does imply the existence of constant-depth circuit implementations of logical Clifford gates on folded surfacemore » codes. We achieve and improve this result by constructing two families of folded surface codes with transversal Clifford gates. This construction is presented generally for qudits of any dimension. Lastly, the specific application of these codes to universal quantum computation based on qubit fusion is also discussed.« less

Engineering integrated photonics for heralded quantum gates

NASA Astrophysics Data System (ADS)

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-06-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Toward spin-based Magneto Logic Gate in Graphene

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

NASA Astrophysics Data System (ADS)

Wang, Han; Gou, Chao; Luo, Kai

2017-04-01

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and {I}{{Q}} of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.

Engineering integrated photonics for heralded quantum gates

PubMed Central

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-01-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process. PMID:27282928

Engineering integrated photonics for heralded quantum gates.

PubMed

Meany, Thomas; Biggerstaff, Devon N; Broome, Matthew A; Fedrizzi, Alessandro; Delanty, Michael; Steel, M J; Gilchrist, Alexei; Marshall, Graham D; White, Andrew G; Withford, Michael J

2016-06-10

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA.

PubMed

Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool

2017-12-01

Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.

Irreversibility and entanglement spectrum statistics in quantum circuits

NASA Astrophysics Data System (ADS)

Shaffer, Daniel; Chamon, Claudio; Hamma, Alioscia; Mucciolo, Eduardo R.

2014-12-01

We show that in a quantum system evolving unitarily under a stochastic quantum circuit the notions of irreversibility, universality of computation, and entanglement are closely related. As the state evolves from an initial product state, it gets asymptotically maximally entangled. We define irreversibility as the failure of searching for a disentangling circuit using a Metropolis-like algorithm. We show that irreversibility corresponds to Wigner-Dyson statistics in the level spacing of the entanglement eigenvalues, and that this is obtained from a quantum circuit made from a set of universal gates for quantum computation. If, on the other hand, the system is evolved with a non-universal set of gates, the statistics of the entanglement level spacing deviates from Wigner-Dyson and the disentangling algorithm succeeds. These results open a new way to characterize irreversibility in quantum systems.

Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.

PubMed

Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl

2010-09-13

Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Iyer, Sukanya; Karig, David K; Norred, Sarah E

Engineered gene circuits offer an opportunity to harness biological systems for biotechnological and biomedical applications. However, reliance on host E. coli promoters for the construction of circuit elements, such as logic gates, makes implementation of predictable, independently functioning circuits difficult. In contrast, T7 promoters offer a simple orthogonal expression system for use in a variety of cellular backgrounds and even in cell free systems. Here we develop a T7 promoter system that can be regulated by two different transcriptional repressors for the construction of a logic gate that functions in cells and in cell free systems. We first present LacImore » repressible T7lacO promoters that are regulated from a distal lac operator site for repression. We next explore the positioning of a tet operator site within the T7lacO framework to create T7 promoters that respond to tet and lac repressors and realize an IMPLIES gate. Finally, we demonstrate that these dual input sensitive promoters function in a commercially available E. coli cell-free protein expression system. Together, our results contribute to the first demonstration of multi-input regulation of T7 promoters and expand the utility of T7 promoters in cell based as well as cell-free gene circuits.« less

Investigation of high sensitivity radio-frequency readout circuit based on AlGaN/GaN high electron mobility transistor

NASA Astrophysics Data System (ADS)

Zhang, Xiao-Yu; Tan, Ren-Bing; Sun, Jian-Dong; Li, Xin-Xing; Zhou, Yu; Lü, Li; Qin, Hua

2015-10-01

An AlGaN/GaN high electron mobility transistor (HEMT) device is prepared by using a semiconductor nanofabrication process. A reflective radio-frequency (RF) readout circuit is designed and the HEMT device is assembled in an RF circuit through a coplanar waveguide transmission line. A gate capacitor of the HEMT and a surface-mounted inductor on the transmission line are formed to generate LC resonance. By tuning the gate voltage Vg, the variations of gate capacitance and conductance of the HEMT are reflected sensitively from the resonance frequency and the magnitude of the RF reflection signal. The aim of the designed RF readout setup is to develop a highly sensitive HEMT-based detector. Project supported by the National Natural Science Foundation of China (Grant No. 61107093), the Suzhou Science and Technology Project, China (Grant No. ZXG2012024), and the Youth Innovation Promotion Association, Chinese Academy of Sciences (Grant No. 2012243).

Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)

NASA Technical Reports Server (NTRS)

Lin, Michael R. (Inventor); Petrick, David J. (Inventor); Ballou, Kevin M. (Inventor); Espinosa, Daniel C. (Inventor); James, Edward F. (Inventor); Kliesner, Matthew A. (Inventor)

2017-01-01

Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Electron transporting water-gated thin film transistors

NASA Astrophysics Data System (ADS)

Al Naim, Abdullah; Grell, Martin

2012-10-01

We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Disjointness of Stabilizer Codes and Limitations on Fault-Tolerant Logical Gates

NASA Astrophysics Data System (ADS)

Jochym-O'Connor, Tomas; Kubica, Aleksander; Yoder, Theodore J.

2018-04-01

Stabilizer codes are among the most successful quantum error-correcting codes, yet they have important limitations on their ability to fault tolerantly compute. Here, we introduce a new quantity, the disjointness of the stabilizer code, which, roughly speaking, is the number of mostly nonoverlapping representations of any given nontrivial logical Pauli operator. The notion of disjointness proves useful in limiting transversal gates on any error-detecting stabilizer code to a finite level of the Clifford hierarchy. For code families, we can similarly restrict logical operators implemented by constant-depth circuits. For instance, we show that it is impossible, with a constant-depth but possibly geometrically nonlocal circuit, to implement a logical non-Clifford gate on the standard two-dimensional surface code.

Significance of the gate voltage-dependent mobility in the electrical characterization of organic field effect transistors

NASA Astrophysics Data System (ADS)

Kim, Jong Beom; Lee, Dong Ryeol

2018-04-01

We studied the effect of the addition of free hole- and electron-rich organic molecules to organic semiconductors (OSCs) in organic field effect transistors (OFETs) on the gate voltage-dependent mobility. The drain current versus gate voltage characteristics were quantitatively analyzed using an OFET mobility model of power law behavior based on hopping transport in an OSC. This analysis distinguished the threshold voltage shifts, depending on the materials and structures of the OFET device, and properly estimated the hopping transport of the charge carriers induced by the gate bias within the OSC from the power law exponent parameter. The addition of pentacene or C60 molecules to a one-monolayer pentacene-based OFET shifted the threshold voltages negatively or positively, respectively, due to the structural changes that occurred in the OFET device. On the other hand, the power law parameters revealed that the addition of charge carriers of the same or opposite polarity enhanced or hindered hopping transport, respectively. This study revealed the need for a quantitative analysis of the gate voltage-dependent mobility while distinguishing this effect from the threshold voltage effect in order to understand OSC hopping transport in OFETs.

Variable-Threshold Threshold Elements,

DTIC Science & Technology

A threshold element is a mathematical model of certain types of logic gates and of a biological neuron. Much work has been done on the subject of... threshold elements with fixed thresholds; this study concerns itself with elements in which the threshold may be varied, variable- threshold threshold ...elements. Physical realizations include resistor-transistor elements, in which the threshold is simply a voltage. Variation of the threshold causes the

Comparative influence study of gate-formation structuring on Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors

NASA Astrophysics Data System (ADS)

Hsu, M. K.; Chiu, S. Y.; Wu, C. H.; Guo, D. F.; Lour, W. S.

2008-12-01

Pseudomorphic Al0.22Ga0.78As/In0.16Ga0.84As/Al0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) fabricated with different gate-formation structures of a single-recess gate (SRG), a double-recess gate (DRG) and a field-plate gate (FPG) were comparatively investigated. FPG devices show the best breakdown characteristics among these devices due to great reduction in the peak electric field between the drain and gate electrodes. The measured gate-drain breakdown voltages defined at a 1 mA mm-1 reverse gate-drain current density were -15.3, -19.1 and -26.0 V for SRG, DRG and FPG devices, respectively. No significant differences in their room-temperature common-source current-voltage characteristics were observed. However, FPG devices exhibit threshold voltages being the least sensitive to temperature. Threshold voltages as a function of temperature indicate a threshold-voltage variation as low as -0.97 mV K-1 for FPG devices. According to the 2.4 GHz load-pull power measurement at VDS = 3.0 V and VGS = -0.5 V, the saturated output power (POUT), power gain (GP) and maximum power-added efficiency (PAE) were 10.3 dBm/13.2 dB/36.6%, 11.2 dBm/13.1 dB/39.7% and 13.06 dBm/12.8 dB/47.3%, respectively, for SRG, DRG and FPG devices with a pi-gate in class AB operation. When the FPG device is biased at a VDS of 10 V, the saturated power density is more than 600 mW mm-1.

Unifying Gate Synthesis and Magic State Distillation.

PubMed

Campbell, Earl T; Howard, Mark

2017-02-10

The leading paradigm for performing a computation on quantum memories can be encapsulated as distill-then-synthesize. Initially, one performs several rounds of distillation to create high-fidelity magic states that provide one good T gate, an essential quantum logic gate. Subsequently, gate synthesis intersperses many T gates with Clifford gates to realize a desired circuit. We introduce a unified framework that implements one round of distillation and multiquibit gate synthesis in a single step. Typically, our method uses the same number of T gates as conventional synthesis but with the added benefit of quadratic error suppression. Because of this, one less round of magic state distillation needs to be performed, leading to significant resource savings.

Parallelizing quantum circuit synthesis

NASA Astrophysics Data System (ADS)

Di Matteo, Olivia; Mosca, Michele

2016-03-01

Quantum circuit synthesis is the process in which an arbitrary unitary operation is decomposed into a sequence of gates from a universal set, typically one which a quantum computer can implement both efficiently and fault-tolerantly. As physical implementations of quantum computers improve, the need is growing for tools that can effectively synthesize components of the circuits and algorithms they will run. Existing algorithms for exact, multi-qubit circuit synthesis scale exponentially in the number of qubits and circuit depth, leaving synthesis intractable for circuits on more than a handful of qubits. Even modest improvements in circuit synthesis procedures may lead to significant advances, pushing forward the boundaries of not only the size of solvable circuit synthesis problems, but also in what can be realized physically as a result of having more efficient circuits. We present a method for quantum circuit synthesis using deterministic walks. Also termed pseudorandom walks, these are walks in which once a starting point is chosen, its path is completely determined. We apply our method to construct a parallel framework for circuit synthesis, and implement one such version performing optimal T-count synthesis over the Clifford+T gate set. We use our software to present examples where parallelization offers a significant speedup on the runtime, as well as directly confirm that the 4-qubit 1-bit full adder has optimal T-count 7 and T-depth 3.

A reconfigurable NAND/NOR genetic logic gate

PubMed Central

2012-01-01

Background Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. Results We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. Conclusions We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications. PMID:22989145

A reconfigurable NAND/NOR genetic logic gate.

PubMed

Goñi-Moreno, Angel; Amos, Martyn

2012-09-18

Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.

GAS PHOTOTUBE CIRCUIT

DOEpatents

Richardson, J.H.

1958-03-01

This patent pertains to electronic circuits for measuring the intensity of light and is especially concerned with measurement between preset light thresholds. Such a circuit has application in connection with devices for reading-out information stored on punch cards or tapes where the cards and tapes are translucent. By the novel arrangement of this invention thc sensitivity of a gas phototube is maintained at a low value when the light intensity is below a first threshold level. If the light level rises above the first threshold level, the tube is rendered highly sensitive and an output signal will vary in proportion to the light intensity change. When the light level decreases below a second threshold level, the gas phototube is automatically rendered highly insensitive. Each of these threshold points is adjustable.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Taped Random Spectra for Reliability Demonstration Testing

DTIC Science & Technology

1981-04-01

circuit , barrier strip terminals 9A and 9B. Closure of the normally-open contacts provides the gate current necessary to trigger the control TRIAC ... Circuit contains a TRIAC , DIAC, Reed Relay (R3) and the Tape Running Relay Driver. The Cam on/off switching is accomplished through the barrier strip...2-25 2I; Input Power Circuit .. .. .... ...... ...... ...... ........... 2-26 2-13 Typical Control Circuit

Dynamical decoupling of local transverse random telegraph noise in a two-qubit gate

NASA Astrophysics Data System (ADS)

D'Arrigo, A.; Falci, G.; Paladino, E.

2015-10-01

Achieving high-fidelity universal two-qubit gates is a central requisite of any implementation of quantum information processing. The presence of spurious fluctuators of various physical origin represents a limiting factor for superconducting nanodevices. Operating qubits at optimal points, where the qubit-fluctuator interaction is transverse with respect to the single qubit Hamiltonian, considerably improved single qubit gates. Further enhancement has been achieved by dynamical decoupling (DD). In this article we investigate DD of transverse random telegraph noise acting locally on each of the qubits forming an entangling gate. Our analysis is based on the exact numerical solution of the stochastic Schrödinger equation. We evaluate the gate error under local periodic, Carr-Purcell and Uhrig DD sequences. We find that a threshold value of the number, n, of pulses exists above which the gate error decreases with a sequence-specific power-law dependence on n. Below threshold, DD may even increase the error with respect to the unconditioned evolution, a behaviour reminiscent of the anti-Zeno effect.

Impulse commutating circuit with transformer to limit reapplied voltage

NASA Technical Reports Server (NTRS)

Mcconville, J. H.

1973-01-01

Silicon controlled rectifier opens circuit with currents flowing up to values of 30 amperes. Switching concept halves both current and voltage in middle of commutating cycle thereby lowering size and weight requirements. Commutating circuit can be turned on or off by command and will remain on in absence of load due to continuous gate.

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Logic circuits from zero forcing.

PubMed

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

Analyzing threshold pressure limitations in microfluidic transistors for self-regulated microfluidic circuits.

PubMed

Kim, Sung-Jin; Yokokawa, Ryuji; Takayama, Shuichi

2012-12-03

This paper reveals a critical limitation in the electro-hydraulic analogy between a microfluidic membrane-valve (μMV) and an electronic transistor. Unlike typical transistors that have similar on and off threshold voltages, in hydraulic μMVs, the threshold pressures for opening and closing are significantly different and can change, even for the same μMVs depending on overall circuit design and operation conditions. We explain, in particular, how the negative values of the closing threshold pressures significantly constrain operation of even simple hydraulic μMV circuits such as autonomously switching two-valve microfluidic oscillators. These understandings have significant implications in designing self-regulated microfluidic devices.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Measuring Input Thresholds on an Existing Board

NASA Technical Reports Server (NTRS)

Kuperman, Igor; Gutrich, Daniel G.; Berkun, Andrew C.

2011-01-01

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

DYNAMIC PATTERN RECOGNITION BY MEANS OF THRESHOLD NETS,

DTIC Science & Technology

A method is expounded for the recognition of visual patterns. A circuit diagram of a device is described which is based on a multilayer threshold ...structure synthesized in accordance with the proposed method. Coded signals received each time an image is displayed are transmitted to the threshold ...circuit which distinguishes the signs, and from there to the layers of threshold resolving elements. The image at each layer is made to correspond

Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.

PubMed

Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J

2017-01-01

The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.

Energy saving in ac generators

NASA Technical Reports Server (NTRS)

Nola, F. J.

1980-01-01

Circuit cuts no-load losses, without sacrificing full-load power. Phase-contro circuit includes gate-controlled semiconductor switch that cuts off applied voltage for most of ac cycle if generator idling. Switch "on" time increases when generator is in operation.

Investigation of AlGaN/GaN HEMTs degradation with gate pulse stressing at cryogenic temperature

NASA Astrophysics Data System (ADS)

Wang, Ning; Wang, Hui; Lin, Xinpeng; Qi, Yongle; Duan, Tianli; Jiang, Lingli; Iervolino, Elina; Cheng, Kai; Yu, Hongyu

2017-09-01

Degradation on DC characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) after applying pulsed gate stress at cryogenic temperatures is presented in this paper. The nitrogen vacancy near to the AlGaN/GaN interface leads to threshold voltage of stress-free sample shifting positively at low temperature. The anomalous behavior of threshold voltage variation (decrease first and then increase) under gate stressing as compared to stress-free sample is observed when lowing temperature. This can be correlated with the pre-existing electron traps in SiNX layer or at SiNX/AlGaN interface which can be de-activated and the captured electrons inject back to channel with lowering temperature, which counterbalances the influence of nitrogen vacancy on threshold voltage shift.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

PubMed Central

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng

2018-01-01

Abstract 2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits. PMID:29721428

Triple voltage dc-to-dc converter and method

DOEpatents

Su, Gui-Jia

2008-08-05

A circuit and method of providing three dc voltage buses and transforming power between a low voltage dc converter and a high voltage dc converter, by coupling a primary dc power circuit and a secondary dc power circuit through an isolation transformer; providing the gating signals to power semiconductor switches in the primary and secondary circuits to control power flow between the primary and secondary circuits and by controlling a phase shift between the primary voltage and the secondary voltage. The primary dc power circuit and the secondary dc power circuit each further comprising at least two tank capacitances arranged in series as a tank leg, at least two resonant switching devices arranged in series with each other and arranged in parallel with the tank leg, and at least one voltage source arranged in parallel with the tank leg and the resonant switching devices, said resonant switching devices including power semiconductor switches that are operated by gating signals. Additional embodiments having a center-tapped battery on the low voltage side and a plurality of modules on both the low voltage side and the high voltage side are also disclosed for the purpose of reducing ripple current and for reducing the size of the components.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Pseudobulbar affect: the spectrum of clinical presentations, etiologies and treatments.

PubMed

Miller, Ariel; Pratt, Hillel; Schiffer, Randolph B

2011-07-01

Pseudobulbar affect (PBA) consists of uncontrollable outbursts of laughter or crying inappropriate to the patient's external circumstances and incongruent with the patient's internal emotional state. Recent data suggest disruption of cortico-pontine-cerebellar circuits, reducing the threshold for motor expression of emotion. Disruption of the microcircuitry of the cerebellum itself may likewise impair its ability to act as a gate-control for emotional expression. Current evidence also suggests that serotonergic and glutamatergic neurotransmission play key roles. Although antidepressants have shown benefit, the supportive clinical data have often derived from small numbers of patients and unvalidated measures of PBA severity. Dextromethorphan/quinidine, the first FDA-approved PBA medication, is a novel therapy with antiglutamatergic actions. As life expectancy lengthens and the neurologic settings of PBA become more common, the need for treatment can be expected to increase.

Four GABAergic interneurons impose feeding restraint in Drosophila

PubMed Central

Pool, Allan-Hermann; Kvello, Pal; Mann, Kevin; Cheung, Samantha K.; Gordon, Michael D.; Wang, Liming; Scott, Kristin

2014-01-01

Summary Feeding is dynamically regulated by the palatability of the food source and the physiological needs of the animal. How consumption is controlled by external sensory cues and internal metabolic state remains under intense investigation. Here, we identify four GABAergic interneurons in the Drosophila brain that establish a central feeding threshold which is required to inhibit consumption. Inactivation of these cells results in indiscriminate and excessive intake of all compounds, independent of taste quality or nutritional state. Conversely, acute activation of these neurons suppresses consumption of water and nutrients. The output from these neurons is required to gate activity in motor neurons that control meal initiation and consumption. Thus, our study reveals a new layer of inhibitory control in feeding circuits that is required to suppress a latent state of unrestricted and non-selective consumption. PMID:24991960

Four-Quadrant Analog Multipliers Using G4-FETs

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Blalock, Benjamin; Christoloveanu, Sorin; Chen, Suheng; Akarvardar, Kerem

2006-01-01

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Delay grid multiplexing: simple time-based multiplexing and readout method for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Won, Jun Yeon; Ko, Guen Bae; Lee, Jae Sung

2016-10-01

In this paper, we propose a fully time-based multiplexing and readout method that uses the principle of the global positioning system. Time-based multiplexing allows simplifying the multiplexing circuits where the only innate traces that connect the signal pins of the silicon photomultiplier (SiPM) channels to the readout channels are used as the multiplexing circuit. Every SiPM channel is connected to the delay grid that consists of the traces on a printed circuit board, and the inherent transit times from each SiPM channel to the readout channels encode the position information uniquely. Thus, the position of each SiPM can be identified using the time difference of arrival (TDOA) measurements. The proposed multiplexing can also allow simplification of the readout circuit using the time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA), where the time-over-threshold (ToT) is used to extract the energy information after multiplexing. In order to verify the proposed multiplexing method, we built a positron emission tomography (PET) detector that consisted of an array of 4  ×  4 LGSO crystals, each with a dimension of 3  ×  3  ×  20 mm3, and one- to-one coupled SiPM channels. We first employed the waveform sampler as an initial study, and then replaced the waveform sampler with an FPGA-TDC to further simplify the readout circuits. The 16 crystals were clearly resolved using only the time information obtained from the four readout channels. The coincidence resolving times (CRTs) were 382 and 406 ps FWHM when using the waveform sampler and the FPGA-TDC, respectively. The proposed simple multiplexing and readout methods can be useful for time-of-flight (TOF) PET scanners.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata.

PubMed

Bahar, Ali Newaz; Rahman, Mohammad Maksudur; Nahid, Nur Mohammad; Hassan, Md Kamrul

2017-02-01

This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T =2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.

Transistor Laser Optical NOR Gate for High Speed Optical Logic Processors

DTIC Science & Technology

2017-03-20

proposes an optical bistable latch can be built with two universal photonic NOR gate circuits, which are implemented by the three-port tunneling ... Tunneling Junction Transistor Laser (TJ-TL); Optical NOR Gate. Introduction To fulfill the future national security and intelligence needs in this...two-terminal diode lasers. Three-Port Transistor Laser – an Integration of Quantum-Wells into Heterojunction Bipolar Transistor Different than

Pulse transmission transmitter including a higher order time derivate filter

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-09-23

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission transmitter includes: a clock; a pseudorandom polynomial generator coupled to the clock, the pseudorandom polynomial generator having a polynomial load input; an exclusive-OR gate coupled to the pseudorandom polynomial generator, the exclusive-OR gate having a serial data input; a programmable delay circuit coupled to both the clock and the exclusive-OR gate; a pulse generator coupled to the programmable delay circuit; and a higher order time derivative filter coupled to the pulse generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Design and Implementation of Readout Circuit with Threshold Voltage Compensation on Glass Substrate for Touch Panel Applications

NASA Astrophysics Data System (ADS)

Lin, Yu-Ta; Ker, Ming-Dou; Wang, Tzu-Ming

2011-03-01

A new on-panel readout circuit with threshold voltage compensation for capacitive sensor in low temperature polycrystalline silicon (poly-Si) thin-film transistor (LTPS-TFT) process has been proposed. In order to compensate the threshold voltage variation from LTPS process variation, the proposed readout circuit applies a novel compensation approach with switch capacitor technique. In addition, a 4-bit analog-to-digital converter (ADC) is added to identify different sensed capacitor values and further enhances the overall resolution of touch panel.

Graded, Dynamically Routable Information Processing with Synfire-Gated Synfire Chains.

PubMed

Wang, Zhuo; Sornborger, Andrew T; Tao, Louis

2016-06-01

Coherent neural spiking and local field potentials are believed to be signatures of the binding and transfer of information in the brain. Coherent activity has now been measured experimentally in many regions of mammalian cortex. Recently experimental evidence has been presented suggesting that neural information is encoded and transferred in packets, i.e., in stereotypical, correlated spiking patterns of neural activity. Due to their relevance to coherent spiking, synfire chains are one of the main theoretical constructs that have been appealed to in order to describe coherent spiking and information transfer phenomena. However, for some time, it has been known that synchronous activity in feedforward networks asymptotically either approaches an attractor with fixed waveform and amplitude, or fails to propagate. This has limited the classical synfire chain's ability to explain graded neuronal responses. Recently, we have shown that pulse-gated synfire chains are capable of propagating graded information coded in mean population current or firing rate amplitudes. In particular, we showed that it is possible to use one synfire chain to provide gating pulses and a second, pulse-gated synfire chain to propagate graded information. We called these circuits synfire-gated synfire chains (SGSCs). Here, we present SGSCs in which graded information can rapidly cascade through a neural circuit, and show a correspondence between this type of transfer and a mean-field model in which gating pulses overlap in time. We show that SGSCs are robust in the presence of variability in population size, pulse timing and synaptic strength. Finally, we demonstrate the computational capabilities of SGSC-based information coding by implementing a self-contained, spike-based, modular neural circuit that is triggered by streaming input, processes the input, then makes a decision based on the processed information and shuts itself down.

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Computer-Aided Design Package for Designers of Digital Optical Computers

DTIC Science & Technology

1991-02-01

circuit depth and in circuit breadth. It appears, from initial studies by PhD students Gupta and Majidi using the newly modified tools, that a few irregular...Gupta, which is based on an earlier tool developed by Majidi . The tool allows logic gates to have fan-ins and fan-outs that vary, and allows circuits

A pH sensor with a double-gate silicon nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

2013-02-01

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

Analyzing threshold pressure limitations in microfluidic transistors for self-regulated microfluidic circuits

PubMed Central

Kim, Sung-Jin; Yokokawa, Ryuji; Takayama, Shuichi

2012-01-01

This paper reveals a critical limitation in the electro-hydraulic analogy between a microfluidic membrane-valve (μMV) and an electronic transistor. Unlike typical transistors that have similar on and off threshold voltages, in hydraulic μMVs, the threshold pressures for opening and closing are significantly different and can change, even for the same μMVs depending on overall circuit design and operation conditions. We explain, in particular, how the negative values of the closing threshold pressures significantly constrain operation of even simple hydraulic μMV circuits such as autonomously switching two-valve microfluidic oscillators. These understandings have significant implications in designing self-regulated microfluidic devices. PMID:23284181

Electronic bidirectional valve circuit prevents crossover distortion and threshold effect

NASA Technical Reports Server (NTRS)

Kernick, A.

1966-01-01

Four-terminal network forms a bidirectional valve which will switch or alternate an ac signal without crossover distortion or threshold effect. In this network, an isolated control signal is sufficient for circuit turn-on.

Plasma-enhanced atomic layer deposition zinc oxide for multifunctional thin film electronics

NASA Astrophysics Data System (ADS)

Mourey, Devin A.

A novel, weak oxidant, plasma-enhanced atomic layer deposition (PEALD) process has been used to fabricate stable, high mobility ZnO thin film transistors (TFTs) and fast circuits on glass and polyimide substrates at 200°C. Weak oxidant PEALD provides a simple, fast deposition process which results in uniform, conformal coatings and highly crystalline, dense ZnO thin films. These films and resulting devices have been compared with those prepared by spatial atomic layer deposition (SALD) throughout the work. Both PEALD and SALD ZnO TFTs have high field-effect mobility (>20 cm 2/V·s) and devices with ALD Al2O3 passivation can have excellent bias stress stability. Temperature dependent measurements of PEALD ZnO TFTs revealed a mobility activation energy < 5 meV and can be described using a simple percolation model with a Gaussian distribution of near-conduction band barriers. Interestingly, both PEALD and SALD devices operate with mobility > 1 cm2/V·s even at temperatures < 10 K. The effects of high energy irradiation have also been investigated. Devices exposed to 1 MGy of gamma irradiation showed small threshold voltage shifts (<2 V) which were fully recoverable with short (1 min) low-temperature (200°C) anneals. ZnO TFTs exhibit a range of non-ideal behavior which has direct implications on how important parameters such as mobility and threshold voltage are quantified. For example, the accumulation-dependent mobility and contact effects can lead to significant overestimations in mobility. It is also found that self-heating plays and important role in the non-ideal behavior of oxide TFTs on low thermal conductivity substrates. In particular, the output conductance and a high current device runaway breakdown effect can be directly ascribed to self-heating. Additionally, a variety of simple ZnO circuits on glass and flexible substrates were demonstrated. A backside exposure process was used to form gate-self-aligned structures with reduced parasitic capacitance and circuits with propagation delay < 10 ns/stage. Finally, to combat some of the self-heating and design challenges associated with unipolar circuits, a simple 4-mask organic-inorganic hybrid CMOS process was demonstrated.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment.

PubMed

Porrazzo, Rossella; Luzio, Alessandro; Bellani, Sebastiano; Bonacchini, Giorgio Ernesto; Noh, Yong-Young; Kim, Yun-Hi; Lanzani, Guglielmo; Antognazza, Maria Rosa; Caironi, Mario

2017-01-31

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm -2 in full accumulation and a mobility-capacitance product of 7 × 10 -3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

ELECTRICAL LOAD ANTICIPATOR AND RECORDER

DOEpatents

Russell, J.B.; Thomas, R.J.

1961-07-25

A system is descrbied in which an indication of the prevailing energy consumption in an electrical power metering system and a projected Power demand for one demand interval is provided at selected increments of time withm the demand interval. Each watthour meter in the system is provided with an impulse generator that generates two impulses for each revolution of the meter disc. The total pulses received frorn all the meters are continuously totaled and are fed to a plurality of parallel connected gated counters. Each counter has its gate opened at different sub-time intervals during the demand interval. A multiplier is connected to each of the gated counters except the last one and each multiplier is provided with a different multiplier constant so as to provide an estimate of the power to be drawn over the entire demand interval at the end of each of the different sub-time intervals. Means are provided for recording the ontputs from the different circuits in synchronism with the actuation oi each gate circuit.

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

PubMed Central

2017-01-01

The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation. PMID:28180187

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

PubMed

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

N channel JFET based digital logic gate structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor)

2010-01-01

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1982-01-01

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

On the photonic implementation of universal quantum gates, bell states preparation circuit and quantum LDPC encoders and decoders based on directional couplers and HNLF.

PubMed

Djordjevic, Ivan B

2010-04-12

The Bell states preparation circuit is a basic circuit required in quantum teleportation. We describe how to implement it in all-fiber technology. The basic building blocks for its implementation are directional couplers and highly nonlinear optical fiber (HNLF). Because the quantum information processing is based on delicate superposition states, it is sensitive to quantum errors. In order to enable fault-tolerant quantum computing the use of quantum error correction is unavoidable. We show how to implement in all-fiber technology encoders and decoders for sparse-graph quantum codes, and provide an illustrative example to demonstrate this implementation. We also show that arbitrary set of universal quantum gates can be implemented based on directional couplers and HNLFs.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Entangling distant resonant exchange qubits via circuit quantum electrodynamics

NASA Astrophysics Data System (ADS)

Srinivasa, V.; Taylor, J. M.; Tahan, Charles

2016-11-01

We investigate a hybrid quantum system consisting of spatially separated resonant exchange qubits, defined in three-electron semiconductor triple quantum dots, that are coupled via a superconducting transmission line resonator. Drawing on methods from circuit quantum electrodynamics and Hartmann-Hahn double resonance techniques, we analyze three specific approaches for implementing resonator-mediated two-qubit entangling gates in both dispersive and resonant regimes of interaction. We calculate entangling gate fidelities as well as the rate of relaxation via phonons for resonant exchange qubits in silicon triple dots and show that such an implementation is particularly well suited to achieving the strong coupling regime. Our approach combines the favorable coherence properties of encoded spin qubits in silicon with the rapid and robust long-range entanglement provided by circuit QED systems.

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

NASA Technical Reports Server (NTRS)

Shuler, Robert L.; Balasubramanian, Anupama; Narasimham, Balaji; Bhuva, Bharat; O'Neill, Patrick M.; Kouba, Coy

2006-01-01

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

A Survey of Memristive Threshold Logic Circuits.

PubMed

Maan, Akshay Kumar; Jayadevi, Deepthi Anirudhan; James, Alex Pappachen

2017-08-01

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO 2 , ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

Design and Application of a Circuit for Measuring Frequency and Duty Cycle of Stimulated Bioelectrical Signal

NASA Astrophysics Data System (ADS)

Tang, Li-Ming; Chang, Ben-Kang; Liu, Tie-Bing; Wu, Min; Ling, Gang

2002-12-01

To design a new type of circuit for measuring frequency & duty cycle of stimulated bioelectrical signal for the project of 'the map of neuron-threshold in human brain and its clinical application'. This circuit was designed according to the character of stimulated bioelectrical signals. It was tested and improved and then used in the neuron -threshold stimulator. The circuit was found to be very accurate for measuring frequency and the error for measuring duty cycle was below 0.2%. This circuit is well-designed, simple, easy to use, and can be applied in many systems.

Logical qubit fusion

NASA Astrophysics Data System (ADS)

Moussa, Jonathan; Ryan-Anderson, Ciaran

The canonical modern plan for universal quantum computation is a Clifford+T gate set implemented in a topological error-correcting code. This plan has the basic disparity that logical Clifford gates are natural for codes in two spatial dimensions while logical T gates are natural in three. Recent progress has reduced this disparity by proposing logical T gates in two dimensions with doubled, stacked, or gauge color codes, but these proposals lack an error threshold. An alternative universal gate set is Clifford+F, where a fusion (F) gate converts two logical qubits into a logical qudit. We show that logical F gates can be constructed by identifying compatible pairs of qubit and qudit codes that stabilize the same logical subspace, much like the original Bravyi-Kitaev construction of magic state distillation. The simplest example of high-distance compatible codes results in a proposal that is very similar to the stacked color code with the key improvement of retaining an error threshold. Sandia National Labs is a multi-program laboratory managed and operated by Sandia Corp, a wholly owned subsidiary of Lockheed Martin Corp, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

Simulation Model of A Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen; Russell, Larry W. (Technical Monitor)

2002-01-01

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

AMPLITUDE DISCRIMINATOR HAVING SEPARATE TRIGGERING AND RECOVERY CONTROLS UTILIZING AUTOMATIC TRIGGERING

DOEpatents

Chase, R.L.

1962-01-23

A transistorized amplitude discriminator circuit is described in which the initial triggering sensitivity and the recovery threshold are separately adjustable in a convenient manner. The discriminator is provided with two independent bias components, one of which is for circuit hysteresis (recovery) and one of which is for trigger threshold level. A switching circuit is provided to remove the second bias component upon activation of the trigger so that the recovery threshold is always at the point where the trailing edge of the input signal pulse goes through zero or other desired value. (AEC)

Regenerative Snubber For GTO-Commutated SCR Inverter

NASA Technical Reports Server (NTRS)

Rippel, Wally E.; Edwards, Dean B.

1992-01-01

Proposed regenerative snubbing circuit substituted for dissipative snubbing circuit in inverter based on silicon controlled rectifiers (SCR's) commutated by gate-turn-off thyristor (GTO). Intended to reduce loss of power that occurs in dissipative snubber. Principal criteria in design: low cost, simplicity, and reliability.

Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates

PubMed Central

Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda

2012-01-01

One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039

Electronic Model of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen; Russell, Larry (Technical Monitor)

2001-01-01

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

New PMOS LTPS TFT pixel for AMOLED to suppress the hysteresis effect on OLED current by employing a reset voltage driving

NASA Astrophysics Data System (ADS)

Lee, Jae-Hoon; Park, Sang-Geun; Han, Sang-Myeon; Han, Min-Koo; Park, Kee-Chan

2008-03-01

New PMOS LTPS (low temperature polycrystalline silicon)-thin film transistor (TFT) pixel circuit, which can suppress an OLED current error caused by the hysteresis of LTPS-TFT for active matrix organic light emitting diode (AMOLED) display, is proposed and fabricated. The proposed pixel circuit employs a reset voltage driving so that the sweep direction of gate voltage in the current driving TFT is not altered by the gate voltage in the previous frame. Our experimental results show that OLED current error of the proposed pixel is successfully suppressed because a reset voltage can enable the starting gate voltage for a desired one not to be varied, while that of the conventional 2-TFT pixel exceeds over 15% due to the hysteresis of LTPS-TFT.

Holonomic Quantum Control with Continuous Variable Systems.

PubMed

Albert, Victor V; Shu, Chi; Krastanov, Stefan; Shen, Chao; Liu, Ren-Bao; Yang, Zhen-Biao; Schoelkopf, Robert J; Mirrahimi, Mazyar; Devoret, Michel H; Jiang, Liang

2016-04-08

Universal computation of a quantum system consisting of superpositions of well-separated coherent states of multiple harmonic oscillators can be achieved by three families of adiabatic holonomic gates. The first gate consists of moving a coherent state around a closed path in phase space, resulting in a relative Berry phase between that state and the other states. The second gate consists of "colliding" two coherent states of the same oscillator, resulting in coherent population transfer between them. The third gate is an effective controlled-phase gate on coherent states of two different oscillators. Such gates should be realizable via reservoir engineering of systems that support tunable nonlinearities, such as trapped ions and circuit QED.

Electro-optical graphene plasmonic logic gates.

PubMed

Ooi, Kelvin J A; Chu, Hong Son; Bai, Ping; Ang, Lay Kee

2014-03-15

The versatile control of graphene's plasmonic modes via an external gate-voltage inspires us to design efficient electro-optical graphene plasmonic logic gates at the midinfrared wavelengths. We show that these devices are superior to the conventional optical logic gates because the former possess cut-off states and interferometric effects. Moreover, the designed six basic logic gates (i.e., NOR/AND, NAND/OR, XNOR/XOR) achieved not only ultracompact size lengths of less than λ/28 with respect to the operating wavelength of 10 μm, but also a minimum extinction ratio as high as 15 dB. These graphene plasmonic logic gates are potential building blocks for future nanoscale midinfrared photonic integrated circuits.

DIGITAL Q METER

DOEpatents

Briscoe, W.L.

1962-02-13

A digital Q meter is described for measuring the Q of mechanical or electrical devices. The meter comprises in combination a transducer coupled to an input amplifier, and an upper and lower level discriminator coupled to the amplifier and having their outputs coupled to an anticoincidence gate. The output of the gate is connected to a scaler. The lower level discriminator is adjusted to a threshold level of 36.8 percent of the operating threshold level of the upper level discriminator. (AEC)

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Optical XOR gate

DOEpatents

Vawter, G. Allen

2013-11-12

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2006-12-12

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2004-05-18

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Stable indium oxide thin-film transistors with fast threshold voltage recovery

NASA Astrophysics Data System (ADS)

Vygranenko, Yuriy; Wang, Kai; Nathan, Arokia

2007-12-01

Stable thin-film transistors (TFTs) with semiconducting indium oxide channel and silicon dioxide gate dielectric were fabricated by reactive ion beam assisted evaporation and plasma-enhanced chemical vapor deposition. The field-effect mobility is 3.3cm2/Vs, along with an on/off current ratio of 106, and subthreshold slope of 0.5V/decade. When subject to long-term gate bias stress, the TFTs show fast recovery of the threshold voltage (VT) when relaxed without annealing, suggesting that charge trapping at the interface and/or in the bulk gate dielectric to be the dominant mechanism underlying VT instability. Device performance and stability make indium oxide TFTs promising for display applications.

Optoelectronic Integrated Circuits For Neural Networks

NASA Technical Reports Server (NTRS)

Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

1990-01-01

Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

High-fidelity gates towards a scalable superconducting quantum processor

NASA Astrophysics Data System (ADS)

Chow, Jerry M.; Corcoles, Antonio D.; Gambetta, Jay M.; Rigetti, Chad; Johnson, Blake R.; Smolin, John A.; Merkel, Seth; Poletto, Stefano; Rozen, Jim; Rothwell, Mary Beth; Keefe, George A.; Ketchen, Mark B.; Steffen, Matthias

2012-02-01

We experimentally explore the implementation of high-fidelity gates on multiple superconducting qubits coupled to multiple resonators. Having demonstrated all-microwave single and two qubit gates with fidelities > 90% on multi-qubit single-resonator systems, we expand the application to qubits across two resonators and investigate qubit coupling in this circuit. The coupled qubit-resonators are building blocks towards two-dimensional lattice networks for the application of surface code quantum error correction algorithms.

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Redundancy Technology With A Focused Ion Beam

NASA Astrophysics Data System (ADS)

Komano, Haruki; Hashimoto, Kazuhiko; Takigawa, Tadahiro

1989-08-01

Fuse cutting with a focused ion beam to activate redundancy circuits is proposed. In order to verify its potential usefulness, experiments have been performed. Fuse-cutting time was evaluated using aluminum fuses with a thin passivation layer, which are difficult to cut by conventional laser-beam technology due to the material's high reflectivity. The fuse width and thickness were 2 and 0.8 μm, respectively. The fuse was cut in 5 seconds with a 30 keV focused ion beam of 0.3 A/cm2 current density. Since the fuses used in DRAMs will be smaller, their cutting time will become shorter by scanning an ion beam on narrower areas. Moreover, it can be shortened by increasing current density. Fuses for redundancy technology in 256 k CMOS SRAMs were cut with a focused ion beam. The operation of the memories was checked with a memory tester. It was confirmed that memories which had failure cells operated normally after focused-ion-beam fuse-cutting. Focused ion beam irradiation effects upon a device have been studied. When a 30 keV gallium focused ion beam was irradiated near the gate of MOSFETs, a threshold voltage shift was not observed at an ion dose of 0.3 C/cm2 which corresponded to the ion dose in cutting a fuse. However, when irradiated on the gate, a threshold voltage shift was observed at ion doses of more than 8 x 10-4 C/cm2. The voltage shift was caused by the charge of ions within the passivation layer. It is necessary at least not to irradiate a focused ion beam on a device in cutting fuses. It is concluded that the focused-ion-beam method will be advantageous for future redundancy technology application.

Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

PubMed

Ha, Mingjing; Zhang, Wei; Braga, Daniele; Renn, Michael J; Kim, Chris H; Frisbie, C Daniel

2013-12-26

In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

The role of Snell's law for a magnonic majority gate.

PubMed

Kanazawa, Naoki; Goto, Taichi; Sekiguchi, Koji; Granovsky, Alexander B; Ross, Caroline A; Takagi, Hiroyuki; Nakamura, Yuichi; Uchida, Hironaga; Inoue, Mitsuteru

2017-08-11

In the fifty years since the postulation of Moore's Law, the increasing energy consumption in silicon electronics has motivated research into emerging devices. An attractive research direction is processing information via the phase of spin waves within magnonic-logic circuits, which function without charge transport and the accompanying heat generation. The functional completeness of magnonic logic circuits based on the majority function was recently proved. However, the performance of such logic circuits was rather poor due to the difficulty of controlling spin waves in the input junction of the waveguides. Here, we show how Snell's law describes the propagation of spin waves in the junction of a Ψ-shaped magnonic majority gate composed of yttrium iron garnet with a partially metallized surface. Based on the analysis, we propose a magnonic counterpart of a core-cladding waveguide to control the wave propagation in the junction. This study has therefore experimentally demonstrated a fundamental building block of a magnonic logic circuit.

Demonstration of qubit operations below a rigorous fault tolerance threshold with gate set tomography

DOE PAGES

Blume-Kohout, Robin; Gamble, John King; Nielsen, Erik; ...

2017-02-15

Quantum information processors promise fast algorithms for problems inaccessible to classical computers. But since qubits are noisy and error-prone, they will depend on fault-tolerant quantum error correction (FTQEC) to compute reliably. Quantum error correction can protect against general noise if—and only if—the error in each physical qubit operation is smaller than a certain threshold. The threshold for general errors is quantified by their diamond norm. Until now, qubits have been assessed primarily by randomized benchmarking, which reports a different error rate that is not sensitive to all errors, and cannot be compared directly to diamond norm thresholds. Finally, we usemore » gate set tomography to completely characterize operations on a trapped-Yb +-ion qubit and demonstrate with greater than 95% confidence that they satisfy a rigorous threshold for FTQEC (diamond norm ≤6.7 × 10 -4).« less

Demonstration of qubit operations below a rigorous fault tolerance threshold with gate set tomography

PubMed Central

Blume-Kohout, Robin; Gamble, John King; Nielsen, Erik; Rudinger, Kenneth; Mizrahi, Jonathan; Fortier, Kevin; Maunz, Peter

2017-01-01

Quantum information processors promise fast algorithms for problems inaccessible to classical computers. But since qubits are noisy and error-prone, they will depend on fault-tolerant quantum error correction (FTQEC) to compute reliably. Quantum error correction can protect against general noise if—and only if—the error in each physical qubit operation is smaller than a certain threshold. The threshold for general errors is quantified by their diamond norm. Until now, qubits have been assessed primarily by randomized benchmarking, which reports a different error rate that is not sensitive to all errors, and cannot be compared directly to diamond norm thresholds. Here we use gate set tomography to completely characterize operations on a trapped-Yb+-ion qubit and demonstrate with greater than 95% confidence that they satisfy a rigorous threshold for FTQEC (diamond norm ≤6.7 × 10−4). PMID:28198466

Demonstration of qubit operations below a rigorous fault tolerance threshold with gate set tomography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blume-Kohout, Robin; Gamble, John King; Nielsen, Erik

Quantum information processors promise fast algorithms for problems inaccessible to classical computers. But since qubits are noisy and error-prone, they will depend on fault-tolerant quantum error correction (FTQEC) to compute reliably. Quantum error correction can protect against general noise if—and only if—the error in each physical qubit operation is smaller than a certain threshold. The threshold for general errors is quantified by their diamond norm. Until now, qubits have been assessed primarily by randomized benchmarking, which reports a different error rate that is not sensitive to all errors, and cannot be compared directly to diamond norm thresholds. Finally, we usemore » gate set tomography to completely characterize operations on a trapped-Yb +-ion qubit and demonstrate with greater than 95% confidence that they satisfy a rigorous threshold for FTQEC (diamond norm ≤6.7 × 10 -4).« less

Interface engineering of semiconductor/dielectric heterojunctions toward functional organic thin-film transistors.

PubMed

Zhang, Hongtao; Guo, Xuefeng; Hui, Jingshu; Hu, Shuxin; Xu, Wei; Zhu, Daoben

2011-11-09

Interface modification is an effective and promising route for developing functional organic field-effect transistors (OFETs). In this context, however, researchers have not created a reliable method of functionalizing the interfaces existing in OFETs, although this has been crucial for the technological development of high-performance CMOS circuits. Here, we demonstrate a novel approach that enables us to reversibly photocontrol the carrier density at the interface by using photochromic spiropyran (SP) self-assembled monolayers (SAMs) sandwiched between active semiconductors and gate insulators. Reversible changes in dipole moment of SPs in SAMs triggered by lights with different wavelengths produce two distinct built-in electric fields on the OFET that can modulate the channel conductance and consequently threshold voltage values, thus leading to a low-cost noninvasive memory device. This concept of interface functionalization offers attractive new prospects for the development of organic electronic devices with tailored electronic and other properties.

A network model of behavioural performance in a rule learning task.

PubMed

Hasselmo, Michael E; Stern, Chantal E

2018-04-19

Humans demonstrate differences in performance on cognitive rule learning tasks which could involve differences in properties of neural circuits. An example model is presented to show how gating of the spread of neural activity could underlie rule learning and the generalization of rules to previously unseen stimuli. This model uses the activity of gating units to regulate the pattern of connectivity between neurons responding to sensory input and subsequent gating units or output units. This model allows analysis of network parameters that could contribute to differences in cognitive rule learning. These network parameters include differences in the parameters of synaptic modification and presynaptic inhibition of synaptic transmission that could be regulated by neuromodulatory influences on neural circuits. Neuromodulatory receptors play an important role in cognitive function, as demonstrated by the fact that drugs that block cholinergic muscarinic receptors can cause cognitive impairments. In discussions of the links between neuromodulatory systems and biologically based traits, the issue of mechanisms through which these linkages are realized is often missing. This model demonstrates potential roles of neural circuit parameters regulated by acetylcholine in learning context-dependent rules, and demonstrates the potential contribution of variation in neural circuit properties and neuromodulatory function to individual differences in cognitive function.This article is part of the theme issue 'Diverse perspectives on diversity: multi-disciplinary approaches to taxonomies of individual differences'. © 2018 The Author(s).

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Quantum Algorithms to Simulate Many-Body Physics of Correlated Fermions

NASA Astrophysics Data System (ADS)

Jiang, Zhang; Sung, Kevin J.; Kechedzhi, Kostyantyn; Smelyanskiy, Vadim N.; Boixo, Sergio

2018-04-01

Simulating strongly correlated fermionic systems is notoriously hard on classical computers. An alternative approach, as proposed by Feynman, is to use a quantum computer. We discuss simulating strongly correlated fermionic systems using near-term quantum devices. We focus specifically on two-dimensional (2D) or linear geometry with nearest-neighbor qubit-qubit couplings, typical for superconducting transmon qubit arrays. We improve an existing algorithm to prepare an arbitrary Slater determinant by exploiting a unitary symmetry. We also present a quantum algorithm to prepare an arbitrary fermionic Gaussian state with O (N2) gates and O (N ) circuit depth. Both algorithms are optimal in the sense that the numbers of parameters in the quantum circuits are equal to those describing the quantum states. Furthermore, we propose an algorithm to implement the 2D fermionic Fourier transformation on a 2D qubit array with only O (N1.5) gates and O (√{N }) circuit depth, which is the minimum depth required for quantum information to travel across the qubit array. We also present methods to simulate each time step in the evolution of the 2D Fermi-Hubbard model—again on a 2D qubit array—with O (N ) gates and O (√{N }) circuit depth. Finally, we discuss how these algorithms can be used to determine the ground-state properties and phase diagrams of strongly correlated quantum systems using the Hubbard model as an example.

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

NASA Astrophysics Data System (ADS)

Chakraborty, S.; Dasgupta, A.; Das, R.; Kar, M.; Kundu, A.; Sarkar, C. K.

2017-12-01

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.

AlGaN/GaN High Electron Mobility Transistor-Based Biosensor for the Detection of C-Reactive Protein

PubMed Central

Lee, Hee Ho; Bae, Myunghan; Jo, Sung-Hyun; Shin, Jang-Kyoo; Son, Dong Hyeok; Won, Chul-Ho; Jeong, Hyun-Min; Lee, Jung-Hee; Kang, Shin-Won

2015-01-01

In this paper, we propose an AlGaN/GaN high electron mobility transistor (HEMT)-based biosensor for the detection of C-reactive protein (CRP) using a null-balancing circuit. A null-balancing circuit was used to measure the output voltage of the sensor directly. The output voltage of the proposed biosensor was varied by antigen-antibody interactions on the gate surface due to CRP charges. The AlGaN/GaN HFET-based biosensor with null-balancing circuit applied shows that CRP can be detected in a wide range of concentrations, varying from 10 ng/mL to 1000 ng/mL. X-ray photoelectron spectroscopy was carried out to verify the immobilization of self-assembled monolayer with Au on the gated region. PMID:26225981

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Razavi, S. M.; Ebrahim Hosseini, Seyed; Amini Moghadam, Hamid

2011-11-01

In this paper, the potential impact of drain side-double recessed gate (DS-DRG) on silicon carbide (SiC)-based metal semiconductor field effect transistors (MESFETs) is studied. We investigate the device performance focusing on breakdown voltage, threshold voltage, drain current and dc output conductance with two-dimensional and two-carrier device simulation. Our simulation results demonstrate that the channel thickness under the gate in the drain side is an important factor in the breakdown voltage. Also, the positive shift in the threshold voltage for the DS-DRG structure is larger in comparison with that for the source side-double recessed gate (SS-DRG) SiC MESFET. The saturated drain current for the DS-DRG structure is larger compared to that for the SS-DRG structure. The maximum dc output conductance in the DS-DRG structure is smaller than that in the SS-DRG structure.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Won Lee, Sang; Suh, Dongseok, E-mail: energy.suh@skku.edu; Department of Energy Science and Department of Physics, Sungkyunkwan University, Suwon 440-746

A prior requirement of any developed transistor for practical use is the stability test. Random network carbon nanotube-thin film transistor (CNT-TFT) was fabricated on SiO{sub 2}/Si. Gate bias stress stability was investigated with various passivation layers of HfO{sub 2} and Al{sub 2}O{sub 3}. Compared to the threshold voltage shift without passivation layer, the measured values in the presence of passivation layers were reduced independent of gate bias polarity except HfO{sub 2} under positive gate bias stress (PGBS). Al{sub 2}O{sub 3} capping layer was found to be the best passivation layer to prevent ambient gas adsorption, while gas adsorption on HfO{submore » 2} layer was unavoidable, inducing surface charges to increase threshold voltage shift in particular for PGBS. This high performance in the gate bias stress test of CNT-TFT even superior to that of amorphous silicon opens potential applications to active TFT industry for soft electronics.« less

Modeling of Dual Gate Material Hetero-dielectric Strained PNPN TFET for Improved ON Current

NASA Astrophysics Data System (ADS)

Kumari, Tripty; Saha, Priyanka; Dash, Dinesh Kumar; Sarkar, Subir Kumar

2018-01-01

The tunnel field effect transistor (TFET) is considered to be a promising alternative device for future low-power VLSI circuits due to its steep subthreshold slope, low leakage current and its efficient performance at low supply voltage. However, the main challenging issue associated with realizing TFET for wide scale applications is its low ON current. To overcome this, a dual gate material with the concept of dielectric engineering has been incorporated into conventional TFET structure to tune the tunneling width at source-channel interface allowing significant flow of carriers. In addition to this, N+ pocket is implanted at source-channel junction of the proposed structure and the effect of strain is added for exploring the performance of the model in nanoscale regime. All these added features upgrade the device characteristics leading to higher ON current, low leakage and low threshold voltage. The present work derives the surface potential, electric field expression and drain current by solving 2D Poisson's equation at different boundary conditions. A comparative analysis of proposed model with conventional TFET has been done to establish the superiority of the proposed structure. All analytical results have been compared with the results obtained in SILVACO ATLAS device simulator to establish the accuracy of the derived analytical model.

Universal model of bias-stress-induced instability in inkjet-printed carbon nanotube networks field-effect transistors

NASA Astrophysics Data System (ADS)

Jung, Haesun; Choi, Sungju; Jang, Jun Tae; Yoon, Jinsu; Lee, Juhee; Lee, Yongwoo; Rhee, Jihyun; Ahn, Geumho; Yu, Hye Ri; Kim, Dong Myong; Choi, Sung-Jin; Kim, Dae Hwan

2018-02-01

We propose a universal model for bias-stress (BS)-induced instability in the inkjet-printed carbon nanotube (CNT) networks used in field-effect transistors (FETs). By combining two experimental methods, i.e., a comparison between air and vacuum BS tests and interface trap extraction, BS instability is explained regardless of either the BS polarity or ambient condition, using a single platform constituted by four key factors: OH- adsorption/desorption followed by a change in carrier concentration, electron concentration in CNT channel corroborated with H2O/O2 molecules in ambient, charge trapping/detrapping, and interface trap generation. Under negative BS (NBS), the negative threshold voltage shift (ΔVT) is dominated by OH- desorption, which is followed by hole trapping in the interface and/or gate insulator. Under positive BS (PBS), the positive ΔVT is dominated by OH- adsorption, which is followed by electron trapping in the interface and/or gate insulator. This instability is compensated by interface trap extraction; PBS instability is slightly more complicated than NBS instability. Furthermore, our model is verified using device simulation, which gives insights on how much each mechanism contributes to BS instability. Our result is potentially useful for the design of highly stable CNT-based flexible circuits in the Internet of Things wearable healthcare era.

Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization

NASA Astrophysics Data System (ADS)

Choi, Woo Young; Woo, Dong-Soo; Choi, Byung Yong; Lee, Jong Duk; Park, Byung-Gook

2004-04-01

We proposed a stable extraction algorithm for threshold voltage using transconductance change method by optimizing node interval. With the algorithm, noise-free gm2 (=dgm/dVGS) profiles can be extracted within one-percent error, which leads to more physically-meaningful threshold voltage calculation by the transconductance change method. The extracted threshold voltage predicts the gate-to-source voltage at which the surface potential is within kT/q of φs=2φf+VSB. Our algorithm makes the transconductance change method more practical by overcoming noise problem. This threshold voltage extraction algorithm yields the threshold roll-off behavior of nanoscale metal oxide semiconductor field effect transistor (MOSFETs) accurately and makes it possible to calculate the surface potential φs at any other point on the drain-to-source current (IDS) versus gate-to-source voltage (VGS) curve. It will provide us with a useful analysis tool in the field of device modeling, simulation and characterization.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

A Novel Implementation of Efficient Algorithms for Quantum Circuit Synthesis

NASA Astrophysics Data System (ADS)

Zeller, Luke

In this project, we design and develop a computer program to effectively approximate arbitrary quantum gates using the discrete set of Clifford Gates together with the T gate (π/8 gate). Employing recent results from Mosca et. al. and Giles and Selinger, we implement a decomposition scheme that outputs a sequence of Clifford, T, and Tt gates that approximate the input to within a specified error range ɛ. Specifically, the given gate is first rounded to an element of Z[1/2, i] with a precision determined by ɛ, and then exact synthesis is employed to produce the resulting gate. It is known that this procedure is optimal in approximating an arbitrary single qubit gate. Our program, written in Matlab and Python, can complete both approximate and exact synthesis of qubits. It can be used to assist in the experimental implementation of an arbitrary fault-tolerant single qubit gate, for which direct implementation isn't feasible.

Electronics. Module 3: Digital Logic Application. Instructor's Guide.

ERIC Educational Resources Information Center

Carter, Ed; Murphy, Mark

This guide contains instructor's materials for a 10-unit secondary school course on digital logic application. The units are introduction to digital, logic gates, digital integrated circuits, combination logic, flip-flops, counters and shift registers, encoders and decoders, arithmetic circuits, memory, and analog/digital and digital/analog…

Three-input majority logic gate and multiple input logic circuit based on DNA strand displacement.

PubMed

Li, Wei; Yang, Yang; Yan, Hao; Liu, Yan

2013-06-12

In biomolecular programming, the properties of biomolecules such as proteins and nucleic acids are harnessed for computational purposes. The field has gained considerable attention due to the possibility of exploiting the massive parallelism that is inherent in natural systems to solve computational problems. DNA has already been used to build complex molecular circuits, where the basic building blocks are logic gates that produce single outputs from one or more logical inputs. We designed and experimentally realized a three-input majority gate based on DNA strand displacement. One of the key features of a three-input majority gate is that the three inputs have equal priority, and the output will be true if any of the two inputs are true. Our design consists of a central, circular DNA strand with three unique domains between which are identical joint sequences. Before inputs are introduced to the system, each domain and half of each joint is protected by one complementary ssDNA that displays a toehold for subsequent displacement by the corresponding input. With this design the relationship between any two domains is analogous to the relationship between inputs in a majority gate. Displacing two or more of the protection strands will expose at least one complete joint and return a true output; displacing none or only one of the protection strands will not expose a complete joint and will return a false output. Further, we designed and realized a complex five-input logic gate based on the majority gate described here. By controlling two of the five inputs the complex gate can realize every combination of OR and AND gates of the other three inputs.

Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

PubMed

LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

2014-06-02

We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching.

Similarity between the response of memristive and memcapacitive circuits subjected to ramped voltage

NASA Astrophysics Data System (ADS)

Kanygin, Mikhail A.; Katkov, Mikhail V.; Pershin, Yuriy V.

2017-07-01

We report a similar feature in the response of resistor-memristor and capacitor-memcapacitor circuits with threshold-type memory devices driven by triangular waveform voltage. In both cases, the voltage across the memory device is stabilized during the switching of the memory device state. While in the memristive circuit this feature is observed when the applied voltage changes in one direction, the memcapacitive circuit with a ferroelectric memcapacitor demonstrates the voltage stabilization effect at both sweep directions. The discovered behavior of capacitor-memcapacitor circuit is also demonstrated experimentally. We anticipate that our observation can be used in the design of electronic circuits with emergent memory devices as well as in the identification and characterization of memory effects in threshold-type memory devices.

2D Quantum Transport Modeling in Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Acousto-optic modulation and opto-acoustic gating in piezo-optomechanical circuits

PubMed Central

Balram, Krishna C.; Davanço, Marcelo I.; Ilic, B. Robert; Kyhm, Ji-Hoon; Song, Jin Dong; Srinivasan, Kartik

2017-01-01

Acoustic wave devices provide a promising chip-scale platform for efficiently coupling radio frequency (RF) and optical fields. Here, we use an integrated piezo-optomechanical circuit platform that exploits both the piezoelectric and photoelastic coupling mechanisms to link 2.4 GHz RF waves to 194 THz (1550 nm) optical waves, through coupling to propagating and localized 2.4 GHz acoustic waves. We demonstrate acousto-optic modulation, resonant in both the optical and mechanical domains, in which waveforms encoded on the RF carrier are mapped to the optical field. We also show opto-acoustic gating, in which the application of modulated optical pulses interferometrically gates the transmission of propagating acoustic pulses. The time-domain characteristics of this system under both pulsed RF and pulsed optical excitation are considered in the context of the different physical pathways involved in driving the acoustic waves, and modelled through the coupled mode equations of cavity optomechanics. PMID:28580373

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

An adiabatic quantum flux parametron as an ultra-low-power logic device

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Ozawa, Dan; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2013-03-01

Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of IcΦ0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Because advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

ERIC Educational Resources Information Center

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

Time-division multiplexer uses digital gates

NASA Technical Reports Server (NTRS)

Myers, C. E.; Vreeland, A. E.

1977-01-01

Device eliminates errors caused by analog gates in multiplexing a large number of channels at high frequency. System was designed for use in aerospace work to multiplex signals for monitoring such variables as fuel consumption, pressure, temperature, strain, and stress. Circuit may be useful in monitoring variables in process control and medicine as well.

Dual-gate GaAs FET switches

NASA Astrophysics Data System (ADS)

Vorhaus, J. L.; Fabian, W.; Ng, P. B.; Tajima, Y.

1981-02-01

A set of multi-pole, multi-throw switch devices consisting of dual-gate GaAs FET's is described. Included are single-pole, single-throw (SPST), double-pole, double-throw (DPDT), and single-pole four-throw (SP4T) switches. Device fabrication and measurement techniques are discussed. The device models for these switches were based on an equivalent circuit of a dual-gate FET. The devices were found to have substantial gain in X-band and low Ku-band.

GaN HEMTs with p-GaN gate: field- and time-dependent degradation

NASA Astrophysics Data System (ADS)

Meneghesso, G.; Meneghini, M.; Rossetto, I.; Canato, E.; Bartholomeus, J.; De Santi, C.; Trivellin, N.; Zanoni, E.

2017-02-01

GaN-HEMTs with p-GaN gate have recently demonstrated to be excellent normally-off devices for application in power conversion systems, thanks to the high and robust threshold voltage (VTH>1 V), the high breakdown voltage, and the low dynamic Ron increase. For this reason, studying the stability and reliability of these devices under high stress conditions is of high importance. This paper reports on our most recent results on the field- and time-dependent degradation of GaN-HEMTs with p-GaN gate submitted to stress with positive gate bias. Based on combined step-stress experiments, constant voltage stress and electroluminescence testing we demonstrated that: (i) when submitted to high/positive gate stress, the transistors may show a negative threshold voltage shift, that is ascribed to the injection of holes from the gate metal towards the p-GaN/AlGaN interface; (ii) in a step-stress experiment, the analyzed commercial devices fail at gate voltages higher than 9-10 V, due to the extremely high electric field over the p-GaN/AlGaN stack; (iii) constant voltage stress tests indicate that the failure is also time-dependent and Weibull distributed. The several processes that can explain the time-dependent failure are discussed in the following.

Transient digitizer with displacement current samplers

DOEpatents

McEwan, T.E.

1996-05-21

A low component count, high speed sample gate, and digitizer architecture using the sample gates is based on use of a signal transmission line, a strobe transmission line and a plurality of sample gates connected to the sample transmission line at a plurality of positions. The sample gates include a strobe pickoff structure near the strobe transmission line which generates a charge displacement current in response to propagation of the strobe signal on the strobe transmission line sufficient to trigger the sample gate. The sample gate comprises a two-diode sampling bridge and is connected to a meandered signal transmission line at one end and to a charge-holding cap at the other. The common cathodes are reverse biased. A voltage step is propagated down the strobe transmission line. As the step propagates past a capacitive pickoff, displacement current i=c(dv/dT), flows into the cathodes, driving the bridge into conduction and thereby charging the charge-holding capacitor to a value related to the signal. A charge amplifier converts the charge on the charge-holding capacitor to an output voltage. The sampler is mounted on a printed circuit board, and the sample transmission line and strobe transmission line comprise coplanar microstrips formed on a surface of the substrate. Also, the strobe pickoff structure may comprise a planar pad adjacent the strobe transmission line on the printed circuit board. 16 figs.

Transient digitizer with displacement current samplers

DOEpatents

McEwan, Thomas E.

1996-01-01

A low component count, high speed sample gate, and digitizer architecture using the sample gates is based on use of a signal transmission line, a strobe transmission line and a plurality of sample gates connected to the sample transmission line at a plurality of positions. The sample gates include a strobe pickoff structure near the strobe transmission line which generates a charge displacement current in response to propagation of the strobe signal on the strobe transmission line sufficient to trigger the sample gate. The sample gate comprises a two-diode sampling bridge and is connected to a meandered signal transmission line at one end and to a charge-holding cap at the other. The common cathodes are reverse biased. A voltage step is propagated down the strobe transmission line. As the step propagates past a capacitive pickoff, displacement current i=c(dv/dT), flows into the cathodes, driving the bridge into conduction and thereby charging the charge-holding capacitor to a value related to the signal. A charge amplifier converts the charge on the charge-holding capacitor to an output voltage. The sampler is mounted on a printed circuit board, and the sample transmission line and strobe transmission line comprise coplanar microstrips formed on a surface of the substrate. Also, the strobe pickoff structure may comprise a planar pad adjacent the strobe transmission line on the printed circuit board.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Niang, K. M.; Flewitt, A. J., E-mail: ajf@eng.cam.ac.uk; Barquinha, P. M. C.

Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys.more » 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.« less

A CMOS matrix for extracting MOSFET parameters before and after irradiation

NASA Technical Reports Server (NTRS)

Blaes, B. R.; Buehler, M. G.; Lin, Y.-S.; Hicks, K. A.

1988-01-01

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

NASA Astrophysics Data System (ADS)

Tang, Lan-Feng; Yu, Guang; Lu, Hai; Wu, Chen-Fei; Qian, Hui-Min; Zhou, Dong; Zhang, Rong; Zheng, You-Dou; Huang, Xiao-Ming

2015-08-01

The influence of white light illumination on the stability of an amorphous InGaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed. Project supported by the State Key Program for Basic Research of China (Grant Nos. 2011CB301900 and 2011CB922100) and the Priority Academic Program Development of Jiangsu Higher Education Institutions, China.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Methods for Quantum Circuit Design and Simulation

DTIC Science & Technology

2010-03-01

cannot be deter- mined given the one output. Reversible gates, expressed mathematically, are unitary matrices. 16 3.3.1 PAULI Gates/Matrices Three...common single-qubit gates are expressed mathematically as Pauli matrices, which are 2x2 matrices. A 2x2 quantum gate can be applied to a single quantum...bit (a 2x1 column vector). The Pauli matrices are expressed as follows: X =   0 1 1 0   Y =   0 −i i 0   Z =   1 0 0 −1   (3.10) where i

Radiation Issues and Applications of Floating Gate Memories

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Nguyen, D. N.

2000-01-01

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Moharrami, Elham; Navimipour, Nima Jafari

2018-04-01

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.

AN EVALUATION OF HEURISTICS FOR THRESHOLD-FUNCTION TEST-SYNTHESIS,

DTIC Science & Technology

Linear programming offers the most attractive procedure for testing and obtaining optimal threshold gate realizations for functions generated in...The design of the experiments may be of general interest to students of automatic problem solving; the results should be of interest in threshold logic and linear programming. (Author)

The physics of bacterial decision making.

PubMed

Ben-Jacob, Eshel; Lu, Mingyang; Schultz, Daniel; Onuchic, Jose' N

2014-01-01

The choice that bacteria make between sporulation and competence when subjected to stress provides a prototypical example of collective cell fate determination that is stochastic on the individual cell level, yet predictable (deterministic) on the population level. This collective decision is performed by an elaborated gene network. Considerable effort has been devoted to simplify its complexity by taking physics approaches to untangle the basic functional modules that are integrated to form the complete network: (1) A stochastic switch whose transition probability is controlled by two order parameters-population density and internal/external stress. (2) An adaptable timer whose clock rate is normalized by the same two previous order parameters. (3) Sensing units which measure population density and external stress. (4) A communication module that exchanges information about the cells' internal stress levels. (5) An oscillating gate of the stochastic switch which is regulated by the timer. The unique circuit architecture of the gate allows special dynamics and noise management features. The gate opens a window of opportunity in time for competence transitions, during which the circuit generates oscillations that are translated into a chain of short intervals with high transition probability. In addition, the unique architecture of the gate allows filtering of external noise and robustness against variations in circuit parameters and internal noise. We illustrate that a physics approach can be very valuable in investigating the decision process and in identifying its general principles. We also show that both cell-cell variability and noise have important functional roles in the collectively controlled individual decisions.

The physics of bacterial decision making

PubMed Central

Ben-Jacob, Eshel; Lu, Mingyang; Schultz, Daniel; Onuchic, Jose' N.

2014-01-01

The choice that bacteria make between sporulation and competence when subjected to stress provides a prototypical example of collective cell fate determination that is stochastic on the individual cell level, yet predictable (deterministic) on the population level. This collective decision is performed by an elaborated gene network. Considerable effort has been devoted to simplify its complexity by taking physics approaches to untangle the basic functional modules that are integrated to form the complete network: (1) A stochastic switch whose transition probability is controlled by two order parameters—population density and internal/external stress. (2) An adaptable timer whose clock rate is normalized by the same two previous order parameters. (3) Sensing units which measure population density and external stress. (4) A communication module that exchanges information about the cells' internal stress levels. (5) An oscillating gate of the stochastic switch which is regulated by the timer. The unique circuit architecture of the gate allows special dynamics and noise management features. The gate opens a window of opportunity in time for competence transitions, during which the circuit generates oscillations that are translated into a chain of short intervals with high transition probability. In addition, the unique architecture of the gate allows filtering of external noise and robustness against variations in circuit parameters and internal noise. We illustrate that a physics approach can be very valuable in investigating the decision process and in identifying its general principles. We also show that both cell-cell variability and noise have important functional roles in the collectively controlled individual decisions. PMID:25401094

Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron-beam direct writing technique

NASA Astrophysics Data System (ADS)

Aoyagi, Masahiro; Nakagawa, Hiroshi

1997-07-01

For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Development of Gating Foils To Inhibit Ion Feedback Using FPC Production Techniques

NASA Astrophysics Data System (ADS)

Arai, D.; Ikematsu, K.; Sugiyama, A.; Iwamura, M.; Koto, A.; Katsuki, K.; Fujii, K.; Matsuda, T.

2018-02-01

Positive ion feedback from a gas amplification device to the drift region of the Time Projection Chamber for the ILC can deteriorate the position resolution. In order to inhibit the feedback ions, MPGD-based gating foils having good electron transmission have been developed to be used instead of the conventional wire gate. The gating foil needs to control the electric field locally in opening or closing the gate. The gating foil with a GEM (gas electron multiplier)-like structure has larger holes and smaller thickness than standard GEMs for gas amplification. It is known that the foil transmits over 80 % of electrons and blocks ions almost completely. We have developed the gating foils using flexible printed circuit (FPC) production techniques including an improved single-mask process. In this paper, we report on the production technique of 335 μm pitch, 12.5 μm thick gating foil with 80 % transmittance of electrons in ILC conditions.

Polymorphic Electronic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian

2004-01-01

Polymorphic electronics is a nascent technological discipline that involves, among other things, designing the same circuit to perform different analog and/or digital functions under different conditions. For example, a circuit can be designed to function as an OR gate or an AND gate, depending on the temperature (see figure). Polymorphic electronics can also be considered a subset of polytronics, which is a broader technological discipline in which optical and possibly other information- processing systems could also be designed to perform multiple functions. Polytronics is an outgrowth of evolvable hardware (EHW). The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles. To recapitulate: The essence of EHW is to design, construct, and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The evolution is guided by a search-and-optimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by computational simulation (in which case the evolution is said to be extrinsic), tested in real hardware (in which case the evolution is said to be intrinsic), or tested in random sequences of computational simulation and real hardware (in which case the evolution is said to be mixtrinsic).

125 GHz sine wave gating InGaAs/InP single-photon detector with a monolithically integrated readout circuit

NASA Astrophysics Data System (ADS)

Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei

2017-12-01

InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. Gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing module size are important challenges for the design of such detector system. Here we present for the first time an InGaAs/InP SPD with 1.25 GHz sine wave gating using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15 mm * 15 mm and implements the miniaturization of avalanche extraction for high-frequency sine wave gating. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of MIRC, and the SPD exhibits excellent performance with 27.5 % photon detection efficiency, 1.2 kcps dark count rate, and 9.1 % afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.

Interconnect-free parallel logic circuits in a single mechanical resonator

PubMed Central

Mahboob, I.; Flurin, E.; Nishiguchi, K.; Fujiwara, A.; Yamaguchi, H.

2011-01-01

In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator. PMID:21326230

Interconnect-free parallel logic circuits in a single mechanical resonator.

PubMed

Mahboob, I; Flurin, E; Nishiguchi, K; Fujiwara, A; Yamaguchi, H

2011-02-15

In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Concrete resource analysis of the quantum linear-system algorithm used to compute the electromagnetic scattering cross section of a 2D target

NASA Astrophysics Data System (ADS)

Scherer, Artur; Valiron, Benoît; Mau, Siun-Chuon; Alexander, Scott; van den Berg, Eric; Chapuran, Thomas E.

2017-03-01

We provide a detailed estimate for the logical resource requirements of the quantum linear-system algorithm (Harrow et al. in Phys Rev Lett 103:150502, 2009) including the recently described elaborations and application to computing the electromagnetic scattering cross section of a metallic target (Clader et al. in Phys Rev Lett 110:250504, 2013). Our resource estimates are based on the standard quantum-circuit model of quantum computation; they comprise circuit width (related to parallelism), circuit depth (total number of steps), the number of qubits and ancilla qubits employed, and the overall number of elementary quantum gate operations as well as more specific gate counts for each elementary fault-tolerant gate from the standard set { X, Y, Z, H, S, T, { CNOT } }. In order to perform these estimates, we used an approach that combines manual analysis with automated estimates generated via the Quipper quantum programming language and compiler. Our estimates pertain to the explicit example problem size N=332{,}020{,}680 beyond which, according to a crude big-O complexity comparison, the quantum linear-system algorithm is expected to run faster than the best known classical linear-system solving algorithm. For this problem size, a desired calculation accuracy ɛ =0.01 requires an approximate circuit width 340 and circuit depth of order 10^{25} if oracle costs are excluded, and a circuit width and circuit depth of order 10^8 and 10^{29}, respectively, if the resource requirements of oracles are included, indicating that the commonly ignored oracle resources are considerable. In addition to providing detailed logical resource estimates, it is also the purpose of this paper to demonstrate explicitly (using a fine-grained approach rather than relying on coarse big-O asymptotic approximations) how these impressively large numbers arise with an actual circuit implementation of a quantum algorithm. While our estimates may prove to be conservative as more efficient advanced quantum-computation techniques are developed, they nevertheless provide a valid baseline for research targeting a reduction of the algorithmic-level resource requirements, implying that a reduction by many orders of magnitude is necessary for the algorithm to become practical.

Representation and design of wavelets using unitary circuits

NASA Astrophysics Data System (ADS)

Evenbly, Glen; White, Steven R.

2018-05-01

The representation of discrete, compact wavelet transformations (WTs) as circuits of local unitary gates is discussed. We employ a similar formalism as used in the multiscale representation of quantum many-body wave functions using unitary circuits, further cementing the relation established in the literature between classical and quantum multiscale methods. An algorithm for constructing the circuit representation of known orthogonal, dyadic, discrete WTs is presented, and the explicit representation for Daubechies wavelets, coiflets, and symlets is provided. Furthermore, we demonstrate the usefulness of the circuit formalism in designing WTs, including various classes of symmetric wavelets and multiwavelets, boundary wavelets, and biorthogonal wavelets.

Efficient quantum circuits for one-way quantum computing.

PubMed

Tanamoto, Tetsufumi; Liu, Yu-Xi; Hu, Xuedong; Nori, Franco

2009-03-13

While Ising-type interactions are ideal for implementing controlled phase flip gates in one-way quantum computing, natural interactions between solid-state qubits are most often described by either the XY or the Heisenberg models. We show an efficient way of generating cluster states directly using either the imaginary SWAP (iSWAP) gate for the XY model, or the sqrt[SWAP] gate for the Heisenberg model. Our approach thus makes one-way quantum computing more feasible for solid-state devices.

Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Realization of a quantum Hamiltonian Boolean logic gate on the Si(001):H surface.

PubMed

Kolmer, Marek; Zuzak, Rafal; Dridi, Ghassen; Godlewski, Szymon; Joachim, Christian; Szymonski, Marek

2015-08-07

The design and construction of the first prototypical QHC (Quantum Hamiltonian Computing) atomic scale Boolean logic gate is reported using scanning tunnelling microscope (STM) tip-induced atom manipulation on an Si(001):H surface. The NOR/OR gate truth table was confirmed by dI/dU STS (Scanning Tunnelling Spectroscopy) tracking how the surface states of the QHC quantum circuit on the Si(001):H surface are shifted according to the input logical status.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

A television scanner for the ultracentrifuge. II. Multiple cell operation.

PubMed

Rockholt, D L; Royce, C R; Richards, E G

1976-07-01

The "Optical Multichannel Analyzer" (OMA) is a commercially available instrument that with the absorption optical system of the ultracentrifuge, provides an entire 500 channel intensity profile of a cell in real time. With its own analog-todigital converter, the OMA integrates a selectable number of 32.8 msec scans to provide a time-averaged image in digital form. This paper describes an interface-controller for operation of the OMA with single- and double-sector cells in multi-cell rotors, simulating double-beam measurement required for absorbance determinations. The desired sector is selected by "gating" the intensifier stage of a "Silicon Intensified Target" vidicon (SIT) used as the light detector. The cell location in the rotor and the position of the gate relative to the cell centerline is obtained from a phase-locked loop circuit which divides each rotation of the rotor into 3600 parts independent of rotor speed. (This circuit employed with photo-multiplier scanners would select the gate position for integration of photomultiplier pulses.) From examination of appropriate signals with an oscilloscope, it was verified that gate positions and widths are located with an accuracy of 0.1degree or better and with a precision of +/- 0.1 mus. The light intensity profile for any desired cell can be examined in "real time", even during acceleration of the rotor. Additional circuits employing a 10 MHz crystal clock 1) control the automatic collection of data for all sectors in multicell rotors at digitally selected time intervals, 2) display the rotor speed, and 3) indicate the elapsed time of the experiment. Constructed but not tested are additional circuits for pulsing a laser into the absorption or Rayleigh optical system. The accuracy of the pulsed SIT has been demonstrated by measurement of absorbances of solutions and also by sedimentation equilibrium experiments with myoglobin. The estimated error is 0.003 for absorbances ranging from 0 to 1. The interface-controller operates extremely well, but problems related to the pulsed SIT (optimum gate position relative to the sector opening shape of high-voltage pulse, slight pincushion distortion) require more work.

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Hybrid Toffoli gate on photons and quantum spins

PubMed Central

Luo, Ming-Xing; Ma, Song-Ya; Chen, Xiu-Bo; Wang, Xiaojun

2015-01-01

Quantum computation offers potential advantages in solving a number of interesting and difficult problems. Several controlled logic gates, the elemental building blocks of quantum computer, have been realized with various physical systems. A general technique was recently proposed that significantly reduces the realization complexity of multiple-control logic gates by harnessing multi-level information carriers. We present implementations of a key quantum circuit: the three-qubit Toffoli gate. By exploring the optical selection rules of one-sided optical microcavities, a Toffoli gate may be realized on all combinations of photon and quantum spins in the QD-cavity. The three general controlled-NOT gates are involved using an auxiliary photon with two degrees of freedom. Our results show that photons and quantum spins may be used alternatively in quantum information processing. PMID:26568078

Hybrid Toffoli gate on photons and quantum spins.

PubMed

Luo, Ming-Xing; Ma, Song-Ya; Chen, Xiu-Bo; Wang, Xiaojun

2015-11-16

Quantum computation offers potential advantages in solving a number of interesting and difficult problems. Several controlled logic gates, the elemental building blocks of quantum computer, have been realized with various physical systems. A general technique was recently proposed that significantly reduces the realization complexity of multiple-control logic gates by harnessing multi-level information carriers. We present implementations of a key quantum circuit: the three-qubit Toffoli gate. By exploring the optical selection rules of one-sided optical microcavities, a Toffoli gate may be realized on all combinations of photon and quantum spins in the QD-cavity. The three general controlled-NOT gates are involved using an auxiliary photon with two degrees of freedom. Our results show that photons and quantum spins may be used alternatively in quantum information processing.

Upsets in Erased Floating Gate Cells With High-Energy Protons

DOE PAGES

Gerardin, S.; Bagatin, M.; Paccagnella, A.; ...

2017-01-01

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

Robot gripper

NASA Technical Reports Server (NTRS)

Webb, Winston S. (Inventor)

1987-01-01

An electronic force-detecting robot gripper for gripping objects and attaching to an external robot arm is disclosed. The gripper comprises motor apparatus, gripper jaws, and electrical circuits for driving the gripper motor and sensing the amount of force applied by the jaws. The force applied by the jaws is proportional to a threshold value of the motor current. When the motor current exceeds the threshold value, the electrical circuits supply a feedback signal to the electrical control circuit which, in turn, stops the gripper motor.

Improvement in Brightness Uniformity by Compensating for the Threshold Voltages of Both the Driving Thin-Film Transistor and the Organic Light-Emitting Diode for Active-Matrix Organic Light-Emitting Diode Displays

NASA Astrophysics Data System (ADS)

Ching-Lin Fan,; Hui-Lung Lai,; Jyu-Yu Chang,

2010-05-01

In this paper, we propose a novel pixel design and driving method for active-matrix organic light-emitting diode (AM-OLED) displays using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The proposed threshold voltage compensation circuit, which comprised five transistors and two capacitors, has been verified to supply uniform output current by simulation work using the automatic integrated circuit modeling simulation program with integrated circuit emphasis (AIM-SPICE) simulator. The driving scheme of this voltage programming method includes four periods: precharging, compensation, data input, and emission. The simulated results demonstrate excellent properties such as low error rate of OLED anode voltage variation (<1%) and high output current. The proposed pixel circuit shows high immunity to the threshold voltage deviation characteristics of both the driving poly-Si TFT and the OLED.

Tumor Immunotherapy by Gene-circuit Recruited Immunomodulatory Systems (TIGRIS) for Prostate Cancer

DTIC Science & Technology

2017-09-01

Fu, X., Huang, W., and Cai, Z. (2014). Syn- thesizing AND gate genetic circuits based on CRISPR -Cas9 for identification of bladder cancer cells. Nat...and Lu, T.K. (2014). Multi- plexed and programmable regulation of gene networks with an integrated RNA and CRISPR /Cas toolkit in human cells. Mol

Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

PubMed

Penchovsky, Robert

2012-10-19

Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

High output lamp with high brightness

DOEpatents

Kirkpatrick, Douglas A.; Bass, Gary K.; Copsey, Jesse F.; Garber, Jr., William E.; Kwong, Vincent H.; Levin, Izrail; MacLennan, Donald A.; Roy, Robert J.; Steiner, Paul E.; Tsai, Peter; Turner, Brian P.

2002-01-01

An ultra bright, low wattage inductively coupled electrodeless aperture lamp is powered by a solid state RF source in the range of several tens to several hundreds of watts at various frequencies in the range of 400 to 900 MHz. Numerous novel lamp circuits and components are disclosed including a wedding ring shaped coil having one axial and one radial lead, a high accuracy capacitor stack, a high thermal conductivity aperture cup and various other aperture bulb configurations, a coaxial capacitor arrangement, and an integrated coil and capacitor assembly. Numerous novel RF circuits are also disclosed including a high power oscillator circuit with reduced complexity resonant pole configuration, parallel RF power FET transistors with soft gate switching, a continuously variable frequency tuning circuit, a six port directional coupler, an impedance switching RF source, and an RF source with controlled frequency-load characteristics. Numerous novel RF control methods are disclosed including controlled adjustment of the operating frequency to find a resonant frequency and reduce reflected RF power, controlled switching of an impedance switched lamp system, active power control and active gate bias control.

GATING CIRCUITS

DOEpatents

Merrill, L.C.

1958-10-14

Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

NASA Astrophysics Data System (ADS)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

A Facile Two-Step Method to Implement N√ {iSWAP} and N√ {SWAP} Gates in a Circuit QED

NASA Astrophysics Data System (ADS)

Said, T.; Chouikh, A.; Bennai, M.

2018-05-01

We propose a way for implementing a two-step N√ {iSWAP} and N √ {SWAP} gates based on the qubit-qubit interaction with N superconducting qubits, by coupling them to a resonator driven by a strong microwave field. The operation times do not increase with the growth of the qubit number. Due to the virtual excitations of the resonator, the scheme is insensitive to the decay of the resonator. Numerical analysis shows that the scheme can be implemented with high fidelity. Moreover, we propose a detailed procedure and analyze the experimental feasibility. So, our proposal can be experimentally realized in the range of current circuit QED techniques.

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation

NASA Astrophysics Data System (ADS)

Abdolmohammadi, Hamid Reza; Khalaf, Abdul Jalil M.; Panahi, Shirin; Rajagopal, Karthikeyan; Pham, Viet-Thanh; Jafari, Sajad

2018-06-01

Nowadays, designing chaotic systems with hidden attractor is one of the most interesting topics in nonlinear dynamics and chaos. In this paper, a new 4D chaotic system is proposed. This new chaotic system has no equilibria, and so it belongs to the category of systems with hidden attractors. Dynamical features of this system are investigated with the help of its state-space portraits, bifurcation diagram, Lyapunov exponents diagram, and basin of attraction. Also a hardware realisation of this system is proposed by using field programmable gate arrays (FPGA). In addition, an electronic circuit design for the chaotic system is introduced.

A Fiber Bragg Grating Interrogation System with Self-Adaption Threshold Peak Detection Algorithm.

PubMed

Zhang, Weifang; Li, Yingwu; Jin, Bo; Ren, Feifei; Wang, Hongxun; Dai, Wei

2018-04-08

A Fiber Bragg Grating (FBG) interrogation system with a self-adaption threshold peak detection algorithm is proposed and experimentally demonstrated in this study. This system is composed of a field programmable gate array (FPGA) and advanced RISC machine (ARM) platform, tunable Fabry-Perot (F-P) filter and optical switch. To improve system resolution, the F-P filter was employed. As this filter is non-linear, this causes the shifting of central wavelengths with the deviation compensated by the parts of the circuit. Time-division multiplexing (TDM) of FBG sensors is achieved by an optical switch, with the system able to realize the combination of 256 FBG sensors. The wavelength scanning speed of 800 Hz can be achieved by a FPGA+ARM platform. In addition, a peak detection algorithm based on a self-adaption threshold is designed and the peak recognition rate is 100%. Experiments with different temperatures were conducted to demonstrate the effectiveness of the system. Four FBG sensors were examined in the thermal chamber without stress. When the temperature changed from 0 °C to 100 °C, the degree of linearity between central wavelengths and temperature was about 0.999 with the temperature sensitivity being 10 pm/°C. The static interrogation precision was able to reach 0.5 pm. Through the comparison of different peak detection algorithms and interrogation approaches, the system was verified to have an optimum comprehensive performance in terms of precision, capacity and speed.

A Fiber Bragg Grating Interrogation System with Self-Adaption Threshold Peak Detection Algorithm

PubMed Central

Zhang, Weifang; Li, Yingwu; Jin, Bo; Ren, Feifei

2018-01-01

A Fiber Bragg Grating (FBG) interrogation system with a self-adaption threshold peak detection algorithm is proposed and experimentally demonstrated in this study. This system is composed of a field programmable gate array (FPGA) and advanced RISC machine (ARM) platform, tunable Fabry–Perot (F–P) filter and optical switch. To improve system resolution, the F–P filter was employed. As this filter is non-linear, this causes the shifting of central wavelengths with the deviation compensated by the parts of the circuit. Time-division multiplexing (TDM) of FBG sensors is achieved by an optical switch, with the system able to realize the combination of 256 FBG sensors. The wavelength scanning speed of 800 Hz can be achieved by a FPGA+ARM platform. In addition, a peak detection algorithm based on a self-adaption threshold is designed and the peak recognition rate is 100%. Experiments with different temperatures were conducted to demonstrate the effectiveness of the system. Four FBG sensors were examined in the thermal chamber without stress. When the temperature changed from 0 °C to 100 °C, the degree of linearity between central wavelengths and temperature was about 0.999 with the temperature sensitivity being 10 pm/°C. The static interrogation precision was able to reach 0.5 pm. Through the comparison of different peak detection algorithms and interrogation approaches, the system was verified to have an optimum comprehensive performance in terms of precision, capacity and speed. PMID:29642507

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Ui, Toshimasa; Nguyen, Tuan Quy

Using aluminum titanium oxide (AlTiO, an alloy of Al{sub 2}O{sub 3} and TiO{sub 2}) as a high-k gate insulator, we fabricated and investigated AlTiO/AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors. From current low-frequency noise (LFN) characterization, we find Lorentzian spectra near the threshold voltage, in addition to 1/f spectra for the well-above-threshold regime. The Lorentzian spectra are attributed to electron trapping/detrapping with two specific time constants, ∼25 ms and ∼3 ms, which are independent of the gate length and the gate voltage, corresponding to two trap level depths of 0.5–0.7 eV with a 0.06 eV difference in the AlTiO insulator. In addition, gate leakage currents aremore » analyzed and attributed to the Poole-Frenkel mechanism due to traps in the AlTiO insulator, where the extracted trap level depth is consistent with the Lorentzian LFN.« less

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.