Influence of Time-Pickoff Circuit Parameters on LiDAR Range Precision

PubMed Central

Wang, Hongming; Yang, Bingwei; Huyan, Jiayue; Xu, Lijun

2017-01-01

A pulsed time-of-flight (TOF) measurement-based Light Detection and Ranging (LiDAR) system is more effective for medium-long range distances. As a key ranging unit, a time-pickoff circuit based on automatic gain control (AGC) and constant fraction discriminator (CFD) is designed to reduce the walk error and the timing jitter for obtaining the accurate time interval. Compared with Cramer–Rao lower bound (CRLB) and the estimation of the timing jitter, four parameters-based Monte Carlo simulations are established to show how the range precision is influenced by the parameters, including pulse amplitude, pulse width, attenuation fraction and delay time of the CFD. Experiments were carried out to verify the relationship between the range precision and three of the parameters, exclusing pulse width. It can be concluded that two parameters of the ranging circuit (attenuation fraction and delay time) were selected according to the ranging performance of the minimum pulse amplitude. The attenuation fraction should be selected in the range from 0.2 to 0.6 to achieve high range precision. The selection criterion of the time-pickoff circuit parameters is helpful for the ranging circuit design of TOF LiDAR system. PMID:29039772

Bidirectional automatic release of reserve for low voltage network made with low capacity PLCs

NASA Astrophysics Data System (ADS)

Popa, I.; Popa, G. N.; Diniş, C. M.; Deaconu, S. I.

2018-01-01

The article presents the design of a bidirectional automatic release of reserve made on two types low capacity programmable logic controllers: PS-3 from Klöckner-Moeller and Zelio from Schneider. It analyses the electronic timing circuits that can be used for making the bidirectional automatic release of reserve: time-on delay circuit and time-off delay circuit (two types). In the paper are present the sequences code for timing performed on the PS-3 PLC, the logical functions for the bidirectional automatic release of reserve, the classical control electrical diagram (with contacts, relays, and time relays), the electronic control diagram (with logical gates and timing circuits), the code (in IL language) made for the PS-3 PLC, and the code (in FBD language) made for Zelio PLC. A comparative analysis will be carried out on the use of the two types of PLC and will be present the advantages of using PLCs.

Estimating the circuit delay of FPGA with a transfer learning method

NASA Astrophysics Data System (ADS)

Cui, Xiuhai; Liu, Datong; Peng, Yu; Peng, Xiyuan

2017-10-01

With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

Reconstructions of parameters of radiophysical chaotic generator with delayed feedback from short time series

NASA Astrophysics Data System (ADS)

Ishbulatov, Yu. M.; Karavaev, A. S.; Kiselev, A. R.; Semyachkina-Glushkovskaya, O. V.; Postnov, D. E.; Bezruchko, B. P.

2018-04-01

A method for the reconstruction of time-delayed feedback system is investigated, which is based on the detection of synchronous response of a slave time-delay system with respect to the driving from the master system under study. The structure of the driven system is similar to the structure of the studied time-delay system, but the feedback circuit is broken in the driven system. The method efficiency is tested using short and noisy data gained from an electronic chaotic oscillator with time-delayed feedback.

Impact of time delays on oscillatory dynamics of interlinked positive and negative feedback loops

NASA Astrophysics Data System (ADS)

Huang, Bo; Tian, Xinyu; Liu, Feng; Wang, Wei

2016-11-01

Interlinking a positive feedback loop (PFL) with a negative feedback loop (NFL) constitutes a typical motif in genetic networks, performing various functions in cell signaling. How time delay in feedback regulation affects the dynamics of such systems still remains unclear. Here, we investigate three systems of interlinked PFL and NFL with time delays: a synthetic genetic oscillator, a three-node circuit, and a simplified single-node model. The stability of steady states and the routes to oscillation in the single-node model are analyzed in detail. The amplitude and period of oscillations vary with a pointwise periodicity over a range of time delay. Larger-amplitude oscillations can be induced when the PFL has an appropriately long delay, in comparison with the PFL with no delay or short delay; this conclusion holds true for all the three systems. We unravel the underlying mechanism for the above effects via analytical derivation under a limiting condition. We also develop a stochastic algorithm for simulating a single reaction with two delays and show that robust oscillations can be maintained by the PFL with a properly long delay in the single-node system. This work presents an effective method for constructing robust large-amplitude oscillators and interprets why similar circuit architectures are engaged in timekeeping systems such as circadian clocks.

Precise delay measurement through combinatorial logic

NASA Technical Reports Server (NTRS)

Burke, Gary R. (Inventor); Chen, Yuan (Inventor); Sheldon, Douglas J. (Inventor)

2010-01-01

A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II.

PubMed

Keivanian, Farshid; Mehrshad, Nasser; Bijari, Abolfazl

2016-01-01

D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

VERNIER CHRONOTRON UTILIZING AT LEAST TWO SHORTED DELAY LINES

DOEpatents

Rufer, R.P.

1964-02-25

An improved vernier chronotron featuring pulse-forming circuits of a ringing'' or back and forth'' oscillatory type is described. A delay line shorted at both ends together with transistor circuitry to introduce a pulse into that line and also to provide reinforcement of the pulse as it oscillates between the pulse-reflective extremities is provided. A transistorized coincidence circuit is also provided. Enhanced measurement of time intervals in the nanosecond range is afforded. (AEC)

Transient-Switch-Signal Suppressor

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1995-01-01

Circuit delays transmission of switch-opening or switch-closing signal until after preset suppression time. Used to prevent transmission of undesired momentary switch signal. Basic mode of operation simple. Beginning of switch signal initiates timing sequence. If switch signal persists after preset suppression time, circuit transmits switch signal to external circuitry. If switch signal no longer present after suppression time, switch signal deemed transient, and circuit does not pass signal on to external circuitry, as though no transient switch signal. Suppression time preset at value large enough to allow for damping of underlying pressure wave or other mechanical transient.

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

PubMed

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Note: electronic circuit for two-way time transfer via a single coaxial cable with picosecond accuracy and precision.

PubMed

Prochazka, Ivan; Kodet, Jan; Panek, Petr

2012-11-01

We have designed, constructed, and tested the overall performance of the electronic circuit for the two-way time transfer between two timing devices over modest distances with sub-picosecond precision and a systematic error of a few picoseconds. The concept of the electronic circuit enables to carry out time tagging of pulses of interest in parallel to the comparison of the time scales of these timing devices. The key timing parameters of the circuit are: temperature change of the delay is below 100 fs/K, timing stability time deviation better than 8 fs for averaging time from minutes to hours, sub-picosecond time transfer precision, and a few picoseconds time transfer accuracy.

Note: Large active area solid state photon counter with 20 ps timing resolution and 60 fs detection delay stability

NASA Astrophysics Data System (ADS)

Prochazka, Ivan; Kodet, Jan; Eckl, Johann; Blazej, Josef

2017-10-01

We are reporting on the design, construction, and performance of a photon counting detector system, which is based on single photon avalanche diode detector technology. This photon counting device has been optimized for very high timing resolution and stability of its detection delay. The foreseen application of this detector is laser ranging of space objects, laser time transfer ground to space and fundamental metrology. The single photon avalanche diode structure, manufactured on silicon using K14 technology, is used as a sensor. The active area of the sensor is circular with 200 μm diameter. Its photon detection probability exceeds 40% in the wavelength range spanning from 500 to 800 nm. The sensor is operated in active quenching and gating mode. A new control circuit was optimized to maintain high timing resolution and detection delay stability. In connection to this circuit, timing resolution of the detector is reaching 20 ps FWHM. In addition, the temperature change of the detection delay is as low as 70 fs/K. As a result, the detection delay stability of the device is exceptional: expressed in the form of time deviation, detection delay stability of better than 60 fs has been achieved. Considering the large active area aperture of the detector, this is, to our knowledge, the best timing performance reported for a solid state photon counting detector so far.

Time-of-flight radio location system

DOEpatents

McEwan, T.E.

1997-08-26

A bi-static radar configuration measures the direct time-of-flight of a transmitted RF pulse and is capable of measuring this time-of-flight with a jitter on the order of about one pico-second, or about 0.01 inch of free space distance for an electromagnetic pulse over a range of about one to ten feet. A transmitter transmits a sequence of electromagnetic pulses in response to a transmit timing signal, and a receiver samples the sequence of electromagnetic pulses with controlled timing in response to a receive timing signal, and generates a sample signal in response to the samples. A timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The receive timing signal causes the receiver to sample the sequence of electromagnetic pulses such that the time between transmission of pulses in the sequence and sampling by the receiver sweeps over a range of delays. The receive timing signal sweeps over the range of delays in a sweep cycle such that pulses in the sequence are sampled at the pulse repetition rate, and with different delays in the range of delays to produce a sample signal representing magnitude of a received pulse in equivalent time. Automatic gain control circuitry in the receiver controls the magnitude of the equivalent time sample signal. A signal processor analyzes the sample signal to indicate the time-of-flight of the electromagnetic pulses in the sequence. The sample signal in equivalent time is passed through an envelope detection circuit, formed of an absolute value circuit followed by a low pass filter, to convert the sample signal to a unipolar signal to eliminate effects of antenna misorientation. 8 figs.

Time-of-flight radio location system

DOEpatents

McEwan, Thomas E.

1997-01-01

A bi-static radar configuration measures the direct time-of-flight of a transmitted RF pulse and is capable of measuring this time-of-flight with a jitter on the order of about one pico-second, or about 0.01 inch of free space distance for an electromagnetic pulse over a range of about one to ten feet. A transmitter transmits a sequence of electromagnetic pulses in response to a transmit timing signal, and a receiver samples the sequence of electromagnetic pulses with controlled timing in response to a receive timing signal, and generates a sample signal in response to the samples. A timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The receive timing signal causes the receiver to sample the sequence of electromagnetic pulses such that the time between transmission of pulses in the sequence and sampling by the receiver sweeps over a range of delays. The receive timing signal sweeps over the range of delays in a sweep cycle such that pulses in the sequence are sampled at the pulse repetition rate, and with different delays in the range of delays to produce a sample signal representing magnitude of a received pulse in equivalent time. Automatic gain control circuitry in the receiver controls the magnitude of the equivalent time sample signal. A signal processor analyzes the sample signal to indicate the time-of-flight of the electromagnetic pulses in the sequence. The sample signal in equivalent time is passed through an envelope detection circuit, formed of an absolute value circuit followed by a low pass filter, to convert the sample signal to a unipolar signal to eliminate effects of antenna misorientation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chertkov, Michael; Turitsyn, Konstantin; Sulc, Petr

The anticipated increase in the number of plug-in electric vehicles (EV) will put additional strain on electrical distribution circuits. Many control schemes have been proposed to control EV charging. Here, we develop control algorithms based on randomized EV charging start times and simple one-way broadcast communication allowing for a time delay between communication events. Using arguments from queuing theory and statistical analysis, we seek to maximize the utilization of excess distribution circuit capacity while keeping the probability of a circuit overload negligible.

Circuit for echo and noise suppression of accoustic signals transmitted through a drill string

DOEpatents

Drumheller, Douglas S.; Scott, Douglas D.

1993-01-01

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output.

Switching Characteristics of Ferroelectric Transistor Inverters

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

2010-01-01

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

Compensation for Lithography Induced Process Variations during Physical Design

NASA Astrophysics Data System (ADS)

Chin, Eric Yiow-Bing

This dissertation addresses the challenge of designing robust integrated circuits in the deep sub micron regime in the presence of lithography process variability. By extending and combining existing process and circuit analysis techniques, flexible software frameworks are developed to provide detailed studies of circuit performance in the presence of lithography variations such as focus and exposure. Applications of these software frameworks to select circuits demonstrate the electrical impact of these variations and provide insight into variability aware compact models that capture the process dependent circuit behavior. These variability aware timing models abstract lithography variability from the process level to the circuit level and are used to estimate path level circuit performance with high accuracy with very little overhead in runtime. The Interconnect Variability Characterization (IVC) framework maps lithography induced geometrical variations at the interconnect level to electrical delay variations. This framework is applied to one dimensional repeater circuits patterned with both 90nm single patterning and 32nm double patterning technologies, under the presence of focus, exposure, and overlay variability. Studies indicate that single and double patterning layouts generally exhibit small variations in delay (between 1--3%) due to self compensating RC effects associated with dense layouts and overlay errors for layouts without self-compensating RC effects. The delay response of each double patterned interconnect structure is fit with a second order polynomial model with focus, exposure, and misalignment parameters with 12 coefficients and residuals of less than 0.1ps. The IVC framework is also applied to a repeater circuit with cascaded interconnect structures to emulate more complex layout scenarios, and it is observed that the variations on each segment average out to reduce the overall delay variation. The Standard Cell Variability Characterization (SCVC) framework advances existing layout-level lithography aware circuit analysis by extending it to cell-level applications utilizing a physically accurate approach that integrates process simulation, compact transistor models, and circuit simulation to characterize electrical cell behavior. This framework is applied to combinational and sequential cells in the Nangate 45nm Open Cell Library, and the timing response of these cells to lithography focus and exposure variations demonstrate Bossung like behavior. This behavior permits the process parameter dependent response to be captured in a nine term variability aware compact model based on Bossung fitting equations. For a two input NAND gate, the variability aware compact model captures the simulated response to an accuracy of 0.3%. The SCVC framework is also applied to investigate advanced process effects including misalignment and layout proximity. The abstraction of process variability from the layout level to the cell level opens up an entire new realm of circuit analysis and optimization and provides a foundation for path level variability analysis without the computationally expensive costs associated with joint process and circuit simulation. The SCVC framework is used with slight modification to illustrate the speedup and accuracy tradeoffs of using compact models. With variability aware compact models, the process dependent performance of a three stage logic circuit can be estimated to an accuracy of 0.7% with a speedup of over 50,000. Path level variability analysis also provides an accurate estimate (within 1%) of ring oscillator period in well under a second. Another significant advantage of variability aware compact models is that they can be easily incorporated into existing design methodologies for design optimization. This is demonstrated by applying cell swapping on a logic circuit to reduce the overall delay variability along a circuit path. By including these variability aware compact models in cell characterization libraries, design metrics such as circuit timing, power, area, and delay variability can be quickly assessed to optimize for the correct balance of all design metrics, including delay variability. Deterministic lithography variations can be easily captured using the variability aware compact models described in this dissertation. However, another prominent source of variability is random dopant fluctuations, which affect transistor threshold voltage and in turn circuit performance. The SCVC framework is utilized to investigate the interactions between deterministic lithography variations and random dopant fluctuations. Monte Carlo studies show that the output delay distribution in the presence of random dopant fluctuations is dependent on lithography focus and exposure conditions, with a 3.6 ps change in standard deviation across the focus exposure process window. This indicates that the electrical impact of random variations is dependent on systematic lithography variations, and this dependency should be included for precise analysis.

Circuit for echo and noise suppression of acoustic signals transmitted through a drill string

DOEpatents

Drumheller, D.S.; Scott, D.D.

1993-12-28

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output. 20 figures.

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

NASA Astrophysics Data System (ADS)

Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

2006-03-01

The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

Periodic, Quasi-periodic and Chaotic Dynamics in Simple Gene Elements with Time Delays

PubMed Central

Suzuki, Yoko; Lu, Mingyang; Ben-Jacob, Eshel; Onuchic, José N.

2016-01-01

Regulatory gene circuit motifs play crucial roles in performing and maintaining vital cellular functions. Frequently, theoretical studies of gene circuits focus on steady-state behaviors and do not include time delays. In this study, the inclusion of time delays is shown to entirely change the time-dependent dynamics for even the simplest possible circuits with one and two gene elements with self and cross regulations. These elements can give rise to rich behaviors including periodic, quasi-periodic, weak chaotic, strong chaotic and intermittent dynamics. We introduce a special power-spectrum-based method to characterize and discriminate these dynamical modes quantitatively. Our simulation results suggest that, while a single negative feedback loop of either one- or two-gene element can only have periodic dynamics, the elements with two positive/negative feedback loops are the minimalist elements to have chaotic dynamics. These elements typically have one negative feedback loop that generates oscillations, and another unit that allows frequent switches among multiple steady states or between oscillatory and non-oscillatory dynamics. Possible dynamical features of several simple one- and two-gene elements are presented in details. Discussion is presented for possible roles of the chaotic behavior in the robustness of cellular functions and diseases, for example, in the context of cancer. PMID:26876008

Periodic, Quasi-periodic and Chaotic Dynamics in Simple Gene Elements with Time Delays

NASA Astrophysics Data System (ADS)

Suzuki, Yoko; Lu, Mingyang; Ben-Jacob, Eshel; Onuchic, José N.

2016-02-01

Regulatory gene circuit motifs play crucial roles in performing and maintaining vital cellular functions. Frequently, theoretical studies of gene circuits focus on steady-state behaviors and do not include time delays. In this study, the inclusion of time delays is shown to entirely change the time-dependent dynamics for even the simplest possible circuits with one and two gene elements with self and cross regulations. These elements can give rise to rich behaviors including periodic, quasi-periodic, weak chaotic, strong chaotic and intermittent dynamics. We introduce a special power-spectrum-based method to characterize and discriminate these dynamical modes quantitatively. Our simulation results suggest that, while a single negative feedback loop of either one- or two-gene element can only have periodic dynamics, the elements with two positive/negative feedback loops are the minimalist elements to have chaotic dynamics. These elements typically have one negative feedback loop that generates oscillations, and another unit that allows frequent switches among multiple steady states or between oscillatory and non-oscillatory dynamics. Possible dynamical features of several simple one- and two-gene elements are presented in details. Discussion is presented for possible roles of the chaotic behavior in the robustness of cellular functions and diseases, for example, in the context of cancer.

ELECTRONIC PHASE CONTROL CIRCUIT

DOEpatents

Salisbury, J.D.; Klein, W.W.; Hansen, C.F.

1959-04-21

An electronic circuit is described for controlling the phase of radio frequency energy applied to a multicavity linear accelerator. In one application of the circuit two cavities are excited from a single radio frequency source, with one cavity directly coupled to the source and the other cavity coupled through a delay line of special construction. A phase detector provides a bipolar d-c output signal proportional to the difference in phase between the voltage in the two cavities. This d-c signal controls a bias supply which provides a d-c output for varying the capacitnce of voltage sensitive capacitors in the delay line. The over-all operation of the circuit is completely electronic, overcoming the time response limitations of the electromechanical control systems, and the relative phase relationship of the radio frequency voltages in the two caviiies is continuously controlled to effect particle acceleration.

ONE SHAKE GATE FORMER

DOEpatents

Kalibjian, R.; Perez-Mendez, V.

1957-08-20

An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

Auxiliary quasi-resonant dc tank electrical power converter

DOEpatents

Peng, Fang Z.

2006-10-24

An auxiliary quasi-resonant dc tank (AQRDCT) power converter with fast current charging, voltage balancing (or charging), and voltage clamping circuits is provided for achieving soft-switched power conversion. The present invention is an improvement of the invention taught in U.S. Pat. No. 6,111,770, herein incorporated by reference. The present invention provides faster current charging to the resonant inductor, thus minimizing delay time of the pulse width modulation (PWM) due to the soft-switching process. The new AQRDCT converter includes three tank capacitors or power supplies to achieve the faster current charging and minimize the soft-switching time delay. The new AQRDCT converter further includes a voltage balancing circuit to charge and discharge the three tank capacitors so that additional isolated power supplies from the utility line are not needed. A voltage clamping circuit is also included for clamping voltage surge due to the reverse recovery of diodes.

CHEETAH: circuit-switched high-speed end-to-end transport architecture

NASA Astrophysics Data System (ADS)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

Photonic integrated circuits unveil crisis-induced intermittency.

PubMed

Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

2016-09-19

We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

High-Speed, High-Resolution Time-to-Digital Conversion

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor; Garcia, Rafael

2013-01-01

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

System and method for assaying a radionuclide

DOEpatents

Cadieux, James R; King, III, George S; Fugate, Glenn A

2014-12-23

A system for assaying a radionuclide includes a liquid scintillation detector, an analyzer connected to the liquid scintillation detector, and a delay circuit connected to the analyzer. A gamma detector and a multi-channel analyzer are connected to the delay circuit and the gamma detector. The multi-channel analyzer produces a signal reflective of the radionuclide in the sample. A method for assaying a radionuclide includes selecting a sample, detecting alpha or beta emissions from the sample with a liquid scintillation detector, producing a first signal reflective of the alpha or beta emissions, and delaying the first signal a predetermined time. The method further includes detecting gamma emissions from the sample, producing a second signal reflective of the gamma emissions, and combining the delayed first signal with the second signal to produce a third signal reflective of the radionuclide.

An Electromagnetically Actuated Vacuum Circuit Breaker Developed by Electromagnetic Analysis Coupled with Motion

NASA Astrophysics Data System (ADS)

Takeuchi, Toshie; Nakagawa, Takafumi; Tsukima, Mitsuru; Koyama, Kenichi; Tohya, Nobumoto; Yano, Tomotaka

A new electromagnetically actuated vacuum circuit breaker (VCB) has been designed and developed on the basis of the transient electromagnetic analysis coupled with motion. The VCB has three advanced bi-stable electromagnetic actuators, which control each phase independently. The VCB serves as a synchronous circuit breaker as well as a standard circuit breaker. In this work, the flux delay due to the eddy current is analytically formulated using the delay time constant of the actuator coil current, thereby leading to accurate driving behavior. With this analytical method, the electromagnetic mechanism for a 24kV rated VCB has been optimized; and as a result, the driving energy is reduced to one fifth of that of a conventional VCB employing spring mechanism, and the number of parts is significantly decreased. Therefore, the developed VCB becomes compact, highly reliable and highly durable.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

High resolution time interval meter

DOEpatents

Martin, A.D.

1986-05-09

Method and apparatus are provided for measuring the time interval between two events to a higher resolution than reliability available from conventional circuits and component. An internal clock pulse is provided at a frequency compatible with conventional component operating frequencies for reliable operation. Lumped constant delay circuits are provided for generating outputs at delay intervals corresponding to the desired high resolution. An initiation START pulse is input to generate first high resolution data. A termination STOP pulse is input to generate second high resolution data. Internal counters count at the low frequency internal clock pulse rate between the START and STOP pulses. The first and second high resolution data are logically combined to directly provide high resolution data to one counter and correct the count in the low resolution counter to obtain a high resolution time interval measurement.

Assessment of Systematic Measurement Errors for Acoustic Travel-Time Tomography of the Atmosphere

DTIC Science & Technology

2013-01-01

measurements include assess- ment of the time delays in electronic circuits and mechanical hardware (e.g., drivers and microphones) of a tomography array ...hardware and electronic circuits of the tomography array and errors in synchronization of the transmitted and recorded signals. For example, if...coordinates can be as large as 30 cm. These errors are equivalent to the systematic errors in the travel times of 0.9 ms. Third, loudspeakers which are used

Delay grid multiplexing: simple time-based multiplexing and readout method for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Won, Jun Yeon; Ko, Guen Bae; Lee, Jae Sung

2016-10-01

In this paper, we propose a fully time-based multiplexing and readout method that uses the principle of the global positioning system. Time-based multiplexing allows simplifying the multiplexing circuits where the only innate traces that connect the signal pins of the silicon photomultiplier (SiPM) channels to the readout channels are used as the multiplexing circuit. Every SiPM channel is connected to the delay grid that consists of the traces on a printed circuit board, and the inherent transit times from each SiPM channel to the readout channels encode the position information uniquely. Thus, the position of each SiPM can be identified using the time difference of arrival (TDOA) measurements. The proposed multiplexing can also allow simplification of the readout circuit using the time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA), where the time-over-threshold (ToT) is used to extract the energy information after multiplexing. In order to verify the proposed multiplexing method, we built a positron emission tomography (PET) detector that consisted of an array of 4  ×  4 LGSO crystals, each with a dimension of 3  ×  3  ×  20 mm3, and one- to-one coupled SiPM channels. We first employed the waveform sampler as an initial study, and then replaced the waveform sampler with an FPGA-TDC to further simplify the readout circuits. The 16 crystals were clearly resolved using only the time information obtained from the four readout channels. The coincidence resolving times (CRTs) were 382 and 406 ps FWHM when using the waveform sampler and the FPGA-TDC, respectively. The proposed simple multiplexing and readout methods can be useful for time-of-flight (TOF) PET scanners.

Method and apparatus for detecting timing errors in a system oscillator

DOEpatents

Gliebe, Ronald J.; Kramer, William R.

1993-01-01

A method of detecting timing errors in a system oscillator for an electronic device, such as a power supply, includes the step of comparing a system oscillator signal with a delayed generated signal and generating a signal representative of the timing error when the system oscillator signal is not identical to the delayed signal. An LED indicates to an operator that a timing error has occurred. A hardware circuit implements the above-identified method.

Chaotic oscillations and noise transformations in a simple dissipative system with delayed feedback

NASA Astrophysics Data System (ADS)

Zverev, V. V.; Rubinstein, B. Ya.

1991-04-01

We analyze the statistical behavior of signals in nonlinear circuits with delayed feedback in the presence of external Markovian noise. For the special class of circuits with intense phase mixing we develop an approach for the computation of the probability distributions and multitime correlation functions based on the random phase approximation. Both Gaussian and Kubo-Andersen models of external noise statistics are analyzed and the existence of the stationary (asymptotic) random process in the long-time limit is shown. We demonstrate that a nonlinear system with chaotic behavior becomes a noise amplifier with specific statistical transformation properties.

Clocking and Synchronization Circuits in Multiprocessor Systems

DTIC Science & Technology

1989-04-01

18 3.4 Inter -chip Clocking Strategies...may occur when two or more of the switches make transitions at different times during the inter - val during which those inputs are being processed...increased without any fruitful computation. The sources of the inter -chip clock skew are the electromagnetic propagation delay, the buffer delay within

Experimental relevance of global properties of time-delayed feedback control.

PubMed

von Loewenich, Clemens; Benner, Hartmut; Just, Wolfram

2004-10-22

We show by means of theoretical considerations and electronic circuit experiments that time-delayed feedback control suffers from severe global constraints if transitions at the control boundaries are discontinuous. Subcritical behavior gives rise to small basins of attraction and thus limits the control performance. The reported properties are, on the one hand, universal since the mechanism is based on general arguments borrowed from bifurcation theory and, on the other hand, directly visible in experimental time series.

TECHNICAL DESIGN NOTE: Picosecond resolution programmable delay line

NASA Astrophysics Data System (ADS)

Suchenek, Mariusz

2009-11-01

The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market.

Variable Delay Element For Jitter Control In High Speed Data Links

DOEpatents

Livolsi, Robert R.

2002-06-11

A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

A high resolution on-chip delay sensor with low supply-voltage sensitivity for high-performance electronic systems.

PubMed

Sheng, Duo; Lai, Hsiu-Fan; Chan, Sheng-Min; Hong, Min-Rong

2015-02-13

An all-digital on-chip delay sensor (OCDS) circuit with high delay-measurement resolution and low supply-voltage sensitivity for efficient detection and diagnosis in high-performance electronic system applications is presented. Based on the proposed delay measurement scheme, the quantization resolution of the proposed OCDS can be reduced to several picoseconds. Additionally, the proposed cascade-stage delay measurement circuit can enhance immunity to supply-voltage variations of the delay measurement resolution without extra self-biasing or calibration circuits. Simulation results show that the delay measurement resolution can be improved to 1.2 ps; the average delay resolution variation is 0.55% with supply-voltage variations of ±10%. Moreover, the proposed delay sensor can be implemented in an all-digital manner, making it very suitable for high-performance electronic system applications as well as system-level integration.

Recirculating cross-correlation detector

DOEpatents

Andrews, W.H. Jr.; Roberts, M.J.

1985-01-18

A digital cross-correlation detector is provided in which two time-varying signals are correlated by repetitively comparing data samples stored in digital form to detect correlation between the two signals. The signals are sampled at a selected rate converted to digital form, and stored in separate locations in separate memories. When the memories are filled, the data samples from each memory are first fed word-by-word through a multiplier and summing circuit and each result is compared to the last in a peak memory circuit and if larger than the last is retained in the peak memory. Then the address line to leading signal memory is offset by one byte to affect one sample period delay of a known amount in that memory and the data in the two memories are then multiplied word-by-word once again and summed. If a new result is larger than a former sum, it is saved in the peak memory together with the time delay. The recirculating process continues with the address of the one memory being offset one additional byte each cycle until the address is shifted through the length of the memory. The correlation between the two signals is indicated by the peak signal stored in the peak memory together with the delay time at which the peak occurred. The circuit is faster and considerably less expensive than comparable accuracy correlation detectors.

SHORT PULSE STRETCHER

DOEpatents

Branum, D.R.; Cummins, W.F.

1962-12-01

>A short pulse stretching circuit capable of stretching a short puise to enable it to be displayed on a relatively slow sweeping oscilloscope is described. Moreover, the duration of the pulse is increased by charging a capacitor through a diode and thereafter discharging the capacitor at such time as is desired. In the circuit the trigger pulse alone passes through a delay line, whereas the main signal passes through the diode only, and results in over-all circuit losses which are proportional to the low losses of the diode only. (AEC)

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

PRECISION TIME-DELAY GENERATOR

DOEpatents

Carr, B.J.; Peckham, V.D.

1959-06-16

A precision time-delay generator circuit with low jitter is described. The first thyratron has a series resonant circuit and a diode which is connected to the second thyratron. The first thyratron is triggered at the begin-ning of a time delay and a capacitor is discharged through the first thyratron and the diode, thereby, triggering the second thyratron. (T.R.H.) l6l9O The instrument described can measure pressures between sea level and 300,000 ft. The pressure- sensing transducer of the instrument is a small cylindrical tube with a thin foil of titanium-tritium fastened around the inside of the tube. Output is a digital signal which can be used for storage or telemetering more conveniently than an analog signal. (W.D.M.) l6l9l An experimental study was made on rolling contacts in the temperature range of 550 to 1000 deg F. Variables such as material composition, hardness, and operating conditions were investigated in a rolling test stand. Ball bearing tests were run to determine the effect of design parameters, bearing materials, lubricants, and operating conditions. (auth)

A chaotic jerk system with non-hyperbolic equilibrium: Dynamics, effect of time delay and circuit realisation

NASA Astrophysics Data System (ADS)

Rajagopal, Karthikeyan; Pham, Viet-Thanh; Tahir, Fadhil Rahma; Akgul, Akif; Abdolmohammadi, Hamid Reza; Jafari, Sajad

2018-04-01

The literature on chaos has highlighted several chaotic systems with special features. In this work, a novel chaotic jerk system with non-hyperbolic equilibrium is proposed. The dynamics of this new system is revealed through equilibrium analysis, phase portrait, bifurcation diagram and Lyapunov exponents. In addition, we investigate the time-delay effects on the proposed system. Realisation of such a system is presented to verify its feasibility.

Pulse transmission transmitter including a higher order time derivate filter

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-09-23

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission transmitter includes: a clock; a pseudorandom polynomial generator coupled to the clock, the pseudorandom polynomial generator having a polynomial load input; an exclusive-OR gate coupled to the pseudorandom polynomial generator, the exclusive-OR gate having a serial data input; a programmable delay circuit coupled to both the clock and the exclusive-OR gate; a pulse generator coupled to the programmable delay circuit; and a higher order time derivative filter coupled to the pulse generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Improved synchronization criteria for time-delayed chaotic Lur'e systems using sampled-data control

NASA Astrophysics Data System (ADS)

Duan, Wenyong; Li, Yan; Fu, Xiaorong; Du, Baozhu

2017-02-01

This paper is concerned with the synchronization for a class of time-delayed chaotic Lur’e systems using sampled-data control. Both of time-varying and time-invariant delays are considered. New criteria are proposed in terms of linear matrix inequalities (LMIs) by employing a modified LKF combined with the delay-fraction theory and some novel terms. The criteria are less conservative than some previous ones and a longer sampling period is achieved under the new results. Furthermore, the derived conditions are employed to design a sampled-data controller. The desired controller gain matrix can be obtained by means of the LMI approach. Finally, a numerical examples and simulations on Chua’s circuit is presented to show the effectiveness of the proposed approach.

Northwest Laboratory for Integrated Systems, University of Washington, Semiannual Technical Report Number 1, July 1-November 8, 1991

DTIC Science & Technology

1991-11-08

only simple bounds on delays but also relate the delays in linear inequalities so that tradeoffs are apparent. We model circuits as communicating...set of linear inequalities constraining the variables. These relations provide synthesis tools with information about tradeoffs between circuit delays...available to express the original circuit as a graph of elementary gates and then cover the graph’s fanout-free trees with collections of three-input

Phase-synchroniser based on gm-C all-pass filter chain with sliding mode control

NASA Astrophysics Data System (ADS)

Mitić, Darko B.; Jovanović, Goran S.; Stojčev, Mile K.; Antić, Dragan S.

2015-03-01

Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on.

Analysis of adaptive algorithms for an integrated communication network

NASA Technical Reports Server (NTRS)

Reed, Daniel A.; Barr, Matthew; Chong-Kwon, Kim

1985-01-01

Techniques were examined that trade communication bandwidth for decreased transmission delays. When the network is lightly used, these schemes attempt to use additional network resources to decrease communication delays. As the network utilization rises, the schemes degrade gracefully, still providing service but with minimal use of the network. Because the schemes use a combination of circuit and packet switching, they should respond to variations in the types and amounts of network traffic. Also, a combination of circuit and packet switching to support the widely varying traffic demands imposed on an integrated network was investigated. The packet switched component is best suited to bursty traffic where some delays in delivery are acceptable. The circuit switched component is reserved for traffic that must meet real time constraints. Selected packet routing algorithms that might be used in an integrated network were simulated. An integrated traffic places widely varying workload demands on a network. Adaptive algorithms were identified, ones that respond to both the transient and evolutionary changes that arise in integrated networks. A new algorithm was developed, hybrid weighted routing, that adapts to workload changes.

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

Global properties in an experimental realization of time-delayed feedback control with an unstable control loop.

PubMed

Höhne, Klaus; Shirahama, Hiroyuki; Choe, Chol-Ung; Benner, Hartmut; Pyragas, Kestutis; Just, Wolfram

2007-05-25

We demonstrate by electronic circuit experiments the feasibility of an unstable control loop to stabilize torsion-free orbits by time-delayed feedback control. Corresponding analytical normal form calculations and numerical simulations reveal a severe dependence of the basin of attraction on the particular coupling scheme of the control force. Such theoretical predictions are confirmed by the experiments and emphasize the importance of the coupling scheme for the global control performance.

The role of the medial prefrontal cortex in trace fear extinction

PubMed Central

Kwapis, Janine L.; Jarome, Timothy J.

2015-01-01

The extinction of delay fear conditioning relies on a neural circuit that has received much attention and is relatively well defined. Whether this established circuit also supports the extinction of more complex associations, however, is unclear. Trace fear conditioning is a better model of complex relational learning, yet the circuit that supports extinction of this memory has received very little attention. Recent research has indicated that trace fear extinction requires a different neural circuit than delay extinction; trace extinction requires the participation of the retrosplenial cortex, but not the amygdala, as noted in a previous study. Here, we tested the roles of the prelimbic and infralimbic regions of the medial prefrontal cortex in trace and delay fear extinction by blocking NMDA receptors during extinction learning. We found that the prelimbic cortex is necessary for trace, but not for delay fear extinction, whereas the infralimbic cortex is involved in both types of extinction. These results are consistent with the idea that trace fear associations require plasticity in multiple cortical areas for successful extinction. Further, the infralimbic cortex appears to play a role in extinction regardless of whether the animal was initially trained in trace or delay conditioning. Together, our results provide new information about how the neural circuits supporting trace and delay fear extinction differ. PMID:25512576

Fine Output Voltage Control Method considering Time-Delay of Digital Inverter System for X-ray Computed Tomography

NASA Astrophysics Data System (ADS)

Shibata, Junji; Kaneko, Kazuhide; Ohishi, Kiyoshi; Ando, Itaru; Ogawa, Mina; Takano, Hiroshi

This paper proposes a new output voltage control for an inverter system, which has time-delay and nonlinear load. In the next generation X-ray computed tomography of a medical device (X-ray CT) that uses the contactless power transfer method, the feedback signal often contains time-delay due to AD/DA conversion and error detection/correction time. When the PID controller of the inverter system is received the adverse effects of the time-delay, the controller often has an overshoot and a oscillated response. In order to overcome this problem, this paper proposes a compensation method based on the Smith predictor for an inverter system having a time-delay and the nonlinear loads which are the diode bridge rectifier and X-ray tube. The proposed compensation method consists of the hybrid Smith predictor system based on an equivalent analog circuit and DSP. The experimental results confirm the validity of the proposed system.

Burner ignition system

DOEpatents

Carignan, Forest J.

1986-01-21

An electronic ignition system for a gas burner is battery operated. The battery voltage is applied through a DC-DC chopper to a step-up transformer to charge a capacitor which provides the ignition spark. The step-up transformer has a significant leakage reactance in order to limit current flow from the battery during initial charging of the capacitor. A tank circuit at the input of the transformer returns magnetizing current resulting from the leakage reactance to the primary in succeeding cycles. An SCR in the output circuit is gated through a voltage divider which senses current flow through a flame. Once the flame is sensed, further sparks are precluded. The same flame sensor enables a thermopile driven main valve actuating circuit. A safety valve in series with the main gas valve responds to a control pressure thermostatically applied through a diaphragm. The valve closes after a predetermined delay determined by a time delay orifice if the pilot gas is not ignited.

BLOCKING OSCILLATOR DOUBLE PULSE GENERATOR CIRCUIT

DOEpatents

Haase, J.A.

1961-01-24

A double-pulse generator, particuiarly a double-pulse generator comprising a blocking oscillator utilizing a feedback circuit to provide means for producing a second pulse within the recovery time of the blocking oscillator, is described. The invention utilized a passive network which permits adjustment of the spacing between the original pulses derived from the blocking oscillator and further utilizes the original pulses to trigger a circuit from which other pulses are initiated. These other pulses are delayed and then applied to the input of the blocking oscillator, with the result that the output from the oscillator circuit contains twice the number of pulses originally initiated by the blocking oscillator itself.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

How to induce multiple delays in coupled chaotic oscillators?

NASA Astrophysics Data System (ADS)

Bhowmick, Sourav K.; Ghosh, Dibakar; Roy, Prodyot K.; Kurths, Jürgen; Dana, Syamal K.

2013-12-01

Lag synchronization is a basic phenomenon in mismatched coupled systems, delay coupled systems, and time-delayed systems. It is characterized by a lag configuration that identifies a unique time shift between all pairs of similar state variables of the coupled systems. In this report, an attempt is made how to induce multiple lag configurations in coupled systems when different pairs of state variables attain different time shift. A design of coupling is presented to realize this multiple lag synchronization. Numerical illustration is given using examples of the Rössler system and the slow-fast Hindmarsh-Rose neuron model. The multiple lag scenario is physically realized in an electronic circuit of two Sprott systems.

New exponential synchronization criteria for time-varying delayed neural networks with discontinuous activations.

PubMed

Cai, Zuowei; Huang, Lihong; Zhang, Lingling

2015-05-01

This paper investigates the problem of exponential synchronization of time-varying delayed neural networks with discontinuous neuron activations. Under the extended Filippov differential inclusion framework, by designing discontinuous state-feedback controller and using some analytic techniques, new testable algebraic criteria are obtained to realize two different kinds of global exponential synchronization of the drive-response system. Moreover, we give the estimated rate of exponential synchronization which depends on the delays and system parameters. The obtained results extend some previous works on synchronization of delayed neural networks not only with continuous activations but also with discontinuous activations. Finally, numerical examples are provided to show the correctness of our analysis via computer simulations. Our method and theoretical results have a leading significance in the design of synchronized neural network circuits involving discontinuous factors and time-varying delays. Copyright © 2015 Elsevier Ltd. All rights reserved.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

NASA Astrophysics Data System (ADS)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Synchronous radio-frequency FM signal generator using direct digital synthesizers

NASA Astrophysics Data System (ADS)

Arablu, Masoud; Kafashi, Sajad; Smith, Stuart T.

2018-04-01

A novel Radio-Frequency Frequency-Modulated (RF-FM) signal generation method is introduced and a prototype circuit developed to evaluate its functionality and performance. The RF-FM signal generator uses a modulated, voltage-controlled time delay to correspondingly modulate the phase of a 10 MHz sinusoidal reference signal. This modulated reference signal is, in turn, used to clock a Direct Digital Synthesizer (DDS) circuit resulting in an FM signal at its output. The modulating signal that is input to the voltage-controlled time delay circuit is generated by another DDS that is synchronously clocked by the same 10 MHz sine wave signal before modulation. As a consequence, all of the digital components are timed from a single sine wave oscillator that forms the basis of all timing. The resultant output signal comprises a center, or carrier, frequency plus a series of phase-synchronized sidebands having exact integer harmonic frequency separation. In this study, carrier frequencies ranging from 10 MHz to 70 MHz are generated with modulation frequencies ranging from 10 kHz to 300 kHz. The captured spectra show that the FM signal characteristics, amplitude and phase, of the sidebands and the modulation depth are consistent with the Jacobi-Anger expansion for modulated harmonic signals.

78 FR 8638 - Self-Regulatory Organizations; National Stock Exchange, Inc.; Notice of Filing and Immediate...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

... Change To Delay the Operative Date of Rule 11.20A Regarding Market-Wide Circuit Breakers Due to... the market- wide circuit breakers on a pilot basis for a period scheduled to start on February 4, 2013... changed to April 8, 2013. The proposal would delay the operative date of the market-wide circuit breaker...

Defective sensorimotor integration in preparation for reaction time tasks in patients with multiple sclerosis.

PubMed

Cabib, Christopher; Llufriu, Sara; Casanova-Molla, Jordi; Saiz, Albert; Valls-Solé, Josep

2015-03-01

Slowness of voluntary movements in patients with multiple sclerosis (MS) may be due to various factors, including attentional and cognitive deficits, delays in motor conduction time, and impairment of specific central nervous system circuits. In 13 healthy volunteers and 20 mildly disabled, relapsing-remitting MS patients, we examined simple reaction time (SRT) tasks requiring sensorimotor integration in circuits involving the corpus callosum and the brain stem. A somatosensory stimulus was used as the imperative signal (IS), and subjects were requested to react with either the ipsilateral or the contralateral hand (uncrossed vs. crossed SRT). In 33% of trials, a startling auditory stimulus was presented together with the IS, and the percentage reaction time change with respect to baseline SRT trials was measured (StartReact effect). The difference between crossed and uncrossed SRT, which requires interhemispheric conduction, was significantly larger in patients than in healthy subjects (P = 0.021). The StartReact effect, which involves activation of brain stem motor pathways, was reduced significantly in patients with respect to healthy subjects (uncrossed trials: P = 0.015; crossed trials: P = 0.005). In patients, a barely significant correlation was found between SRT delay and conduction abnormalities in motor and sensory pathways (P = 0.02 and P = 0.04, respectively). The abnormalities found specifically in trials reflecting interhemispheric transfer of information, as well as the evidence for reduced subcortical motor preparation, indicate that a delay in reaction time execution in MS patients cannot be explained solely by conduction slowing in motor and sensory pathways but suggest, instead, defective sensorimotor integration mechanisms in at least the two circuits examined. Copyright © 2015 The American Physiological Society.

TIME-INTERVAL MEASURING DEVICE

DOEpatents

Gross, J.E.

1958-04-15

An electronic device for measuring the time interval between two control pulses is presented. The device incorporates part of a previous approach for time measurement, in that pulses from a constant-frequency oscillator are counted during the interval between the control pulses. To reduce the possible error in counting caused by the operation of the counter gating circuit at various points in the pulse cycle, the described device provides means for successively delaying the pulses for a fraction of the pulse period so that a final delay of one period is obtained and means for counting the pulses before and after each stage of delay during the time interval whereby a plurality of totals is obtained which may be averaged and multplied by the pulse period to obtain an accurate time- Interval measurement.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

A Simple Snap Oscillator with Coexisting Attractors, Its Time-Delayed Form, Physical Realization, and Communication Designs

NASA Astrophysics Data System (ADS)

Rajagopal, Karthikeyan; Jafari, Sajad; Akgul, Akif; Karthikeyan, Anitha; Çiçek, Serdar; Shekofteh, Yasser

2018-05-01

In this paper, we report a novel chaotic snap oscillator with one nonlinear function. Dynamic analysis of the system shows the existence of bistability. To study the time delay effects on the proposed snap oscillator, we introduce multiple time delay in the fourth state equation. Investigation of dynamical properties of the time-delayed system shows that the snap oscillator exhibits the same multistable properties as the nondelayed system. The new multistable hyperjerk chaotic system has been tested in chaos shift keying and symmetric choc shift keying modulated communication designs for engineering applications. It has been determined that the symmetric chaos shift keying modulated communication system implemented with the new chaotic system is more successful than the chaos shift keying modulation for secure communication. Also, circuit implementation of the chaotic snap oscillator with tangent function is carried out showing its feasibility.

Algorithms and architecture for multiprocessor based circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deutsch, J.T.

Accurate electrical simulation is critical to the design of high performance integrated circuits. Logic simulators can verify function and give first-order timing information. Switch level simulators are more effective at dealing with charge sharing than standard logic simulators, but cannot provide accurate timing information or discover DC problems. Delay estimation techniques and cell level simulation can be used in constrained design methods, but must be tuned for each application, and circuit simulation must still be used to generate the cell models. None of these methods has the guaranteed accuracy that many circuit designers desire, and none can provide detailed waveformmore » information. Detailed electrical-level simulation can predict circuit performance if devices and parasitics are modeled accurately. However, the computational requirements of conventional circuit simulators make it impractical to simulate current large circuits. In this dissertation, the implementation of Iterated Timing Analysis (ITA), a relaxation-based technique for accurate circuit simulation, on a special-purpose multiprocessor is presented. The ITA method is an SOR-Newton, relaxation-based method which uses event-driven analysis and selective trace to exploit the temporal sparsity of the electrical network. Because event-driven selective trace techniques are employed, this algorithm lends itself to implementation on a data-driven computer.« less

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Five Bit, Five Gigasample TED Analog-to-Digital Converter Development.

DTIC Science & Technology

1981-06-01

pliers. TRW uses two sources at present: materials grown by Horizontal I Bridgman technique from Crystal Specialties, and Czochralski from MRI. The...the circuit modelling and circuit design tasks. A number of design iterations were required to arrive at a satisfactory design. In or-der to riake...made by modeling the TELD as a voltage-controlled current generator with a built-in time delay between impressed voltage and output current. Based on

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

Finite-time mixed outer synchronization of complex networks with coupling time-varying delay.

PubMed

He, Ping; Ma, Shu-Hua; Fan, Tao

2012-12-01

This article is concerned with the problem of finite-time mixed outer synchronization (FMOS) of complex networks with coupling time-varying delay. FMOS is a recently developed generalized synchronization concept, i.e., in which different state variables of the corresponding nodes can evolve into finite-time complete synchronization, finite-time anti-synchronization, and even amplitude finite-time death simultaneously for an appropriate choice of the controller gain matrix. Some novel stability criteria for the synchronization between drive and response complex networks with coupling time-varying delay are derived using the Lyapunov stability theory and linear matrix inequalities. And a simple linear state feedback synchronization controller is designed as a result. Numerical simulations for two coupled networks of modified Chua's circuits are then provided to demonstrate the effectiveness and feasibility of the proposed complex networks control and synchronization schemes and then compared with the proposed results and the previous schemes for accuracy.

Development of ball surface acoustic wave trace moisture analyzer using burst waveform undersampling circuit

NASA Astrophysics Data System (ADS)

Tsuji, Toshihiro; Oizumi, Toru; Fukushi, Hideyuki; Takeda, Nobuo; Akao, Shingo; Tsukahara, Yusuke; Yamanaka, Kazushi

2018-05-01

The measurement and control of trace moisture, where the water concentration is lower than 1 ppmv [-76.2 °C for the frost point (°CFP)], are essential for improving the yield rate of semiconductor devices and for ensuring their reliability. A ball surface acoustic wave (SAW) sensor with a sol-gel silica coating exhibited useful characteristics for a trace moisture analyzer (TMA) when the temperature drift of the delay time output was precisely compensated using two-frequency measurement (TFM), where the temperature-compensated relative delay time change (RDTC) was obtained by subtracting the RDTC at the fundamental frequency from that at the third harmonic frequency on an identical propagation path. However, the cost of the measurement circuit was a problem. In this study, a burst waveform undersampling (BUS) circuit based on the theory of undersampling measurement was developed as a practical means. The BUS circuit was useful for precise temperature compensation of the RDTC, and the ball SAW TMA was prototyped by calibrating the RDTC using a TMA based on cavity ring-down spectroscopy (CRDS), which is the most reliable method for trace moisture measurement. The ball SAW TMA outputted a similar concentration to that obtained by the CRDS TMA, and its response time at a set concentration in N2 with a flow rate of 1 l/min was about half that of the CRDS TMA, suggesting that moisture of -80 °CFP was measured within only 1 min. The detection limit at a signal-to-noise ratio of 3 was estimated to be 0.05 ppbv, comparable with that of the CRDS TMA. From these results, it was demonstrated that a practical ball SAW TMA can be realized using the developed BUS circuit.

Comparison of in-situ delay monitors for use in Adaptive Voltage Scaling

NASA Astrophysics Data System (ADS)

Pour Aryan, N.; Heiß, L.; Schmitt-Landsiedel, D.; Georgakos, G.; Wirnshofer, M.

2012-09-01

In Adaptive Voltage Scaling (AVS) the supply voltage of digital circuits is tuned according to the circuit's actual operating condition, which enables dynamic compensation to PVTA variations. By exploiting the excessive safety margins added in state-of-the-art worst-case designs considerable power saving is achieved. In our approach, the operating condition of the circuit is monitored by in-situ delay monitors. This paper presents different designs to implement the in-situ delay monitors capable of detecting late but still non-erroneous transitions, called Pre-Errors. The developed Pre-Error monitors are integrated in a 16 bit multiplier test circuit and the resulting Pre-Error AVS system is modeled by a Markov chain in order to determine the power saving potential of each Pre-Error detection approach.

An ultra low-power CMOS automatic action potential detector.

PubMed

Gosselin, Benoit; Sawan, Mohamad

2009-08-01

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- microm chip dissipates 780 nW, and it features a size of 0.07 mm(2). So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Seyedi, Saeid; Navimipour, Nima Jafari

2018-03-01

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal-Oxide-Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.

Theoretical and experimental aspects of chaos control by time-delayed feedback.

PubMed

Just, Wolfram; Benner, Hartmut; Reibold, Ekkehard

2003-03-01

We review recent developments for the control of chaos by time-delayed feedback methods. While such methods are easily applied even in quite complex experimental context the theoretical analysis yields infinite-dimensional differential-difference systems which are hard to tackle. The essential ideas for a general theoretical approach are sketched and the results are compared to electronic circuits and to high power ferromagnetic resonance experiments. Our results show that the control performance can be understood on the basis of experimentally accessible quantities without resort to any model for the internal dynamics.

Lag and anticipating synchronization without time-delay coupling.

PubMed

Corron, Ned J; Blakely, Jonathan N; Pethel, Shawn D

2005-06-01

We describe a new method for achieving approximate lag and anticipating synchronization in unidirectionally coupled chaotic oscillators. The method uses a specific parameter mismatch between the drive and response that is a first-order approximation to true time-delay coupling. As a result, an adjustable lag or anticipation effect can be achieved without the need for a variable delay line, making the method simpler and more economical to implement in many physical systems. We present a stability analysis, demonstrate the method numerically, and report experimental observation of the effect in radio-frequency electronic oscillators. In the circuit experiments, both lag and anticipation are controlled by tuning a single capacitor in the response oscillator.

Developmental excitatory-to-inhibitory GABA polarity switch is delayed in Ts65Dn mice, a genetic model of Down syndrome.

PubMed

Lysenko, Larisa V; Kim, Jeesun; Madamba, Francisco; Tyrtyshnaia, Anna A; Ruparelia, Aarti; Kleschevnikov, Alexander M

2018-07-01

Down syndrome (DS) is the most frequent genetic cause of developmental abnormalities leading to intellectual disability. One notable phenomenon affecting the formation of nascent neural circuits during late developmental periods is developmental switch of GABA action from depolarizing to hyperpolarizing mode. We examined properties of this switch in DS using primary cultures and acute hippocampal slices from Ts65Dn mice, a genetic model of DS. Cultures of DIV3-DIV13 Ts65Dn and control normosomic (2 N) neurons were loaded with FURA-2 AM, and GABA action was assessed using local applications. In 2 N cultures, the number of GABA-activated cells dropped from ~100% to 20% between postnatal days 3-13 (P3-P13) reflecting the switch in GABA action polarity. In Ts65Dn cultures, the timing of this switch was delayed by 2-3 days. Next, microelectrode recordings of multi-unit activity (MUA) were performed in CA3 slices during bath application of the GABA A agonist isoguvacine. MUA frequency was increased in P8-P12 and reduced in P14-P22 slices reflecting the switch of GABA action from excitatory to inhibitory mode. The timing of this switch was delayed in Ts65Dn by approximately 2 days. Finally, frequency of giant depolarizing potentials (GDPs), a form of primordial neural activity, was significantly increased in slices from Ts65Dn pups at P12 and P14. These experimental evidences show that GABA action polarity switch is delayed in Ts65Dn model of DS, and that these changes lead to a delay in maturation of nascent neural circuits. These alterations may affect properties of neural circuits in adult animals and, therefore, represent a prospective target for pharmacotherapy of cognitive impairment in DS. Copyright © 2018 Elsevier Inc. All rights reserved.

Zero-lag synchronization in coupled time-delayed piecewise linear electronic circuits

NASA Astrophysics Data System (ADS)

Suresh, R.; Srinivasan, K.; Senthilkumar, D. V.; Raja Mohamed, I.; Murali, K.; Lakshmanan, M.; Kurths, J.

2013-07-01

We investigate and report an experimental confirmation of zero-lag synchronization (ZLS) in a system of three coupled time-delayed piecewise linear electronic circuits via dynamical relaying with different coupling configurations, namely mutual and subsystem coupling configurations. We have observed that when there is a feedback between the central unit (relay unit) and at least one of the outer units, ZLS occurs in the two outer units whereas the central and outer units exhibit inverse phase synchronization (IPS). We find that in the case of mutual coupling configuration ZLS occurs both in periodic and hyperchaotic regimes, while in the subsystem coupling configuration it occurs only in the hyperchaotic regime. Snapshots of the time evolution of outer circuits as observed from the oscilloscope confirm the occurrence of ZLS experimentally. The quality of ZLS is numerically verified by correlation coefficient and similarity function measures. Further, the transition to ZLS is verified from the changes in the largest Lyapunov exponents and the correlation coefficient as a function of the coupling strength. IPS is experimentally confirmed using time series plots and also can be visualized using the concept of localized sets which are also corroborated by numerical simulations. In addition, we have calculated the correlation of probability of recurrence to quantify the phase coherence. We have also analytically derived a sufficient condition for the stability of ZLS using the Krasovskii-Lyapunov theory.

A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

NASA Astrophysics Data System (ADS)

Zhujia, Chen; Haigang, Yang; Fei, Liu; Yu, Wang

2011-10-01

A fast-locking all-digital delay-locked loop (ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array (FPGA). The ADDLL performs a 90° phase-shift so that the data strobe (DQS) can enlarge the data valid window in order to minimize skew. In order to further reduce the locking time and to prevent the harmonic locking problem, a time-to-digital converter (TDC) is proposed. A duty cycle corrector (DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%. The ADDLL, implemented in a commercial 0.13 μm CMOS process, occupies a total of 0.017 mm2 of active area. Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps. The time interval error (TIE) of the proposed circuit is 60.7 ps.

Subwavelength grating enabled on-chip ultra-compact optical true time delay line

PubMed Central

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R.

2016-01-01

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth. PMID:27457024

Subwavelength grating enabled on-chip ultra-compact optical true time delay line.

PubMed

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R

2016-07-26

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth.

Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

DTIC Science & Technology

2008-10-01

memory interface, arbiter/ schedulers for rescheduling the memory requests according to some schedule policy, and memory channels for communicating...between the power-savings and the wakeup overhead with respect to both wakeup power and wakeup delay. For example, dream mode can save 50% more static...power than sleep mode, but at the expense of twice the wake delay and three times the wakeup energy. The user can specify power-gating modes for various components.

Phase-locked-loop-based delay-line-free picosecond electro-optic sampling system

NASA Astrophysics Data System (ADS)

Lin, Gong-Ru; Chang, Yung-Cheng

2003-04-01

A delay-line-free, high-speed electro-optic sampling (EOS) system is proposed by employing a delay-time-controlled ultrafast laser diode as the optical probe. Versatile optoelectronic delay-time controllers (ODTCs) based on modified voltage-controlled phase-locked-loop phase-shifting technologies are designed for the laser. The integration of the ODTC circuit and the pulsed laser diode has replaced the traditional optomechanical delay-line module used in the conventional EOS system. This design essentially prevents sampling distortion from misalignment of the probe beam, and overcomes the difficulty in sampling free-running high-speed transients. The maximum tuning range, error, scanning speed, tuning responsivity, and resolution of the ODTC are 3.9π (700°), <5% deviation, 25-2405 ns/s, 0.557 ps/mV, and ˜1 ps, respectively. Free-running wave forms from the analog, digital, and pulsed microwave signals are sampled and compared with those measured by the commercial apparatus.

Repetitive Series Interrupter II.

DTIC Science & Technology

1977-07-01

nated by other authorized documents. The citation of trade names and names of manufacturers is this report is not to be construed as official... intergrating inductor Magnet circuit load resistance Pulse-forming network load resistance Fault network load resistance Time delay between TUT fire and

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation

PubMed Central

Wang, Runchun M.; Hamilton, Tara J.; Tapson, Jonathan C.; van Schaik, André

2014-01-01

We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits. PMID:24672422

A mixed-signal implementation of a polychronous spiking neural network with delay adaptation.

PubMed

Wang, Runchun M; Hamilton, Tara J; Tapson, Jonathan C; van Schaik, André

2014-01-01

We present a mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns. The proposed neural network contains one neuron array and one axon array. Spike Timing Dependent Delay Plasticity is used to fine-tune delays and add dynamics to the network. In our mixed-signal implementation, the neurons and axons have been implemented as both analog and digital circuits. The system thus consists of one FPGA, containing the digital neuron array and the digital axon array, and one analog IC containing the analog neuron array and the analog axon array. The system can be easily configured to use different combinations of each. We present and discuss the experimental results of all combinations of the analog and digital axon arrays and the analog and digital neuron arrays. The test results show that the proposed neural network is capable of successfully recalling more than 85% of stored patterns using both analog and digital circuits.

Understanding in an instant: neurophysiological evidence for mechanistic language circuits in the brain.

PubMed

Pulvermüller, Friedemann; Shtyrov, Yury; Hauk, Olaf

2009-08-01

How long does it take the human mind to grasp the idea when hearing or reading a sentence? Neurophysiological methods looking directly at the time course of brain activity indexes of comprehension are critical for finding the answer to this question. As the dominant cognitive approaches, models of serial/cascaded and parallel processing, make conflicting predictions on the time course of psycholinguistic information access, they can be tested using neurophysiological brain activation recorded in MEG and EEG experiments. Seriality and cascading of lexical, semantic and syntactic processes receives support from late (latency approximately 1/2s) sequential neurophysiological responses, especially N400 and P600. However, parallelism is substantiated by early near-simultaneous brain indexes of a range of psycholinguistic processes, up to the level of semantic access and context integration, emerging already 100-250ms after critical stimulus information is present. Crucially, however, there are reliable latency differences of 20-50ms between early cortical area activations reflecting lexical, semantic and syntactic processes, which are left unexplained by current serial and parallel brain models of language. We here offer a mechanistic model grounded in cortical nerve cell circuits that builds upon neuroanatomical and neurophysiological knowledge and explains both near-simultaneous activations and fine-grained delays. A key concept is that of discrete distributed cortical circuits with specific inter-area topographies. The full activation, or ignition, of specifically distributed binding circuits explains the near-simultaneity of early neurophysiological indexes of lexical, syntactic and semantic processing. Activity spreading within circuits determined by between-area conduction delays accounts for comprehension-related regional activation differences in the millisecond range.

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

NASA Astrophysics Data System (ADS)

Chen, R. M.; Mahatme, N. N.; Diggins, Z. J.; Wang, L.; Zhang, E. X.; Chen, Y. P.; Liu, Y. N.; Narasimham, B.; Witulski, A. F.; Bhuva, B. L.; Fleetwood, D. M.

2017-08-01

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed.

Programmable Differential Delay Circuit With Fine Delay Adjustment

DOEpatents

DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan

2002-07-09

Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

PARALYZER FOR PULSE HEIGHT DISTRIBUTION ANALYZER

DOEpatents

Fairstein, E.

1960-01-19

A paralyzer circuit is described for use with a pulseheight distribution analyzer to prevent the analyzer from counting overlapping pulses where they would serve to provide a false indication. The paralyzer circuit comprises a pair of cathode-coupled amplifiers for amplifying pulses of opposite polarity. Diodes are provided having their anodes coupled to the separate outputs of the amplifiers to produce only positive signals, and a trigger circuit is coupled to the diodes ior operation by input pulses of either polarity from the amplifiers. A delay network couples the output of the trigger circuit for delaying the pulses.

Method and apparatus for characterizing propagation delays of integrated circuit devices

NASA Technical Reports Server (NTRS)

Blaes, Brent R. (Inventor); Buehler, Martin G. (Inventor)

1987-01-01

Propagation delay of a signal through a channel is measured by cyclically generating a first step-wave signal for transmission through the channel to a two-input logic element and a second step-wave signal with a controlled delay to the second input terminal of the logic element. The logic element determines which signal is present first at its input terminals and stores a binary signal indicative of that determination for control of the delay of the second signal which is advanced or retarded for the next cycle until both the propagation delayed first step-wave signal and the control delayed step-wave signal are coincident. The propagation delay of the channel is then determined by measuring the time between the first and second step-wave signals out of the controlled step-wave signal generator.

VLSI Design Tools, Reference Manual, Release 2.0.

DTIC Science & Technology

1984-08-01

eder. 2.3 ITACV: Libary ofC readne. far oesumdg a layoit 1-,, tiling. V ~2.4 "QUILT: CeinS"Wbesa-i-M-8euar ray f atwok til 2.5 "TIL: Tockmeleff...8217patterns package was added so that complex and repetitive digital waveforms could be generated far more easily. The recently written program MTP (Multiple...circuit model to estimate timing delays through digital circuits. It also has a mode that allows it to be used as a switch (gate) level simulator

Reduction in maximum time uncertainty of paired time signals

DOEpatents

Theodosiou, G.E.; Dawson, J.W.

1983-10-04

Reduction in the maximum time uncertainty (t[sub max]--t[sub min]) of a series of paired time signals t[sub 1] and t[sub 2] varying between two input terminals and representative of a series of single events where t[sub 1][<=]t[sub 2] and t[sub 1]+t[sub 2] equals a constant, is carried out with a circuit utilizing a combination of OR and AND gates as signal selecting means and one or more time delays to increase the minimum value (t[sub min]) of the first signal t[sub 1] closer to t[sub max] and thereby reduce the difference. The circuit may utilize a plurality of stages to reduce the uncertainty by factors of 20--800. 6 figs.

Reduction in maximum time uncertainty of paired time signals

DOEpatents

Theodosiou, George E.; Dawson, John W.

1983-01-01

Reduction in the maximum time uncertainty (t.sub.max -t.sub.min) of a series of paired time signals t.sub.1 and t.sub.2 varying between two input terminals and representative of a series of single events where t.sub.1 .ltoreq.t.sub.2 and t.sub.1 +t.sub.2 equals a constant, is carried out with a circuit utilizing a combination of OR and AND gates as signal selecting means and one or more time delays to increase the minimum value (t.sub.min) of the first signal t.sub.1 closer to t.sub.max and thereby reduce the difference. The circuit may utilize a plurality of stages to reduce the uncertainty by factors of 20-800.

A Method for Measuring the Effective Throughput Time Delay in Simulated Displays Involving Manual Control

NASA Technical Reports Server (NTRS)

Jewell, W. F.; Clement, W. F.

1984-01-01

The advent and widespread use of the computer-generated image (CGI) device to simulate visual cues has a mixed impact on the realism and fidelity of flight simulators. On the plus side, CGIs provide greater flexibility in scene content than terrain boards and closed circuit television based visual systems, and they have the potential for a greater field of view. However, on the minus side, CGIs introduce into the visual simulation relatively long time delays. In many CGIs, this delay is as much as 200 ms, which is comparable to the inherent delay time of the pilot. Because most GCIs use multiloop processing and smoothing algorithms and are linked to a multiloop host computer, it is seldom possible to identify a unique throughput time delay, and it is therefore difficult to quantify the performance of the closed loop pilot simulator system relative to the real world task. A method to address these issues using the critical task tester is described. Some empirical results from applying the method are presented, and a novel technique for improving the performance of GCIs is discussed.

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

NASA Technical Reports Server (NTRS)

Wong, Derek C.; De Micheli, Giovanni; Flynn, Michael J.; Huston, Robert E.

1992-01-01

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

Superconducting flux flow digital circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.

1993-03-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-[mu]m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps,more » and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic.« less

Gender and socio-cultural determinants of delay to diagnosis of TB in Bangladesh, India and Malawi.

PubMed

Gosoniu, G D; Ganapathy, S; Kemp, J; Auer, C; Somma, D; Karim, F; Weiss, M G

2008-07-01

Tuberculosis (TB) control programmes in Bangladesh, India and Malawi. To compare the interval from symptom onset to diagnosis of TB for men and women, and to assess socio-cultural and gender-related features of illness explaining diagnostic delay. Semi-structured Explanatory Model Interview Catalogue (EMIC) interviews were administered to 100 or more patients at each site, assessing categories of distress, perceived causes and help seeking. Based on time from initial symptoms to diagnosis of TB, patients were classified with problem delay (>90 days), timely diagnosis (< or =30 days) or moderate delay. EMIC interview data were analysed to explain problem delay. The median interval from symptom onset to diagnosis was longest in India and shortest in Malawi. With adjustment for confounding, female sex (Bangladesh), and status of married woman (India) and housewife (Malawi) were associated with problem delay. Prominent non-specific symptoms--chest pain (Bangladesh) and breathlessness (Malawi)--were also significant. Cough in India, widely associated with TB, was associated with timely diagnosis. Sanitation as a perceived cause linked to poor urban conditions was associated with delayed diagnosis in India. Specific prior help seeking with circuitous referral patterns was identified. The study identified gender- and illness-related features of diagnostic delay. Further research distinguishing patient and provider delay is needed.

Chaos in the fractional order logistic delay system: Circuit realization and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baskonus, Haci Mehmet; Hammouch, Zakia; Mekkaoui, Toufik

2016-06-08

In this paper, we present a numerical study and a circuit design to prove existence of chaos in the fractional order Logistic delay system. In addition, we investigate an active control synchronization scheme in this system. Numerical and cicruit simulations show the effectiveness and feasibility of this method.

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

NASA Technical Reports Server (NTRS)

Smith, Edwyn D.

1991-01-01

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

DTIC Science & Technology

1992-06-01

V6Z2J7 Canada Gustavo A. Cubas E. 1 Engineered Systems, Inc 2 Seccion De Transmission ATTN: Mr. David Gilfillan Direccion De Ingenieria Y Proyectos 14775...buffering, and and filter delay (for a voice circuit). Propagation delay is independent of data rate, while buffering delay is inversely proportional to...Complexe Des Jardins, 15th Fl. 171 N. Covington Drive 75 Rene Levesque West Bloomingdale, IL 60108 Montreal, PG H2Z Canada DISTRIBUTION LIST Department

Centering a DDR Strobe in the Middle of a Data Packet

NASA Technical Reports Server (NTRS)

Johnson, Michael; Nelson, Dave; Seefeldt, James; Roper, Weston; Passow, Craig

2014-01-01

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Reduction in maximum time uncertainty of paired time signals

DOEpatents

Theodosiou, G.E.; Dawson, J.W.

1981-02-11

Reduction in the maximum time uncertainty (t/sub max/ - t/sub min/) of a series of paired time signals t/sub 1/ and t/sub 2/ varying between two input terminals and representative of a series of single events where t/sub 1/ less than or equal to t/sub 2/ and t/sub 1/ + t/sub 2/ equals a constant, is carried out with a circuit utilizing a combination of OR and AND gates as signal selecting means and one or more time delays to increase the minimum value (t/sub min/) of the first signal t/sub 1/ closer to t/sub max/ and thereby reduce the difference. The circuit may utilize a plurality of stages to reduce the uncertainty by factors of 20 to 800.

Variability-aware double-patterning layout optimization for analog circuits

NASA Astrophysics Data System (ADS)

Li, Yongfu; Perez, Valerio; Tripathi, Vikas; Lee, Zhao Chuan; Tseng, I.-Lun; Ong, Jonathan Yoong Seang

2018-03-01

The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit's mismatch. To overcome the problem and improve the turn-around time, we proposed our smart "anchoring" placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.

Amplitude death and synchronized states in nonlinear time-delay systems coupled through mean-field diffusion

NASA Astrophysics Data System (ADS)

Banerjee, Tanmoy; Biswas, Debabrata

2013-12-01

We explore and experimentally demonstrate the phenomena of amplitude death (AD) and the corresponding transitions through synchronized states that lead to AD in coupled intrinsic time-delayed hyperchaotic oscillators interacting through mean-field diffusion. We identify a novel synchronization transition scenario leading to AD, namely transitions among AD, generalized anticipatory synchronization (GAS), complete synchronization (CS), and generalized lag synchronization (GLS). This transition is mediated by variation of the difference of intrinsic time-delays associated with the individual systems and has no analogue in non-delayed systems or coupled oscillators with coupling time-delay. We further show that, for equal intrinsic time-delays, increasing coupling strength results in a transition from the unsynchronized state to AD state via in-phase (complete) synchronized states. Using Krasovskii-Lyapunov theory, we derive the stability conditions that predict the parametric region of occurrence of GAS, GLS, and CS; also, using a linear stability analysis, we derive the condition of occurrence of AD. We use the error function of proper synchronization manifold and a modified form of the similarity function to provide the quantitative support to GLS and GAS. We demonstrate all the scenarios in an electronic circuit experiment; the experimental time-series, phase-plane plots, and generalized autocorrelation function computed from the experimental time series data are used to confirm the occurrence of all the phenomena in the coupled oscillators.

Optoelectronic Infrastructure for Radio Frequency and Optical Phased Arrays

NASA Technical Reports Server (NTRS)

Cai, Jianhong

2015-01-01

Optoelectronic integrated circuits offer radiation-hardened solutions for satellite systems in addition to improved size, weight, power, and bandwidth characteristics. ODIS, Inc., has developed optoelectronic integrated circuit technology for sensing and data transfer in phased arrays. The technology applies integrated components (lasers, amplifiers, modulators, detectors, and optical waveguide switches) to a radio frequency (RF) array with true time delay for beamsteering. Optical beamsteering is achieved by controlling the current in a two-dimensional (2D) array. In this project, ODIS integrated key components to produce common RF-optical aperture operation.

Feedback in Action--The Mechanism of the Iris.

ERIC Educational Resources Information Center

Pingnet, B.; And Others

1988-01-01

Describes two demonstration experiments. Outlines a demonstration of the general principle of positive and negative feedback and the influence of time delays in feedback circuits. Elucidates the principle of negative feedback with a model of the iris of the eye. Emphasizes the importance of feedback in biological systems. (CW)

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

NASA Technical Reports Server (NTRS)

Shuler, Robert L.; Balasubramanian, Anupama; Narasimham, Balaji; Bhuva, Bharat; O'Neill, Patrick M.; Kouba, Coy

2006-01-01

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

PubMed

Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

2017-07-01

Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

High frequency modulation circuits based on photoconductive wide bandgap switches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sampayan, Stephen

Methods, systems, and devices for high voltage and/or high frequency modulation. In one aspect, an optoelectronic modulation system includes an array of two or more photoconductive switch units each including a wide bandgap photoconductive material coupled between a first electrode and a second electrode, a light source optically coupled to the WBGP material of each photoconductive switch unit via a light path, in which the light path splits into multiple light paths to optically interface with each WBGP material, such that a time delay of emitted light exists along each subsequent split light path, and in which the WBGP materialmore » conducts an electrical signal when a light signal is transmitted to the WBGP material, and an output to transmit the electrical signal conducted by each photoconductive switch unit. The time delay of the photons emitted through the light path is substantially equivalent to the time delay of the electrical signal.« less

A simple device for long-term radar cross section recordings.

PubMed

Eskelinen, Pekka; Ruoskanen, Jukka; Peltonen, Jouni

2009-05-01

A sample and hold circuit with settable delay can be used for recording of radar echo amplitude variations having time scales up to 100 s at the selected range bin in systems utilizing short rf pulses. The design is based on two integrated circuits and gives 1% uncertainty for 70 ns pulses. The key benefit is a real-time display of lengthy amplitude variations because the sample rate is defined by the radar pulse repetition frequency. Additionally we get a reduction in file size at least by the inverse of the radar's duty cycle. Examples of 10 and 100 s recordings with a Ka-band short pulse radar are described.

Versatile solid-state relay

NASA Technical Reports Server (NTRS)

Fox, D. A.

1977-01-01

Solid-state relay (SSR), containing multinode control logic, is operated as normally open, normally closed, or latched. Moreover several can be paralleled to form two-pole or double-throw relays. Versatile unit ends need to design custom control circuit for every relay application. Technique can be extended to incorporate selectable time delay, on operation or release, or pulsed output.

Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC

NASA Astrophysics Data System (ADS)

Xu, Zule; Miyahara, Masaya; Matsuzawa, Akira

2014-04-01

A picosecond resolution time-to-digital converter (TDC) is presented. The resolution of a conventional delay chain TDC is limited by the delay of a logic buffer. Various types of recent TDCs are successful in breaking this limitation, but they require a significant calibration effort to achieve picosecond resolution with a sufficient linear range. To address these issues, we propose a simple method to break the resolution limitation without any calibration: a Gm-C integrator followed by a successive approximation register analog-to-digital converter (SAR-ADC). This translates the time interval into charge, and then the charge is quantized. A prototype chip was fabricated in 90 nm CMOS. The measurement results reveal a 1 ps resolution, a -0.6/0.7 LSB differential nonlinearity (DNL), a -1.1/2.3 LSB integral nonlinearity (INL), and a 9-bit range. The measured 11.74 ps single-shot precision is caused by the noise of the integrator. We analyze the noise of the integrator and propose an improved front-end circuit to reduce this noise. The proposal is verified by simulations showing the maximum single-shot precision is less than 1 ps. The proposed front-end circuit can also diminish the mismatch effects.

The Induction of Chaos in Electronic Circuits Final Report-October 1, 2001

DOE Office of Scientific and Technical Information (OSTI.GOV)

R.M.Wheat, Jr.

2003-04-01

This project, now known by the name ''Chaos in Electronic Circuits,'' was originally tasked as a two-year project to examine various ''fault'' or ''non-normal'' operational states of common electronic circuits with some focus on determining the feasibility of exploiting these states. Efforts over the two-year duration of this project have been dominated by the study of the chaotic behavior of electronic circuits. These efforts have included setting up laboratory space and hardware for conducting laboratory tests and experiments, acquiring and developing computer simulation and analysis capabilities, conducting literature surveys, developing test circuitry and computer models to exercise and test ourmore » capabilities, and experimenting with and studying the use of RF injection as a means of inducing chaotic behavior in electronics. An extensive array of nonlinear time series analysis tools have been developed and integrated into a package named ''After Acquisition'' (AA), including capabilities such as Delayed Coordinate Embedding Mapping (DCEM), Time Resolved (3-D) Fourier Transform, and several other phase space re-creation methods. Many computer models have been developed for Spice and for the ATP (Alternative Transients Program), modeling the several working circuits that have been developed for use in the laboratory. And finally, methods of induction of chaos in electronic circuits have been explored.« less

Overload protection for switching regulators

NASA Technical Reports Server (NTRS)

Lachochi, E.

1980-01-01

Circuit protects all output lines of switching regulator against overloads without requiring current sensors on every line. If overload is sensed, device short circuits bias on switching transistor so that power is rapidly cut off from loads. Circuit also includes delay network to inhibit erroneous operation during startup.

Long period pseudo random number sequence generator

NASA Technical Reports Server (NTRS)

Wang, Charles C. (Inventor)

1989-01-01

A circuit for generating a sequence of pseudo random numbers, (A sub K). There is an exponentiator in GF(2 sup m) for the normal basis representation of elements in a finite field GF(2 sup m) each represented by m binary digits and having two inputs and an output from which the sequence (A sub K). Of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs (E sub K) of maximal length shift register of n stages. There is a switch having a pair of inputs and an output. The switch outputs is connected to the other of the two inputs of the exponentiator. One of the switch inputs is connected for initially receiving a primitive element (A sub O) in GF(2 sup m). Finally, there is a delay circuit having an input and an output. The delay circuit output is connected to the other of the switch inputs and the delay circuit input is connected to the output of the exponentiator. Whereby after the exponentiator initially receives the primitive element (A sub O) in GF(2 sup m) through the switch, the switch can be switched to cause the exponentiator to receive as its input a delayed output A(K-1) from the exponentiator thereby generating (A sub K) continuously at the output of the exponentiator. The exponentiator in GF(2 sup m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U(sub i) = 92(sup i) (for n(sub i) = 1 or 1 (for n(subi) = 0).

Principles of cell-free genetic circuit assembly.

PubMed

Noireaux, Vincent; Bar-Ziv, Roy; Libchaber, Albert

2003-10-28

Cell-free genetic circuit elements were constructed in a transcription-translation extract. We engineered transcriptional activation and repression cascades, in which the protein product of each stage is the input required to drive or block the following stage. Although we can find regions of linear response for single stages, cascading to subsequent stages requires working in nonlinear regimes. Substantial time delays and dramatic decreases in output production are incurred with each additional stage because of a bottleneck at the translation machinery. Faster turnover of RNA message can relieve competition between genes and stabilize output against variations in input and parameters.

Controlling state explosion during automatic verification of delay-insensitive and delay-constrained VLSI systems using the POM verifier

NASA Technical Reports Server (NTRS)

Probst, D.; Jensen, L.

1991-01-01

Delay-insensitive VLSI systems have a certain appeal on the ground due to difficulties with clocks; they are even more attractive in space. We answer the question, is it possible to control state explosion arising from various sources during automatic verification (model checking) of delay-insensitive systems? State explosion due to concurrency is handled by introducing a partial-order representation for systems, and defining system correctness as a simple relation between two partial orders on the same set of system events (a graph problem). State explosion due to nondeterminism (chiefly arbitration) is handled when the system to be verified has a clean, finite recurrence structure. Backwards branching is a further optimization. The heart of this approach is the ability, during model checking, to discover a compact finite presentation of the verified system without prior composition of system components. The fully-implemented POM verification system has polynomial space and time performance on traditional asynchronous-circuit benchmarks that are exponential in space and time for other verification systems. We also sketch the generalization of this approach to handle delay-constrained VLSI systems.

New results on anti-synchronization of switched neural networks with time-varying delays and lag signals.

PubMed

Cao, Yuting; Wen, Shiping; Chen, Michael Z Q; Huang, Tingwen; Zeng, Zhigang

2016-09-01

This paper investigates the problem of global exponential anti-synchronization of a class of switched neural networks with time-varying delays and lag signals. Considering the packed circuits, the controller is dependent on the output of the system as the inner states are very hard to measure. Therefore, it is necessary to investigate the controller based on the output of the neuron cell. Through theoretical analysis, it is obvious that the obtained ones improve and generalize the results derived in the previous literature. To illustrate the effectiveness, a simulation example with applications in image encryptions is also presented in the paper. Copyright © 2016 Elsevier Ltd. All rights reserved.

UWB delay and multiply receiver

DOEpatents

Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

2013-09-10

An ultra-wideband (UWB) delay and multiply receiver is formed of a receive antenna; a variable gain attenuator connected to the receive antenna; a signal splitter connected to the variable gain attenuator; a multiplier having one input connected to an undelayed signal from the signal splitter and another input connected to a delayed signal from the signal splitter, the delay between the splitter signals being equal to the spacing between pulses from a transmitter whose pulses are being received by the receive antenna; a peak detection circuit connected to the output of the multiplier and connected to the variable gain attenuator to control the variable gain attenuator to maintain a constant amplitude output from the multiplier; and a digital output circuit connected to the output of the multiplier.

Exponential H(infinity) synchronization of general discrete-time chaotic neural networks with or without time delays.

PubMed

Qi, Donglian; Liu, Meiqin; Qiu, Meikang; Zhang, Senlin

2010-08-01

This brief studies exponential H(infinity) synchronization of a class of general discrete-time chaotic neural networks with external disturbance. On the basis of the drive-response concept and H(infinity) control theory, and using Lyapunov-Krasovskii (or Lyapunov) functional, state feedback controllers are established to not only guarantee exponential stable synchronization between two general chaotic neural networks with or without time delays, but also reduce the effect of external disturbance on the synchronization error to a minimal H(infinity) norm constraint. The proposed controllers can be obtained by solving the convex optimization problems represented by linear matrix inequalities. Most discrete-time chaotic systems with or without time delays, such as Hopfield neural networks, cellular neural networks, bidirectional associative memory networks, recurrent multilayer perceptrons, Cohen-Grossberg neural networks, Chua's circuits, etc., can be transformed into this general chaotic neural network to be H(infinity) synchronization controller designed in a unified way. Finally, some illustrated examples with their simulations have been utilized to demonstrate the effectiveness of the proposed methods.

Implement an adjustable delay time digital trigger for an NI data acquisition card in a high-speed demodulation system

NASA Astrophysics Data System (ADS)

Zhang, Hongtao; Fan, Lingling; Wang, Pengfei; Park, Seong-Wook

2012-06-01

A National Instruments (NI) DAQ card PCI 5105 is installed in a high-speed demodulation system based on Fiber Fabry-Pérot Tunable Filter. The instability of the spectra of Fiber Bragg Grating sensors caused by intrinsic drifts of FFP-TF needs an appropriate, flexible trigger. However, the driver of the DAQ card in the current development environment does not provide the functions of analog trigger but digital trigger type. Moreover, the high level of the trigger signal from the tuning voltage of FFP-TF is larger than the maximum input overload voltage of PCI 5105 card. To resolve this incompatibility, a novel converter to change an analog trigger signal into a digital trigger signal has been reported previously. However, the obvious delay time between input and output signals limits the function of demodulation system. Accordingly, we report an improved low-cost, small-size converter with an adjustable delay time. This new scheme can decline the delay time to or close to zero when the frequency of trigger signal is less than 3,000 Hz. This method might be employed to resolve similar problems or to be applied in semiconductor integrated circuits.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rivera-Durón, R. R., E-mail: roberto.rivera@ipicyt.edu.mx; Campos-Cantón, E., E-mail: eric.campos@ipicyt.edu.mx; Campos-Cantón, I.

We present the design of an autonomous time-delay Boolean network realized with readily available electronic components. Through simulations and experiments that account for the detailed nonlinear response of each circuit element, we demonstrate that a network with five Boolean nodes displays complex behavior. Furthermore, we show that the dynamics of two identical networks display near-instantaneous synchronization to a periodic state when forced by a common periodic Boolean signal. A theoretical analysis of the network reveals the conditions under which complex behavior is expected in an individual network and the occurrence of synchronization in the forced networks. This research will enablemore » future experiments on autonomous time-delay networks using readily available electronic components with dynamics on a slow enough time-scale so that inexpensive data collection systems can faithfully record the dynamics.« less

High-speed MCP anodes for high time resolution low-energy charged particle spectrometers

NASA Astrophysics Data System (ADS)

Saito, Yoshifumi; Yokota, Shoichiro; Asamura, Kazushi; Krieger, Amanda

2017-02-01

The time resolution of low-energy charged particle measurements is becoming higher and higher. In order to realize high time resolution measurements, a 1-D circular delay line anode has been developed as a high-speed microchannel plate (MCP) anode. The maximum count rate of the 1-D circular delay line anode is around 1 × 107/s/360°, which is much higher than the widely used resistive anode, whose maximum count rate is around 1 × 106/s/360°. In order to achieve much higher speeds, an MCP anode with application-specific integrated circuit (ASIC) has been developed. We have decided to adopt an anode configuration in which a discrete anode is formed on a ceramic substrate, and a bare ASIC chip is installed on the back of the ceramic. It has been found that the anode can detect at a high count rate of 2 × 108/s/360°. Developments in both delay line and discrete anodes, as well as readout electronics, will be reviewed.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

NASA Astrophysics Data System (ADS)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

The Role of the Medial Prefrontal Cortex in Trace Fear Extinction

ERIC Educational Resources Information Center

Kwapis, Janine L.; Jarome, Timothy J.; Helmstetter, Fred J.

2015-01-01

The extinction of delay fear conditioning relies on a neural circuit that has received much attention and is relatively well defined. Whether this established circuit also supports the extinction of more complex associations, however, is unclear. Trace fear conditioning is a better model of complex relational learning, yet the circuit that…

An advanced SEU tolerant latch based on error detection

NASA Astrophysics Data System (ADS)

Xu, Hui; Zhu, Jianwei; Lu, Xiaoping; Li, Jingzhao

2018-05-01

This paper proposes a latch that can mitigate SEUs via an error detection circuit. The error detection circuit is hardened by a C-element and a stacked PMOS. In the hold state, a particle strikes the latch or the error detection circuit may cause a fault logic state of the circuit. The error detection circuit can detect the upset node in the latch and the fault output will be corrected. The upset node in the error detection circuit can be corrected by the C-element. The power dissipation and propagation delay of the proposed latch are analyzed by HSPICE simulations. The proposed latch consumes about 77.5% less energy and 33.1% less propagation delay than the triple modular redundancy (TMR) latch. Simulation results demonstrate that the proposed latch can mitigate SEU effectively. Project supported by the National Natural Science Foundation of China (Nos. 61404001, 61306046), the Anhui Province University Natural Science Research Major Project (No. KJ2014ZD12), the Huainan Science and Technology Program (No. 2013A4011), and the National Natural Science Foundation of China (No. 61371025).

Design of replica bit line control circuit to optimize power for SRAM

NASA Astrophysics Data System (ADS)

Pengjun, Wang; Keji, Zhou; Huihong, Zhang; Daohui, Gong

2016-12-01

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002, 61474068), and the K. C. Wong Magna Fund in Ningbo University.

ELECTRICAL PULSE COUNTER APPARATUS

DOEpatents

Kaufman, W.M.; Jeeves, T.A.

1962-09-01

A progressive electrical pulse counter circuit rs designed for the counting of a chain of input pulses. The circuit employs a series of direct connected bistable counting stages simultaneously pulsed by each input pulse and a delay means connected between each of the stages. Each bistable stage has two d-c operative states, which stage, when in its initial state, prevents the next succeeding stage from changing its condition when the latter stage is pulsed. Since the delay circuits between the stages prevents the immediate decay of the d-c state of each stage when the stages are pulsed, only one stage will change its state for each input pulse, thereby providing progressive stage-by-stage counting. (AEC)

Superconducting Qubit (transmon) coupled to Surface Acoustic Waves (SAWs)

NASA Astrophysics Data System (ADS)

Guo, Lingzhen; Johansson, Göran

We work on a hybrid system, which couples the transmon in circuit QED to the propagating mechanical modes of Surface Acoustic Waves (SAWs). This is an analogue of circuit QED system but replacing the microwave photons by SAW phonons. We investigate the quantum dynamics of a single transmon qubit coupled to surface acoustic waves (SAWs) via two distant connection points. Since the acoustic speed is five orders of magnitude slower than the speed of light, the travelling time between the two connection points needs to be taken into account. Therefore, we treat the transmon qubit as a giant atom with a deterministic time delay. We find that the spontaneous emission of the system, formed by the giant atom and the SAWs between its connection points, initially follows a polynomial decay law instead of an exponential one, as would be the case for a small atom. We obtain exact analytical results for the scattering properties of the giant atom up to two-phonon processes by using a diagrammatic approach. The time delay gives rise to novel features in the reflection, transmission, power spectra, and second-order correlation functions of the system. We show that the giant atom can generate entangled phonon pairs, which may have applications in quantum communication. L.G. acknowledges financial support from Carl-Zeiss Stiftung (0563-2.8/508/2).

Delayed Maturation of Fast-Spiking Interneurons Is Rectified by Activation of the TrkB Receptor in the Mouse Model of Fragile X Syndrome

PubMed Central

Nomura, Toshihiro; Zhu, Yiwen; Remmers, Christine L.; Xu, Jian; Nicholson, Daniel A.

2017-01-01

Fragile X syndrome (FXS) is a neurodevelopmental disorder that is a leading cause of inherited intellectual disability, and the most common known cause of autism spectrum disorder. FXS is broadly characterized by sensory hypersensitivity and several developmental alterations in synaptic and circuit function have been uncovered in the sensory cortex of the mouse model of FXS (Fmr1 KO). GABA-mediated neurotransmission and fast-spiking (FS) GABAergic interneurons are central to cortical circuit development in the neonate. Here we demonstrate that there is a delay in the maturation of the intrinsic properties of FS interneurons in the sensory cortex, and a deficit in the formation of excitatory synaptic inputs on to these neurons in neonatal Fmr1 KO mice. Both these delays in neuronal and synaptic maturation were rectified by chronic administration of a TrkB receptor agonist. These results demonstrate that the maturation of the GABAergic circuit in the sensory cortex is altered during a critical developmental period due in part to a perturbation in BDNF-TrkB signaling, and could contribute to the alterations in cortical development underlying the sensory pathophysiology of FXS. SIGNIFICANCE STATEMENT Fragile X (FXS) individuals have a range of sensory related phenotypes, and there is growing evidence of alterations in neuronal circuits in the sensory cortex of the mouse model of FXS (Fmr1 KO). GABAergic interneurons are central to the correct formation of circuits during cortical critical periods. Here we demonstrate a delay in the maturation of the properties and synaptic connectivity of interneurons in Fmr1 KO mice during a critical period of cortical development. The delays both in cellular and synaptic maturation were rectified by administration of a TrkB receptor agonist, suggesting reduced BDNF-TrkB signaling as a contributing factor. These results provide evidence that the function of fast-spiking interneurons is disrupted due to a deficiency in neurotrophin signaling during early development in FXS. PMID:29038238

Timeliness and Delay in the Cook County Juvenile Court Child Protection Division. Discussion Paper CS-45.

ERIC Educational Resources Information Center

Merry, Sheila M.; Peters, Clark M.; Goerge, Robert M.; Osuch, Ruth; Minor, Maria; Budde, Stephen

This study suggests that court procedures in Illinois must improve to assure that more children are placed in permanent homes in a timely way. The University of Chicago's Chapin Hall Center for Children examined the timeliness of the Circuit Court of Cook County, Illinois' Child Protection Division in completing the sequence of hearings and…

Time-of-flight radio location system

DOEpatents

McEwan, T.E.

1996-04-23

A bi-static radar configuration measures the direct time-of-flight of a transmitted RF pulse and is capable of measuring this time-of-flight with a jitter on the order of about one pico-second, or about 0.01 inch of free space distance for an electromagnetic pulse over a range of about one to ten feet. A transmitter transmits a sequence of electromagnetic pulses in response to a transmit timing signal, and a receiver samples the sequence of electromagnetic pulses with controlled timing in response to a receive timing signal, and generates a sample signal in response to the samples. A timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The receive timing signal causes the receiver to sample the sequence of electromagnetic pulses such that the time between transmission of pulses in the sequence and sampling by the receiver sweeps over a range of delays. The receive timing signal sweeps over the range of delays in a sweep cycle such that pulses in the sequence are sampled at the pulse repetition rate, and with different delays in the range of delays to produce a sample signal representing magnitude of a received pulse in equivalent time. Automatic gain control circuitry in the receiver controls the magnitude of the equivalent time sample signal. A signal processor analyzes the sample signal to indicate the time-of-flight of the electromagnetic pulses in the sequence. 7 figs.

Time-of-flight radio location system

DOEpatents

McEwan, Thomas E.

1996-01-01

A bi-static radar configuration measures the direct time-of-flight of a transmitted RF pulse and is capable of measuring this time-of-flight with a jitter on the order of about one pico-second, or about 0.01 inch of free space distance for an electromagnetic pulse over a range of about one to ten feet. A transmitter transmits a sequence of electromagnetic pulses in response to a transmit timing signal, and a receiver samples the sequence of electromagnetic pulses with controlled timing in response to a receive timing signal, and generates a sample signal in response to the samples. A timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The receive timing signal causes the receiver to sample the sequence of electromagnetic pulses such that the time between transmission of pulses in the sequence and sampling by the receiver sweeps over a range of delays. The receive timing signal sweeps over the range of delays in a sweep cycle such that pulses in the sequence are sampled at the pulse repetition rate, and with different delays in the range of delays to produce a sample signal representing magnitude of a received pulse in equivalent time. Automatic gain control circuitry in the receiver controls the magnitude of the equivalent time sample signal. A signal processor analyzes the sample signal to indicate the time-of-flight of the electromagnetic pulses in the sequence.

Bit error rate tester using fast parallel generation of linear recurring sequences

DOEpatents

Pierson, Lyndon G.; Witzke, Edward L.; Maestas, Joseph H.

2003-05-06

A fast method for generating linear recurring sequences by parallel linear recurring sequence generators (LRSGs) with a feedback circuit optimized to balance minimum propagation delay against maximal sequence period. Parallel generation of linear recurring sequences requires decimating the sequence (creating small contiguous sections of the sequence in each LRSG). A companion matrix form is selected depending on whether the LFSR is right-shifting or left-shifting. The companion matrix is completed by selecting a primitive irreducible polynomial with 1's most closely grouped in a corner of the companion matrix. A decimation matrix is created by raising the companion matrix to the (n*k).sup.th power, where k is the number of parallel LRSGs and n is the number of bits to be generated at a time by each LRSG. Companion matrices with 1's closely grouped in a corner will yield sparse decimation matrices. A feedback circuit comprised of XOR logic gates implements the decimation matrix in hardware. Sparse decimation matrices can be implemented with minimum number of XOR gates, and therefore a minimum propagation delay through the feedback circuit. The LRSG of the invention is particularly well suited to use as a bit error rate tester on high speed communication lines because it permits the receiver to synchronize to the transmitted pattern within 2n bits.

Digital coincidence counting

NASA Astrophysics Data System (ADS)

Buckman, S. M.; Ius, D.

1996-02-01

This paper reports on the development of a digital coincidence-counting system which comprises a custom-built data acquisition card and associated PC software. The system has been designed to digitise the pulse-trains from two radiation detectors at a rate of 20 MSamples/s with 12-bit resolution. Through hardware compression of the data, the system can continuously record both individual pulse-shapes and the time intervals between pulses. Software-based circuits are used to process the stored pulse trains. These circuits are constructed simply by linking together icons representing various components such as coincidence mixers, time delays, single-channel analysers, deadtimes and scalers. This system enables a pair of pulse trains to be processed repeatedly using any number of different methods. Some preliminary results are presented in order to demonstrate the versatility and efficiency of this new method.

Pulse advancement and delay in an integrated-optical two-port ring-resonator circuit: direct experimental observations.

PubMed

Uranus, H P; Zhuang, L; Roeloffzen, C G H; Hoekstra, H J W M

2007-09-01

We report experimental observations of the negative-group-velocity (v(g)) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v(g) is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v(g), the situation is the other way around. We observed that a pulse splitting phenomenon occurs in the neighborhood of the critical-coupling point. This pulse splitting limits the maximum achievable delay and advancement of a single device as well as facilitating a smooth transition from highly advanced to highly delayed pulse, and vice versa, across the critical-coupling point.

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

NASA Technical Reports Server (NTRS)

Kaplan, Steven B.; Pylov, Sergey V.; Pambianchi, Michael

2003-01-01

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Phase coded, micro-power impulse radar motion sensor

DOEpatents

McEwan, Thomas E.

1996-01-01

A motion sensing, micro-power impulse radar MIR impresses on the transmitted signal, or the received pulse timing signal, one or more frequencies lower than the pulse repetition frequency, that become intermediate frequencies in a "IF homodyne" receiver. Thus, many advantages of classical RF receivers can be thereby be realized with ultra-wide band radar. The sensor includes a transmitter which transmits a sequence of electromagnetic pulses in response to a transmit timing signal at a nominal pulse repetition frequency. A receiver samples echoes of the sequence of electromagnetic pulses from objects within the field with controlled timing, in response to a receive timing signal, and generates a sample signal in response to the samples. A timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The relative timing of the transmit timing signal and the receive timing signal is modulated between a first relative delay and a second relative delay at an intermediate frequency, causing the receiver to sample the echoes such that the time between transmissions of pulses in the sequence and samples by the receiver is modulated at the intermediate frequency. Modulation may be executed by modulating the pulse repetition frequency which drives the transmitter, by modulating the delay circuitry which controls the relative timing of the sample strobe, or by modulating amplitude of the transmitted pulses. The electromagnetic pulses will have a nominal center frequency related to pulse width, and the first relative delay and the second relative delay between which the timing signals are modulated, differ by less than the nominal pulse width, and preferably by about one-quarter wavelength at the nominal center frequency of the transmitted pulses.

Phase coded, micro-power impulse radar motion sensor

DOEpatents

McEwan, T.E.

1996-05-21

A motion sensing, micro-power impulse radar MIR impresses on the transmitted signal, or the received pulse timing signal, one or more frequencies lower than the pulse repetition frequency, that become intermediate frequencies in a ``IF homodyne`` receiver. Thus, many advantages of classical RF receivers can be thereby be realized with ultra-wide band radar. The sensor includes a transmitter which transmits a sequence of electromagnetic pulses in response to a transmit timing signal at a nominal pulse repetition frequency. A receiver samples echoes of the sequence of electromagnetic pulses from objects within the field with controlled timing, in response to a receive timing signal, and generates a sample signal in response to the samples. A timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The relative timing of the transmit timing signal and the receive timing signal is modulated between a first relative delay and a second relative delay at an intermediate frequency, causing the receiver to sample the echoes such that the time between transmissions of pulses in the sequence and samples by the receiver is modulated at the intermediate frequency. Modulation may be executed by modulating the pulse repetition frequency which drives the transmitter, by modulating the delay circuitry which controls the relative timing of the sample strobe, or by modulating amplitude of the transmitted pulses. The electromagnetic pulses will have a nominal center frequency related to pulse width, and the first relative delay and the second relative delay between which the timing signals are modulated, differ by less than the nominal pulse width, and preferably by about one-quarter wavelength at the nominal center frequency of the transmitted pulses. 5 figs.

Effect of the RC time on photocurrent transients and determination of charge carrier mobilities

NASA Astrophysics Data System (ADS)

Kniepert, Juliane; Neher, Dieter

2017-11-01

We present a closed analytical model to describe time dependent photocurrents upon pulsed illumination in the presence of an external RC circuit. In combination with numerical drift diffusion simulations, it is shown that the RC time has a severe influence on the shape of the transients. In particular, the maximum of the photocurrent is delayed due to a delayed recharging of the electrodes. This delay increases with the increasing RC constant. As a consequence, charge carrier mobilities determined from simple extrapolation of the initial photocurrent decay will be in general too small and feature a false dependence on the electric field. Here, we present a recipe to correct charge carrier mobilities determined from measured photocurrent transients by taking into account the RC time of the experimental set-up. We also demonstrate how the model can be used to more reliably determine the charge carrier mobility from experimental data of a typical polymer/fullerene organic solar cell. It is shown that further aspects like a finite rising time of the pulse generator and the current contribution of the slower charger carriers influence the shape of the transients and may lead to an additional underestimation of the transit time.

Multifrequency zero-jitter delay-locked loop

NASA Astrophysics Data System (ADS)

Efendovich, Avner; Afek, Yachin; Sella, Coby; Bikowsky, Zeev

1994-01-01

The approach of an all-digital phase locked loop is used in this delay-locked loop circuit. This design is designated to a system with two processing units, a master CPU and a slave system chip, that share the same bus. It allows maximum utilization of the bus, as the minimal skew between the clocks of the two components significantly reduces idle periods, and also set-up and hold times. Changes in the operating frequency are possible, without falling out of synchronization. Due to the special lead-lag phase detector, the jitter of the clock is zero, when the loop is locked, under any working conditions.

Nanosecond monolithic CMOS readout cell

DOEpatents

Souchkov, Vitali V.

2004-08-24

A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

78 FR 8675 - Self-Regulatory Organizations; International Securities Exchange, LLC; Notice of Filing and...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

... Proposed Rule Change to Amend ISE Rule 2102 to Extend the Market-Wide Circuit Breaker Pilot Program January...- wide circuit breaker on a pilot basis for a period that corresponds to the pilot period for the LULD... delay the operative date of the market-wide circuit breaker pilot to April 8, 2013 in order for the...

78 FR 8666 - Self-Regulatory Organizations; The NASDAQ Stock Market LLC; Notice of Filing and Immediate...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-06

... adopted the proposed changes to the market-wide circuit breakers on a pilot basis for a period that... to April 8, 2013. The proposal would delay the operative date of the market-wide circuit breaker pilot to April 8, 2013 in order for the implementation date for the market-wide circuit breaker pilot...

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, A.D.; Haigh, R.E.; Hugenberg, K.F.

1995-09-26

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place. 7 figs.

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, Alan D.; Haigh, Ronald E.; Hugenberg, Keith F.

1995-01-01

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place.

Introduction to Focus Issue: Time-delay dynamics

NASA Astrophysics Data System (ADS)

Erneux, Thomas; Javaloyes, Julien; Wolfrum, Matthias; Yanchuk, Serhiy

2017-11-01

The field of dynamical systems with time delay is an active research area that connects practically all scientific disciplines including mathematics, physics, engineering, biology, neuroscience, physiology, economics, and many others. This Focus Issue brings together contributions from both experimental and theoretical groups and emphasizes a large variety of applications. In particular, lasers and optoelectronic oscillators subject to time-delayed feedbacks have been explored by several authors for their specific dynamical output, but also because they are ideal test-beds for experimental studies of delay induced phenomena. Topics include the control of cavity solitons, as light spots in spatially extended systems, new devices for chaos communication or random number generation, higher order locking phenomena between delay and laser oscillation period, and systematic bifurcation studies of mode-locked laser systems. Moreover, two original theoretical approaches are explored for the so-called Low Frequency Fluctuations, a particular chaotical regime in laser output which has attracted a lot of interest for more than 30 years. Current hot problems such as the synchronization properties of networks of delay-coupled units, novel stabilization techniques, and the large delay limit of a delay differential equation are also addressed in this special issue. In addition, analytical and numerical tools for bifurcation problems with or without noise and two reviews on concrete questions are proposed. The first review deals with the rich dynamics of simple delay climate models for El Nino Southern Oscillations, and the second review concentrates on neuromorphic photonic circuits where optical elements are used to emulate spiking neurons. Finally, two interesting biological problems are considered in this Focus Issue, namely, multi-strain epidemic models and the interaction of glucose and insulin for more effective treatment.

Lag Synchronization of Switched Neural Networks via Neural Activation Function and Applications in Image Encryption.

PubMed

Wen, Shiping; Zeng, Zhigang; Huang, Tingwen; Meng, Qinggang; Yao, Wei

2015-07-01

This paper investigates the problem of global exponential lag synchronization of a class of switched neural networks with time-varying delays via neural activation function and applications in image encryption. The controller is dependent on the output of the system in the case of packed circuits, since it is hard to measure the inner state of the circuits. Thus, it is critical to design the controller based on the neuron activation function. Comparing the results, in this paper, with the existing ones shows that we improve and generalize the results derived in the previous literature. Several examples are also given to illustrate the effectiveness and potential applications in image encryption.

An efficient current-based logic cell model for crosstalk delay analysis

NASA Astrophysics Data System (ADS)

Nazarian, Shahin; Das, Debasish

2013-04-01

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.

Application of Signal Analysis to the Climate

PubMed Central

2014-01-01

The primary ingredient of the Anthropogenic Global Warming hypothesis, namely, the assumption that additional atmospheric carbon dioxide substantially raises the global temperature, is studied. This is done by looking at the data of temperature and CO2, both in the time domain and in the phase domain of periodic data. Bicentenary measurements are analyzed and a relaxation model is introduced in the form of an electronic equivalent circuit. The effects of this relaxation manifest themselves in delays in the time domain and correlated phase shifts in the phase domain. For extremely long relaxation time constants, the delay is maximally one-quarter period, which for the yearly-periodic signal means 3 months. This is not in line with the analyzed data, the latter showing delays of 9 (−3) months. These results indicate a reverse function of cause and effect, with temperature being the cause for atmospheric CO2 changes, rather than their effect. These two hypotheses are discussed on basis of literature, where it was also reported that CO2 variations are lagging behind temperature variations. PMID:27350978

Mechanisms for Adjusting Interaural Time Differences to Achieve Binaural Coincidence Detection

PubMed Central

Seidl, Armin H.; Rubel, Edwin W; Harris, David M.

2010-01-01

Understanding binaural perception requires detailed analyses of the neural circuitry responsible for the computation of interaural time differences (ITDs). In the avian brainstem, this circuit consists of internal axonal delay lines innervating an array of coincidence detector neurons that encode external ITDs. Nucleus magnocellularis (NM) neurons project to the dorsal dendritic field of the ipsilateral nucleus laminaris (NL) and to the ventral field of the contralateral NL. Contralateral-projecting axons form a delay line system along a band of NL neurons. Binaural acoustic signals in the form of phase-locked action potentials from NM cells arrive at NL and establish a topographic map of sound source location along the azimuth. These pathways are assumed to represent a circuit similar to the Jeffress model of sound localization, establishing a place code along an isofrequency contour of NL. Three-dimensional measurements of axon lengths reveal major discrepancies with the current model; the temporal offset based on conduction length alone makes encoding of physiological ITDs impossible. However, axon diameter and distances between Nodes of Ranvier also influence signal propagation times along an axon. Our measurements of these parameters reveal that diameter and internode distance can compensate for the temporal offset inferred from axon lengths alone. Together with other recent studies these unexpected results should inspire new thinking on the cellular biology, evolution and plasticity of the circuitry underlying low frequency sound localization in both birds and mammals. PMID:20053889

Dynamic bifurcation and strange nonchaos in a two-frequency parametrically driven nonlinear oscillator

NASA Astrophysics Data System (ADS)

Premraj, D.; Suresh, K.; Palanivel, J.; Thamilmaran, K.

2017-09-01

A periodically forced series LCR circuit with Chua's diode as a nonlinear element exhibits slow passage through Hopf bifurcation. This slow passage leads to a delay in the Hopf bifurcation. The delay in this bifurcation is a unique quantity and it can be predicted using various numerical analysis. We find that when an additional periodic force is added to the system, the delay in bifurcation becomes chaotic which leads to an unpredictability in bifurcation delay. Further, we study the bifurcation of the periodic delay to chaotic delay in the slow passage effect through strange nonchaotic delay. We also report the occurrence of strange nonchaotic dynamics while varying the parameter of the additional force included in the system. We observe that the system exhibits a hitherto unknown dynamical transition to a strange nonchaotic attractor. With the help of Lyapunov exponent, we explain the new transition to strange nonchaotic attractor and its mechanism is studied by making use of rational approximation theory. The birth of SNA has also been confirmed numerically, using Poincaré maps, phase sensitivity exponent, the distribution of finite-time Lyapunov exponents and singular continuous spectrum analysis.

Delayed in vitro development of Up states but normal network plasticity in Fragile X circuits.

PubMed

Motanis, Helen; Buonomano, Dean

2015-09-01

A broad range of neurophysiological phenotypes have been reported since the generation of the first mouse model of Fragile X syndrome (FXS). However, it remains unclear which phenotypes are causally related to the cognitive deficits associated with FXS. Indeed, because many of these phenotypes are known to be modulated by experience, a confounding factor in the interpretation of many studies is whether some phenotypes are an indirect consequence of abnormal development and experience. To help diminish this confound we first conducted an in vitro developmental study of spontaneous neural dynamics in cortical organotypic cultures. A significant developmental increase in network activity and Up states was observed in both wild-type and Fmr1(-/y) circuits, along with a specific developmental delay in the emergence of Up states in knockout circuits. To determine whether Up state regulation is generally impaired in FXS circuits, we examined Up state plasticity using chronic optogenetic stimulation. Wild-type and Fmr1(-/y) stimulated circuits exhibited a significant decrease in overall spontaneous activity including Up state frequency; however, no significant effect of genotype was observed. These results demonstrate that developmental delays characteristic of FXS are recapitulated during in vitro development, and that Up state abnormalities are probably a direct consequence of the disease, and not an indirect consequence of abnormal experience. However, the fact that Fmr1(-/y) circuits exhibited normal homeostatic modulation of Up states suggests that these plasticity mechanisms are largely intact, and that some of the previously reported plasticity deficits could reflect abnormal experience or the engagement of compensatory mechanisms. © 2015 Federation of European Neuroscience Societies and John Wiley & Sons Ltd.

Research on key technologies of LADAR echo signal simulator

NASA Astrophysics Data System (ADS)

Xu, Rui; Shi, Rui; Ye, Jiansen; Wang, Xin; Li, Zhuo

2015-10-01

LADAR echo signal simulator is one of the most significant components of hardware-in-the-loop (HWIL) simulation systems for LADAR, which is designed to simulate the LADAR return signal in laboratory conditions. The device can provide the laser echo signal of target and background for imaging LADAR systems to test whether it is of good performance. Some key technologies are investigated in this paper. Firstly, the 3D model of typical target is built, and transformed to the data of the target echo signal based on ranging equation and targets reflection characteristics. Then, system model and time series model of LADAR echo signal simulator are established. Some influential factors which could induce fixed delay error and random delay error on the simulated return signals are analyzed. In the simulation system, the signal propagating delay of circuits and the response time of pulsed lasers are belong to fixed delay error. The counting error of digital delay generator, the jitter of system clock and the desynchronized between trigger signal and clock signal are a part of random delay error. Furthermore, these system insertion delays are analyzed quantitatively, and the noisy data are obtained. The target echo signals are got by superimposing of the noisy data and the pure target echo signal. In order to overcome these disadvantageous factors, a method of adjusting the timing diagram of the simulation system is proposed. Finally, the simulated echo signals are processed by using a detection algorithm to complete the 3D model reconstruction of object. The simulation results reveal that the range resolution can be better than 8 cm.

Delayed Maturation of Fast-Spiking Interneurons Is Rectified by Activation of the TrkB Receptor in the Mouse Model of Fragile X Syndrome.

PubMed

Nomura, Toshihiro; Musial, Timothy F; Marshall, John J; Zhu, Yiwen; Remmers, Christine L; Xu, Jian; Nicholson, Daniel A; Contractor, Anis

2017-11-22

Fragile X syndrome (FXS) is a neurodevelopmental disorder that is a leading cause of inherited intellectual disability, and the most common known cause of autism spectrum disorder. FXS is broadly characterized by sensory hypersensitivity and several developmental alterations in synaptic and circuit function have been uncovered in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABA-mediated neurotransmission and fast-spiking (FS) GABAergic interneurons are central to cortical circuit development in the neonate. Here we demonstrate that there is a delay in the maturation of the intrinsic properties of FS interneurons in the sensory cortex, and a deficit in the formation of excitatory synaptic inputs on to these neurons in neonatal Fmr1 KO mice. Both these delays in neuronal and synaptic maturation were rectified by chronic administration of a TrkB receptor agonist. These results demonstrate that the maturation of the GABAergic circuit in the sensory cortex is altered during a critical developmental period due in part to a perturbation in BDNF-TrkB signaling, and could contribute to the alterations in cortical development underlying the sensory pathophysiology of FXS. SIGNIFICANCE STATEMENT Fragile X (FXS) individuals have a range of sensory related phenotypes, and there is growing evidence of alterations in neuronal circuits in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABAergic interneurons are central to the correct formation of circuits during cortical critical periods. Here we demonstrate a delay in the maturation of the properties and synaptic connectivity of interneurons in Fmr1 KO mice during a critical period of cortical development. The delays both in cellular and synaptic maturation were rectified by administration of a TrkB receptor agonist, suggesting reduced BDNF-TrkB signaling as a contributing factor. These results provide evidence that the function of fast-spiking interneurons is disrupted due to a deficiency in neurotrophin signaling during early development in FXS. Copyright © 2017 the authors 0270-6474/17/3711298-13$15.00/0.

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

NASA Astrophysics Data System (ADS)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

UWB multi-burst transmit driver for averaging receivers

DOEpatents

Dallum, Gregory E

2012-11-20

A multi-burst transmitter for ultra-wideband (UWB) communication systems generates a sequence of precisely spaced RF bursts from a single trigger event. There are two oscillators in the transmitter circuit, a gated burst rate oscillator and a gated RF burst or RF power output oscillator. The burst rate oscillator produces a relatively low frequency, i.e., MHz, square wave output for a selected transmit cycle, and drives the RF burst oscillator, which produces RF bursts of much higher frequency, i.e., GHz, during the transmit cycle. The frequency of the burst rate oscillator sets the spacing of the RF burst packets. The first oscillator output passes through a bias driver to the second oscillator. The bias driver conditions, e.g., level shifts, the signal from the first oscillator for input into the second oscillator, and also controls the length of each RF burst. A trigger pulse actuates a timing circuit, formed of a flip-flop and associated reset time delay circuit, that controls the operation of the first oscillator, i.e., how long it oscillates (which defines the transmit cycle).

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Development of True Time Delay Circuits

DTIC Science & Technology

2014-06-13

public release Distribution is unlimited DATA SHEET SKY65014-70LF: 0.1-7.0 GHz InGaP Cascadable Amplifier Applications • Wireless infrastructure: WLAN ...decoupling network out of band. For low frequency applications , R1 may be used to conveniently limit supply current on the Evaluation Board. The Evaluation...additional information, refer to the Skyworks Application Note, Solder Reflow Information, document number 200164. Care must be taken when attaching this

Neuronal responses to target onset in oculomotor and somatomotor parietal circuits differ markedly in a choice task.

PubMed

Kubanek, J; Wang, C; Snyder, L H

2013-11-01

We often look at and sometimes reach for visible targets. Looking at a target is fast and relatively easy. By comparison, reaching for an object is slower and is associated with a larger cost. We hypothesized that, as a result of these differences, abrupt visual onsets may drive the circuits involved in saccade planning more directly and with less intermediate regulation than the circuits involved in reach planning. To test this hypothesis, we recorded discharge activity of neurons in the parietal oculomotor system (area LIP) and in the parietal somatomotor system (area PRR) while monkeys performed a visually guided movement task and a choice task. We found that in the visually guided movement task LIP neurons show a prominent transient response to target onset. PRR neurons also show a transient response, although this response is reduced in amplitude, is delayed, and has a slower rise time compared with LIP. A more striking difference is observed in the choice task. The transient response of PRR neurons is almost completely abolished and replaced with a slow buildup of activity, while the LIP response is merely delayed and reduced in amplitude. Our findings suggest that the oculomotor system is more closely and obligatorily coupled to the visual system, whereas the somatomotor system operates in a more discriminating manner.

Light beam range finder

DOEpatents

McEwan, Thomas E.

1998-01-01

A "laser tape measure" for measuring distance which includes a transmitter such as a laser diode which transmits a sequence of electromagnetic pulses in response to a transmit timing signal. A receiver samples reflections from objects within the field of the sequence of visible electromagnetic pulses with controlled timing, in response to a receive timing signal. The receiver generates a sample signal in response to the samples which indicates distance to the object causing the reflections. The timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The receive timing signal causes the receiver to sample the reflection such that the time between transmission of pulses in the sequence in sampling by the receiver sweeps over a range of delays. The transmit timing signal causes the transmitter to transmit the sequence of electromagnetic pulses at a pulse repetition rate, and the received timing signal sweeps over the range of delays in a sweep cycle such that reflections are sampled at the pulse repetition rate and with different delays in the range of delays, such that the sample signal represents received reflections in equivalent time. The receiver according to one aspect of the invention includes an avalanche photodiode and a sampling gate coupled to the photodiode which is responsive to the received timing signal. The transmitter includes a laser diode which supplies a sequence of visible electromagnetic pulses. A bright spot projected on to the target clearly indicates the point that is being measured, and the user can read the range to that point with precision of better than 0.1%.

Light beam range finder

DOEpatents

McEwan, T.E.

1998-06-16

A ``laser tape measure`` for measuring distance is disclosed which includes a transmitter such as a laser diode which transmits a sequence of electromagnetic pulses in response to a transmit timing signal. A receiver samples reflections from objects within the field of the sequence of visible electromagnetic pulses with controlled timing, in response to a receive timing signal. The receiver generates a sample signal in response to the samples which indicates distance to the object causing the reflections. The timing circuit supplies the transmit timing signal to the transmitter and supplies the receive timing signal to the receiver. The receive timing signal causes the receiver to sample the reflection such that the time between transmission of pulses in the sequence in sampling by the receiver sweeps over a range of delays. The transmit timing signal causes the transmitter to transmit the sequence of electromagnetic pulses at a pulse repetition rate, and the received timing signal sweeps over the range of delays in a sweep cycle such that reflections are sampled at the pulse repetition rate and with different delays in the range of delays, such that the sample signal represents received reflections in equivalent time. The receiver according to one aspect of the invention includes an avalanche photodiode and a sampling gate coupled to the photodiode which is responsive to the received timing signal. The transmitter includes a laser diode which supplies a sequence of visible electromagnetic pulses. A bright spot projected on to the target clearly indicates the point that is being measured, and the user can read the range to that point with precision of better than 0.1%. 7 figs.

A SERIES OF SUPPRESSIVE SIGNALS WITHIN THE DROSOPHILA CIRCADIAN NEURAL CIRCUIT GENERATES SEQUENTIAL DAILY OUTPUTS

PubMed Central

Liang, Xitong; Holy, Timothy E; Taghert, Paul H

2017-01-01

Summary We studied the Drosophila circadian neural circuit using whole brain imaging in vivo. Five major groups of pacemaker neurons display synchronized molecular clocks, yet each exhibits a distinct phase of daily Ca2+ activation. Light and neuropeptide PDF from morning cells (s-LNv) together delay the phase of the evening (LNd) group by ~12 h; PDF alone delays the phase of the DN3 group, by ~17 h. Neuropeptide sNPF, released from s-LNv and LNd pacemakers, produces latenight Ca2+ activation in the DN1 group. The circuit also features negative feedback by PDF to truncate the s-LNv Ca2+ wave and terminate PDF release. Both PDF and sNPF suppress basal Ca2+ levels in target pacemakers with long durations by cell autonomous actions. Thus, light and neuropeptides act dynamically at distinct hubs of the circuit to produce multiple suppressive events that create the proper tempo and sequence of circadian pacemaker neuronal activities. PMID:28552314

Measuring Information-Transfer Delays

PubMed Central

Wibral, Michael; Pampu, Nicolae; Priesemann, Viola; Siebenhühner, Felix; Seiwert, Hannes; Lindner, Michael; Lizier, Joseph T.; Vicente, Raul

2013-01-01

In complex networks such as gene networks, traffic systems or brain circuits it is important to understand how long it takes for the different parts of the network to effectively influence one another. In the brain, for example, axonal delays between brain areas can amount to several tens of milliseconds, adding an intrinsic component to any timing-based processing of information. Inferring neural interaction delays is thus needed to interpret the information transfer revealed by any analysis of directed interactions across brain structures. However, a robust estimation of interaction delays from neural activity faces several challenges if modeling assumptions on interaction mechanisms are wrong or cannot be made. Here, we propose a robust estimator for neuronal interaction delays rooted in an information-theoretic framework, which allows a model-free exploration of interactions. In particular, we extend transfer entropy to account for delayed source-target interactions, while crucially retaining the conditioning on the embedded target state at the immediately previous time step. We prove that this particular extension is indeed guaranteed to identify interaction delays between two coupled systems and is the only relevant option in keeping with Wiener’s principle of causality. We demonstrate the performance of our approach in detecting interaction delays on finite data by numerical simulations of stochastic and deterministic processes, as well as on local field potential recordings. We also show the ability of the extended transfer entropy to detect the presence of multiple delays, as well as feedback loops. While evaluated on neuroscience data, we expect the estimator to be useful in other fields dealing with network dynamics. PMID:23468850

Real-time distributed scheduling algorithm for supporting QoS over WDM networks

NASA Astrophysics Data System (ADS)

Kam, Anthony C.; Siu, Kai-Yeung

1998-10-01

Most existing or proposed WDM networks employ circuit switching, typically with one session having exclusive use of one entire wavelength. Consequently they are not suitable for data applications involving bursty traffic patterns. The MIT AON Consortium has developed an all-optical LAN/MAN testbed which provides time-slotted WDM service and employs fast-tunable transceivers in each optical terminal. In this paper, we explore extensions of this service to achieve fine-grained statistical multiplexing with different virtual circuits time-sharing the wavelengths in a fair manner. In particular, we develop a real-time distributed protocol for best-effort traffic over this time-slotted WDM service with near-optical fairness and throughput characteristics. As an additional design feature, our protocol supports the allocation of guaranteed bandwidths to selected connections. This feature acts as a first step towards supporting integrated services and quality-of-service guarantees over WDM networks. To achieve high throughput, our approach is based on scheduling transmissions, as opposed to collision- based schemes. Our distributed protocol involves one MAN scheduler and several LAN schedulers (one per LAN) in a master-slave arrangement. Because of propagation delays and limits on control channel capacities, all schedulers are designed to work with partial, delayed traffic information. Our distributed protocol is of the `greedy' type to ensure fast execution in real-time in response to dynamic traffic changes. It employs a hybrid form of rate and credit control for resource allocation. We have performed extensive simulations, which show that our protocol allocates resources (transmitters, receivers, wavelengths) fairly with high throughput, and supports bandwidth guarantees.

Amplitude- and rise-time-compensated filters

DOEpatents

Nowlin, Charles H.

1984-01-01

An amplitude-compensated rise-time-compensated filter for a pulse time-of-occurrence (TOOC) measurement system is disclosed. The filter converts an input pulse, having the characteristics of random amplitudes and random, non-zero rise times, to a bipolar output pulse wherein the output pulse has a zero-crossing time that is independent of the rise time and amplitude of the input pulse. The filter differentiates the input pulse, along the linear leading edge of the input pulse, and subtracts therefrom a pulse fractionally proportional to the input pulse. The filter of the present invention can use discrete circuit components and avoids the use of delay lines.

Demonstration of optical computing logics based on binary decision diagram.

PubMed

Lin, Shiyun; Ishikawa, Yasuhiko; Wada, Kazumi

2012-01-16

Optical circuits are low power consumption and fast speed alternatives for the current information processing based on transistor circuits. However, because of no transistor function available in optics, the architecture for optical computing should be chosen that optics prefers. One of which is Binary Decision Diagram (BDD), where signal is processed by sending an optical signal from the root through a serial of switching nodes to the leaf (terminal). Speed of optical computing is limited by either transmission time of optical signals from the root to the leaf or switching time of a node. We have designed and experimentally demonstrated 1-bit and 2-bit adders based on the BDD architecture. The switching nodes are silicon ring resonators with a modulation depth of 10 dB and the states are changed by the plasma dispersion effect. The quality, Q of the rings designed is 1500, which allows fast transmission of signal, e.g., 1.3 ps calculated by a photon escaping time. A total processing time is thus analyzed to be ~9 ps for a 2-bit adder and would scales linearly with the number of bit. It is two orders of magnitude faster than the conventional CMOS circuitry, ~ns scale of delay. The presented results show the potential of fast speed optical computing circuits.

A twofold quantum delayed-choice experiment in a superconducting circuit

PubMed Central

Liu, Ke; Xu, Yuan; Wang, Weiting; Zheng, Shi-Biao; Roy, Tanay; Kundu, Suman; Chand, Madhavi; Ranadive, Arpit; Vijay, Rajamani; Song, Yipu; Duan, Luming; Sun, Luyan

2017-01-01

Wave-particle complementarity lies at the heart of quantum mechanics. To illustrate this mysterious feature, Wheeler proposed the delayed-choice experiment, where a quantum system manifests the wave- or particle-like attribute, depending on the experimental arrangement, which is made after the system has entered the interferometer. In recent quantum delayed-choice experiments, these two complementary behaviors were simultaneously observed with a quantum interferometer in a superposition of being closed and open. We suggest and implement a conceptually different quantum delayed-choice experiment by introducing a which-path detector (WPD) that can simultaneously record and neglect the system’s path information, but where the interferometer itself is classical. Our experiment is realized with a superconducting circuit, where a cavity acts as the WPD for an interfering qubit. Using this setup, we implement the first twofold delayed-choice experiment, which demonstrates that the system’s behavior depends not only on the measuring device’s configuration that can be chosen even after the system has been detected but also on whether we a posteriori erase or mark the which-path information, the latter of which cannot be revealed by previous quantum delayed-choice experiments. Our results represent the first demonstration of both counterintuitive features with the same experimental setup, significantly extending the concept of quantum delayed-choice experiment. PMID:28508079

A twofold quantum delayed-choice experiment in a superconducting circuit.

PubMed

Liu, Ke; Xu, Yuan; Wang, Weiting; Zheng, Shi-Biao; Roy, Tanay; Kundu, Suman; Chand, Madhavi; Ranadive, Arpit; Vijay, Rajamani; Song, Yipu; Duan, Luming; Sun, Luyan

2017-05-01

Wave-particle complementarity lies at the heart of quantum mechanics. To illustrate this mysterious feature, Wheeler proposed the delayed-choice experiment, where a quantum system manifests the wave- or particle-like attribute, depending on the experimental arrangement, which is made after the system has entered the interferometer. In recent quantum delayed-choice experiments, these two complementary behaviors were simultaneously observed with a quantum interferometer in a superposition of being closed and open. We suggest and implement a conceptually different quantum delayed-choice experiment by introducing a which-path detector (WPD) that can simultaneously record and neglect the system's path information, but where the interferometer itself is classical. Our experiment is realized with a superconducting circuit, where a cavity acts as the WPD for an interfering qubit. Using this setup, we implement the first twofold delayed-choice experiment, which demonstrates that the system's behavior depends not only on the measuring device's configuration that can be chosen even after the system has been detected but also on whether we a posteriori erase or mark the which-path information, the latter of which cannot be revealed by previous quantum delayed-choice experiments. Our results represent the first demonstration of both counterintuitive features with the same experimental setup, significantly extending the concept of quantum delayed-choice experiment.

Design of a delay-locked-loop-based time-to-digital converter

NASA Astrophysics Data System (ADS)

Zhaoxin, Ma; Xuefei, Bai; Lu, Huang

2013-09-01

A time-to-digital converter (TDC) based on a reset-free and anti-harmonic delay-locked loop (DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid “false locking". Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18 μm CMOS technology, and its core area occupies 0.7 × 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than ±0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

NASA Astrophysics Data System (ADS)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

PULSE SYNTHESIZING GENERATOR

DOEpatents

Kerns, Q.A.

1963-08-01

>An electronlc circuit for synthesizing electrical current pulses having very fast rise times includes several sinewave generators tuned to progressively higher harmonic frequencies with signal amplitudes and phases selectable according to the Fourier series of the waveform that is to be synthesized. Phase control is provided by periodically triggering the generators at precisely controlled times. The outputs of the generators are combined in a coaxial transmission line. Any frequency-dependent delays that occur in the transmission line can be readily compensated for so that the desired signal wave shape is obtained at the output of the line. (AEC)

Space shuttle main engine controller assembly, phase C-D. [with lagging system design and analysis

NASA Technical Reports Server (NTRS)

1973-01-01

System design and system analysis and simulation are slightly behind schedule, while design verification testing has improved. Input/output circuit design has improved, but digital computer unit (DCU) and mechanical design continue to lag. Part procurement was impacted by delays in printed circuit board, assembly drawing releases. These are the result of problems in generating suitable printed circuit artwork for the very complex and high density multilayer boards.

UWB transmitter

DOEpatents

Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

2013-01-15

An ultra-wideband (UWB) dual impulse transmitter is made up of a trigger edge selection circuit actuated by a single trigger input pulse; a first step recovery diode (SRD) based pulser connected to the trigger edge selection circuit to generate a first impulse output; and a second step recovery diode (SRD) based pulser connected to the trigger edge selection circuit in parallel to the first pulser to generate a second impulse output having a selected delay from the first impulse output.

High-precision two-way optic-fiber time transfer using an improved time code.

PubMed

Wu, Guiling; Hu, Liang; Zhang, Hao; Chen, Jianping

2014-11-01

We present a novel high-precision two-way optic-fiber time transfer scheme. The Inter-Range Instrumentation Group (IRIG-B) time code is modified by increasing bit rate and defining new fields. The modified time code can be transmitted directly using commercial optical transceivers and is able to efficiently suppress the effect of the Rayleigh backscattering in the optical fiber. A dedicated codec (encoder and decoder) with low delay fluctuation is developed. The synchronization issue is addressed by adopting a mask technique and combinational logic circuit. Its delay fluctuation is less than 27 ps in terms of the standard deviation. The two-way optic-fiber time transfer using the improved codec scheme is verified experimentally over 2 m to100 km fiber links. The results show that the stability over 100 km fiber link is always less than 35 ps with the minimum value of about 2 ps at the averaging time around 1000 s. The uncertainty of time difference induced by the chromatic dispersion over 100 km is less than 22 ps.

Extended Range Passive Wireless Tag System and Method

NASA Technical Reports Server (NTRS)

Fink, Patrick W. (Inventor); Lin, Gregory Y. (Inventor); Kennedy, Timothy F. (Inventor)

2013-01-01

A passive wireless tag assembly comprises a plurality of antennas and transmission lines interconnected with circuitry and constructed and arranged in a Van Atta array or configuration to reflect an interrogator signal in the direction from where it came. The circuitry may comprise at least one surface acoustic wave (SAW)-based circuit that functions as a signal reflector and is operatively connected with an information circuit. In another embodiment, at least one delay circuit and/or at least one passive modulation circuit(s) are utilized. In yet another embodiment, antennas connected to SAW-based devices are mounted to at least one of the orthogonal surfaces of a corner reflector.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Experimental demonstration of revival of oscillations from death in coupled nonlinear oscillators.

PubMed

Senthilkumar, D V; Suresh, K; Chandrasekar, V K; Zou, Wei; Dana, Syamal K; Kathamuthu, Thamilmaran; Kurths, Jürgen

2016-04-01

We experimentally demonstrate that a processing delay, a finite response time, in the coupling can revoke the stability of the stable steady states, thereby facilitating the revival of oscillations in the same parameter space where the coupled oscillators suffered the quenching of oscillation. This phenomenon of reviving of oscillations is demonstrated using two different prototype electronic circuits. Further, the analytical critical curves corroborate that the spread of the parameter space with stable steady state is diminished continuously by increasing the processing delay. Finally, the death state is completely wiped off above a threshold value by switching the stability of the stable steady state to retrieve sustained oscillations in the same parameter space. The underlying dynamical mechanism responsible for the decrease in the spread of the stable steady states and the eventual reviving of oscillation as a function of the processing delay is explained using analytical results.

O(t-α)-synchronization and Mittag-Leffler synchronization for the fractional-order memristive neural networks with delays and discontinuous neuron activations.

PubMed

Chen, Jiejie; Chen, Boshan; Zeng, Zhigang

2018-04-01

This paper investigates O(t -α )-synchronization and adaptive Mittag-Leffler synchronization for the fractional-order memristive neural networks with delays and discontinuous neuron activations. Firstly, based on the framework of Filippov solution and differential inclusion theory, using a Razumikhin-type method, some sufficient conditions ensuring the global O(t -α )-synchronization of considered networks are established via a linear-type discontinuous control. Next, a new fractional differential inequality is established and two new discontinuous adaptive controller is designed to achieve Mittag-Leffler synchronization between the drive system and the response systems using this inequality. Finally, two numerical simulations are given to show the effectiveness of the theoretical results. Our approach and theoretical results have a leading significance in the design of synchronized fractional-order memristive neural networks circuits involving discontinuous activations and time-varying delays. Copyright © 2018 Elsevier Ltd. All rights reserved.

Experimental demonstration of revival of oscillations from death in coupled nonlinear oscillators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Senthilkumar, D. V., E-mail: skumarusnld@gmail.com; Centre for Nonlinear Science and Engineering, School of Electrical and Electronics Engineering, SASTRA University, Thanjavur 613 401; Suresh, K.

We experimentally demonstrate that a processing delay, a finite response time, in the coupling can revoke the stability of the stable steady states, thereby facilitating the revival of oscillations in the same parameter space where the coupled oscillators suffered the quenching of oscillation. This phenomenon of reviving of oscillations is demonstrated using two different prototype electronic circuits. Further, the analytical critical curves corroborate that the spread of the parameter space with stable steady state is diminished continuously by increasing the processing delay. Finally, the death state is completely wiped off above a threshold value by switching the stability of themore » stable steady state to retrieve sustained oscillations in the same parameter space. The underlying dynamical mechanism responsible for the decrease in the spread of the stable steady states and the eventual reviving of oscillation as a function of the processing delay is explained using analytical results.« less

Intrinsic modulation of pulse-coupled integrate-and-fire neurons

NASA Astrophysics Data System (ADS)

Coombes, S.; Lord, G. J.

1997-11-01

Intrinsic neuromodulation is observed in sensory and neuromuscular circuits and in biological central pattern generators. We model a simple neuronal circuit with a system of two pulse-coupled integrate-and-fire neurons and explore the parameter regimes for periodic firing behavior. The inclusion of biologically realistic features shows that the speed and onset of neuronal response plays a crucial role in determining the firing phase for periodic rhythms. We explore the neurophysiological function of distributed delays arising from both the synaptic transmission process and dendritic structure as well as discrete delays associated with axonal communication delays. Bifurcation and stability diagrams are constructed with a mixture of simple analysis, numerical continuation and the Kuramoto phase-reduction technique. Moreover, we show that, for asynchronous behavior, the strength of electrical synapses can control the firing rate of the system.

A Low Power Linear Phase Programmable Long Delay Circuit.

PubMed

Rodriguez-Villegas, Esther; Logesparan, Lojini; Casson, Alexander J

2014-06-01

A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

CMOS time-to-digital converter based on a pulse-mixing scheme

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Liu, Keng-Chih; Chen, Guan-Hong

2014-11-01

This paper proposes a new pulse-mixing scheme utilizing both pulse-shrinking and pulse-stretching mechanisms to improve the performance of time-to-digital converters (TDCs). The temporal resolution of the conventional pulse-shrinking mechanism is determined by the size ratio between homogeneous and inhomogeneous elements. The proposed scheme which features double-stage operation derives its resolution according to the time difference between pulse-shrinking and pulse-stretching amounts. Thus, it can achieve greater immunity against temperature and ambient variations than that of the single-stage scheme. The circuit area also can be reduced by the proposed pulse-mixing scheme. In addition, this study proposes an improved cyclic delay line to eliminate the undesirable shift in the temporal resolution successfully. Therefore, the effective resolution can be controlled completely by the pulse-mixing unit to improve accuracy. The proposed TDC composed of only one cyclic delay line and one counter is fabricated in a TSMC CMOS 0.35-μm DPQM process. The chip core occupies an extremely small area of 0.02 mm2, which is the best among the related works. The experimental result shows that an effective resolution of around 53 ps within ±13% variation over a 0-100 °C temperature range is achieved. The power consumption is 90 μW at a sample rate of 1000 samples/s. In addition to the reduced area, the proposed TDC circuit achieves its resolution with less thermal-sensitivity and better fluctuations caused by process variations.

Tunable electromagnetically induced transparency in integrated silicon photonics circuit.

PubMed

Li, Ang; Bogaerts, Wim

2017-12-11

We comprehensively simulate and experimentally demonstrate a novel approach to generate tunable electromagnetically induced transparency (EIT) in a fully integrated silicon photonics circuit. It can also generate tunable fast and slow light. The circuit is a single ring resonator with two integrated tunable reflectors inside, which form an embedded Fabry-Perot (FP) cavity inside the ring cavity. The mode of the FP cavity can be controlled by tuning the reflections using integrated thermo-optic tuners. Under correct tuning conditions, the interaction of the FP mode and the ring resonance mode will generate a Fano resonance and an EIT response. The extinction ratio and bandwidth of the EIT can be tuned by controlling the reflectors. Measured group delay proves that both fast light and slow light can be generated under different tuning conditions. A maximum group delay of 1100 ps is observed because of EIT. Pulse advance around 1200 ps is also demonstrated.

Automatic control of clock duty cycle

NASA Technical Reports Server (NTRS)

Feng, Xiaoxin (Inventor); Roper, Weston (Inventor); Seefeldt, James D. (Inventor)

2010-01-01

In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

A fluidic diode, valves, and a sequential-loading circuit fabricated on layered paper.

PubMed

Chen, Hong; Cogswell, Jeremy; Anagnostopoulos, Constantine; Faghri, Mohammad

2012-08-21

Current microfluidic paper-based devices lack crucial components for fluid manipulation. We created a fluidic diode fabricated entirely on a single layer of paper to control the wicking of fluids. The fluidic diode is a two-terminal component that promotes or stops wicking along a paper channel. We further constructed a trigger and a delay valve based on the fluidic diode. Furthermore, we demonstrated a high-level functional circuit, consisting of a diode and a delay valve, to manipulate two fluids in a sequential manner. Our study provides new, transformative tools to manipulate fluid in microfluidic paper-based devices.

Dynamical Consequences of Bandpass Feedback Loops in a Bacterial Phosphorelay

PubMed Central

Sen, Shaunak; Garcia-Ojalvo, Jordi; Elowitz, Michael B.

2011-01-01

Under conditions of nutrient limitation, Bacillus subtilis cells terminally differentiate into a dormant spore state. Progression to sporulation is controlled by a genetic circuit consisting of a phosphorelay embedded in multiple transcriptional feedback loops, which is used to activate the master regulator Spo0A by phosphorylation. These transcriptional regulatory interactions are “bandpass”-like, in the sense that activation occurs within a limited band of Spo0A∼P concentrations. Additionally, recent results show that the phosphorelay activation occurs in pulses, in a cell-cycle dependent fashion. However, the impact of these pulsed bandpass interactions on the circuit dynamics preceding sporulation remains unclear. In order to address this question, we measured key features of the bandpass interactions at the single-cell level and analyzed them in the context of a simple mathematical model. The model predicted the emergence of a delayed phase shift between the pulsing activity of the different sporulation genes, as well as the existence of a stable state, with elevated Spo0A activity but no sporulation, embedded within the dynamical structure of the system. To test the model, we used time-lapse fluorescence microscopy to measure dynamics of single cells initiating sporulation. We observed the delayed phase shift emerging during the progression to sporulation, while a re-engineering of the sporulation circuit revealed behavior resembling the predicted additional state. These results show that periodically-driven bandpass feedback loops can give rise to complex dynamics in the progression towards sporulation. PMID:21980382

VHDL Simulation of the Implementation of a Costfunction Circuit.

DTIC Science & Technology

1990-09-01

the characteristic delays for each component. At this point in time, it is not necessary for the VHDL code to implement the exact hardware...NAVAL POSTGRADUATE SCHOOL Monterey, California AD-A240 430 ,DSTATv, OTIC"b El FCTE 9% SEP 16 1991 ru m D THESIS VHDL Simulation of the Implementation ...partition algorithm is used here as an example to test the VHDL design methodology. Subroutines or statements in the software can be implemented into

Extinguishing trace fear engages the retrosplenial cortex rather than the amygdala

PubMed Central

Kwapis, Janine L.; Jarome, Timothy J.; Lee, Jonathan L.; Gilmartin, Marieke R.; Helmstetter, Fred J.

2013-01-01

Extinction learning underlies the treatment for a variety of anxiety disorders. Most of what is known about the neurobiology of extinction is based on standard “delay” fear conditioning, in which awareness is not required for learning. Little is known about how complex, explicit associations extinguish, however. “Trace” conditioning is considered to be a rodent model of explicit fear because it relies on both the cortex and hippocampus and requires explicit contingency awareness in humans. Here, we explore the neural circuit supporting trace fear extinction in order to better understand how complex memories extinguish. We first show that the amygdala is selectively involved in delay fear extinction; blocking intra-amygdala glutamate receptors disrupted delay, but not trace extinction. Further, ERK phosphorylation was increased in the amygdala after delay, but not trace extinction. We then identify the retrosplenial cortex (RSC) as a key structure supporting trace extinction. ERK phosphorylation was selectively increased in the RSC following trace extinction and blocking intra-RSC NMDA receptors impaired trace, but not delay extinction. These findings indicate that delay and trace extinction require different neural circuits; delay extinction requires plasticity in the amygdala whereas trace extinction requires the RSC. Anxiety disorders linked to explicit memory may therefore depend on cortical processes that have not been traditionally targeted by extinction studies based on delay fear. PMID:24055593

Optically-switched submillimeter-wave oscillator and radiator having a switch-to-switch propagation delay

NASA Technical Reports Server (NTRS)

Spencer, Michael G. (Inventor); Maserjian, Joseph (Inventor)

1995-01-01

A submillimeter wave-generating integrated circuit includes an array of N photoconductive switches biased across a common voltage source and an optical path difference from a common optical pulse of repetition rate f sub 0 providing a different optical delay to each of the switches. In one embodiment, each incoming pulse is applied to successive ones of the N switches with successive delays. The N switches are spaced apart with a suitable switch-to-switch spacing so as to generate at the output load or antenna radiation of a submillimeter wave frequency f on the order of N f sub 0. Preferably, the optical pulse has a repetition rate of at least 10 GHz and N is of the order of 100, so that the circuit generates radiation of frequency of the order of or greater than 1 Terahertz.

β-Adrenoceptor Blockade in the Basolateral Amygdala, But Not the Medial Prefrontal Cortex, Rescues the Immediate Extinction Deficit.

PubMed

Giustino, Thomas F; Seemann, Jocelyn R; Acca, Gillian M; Goode, Travis D; Fitzgerald, Paul J; Maren, Stephen

2017-12-01

Early psychological interventions, such as exposure therapy, rely on extinction learning to reduce the development of stress- and trauma-related disorders. However, recent research suggests that extinction often fails to reduce fear when administered soon after trauma. This immediate extinction deficit (IED) may be due to stress-induced dysregulation of neural circuits involved in extinction learning. We have shown that systemic β-adrenoceptor blockade with propranolol rescues the IED, but impairs delayed extinction. Here we sought to determine the neural locus of these effects. Rats underwent auditory fear conditioning and then received either immediate (30 min) or delayed (24 h) extinction training. We used bilateral intracranial infusions of propranolol into either the infralimbic division of the medial prefrontal cortex (mPFC) or the basolateral amygdala (BLA) to examine the effects of β-adrenoceptor blockade on immediate and delayed extinction learning. Interestingly, intra-BLA, but not intra-mPFC, propranolol rescued the IED; animals receiving intra-BLA propranolol prior to immediate extinction showed less spontaneous recovery of fear during extinction retrieval. Importantly, this was not due to impaired consolidation of the conditioning memory. In contrast, neither intra-BLA nor intra-mPFC propranolol affected delayed extinction learning. Overall, these data contribute to a growing literature suggesting dissociable roles for key nodes in the fear extinction circuit depending on the timing of extinction relative to conditioning. These data also suggest that heightened noradrenergic activity in the BLA underlies stress-induced extinction deficits. Propranolol may be a useful adjunct to behavioral therapeutic interventions in recently traumatized individuals who are at risk for developing trauma-related disorders.

Damping Resonant Current in a Spark-Gap Trigger Circuit to Reduce Noise

DTIC Science & Technology

2009-06-01

DAMPING RESONANT CURRENT IN A SPARK- GAP TRIGGER CIRCUIT TO REDUCE NOISE E. L. Ruden Air Force Research Laboratory, Directed Energy Directorate, AFRL...REPORT TYPE N/A 3. DATES COVERED - 4. TITLE AND SUBTITLE Damping Resonant Current In A Spark- Gap Trigger Circuit To Reduce Noise 5a...thereby triggering 2 after delay 0, is 1. Each of the two rail- gaps (represented by 2) is trig- gered to close after the spark- gap (1) in the

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

PubMed

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

A megahertz-frequency tunable piecewise-linear electromechanical resonator realized via nonlinear feedback

NASA Astrophysics Data System (ADS)

Bajaj, Nikhil; Chiu, George T.-C.; Rhoads, Jeffrey F.

2018-07-01

Vibration-based sensing modalities traditionally have relied upon monitoring small shifts in natural frequency in order to detect structural changes (such as those in mass or stiffness). In contrast, bifurcation-based sensing schemes rely on the detection of a qualitative change in the behavior of a system as a parameter is varied. This can produce easy-to-detect changes in response amplitude with high sensitivity to structural change, but requires resonant devices with specific dynamic behavior which is not always easily reproduced. Desirable behavior for such devices can be produced reliably via nonlinear feedback circuitry, but has in past efforts been largely limited to sub-MHz operation, partially due to the time delay limitations present in certain nonlinear feedback circuits, such as multipliers. This work demonstrates the design and implementation of a piecewise-linear resonator realized via diode- and integrated circuit-based feedback electronics and a quartz crystal resonator. The proposed system is fabricated and characterized, and the creation and selective placement of the bifurcation points of the overall electromechanical system is demonstrated by tuning the circuit gains. The demonstrated circuit operates at 16 MHz. Preliminary modeling and analysis is presented that qualitatively agrees with the experimentally-observed behavior.

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

NASA Astrophysics Data System (ADS)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

An Inductorless Self-Controlled Rectifier for Piezoelectric Energy Harvesting

PubMed Central

Lu, Shaohua; Boussaid, Farid

2015-01-01

This paper presents a high-efficiency inductorless self-controlled rectifier for piezoelectric energy harvesting. High efficiency is achieved by discharging the piezoelectric device (PD) capacitance each time the current produced by the PD changes polarity. This is achieved automatically without the use of delay lines, thereby making the proposed circuit compatible with any type of PD. In addition, the proposed rectifier alleviates the need for an inductor, making it suitable for on-chip integration. Reported experimental results show that the proposed rectifier can harvest up to 3.9 times more energy than a full wave bridge rectifier. PMID:26610492

An Inductorless Self-Controlled Rectifier for Piezoelectric Energy Harvesting.

PubMed

Lu, Shaohua; Boussaid, Farid

2015-11-19

This paper presents a high-efficiency inductorless self-controlled rectifier for piezoelectric energy harvesting. High efficiency is achieved by discharging the piezoelectric device (PD) capacitance each time the current produced by the PD changes polarity. This is achieved automatically without the use of delay lines, thereby making the proposed circuit compatible with any type of PD. In addition, the proposed rectifier alleviates the need for an inductor, making it suitable for on-chip integration. Reported experimental results show that the proposed rectifier can harvest up to 3.9 times more energy than a full wave bridge rectifier.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Topics investigated include: measurements of transistor delay time; application of the infrared response technique to the study of radiation-damaged, lithium-drifted silicon detectors; and identification of a condition that minimizes wire flexure and reduces the failure rate of wire bonds in transistors and integrated circuits under slow thermal cycling conditions. Supplementary data concerning staff, standards committee activities, technical services, and publications are included as appendixes.

An Application Of High-Speed Photography To The Real Ignition Course Of Composite Propellants

NASA Astrophysics Data System (ADS)

Fusheng, Zhang; Gongshan, Cheng; Yong, Zhang; Fengchun, Li; Fanpei, Lei

1989-06-01

That the actual solid rocket motor behavior and delay time of the ignition of Ap/HTPB composite propellant ignited by high energy pyrotechics contained condensed particles have been investigated is the key of this paper. In experiments, using high speed camera, the pressure transducer, the photodiode and synchro circuit control system designed by us synchronistically observe and record all course and details of the ignition. And pressure signal, photodiode signal and high speed photography frame are corresponded one by one.

A finite state machine read-out chip for integrated surface acoustic wave sensors

NASA Astrophysics Data System (ADS)

Rakshit, Sambarta; Iliadis, Agis A.

2015-01-01

A finite state machine based integrated sensor circuit suitable for the read-out module of a monolithically integrated SAW sensor on Si is reported. The primary sensor closed loop consists of a voltage controlled oscillator (VCO), a peak detecting comparator, a finite state machine (FSM), and a monolithically integrated SAW sensor device. The output of the system oscillates within a narrow voltage range that correlates with the SAW pass-band response. The period of oscillation is of the order of the SAW phase delay. We use timing information from the FSM to convert SAW phase delay to an on-chip 10 bit digital output operating on the principle of time to digital conversion (TDC). The control inputs of this digital conversion block are generated by a second finite state machine operating under a divided system clock. The average output varies with changes in SAW center frequency, thus tracking mass sensing events in real time. Based on measured VCO gain of 16 MHz/V our system will convert a 10 kHz SAW frequency shift to a corresponding mean voltage shift of 0.7 mV. A corresponding shift in phase delay is converted to a one or two bit shift in the TDC output code. The system can handle alternate SAW center frequencies and group delays simply by adjusting the VCO control and TDC delay control inputs. Because of frequency to voltage and phase to digital conversion, this topology does not require external frequency counter setups and is uniquely suitable for full monolithic integration of autonomous sensor systems and tags.

Analog circuit for controlling acoustic transducer arrays

DOEpatents

Drumheller, Douglas S.

1991-01-01

A simplified ananlog circuit is presented for controlling electromechanical transducer pairs in an acoustic telemetry system. The analog circuit of this invention comprises a single electrical resistor which replaces all of the digital components in a known digital circuit. In accordance with this invention, a first transducer in a transducer pair of array is driven in series with the resistor. The voltage drop across this resistor is then amplified and used to drive the second transducer. The voltage drop across the resistor is proportional and in phase with the current to the transducer. This current is approximately 90 degrees out of phase with the driving voltage to the transducer. This phase shift replaces the digital delay required by the digital control circuit of the prior art.

Diffuse traumatic brain injury initially attenuates and later expands activation of the rat somatosensory whisker circuit concomitant with neuroplastic responses.

PubMed

Hall, Kelley D; Lifshitz, Jonathan

2010-04-06

Traumatic brain injury can initiate an array of chronic neurological deficits, effecting executive function, language and sensorimotor integration. Mechanical forces produce the diffuse pathology that disrupts neural circuit activation across vulnerable brain regions. The present manuscript explores the hypothesis that the extent of functional activation of brain-injured circuits is a consequence of initial disruption and consequent reorganization. In the rat, enduring sensory sensitivity to whisker stimulation directs regional analysis to the whisker barrel circuit. Adult, male rats were subjected to midline fluid percussion brain or sham injury and evaluated between 1day and 42days post-injury. Whisker somatosensory regions of the cortex and thalamus maintained cellular composition as visualized by Nissl stain. Within the first week post-injury, quantitatively less cFos activation was elicited by whisker stimulation, potentially due to axotomy within and surrounding the whisker circuit as visualized by amyloid precursor protein immunohistochemistry. Over six weeks post-injury, cFos activation after whisker stimulation showed a significant linear correlation with time in the cortex (r(2)=0.545; p=0.015), non-significant correlation in the thalamus (r(2)=0.326) and U-shaped correlation in the dentate gyrus (r(2)=0.831), all eventually exceeding sham levels. Ongoing neuroplastic responses in the cortex are evidenced by accumulating growth associated protein and synaptophysin gene expression. In the thalamus, the delayed restoration of plasticity markers may explain the broad distribution of neuronal activation extending into the striatum and hippocampus with whisker stimulation. The sprouting of diffuse-injured circuits into diffuse-injured tissue likely establishes maladaptive circuits responsible for behavioral morbidity. Therapeutic interventions to promote adaptive circuit restructuring may mitigate post-traumatic morbidity. Copyright 2010 Elsevier B.V. All rights reserved.

Low-power, high-speed 1-bit inexact Full Adder cell designs applicable to low-energy image processing

NASA Astrophysics Data System (ADS)

Zareei, Zahra; Navi, Keivan; Keshavarziyan, Peiman

2018-03-01

In this paper, three novel low-power and high-speed 1-bit inexact Full Adder cell designs are presented based on current mode logic in 32 nm carbon nanotube field effect transistor technology for the first time. The circuit-level figures of merits, i.e. power, delay and power-delay product as well as application-level metric such as error distance, are considered to assess the efficiency of the proposed cells over their counterparts. The effect of voltage scaling and temperature variation on the proposed cells is studied using HSPICE tool. Moreover, using MATLAB tool, the peak signal to noise ratio of the proposed cells is evaluated in an image-processing application referred to as motion detector. Simulation results confirm the efficiency of the proposed cells.

Controller Synthesis for Periodically Forced Chaotic Systems

NASA Astrophysics Data System (ADS)

Basso, Michele; Genesio, Roberto; Giovanardi, Lorenzo

Delayed feedback controllers are an appealing tool for stabilization of periodic orbits in chaotic systems. Despite their conceptual simplicity, specific and reliable design procedures are difficult to obtain, partly also because of their inherent infinite-dimensional structure. This chapter considers the use of finite dimensional linear time invariant controllers for stabilization of periodic solutions in a general class of sinusoidally forced nonlinear systems. For such controllers — which can be interpreted as rational approximations of the delayed ones — we provide a computationally attractive synthesis technique based on Linear Matrix Inequalities (LMIs), by mixing results concerning absolute stability of nonlinear systems and robustness of uncertain linear systems. The resulting controllers prove to be effective for chaos suppression in electronic circuits and systems, as shown by two different application examples.

Apparatus and method for defect testing of integrated circuits

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Synchronous Phase-Resolving Flash Range Imaging

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Hancock, Bruce

2007-01-01

An apparatus, now undergoing development, for range imaging based on measurement of the round-trip phase delay of a pulsed laser beam is described. The apparatus would operate in a staring mode. A pulsed laser would illuminate a target. Laser light reflected from the target would be imaged on a verylarge- scale integrated (VLSI)-circuit image detector, each pixel of which would contain a photodetector and a phase-measuring circuit. The round-trip travel time for the reflected laser light incident on each pixel, and thus the distance to the portion of the target imaged in that pixel, would be measured in terms of the phase difference between (1) the photodetector output pulse and (2) a local-oscillator signal that would have a frequency between 10 and 20 MHz and that would be synchronized with the laser-pulse-triggering signal.

Acute ethanol effects on neural encoding of reward size and delay in the nucleus accumbens

PubMed Central

Gutman, Andrea L.

2016-01-01

Acute ethanol administration can cause impulsivity, resulting in increased preference for immediately available rewards over delayed but more valuable alternatives. The manner in which reward size and delay are represented in neural firing is not fully understood, and very little is known about ethanol effects on this encoding. To address this issue, we used in vivo electrophysiology to characterize neural firing in the core of the nucleus accumbens (NAcc) in rats responding for rewards that varied in size or delay after vehicle or ethanol administration. The NAcc is a central element in the circuit that governs decision-making and importantly, promotes choice of delayed rewards. We found that NAcc firing in response to reward-predictive cues encoded anticipated reward value after vehicle administration, but ethanol administration disrupted this encoding, resulting in a loss of discrimination between immediate and delayed rewards in cue-evoked neural responses. In addition, NAcc firing occurring at the time of the operant response (lever pressing) was inversely correlated with behavioral response latency, such that increased firing rates were associated with decreased latencies to lever press. Ethanol administration selectively attenuated this lever press-evoked firing when delayed but not immediate rewards were expected. These effects on neural firing were accompanied by increased behavioral latencies to respond for delayed rewards. Our results suggest that ethanol effects on NAcc cue- and lever press-evoked encoding may contribute to ethanol-induced impulsivity. PMID:27169507

Effect of a Diagram on Primary Students' Understanding About Electric Circuits

NASA Astrophysics Data System (ADS)

Preston, Christine Margaret

2017-09-01

This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

Synergic solventing-out crystallization with subsequent time-delay thermal annealing of PbI2 precursor in mesostructured perovskite solar cells

NASA Astrophysics Data System (ADS)

Jia, Fujin; Guo, Yanqun; Che, Lijia; Liu, Zhiyong; Zeng, Zhigang; Cai, Chuanbing

2018-06-01

Although the two-step sequential deposition method provides an efficient route to fabricate high performance perovskite solar cells (PSSCs) with increasing reproducibility, the inefficient and incomplete conversion of PbI2 to perovskite is still quite a challenge. Following pioneering works, we found that the conversion process from PbI2 to perovskite mainly involves diffusion, infiltration, contact and reaction. In order to facilitate the conversion from PbI2 to perovskite, we demonstrate an effective method to regulate supersaturation level (the driving force to crystallization) of PbI2 by solventing-out crystallization combining with subsequent time-delay thermal annealing of PbI2 wet film. Enough voids and spaces in resulting porous PbI2 layer will be in favor of efficient diffusion, infiltration of CH3NH3I solution, and further enhance the contact and reaction between PbI2 and CH3NH3I in the whole film, leading to rapid, efficient and complete perovskite conversion with a conversion level of about 99.9%. Enhancement of light harvesting ranging from visible to near-IR region was achieved for the resultant high-quality perovskite. Upon this combined method, the fabricated mesostructured solar cells show tremendous power conversion efficiency (PCE) improvement from 3.2% to about 12.3% with less hysteresis owing to the simultaneous enhancement of short-circuit photocurrent density (J sc), open-circuit voltage (V oc) and fill factor (FF).

Instant provisioning of wavelength service using quasi-circuit optical burst switching

NASA Astrophysics Data System (ADS)

Xie, Hongyi; Li, Yanhe; Zheng, Xiaoping; Zhang, Hanyi

2006-09-01

Due to the recent outstanding advancement of optical networking technology, pervasive Grid computing will be a feasible option in the near future. As Grid infrastructure, optical networks must be able to handle different Grid traffic patterns with various traffic characteristics as well as different QoS requirements. With current optical switching technology, optical circuit switching is suitable for data-intensive Grid applications while optical burst switching is suitable to submit small Grid jobs. However, there would be high bandwidth short-lived traffic in some emerging Grid applications such as multimedia editing. This kind of traffic couldn't be well supported by both OCS and conventional OBS because of considerable path setup delay and bandwidth waste in OCS and inherent loss in OBS. Quasi-Circuit OBS (QCOBS) is proposed in this paper to address this challenge, providing one-way reserved, nearly lossless, instant provisioned wavelength service in OBS networks. Simulation results show that QCOBS achieves lossless transmission at low and moderate loads, and very low loss probability at high loads with proper guard time configuration.

A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

PubMed Central

Chen, Chun-Chi; Lin, Shih-Hao

2013-01-01

This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-μm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 μW at a sample rate of 10 samples/s. PMID:23385403

Quantized Synchronization of Chaotic Neural Networks With Scheduled Output Feedback Control.

PubMed

Wan, Ying; Cao, Jinde; Wen, Guanghui

In this paper, the synchronization problem of master-slave chaotic neural networks with remote sensors, quantization process, and communication time delays is investigated. The information communication channel between the master chaotic neural network and slave chaotic neural network consists of several remote sensors, with each sensor able to access only partial knowledge of output information of the master neural network. At each sampling instants, each sensor updates its own measurement and only one sensor is scheduled to transmit its latest information to the controller's side in order to update the control inputs for the slave neural network. Thus, such communication process and control strategy are much more energy-saving comparing with the traditional point-to-point scheme. Sufficient conditions for output feedback control gain matrix, allowable length of sampling intervals, and upper bound of network-induced delays are derived to ensure the quantized synchronization of master-slave chaotic neural networks. Lastly, Chua's circuit system and 4-D Hopfield neural network are simulated to validate the effectiveness of the main results.In this paper, the synchronization problem of master-slave chaotic neural networks with remote sensors, quantization process, and communication time delays is investigated. The information communication channel between the master chaotic neural network and slave chaotic neural network consists of several remote sensors, with each sensor able to access only partial knowledge of output information of the master neural network. At each sampling instants, each sensor updates its own measurement and only one sensor is scheduled to transmit its latest information to the controller's side in order to update the control inputs for the slave neural network. Thus, such communication process and control strategy are much more energy-saving comparing with the traditional point-to-point scheme. Sufficient conditions for output feedback control gain matrix, allowable length of sampling intervals, and upper bound of network-induced delays are derived to ensure the quantized synchronization of master-slave chaotic neural networks. Lastly, Chua's circuit system and 4-D Hopfield neural network are simulated to validate the effectiveness of the main results.

Feedforward and feedback inhibition in neostriatal GABAergic spiny neurons.

PubMed

Tepper, James M; Wilson, Charles J; Koós, Tibor

2008-08-01

There are two distinct inhibitory GABAergic circuits in the neostriatum. The feedforward circuit consists of a relatively small population of GABAergic interneurons that receives excitatory input from the neocortex and exerts monosynaptic inhibition onto striatal spiny projection neurons. The feedback circuit comprises the numerous spiny projection neurons and their interconnections via local axon collaterals. This network has long been assumed to provide the majority of striatal GABAergic inhibition and to sharpen and shape striatal output through lateral inhibition, producing increased activity in the most strongly excited spiny cells at the expense of their less strongly excited neighbors. Recent results, mostly from recording experiments of synaptically connected pairs of neurons, have revealed that the two GABAergic circuits differ markedly in terms of the total number of synapses made by each, the strength of the postsynaptic response detected at the soma, the extent of presynaptic convergence and divergence and the net effect of the activation of each circuit on the postsynaptic activity of the spiny neuron. These data have revealed that the feedforward inhibition is powerful and widespread, with spiking in a single interneuron being capable of significantly delaying or even blocking the generation of spikes in a large number of postsynaptic spiny neurons. In contrast, the postsynaptic effects of spiking in a single presynaptic spiny neuron on postsynaptic spiny neurons are weak when measured at the soma, and unable to significantly affect spike timing or generation. Further, reciprocity of synaptic connections between spiny neurons is only rarely observed. These results suggest that the bulk of the fast inhibition that has the strongest effects on spiny neuron spike timing comes from the feedforward interneuronal system whereas the axon collateral feedback system acts principally at the dendrites to control local excitability as well as the overall level of activity of the spiny neuron.

Efficient high-performance ultrasound beamforming using oversampling

NASA Astrophysics Data System (ADS)

Freeman, Steven R.; Quick, Marshall K.; Morin, Marc A.; Anderson, R. C.; Desilets, Charles S.; Linnenbrink, Thomas E.; O'Donnell, Matthew

1998-05-01

High-performance and efficient beamforming circuitry is very important in large channel count clinical ultrasound systems. Current state-of-the-art digital systems using multi-bit analog to digital converters (A/Ds) have matured to provide exquisite image quality with moderate levels of integration. A simplified oversampling beamforming architecture has been proposed that may a low integration of delta-sigma A/Ds onto the same chip as digital delay and processing circuitry to form a monolithic ultrasound beamformer. Such a beamformer may enable low-power handheld scanners for high-end systems with very large channel count arrays. This paper presents an oversampling beamformer architecture that generates high-quality images using very simple; digitization, delay, and summing circuits. Additional performance may be obtained with this oversampled system for narrow bandwidth excitations by mixing the RF signal down in frequency to a range where the electronic signal to nose ratio of the delta-sigma A/D is optimized. An oversampled transmit beamformer uses the same delay circuits as receive and eliminates the need for separate transmit function generators.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause tile voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Anticipated synchronization in neuronal circuits unveiled by a phase-response-curve analysis

NASA Astrophysics Data System (ADS)

Matias, Fernanda S.; Carelli, Pedro V.; Mirasso, Claudio R.; Copelli, Mauro

2017-05-01

Anticipated synchronization (AS) is a counterintuitive behavior that has been observed in several systems. When AS occurs in a sender-receiver configuration, the latter can predict the future dynamics of the former for certain parameter values. In particular, in neuroscience AS was proposed to explain the apparent discrepancy between information flow and time lag in the cortical activity recorded in monkeys. Despite its success, a clear understanding of the mechanisms yielding AS in neuronal circuits is still missing. Here we use the well-known phase-response-curve (PRC) approach to study the prototypical sender-receiver-interneuron neuronal motif. Our aim is to better understand how the transitions between delayed to anticipated synchronization and anticipated synchronization to phase-drift regimes occur. We construct a map based on the PRC method to predict the phase-locking regimes and their stability. We find that a PRC function of two variables, accounting simultaneously for the inputs from sender and interneuron into the receiver, is essential to reproduce the numerical results obtained using a Hodgkin-Huxley model for the neurons. On the contrary, the typical approximation that considers a sum of two independent single-variable PRCs fails for intermediate to high values of the inhibitory coupling strength of the interneuron. In particular, it loses the delayed-synchronization to anticipated-synchronization transition.

Laser beam pulse formatting method

DOEpatents

Daly, T.P.; Moses, E.I.; Patterson, R.W.; Sawicki, R.H.

1994-08-09

A method for formatting a laser beam pulse using one or more delay loops is disclosed. The delay loops have a partially reflective beam splitter and a plurality of highly reflective mirrors arranged such that the laser beam pulse enters into the delay loop through the beam splitter and circulates therein along a delay loop length defined by the mirrors. As the laser beam pulse circulates within the delay loop a portion thereof is emitted upon each completed circuit when the laser beam pulse strikes the beam splitter. The laser beam pulse is thereby formatted into a plurality of sub-pulses. The delay loops are used in combination to produce complex waveforms by combining the sub-pulses using additive waveform synthesis. 8 figs.

Theoretical analysis of cross-talking signals between counter-streaming electron beams in a vacuum tube oscillator

NASA Astrophysics Data System (ADS)

Shin, Y. M.; Ryskin, N. M.; Won, J. H.; Han, S. T.; Park, G. S.

2006-03-01

The basic theory of cross-talking signals between counter-streaming electron beams in a vacuum tube oscillator consisting of two two-cavity klystron amplifiers reversely coupled through input/output slots is theoretically investigated. Application of Kirchhoff's laws to the coupled equivalent RLC circuit model of the device provides four nonlinear coupled equations, which are the first-order time-delayed differential equations. Analytical solutions obtained through linearization of the equations provide oscillation frequencies and thresholds of four fundamental eigenstates, symmetric/antisymmetric 0/π modes. Time-dependent output signals are numerically analyzed with variation of the beam current, and a self-modulation mechanism and transition to chaos scenario are examined. The oscillator shows a much stronger multistability compared to a delayed feedback klystron oscillator owing to the competitions among more diverse eigenmodes. A fully developed chaos region also appears at a relatively lower beam current, ˜3.5Ist, compared to typical vacuum tube oscillators (10-100Ist), where Ist is a start-oscillation current.

Real-time cerebellar neuroprosthetic system based on a spiking neural network model of motor learning.

PubMed

Xu, Tao; Xiao, Na; Zhai, Xiaolong; Kwan Chan, Pak; Tin, Chung

2018-02-01

Damage to the brain, as a result of various medical conditions, impacts the everyday life of patients and there is still no complete cure to neurological disorders. Neuroprostheses that can functionally replace the damaged neural circuit have recently emerged as a possible solution to these problems. Here we describe the development of a real-time cerebellar neuroprosthetic system to substitute neural function in cerebellar circuitry for learning delay eyeblink conditioning (DEC). The system was empowered by a biologically realistic spiking neural network (SNN) model of the cerebellar neural circuit, which considers the neuronal population and anatomical connectivity of the network. The model simulated synaptic plasticity critical for learning DEC. This SNN model was carefully implemented on a field programmable gate array (FPGA) platform for real-time simulation. This hardware system was interfaced in in vivo experiments with anesthetized rats and it used neural spikes recorded online from the animal to learn and trigger conditioned eyeblink in the animal during training. This rat-FPGA hybrid system was able to process neuronal spikes in real-time with an embedded cerebellum model of ~10 000 neurons and reproduce learning of DEC with different inter-stimulus intervals. Our results validated that the system performance is physiologically relevant at both the neural (firing pattern) and behavioral (eyeblink pattern) levels. This integrated system provides the sufficient computation power for mimicking the cerebellar circuit in real-time. The system interacts with the biological system naturally at the spike level and can be generalized for including other neural components (neuron types and plasticity) and neural functions for potential neuroprosthetic applications.

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

NASA Technical Reports Server (NTRS)

Schuler, Robert L., Jr.; Wu, Qiong; Liu, Rui; Chen, Li; Madala, Shridhar

2014-01-01

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Frequency dependence of sensitivities in second-order RC active filters

NASA Astrophysics Data System (ADS)

Kunieda, T.; Hiramatsu, Y.; Fukui, A.

1980-02-01

This paper presents that gain and phase sensitivities to some element in biquadratic filters approximately constitute a circle on the complex sensitivity plane, provided that the quality factor Q of the circuit is appreciably larger than unity. Moreover, the group delay sensitivity is represented by the imaginary part of a cardioid. Using these results, bounds of maximum values of gain, phase, and group delay sensitivities are obtained. Further, it is proved that the maximum values of these sensitivities can be simultaneously minimized by minimizing the absolute value of the transfer function sensitivity at the center frequency provided that w(0)-sensitivities are constant and do not contain design parameters. Next, a statistical variability measure for the optimal-filter design is proposed. Finally, the relation between some variability measures proposed to the present time is made clear.

Efficient Hybrid Actuation Using Solid-State Actuators

NASA Technical Reports Server (NTRS)

Leo, Donald J.; Cudney, Harley H.; Horner, Garnett (Technical Monitor)

2001-01-01

Piezohydraulic actuation is the use of fluid to rectify the motion of a piezoelectric actuator for the purpose of overcoming the small stroke limitations of the material. In this work we study a closed piezohydraulic circuit that utilizes active valves to rectify the motion of a hydraulic end affector. A linear, lumped parameter model of the system is developed and correlated with experiments. Results demonstrate that the model accurately predicts the filtering of the piezoelectric motion caused by hydraulic compliance. Accurate results are also obtained for predicting the unidirectional motion of the cylinder when the active valves are phased with respect to the piezoelectric actuator. A time delay associated with the mechanical response of the valves is incorporated into the model to reflect the finite time required to open or close the valves. This time delay is found to be the primary limiting factor in achieving higher speed and greater power from the piezohydraulic unit. Experiments on the piezohydraulic unit demonstrate that blocked forces on the order of 100 N and unloaded velocities of 180 micrometers/sec are achieved.

Functional MRI and Multivariate Autoregressive Models

PubMed Central

Rogers, Baxter P.; Katwal, Santosh B.; Morgan, Victoria L.; Asplund, Christopher L.; Gore, John C.

2010-01-01

Connectivity refers to the relationships that exist between different regions of the brain. In the context of functional magnetic resonance imaging (fMRI), it implies a quantifiable relationship between hemodynamic signals from different regions. One aspect of this relationship is the existence of small timing differences in the signals in different regions. Delays of 100 ms or less may be measured with fMRI, and these may reflect important aspects of the manner in which brain circuits respond as well as the overall functional organization of the brain. The multivariate autoregressive time series model has features to recommend it for measuring these delays, and is straightforward to apply to hemodynamic data. In this review, we describe the current usage of the multivariate autoregressive model for fMRI, discuss the issues that arise when it is applied to hemodynamic time series, and consider several extensions. Connectivity measures like Granger causality that are based on the autoregressive model do not always reflect true neuronal connectivity; however, we conclude that careful experimental design could make this methodology quite useful in extending the information obtainable using fMRI. PMID:20444566

Averaging of phase noise in PSK signals by an opto-electrical feed-forward circuit

NASA Astrophysics Data System (ADS)

Inoue, K.; Ohta, M.

2013-10-01

This paper proposes an opto-electrical feed-forward circuit that reduces phase noise in binary PSK signals by averaging the noise. Random and independent phase noise is averaged over several bit slots by externally modulating a phase-fluctuating PSK signal with feed-forward signal obtained from signal processing of the outputs of delay interferometers. The simulation results demonstrate a reduction in the phase noise.

A CCD Monolithic LMS Adaptive Analog Signal Processor Integrated Circuit.

DTIC Science & Technology

1980-03-01

adaptive filter with electrically- reprogrammable MOS analog conductance weights. I The analog and digital peripheral MOS on-chip circuits are provided with...electrically reprogrammable analog weights at tap positions along a CCD analog delay line in order to form a basic linear combiner for adaptive filtering...electrically reprogrammable analog conductance weights was introduced with the use of non-volatile MNOS memory 6-7 transistors biased in their triode

Design and status of the RF-digitizer integrated circuit

NASA Technical Reports Server (NTRS)

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

NASA Astrophysics Data System (ADS)

Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernandez-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph

2015-11-01

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 μm × 10 μm using 6 NEM switches. Each NEM switch device has a footprint of 5 μm × 3 μm, an air gap of 60 μm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

NASA Technical Reports Server (NTRS)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Arya, Sandeep K.; Pandey, Sujata

2012-03-01

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

SpikingLab: modelling agents controlled by Spiking Neural Networks in Netlogo.

PubMed

Jimenez-Romero, Cristian; Johnson, Jeffrey

2017-01-01

The scientific interest attracted by Spiking Neural Networks (SNN) has lead to the development of tools for the simulation and study of neuronal dynamics ranging from phenomenological models to the more sophisticated and biologically accurate Hodgkin-and-Huxley-based and multi-compartmental models. However, despite the multiple features offered by neural modelling tools, their integration with environments for the simulation of robots and agents can be challenging and time consuming. The implementation of artificial neural circuits to control robots generally involves the following tasks: (1) understanding the simulation tools, (2) creating the neural circuit in the neural simulator, (3) linking the simulated neural circuit with the environment of the agent and (4) programming the appropriate interface in the robot or agent to use the neural controller. The accomplishment of the above-mentioned tasks can be challenging, especially for undergraduate students or novice researchers. This paper presents an alternative tool which facilitates the simulation of simple SNN circuits using the multi-agent simulation and the programming environment Netlogo (educational software that simplifies the study and experimentation of complex systems). The engine proposed and implemented in Netlogo for the simulation of a functional model of SNN is a simplification of integrate and fire (I&F) models. The characteristics of the engine (including neuronal dynamics, STDP learning and synaptic delay) are demonstrated through the implementation of an agent representing an artificial insect controlled by a simple neural circuit. The setup of the experiment and its outcomes are described in this work.

Regulatory heterochronies and loose temporal scaling between sea star and sea urchin regulatory circuits.

PubMed

Gildor, Tsvia; Hinman, Veronica; Ben-Tabou-De-Leon, Smadar

2017-01-01

It has long been argued that heterochrony, a change in relative timing of a developmental process, is a major source of evolutionary innovation. Heterochronic changes of regulatory gene activation could be the underlying molecular mechanism driving heterochronic changes through evolution. Here, we compare the temporal expression profiles of key regulatory circuits between sea urchin and sea star, representative of two classes of Echinoderms that shared a common ancestor about 500 million years ago. The morphologies of the sea urchin and sea star embryos are largely comparable, yet, differences in certain mesodermal cell types and ectodermal patterning result in distinct larval body plans. We generated high resolution temporal profiles of 17 mesodermally-, endodermally- and ectodermally-expressed regulatory genes in the sea star, Patiria miniata, and compared these to their orthologs in the Mediterranean sea urchin, Paracentrotus lividus. We found that the maternal to zygotic transition is delayed in the sea star compared to the sea urchin, in agreement with the longer cleavage stage in the sea star. Interestingly, the order of gene activation shows the highest variation in the relatively diverged mesodermal circuit, while the correlations of expression dynamics are the highest in the strongly conserved endodermal circuit. We detected loose scaling of the developmental rates of these species and observed interspecies heterochronies within all studied regulatory circuits. Thus, after 500 million years of parallel evolution, mild heterochronies between the species are frequently observed and the tight temporal scaling observed for closely related species no longer holds.

Réalisation de circuits intégrés I^2L à base de transistors bipolaires a double hétérojonction GaAlAs/GaAs

NASA Astrophysics Data System (ADS)

Vannel, J. P.; Camps, T.; Ferreira, A. S.; Tasselh, J.; Cazarré, A.; Marty, A.; Bailbé, J. P.

1991-04-01

GaAlAs/GaAs double heterojunction bipolar transistors (DHBT's) have a number of advantages for I^2L (integrated injection logic) high speed integrated circuits concerning the interchangeability between the emitter and the collector and a high design flexibility due to the use of two heterojunctions. We present the fabrication process of an I^2L integrated circuit including a frequency divider-by-two and a ring oscillator which presents a propagation delay time of 1.2 ns for a power consumption of 8 mW. Les transistors bipolaires à double hétérojonction GaAlAs/GaAs (TBDH) présentent de nombreux avantages pour leur application dans des circuits intégrés de logique I^2L (logique à injection intégrée), dont en particulier l'interchangeabilité entre émetteur et collecteur, et la liberté de conception résultant de l'utilisation de deux hétérojonctions. Dans ce cadre nous décrivons les principales étapes technologiques de fabrication d'un circuit intégré I^2L comportant un diviseur de fréquence par 2 et un oscillateur en anneau. Ce demier présente un temps de propagation de 1,2 ns pour une puissance dissipée de 8 mW.

The dual pathway model of AD/HD: an elaboration of neuro-developmental characteristics.

PubMed

Sonuga-Barke, Edmund J S

2003-11-01

The currently dominant neuro-cognitive model of Attention Deficit Hyperactivity Disorder (AD/HD) presents the condition as executive dysfunction (EDF) underpinned by disturbances in the fronto-dorsal striatal circuit and associated dopaminergic branches (e.g. meso-cortical). In contrast, motivationally-based accounts focus on altered reward processes and implicate fronto-ventral striatal reward circuits and those meso-limbic branches that terminate in the ventral striatum especially the nucleus accumbens. One such account, delay aversion (DEL), presents AD/HD as a motivational style-characterised by attempts to escape or avoid delay-arising from fundamental disturbances in these reward centres. While traditionally regarded as competing, EDF and DEL models have recently been presented as complimentary accounts of two psycho-patho-physiological subtypes of AD/HD with different developmental pathways, underpinned by different cortico-striatal circuits and modulated by different branches of the dopamine system. In the current paper we describe the development of this model in more detail. We elaborate on the neuro-circuitry possibly underpinning these two pathways and explore their developmental significance within a neuro-ecological framework.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Two stage kickdown control system for a motor vehicle automatic transmission

DOE Office of Scientific and Technical Information (OSTI.GOV)

Higashi, H.; Waki, K.; Fukuiri, M.

This patent describes a vehicle automatic transmission including a hydraulic torque converter and a transmission gear mechanism connected with the torque converter and having at least three gear stages of different gear ratios for forward drive. A principal feature of this system as described is a friction means for selecting one of the gear stages as well as a kickdown control means consisting of the first shift down circuit means for control of the friction means so that the transmission gear mechanism is shifted downward. A solenoid kick down means within the modality of the first shift down circuit andmore » a kick down switch means actuated by an engine control member when it is moved to a full power position provides control of the kick down solenoid and the effecting of a down shift. The shift down control means is composed of a second shift down circuit means for controlling the friction means so shift down occurs. The shift down solenoid contained in the second shift down circuit means in conjunction with a shift down switch actuated by engine control member movement to a position spaced a predetermined distance from the full power position control the shift down solenoid to effect a shift down. Thus this mechanism is actuated earlier than the kickdown switch means when the engine control member is moved toward the full power position. A time delay means from the time of actuation of the shift down switch means and controlling kickdown switch activation is also described.« less

Deconstructing the core dynamics from a complex time-lagged regulatory biological circuit.

PubMed

Eriksson, O; Brinne, B; Zhou, Y; Björkegren, J; Tegnér, J

2009-03-01

Complex regulatory dynamics is ubiquitous in molecular networks composed of genes and proteins. Recent progress in computational biology and its application to molecular data generate a growing number of complex networks. Yet, it has been difficult to understand the governing principles of these networks beyond graphical analysis or extensive numerical simulations. Here the authors exploit several simplifying biological circumstances which thereby enable to directly detect the underlying dynamical regularities driving periodic oscillations in a dynamical nonlinear computational model of a protein-protein network. System analysis is performed using the cell cycle, a mathematically well-described complex regulatory circuit driven by external signals. By introducing an explicit time delay and using a 'tearing-and-zooming' approach the authors reduce the system to a piecewise linear system with two variables that capture the dynamics of this complex network. A key step in the analysis is the identification of functional subsystems by identifying the relations between state-variables within the model. These functional subsystems are referred to as dynamical modules operating as sensitive switches in the original complex model. By using reduced mathematical representations of the subsystems the authors derive explicit conditions on how the cell cycle dynamics depends on system parameters, and can, for the first time, analyse and prove global conditions for system stability. The approach which includes utilising biological simplifying conditions, identification of dynamical modules and mathematical reduction of the model complexity may be applicable to other well-characterised biological regulatory circuits. [Includes supplementary material].

InGaAs/InP SPAD photon-counting module with auto-calibrated gate-width generation and remote control

NASA Astrophysics Data System (ADS)

Tosi, Alberto; Ruggeri, Alessandro; Bahgat Shehata, Andrea; Della Frera, Adriano; Scarcella, Carmelo; Tisa, Simone; Giudice, Andrea

2013-01-01

We present a photon-counting module based on InGaAs/InP SPAD (Single-Photon Avalanche Diode) for detecting single photons up to 1.7 μm. The module exploits a novel architecture for generating and calibrating the gate width, along with other functions (such as module supervision, counting and processing of detected photons, etc.). The gate width, i.e. the time interval when the SPAD is ON, is user-programmable in the range from 500 ps to 1.5 μs, by means of two different delay generation methods implemented with an FPGA (Field-Programmable Gate Array). In order to compensate chip-to-chip delay variation, an auto-calibration circuit picks out a combination of delays in order to match at best the selected gate width. The InGaAs/InP module accepts asynchronous and aperiodic signals and introduces very low timing jitter. Moreover the photon counting module provides other new features like a microprocessor for system supervision, a touch-screen for local user interface, and an Ethernet link for smart remote control. Thanks to the fullyprogrammable and configurable architecture, the overall instrument provides high system flexibility and can easily match all requirements set by many different applications requiring single photon-level sensitivity in the near infrared with very low photon timing jitter.

The influence of micro-vibration on space-borne Fourier transform spectrometers

NASA Astrophysics Data System (ADS)

Bai, Shaojun; Hou, Lizhou; Ke, Junyu

2014-11-01

The space-borne Fourier Transform Spectrometers (FTS) are widely used for atmospheric studies and planetary explorations. An adapted version of the classical Michelson interferometer have succeeded in several space missions, which utilized a rotating arm carrying a pair of cube corner retro-reflectors to produce a variable optical path difference (OPD), and a metrology laser source to generate the trigger signals. One characteristic of this kind of FTS is that it is highly sensitive to micro-vibration disturbances. However, a variety of mechanical disturbances are present as the satellite is in orbit, such as flying wheels, pointing mechanisms and cryocoolers. Therefore, this paper investigates the influence of micro-vibration on the space-borne FTS. Firstly, the interferogram of metrology laser under harmonic disturbances is analyzed. The results show that the zero crossings of interferogram shift periodically, and it gives rise to ghost lines in the retrieved spectra. The amplitudes of ghost lines increase rapidly with the increasing of micro-vibration levels. As to the system that employs the constant OPD sampling strategy, the effect of zero-crossing shifting is reduced significantly. Nevertheless, the time delays between the reference signal and the main signal acquisition are inevitable because of the electronic circuit. Thus, the effect of time delays on the interferogram and eventually on the spectra is simulated. The analysis suggests that the amplitudes of ghost line in spectra increase with the increasing of time delay intervals.

Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemicalmore » Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.« less

Ultra-Low Loss Waveguides with Application to Photonic Integrated Circuits

NASA Astrophysics Data System (ADS)

Bauters, Jared F.

The integration of photonic components using a planar platform promises advantages in cost, size, weight, and power consumption for optoelectronic systems. Yet, the typical propagation loss of 5-10 dB/m in a planar silica waveguide is nearly five orders-of-magnitude larger than that in low loss optical fibers. For some applications, the miniaturization of the photonic system and resulting smaller propagation lengths from integration are enough to overcome the increase in propagation loss. For other more demanding systems or applications, such as those requiring long optical time delays or high-quality-factor (Q factor) resonators, the high propagation loss can degrade system performance to a degree that trumps the potential advantages offered by integration. Thus, the reduction of planar waveguide propagation loss in a Si3-N4 based waveguide platform is a primary focus of this dissertation. The ultra-low loss stoichiometric Si3-N4 waveguide platform offers the additional advantages of fabrication process stability and repeatability. Yet, active devices such as lasers, amplifiers, and photodetectors have not been monolithically integrated with ultra-low loss waveguides due to the incompatibility of the active and ultra-low loss processing thermal budgets (ultra-low loss waveguides are annealed at temperatures exceeding 1000 °C in order to drive out impurities). So a platform that enables the integration of active devices with the ultra-low losses of the Si3- N4 waveguide platform is this dissertation's second focus. The work enables the future fabrication of sensor, gyroscope, true time delay, and low phase noise oscillator photonic integrated circuits.

Advanced active quenching circuit for ultra-fast quantum cryptography.

PubMed

Stipčević, Mario; Christensen, Bradley G; Kwiat, Paul G; Gauthier, Daniel J

2017-09-04

Commercial photon-counting modules based on actively quenched solid-state avalanche photodiode sensors are used in a wide variety of applications. Manufacturers characterize their detectors by specifying a small set of parameters, such as detection efficiency, dead time, dark counts rate, afterpulsing probability and single-photon arrival-time resolution (jitter). However, they usually do not specify the range of conditions over which these parameters are constant or present a sufficient description of the characterization process. In this work, we perform a few novel tests on two commercial detectors and identify an additional set of imperfections that must be specified to sufficiently characterize their behavior. These include rate-dependence of the dead time and jitter, detection delay shift, and "twilighting". We find that these additional non-ideal behaviors can lead to unexpected effects or strong deterioration of the performance of a system using these devices. We explain their origin by an in-depth analysis of the active quenching process. To mitigate the effects of these imperfections, a custom-built detection system is designed using a novel active quenching circuit. Its performance is compared against two commercial detectors in a fast quantum key distribution system with hyper-entangled photons and a random number generator.

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

PubMed

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

Carbon nanotube circuit integration up to sub-20 nm channel lengths.

PubMed

Shulaker, Max Marcel; Van Rethy, Jelle; Wu, Tony F; Liyanage, Luckshitha Suriyasena; Wei, Hai; Li, Zuanyi; Pop, Eric; Gielen, Georges; Wong, H-S Philip; Mitra, Subhasish

2014-04-22

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Synchronizing A Stroboscope With A Video Camera

NASA Technical Reports Server (NTRS)

Rhodes, David B.; Franke, John M.; Jones, Stephen B.; Dismond, Harriet R.

1993-01-01

Circuit synchronizes flash of light from stroboscope with frame and field periods of video camera. Sync stripper sends vertical-synchronization signal to delay generator, which generates trigger signal. Flashlamp power supply accepts delayed trigger signal and sends pulse of power to flash lamp. Designed for use in making short-exposure images that "freeze" flow in wind tunnel. Also used for making longer-exposure images obtained by use of continuous intense illumination.

Monolithic mm-wave phase shifter using optically activated superconducting switches

NASA Technical Reports Server (NTRS)

Romanofsky, Robert R. (Inventor); Bhasin, Kul B. (Inventor)

1992-01-01

A phase shifter is disclosed having a reference path and a delay path, light sources, and superconductive switches. Each of the superconductive switches is terminated in a virtual short circuit, which may be a radial stub. Switching between the reference path and delayed path is accomplished by illuminating the superconductive switches connected to the desired path, while not illuminating the superconductive switches connected to the other path.

Microwave evaluation of electromigration susceptibility in advanced interconnects

NASA Astrophysics Data System (ADS)

Sunday, Christopher E.; Veksler, Dmitry; Cheung, Kin C.; Obeng, Yaw S.

2017-11-01

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs.

SAMPLING OSCILLOSCOPE

DOEpatents

Sugarman, R.M.

1960-08-30

An oscilloscope is designed for displaying transient signal waveforms having random time and amplitude distributions. The oscilloscopc is a sampling device that selects for display a portion of only those waveforms having a particular range of amplitudes. For this purpose a pulse-height analyzer is provided to screen the pulses. A variable voltage-level shifter and a time-scale rampvoltage generator take the pulse height relative to the start of the waveform. The variable voltage shifter produces a voltage level raised one step for each sequential signal waveform to be sampled and this results in an unsmeared record of input signal waveforms. Appropriate delay devices permit each sample waveform to pass its peak amplitude before the circuit selects it for display.

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

NASA Technical Reports Server (NTRS)

Russinoff, David M.

1995-01-01

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Laser beam pulse formatting method

DOEpatents

Daly, Thomas P.; Moses, Edward I.; Patterson, Ralph W.; Sawicki, Richard H.

1994-01-01

A method for formatting a laser beam pulse (20) using one or more delay loops (10). The delay loops (10) have a partially reflective beam splitter (12) and a plurality of highly reflective mirrors (14) arranged such that the laser beam pulse (20) enters into the delay loop (10) through the beam splitter (12) and circulates therein along a delay loop length (24) defined by the mirrors (14). As the laser beam pulse (20) circulates within the delay loop (10) a portion thereof is emitted upon each completed circuit when the laser beam pulse (20) strikes the beam splitter (12). The laser beam pulse (20) is thereby formatted into a plurality of sub-pulses (50, 52, 54 and 56). The delay loops (10) are used in combination to produce complex waveforms by combining the sub-pulses (50, 52, 54 and 56) using additive waveform synthesis.

Reconfigurable all-optical NOT, XOR, and NOR logic gates based on two dimensional photonic crystals

NASA Astrophysics Data System (ADS)

Parandin, Fariborz; Malmir, M. Reza; Naseri, Mosayeb; Zahedi, Abdulhamid

2018-01-01

Photonic crystals can be considered as one of the most important basis for designing optical devices. In this research, using two-dimensional photonic crystals with triangular lattices, ultra-compact logic gates are designed and simulated. The intended structure has the capability to be used as three logical gates (NOT, XOR, and NOR). The designed structures not only have characteristics of small dimensions which make them suitable for integrated optical circuits, but also exhibit very low power transfer delay which makes it possible to design high speed gates. On comparison with the previous works, our simulations show that at a wavelength of 1.55 μm , the gates indicate a time delay of about 0.1 ps and the contrast ratio for the XOR gate is about 30 dB, i.e., the proposed structures are more applicable in designing low error optical logic gates.

Associative plasticity in intracortical inhibitory circuits in human motor cortex.

PubMed

Russmann, Heike; Lamy, Jean-Charles; Shamim, Ejaz A; Meunier, Sabine; Hallett, Mark

2009-06-01

Paired associative stimulation (PAS) is a transcranial magnetic stimulation technique inducing Hebbian-like synaptic plasticity in the human motor cortex (M1). PAS is produced by repetitive pairing of a peripheral nerve shock and a transcranial magnetic stimulus (TMS). Its effect is assessed by a change in size of a motor evoked response (MEP). MEP size results from excitatory and inhibitory influences exerted on cortical pyramidal cells, but no robust effects on inhibitory networks have been demonstrated so far. In 38 healthy volunteers, we assessed whether a PAS intervention influences three intracortical inhibitory circuits: short (SICI) and long (LICI) intracortical inhibitions reflecting activity of GABA(A) and GABA(B) interneurons, respectively, and long afferent inhibition (LAI) reflecting activity of somatosensory inputs. After PAS, MEP sizes, LICI and LAI levels were significantly changed while changes of SICI were inconsistent. The changes in LICI and LAI lasted 45 min after PAS. Their direction depended on the delay between the arrival time of the afferent volley at the cortex and the TMS-induced cortical activation during the PAS. PAS influences inhibitory circuits in M1. PAS paradigms can demonstrate Hebbian-like plasticity at selected inhibitory networks as well as excitatory networks.

Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron-beam direct writing technique

NASA Astrophysics Data System (ADS)

Aoyagi, Masahiro; Nakagawa, Hiroshi

1997-07-01

For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

Real-time cerebellar neuroprosthetic system based on a spiking neural network model of motor learning

NASA Astrophysics Data System (ADS)

Xu, Tao; Xiao, Na; Zhai, Xiaolong; Chan, Pak Kwan; Tin, Chung

2018-02-01

Objective. Damage to the brain, as a result of various medical conditions, impacts the everyday life of patients and there is still no complete cure to neurological disorders. Neuroprostheses that can functionally replace the damaged neural circuit have recently emerged as a possible solution to these problems. Here we describe the development of a real-time cerebellar neuroprosthetic system to substitute neural function in cerebellar circuitry for learning delay eyeblink conditioning (DEC). Approach. The system was empowered by a biologically realistic spiking neural network (SNN) model of the cerebellar neural circuit, which considers the neuronal population and anatomical connectivity of the network. The model simulated synaptic plasticity critical for learning DEC. This SNN model was carefully implemented on a field programmable gate array (FPGA) platform for real-time simulation. This hardware system was interfaced in in vivo experiments with anesthetized rats and it used neural spikes recorded online from the animal to learn and trigger conditioned eyeblink in the animal during training. Main results. This rat-FPGA hybrid system was able to process neuronal spikes in real-time with an embedded cerebellum model of ~10 000 neurons and reproduce learning of DEC with different inter-stimulus intervals. Our results validated that the system performance is physiologically relevant at both the neural (firing pattern) and behavioral (eyeblink pattern) levels. Significance. This integrated system provides the sufficient computation power for mimicking the cerebellar circuit in real-time. The system interacts with the biological system naturally at the spike level and can be generalized for including other neural components (neuron types and plasticity) and neural functions for potential neuroprosthetic applications.

Assessment of satellite communications quality study. Addendum 1: Impact of propagation delay on data transmission

NASA Technical Reports Server (NTRS)

Campanella, S. J.; Chitre, D. M.

1988-01-01

The single factor that irrevocably distinguishes geostationary satellite telephony transmission from terrestrial transmission is the greater propagation delay over satellite links. This difference has always provoked vigorous debate over the impact of delay on the subscribers using services incorporating satellite links. The issue is addressed from a variety of directions including human factors studies, laboratory subjective tests that evaluate delay with and without echo, and field tests that obtain data on the opinion of subscribers regarding the quality of service of operational circuits in both national U.S. domestic and international trans-Atlantic network. The tests involved the use of both echo suppressors and echo cancellers.

Synchronization error estimation and controller design for delayed Lur'e systems with parameter mismatches.

PubMed

He, Wangli; Qian, Feng; Han, Qing-Long; Cao, Jinde

2012-10-01

This paper investigates the problem of master-slave synchronization of two delayed Lur'e systems in the presence of parameter mismatches. First, by analyzing the corresponding synchronization error system, synchronization with an error level, which is referred to as quasi-synchronization, is established. Some delay-dependent quasi-synchronization criteria are derived. An estimation of the synchronization error bound is given, and an explicit expression of error levels is obtained. Second, sufficient conditions on the existence of feedback controllers under a predetermined error level are provided. The controller gains are obtained by solving a set of linear matrix inequalities. Finally, a delayed Chua's circuit is chosen to illustrate the effectiveness of the derived results.

Design and test of a flat-top magnetic field system driven by capacitor banks.

PubMed

Jiang, Fan; Peng, Tao; Xiao, Houxiu; Zhao, Jianlong; Pan, Yuan; Herlach, Fritz; Li, Liang

2014-04-01

An innovative method for generating a flat-top pulsed magnetic field by means of capacitor banks is developed at the Wuhan National High Magnetic Field Center (WHMFC). The system consists of two capacitor banks as they are normally used to generate a pulsed field. The two discharge circuits (the magnet circuit and the auxiliary circuit) are coupled by a pulse transformer such that the electromotive force (EMF) induced via the transformer in the magnet circuit containing the magnet coil is opposed to the EMF of the capacitor bank. At a certain point before the current pulse in the coil reaches its peak, the auxiliary circuit is triggered. With optimized parameters for charging voltage and trigger delay, the current in the magnet circuit can be approximately kept constant to obtain a flat-top. A prototype was developed at the WHMFC; the magnet circuit was energized by seven 1 MJ (3.2 mF/25 kV) capacitor modules and the auxiliary circuit by four 1 MJ modules. Fields up to 41 T with 6 ms flat-top have been obtained with a conventional user magnet used at the WHMFC.

High-Precision Pulse Generator

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A document discusses a pulse generator with subnanosecond resolution implemented with a low-cost field-programmable gate array (FPGA) at low power levels. The method used exploits the fast carry chains of certain FPGAs. Prototypes have been built and tested in both Actel AX and Xilinx Virtex 4 technologies. In-flight calibration or control can be performed by using a similar and related technique as a time interval measurement circuit by measuring a period of the stable oscillator, as the delays through the fast carry chains will vary as a result of manufacturing variances as well as the result of environmental conditions (voltage, aging, temperature, and radiation).

Charge Coupled Devices in Signal Processing Systems. Volume V. Final Report.

DTIC Science & Technology

1979-12-01

the Phase III program. At that time, mutual customer /contractor interest arose in a unique application area, involving manipulation of lists of...using half adders and "or" circuits. 4-35 3 b 2 b3 01 b *3b, *2 b 1 b2b 1 0 1 b, + + + + + + ++ r T 7 7 r* 7FA +-0j FA 147 7 7 1 77 7 7 TL NO.6 NO. 5...which the cell could be step-and- repeated into an array in the CAD system. In practice we found that the attendent custom skewing delay layout

A Coherent VLSI Design Environment.

DTIC Science & Technology

1986-03-31

Schema were a CMOS sorter and a TTL PC board for gathering statistics from a Multibus. Neither design was completed using Schema, but at least in the...technique for automatically adjusting signal delays in an MOS system has been developed. The Dynamic Delay Adjustment (DDA) technique provides...34Synchronization Reliability in CMOS Technology," IEEE J. of Solid - State Circuits, Vol. SC-20, No. 4, pp. 880-883, 1985. * [8] J. Hohl, W. Larsen and L. Schooley

Line length dependencies in interconnect optimization

NASA Astrophysics Data System (ADS)

Kadoch, Daniel; Duane, Michael; Lee, Yohan

1997-09-01

Metal line delay has become increasingly important for ULSI devices. Numerous expressions and software tools have been developed to describe interconnect delay as a function of the geometry and layout. Although many of these formulas have line length effects, this has not been explored in depth. Most software tools are either geared towards circuit designers, or involve more complex and CPU-intensive 3D modeling. In this work, PISCES (a 2D device simulator) was used to extract metal capacitance per unit length. We extend this approach for various lengths by creating a ladder network of the RC components and simulating in SPICE, or using simple closed-form Elmore delay equations. A new key result is that there are optimum metal line width/space for a fixed pitch and height/space ratios that are metal length dependent. For metal lines shorter than about 1500 micrometers , it is better to have narrower metal lines, and for lengths less than 500 micrometers , shrinking metal height is desirable because the penalty in resistance is more than compensated by the decrease in capacitance. For longer lines, the time delay is dominated by resistance, and wider, taller lines are better. Increasing metal spacing or reducing dielectric constant were beneficial for both long and short metal lines.

A neuromorphic implementation of multiple spike-timing synaptic plasticity rules for large-scale neural networks

PubMed Central

Wang, Runchun M.; Hamilton, Tara J.; Tapson, Jonathan C.; van Schaik, André

2015-01-01

We present a neuromorphic implementation of multiple synaptic plasticity learning rules, which include both Spike Timing Dependent Plasticity (STDP) and Spike Timing Dependent Delay Plasticity (STDDP). We present a fully digital implementation as well as a mixed-signal implementation, both of which use a novel dynamic-assignment time-multiplexing approach and support up to 226 (64M) synaptic plasticity elements. Rather than implementing dedicated synapses for particular types of synaptic plasticity, we implemented a more generic synaptic plasticity adaptor array that is separate from the neurons in the neural network. Each adaptor performs synaptic plasticity according to the arrival times of the pre- and post-synaptic spikes assigned to it, and sends out a weighted or delayed pre-synaptic spike to the post-synaptic neuron in the neural network. This strategy provides great flexibility for building complex large-scale neural networks, as a neural network can be configured for multiple synaptic plasticity rules without changing its structure. We validate the proposed neuromorphic implementations with measurement results and illustrate that the circuits are capable of performing both STDP and STDDP. We argue that it is practical to scale the work presented here up to 236 (64G) synaptic adaptors on a current high-end FPGA platform. PMID:26041985

Delay in micro-discharges appearance during PEO of Al: Evidence of a mechanism of charge accumulation at the electrolyte/oxide interface

NASA Astrophysics Data System (ADS)

Martin, J.; Nominé, A.; Brochard, F.; Briançon, J.-L.; Noël, C.; Belmonte, T.; Czerwiec, T.; Henrion, G.

2017-07-01

PEO was conducted on Al by applying a pulsed bipolar current. The role of the cathodic polarization on the appearance of micro-discharges (MDs) and on the subsequent formation of the PEO oxide layers is investigated. Various ratios of the charge quantity RCQ = Qp/Qn (defined as the anodic Qp to cathodic Qn charge quantity ratio over one current pulse period) in the range [0.5; 6.0] were selected by changing the waveform parameters of the cathodic current while keeping the waveform of the anodic current unchanged. Results show that the appearance of MDs is delayed with respect to the rising edge of the anodic current; this delay strongly depends on both the processing time and the applied cathodic charge quantity. It is also evidenced that shorter delays promoted by high RCQ values (RCQ > 1) are associated with stronger MDs (large size and long life) that have detrimental effects on the formed PEO oxide layers. Thicker and the more compact oxide layer morphology is achieved with the intermediate RCQ value (RCQ = 0.9) for which the delay of the MDs appearance is high and the MDs softer. Low RCQ (RCQ < 0.9) results in an earlier extinction of the MDs as the process goes on, which leads to poorly oxidized metal. A mechanism of charge accumulation taking place at the oxide/electrolyte interface and arising before the occurrence of dielectric breakdown is proposed to explain the ignition of MDs during pulsed bipolar PEO of aluminium. A close examination of the voltage-time response which can be adequately simulated with an equivalent RC circuit evidences the capacitive behaviour of the oxide layer and therefore confirms this proposed mechanism of charge accumulation.

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Theoretical analysis of cross-talking signals between counter-streaming electron beams in a vacuum tube oscillator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shin, Y.M.; Ryskin, N.M.; Won, J.H.

The basic theory of cross-talking signals between counter-streaming electron beams in a vacuum tube oscillator consisting of two two-cavity klystron amplifiers reversely coupled through input/output slots is theoretically investigated. Application of Kirchhoff's laws to the coupled equivalent RLC circuit model of the device provides four nonlinear coupled equations, which are the first-order time-delayed differential equations. Analytical solutions obtained through linearization of the equations provide oscillation frequencies and thresholds of four fundamental eigenstates, symmetric/antisymmetric 0/{pi} modes. Time-dependent output signals are numerically analyzed with variation of the beam current, and a self-modulation mechanism and transition to chaos scenario are examined. The oscillatormore » shows a much stronger multistability compared to a delayed feedback klystron oscillator owing to the competitions among more diverse eigenmodes. A fully developed chaos region also appears at a relatively lower beam current, {approx}3.5I{sub st}, compared to typical vacuum tube oscillators (10-100I{sub st}), where I{sub st} is a start-oscillation current.« less

Optimal design of leak-proof SRAM cell using MCDM method

NASA Astrophysics Data System (ADS)

Wang, Qi; Kang, Sung-Mo

2003-04-01

As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on microprocessor's performance. Meanwhile, it also occupies a big percentage of processor area and consumes large power. Speed, power and area of SRAM are mutually contradicting, and not easy to be met simultaneously. Many existent leakage suppression techniques have been proposed, but they limit the circuit's performance. We apply a Multi-Criteria Decision Making strategy to perform a minimum delay-power-area optimization on SRAM circuit under some certain constraints. Based on an integrated device and circuit-level approach, we search for a process that yields a targeted composite performance. In consideration of the huge amount of simulation workload involved in the optimal design-seeking process, most of this process is automated to facilitate our goal-pursuant. With varying emphasis put on delay, power or area, different optimal SRAM designs are derived and a gate-oxide thickness scaling limit is projected. The result seems to indicate that a better composite performance could be achieved under a thinner oxide thickness. Under the derived optimal oxide thickness, the static leakage power consumption contributes less than 1% in the total power dissipation.

The Generation of Antiphase Oscillations and Synchrony by a Rebound-Based Vertebrate Central Pattern Generator

PubMed Central

Merrison-Hort, Robert; Zhang, Hong-Yan; Borisyuk, Roman

2014-01-01

Many neural circuits are capable of generating multiple stereotyped outputs after different sensory inputs or neuromodulation. We have previously identified the central pattern generator (CPG) for Xenopus tadpole swimming that involves antiphase oscillations of activity between the left and right sides. Here we analyze the cellular basis for spontaneous left–right motor synchrony characterized by simultaneous bursting on both sides at twice the swimming frequency. Spontaneous synchrony bouts are rare in most tadpoles, and they instantly emerge from and switch back to swimming, most frequently within the first second after skin stimulation. Analyses show that only neurons that are active during swimming fire action potentials in synchrony, suggesting both output patterns derive from the same neural circuit. The firing of excitatory descending interneurons (dINs) leads that of other types of neurons in synchrony as it does in swimming. During synchrony, the time window between phasic excitation and inhibition is 7.9 ± 1 ms, shorter than that in swimming (41 ± 2.3 ms). The occasional, extra midcycle firing of dINs during swimming may initiate synchrony, and mismatches of timing in the left and right activity can switch synchrony back to swimming. Computer modeling supports these findings by showing that the same neural network, in which reciprocal inhibition mediates rebound firing, can generate both swimming and synchrony without circuit reconfiguration. Modeling also shows that lengthening the time window between phasic excitation and inhibition by increasing dIN synaptic/conduction delay can improve the stability of synchrony. PMID:24760866

Flat-Passband 3 × 3 Interleaving Filter Designed With Optical Directional Couplers in Lattice Structure

NASA Astrophysics Data System (ADS)

Wang, Qi Jie; Zhang, Ying; Soh, Yeng Chai

2005-12-01

This paper presents a novel lattice optical delay-line circuit using 3 × 3 directional couplers to implement three-port optical interleaving filters. It is shown that the proposed circuit can deliver three channels of 2pi/3 phase-shifted interleaving transmission spectra if the coupling ratios of the last two directional couplers are selected appropriately. The other performance requirements of an optical interleaver can be achieved by designing the remaining part of the lattice circuit. A recursive synthesis design algorithm is developed to calculate the design parameters of the lattice circuit that will yield the desired filter response. As illustrative examples, interleavers with maximally flat-top passband transmission and with given transmission performance on passband ripples and passband bandwidth, respectively, are designed to verify the effectiveness of the proposed design scheme.

Non-Foster Circuits for High Performance Antennas: Advantages and Practical Limitations

NASA Astrophysics Data System (ADS)

Jacob, Minu Mariam

The demand for miniaturized, broadband communication systems has created a need for electrically small, broadband antennas. However, all passive electrically small antennas have a fundamental gain-bandwidth limitation related to their electrical size, as first described by Wheeler and Chu. This limitation can be overcome using active non-Foster circuits (negative inductors and/or negative capacitors), which can deliver a broadband input match with active matching techniques, or can help reduce phase dispersion using negative delay effects. This thesis will illustrate the advantages of non-Foster circuits in obtaining broadband small antennas, in addition to examining their practical limitations due to noise in receive applications, and nonlinearity in transmit applications.

FREQUENCY STABILIZING SYSTEM

DOEpatents

Kerns, Q.A.; Anderson, O.A.

1960-05-01

An electronic control circuit is described in which a first signal frequency is held in synchronization with a second varying reference signal. The circuit receives the first and second signals as inputs and produces an output signal having an amplitude dependent upon rate of phase change between the two signals and a polarity dependent on direction of the phase change. The output may thus serve as a correction signal for maintaining the desired synchronization. The response of the system is not dependent on relative phase angle between the two compared signals. By having practically no capacitance in the circuit, there is minimum delay between occurrence of a phase shift and a response in the output signal and therefore very fast synchronization is effected.

Benzothiadiazole-based polymer for single and double junction solar cells with high open circuit voltage.

PubMed

Venkatesan, Swaminathan; Ngo, Evan C; Chen, Qiliang; Dubey, Ashish; Mohammad, Lal; Adhikari, Nirmal; Mitul, Abu Farzan; Qiao, Qiquan

2014-06-21

Single and double junction solar cells with high open circuit voltage were fabricated using poly{thiophene-2,5-diyl-alt-[5,6-bis(dodecyloxy)benzo[c][1,2,5]thiadiazole]-4,7-diyl} (PBT-T1) blended with fullerene derivatives in different weight ratios. The role of fullerene loading on structural and morphological changes was investigated using atomic force microscopy (AFM) and X-ray diffraction (XRD). The XRD and AFM measurements showed that a higher fullerene mixing ratio led to breaking of inter-chain packing and hence resulted in smaller disordered polymer domains. When the PBT-T1:PC60BM weight ratio was 1 : 1, the polymer retained its structural order; however, large aggregated domains formed, leading to poor device performance due to low fill factor and short circuit current density. When the ratio was increased to 1 : 2 and then 1 : 3, smaller amorphous domains were observed, which improved photovoltaic performance. The 1 : 2 blending ratio was optimal due to adequate charge transport pathways giving rise to moderate short circuit current density and fill factor. Adding 1,8-diiodooctane (DIO) additive into the 1 : 2 blend films further improved both the short circuit current density and fill factor, leading to an increased efficiency to 4.5% with PC60BM and 5.65% with PC70BM. These single junction solar cells exhibited a high open circuit voltage at ∼ 0.9 V. Photo-charge extraction by linearly increasing voltage (Photo-CELIV) measurements showed the highest charge carrier mobility in the 1 : 2 film among the three ratios, which was further enhanced by introducing the DIO. The Photo-CELIV measurements with varying delay times showed significantly higher extracted charge carrier density for cells processed with DIO. Tandem devices using P3HT:IC60BA as bottom cell and PBT-T1:PC60BM as top cell exhibited a high open circuit voltage of 1.62 V with 5.2% power conversion efficiency.

Effect of liquid gate bias rising time in pH sensors based on Si nanowire ion sensitive field effect transistors

NASA Astrophysics Data System (ADS)

Jang, Jungkyu; Choi, Sungju; Kim, Jungmok; Park, Tae Jung; Park, Byung-Gook; Kim, Dong Myong; Choi, Sung-Jin; Lee, Seung Min; Kim, Dae Hwan; Mo, Hyun-Sun

2018-02-01

In this study, we investigate the effect of rising time (TR) of liquid gate bias (VLG) on transient responses in pH sensors based on Si nanowire ion-sensitive field-effect transistors (ISFETs). As TR becomes shorter and pH values decrease, the ISFET current takes a longer time to saturate to the pH-dependent steady-state value. By correlating VLG with the internal gate-to-source voltage of the ISFET, we found that this effect occurs when the drift/diffusion of mobile ions in analytes in response to VLG is delayed. This gives us useful insight on the design of ISFET-based point-of-care circuits and systems, particularly with respect to determining an appropriate rising time for the liquid gate bias.

Effects of Frequency Dependence of the External Quantum Efficiency of Perovskite Solar Cells.

PubMed

Ravishankar, Sandheep; Aranda, Clara; Boix, Pablo P; Anta, Juan A; Bisquert, Juan; Garcia-Belmonte, Germà

2018-06-07

Perovskite solar cells are known to show very long response time scales, on the order of milliseconds to seconds. This generates considerable doubt over the validity of the measured external quantum efficiency (EQE) and consequently the estimation of the short-circuit current density. We observe a variation as high as 10% in the values of the EQE of perovskite solar cells for different optical chopper frequencies between 10 and 500 Hz, indicating a need to establish well-defined protocols of EQE measurement. We also corroborate these values and obtain new insights regarding the working mechanisms of perovskite solar cells from intensity-modulated photocurrent spectroscopy measurements, identifying the evolution of the EQE over a range of frequencies, displaying a singular reduction at very low frequencies. This reduction in EQE is ascribed to additional resistive contributions hindering charge extraction in the perovskite solar cell at short-circuit conditions, which are delayed because of the concomitant large low-frequency capacitance.

A Post-Transcriptional Feedback Mechanism for Noise Suppression and Fate Stabilization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hansen, Maike M. K.; Wen, Winnie Y.; Ingerman, Elena

Diverse biological systems utilize fluctuations (“noise”) in gene expression to drive lineage-commitment decisions. However, once a commitment is made, noise becomes detrimental to reliable function, and the mechanisms enabling post-commitment noise suppression are unclear. Here, we find that architectural constraints on noise suppression are overcome to stabilize fate commitment. Using single-molecule and time-lapse imaging, we find that—after a noise-driven event—human immunodeficiency virus (HIV) strongly attenuates expression noise through a non-transcriptional negative-feedback circuit. Feedback is established through a serial cascade of post-transcriptional splicing, whereby proteins generated from spliced mRNAs auto-deplete their own precursor unspliced mRNAs. Strikingly, this auto-depletion circuitry minimizes noisemore » to stabilize HIV’s commitment decision, and a noise-suppression molecule promotes stabilization. Lastly, this feedback mechanism for noise suppression suggests a functional role for delayed splicing in other systems and may represent a generalizable architecture of diverse homeostatic signaling circuits.« less

A Post-Transcriptional Feedback Mechanism for Noise Suppression and Fate Stabilization

DOE PAGES

Hansen, Maike M. K.; Wen, Winnie Y.; Ingerman, Elena; ...

2018-05-10

Diverse biological systems utilize fluctuations (“noise”) in gene expression to drive lineage-commitment decisions. However, once a commitment is made, noise becomes detrimental to reliable function, and the mechanisms enabling post-commitment noise suppression are unclear. Here, we find that architectural constraints on noise suppression are overcome to stabilize fate commitment. Using single-molecule and time-lapse imaging, we find that—after a noise-driven event—human immunodeficiency virus (HIV) strongly attenuates expression noise through a non-transcriptional negative-feedback circuit. Feedback is established through a serial cascade of post-transcriptional splicing, whereby proteins generated from spliced mRNAs auto-deplete their own precursor unspliced mRNAs. Strikingly, this auto-depletion circuitry minimizes noisemore » to stabilize HIV’s commitment decision, and a noise-suppression molecule promotes stabilization. Lastly, this feedback mechanism for noise suppression suggests a functional role for delayed splicing in other systems and may represent a generalizable architecture of diverse homeostatic signaling circuits.« less

Capacity loss on storage and possible capacity recovery for HST nickel-hydrogen cells

NASA Technical Reports Server (NTRS)

Lowery, John E.

1992-01-01

Negatively precharged nickel hydrogen cells will experience a useable capacity loss during extended open circuit storage periods. Some of the lost capacity can be recovered through cycling. Capacity recovery through cycling can be enhanced by cycling at high depths of discharge (DOD). The most timely procedure for recovering the faded capacity is to charge the cell fully and allow the cell to sit open-circuit at room temperature. This procedure seems to be effective in part because of the enlarged structure of the active materials. The compounds that formed during storage at the low electrode potentials can more easily dissolve and redistribute. All of the original capacity cannot be recovered because the lattice structure of the active material is irreversibly altered during storage. The recommendation is to use positively precharged cells activated with 26 percent KOH if possible. In aerospace applications, the benefits of negative precharge are offset by the possibility of delays and storage periods.

Reward circuit connectivity relates to delay discounting in children with attention-deficit/hyperactivity disorder

PubMed Central

Costa Dias, Taciana G.; Wilson, Vanessa B.; Bathula, Deepti R.; Iyer, Swathi P.; Mills, Kathryn L.; Thurlow, Bria L.; Stevens, Corinne A.; Musser, Erica D.; Carpenter, Samuel D.; Grayson, David S.; Mitchell, Suzanne H.; Nigg, Joel T.; Fair, Damien A.

2012-01-01

Attention-deficit/hyperactivity disorder (ADHD) is a prevalent psychiatric disorder that has poor long-term outcomes and remains a major public health concern. Recent theories have proposed that ADHD arises from alterations in multiple neural pathways. Alterations in reward circuits are hypothesized as one core dysfunction, leading to altered processing of anticipated rewards. The nucleus accumbens (NAcc) is particularly important for reward processes; task-based fMRI studies have found atypical activation of this region while the participants performed a reward task. Understanding how reward circuits are involved with ADHD may be further enhanced by considering how the NAcc interacts with other brain regions. Here we used the technique of resting-state functional connectivity MRI (rs-fcMRI) to examine the alterations in the NAcc interactions and how they relate to impulsive decision making in ADHD. Using rs-fcMRI, this study: examined differences in functional connectivity of the NAcc between children with ADHD and control children; correlated the functional connectivity of NAcc with impulsivity, as measured by a delay discounting task; and combined these two initial segments to identify the atypical NAcc connections that were associated with impulsive decision making in ADHD. We found that functional connectivity of NAcc was atypical in children with ADHD and the ADHD-related increased connectivity between NAcc and the prefrontal cortex was associated with greater impulsivity (steeper delayed-reward discounting). These findings are consistent with the hypothesis that atypical signaling of the NAcc to the prefrontal cortex in ADHD may lead to excessive approach and failure in estimating future consequences; thus, leading to impulsive behavior. PMID:23206930

High-performance reconfigurable coincidence counting unit based on a field programmable gate array.

PubMed

Park, Byung Kwon; Kim, Yong-Su; Kwon, Osung; Han, Sang-Wook; Moon, Sung

2015-05-20

We present a high-performance reconfigurable coincidence counting unit (CCU) using a low-end field programmable gate array (FPGA) and peripheral circuits. Because of the flexibility guaranteed by the FPGA program, we can easily change system parameters, such as internal input delays, coincidence configurations, and the coincidence time window. In spite of a low-cost implementation, the proposed CCU architecture outperforms previous ones in many aspects: it has 8 logic inputs and 4 coincidence outputs that can measure up to eight-fold coincidences. The minimum coincidence time window and the maximum input frequency are 0.47 ns and 163 MHz, respectively. The CCU will be useful in various experimental research areas, including the field of quantum optics and quantum information.

Computational modeling of stuttering caused by impairments in a basal ganglia thalamo-cortical circuit involved in syllable selection and initiation

PubMed Central

Civier, Oren; Bullock, Daniel; Max, Ludo; Guenther, Frank H.

2013-01-01

A typical white-matter integrity and elevated dopamine levels have been reported for individuals who stutter. We investigated how such abnormalities may lead to speech dysfluencies due to their effects on a syllable-sequencing circuit that consists of basal ganglia (BG), thalamus, and left ventral premotor cortex (vPMC). “Neurally impaired” versions of the neurocomputational speech production model GODIVA were utilized to test two hypotheses: (1) that white-matter abnormalities disturb the circuit via corticostriatal projections carrying copies of executed motor commands, and (2) that dopaminergic abnormalities disturb the circuit via the striatum. Simulation results support both hypotheses: in both scenarios, the neural abnormalities delay readout of the next syllable’s motor program, leading to dysfluency. The results also account for brain imaging findings during dysfluent speech. It is concluded that each of the two abnormality types can cause stuttering moments, probably by affecting the same BG-thalamus-vPMC circuit. PMID:23872286

Hyperkalemia of the blood-primed ECLS circuit does not result in post-initiation hyperkalemia in infants < 10 kg.

PubMed

Fleming, Geoffrey M; Remenapp, Robert T; Bartlett, Robert H; Annich, Gail M

2006-05-01

To assess the risk of hyperkalemia with blood-primed extracorporeal life support (ECLS) circuits in infants < 10 kg. Retrospective cohort study of all neonatal and pediatric patients < 10 kg placed on ECLS from May 1998 to April 2001. Data collection including patient weight, patient potassium levels pre- and post-initiation of ECLS, potassium level of the primed ECLS circuit, age of the packed red blood cell (PRBC) unit, type of preservative, and preservative reduction status. Seventy-six circuits were available for the analysis. The age of the PRBC unit and preservative reduction status significantly affected the potassium level of the primed ECLS circuit. Multivariate linear regression analysis showed no significant effect on the post-ECLS initiation patient potassium level with respect to the PRBC age, the preservative reduction status, the patient potassium level prior to ECLS initiation, and the potassium level of the primed ECLS circuit. Initiation of ECLS in infants < 10 kg should not be delayed unnecessarily to perform preservative reduction or to utilize PRBC units of a specific age, as hyperkalemia of the primed ECLS circuit is not associated with systemic hyperkalemia in the patient post-initiation of ECLS.

Microwave evaluation of electromigration susceptibility in advanced interconnects.

PubMed

Sunday, Christopher E; Veksler, Dmitry; Cheung, Kin C; Obeng, Yaw S

2017-11-07

Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs. https://doi.org/10.1063/1.4992135.

Multigranular integrated services optical network

NASA Astrophysics Data System (ADS)

Yu, Oliver; Yin, Leping; Xu, Huan; Liao, Ming

2006-12-01

Based on all-optical switches without requiring fiber delay lines and optical-electrical-optical interfaces, the multigranular optical switching (MGOS) network integrates three transport services via unified core control to efficiently support bursty and stream traffic of subwavelength to multiwavelength bandwidth. Adaptive robust optical burst switching (AR-OBS) aggregates subwavelength burst traffic into asynchronous light-rate bursts, transported via slotted-time light paths established by fast two-way reservation with robust blocking recovery control. Multiwavelength optical switching (MW-OS) decomposes multiwavelength stream traffic into a group of timing-related light-rate streams, transported via a light-path group to meet end-to-end delay-variation requirements. Optical circuit switching (OCS) simply converts wavelength stream traffic from an electrical-rate into a light-rate stream. The MGOS network employs decoupled routing, wavelength, and time-slot assignment (RWTA) and novel group routing and wavelength assignment (GRWA) to select slotted-time light paths and light-path groups, respectively. The selected resources are reserved by the unified multigranular robust fast optical reservation protocol (MG-RFORP). Simulation results show that elastic traffic is efficiently supported via AR-OBS in terms of loss rate and wavelength utilization, while connection-oriented wavelength traffic is efficiently supported via wavelength-routed OCS in terms of connection blocking and wavelength utilization. The GRWA-tuning result for MW-OS is also shown.

Implementation study of patient-ready syringes containing 25 mg/mL methotrexate solution for use in treating ectopic pregnancy.

PubMed

Respaud, R; Gaudy, A S; Arlicot, C; Tournamille, J F; Viaud-Massuard, M C; Elfakir, C; Antier, D

2014-01-01

Ectopic pregnancy (EP) is a significant cause of morbidity and mortality during the first trimester of pregnancy. Small unruptured tubal pregnancies can be treated medically with a single dose of methotrexate (MTX). The aim of this study was to evaluate the stability of a 25 mg/mL solution of MTX to devise a secure delivery circuit for the preparation and use of this medication in the management of EP. MTX solutions were packaged in polypropylene syringes, stored over an 84-day period, and protected from light either at +2 to +8°C or at 23°C. We assessed the physical and chemical stability of the solutions at various time points over the storage period. A pharmaceutical delivery circuit was implemented that involved the batch preparation of MTX syringes. We show that 25 mg/mL MTX solutions remain stable over an 84-day period under the storage conditions tested. Standard doses were prepared, ranging from 50 mg to 100 mg. The results of this study suggest that MTX syringes can be prepared in advance by the pharmacy, ready to be dispensed at any time that a diagnosis of EP is made. The high stability of a 25 mg/mL MTX solution in polypropylene syringes makes it possible to implement a flexible and cost-effective delivery circuit for ready-to-use preparations of this drug, providing 24-hour access and preventing treatment delays.

Time and position sensitive single photon detector for scintillator read-out

NASA Astrophysics Data System (ADS)

Schössler, S.; Bromberger, B.; Brandis, M.; Schmidt, L. Ph H.; Tittelmeier, K.; Czasch, A.; Dangendorf, V.; Jagutzki, O.

2012-02-01

We have developed a photon counting detector system for combined neutron and γ radiography which can determine position, time and intensity of a secondary photon flash created by a high-energy particle or photon within a scintillator screen. The system is based on a micro-channel plate photomultiplier concept utilizing image charge coupling to a position- and time-sensitive read-out anode placed outside the vacuum tube in air, aided by a standard photomultiplier and very fast pulse-height analyzing electronics. Due to the low dead time of all system components it can cope with the high throughput demands of a proposed combined fast neutron and dual discrete energy γ radiography method (FNDDER). We show tests with different types of delay-line read-out anodes and present a novel pulse-height-to-time converter circuit with its potential to discriminate γ energies for the projected FNDDER devices for an automated cargo container inspection system (ACCIS).

Digital Synchronizer without Metastability

NASA Technical Reports Server (NTRS)

Simle, Robert M.; Cavazos, Jose A.

2009-01-01

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Unconstitutionality of abortion laws affirmed.

PubMed

1979-08-01

A federal appeals court has affirmed lower court rulings that substantial portions of the Illinois' 1975 Abortion Act and 1977 Abortion Parental Consent Act are unconstitutional. The 7th Court adopted an April 12, 1978 district court opinion that invalidated several sections of the Illinois 1975 abortion statute, including parental and spousal consent requirements and provisions requiring that a woman be informed of the "physical competency" of the fetus at the time the abortion was to be performed. The appeals court specifically addressed the statute's provision making a liveborn fetus resulting from an abortion a ward of the state, unless the abortion was performed to save the woman's life. Regarding the 1977 Parental Consent Act, the 7th Circuit reaffirmed its August 1978 ruling that it is unconstitutional to require an unmarried minor to have the consent of both parents or, if they refused consent, a circuit court judge before undergoing an abortion. The appeals court also agreed with the lower court's November 2nd ruling that the Act's requirement of a 48-hour delay between the time the minor gives her consent and the performance of an abortion violated the equal protection clause of the 14th amendment.

Integrated mixed signal control IC for 500-kHz switching frequency buck regulator

NASA Astrophysics Data System (ADS)

Chen, Keng; Zhang, Hong

2015-12-01

The main purpose for this work is to study the challenges of designing a digital buck regulator using pipelined analog to digital converter (ADC). Although pipelined ADC can achieve high sampling speed, it will introduce additional phase lag to the buck circuit. Along with the latency brought by processing time of additional digital circuits, as well as the time delay associated with the switching frequency, the closed loop will be unstable; moreover, raw ADC outputs have low signal-to-noise ratio, which usually need back-end calibration. In order to compensate these phase lag and make control loop unconditional stable, as well as boost up signal-to-noise ratio of the ADC block with cost-efficient design, a finite impulse response filter followed by digital proportional-integral-derivative blocks were designed. All these digital function blocks were optimised with processing speed. In the system simulation, it can be found that this controller achieved output regulation within 10% of nominal 5 V output voltage under 1 A/µs load transient condition; moreover, with the soft-start method, there is no turn-on overshooting. The die size of this controller is controlled within 3 mm2 by using 180 nm CMOS technology.

Active feedforward noise control and signal tracking of headsets: Electroacoustic analysis and system implementation.

PubMed

Bai, Mingsian R; Pan, Weichi; Chen, Hungyu

2018-03-01

Active noise control (ANC) of headsets is revisited in this paper. An in-depth electroacoustic analysis of the combined loudspeaker-cavity headset system is conducted on the basis of electro-mechano-acoustical analogous circuits. Model matching of the primary path and the secondary path leads to a feedforward control architecture. The ideal controller sheds some light on the key parameters that affect the noise reduction performance. Filtered-X least-mean-squares algorithm is employed to implement the feedforward controller on a digital signal processor. Since the relative delay of the primary path and the secondary path is crucial to the noise reduction performance, multirate signal processing with polyphase implementation is utilized to minimize the effective analog-digital conversion delay in the secondary path. Ad hoc decimation and interpolation filters are designed in order not to introduce excessive phase delays at the cutoff. Real-time experiments are undertaken to validate the implemented ANC system. Listening tests are also conducted to compare the fixed controller and the adaptive controller in terms of noise reduction and signal tracking performance for three noise types. The results have demonstrated that the fixed feedforward controller achieved satisfactory noise reduction performance and signal tracking quality.

The DCU: the detector control unit of the SAFARI instrument onboard SPICA

NASA Astrophysics Data System (ADS)

Clénet, A.; Ravera, L.; Bertrand, B.; Cros, A.; Hou, R.; Jackson, B. D.; van Leeuwen, B. J.; Van Loon, D.; Parot, Y.; Pointecouteau, E.; Sournac, A.; Ta, N.

2012-09-01

The SpicA FAR infrared Instrument (SAFARI) is a European instrument for the infrared domain telescope SPICA, a JAXA space mission. The SAFARI detectors are Transistor Edge Sensors (TES) arranged in 3 matrixes. The TES front end electronic is based on Superconducting Quantum Interference Devices (SQUIDs) and it does the readout of the 3500 detectors with Frequency Division Multiplexing (FDM) type architecture. The Detector Control Unit (DCU), contributed by IRAP, manages the readout of the TES by computing and providing the AC-bias signals (1 - 3 MHz) to the TES and by computing the demodulation of the returning signals. The SQUID being highly non-linear, the DCU has also to provide a feedback signal to increase the SQUID dynamic. Because of the propagation delay in the cables and the processing time, a classic feedback will not be stable for AC-bias frequencies up to 3 MHz. The DCU uses a specific technique to compensate for those delays: the BaseBand FeedBack (BBFB). This digital data processing is done for the 3500 pixels in parallel. Thus, to keep the DCU power budget within its allocation we have to specifically optimize the architecture of the digital circuit with respect to the power consumption. In this paper we will mainly present the DCU architecture. We will particularly focus on the BBFB technique used to linearize the SQUID and on the optimization done to reduce the power consumption of the digital processing circuit.

FELERION: a new approach for leakage power reduction

NASA Astrophysics Data System (ADS)

R, Anjana; Somkuwar, Ajay

2014-12-01

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%-94% as compared to the conventional approach.

A Right Way and a Wrong Way: Remedying Excessive Post-Trial Delay in Light of Tardiff, Moreno, and Toohey

DTIC Science & Technology

2007-04-01

Guard (enlisted service), 1991-1993. Member of the bars of the Commonwealth of Virginia, the United States Court of Appeals for the Federal Circuit...the United States Court of Appeals for the Armed Forces, the Court of Federal Claims, and the United States Army Court of Criminal Appeals . This...I. Introduction 3 II. Historical Background 6 A. History of Criminal Appeals 6 B. Post-Trial Delay Cases 11 III. United States v. Tardiff. 21 IV

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

DTIC Science & Technology

2007-06-01

requires a significant deviation from previous work. For instance, we find that using the relaxed input replication model from Reunion incurs a...Circuit Width Delay Count CRC-16 16 6.65 754 CRC- SDLC -16 16 6.10 888 CRC-32 16 7.28 2260 CRC-32 32 8.60 4240 Table 1. FO4 delay and transistor count for...the operation of our proposed system is the same in all other respects. 4.4 Compatibility Across Memory Consis- tency Models The memory consistency

Signatures of Hong-Ou-Mandel interference at microwave frequencies

NASA Astrophysics Data System (ADS)

Woolley, M. J.; Lang, C.; Eichler, C.; Wallraff, A.; Blais, A.

2013-10-01

Two-photon quantum interference at a beam splitter, commonly known as Hong-Ou-Mandel interference, is a fundamental demonstration of the quantum mechanical nature of electromagnetic fields and a key component of various quantum information processing protocols. The phenomenon was recently demonstrated with microwave-frequency photons by Lang et al (2013 Nature Phys. 9 345-8). This experiment employed circuit QED systems as sources of microwave photons, and was based on the measurement of second-order cross-correlation and auto-correlation functions of the microwave fields at the outputs of the beam splitter using linear detectors. Here we present the calculation of these correlation functions for the cases of inputs corresponding to: (i) trains of pulsed Gaussian or Lorentzian single microwave photons and (ii) resonant fluorescent microwave fields from continuously driven circuit QED systems. In both cases, the signature of two-photon quantum interference is a suppression of the second-order cross-correlation function for small delays. The experiment described in Lang et al (2013) was performed with trains of Lorentzian single photons, and very good agreement with experimental data is obtained. The results are relevant not only to interference experiments using circuit QED systems, but any such setup with highly controllable sources and time-resolved detection.

High-temperature superconductivity for avionic electronic warfare and radar systems

NASA Astrophysics Data System (ADS)

Ryan, Paul A.

1994-01-01

The electronic warfare (EW) and radar communities expect to be major beneficiaries of the performance advantages high-temperature superconductivity (HTS) has to offer over conventional technology. Near term upgrades to system hardware can be envisioned using extremely small, high Q, microwave filters and resonators; compact, wideband, low loss, microwave delay and transmission lines; as well as, wideband, low loss, monolithic microwave integrated circuit phase shifters. The most dramatic impact will be in the far term, using HTS to develop new, real time threat identification and response strategy receiver/processing systems designed to utilize the unique high frequency properties of microwave and ultimately digital HTS.

Dynamic Excitatory and Inhibitory Gain Modulation Can Produce Flexible, Robust and Optimal Decision-making

PubMed Central

Niyogi, Ritwik K.; Wong-Lin, KongFatt

2013-01-01

Behavioural and neurophysiological studies in primates have increasingly shown the involvement of urgency signals during the temporal integration of sensory evidence in perceptual decision-making. Neuronal correlates of such signals have been found in the parietal cortex, and in separate studies, demonstrated attention-induced gain modulation of both excitatory and inhibitory neurons. Although previous computational models of decision-making have incorporated gain modulation, their abstract forms do not permit an understanding of the contribution of inhibitory gain modulation. Thus, the effects of co-modulating both excitatory and inhibitory neuronal gains on decision-making dynamics and behavioural performance remain unclear. In this work, we incorporate time-dependent co-modulation of the gains of both excitatory and inhibitory neurons into our previous biologically based decision circuit model. We base our computational study in the context of two classic motion-discrimination tasks performed in animals. Our model shows that by simultaneously increasing the gains of both excitatory and inhibitory neurons, a variety of the observed dynamic neuronal firing activities can be replicated. In particular, the model can exhibit winner-take-all decision-making behaviour with higher firing rates and within a significantly more robust model parameter range. It also exhibits short-tailed reaction time distributions even when operating near a dynamical bifurcation point. The model further shows that neuronal gain modulation can compensate for weaker recurrent excitation in a decision neural circuit, and support decision formation and storage. Higher neuronal gain is also suggested in the more cognitively demanding reaction time than in the fixed delay version of the task. Using the exact temporal delays from the animal experiments, fast recruitment of gain co-modulation is shown to maximize reward rate, with a timescale that is surprisingly near the experimentally fitted value. Our work provides insights into the simultaneous and rapid modulation of excitatory and inhibitory neuronal gains, which enables flexible, robust, and optimal decision-making. PMID:23825935

Cycles of self-pulsations in a photonic integrated circuit.

PubMed

Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

2015-12-01

We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

Slow-Wave Phase Shifters, Based on Thin Ferroelectric Films, for Reflectarray Antennas. Frequency-Agile Radio: Systems and Technlogies, WMG 139

NASA Technical Reports Server (NTRS)

Romanofsky, Robert R.

2006-01-01

We have developed relatively broadband K- and Ka-band phase shifters using synthetic (slow-wave) transmission lines employing coupled microstripline "varactors". The tunable coupled microstripline circuits are based on laser ablated BaSrTiO films on lanthanum aluminate substrates. A model and design criteria for these novel circuits will be presented, along with measured performance including anomalous phase delay characteristics. The critical role of phase shifter loss and transient response in reflectarray antennas will be emphasized.

Design of time-pulse coded optoelectronic neuronal elements for nonlinear transformation and integration

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

2008-03-01

In the paper the actuality of neurophysiologically motivated neuron arrays with flexibly programmable functions and operations with possibility to select required accuracy and type of nonlinear transformation and learning are shown. We consider neurons design and simulation results of multichannel spatio-time algebraic accumulation - integration of optical signals. Advantages for nonlinear transformation and summation - integration are shown. The offered circuits are simple and can have intellectual properties such as learning and adaptation. The integrator-neuron is based on CMOS current mirrors and comparators. The performance: consumable power - 100...500 μW, signal period- 0.1...1ms, input optical signals power - 0.2...20 μW time delays - less 1μs, the number of optical signals - 2...10, integration time - 10...100 of signal periods, accuracy or integration error - about 1%. Various modifications of the neuron-integrators with improved performance and for different applications are considered in the paper.

QCA Gray Code Converter Circuits Using LTEx Methodology

NASA Astrophysics Data System (ADS)

Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish Kumar; Maji, Bansibadan

2018-07-01

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The "defect-tolerant analysis" of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

QCA Gray Code Converter Circuits Using LTEx Methodology

NASA Astrophysics Data System (ADS)

Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish Kumar; Maji, Bansibadan

2018-04-01

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The "defect-tolerant analysis" of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

Synchronization properties of network motifs: Influence of coupling delay and symmetry

NASA Astrophysics Data System (ADS)

D'Huys, O.; Vicente, R.; Erneux, T.; Danckaert, J.; Fischer, I.

2008-09-01

We investigate the effect of coupling delays on the synchronization properties of several network motifs. In particular, we analyze the synchronization patterns of unidirectionally coupled rings, bidirectionally coupled rings, and open chains of Kuramoto oscillators. Our approach includes an analytical and semianalytical study of the existence and stability of different in-phase and out-of-phase periodic solutions, complemented by numerical simulations. The delay is found to act differently on networks possessing different symmetries. While for the unidirectionally coupled ring the coupling delay is mainly observed to induce multistability, its effect on bidirectionally coupled rings is to enhance the most symmetric solution. We also study the influence of feedback and conclude that it also promotes the in-phase solution of the coupled oscillators. We finally discuss the relation between our theoretical results on delay-coupled Kuramoto oscillators and the synchronization properties of networks consisting of real-world delay-coupled oscillators, such as semiconductor laser arrays and neuronal circuits.

Vertical feed stick wood fuel burning furnace system

DOEpatents

Hill, Richard C.

1984-01-01

A new and improved stove or furnace for efficient combustion of wood fuel including a vertical feed combustion chamber for receiving and supporting wood fuel in a vertical attitude or stack, a major upper portion of the combustion chamber column comprising a water jacket for coupling to a source of water or heat transfer fluid and for convection circulation of the fluid for confining the locus of wood fuel combustion to the bottom of the vertical gravity feed combustion chamber. A flue gas propagation delay channel extending from the laterally directed draft outlet affords delayed travel time in a high temperature environment to assure substantially complete combustion of the gaseous products of wood burning with forced air as an actively induced draft draws the fuel gas and air mixture laterally through the combustion and high temperature zone. Active sources of forced air and induced draft are included, multiple use and circuit couplings for the recovered heat, and construction features in the refractory material substructure and metal component superstructure.

Membrane Potential Dynamics of CA1 Pyramidal Neurons During Hippocampal Ripples in Awake Mice

PubMed Central

Hulse, Brad K.; Moreaux, Laurent C.; Lubenov, Evgueniy V.; Siapas, Athanassios G.

2016-01-01

Ripples are high-frequency oscillations associated with population bursts in area CA1 of the hippocampus that play a prominent role in theories of memory consolidation. While spiking during ripples has been extensively studied, our understanding of the subthreshold behavior of hippocampal neurons during these events remains incomplete. Here, we combine in vivo whole-cell and multisite extracellular recordings to characterize the membrane potential dynamics of identified CA1 pyramidal neurons during ripples. We find that the subthreshold depolarization during ripples is uncorrelated with the net excitatory input to CA1, while the post-ripple hyperpolarization varies proportionately. This clarifies the circuit mechanism keeping most neurons silent during ripples. On a finer time scale, the phase delay between intracellular and extracellular ripple oscillations varies systematically with membrane potential. Such smoothly varying delays are inconsistent with models of intracellular ripple generation involving perisomatic inhibition alone. Instead, they suggest that ripple-frequency excitation leading inhibition shapes intracellular ripple oscillations. PMID:26889811

Combinational logic for generating gate drive signals for phase control rectifiers

NASA Technical Reports Server (NTRS)

Dolland, C. R.; Trimble, D. W. (Inventor)

1982-01-01

Control signals for phase-delay rectifiers, which require a variable firing angle that ranges from 0 deg to 180 deg, are derived from line-to-line 3-phase signals and both positive and negative firing angle control signals which are generated by comparing current command and actual current. Line-to-line phases are transformed into line-to-neutral phases and integrated to produce 90 deg phase delayed signals that are inverted to produce three cosine signals, such that for each its maximum occurs at the intersection of positive half cycles of the other two phases which are inputs to other inverters. At the same time, both positive and negative (inverted) phase sync signals are generated for each phase by comparing each with the next and producing a square wave when it is greater. Ramp, sync and firing angle controls signals are than used in combinational logic to generate the gate firing control signals SCR gate drives which fire SCR devices in a bridge circuit.

Effects of neonatal inferior prefrontal and medial temporal lesions on learning the rule for delayed nonmatching-to-sample.

PubMed

Málková, L; Bachevalier, J; Webster, M; Mishkin, M

2000-01-01

The ability of rhesus monkeys to master the rule for delayed nonmatching-to-sample (DNMS) has a protracted ontogenetic development, reaching adult levels of proficiency around 4 to 5 years of age (Bachevalier, 1990). To test the possibility that this slow development could be due, at least in part, to immaturity of the prefrontal component of a temporo-prefrontal circuit important for DNMS rule learning (Kowalska, Bachevalier, & Mishkin, 1991; Weinstein, Saunders, & Mishkin, 1988), monkeys with neonatal lesions of the inferior prefrontal convexity were compared on DNMS with both normal controls and animals given neonatal lesions of the medial temporal lobe. Consistent with our previous results (Bachevalier & Mishkin, 1994; Málková, Mishkin, & Bachevalier, 1995), the neonatal medial temporal lesions led to marked impairment in rule learning (as well as in recognition memory with long delays and list lengths) at both 3 months and 2 years of age. By contrast, the neonatal inferior convexity lesions yielded no impairment in rule-learning at 3 months and only a mild impairment at 2 years, a finding that also contrasts sharply with the marked effects of the same lesion made in adulthood. This pattern of sparing closely resembles the one found earlier after neonatal lesions to the cortical visual area TE (Bachevalier & Mishkin, 1994; Málková et al., 1995). The functional sparing at 3 months probably reflects the fact that the temporo-prefrontal circuit is nonfunctional at this early age, resulting in a total dependency on medial temporal contributions to rule learning. With further development, however, this circuit begins to provide a supplementary route for learning.

A Star Image Extractor for Small Satellites

NASA Astrophysics Data System (ADS)

Yamada, Yoshiyuki; Yamauchi, Masahiro; Gouda, Naoteru; Kobayashi, Yukiyasu; Tsujimoto, Takuji; Yano, Taihei; Suganuma, Masahiro; Nakasuka, Shinichi; Sako, Nobutada; Inamori, Takaya

We have developed a Star Image Extractor (SIE) which works as an on-board real-time image processor. It is a logic circuit written on an FPGA(Field Programmable Gate Array) device. It detects and extracts only an object data from raw image data. SIE will be required with the Nano-JASMINE 1) satellite. Nano-JASMINE is the small astrometry satellite that observes objects in our galaxy. It will be launched in 2010 and needs two years mission period. Nano-JASMINE observes an object with the TDI (Time Delayed Integration) observation mode. TDI is one of operation modes of CCD detector. Data is obtained, by rotating the imaging system including CCD at a rated synchronized with a vertical charge transfer of CCD. Obtained image data is sent through SIE to the Mission-controller.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Ajitha, D.; Ramanaiah, K. V.; Sumalatha, V.

2017-02-01

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

Proximity fuze

DOEpatents

Harrison, T.R.

1987-07-10

A proximity fuze system includes an optical ranging apparatus, a detonation circuit controlled by the optical ranging apparatus, and an explosive charge detonated by the detonation circuit. The optical ranging apparatus includes a pulsed laser light source for generating target ranging light pulses and optical reference light pulses. A single lens directs ranging pulses to a target and collects reflected light from the target. An optical fiber bundle is used for delaying the optical reference pulses to correspond to a predetermined distance from the target. The optical ranging apparatus includes circuitry for providing a first signal depending upon the light pulses reflected from the target, a second signal depending upon the light pulses from the optical delay fiber bundle, and an output signal when the first and second signals coincide with each other. The output signal occurs when the distance from the target is equal to the predetermined distance from the target. Additional circuitry distinguishes pulses reflected from the target from background solar radiation. 3 figs.

Proximity fuze

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harrison, T.R.

1987-07-10

A proximity fuze system includes an optical ranging apparatus, a detonation circuit controlled by the optical ranging apparatus, and an explosive charge detonated by the detonation circuit. The optical ranging apparatus includes a pulsed laser light source for generating target ranging light pulses and optical reference light pulses. A single lens directs ranging pulses to a target and collects reflected light from the target. An optical fiber bundle is used for delaying the optical reference pulses to correspond to a predetermined distance from the target. The optical ranging apparatus includes circuitry for providing a first signal depending upon the lightmore » pulses reflected from the target, a second signal depending upon the light pulses from the optical delay fiber bundle, and an output signal when the first and second signals coincide with each other. The output signal occurs when the distance from the target is equal to the predetermined distance from the target. Additional circuitry distinguishes pulses reflected from the target from background solar radiation. 3 figs.« less

Proximity fuze

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harrison, T.R.

1989-08-22

A proximity fuze system is described. It includes an optical ranging apparatus, a detonation circuit controlled by the optical ranging apparatus, and an explosive charge detonated by the detonation circuit. The optical ranging apparatus includes a pulsed laser light source for generating target ranging light pulses and optical reference light pulses. A single lens directs ranging pulses to a target and collects reflected light from the target. An optical fiber bundle is used for delaying the optical reference pulses to correspond to a predetermined distance from the target. The optical ranging apparatus includes circuitry for providing a first signal dependingmore » upon the light pulses reflected from the target, a second signal depending upon the light pulses from the optical delay fiber bundle, and an output signal when the first and second signals coincide with each other. The output signal occurs when the distance from the target is equal to the predetermined distance from the target. Additional circuitry distinguishes pulses reflected from the target from background solar radiation.« less

Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

NASA Astrophysics Data System (ADS)

Zand, Ramtin; DeMara, Ronald F.

2017-12-01

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

The design of infrared information collection circuit based on embedded technology

NASA Astrophysics Data System (ADS)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

The effects of nuclear radiation on Schottky power diodes and power MOSFETs

NASA Astrophysics Data System (ADS)

Kulisek, Jonathan Andrew

NASA is exploring the potential use of nuclear reactors as power sources for future space missions. These missions will require electrical components, consisting of power circuits and semiconductor devices, to be placed in close vicinity to the reactor, in the midst of a high neutron and gamma-ray radiation field. Therefore, the primary goal of this research is to examine the effects of a mixed neutron and gamma-ray radiation field on the static and dynamic electrical performance of power Schottky diodes and power MOSFETs in order to support future design efforts of radiation-hard power semiconductors and circuits. In order to accomplish this, non-radiation hardened commercial power Si and SiC Schottky power diodes, manufactured by International Rectifier and Cree, respectively, were irradiated in the Ohio State University Research Reactor (OSURR), and their degradation in electrical performance was observed using I-V characterization. Key electrical performance parameters were extracted using least squares curve-fits of the corresponding semiconductor physics model equations to the experimental data, and these electrical performance parameters were used to model the diodes in PSpice. A half-wave rectifier circuit containing Cree SiC Schottky diodes, rated for 5 A DC forward current and 1200 V DC blocking voltage, was also tested and modeled in order to determine and analyze changes in overall circuit performance and diode power dissipation as a function of radiation dose. Also, electrical components will be exposed to charged particle radiation from space, such as high energy protons in the Van Allen Radiation Belts surrounding earth. Therefore, the results from this study, with respect to the Si and SiC Schottky power diodes, were compared to results published by NASA, which had tested the same diode models at the Indiana University Cyclotron Facility (IUCF) with a 203 MeV proton beam. The comparison was made on the basis of displacement damage dose, calculated with the aid of MCNPX 2.6.0, a charged particle transport code. From the results of the calculation, it was determined that the response of both the Si and SiC diodes to the OSURR neutron and gamma-ray radiation field could be used to predict the response of the same diodes to the 203 MeV proton beam to a reasonable extent, relative to other published studies employing the same model. In addition, 100 V and 500 V power MOSFETs were irradiated in the OSURR, and their degradation in electrical performance was observed using I-V characterization. Changes in threshold voltage, transconductance parameter, and on-state resistance were observed for both 100 V and 500 V MOSFETs and were attributed to radiation-induced degradation of the SiO2 gate, Si-SiO2 interface, and n- drift layer. Furthermore, diodes and MOSFETs were irradiated and tested in basic power electronic circuits in order to determine the overall circuit response, as well as the dynamic electrical performance characteristics of the diodes and MOSFETs as they are switched from conducting (on) to non-conducting (off) states. All of the Schottky diodes maintained their voltage-blocking capability in the tested circuits, despite substantial radiation-induced increases in series resistance. Also, as radiation dose increased, an increase was observed in the turn-off delay times and turn-off times of the MOSFETs coupled with a decrease in turn-on delay time, which caused an increase in the output voltage in the buck and boost converters of which the MOSFETs were a part. Furthermore, the power dissipation in the MOSFETs during conduction and the over-voltage turn-off transient increased as a function of radiation dose, while the power dissipation during turn-on was essentially unaffected by the radiation.

Implementation Study of Patient-Ready Syringes Containing 25 mg/mL Methotrexate Solution for Use in Treating Ectopic Pregnancy

PubMed Central

Respaud, R.; Gaudy, A. S.; Arlicot, C.; Tournamille, J. F.; Viaud-Massuard, M. C.; Elfakir, C.; Antier, D.

2014-01-01

Background. Ectopic pregnancy (EP) is a significant cause of morbidity and mortality during the first trimester of pregnancy. Small unruptured tubal pregnancies can be treated medically with a single dose of methotrexate (MTX). Objective. The aim of this study was to evaluate the stability of a 25 mg/mL solution of MTX to devise a secure delivery circuit for the preparation and use of this medication in the management of EP. Method. MTX solutions were packaged in polypropylene syringes, stored over an 84-day period, and protected from light either at +2 to +8°C or at 23°C. We assessed the physical and chemical stability of the solutions at various time points over the storage period. A pharmaceutical delivery circuit was implemented that involved the batch preparation of MTX syringes. Results. We show that 25 mg/mL MTX solutions remain stable over an 84-day period under the storage conditions tested. Standard doses were prepared, ranging from 50 mg to 100 mg. The results of this study suggest that MTX syringes can be prepared in advance by the pharmacy, ready to be dispensed at any time that a diagnosis of EP is made. Conclusion. The high stability of a 25 mg/mL MTX solution in polypropylene syringes makes it possible to implement a flexible and cost-effective delivery circuit for ready-to-use preparations of this drug, providing 24-hour access and preventing treatment delays. PMID:24900977

A centre for accommodative vergence motor control

NASA Technical Reports Server (NTRS)

Wilson, D.

1973-01-01

Latencies in accommodation, accommodative-vergence, and pupil-diameter responses to changing accommodation stimuli, as well as latencies in pupil response to light-intensity changes were measured. From the information obtained, a block diagram has been derived that uses the least number of blocks for representing the accommodation, accommodative-vergence, and pupil systems. The signal transmission delays over the various circuits of the model have been determined and compared to known experimental physiological-delay data. The results suggest the existence of a motor center that controls the accommodative vergence and is completely independent of the accommodation system.

Typical effects of laser dazzling CCD camera

NASA Astrophysics Data System (ADS)

Zhang, Zhen; Zhang, Jianmin; Shao, Bibo; Cheng, Deyan; Ye, Xisheng; Feng, Guobin

2015-05-01

In this article, an overview of laser dazzling effect to buried channel CCD camera is given. The CCDs are sorted into staring and scanning types. The former includes the frame transfer and interline transfer types. The latter includes linear and time delay integration types. All CCDs must perform four primary tasks in generating an image, which are called charge generation, charge collection, charge transfer and charge measurement. In camera, the lenses are needed to input the optical signal to the CCD sensors, in which the techniques for erasing stray light are used. And the electron circuits are needed to process the output signal of CCD, in which many electronic techniques are used. The dazzling effects are the conjunct result of light distribution distortion and charge distribution distortion, which respectively derive from the lens and the sensor. Strictly speaking, in lens, the light distribution is not distorted. In general, the lens are so well designed and fabricated that its stray light can be neglected. But the laser is of much enough intensity to make its stray light obvious. In CCD image sensors, laser can induce a so large electrons generation. Charges transfer inefficiency and charges blooming will cause the distortion of the charge distribution. Commonly, the largest signal outputted from CCD sensor is restricted by capability of the collection well of CCD, and can't go beyond the dynamic range for the subsequent electron circuits maintaining normal work. So the signal is not distorted in the post-processing circuits. But some techniques in the circuit can make some dazzling effects present different phenomenon in final image.

A Sharp methodology for VLSI layout

NASA Astrophysics Data System (ADS)

Bapat, Shekhar

1993-01-01

The layout problem for VLSI circuits is recognized as a very difficult problem and has been traditionally decomposed into the several seemingly independent sub-problems of placement, global routing, and detailed routing. Although this structure achieves a reduction in programming complexity, it is also typically accompanied by a reduction in solution quality. Most current placement research recognizes that the separation is artificial, and that the placement and routing problems should be solved ideally in tandem. We propose a new interconnection model, Sharp and an associated partitioning algorithm. The Sharp interconnection model uses a partitioning shape that roughly resembles the musical sharp 'number sign' and makes extensive use of pre-computed rectilinear Steiner trees. The model is designed to generate strategic routing information along with the partitioning results. Additionally, the Sharp model also generates estimates of the routing congestion. We also propose the Sharp layout heuristic that solves the layout problem in its entirety. The Sharp layout heuristic makes extensive use of the Sharp partitioning model. The use of precomputed Steiner tree forms enables the method to model accurately net characteristics. For example, the Steiner tree forms can model both the length of the net and more importantly its route. In fact, the tree forms are also appropriate for modeling the timing delays of nets. The Sharp heuristic works to minimize both the total layout area by minimizing total net length (thus reducing the total wiring area), and the congestion imbalances in the various channels (thus reducing the unused or wasted channel area). Our heuristic uses circuit element movements amongst the different partitioning blocks and selection of alternate minimal Steiner tree forms to achieve this goal. The objective function for the algorithm can be modified readily to include other important circuit constraints like propagation delays. The layout technique first computes a very high-level approximation of the layout solution (i.e., the positions of the circuit elements and the associated net routes). The approximate solution is alternately refined, objective function. The technique creates well defined sub-problems and offers intermediary steps that can be solved in parallel, as well as a parallel mechanism to merge the sub-problem solutions.

A Photogate Flash Trigger and a Demonstration of Inertia.

ERIC Educational Resources Information Center

Winters, Loren

1992-01-01

Describes a photogate electronic flash trigger that synchronizes flash discharge with high-speed events. Presents a photographic study of a high-speed collision demonstrating the passage of a BB through an elastic strip. Provides the schematic of the delay circuit utilized in the trigger. (MDH)

Delay of cognitive gamma responses in Alzheimer's disease

PubMed Central

Başar, Erol; Emek-Savaş, Derya Durusu; Güntekin, Bahar; Yener, Görsev G.

2016-01-01

Event-related oscillations (EROs) reflect cognitive brain dynamics, while sensory-evoked oscillations (SEOs) reflect sensory activities. Previous reports from our lab have shown that those with Alzheimer's disease (AD) or mild cognitive impairment (MCI) have decreased activity and/or coherence in delta, theta, alpha and beta cognitive responses. In the current study, we investigated gamma responses in visual SEO and ERO in 15 patients with AD and in 15 age-, gender- and education-matched healthy controls. The following parameters were analyzed over the parietal-occipital regions in both groups: (i) latency of the maximum gamma response over a 0–800 ms time window; (ii) the maximum peak-to-peak amplitudes for each participant's averaged SEO and ERO gamma responses in 3 frequency ranges (25–30, 30–35, 40–48 Hz); and (iii) the maximum peak-to-peak amplitudes for each participant's averaged SEO and ERO gamma responses over a 0–800 ms time block containing four divided time windows (0–200, 200–400, 400–600, and 600–800 ms). There were main group effects in terms of both latency and peak-to-peak amplitudes of gamma ERO. However, peak-to-peak gamma ERO amplitude differences became noticeable only when the time block was divided into four time windows. SEO amplitudes in the 25–30 Hz frequency range of the 0–200 ms time window over the left hemisphere were greater in the healthy controls than in those with AD. Gamma target ERO latency was delayed up to 138 ms in AD patients when compared to healthy controls. This finding may be an effect of lagged neural signaling in cognitive circuits, which is reflected by the delayed gamma responses in those with AD. Based on the results of this study, we propose that gamma responses should be examined in a more detailed fashion using multiple frequency and time windows. PMID:26937378

Programmable Pulser

NASA Technical Reports Server (NTRS)

Baumann, Eric; Merolla, Anthony

1988-01-01

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Communications processor for C3 analysis and wargaming

NASA Astrophysics Data System (ADS)

Clark, L. N.; Pless, L. D.; Rapp, R. L.

1982-03-01

This thesis developed the software capability to allow the investigation of c3 problems, procedures and methodologies. The resultant communications model, that while independent of a specific wargame, is currently implemented in conjunction with the McClintic Theater Model. It provides a computerized message handling system (C3 Model) which allows simulation of communication links (circuits) with user-definable delays; garble and loss rates; and multiple circuit types, addresses, and levels of command. It is designed to be used for test and evaluation of command and control problems in the areas of organizational relationships, communication networks and procedures, and combat doctrine or tactics.

Commutated automatic gain control system

NASA Technical Reports Server (NTRS)

Yost, S. R.

1982-01-01

A commutated automatic gain control (AGC) system was designed and built for a prototype Loran C receiver. The receiver uses a microcomputer to control a memory aided phase-locked loop (MAPLL). The microcomputer also controls the input/output, latitude/longitude conversion, and the recently added AGC system. The circuit designed for the AGC is described, and bench and flight test results are presented. The AGC circuit described actually samples starting at a point 40 microseconds after a zero crossing determined by the software lock pulse ultimately generated by a 30 microsecond delay and add network in the receiver front end envelope detector.

The design and hardware implementation of a low-power real-time seizure detection algorithm

NASA Astrophysics Data System (ADS)

Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

2009-10-01

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

Low jitter RF distribution system

DOEpatents

Wilcox, Russell; Doolittle, Lawrence; Huang, Gang

2012-09-18

A timing signal distribution system includes an optical frequency stabilized laser signal amplitude modulated at an rf frequency. A transmitter box transmits a first portion of the laser signal and receive a modified optical signal, and outputs a second portion of the laser signal and a portion of the modified optical signal. A first optical fiber carries the first laser signal portion and the modified optical signal, and a second optical fiber carries the second portion of the laser signal and the returned modified optical signal. A receiver box receives the first laser signal portion, shifts the frequency of the first laser signal portion outputs the modified optical signal, and outputs an electrical signal on the basis of the laser signal. A detector at the end of the second optical fiber outputs a signal based on the modified optical signal. An optical delay sensing circuit outputs a data signal based on the detected modified optical signal. An rf phase detect and correct signal circuit outputs a signal corresponding to a phase stabilized rf signal based on the data signal and the frequency received from the receiver box.

Formation of retinal direction-selective circuitry initiated by starburst amacrine cell homotypic contact

PubMed Central

Ray, Thomas A; Roy, Suva; Kozlowski, Christopher; Wang, Jingjing; Cafaro, Jon; Hulbert, Samuel W; Wright, Christopher V; Field, Greg D

2018-01-01

A common strategy by which developing neurons locate their synaptic partners is through projections to circuit-specific neuropil sublayers. Once established, sublayers serve as a substrate for selective synapse formation, but how sublayers arise during neurodevelopment remains unknown. Here, we identify the earliest events that initiate formation of the direction-selective circuit in the inner plexiform layer of mouse retina. We demonstrate that radially migrating newborn starburst amacrine cells establish homotypic contacts on arrival at the inner retina. These contacts, mediated by the cell-surface protein MEGF10, trigger neuropil innervation resulting in generation of two sublayers comprising starburst-cell dendrites. This dendritic scaffold then recruits projections from circuit partners. Abolishing MEGF10-mediated contacts profoundly delays and ultimately disrupts sublayer formation, leading to broader direction tuning and weaker direction-selectivity in retinal ganglion cells. Our findings reveal a mechanism by which differentiating neurons transition from migratory to mature morphology, and highlight this mechanism’s importance in forming circuit-specific sublayers. PMID:29611808

Optical Circuit Switched Protocol

NASA Technical Reports Server (NTRS)

Monacos, Steve P. (Inventor)

2000-01-01

The present invention is a system and method embodied in an optical circuit switched protocol for the transmission of data through a network. The optical circuit switched protocol is an all-optical circuit switched network and includes novel optical switching nodes for transmitting optical data packets within a network. Each optical switching node comprises a detector for receiving the header, header detection logic for translating the header into routing information and eliminating the header, and a controller for receiving the routing information and configuring an all optical path within the node. The all optical path located within the node is solely an optical path without having electronic storage of the data and without having optical delay of the data. Since electronic storage of the header is not necessary and the initial header is eliminated by the first detector of the first switching node. multiple identical headers are sent throughout the network so that subsequent switching nodes can receive and read the header for setting up an optical data path.

A four-element end-fire microphone array for acoustic measurements in wind tunnels

NASA Technical Reports Server (NTRS)

Soderman, P. T.; Noble, S. C.

1974-01-01

A prototype four-element end-fire microphone array was designed and built for evaluation as a directional acoustic receiver for use in large wind tunnels. The microphone signals were digitized, time delayed, summed, and reconverted to analog form in such a way as to create a directional response with the main lobe along the array axis. The measured array directivity agrees with theoretical predictions confirming the circuit design of the electronic control module. The array with 0.15 m (0.5 ft) microphone spacing rejected reverberations and background noise in the Ames 40- by 80-foot wind tunnel by 5 to 12 db for frequencies above 400 Hz.

Interactive coupling of electronic and optical man-made devices to biological systems

NASA Astrophysics Data System (ADS)

Ozden, Ilker

Fireflies blink synchronously, lasers are "mode-locked" for amplification, cardiac pacemaker cells maintain a steady heartbeat, and crickets chirps get in step. These are examples of coupled oscillators. Coupled non-linear limit-cycle oscillator models are used extensively to provide information about the collective behavior of many physical and biological systems. Depending on the system parameters, namely, the coupling coefficient and the time delay in the coupling, these coupled limit-cycle oscillator exhibit several interesting phenomena; they either synchronize to a common frequency, or oscillate completely independent of each other, or drag each other to a standstill i.e., show "amplitude death". Many neuronal systems exhibit synchronized limit-cycle oscillations in network of electrically coupled cells. The inferior olivary (IO) neuron is an example of such a system. The inferior olive has been widely studied by neuroscientists as it exhibits spontaneous oscillations in its membrane potential, typically in the range of 1--10 Hz. Located in the medulla, the inferior olive is believed to form the neural basis for precise timing and learning in motor circuits by making strong synaptic connections onto Purkinjee cells in the cerebellum. In this thesis work, we report on work, which focuses on the implementation and study of coupling of a biological circuit, which is the inferior olivary system, with a man-made electronic oscillator, the so-called Chua's circuit. We were able to study the interaction between the two oscillators over a wide range coupling conditions. With increasing coupling strength, the oscillators become phase-locked, or synchronized, but with a phase relationship which is either in- or out-of-phase depending on the detailed adjustment in the coupling. Finally, the coupled system reaches the conditions for amplitude death, a rather fundamental result given that the interaction has taken place between purely biological and man-made circuit elements.

2D particle-in-cell simulation of the entire process of surface flashover on insulator in vacuum

NASA Astrophysics Data System (ADS)

Wang, Hongguang; Zhang, Jianwei; Li, Yongdong; Lin, Shu; Zhong, Pengfeng; Liu, Chunliang

2018-04-01

With the introduction of an external circuit model and a gas desorption model, the surface flashover on the plane insulator-vacuum interface perpendicular to parallel electrodes is simulated by a Particle-In-Cell method. It can be seen from simulations that when the secondary electron emission avalanche (SEEA) occurs, the current sharply increases because of the influence of the insulator surface charge on the cathode field emission. With the introduction of the gas desorption model, the current keeps on increasing after SEEA, and then the feedback of the external circuit causes the voltage between the two electrodes to decrease. The cathode emission current decreases, while the anode current keeps growing. With the definition that flashover occurs when the diode voltage drops by more than 20%, we obtained the simulated flashover voltage which agrees with the experimental value with the use of the field enhancement factor β = 145 and the gas molecule desorption coefficient γ=0.25 . From the simulation results, we can also see that the time delay of flashover decreases exponentially with voltage. In addition, from the gas desorption model, the gas density on the insulator surface is found to be proportional to the square of the gas desorption rate and linear with time.

Design and Development of a Series Switch for High Voltage in RF Heating

NASA Astrophysics Data System (ADS)

Patel, Himanshu K.; Shah, Deep; Thacker, Mauli; Shah, Atman

2013-02-01

Plasma is the fourth state of matter. To sustain plasma in its ionic form very high temperature is essential. RF heating systems are used to provide the required temperature. Arching phenomenon in these systems can cause enormous damage to the RF tube. Heavy current flows across the anode-cathode junction, which need to be suppressed in minimal time for its protection. Fast-switching circuit breakers are used to cut-off the load from the supply in cases of arching. The crowbar interrupts the connection between the high voltage power supply (HVPS) and the RF tube for a temporary period between which the series switch has to open. The crowbar shunts the current across the load but in the process leads to short circuiting the HVPS. Thus, to protect the load as well as the HVPS a series switch is necessary. This paper presents the design and development of high voltage Series Switch for the high power switching applications. Fiber optic based Optimum triggering scheme is designed and tested to restrict the time delay well within the stipulated limits. The design is well supported with the experimental results for the whole set-up along with the series switch at various voltage level before its approval for operation at 5.2 kV.

Delayed stabilization of dendritic spines in fragile X mice.

PubMed

Cruz-Martín, Alberto; Crespo, Michelle; Portera-Cailliau, Carlos

2010-06-09

Fragile X syndrome (FXS) causes mental impairment and autism through transcriptional silencing of the Fmr1 gene, resulting in the loss of the RNA-binding protein fragile X mental retardation protein (FMRP). Cortical pyramidal neurons in affected individuals and Fmr1 knock-out (KO) mice have an increased density of dendritic spines. The mutant mice also show defects in synaptic and experience-dependent circuit plasticity, which are known to be mediated in part by dendritic spine dynamics. We used in vivo time-lapse imaging with two-photon microscopy through cranial windows in male and female neonatal mice to test the hypothesis that dynamics of dendritic protrusions are altered in KO mice during early postnatal development. We find that layer 2/3 neurons from wild-type mice exhibit a rapid decrease in dendritic spine dynamics during the first 2 postnatal weeks, as immature filopodia are replaced by mushroom spines. In contrast, KO mice show a developmental delay in the downregulation of spine turnover and in the transition from immature to mature spine subtypes. Blockade of metabotropic glutamate receptor (mGluR) signaling, which reverses some adult phenotypes of KO mice, accentuated this immature protrusion phenotype in KO mice. Thus, absence of FMRP delays spine stabilization and dysregulated mGluR signaling in FXS may partially normalize this early synaptic defect.

The role of muscarinic cholinergic signaling in cost-benefit decision making

NASA Astrophysics Data System (ADS)

Fobbs, Wambura

Animals regularly face decisions that affect both their immediate success and long term survival. Such decisions typically involve some form of cost-benefit analysis and engage a number of high level cognitive processes, including learning, memory and motivational influences. While decision making has been a focus of study for over a century, it's only in the last 20 years that researchers have begun to identify functional neural circuits that subserve different forms of cost-benefit decision making. Even though the cholinergic system is both functionally and anatomically positioned to modulate cost-benefit decision circuits, the contribution of the cholinergic system to decision making has been little studied. In this thesis, I investigated the cognitive and neural contribution of muscarinic cholinergic signaling to cost-benefit decision making. I, first, re-examined the effects of systemic administration of 0.3 mg/kg atropine on delay and probability discounting tasks and found that blockade of muscarinic acetylcholine receptors by atropine induced suboptimal choices (impulsive and risky) in both tasks. Since the effect on delay discounting was restricted to the No Cue version of the delay discounting task, I concluded that muscarinic cholinergic signaling mediates both forms of cost-benefit decision making and is selectively engaged when decisions require valuation of reward options whose costs are not externally signified. Second, I assessed the impact of inactivating the nucleus basalis (NBM) on both forms decision making and the effect of injecting atropine locally into the orbitofrontal cortex (OFC), basolateral amygdala (BLA), or nucleus accumbens (NAc) core during the No Cue version of the delay discounting task. I discovered that although NBM inactivation failed to affect delay discounting, it induced risk aversion in the probability discounting task; and blockade of intra- NAc core, but not intra-OFC or intra-BLA, muscarinic cholinergic signaling lead to increased choice of the delayed reward. While those findings implicate the NBM in supporting risky choices and intra-NAc core muscarinic signaling in discouraging delayed choice, more work is needed to fully elucidate the underlying mechanisms.

Fiber Optic Wink-around Speed of Light Experiment.

ERIC Educational Resources Information Center

Blackburn, James A.

1980-01-01

Describes an experiment in which a recycling oscillator has been designed having a fiber optic data link that closes the loop. Outlines the use of this wink-around system to determine the speed of light and suggests additional application for measuring integrated circuit propagation delays to subnanosecond resolution. (GS)

A linearization time-domain CMOS smart temperature sensor using a curvature compensation oscillator.

PubMed

Chen, Chun-Chi; Chen, Hao-Wen

2013-08-28

This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a -40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT). Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-mm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of -1.2 to 0.2 °C is achieved in an operation range of -40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 mW at a sample rate of 10 samples/s.

Motion-compensated detection of heart rate based on the time registration adaptive filter

NASA Astrophysics Data System (ADS)

Yang, Lei; Zhou, Jinsong; Jing, Juanjuan; Li, Yacan; Wei, Lidong; Feng, Lei; He, Xiaoying; Bu, Meixia; Fu, Xilu

2018-01-01

A non-contact heart rate detection method based on the dual-wavelength technique is proposed and demonstrated experimentally. The heart rate is obtained based on the PhotoPlethysmoGraphy (PPG). Each detection module uses the reflection detection probe which is composed of the LED and the photodiode. It is a well-known fact that the differences in the circuits of two detection modules result in different responses of two modules for motion artifacts. It will cause a time delay between the two signals. This poses a great challenge to compensate the motion artifacts during measurements. In order to solve this problem, we have firstly used the time registration and translated the signals to ensure that the two signals are consistent in time domain. Then the adaptive filter is used to compensate the motion artifacts. Moreover, the data obtained by using this non-contact detection system is compared with those of the conventional finger blood volume pulse (BVP) sensor by simultaneously measuring the heart rate of the subject. During the experiment, the left hand remains stationary and is detected by a conventional finger BVP sensor. Meanwhile, the moving palm of right hand is detected by the proposed system. The data obtained from the proposed non-contact system are consistent and comparable with that of the BVP sensor. This method can effectively suppress the interference caused by the two circuit differences and successfully compensate the motion artifacts. This technology can be used in medical and daily heart rate measurement.

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

NASA Astrophysics Data System (ADS)

Moharrami, Elham; Navimipour, Nima Jafari

2018-04-01

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.

Evaluation of left ventricular scar identification from contrast enhanced magnetic resonance imaging for guidance of ventricular catheter ablation therapy

NASA Astrophysics Data System (ADS)

Rettmann, M. E.; Lehmann, H. I.; Johnson, S. B.; Packer, D. L.

2016-03-01

Patients with ventricular arrhythmias typically exhibit myocardial scarring, which is believed to be an important anatomic substrate for reentrant circuits, thereby making these regions a key target in catheter ablation therapy. In ablation therapy, a catheter is guided into the left ventricle and radiofrequency energy is delivered into the tissue to interrupt arrhythmic electrical pathways. Low bipolar voltage regions are typically localized during the procedure through point-by-point construction of an electroanatomic map by sampling the endocardial surface with the ablation catheter and are used as a surrogate for myocardial scar. This process is time consuming, requires significant skill, and has the potential to miss low voltage sites. This has led to efforts to quantify myocardial scar preoperatively using delayed, contrast-enhanced MRI. In this paper, we evaluate the utility of left ventricular scar identification from delayed contrast enhanced magnetic resonance imaging for guidance of catheter ablation of ventricular arrhythmias. Myocardial infarcts were created in three canines followed by a delayed, contrast enhanced MRI scan and electroanatomic mapping. The left ventricle and myocardial scar is segmented from preoperative MRI images and sampled points from the procedural electroanatomical map are registered to the segmented endocardial surface. Sampled points with low bipolar voltage points visually align with the segmented scar regions. This work demonstrates the potential utility of using preoperative delayed, enhanced MRI to identify myocardial scarring for guidance of ventricular catheter ablation therapy.

Delay dynamics of neuromorphic optoelectronic nanoscale resonators: Perspectives and applications

NASA Astrophysics Data System (ADS)

Romeira, Bruno; Figueiredo, José M. L.; Javaloyes, Julien

2017-11-01

With the recent exponential growth of applications using artificial intelligence (AI), the development of efficient and ultrafast brain-like (neuromorphic) systems is crucial for future information and communication technologies. While the implementation of AI systems using computer algorithms of neural networks is emerging rapidly, scientists are just taking the very first steps in the development of the hardware elements of an artificial brain, specifically neuromorphic microchips. In this review article, we present the current state of the art of neuromorphic photonic circuits based on solid-state optoelectronic oscillators formed by nanoscale double barrier quantum well resonant tunneling diodes. We address, both experimentally and theoretically, the key dynamic properties of recently developed artificial solid-state neuron microchips with delayed perturbations and describe their role in the study of neural activity and regenerative memory. This review covers our recent research work on excitable and delay dynamic characteristics of both single and autaptic (delayed) artificial neurons including all-or-none response, spike-based data encoding, storage, signal regeneration and signal healing. Furthermore, the neural responses of these neuromorphic microchips display all the signatures of extended spatio-temporal localized structures (LSs) of light, which are reviewed here in detail. By taking advantage of the dissipative nature of LSs, we demonstrate potential applications in optical data reconfiguration and clock and timing at high-speeds and with short transients. The results reviewed in this article are a key enabler for the development of high-performance optoelectronic devices in future high-speed brain-inspired optical memories and neuromorphic computing.

Delay dynamics of neuromorphic optoelectronic nanoscale resonators: Perspectives and applications.

PubMed

Romeira, Bruno; Figueiredo, José M L; Javaloyes, Julien

2017-11-01

With the recent exponential growth of applications using artificial intelligence (AI), the development of efficient and ultrafast brain-like (neuromorphic) systems is crucial for future information and communication technologies. While the implementation of AI systems using computer algorithms of neural networks is emerging rapidly, scientists are just taking the very first steps in the development of the hardware elements of an artificial brain, specifically neuromorphic microchips. In this review article, we present the current state of the art of neuromorphic photonic circuits based on solid-state optoelectronic oscillators formed by nanoscale double barrier quantum well resonant tunneling diodes. We address, both experimentally and theoretically, the key dynamic properties of recently developed artificial solid-state neuron microchips with delayed perturbations and describe their role in the study of neural activity and regenerative memory. This review covers our recent research work on excitable and delay dynamic characteristics of both single and autaptic (delayed) artificial neurons including all-or-none response, spike-based data encoding, storage, signal regeneration and signal healing. Furthermore, the neural responses of these neuromorphic microchips display all the signatures of extended spatio-temporal localized structures (LSs) of light, which are reviewed here in detail. By taking advantage of the dissipative nature of LSs, we demonstrate potential applications in optical data reconfiguration and clock and timing at high-speeds and with short transients. The results reviewed in this article are a key enabler for the development of high-performance optoelectronic devices in future high-speed brain-inspired optical memories and neuromorphic computing.

Measurement of the response time of the delay window for the neutron converter of the SPIRAL2 project

NASA Astrophysics Data System (ADS)

Acosta, G.; Andre, T.; Bermudez, J.; Blinov, M. F.; Jamet, C.; Logatchev, P. V.; Semenov, Y. I.; Starostenko, A. A.; Tecchio, L. B.; Tsyganov, A. S.; Udup, E.; Vasquez, J.

2014-09-01

Research and development of a safety system for the SPIRAL2 facility has been conceived to protect the UCx target from a possible interaction with the 200 kW deuteron beam. The system called "delay window" (DW) is designed as an integral part of the neutron converter module and is located in between the neutron converter and the fission target. The device has been designed as a barrier, located directly behind the neutron converter on the axis of the deuteron beam, with the purpose of "delaying" the eventual interaction of the deuteron beam with the UCx target in case of a failure of the neutron converter. The "delay" must be long enough to allow the interlock to react and safely stop the beam operation, before the beam will reach the UCx target. The working concept of the DW is based on the principle of the electrical fuse. Electrically insulated wires placed on the surface of a Tantalum disk assure a so called "free contact", normally closed to an electronic circuit located on the HV platform, far from the radioactive environment. The melting temperature of the wires is much less than Tantalum. Once the beam is impinging on the disk, one or more wires are melted and the "free contact" is open. A solid state relay is changing its state and a signal is sent to the interlock device. A prototype of the DW has been constructed and tested with an electron beam of power density equivalent to the SPIRAL2 beam. The measured "delay" is 682.5 ms (σ=116 ms), that is rather long in comparison to the intrinsic delays introduced by the detectors itself (2 ms) and by the associated electronic devices (120 ns). The experimental results confirm that, in the case of a failure of the neutron converter, the DW as conceived is enable to withstand the beam power for a period of time sufficiently long to safely shut down the SPIRAL2 accelerator.

Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover

NASA Astrophysics Data System (ADS)

Bao, Zhiguo; Watanabe, Takahiro

Evolvable hardware (EHW) is a new research field about the use of Evolutionary Algorithms (EAs) to construct electronic systems. EHW refers in a narrow sense to use evolutionary mechanisms as the algorithmic drivers for system design, while in a general sense to the capability of the hardware system to develop and to improve itself. Genetic Algorithm (GA) is one of typical EAs. We propose optimal circuit design by using GA with parameterized uniform crossover (GApuc) and with fitness function composed of circuit complexity, power, and signal delay. Parameterized uniform crossover is much more likely to distribute its disruptive trials in an unbiased manner over larger portions of the space, then it has more exploratory power than one and two-point crossover, so we have more chances of finding better solutions. Its effectiveness is shown by experiments. From the results, we can see that the best elite fitness, the average value of fitness of the correct circuits and the number of the correct circuits of GApuc are better than that of GA with one-point crossover or two-point crossover. The best case of optimal circuits generated by GApuc is 10.18% and 6.08% better in evaluating value than that by GA with one-point crossover and two-point crossover, respectively.

The importance of explicitly mapping instructional analogies in science education

NASA Astrophysics Data System (ADS)

Asay, Loretta Johnson

Analogies are ubiquitous during instruction in science classrooms, yet research about the effectiveness of using analogies has produced mixed results. An aspect seldom studied is a model of instruction when using analogies. The few existing models for instruction with analogies have not often been examined quantitatively. The Teaching With Analogies (TWA) model (Glynn, 1991) is one of the models frequently cited in the variety of research about analogies. The TWA model outlines steps for instruction, including the step of explicitly mapping the features of the source to the target. An experimental study was conducted to examine the effects of explicitly mapping the features of the source and target in an analogy during computer-based instruction about electrical circuits. Explicit mapping was compared to no mapping and to a control with no analogy. Participants were ninth- and tenth-grade biology students who were each randomly assigned to one of three conditions (no analogy module, analogy module, or explicitly mapped analogy module) for computer-based instruction. Subjects took a pre-test before the instruction, which was used to assign them to a level of previous knowledge about electrical circuits for analysis of any differential effects. After the instruction modules, students took a post-test about electrical circuits. Two weeks later, they took a delayed post-test. No advantage was found for explicitly mapping the analogy. Learning patterns were the same, regardless of the type of instruction. Those who knew the least about electrical circuits, based on the pre-test, made the most gains. After the two-week delay, this group maintained the largest amount of their gain. Implications exist for science education classrooms, as analogy use should be based on research about effective practices. Further studies are suggested to foster the building of research-based models for classroom instruction with analogies.

A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module

NASA Astrophysics Data System (ADS)

Nasir, Z.; Ruslan, S. H.

2017-08-01

A sample and hold (S/H) block is typically used as an analogue to digital interface in the analogue to digital converter (ADC) system. Since ADC is widely used in processing signals, the power consumption of the ADC must be lowered to conserve energy. Therefore the S/H circuit must be of a low powered too. Sampling phase and hold phase are the two phases of the operation cycle of the S/H circuit. Switched capacitor (SC) techniques have been developed in order to allow the integration on a single silicon chip of both digital and analogue functions. By controlling switches around the SC, the SC circuit works by passing charge into and out of a capacitor. SC circuits are suitable for on chip implementations because they replace a resistor with switches and capacitors. In this research, a closed-loop sample and hold circuit based on SC is designed and simulated with Cadence EDA tools. The schematic, layout, and simulation of the circuit is done using generic Silterra 130 nm technology file. All the analysis is done using Virtuoso Analog Design Environment. Layout and schematic are drawn using Virtuoso Schematic Editor and Virtuoso Layout Editor, Calibre is used for post layout simulation. The closed loop S/H circuit based on SC is successfully designed and able to sample and hold the analogue input waveform. The power consumption of the circuit is 0.919 mW and the propagation delay is 64.96 ps.

Demonstrator study for micro-ranging-laser device

NASA Astrophysics Data System (ADS)

Henkel, Hartmut; Bernhardt, Bodo; Pereira do Carmo, J.

2017-11-01

Within ESA's Innovation Triangle Initiative (ITI) a demonstrator breadboard for a micro-ranging-laser device "MYLRAD" has been developed. Its working principle is the measurement of the round-trip delay time of a laser beam as a phase shift. The demonstrator consists of the laser diode (30 mW, square wave AM), optics, APD detector, narrowband preamplifier, limiter, and a phase digitiser based on a novel noise-shaping synchroniser (NSS) circuit; this works without ADCs and can be built from rad-hard components for space. The system timing and the digitiser algorithm are performed by an FPGA. The demonstrator has been tested at ranges from 1 m to 30 m. With a static non-cooperative target an RMS noise of 1 mm at a result rate of 60 Hz was reached. The demonstrator needs less than 2.5 W power.

Computation of interaural time difference in the owl's coincidence detector neurons.

PubMed

Funabiki, Kazuo; Ashida, Go; Konishi, Masakazu

2011-10-26

Both the mammalian and avian auditory systems localize sound sources by computing the interaural time difference (ITD) with submillisecond accuracy. The neural circuits for this computation in birds consist of axonal delay lines and coincidence detector neurons. Here, we report the first in vivo intracellular recordings from coincidence detectors in the nucleus laminaris of barn owls. Binaural tonal stimuli induced sustained depolarizations (DC) and oscillating potentials whose waveforms reflected the stimulus. The amplitude of this sound analog potential (SAP) varied with ITD, whereas DC potentials did not. The amplitude of the SAP was correlated with firing rate in a linear fashion. Spike shape, synaptic noise, the amplitude of SAP, and responsiveness to current pulses differed between cells at different frequencies, suggesting an optimization strategy for sensing sound signals in neurons tuned to different frequencies.

Design of optical axis jitter control system for multi beam lasers based on FPGA

NASA Astrophysics Data System (ADS)

Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

2018-02-01

A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

High pulse rate high resolution optical radar system

NASA Technical Reports Server (NTRS)

Goss, W. C.; Burns, R. H.; Chi, K. (Inventor)

1973-01-01

The system is composed of an optical cavity with a laser and a mode locking means to build up an optical pulse. An optical switch is also provided within the cavity to convert the polarization of the optical pulse generated within the cavity. The optical switch comprises an electro-optical crystal driven by a time delayed driver circuit which is triggered by a coincident signal made from an optical pulse signal and a gating pulse signal. The converted optical pulse strikes a polarization sensitive prism and is deflected out of the cavity toward the pending target in the form of a pulse containing most of the optical energy generated by the laser in the pulse build-up period. After striking the target, the reflected energy is picked up by a transceiver with the total travel time of the pulse being recorded.

Simulation Approach for Timing Analysis of Genetic Logic Circuits.

PubMed

Baig, Hasan; Madsen, Jan

2017-07-21

Constructing genetic logic circuits is an application of synthetic biology in which parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by an appropriate concentration of certain proteins or by different genetic components. These logic circuits work in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits, a capability that we believe will be important for design automation in synthetic biology.

Genetic programs constructed from layered logic gates in single cells

PubMed Central

Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.

2014-01-01

Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931

True-time-delay photonic beamformer for an L-band phased array radar

NASA Astrophysics Data System (ADS)

Zmuda, Henry; Toughlian, Edward N.; Payson, Paul M.; Malowicki, John E.

1995-10-01

The problem of obtaining a true-time-delay photonic beamformer has recently been a topic of great interest. Many interesting and novel approaches to this problem have been studied. This paper examines the design, construction, and testing of a dynamic optical processor for the control of a 20-element phased array antenna operating at L-band (1.2-1.4 GHz). The approach taken here has several distinct advantages. The actual optical control is accomplished with a class of spatial light modulator known as a segmented mirror device (SMD). This allows for the possibility of controlling an extremely large number (tens of thousands) of antenna elements using integrated circuit technology. The SMD technology is driven by the HDTV and laser printer markets so ultimate cost reduction as well as technological improvements are expected. Optical splitting is efficiently accomplished using a diffractive optical element. This again has the potential for use in antenna array systems with a large number of radiating elements. The actual time delay is achieved using a single acousto-optic device for all the array elements. Acousto-optic device technologies offer sufficient delay as needed for a time steered array. The topological configuration is an optical heterodyne system, hence high, potentially millimeter wave center frequencies are possible by mixing two lasers of slightly differing frequencies. Finally, the entire system is spatially integrated into a 3D glass substrate. The integrated system provides the ruggedness needed in most applications and essentially eliminates the drift problems associated with free space optical systems. Though the system is presently being configured as a beamformer, it has the ability to operate as a general photonic signal processing element in an adaptive (reconfigurable) transversal frequency filter configuration. Such systems are widely applicable in jammer/noise canceling systems, broadband ISDN, and for spread spectrum secure communications. This paper also serves as an update of work-in-progress at the Rome Laboratory Photonics Center Optical Beamforming Lab. The multi-faceted aspects of the design and construction of this state-of-the-art beamforming project will be discussed. Experimental results which demonstrate the performance of the system to-date with regard to both maximum delay and resolution over a broad bandwidth are presented.

Existence and global exponential stability of periodic solution to BAM neural networks with periodic coefficients and continuously distributed delays

NASA Astrophysics Data System (ADS)

Zhou, distributed delays [rapid communication] T.; Chen, A.; Zhou, Y.

2005-08-01

By using the continuation theorem of coincidence degree theory and Liapunov function, we obtain some sufficient criteria to ensure the existence and global exponential stability of periodic solution to the bidirectional associative memory (BAM) neural networks with periodic coefficients and continuously distributed delays. These results improve and generalize the works of papers [J. Cao, L. Wang, Phys. Rev. E 61 (2000) 1825] and [Z. Liu, A. Chen, J. Cao, L. Huang, IEEE Trans. Circuits Systems I 50 (2003) 1162]. An example is given to illustrate that the criteria are feasible.

Enhancing synchrony in chaotic oscillators by dynamic relaying

NASA Astrophysics Data System (ADS)

Banerjee, Ranjib; Ghosh, Dibakar; Padmanaban, E.; Ramaswamy, R.; Pecora, L. M.; Dana, Syamal K.

2012-02-01

In a chain of mutually coupled oscillators, the coupling threshold for synchronization between the outermost identical oscillators decreases when a type of impurity (in terms of parameter mismatch) is introduced in the inner oscillator(s). The outer oscillators interact indirectly via dynamic relaying, mediated by the inner oscillator(s). We confirm this enhancing of critical coupling in the chaotic regimes of the Lorenz system, in the Rössler system in the absence of coupling delay, and in the Mackey-Glass system with delay coupling. The enhancing effect is experimentally verified in the electronic circuit of Rössler oscillators.

42 CFR 84.96 - Service time test; closed-circuit apparatus.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 42 Public Health 1 2011-10-01 2011-10-01 false Service time test; closed-circuit apparatus. 84.96...-Contained Breathing Apparatus § 84.96 Service time test; closed-circuit apparatus. (a) The closed-circuit apparatus will be classified according to the length of time it supplies adequate breathing gas to the...

42 CFR 84.96 - Service time test; closed-circuit apparatus.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 42 Public Health 1 2010-10-01 2010-10-01 false Service time test; closed-circuit apparatus. 84.96...-Contained Breathing Apparatus § 84.96 Service time test; closed-circuit apparatus. (a) The closed-circuit apparatus will be classified according to the length of time it supplies adequate breathing gas to the...

Dynamic autofocus for continuous-scanning time-delay-and-integration image acquisition in automated microscopy.

PubMed

Bravo-Zanoguera, Miguel E; Laris, Casey A; Nguyen, Lam K; Oliva, Mike; Price, Jeffrey H

2007-01-01

Efficient image cytometry of a conventional microscope slide means rapid acquisition and analysis of 20 gigapixels of image data (at 0.3-microm sampling). The voluminous data motivate increased acquisition speed to enable many biomedical applications. Continuous-motion time-delay-and-integrate (TDI) scanning has the potential to speed image acquisition while retaining sensitivity, but the challenge of implementing high-resolution autofocus operating simultaneously with acquisition has limited its adoption. We develop a dynamic autofocus system for this need using: 1. a "volume camera," consisting of nine fiber optic imaging conduits to charge-coupled device (CCD) sensors, that acquires images in parallel from different focal planes, 2. an array of mixed analog-digital processing circuits that measure the high spatial frequencies of the multiple image streams to create focus indices, and 3. a software system that reads and analyzes the focus data streams and calculates best focus for closed feedback loop control. Our system updates autofocus at 56 Hz (or once every 21 microm of stage travel) to collect sharply focused images sampled at 0.3x0.3 microm(2)/pixel at a stage speed of 2.3 mms. The system, tested by focusing in phase contrast and imaging long fluorescence strips, achieves high-performance closed-loop image-content-based autofocus in continuous scanning for the first time.

Universal nondestructive mm-wave integrated circuit test fixture

NASA Technical Reports Server (NTRS)

Romanofsky, Robert R. (Inventor); Shalkhauser, Kurt A. (Inventor)

1990-01-01

Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

Correlation-based model of artificially induced plasticity in motor cortex by a bidirectional brain-computer interface.

PubMed

Lajoie, Guillaume; Krouchev, Nedialko I; Kalaska, John F; Fairhall, Adrienne L; Fetz, Eberhard E

2017-02-01

Experiments show that spike-triggered stimulation performed with Bidirectional Brain-Computer-Interfaces (BBCI) can artificially strengthen connections between separate neural sites in motor cortex (MC). When spikes from a neuron recorded at one MC site trigger stimuli at a second target site after a fixed delay, the connections between sites eventually strengthen. It was also found that effective spike-stimulus delays are consistent with experimentally derived spike-timing-dependent plasticity (STDP) rules, suggesting that STDP is key to drive these changes. However, the impact of STDP at the level of circuits, and the mechanisms governing its modification with neural implants remain poorly understood. The present work describes a recurrent neural network model with probabilistic spiking mechanisms and plastic synapses capable of capturing both neural and synaptic activity statistics relevant to BBCI conditioning protocols. Our model successfully reproduces key experimental results, both established and new, and offers mechanistic insights into spike-triggered conditioning. Using analytical calculations and numerical simulations, we derive optimal operational regimes for BBCIs, and formulate predictions concerning the efficacy of spike-triggered conditioning in different regimes of cortical activity.

Correlation-based model of artificially induced plasticity in motor cortex by a bidirectional brain-computer interface

PubMed Central

Lajoie, Guillaume; Kalaska, John F.; Fairhall, Adrienne L.; Fetz, Eberhard E.

2017-01-01

Experiments show that spike-triggered stimulation performed with Bidirectional Brain-Computer-Interfaces (BBCI) can artificially strengthen connections between separate neural sites in motor cortex (MC). When spikes from a neuron recorded at one MC site trigger stimuli at a second target site after a fixed delay, the connections between sites eventually strengthen. It was also found that effective spike-stimulus delays are consistent with experimentally derived spike-timing-dependent plasticity (STDP) rules, suggesting that STDP is key to drive these changes. However, the impact of STDP at the level of circuits, and the mechanisms governing its modification with neural implants remain poorly understood. The present work describes a recurrent neural network model with probabilistic spiking mechanisms and plastic synapses capable of capturing both neural and synaptic activity statistics relevant to BBCI conditioning protocols. Our model successfully reproduces key experimental results, both established and new, and offers mechanistic insights into spike-triggered conditioning. Using analytical calculations and numerical simulations, we derive optimal operational regimes for BBCIs, and formulate predictions concerning the efficacy of spike-triggered conditioning in different regimes of cortical activity. PMID:28151957

Vertical feed stick wood fuel burning furnace system

DOEpatents

Hill, Richard C.

1982-01-01

A stove or furnace for efficient combustion of wood fuel includes a vertical feed combustion chamber (15) for receiving and supporting wood fuel in a vertical attitude or stack. A major upper portion of the combustion chamber column comprises a water jacket (14) for coupling to a source of water or heat transfer fluid for convection circulation of the fluid. The locus (31) of wood fuel combustion is thereby confined to the refractory base of the combustion chamber. A flue gas propagation delay channel (34) extending laterally from the base of the chamber affords delayed travel time in a high temperature refractory environment sufficient to assure substantially complete combustion of the gaseous products of wood burning with forced air prior to extraction of heat in heat exchanger (16). Induced draft draws the fuel gas and air mixture laterally through the combustion chamber and refractory high temperature zone to the heat exchanger and flue. Also included are active sources of forced air and induced draft, multiple circuit couplings for the recovered heat, and construction features in the refractory material substructure and metal component superstructure.

Delay of gratification is associated with white matter connectivity in the dorsal prefrontal cortex: a diffusion tensor imaging study in chimpanzees (Pan troglodytes)

PubMed Central

Latzman, Robert D.; Taglialatela, Jared P.; Hopkins, William D.

2015-01-01

Individual variability in delay of gratification (DG) is associated with a number of important outcomes in both non-human and human primates. Using diffusion tensor imaging (DTI), this study describes the relationship between probabilistic estimates of white matter tracts projecting from the caudate to the prefrontal cortex (PFC) and DG abilities in a sample of 49 captive chimpanzees (Pan troglodytes). After accounting for time between collection of DTI scans and DG measurement, age and sex, higher white matter connectivity between the caudate and right dorsal PFC was found to be significantly associated with the acquisition (i.e. training phase) but not the maintenance of DG abilities. No other associations were found to be significant. The integrity of white matter connectivity between regions of the striatum and the PFC appear to be associated with inhibitory control in chimpanzees, with perturbations on this circuit potentially leading to a variety of maladaptive outcomes. Additionally, results have potential translational implications for understanding the pathophysiology of a number of psychiatric and clinical outcomes in humans. PMID:26041344

The Role of Contingency Awareness in Single-Cue Human Eyeblink Conditioning

ERIC Educational Resources Information Center

Weidemann, Gabrielle; Best, Erin; Lee, Jessica C; Lovibond, Peter F.

2013-01-01

Single-cue delay eyeblink conditioning is presented as a prototypical example of automatic, nonsymbolic learning that is carried out by subcortical circuits. However, it has been difficult to assess the role of cognition in single-cue conditioning because participants become aware of the simple stimulus contingency so quickly. In this experiment…

A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices

NASA Technical Reports Server (NTRS)

Kulkarni, Shriram; Mazumder, Pinaki; Haddad, George I.

1995-01-01

An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations.

Programmable logic construction kits for hyper-real-time neuronal modeling.

PubMed

Guerrero-Rivera, Ruben; Morrison, Abigail; Diesmann, Markus; Pearce, Tim C

2006-11-01

Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

Dynamic Divisive Normalization Predicts Time-Varying Value Coding in Decision-Related Circuits

PubMed Central

LoFaro, Thomas; Webb, Ryan; Glimcher, Paul W.

2014-01-01

Normalization is a widespread neural computation, mediating divisive gain control in sensory processing and implementing a context-dependent value code in decision-related frontal and parietal cortices. Although decision-making is a dynamic process with complex temporal characteristics, most models of normalization are time-independent and little is known about the dynamic interaction of normalization and choice. Here, we show that a simple differential equation model of normalization explains the characteristic phasic-sustained pattern of cortical decision activity and predicts specific normalization dynamics: value coding during initial transients, time-varying value modulation, and delayed onset of contextual information. Empirically, we observe these predicted dynamics in saccade-related neurons in monkey lateral intraparietal cortex. Furthermore, such models naturally incorporate a time-weighted average of past activity, implementing an intrinsic reference-dependence in value coding. These results suggest that a single network mechanism can explain both transient and sustained decision activity, emphasizing the importance of a dynamic view of normalization in neural coding. PMID:25429145

Quality of Service for Real-Time Applications Over Next Generation Data Networks

NASA Technical Reports Server (NTRS)

Ivancic, William; Atiquzzaman, Mohammed; Bai, Haowei; Su, Hongjun; Jain, Raj; Duresi, Arjan; Goyal, Mukyl; Bharani, Venkata; Liu, Chunlei; Kota, Sastri

2001-01-01

This project, which started on January 1, 2000, was funded by NASA Glenn Research Center for duration of one year. The deliverables of the project included the following tasks: Study of QoS mapping between the edge and core networks envisioned in the Next Generation networks will provide us with the QoS guarantees that can be obtained from next generation networks. Buffer management techniques to provide strict guarantees to real-time end-to-end applications through preferential treatment to packets belonging to real-time applications. In particular, use of ECN to help reduce the loss on high bandwidth-delay product satellite networks needs to be studied. Effect of Prioritized Packet Discard to increase goodput of the network and reduce the buffering requirements in the ATM switches. Provision of new IP circuit emulation services over Satellite IP backbones using MPLS will be studied. Determine the architecture and requirements for internetworking ATN and the Next Generation Internet for real-time applications.

Optogenetic Examination of Prefrontal-Amygdala Synaptic Development.

PubMed

Arruda-Carvalho, Maithe; Wu, Wan-Chen; Cummings, Kirstie A; Clem, Roger L

2017-03-15

A brain network comprising the medial prefrontal cortex (mPFC) and amygdala plays important roles in developmentally regulated cognitive and emotional processes. However, very little is known about the maturation of mPFC-amygdala circuitry. We conducted anatomical tracing of mPFC projections and optogenetic interrogation of their synaptic connections with neurons in the basolateral amygdala (BLA) at neonatal to adult developmental stages in mice. Results indicate that mPFC-BLA projections exhibit delayed emergence relative to other mPFC pathways and establish synaptic transmission with BLA excitatory and inhibitory neurons in late infancy, events that coincide with a massive increase in overall synaptic drive. During subsequent adolescence, mPFC-BLA circuits are further modified by excitatory synaptic strengthening as well as a transient surge in feedforward inhibition. The latter was correlated with increased spontaneous inhibitory currents in excitatory neurons, suggesting that mPFC-BLA circuit maturation culminates in a period of exuberant GABAergic transmission. These findings establish a time course for the onset and refinement of mPFC-BLA transmission and point to potential sensitive periods in the development of this critical network. SIGNIFICANCE STATEMENT Human mPFC-amygdala functional connectivity is developmentally regulated and figures prominently in numerous psychiatric disorders with a high incidence of adolescent onset. However, it remains unclear when synaptic connections between these structures emerge or how their properties change with age. Our work establishes developmental windows and cellular substrates for synapse maturation in this pathway involving both excitatory and inhibitory circuits. The engagement of these substrates by early life experience may support the ontogeny of fundamental behaviors but could also lead to inappropriate circuit refinement and psychopathology in adverse situations. Copyright © 2017 the authors 0270-6474/17/372976-10$15.00/0.

Separating OR, SUM, and XOR Circuits.

PubMed

Find, Magnus; Göös, Mika; Järvisalo, Matti; Kaski, Petteri; Koivisto, Mikko; Korhonen, Janne H

2016-08-01

Given a boolean n × n matrix A we consider arithmetic circuits for computing the transformation x ↦ Ax over different semirings. Namely, we study three circuit models: monotone OR-circuits, monotone SUM-circuits (addition of non-negative integers), and non-monotone XOR-circuits (addition modulo 2). Our focus is on separating OR-circuits from the two other models in terms of circuit complexity: We show how to obtain matrices that admit OR-circuits of size O ( n ), but require SUM-circuits of size Ω( n 3/2 /log 2 n ).We consider the task of rewriting a given OR-circuit as a XOR-circuit and prove that any subquadratic-time algorithm for this task violates the strong exponential time hypothesis.

42 CFR 84.95 - Service time test; open-circuit apparatus.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 42 Public Health 1 2011-10-01 2011-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be measured with a breathing machine as described in § 84.88. (b) The open-circuit apparatus will be...

42 CFR 84.95 - Service time test; open-circuit apparatus.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 42 Public Health 1 2010-10-01 2010-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be measured with a breathing machine as described in § 84.88. (b) The open-circuit apparatus will be...

Two-phase flow in the cooling circuit of a cryogenic rocket engine

NASA Astrophysics Data System (ADS)

Preclik, D.

1992-07-01

Transient two-phase flow was investigated for the hydrogen cooling circuit of the HM7 rocket engine. The nuclear reactor code ATHLET/THESEUS was adapted to cryogenics and applied to both principal and prototype experiments for validation and simulation purposes. The cooling circuit two-phase flow simulation focused on the hydrogen prechilling and pump transient phase prior to ignition. Both a single- and a multichannel model were designed and employed for a valve leakage flow, a nominal prechilling flow, and a prechilling with a subsequent pump-transient flow. The latter case was performed in order to evaluate the difference between a nominal and a delayed turbo-pump start-up. It was found that an extension of the nominal prechilling sequence in the order of 1 second is sufficient to finally provide for liquid injection conditions of hydrogen which, as commonly known, is undesirable for smooth ignition and engine starting transients.

A ROIC for Mn(TPP)Cl-DOP-THF-Polyhema PVC membrane modified n-channel Si3N4 ISFET sensitive to histamine.

PubMed

Samah, N L M A; Lee, Khuan Y; Sulaiman, S A; Jarmin, R

2017-07-01

Intolerance of histamine could lead to scombroid poisoning with fatal consequences. Current detection methods for histamine are wet laboratory techniques which employ expensive equipment that depends on skills of seasoned technicians and produces delayed test analysis result. Previous works from our group has established that ISFETs can be adapted for detecting histamine with the use of a novel membrane. However, work to integrate ISFETs with a readout interfacing circuit (ROIC) circuit to display the histamine concentration has not been reported so far. This paper concerns the development of a ROIC specifically to integrate with a Mn(TPP)Cl-DOP-THF-Polyhema PVC membrane modified n-channel Si3N4 ISFET to display the histamine concentration. It embodies the design of constant voltage constant current (CVCC) circuit, amplification circuit and micro-controller based display circuit. A DC millivolt source is used to substitute the membrane modified ISFET as preliminary work. Input is histamine concentration corresponding to the safety level designated by the Food and Drugs Administration (FDA). Results show the CVCC circuit makes the output follows the input and keeps VDS constant. The amplification circuit amplifies the output from the CVCC circuit to the range 2.406-4.888V to integrate with the microcontroller, which is programmed to classify and display the histamine safety level and its corresponding voltage on a LCD panel. The ROIC could be used to produce direct output voltages corresponding to histamine concentrations, for in-situ applications.

Demodulator for carrier transducers

NASA Technical Reports Server (NTRS)

Roller, R. F. (Inventor)

1974-01-01

A carrier type transducer is supplied with a carrier wave via an audio amplifier, a filter, a frequency divider, and an oscillator. The carrier is modulated in accordance with the parameter being measured by the transducer and is fed to the input of a digital data system which may include a voltmeter. The output of the oscillator and the output of each stage of the divider are fed to an AND or a NAND gate and suitable variable and fixed delay circuits to the command input of the digital data system. With this arrangement, the digital data system is commanded to sample at the proper time so that the average voltage of the modulated carrier is measured. It may be utilized with ancillary circuitry for control of the parameter

Development of signal processing system of avalanche photo diode for space observations by Astro-H

NASA Astrophysics Data System (ADS)

Ohno, M.; Goto, K.; Hanabata, Y.; Takahashi, H.; Fukazawa, Y.; Yoshino, M.; Saito, T.; Nakamori, T.; Kataoka, J.; Sasano, M.; Torii, S.; Uchiyama, H.; Nakazawa, K.; Watanabe, S.; Kokubun, M.; Ohta, M.; Sato, T.; Takahashi, T.; Tajima, H.

2013-01-01

Astro-H is the sixth Japanese X-ray space observatory which will be launched in 2014. Two of onboard instruments of Astro-H, Hard X-ray Imager and Soft Gamma-ray Detector are surrounded by many number of large Bismuth Germanate (Bi4Ge3O12; BGO) scintillators. Optimum readout system of scintillation lights from these BGOs are essential to reduce the background signals and achieve high performance for main detectors because most of gamma-rays from out of field-of-view of main detectors or radio-isotopes produced inside them due to activation can be eliminated by anti-coincidence technique using BGO signals. We apply Avalanche Photo Diode (APD) for light sensor of these BGO detectors since their compactness and high quantum efficiency make it easy to design such large number of BGO detector system. For signal processing from APDs, digital filter and other trigger logics on the Field-Programmable Gate Array (FPGA) is used instead of discrete analog circuits due to limitation of circuit implementation area on spacecraft. For efficient observations, we have to achieve as low threshold of anti-coincidence signal as possible by utilizing the digital filtering. In addition, such anti-coincident signals should be sent to the main detector within 5 μs to make it in time to veto the A-D conversion. Considering this requirement and constraint from logic size of FPGA, we adopt two types of filter, 8 delay taps filter with only 2 bit precision coefficient and 16 delay taps filter with 8 bit precision coefficient. The data after former simple filter provides anti-coincidence signal quickly in orbit, and the latter filter is used for detail analysis after the data is down-linked.

Intralimb and Interlimb Cutaneous Reflexes during Locomotion in the Intact Cat.

PubMed

Hurteau, Marie-France; Thibaudier, Yann; Dambreville, Charline; Danner, Simon M; Rybak, Ilya A; Frigon, Alain

2018-04-25

When the foot contacts an obstacle during locomotion, cutaneous inputs activate spinal circuits to ensure dynamic balance and forward progression. In quadrupeds, this requires coordinated reflex responses between the four limbs. Here, we investigated the patterns and phasic modulation of cutaneous reflexes in forelimb and hindlimb muscles evoked by inputs from all four limbs. Five female cats were implanted to record muscle activity and to stimulate the superficial peroneal and superficial radial nerves during locomotion. Stimulating these nerves evoked short-, mid-, and longer-latency excitatory and/or inhibitory responses in all four limbs that were phase-dependent. The largest responses were generally observed during the peak activity of the muscle. Cutaneous reflexes during mid-swing were consistent with flexion of the homonymous limb and accompanied by modification of the stance phases of the other three limbs, by coactivating flexors and extensors and/or by delaying push-off. Cutaneous reflexes during mid-stance were consistent with stabilizing the homonymous limb by delaying and then facilitating its push-off and modifying the support phases of the homolateral and diagonal limbs, characterized by coactivating flexors and extensors, reinforcing extensor activity and/or delaying push-off. The shortest latencies of homolateral and diagonal responses were consistent with fast-conducting disynaptic or trisynaptic pathways. Descending homolateral and diagonal pathways from the forelimbs to the hindlimbs had a higher probability of eliciting responses compared with ascending pathways from the hindlimbs to the forelimbs. Thus, in quadrupeds, intralimb and interlimb reflexes activated by cutaneous inputs ensure dynamic coordination of the four limbs, producing a whole-body response. SIGNIFICANCE STATEMENT The skin contains receptors that, when activated, send inputs to spinal circuits, signaling a perturbation. Rapid responses, or reflexes, in muscles of the contacted limb and opposite homologous limb help maintain balance and forward progression. Here, we investigated reflexes during quadrupedal locomotion in the cat by electrically stimulating cutaneous nerves in each of the four limbs. Functionally, responses appear to modify the trajectory or stabilize the movement of the stimulated limb while modifying the support phase of the other limbs. Reflexes between limbs are mediated by fast-conducting pathways that involve excitatory and inhibitory circuits controlling each limb. The comparatively stronger descending pathways from cervical to lumbar circuits controlling the forelimbs and hindlimbs, respectively, could serve a protective function. Copyright © 2018 the authors 0270-6474/18/384104-19$15.00/0.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

NASA Astrophysics Data System (ADS)

Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

2018-04-01

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Chronic Stress Alters Striosome-Circuit Dynamics, Leading to Aberrant Decision-Making.

PubMed

Friedman, Alexander; Homma, Daigo; Bloem, Bernard; Gibb, Leif G; Amemori, Ken-Ichi; Hu, Dan; Delcasso, Sebastien; Truong, Timothy F; Yang, Joyce; Hood, Adam S; Mikofalvy, Katrina A; Beck, Dirk W; Nguyen, Norah; Nelson, Erik D; Toro Arana, Sebastian E; Vorder Bruegge, Ruth H; Goosens, Ki A; Graybiel, Ann M

2017-11-16

Effective evaluation of costs and benefits is a core survival capacity that in humans is considered as optimal, "rational" decision-making. This capacity is vulnerable in neuropsychiatric disorders and in the aftermath of chronic stress, in which aberrant choices and high-risk behaviors occur. We report that chronic stress exposure in rodents produces abnormal evaluation of costs and benefits resembling non-optimal decision-making in which choices of high-cost/high-reward options are sharply increased. Concomitantly, alterations in the task-related spike activity of medial prefrontal neurons correspond with increased activity of their striosome-predominant striatal projection neuron targets and with decreased and delayed striatal fast-firing interneuron activity. These effects of chronic stress on prefronto-striatal circuit dynamics could be blocked or be mimicked by selective optogenetic manipulation of these circuits. We suggest that altered excitation-inhibition dynamics of striosome-based circuit function could be an underlying mechanism by which chronic stress contributes to disorders characterized by aberrant decision-making under conflict. VIDEO ABSTRACT. Copyright © 2017 Elsevier Inc. All rights reserved.

The Mechanism of Cortico-Striato-Thalamo-Cortical Neurocircuitry in Response Inhibition and Emotional Responding in Attention Deficit Hyperactivity Disorder with Comorbid Disruptive Behavior Disorder.

PubMed

Zhu, Yuncheng; Jiang, Xixi; Ji, Weidong

2018-06-01

The neurocircuitries that constitute the cortico-striato-thalamo-cortical (CSTC) circuit provide a framework for bridging gaps between neuroscience and executive function in attention deficit hyperactivity disorder (ADHD), but it has been difficult to identify the mechanisms for regulating emotional problems from the understanding of ADHD comorbidity with disruptive behavior disorders (DBD). Research based on "cool" and "hot" executive functional theory and the dual pathway models, which are thought of as applied response inhibition and delay aversion, respectively, within the neuropsychological view of ADHD, has shed light on emotional responding before and after decontextualized stimuli, while CSTC circuit-related domains have been suggested to explain the different emotional symptoms of ADHD with or without comorbid DBD. This review discusses the role of abnormal connections in each CSTC circuit, especially in the emotion circuit, which may be responsible for targeted executive dysfunction at the neuroscience level. Thus, the two major domains - abstract thinking (cool) and emotional trait (hot) - trigger the mechanism of onset of ADHD.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

PubMed

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Embedding the dynamics of a single delay system into a feed-forward ring.

PubMed

Klinshov, Vladimir; Shchapin, Dmitry; Yanchuk, Serhiy; Wolfrum, Matthias; D'Huys, Otti; Nekorkin, Vladimir

2017-10-01

We investigate the relation between the dynamics of a single oscillator with delayed self-feedback and a feed-forward ring of such oscillators, where each unit is coupled to its next neighbor in the same way as in the self-feedback case. We show that periodic solutions of the delayed oscillator give rise to families of rotating waves with different wave numbers in the corresponding ring. In particular, if for the single oscillator the periodic solution is resonant to the delay, it can be embedded into a ring with instantaneous couplings. We discover several cases where the stability of a periodic solution for the single unit can be related to the stability of the corresponding rotating wave in the ring. As a specific example, we demonstrate how the complex bifurcation scenario of simultaneously emerging multijittering solutions can be transferred from a single oscillator with delayed pulse feedback to multijittering rotating waves in a sufficiently large ring of oscillators with instantaneous pulse coupling. Finally, we present an experimental realization of this dynamical phenomenon in a system of coupled electronic circuits of FitzHugh-Nagumo type.

Real-Time Phase Correction Based on FPGA in the Beam Position and Phase Measurement System

NASA Astrophysics Data System (ADS)

Gao, Xingshun; Zhao, Lei; Liu, Jinxin; Jiang, Zouyi; Hu, Xiaofang; Liu, Shubin; An, Qi

2016-12-01

A fully digital beam position and phase measurement (BPPM) system was designed for the linear accelerator (LINAC) in Accelerator Driven Sub-critical System (ADS) in China. Phase information is obtained from the summed signals from four pick-ups of the Beam Position Monitor (BPM). Considering that the delay variations of different analog circuit channels would introduce phase measurement errors, we propose a new method to tune the digital waveforms of four channels before summation and achieve real-time error correction. The process is based on the vector rotation method and implemented within one single Field Programmable Gate Array (FPGA) device. Tests were conducted to evaluate this correction method and the results indicate that a phase correction precision better than ± 0.3° over the dynamic range from -60 dBm to 0 dBm is achieved.

Critical period plasticity is disrupted in the barrel cortex of Fmr1 knockout mice

PubMed Central

Harlow, Emily G.; Till, Sally M.; Russell, Theron A.; Wijetunge, Lasani S.; Kind, Peter; Contractor, Anis

2010-01-01

Summary Alterations in sensory processing constitute prominent symptoms of Fragile X syndrome; however, little is known about how disrupted synaptic and circuit development in sensory cortex contributes to these deficits. To investigate how the loss of fragile X mental retardation protein (FMRP) impacts the development of cortical synapses, we examined excitatory thalamocortical synapses in somatosensory cortex during the perinatal critical period in Fmr1 knockout mice. FMRP ablation resulted in dysregulation of glutamatergic signaling maturation. The fraction of silent synapses persisting to later developmental times was increased, there was a temporal delay in the window for synaptic plasticity, while other forms of developmental plasticity were not altered in Fmr1 knockout mice. Our results indicate that FMRP is required for the normal developmental progression of synaptic maturation, and loss of this important RNA binding protein impacts the timing of the critical period for layer IV synaptic plasticity. PMID:20159451

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems

PubMed Central

Chang, Sun-Il

2018-01-01

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm2 and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µVrms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW. PMID:29342103

Minimally-Invasive Neural Interface for Distributed Wireless Electrocorticogram Recording Systems.

PubMed

Chang, Sun-Il; Park, Sung-Yun; Yoon, Euisik

2018-01-17

This paper presents a minimally-invasive neural interface for distributed wireless electrocorticogram (ECoG) recording systems. The proposed interface equips all necessary components for ECoG recording, such as the high performance front-end integrated circuits, a fabricated flexible microelectrode array, and wireless communication inside a miniaturized custom-made platform. The multiple units of the interface systems can be deployed to cover a broad range of the target brain region and transmit signals via a built-in intra-skin communication (ISCOM) module. The core integrated circuit (IC) consists of 16-channel, low-power push-pull double-gated preamplifiers, in-channel successive approximation register analog-to-digital converters (SAR ADC) with a single-clocked bootstrapping switch and a time-delayed control unit, an ISCOM module for wireless data transfer through the skin instead of a power-hungry RF wireless transmitter, and a monolithic voltage/current reference generator to support the aforementioned analog and mixed-signal circuit blocks. The IC was fabricated using 250 nm CMOS processes in an area of 3.2 × 0.9 mm² and achieved the low-power operation of 2.5 µW per channel. Input-referred noise was measured as 5.62 µV rms for 10 Hz to 10 kHz and ENOB of 7.21 at 31.25 kS/s. The implemented system successfully recorded multi-channel neural activities in vivo from a primate and demonstrated modular expandability using the ISCOM with power consumption of 160 µW.

Primary lithium cell life studies

NASA Technical Reports Server (NTRS)

Capulli, John; Donley, Sam; Deligiannis, Frank; Shen, David

1990-01-01

One solution for providing a truly independent power source is to package, within the critical subsystem element, a primary battery that can remain dormant for time periods as long as the mission life, which can be 10-15 years, maximum. When primary power from the spacecraft solar array/battery system is interrupted, the backup battery system, which is connected through a diode to the power input line, would automatically support the load to avoid a power interruption to the critical load for a time period long enough to ensure that ground control could access the satellite and correct the anomaly by sending appropriate commands to the spacecraft. Critical subsystems identified for the application are telemetry and command circuits, volatile computer memory, attitude control circuits, and some critical payloads. Due to volume packaging and weight restrictions that exist on most spacecraft, coupled with the long storage periods required, lithium cell technology was selected for the backup power source. Because of the high energy density (200-400 Wh/kg), long shelf life, and load capability, soluble cathode primary lithium technology was chosen. The most important lithium cell properties that require detail characterization for this application are capacity loss, shelf life, and the voltage delay mechanism. These are functions of storage time and temperature. During storage, a passive film builds up on the lithium electrode. The film protects the lithium electrode from progressive capacity decay but requires time to break down when a load is applied. This phenomenon results in a depressed voltage during the period of film breakdown which can last from fractions of a second to minutes.

Lossless microwave photonic delay line using a ring resonator with an integrated semiconductor optical amplifier

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Zhuang, Leimeng; Boller, Klaus-Jochen; Lowery, Arthur James

2017-06-01

Optical delay lines implemented in photonic integrated circuits (PICs) are essential for creating robust and low-cost optical signal processors on miniaturized chips. In particular, tunable delay lines enable a key feature of programmability for the on-chip processing functions. However, the previously investigated tunable delay lines are plagued by a severe drawback of delay-dependent loss due to the propagation loss in the constituent waveguides. In principle, a serial-connected amplifier can be used to compensate such losses or perform additional amplitude manipulation. However, this solution is generally unpractical as it introduces additional burden on chip area and power consumption, particularly for large-scale integrated PICs. Here, we report an integrated tunable delay line that overcomes the delay-dependent loss, and simultaneously allows for independent manipulation of group delay and amplitude responses. It uses a ring resonator with a tunable coupler and a semiconductor optical amplifier in the feedback path. A proof-of-concept device with a free spectral range of 11.5 GHz and a delay bandwidth in the order of 200 MHz is discussed in the context of microwave photonics and is experimentally demonstrated to be able to provide a lossless delay up to 1.1 to a 5 ns Gaussian pulse. The proposed device can be designed for different frequency scales with potential for applications across many other areas such as telecommunications, LIDAR, and spectroscopy, serving as a novel building block for creating chip-scale programmable optical signal processors.

Development, Integration and Testing of Automated Triggering Circuit for Hybrid DC Circuit Breaker

NASA Astrophysics Data System (ADS)

Kanabar, Deven; Roy, Swati; Dodiya, Chiragkumar; Pradhan, Subrata

2017-04-01

A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed.

Measurement of collective dynamical mass of Dirac fermions in graphene.

PubMed

Yoon, Hosang; Forsythe, Carlos; Wang, Lei; Tombros, Nikolaos; Watanabe, Kenji; Taniguchi, Takashi; Hone, James; Kim, Philip; Ham, Donhee

2014-08-01

Individual electrons in graphene behave as massless quasiparticles. Unexpectedly, it is inferred from plasmonic investigations that electrons in graphene must exhibit a non-zero mass when collectively excited. The inertial acceleration of the electron collective mass is essential to explain the behaviour of plasmons in this material, and may be directly measured by accelerating it with a time-varying voltage and quantifying the phase delay of the resulting current. This voltage-current phase relation would manifest as a kinetic inductance, representing the reluctance of the collective mass to accelerate. However, at optical (infrared) frequencies, phase measurements of current are generally difficult, and, at microwave frequencies, the inertial phase delay has been buried under electron scattering. Therefore, to date, the collective mass in graphene has defied unequivocal measurement. Here, we directly and precisely measure the kinetic inductance, and therefore the collective mass, by combining device engineering that reduces electron scattering and sensitive microwave phase measurements. Specifically, the encapsulation of graphene between hexagonal boron nitride layers, one-dimensional edge contacts and a proximate top gate configured as microwave ground together enable the inertial phase delay to be resolved from the electron scattering. Beside its fundamental importance, the kinetic inductance is found to be orders of magnitude larger than the magnetic inductance, which may be utilized to miniaturize radiofrequency integrated circuits. Moreover, its bias dependency heralds a solid-state voltage-controlled inductor to complement the prevalent voltage-controlled capacitor.

Simple Optoelectronic Feedback in Microwave Oscillators

NASA Technical Reports Server (NTRS)

Maleki, Lute; Iltchenko, Vladimir

2009-01-01

A proposed method of stabilizing microwave and millimeter-wave oscillators calls for the use of feedback in optoelectronic delay lines characterized by high values of the resonance quality factor (Q). The method would extend the applicability of optoelectronic feedback beyond the previously reported class of optoelectronic oscillators that comprise two-port electronic amplifiers in closed loops with high-Q feedback circuits.

Functional differences in bi-level pressure preset ventilators.

PubMed

Highcock, M P; Shneerson, J M; Smith, I E

2001-02-01

The performance of four bilevel positive pressure preset ventilators was compared. The ventilators tested were; BiPAP ST30 (Respironics); Nippy2 (B + D Electrical); Quantum PSV (Healthdyne); and Sullivan VPAP H ST (Resmed). A patient simulator was used to determine the sensitivity of the triggering mechanisms and the responses to a leak within the patient circuit, and to changes in patient effort. Significant differences (p <0.05) between the devices were seen in the trigger delay time and inspiratory trigger pressure. When a leak was introduced into the patient circuit, the fall in tidal volume (VT) was less than ten per cent for each ventilator. The addition of patient effort produced a number of changes in the ventilation delivered. Patient efforts of 0.25 s induced a variable fall in VT. An increase in VT was seen with some ventilators with patient efforts of 1 s but the effect was variable. Trigger failures and subsequent falls in minute volume were seen with the BiPAP and the Nippy2 at the highest respiratory frequency. Differences in the responses of the ventilators are demonstrated that may influence the selection of a ventilator, particularly in the treatment of breathless patients with ventilatory failure.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

PubMed Central

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Quasi-lattice of qubits and its mesoscopic features

NASA Astrophysics Data System (ADS)

Ian, Hou; Liu, Yu-Xi

2014-03-01

In a circuit quantum electrodynamic system, both the size of superconducting qubits and the length scale of the inter-qubit spacing in a chain of such qubits are mesoscopic. As a result, the qubit-field coupling is inhomogeneous. The excitation on the qubits is described by a projection-deformation model and this set of qubits exhibit unique mesoscopic features of what we termed a quasi-lattice. A quasi-lattice in a circuit cavity has a spacing-dependent excitation spectrum. Inhomogeneous coupling giving rise to asynchronously excited qubits, the probability of multi-photon resonance on the quasi-lattice as a whole has increased. This induces simultaneous generations of GHZ-type and W-type entanglements among the qubits. Moreover, the polaritons formed by the mixing of the quasi-lattice excitation and the cavity photon has a selective spontaneous radiation. The spectrum of the radiation has a periodicity governed by the spacing and the variation of the decay rate over the spacing coincides with the cooperation of atoms predicted by Dicke model. We present the theory behinds these effects of the quasi-lattice and discuss how the spacing affects the delay and life time of a superfluorescent pulse arising from it. Supported by Univ. of Macau and FDCT Macau.

Separating OR, SUM, and XOR Circuits☆

PubMed Central

Find, Magnus; Göös, Mika; Järvisalo, Matti; Kaski, Petteri; Koivisto, Mikko; Korhonen, Janne H.

2017-01-01

Given a boolean n × n matrix A we consider arithmetic circuits for computing the transformation x ↦ Ax over different semirings. Namely, we study three circuit models: monotone OR-circuits, monotone SUM-circuits (addition of non-negative integers), and non-monotone XOR-circuits (addition modulo 2). Our focus is on separating OR-circuits from the two other models in terms of circuit complexity: We show how to obtain matrices that admit OR-circuits of size O(n), but require SUM-circuits of size Ω(n3/2/log2n).We consider the task of rewriting a given OR-circuit as a XOR-circuit and prove that any subquadratic-time algorithm for this task violates the strong exponential time hypothesis. PMID:28529379

Photonic integrated circuit optical buffer for packet-switched networks.

PubMed

Burmeister, Emily F; Mack, John P; Poulsen, Henrik N; Masanović, Milan L; Stamenić, Biljana; Blumenthal, Daniel J; Bowers, John E

2009-04-13

A chip-scale optical buffer performs autonomous contention resolution for 40-byte packets with 99% packet recovery. The buffer consists of a fast, InP-based 2 x 2 optical switch and a silica-on-silicon low loss delay loop. The buffer is demonstrated in recirculating operation, but may be reconfigured in feed-forward operation for longer packet lengths. The recirculating buffer provides packet storage in integer multiples of the delay length of 12.86 ns up to 64.3 ns with 98% packet recovery. The buffer is used to resolve contention between two 40 Gb/s packet streams using multiple photonic chip optical buffers.

Displacement sensors using soft magnetostrictive alloys

NASA Astrophysics Data System (ADS)

Hristoforou, E.; Reilly, R. E.

1994-09-01

We report results on the response of a family of displacement sensors, which are based on the magentostrictive delay line (MDL) technique, using current conductors orthogonal to the MDL. Such sensing technique is based on the change of the magnetic circuit at the acoustic stress point of origin due to the displacement of a soft magnetic material above it. Integrated arrays of sensors can be obtained due to the acoustic delay line technique and they can be used as tactile arrays, digitizers or devices for medical applications (gait analysis etc.), while absence of hysteresis and low cost of manufacturing make them competent in this sector of sensor market.

Properties of a Variable-Delay Polarization Modulator

NASA Technical Reports Server (NTRS)

Chuss, David T.; Wollack, Edward J.; Henry, Ross; Hui, Howard; Juarez, Aaron J.; Krenjy, Megan; Moseley, Harvey; Novak, Giles

2011-01-01

We investigate the polarization modulation properties of a variable-delay polarization modulator (VPM). The VPM modulates polarization via a variable separation between a polarizing grid and a parallel mirror. We find that in the limit where the wavelength is much larger than the diameter of the metal wires that comprise the grid, the phase delay derived from the geometric separation between the mirror and the grid is sufficient to characterize the device. However, outside of this range, additional parameters describing the polarizing grid geometry must be included to fully characterize the modulator response. In this paper, we report test results of a VPM at wavelengths of 350 micron and 3 mm. Electromagnetic simulations of wire grid polarizers were performed and are summarized using a simple circuit model that incorporates the loss and polarization properties of the device.

Topological Acoustic Delay Line

NASA Astrophysics Data System (ADS)

Zhang, Zhiwang; Tian, Ye; Cheng, Ying; Wei, Qi; Liu, Xiaojun; Christensen, Johan

2018-03-01

Topological protected wave engineering in artificially structured media is at the frontier of ongoing metamaterials research that is inspired by quantum mechanics. Acoustic analogues of electronic topological insulators have recently led to a wealth of new opportunities in manipulating sound propagation with strikingly unconventional acoustic edge modes immune to backscattering. Earlier fabrications of topological insulators are characterized by an unreconfigurable geometry and a very narrow frequency response, which severely hinders the exploration and design of useful devices. Here we establish topologically protected sound in reconfigurable phononic crystals that can be switched on and off simply by rotating its three-legged "atoms" without altering the lattice structure. In particular, we engineer robust phase delay defects that take advantage of the ultrabroadband reflection-free sound propagation. Such topological delay lines serve as a paradigm in compact acoustic devices, interconnects, and electroacoustic integrated circuits.

Adaptive sequential controller

DOEpatents

El-Sharkawi, Mohamed A.; Xing, Jian; Butler, Nicholas G.; Rodriguez, Alonso

1994-01-01

An adaptive sequential controller (50/50') for controlling a circuit breaker (52) or other switching device to substantially eliminate transients on a distribution line caused by closing and opening the circuit breaker. The device adaptively compensates for changes in the response time of the circuit breaker due to aging and environmental effects. A potential transformer (70) provides a reference signal corresponding to the zero crossing of the voltage waveform, and a phase shift comparator circuit (96) compares the reference signal to the time at which any transient was produced when the circuit breaker closed, producing a signal indicative of the adaptive adjustment that should be made. Similarly, in controlling the opening of the circuit breaker, a current transformer (88) provides a reference signal that is compared against the time at which any transient is detected when the circuit breaker last opened. An adaptive adjustment circuit (102) produces a compensation time that is appropriately modified to account for changes in the circuit breaker response, including the effect of ambient conditions and aging. When next opened or closed, the circuit breaker is activated at an appropriately compensated time, so that it closes when the voltage crosses zero and opens when the current crosses zero, minimizing any transients on the distribution line. Phase angle can be used to control the opening of the circuit breaker relative to the reference signal provided by the potential transformer.

Neural circuit basis of visuo-spatial working memory precision: a computational and behavioral study.

PubMed

Almeida, Rita; Barbosa, João; Compte, Albert

2015-09-01

The amount of information that can be retained in working memory (WM) is limited. Limitations of WM capacity have been the subject of intense research, especially in trying to specify algorithmic models for WM. Comparatively, neural circuit perspectives have barely been used to test WM limitations in behavioral experiments. Here we used a neuronal microcircuit model for visuo-spatial WM (vsWM) to investigate memory of several items. The model assumes that there is a topographic organization of the circuit responsible for spatial memory retention. This assumption leads to specific predictions, which we tested in behavioral experiments. According to the model, nearby locations should be recalled with a bias, as if the two memory traces showed attraction or repulsion during the delay period depending on distance. Another prediction is that the previously reported loss of memory precision for an increasing number of memory items (memory load) should vanish when the distances between items are controlled for. Both predictions were confirmed experimentally. Taken together, our findings provide support for a topographic neural circuit organization of vsWM, they suggest that interference between similar memories underlies some WM limitations, and they put forward a circuit-based explanation that reconciles previous conflicting results on the dependence of WM precision with load. Copyright © 2015 the American Physiological Society.

Novel Designs of Quantum Reversible Counters

NASA Astrophysics Data System (ADS)

Qi, Xuemei; Zhu, Haihong; Chen, Fulong; Zhu, Junru; Zhang, Ziyang

2016-11-01

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits' logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems.

A systems analysis of the erythropoietic responses to weightlessness. Volume 2: Description of the model of erythropoiesis regulation. Part A: Model for regulation of erythropoiesis. Part B: Detailed description of the model for regulation of erythropoiesis

NASA Technical Reports Server (NTRS)

Leonard, J. I.

1985-01-01

A mathematical model of the erythropoiesis on total red blood cell mass is presented. The loss of red cell mass has been a consistent finding during space flight. Computer simulation of this phenomenon required a model that could account for oxygen transport, red cell production, and red cell destruction. The elements incorporated into the feedback regulation loop of the model are based on the accepted concept that erythrocyte production is governed by the balance between oxygen supply and demand in the body. The mechanisms and pathways of the control circuit include oxygenation of hemoglobin and oxygenation of tissues by blood transport and diffusional processes. Other features of the model include a variable oxygen-hemoglobin affinity, and time delays which represent time for erythropoietin (erythrocyte-stimulating hormone) distribution in plasma, and time for maturation of the erythrocytes in bone marrow.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Rulemaking To Amend Dates in Federal Implementation Plans Addressing Interstate Transport of Ozone and Fine Particulate Matter (79 FR 71663)

EPA Pesticide Factsheets

EPA amends the Code of Federal Regulations to reflect compliance deadlines for CSAPR as revised by the action of the U.S. Court of Appeals for the D.C. Circuit granting the EPA’s motion to lift the previous stay of CSAPR and delay its deadlines by 3 years.

Phase Holograms In PMMA

NASA Technical Reports Server (NTRS)

Maker, Paul D.; Muller, Richard E.

1994-01-01

Complex, computer-generated phase holograms written in thin films of poly(methyl methacrylate) (PMMA) by process of electron-beam exposure followed by chemical development. Spatial variations of phase delay in holograms quasi-continuous, as distinquished from stepwise as in binary phase holograms made by integrated-circuit fabrication. Holograms more precise than binary holograms. Greater continuity and precision results in decreased scattering loss and increased imaging efficiency.

Design of a 0.13 µm SiGe Limiting Amplifier with 14.6 THz Gain-Bandwidth-Product

NASA Astrophysics Data System (ADS)

Park, Sehoon; Du, Xuan-Quang; Grözing, Markus; Berroth, Manfred

2017-09-01

This paper presents the design of a limiting amplifier with 1-to-3 fan-out implementation in a 0.13 µm SiGe BiCMOS technology and gives a detailed guideline to determine the circuit parameters of the amplifier for optimum high-frequency performance based on simplified gain estimations. The proposed design uses a Cherry-Hooper topology for bandwidth enhancement and is optimized for maximum group delay flatness to minimize phase distortion of the input signal. With regard to a high integration density and a small chip area, the design employs no passive inductors which might be used to boost the circuit bandwidth with inductive peaking. On a RLC-extracted post-layout simulation level, the limiting amplifier exhibits a gain-bandwidth-product of 14.6 THz with 56.6 dB voltage gain and 21.5 GHz 3 dB bandwidth at a peak-to-peak input voltage of 1.5 mV. The group delay variation within the 3 dB bandwidth is less than 0.5 ps and the power dissipation at a power supply voltage of 3 V including output drivers is 837 mW.

Causal models of attention-deficit/hyperactivity disorder: from common simple deficits to multiple developmental pathways.

PubMed

Sonuga-Barke, Edmund J S

2005-06-01

Until recently, causal models of attention-deficit/hyperactivity disorder (ADHD) have tended to focus on the role of common, simple, core deficits. One such model highlights the role of executive dysfunction due to deficient inhibitory control resulting from disturbances in the frontodorsal striatal circuit and associated mesocortical dopaminergic branches. An alternative model presents ADHD as resulting from impaired signaling of delayed rewards arising from disturbances in motivational processes, involving frontoventral striatal reward circuits and mesolimbic branches terminating in the ventral striatum, particularly the nucleus accumbens. In the present article, these models are elaborated in two ways. First, they are each placed within their developmental context by consideration of the role of person x environment correlation and interaction and individual adaptation to developmental constraint. Second, their relationship to one another is reviewed in the light of recent data suggesting that delay aversion and executive functions might each make distinctive contributions to the development of the disorder. This provides an impetus for theoretical models built around the idea of multiple neurodevelopmental pathways. The possibility of neuropathologic heterogeneity in ADHD is likely to have important implications for the clinical management of the condition, potentially impacting on both diagnostic strategies and treatment options.

Selective randomized load balancing and mesh networks with changing demands

NASA Astrophysics Data System (ADS)

Shepherd, F. B.; Winzer, P. J.

2006-05-01

We consider the problem of building cost-effective networks that are robust to dynamic changes in demand patterns. We compare several architectures using demand-oblivious routing strategies. Traditional approaches include single-hop architectures based on a (static or dynamic) circuit-switched core infrastructure and multihop (packet-switched) architectures based on point-to-point circuits in the core. To address demand uncertainty, we seek minimum cost networks that can carry the class of hose demand matrices. Apart from shortest-path routing, Valiant's randomized load balancing (RLB), and virtual private network (VPN) tree routing, we propose a third, highly attractive approach: selective randomized load balancing (SRLB). This is a blend of dual-hop hub routing and randomized load balancing that combines the advantages of both architectures in terms of network cost, delay, and delay jitter. In particular, we give empirical analyses for the cost (in terms of transport and switching equipment) for the discussed architectures, based on three representative carrier networks. Of these three networks, SRLB maintains the resilience properties of RLB while achieving significant cost reduction over all other architectures, including RLB and multihop Internet protocol/multiprotocol label switching (IP/MPLS) networks using VPN-tree routing.

Voltages induced on a power distribution line by overhead cloud lightning

NASA Technical Reports Server (NTRS)

Yacoub, Ziad; Rubinstein, Marcos; Uman, Martin A.; Thomson, Ewen M.; Medelius, Pedro J.

1991-01-01

Voltages induced by overhead cloud lightning on a 448 m open circuited power distribution line and the corresponding north-south component of the lightning magnetic field were simultaneously measured at the NASA Kennedy Space Center during the summer of 1986. The incident electric field was calculated from the measured magnetic field. The electric field was then used as an input to the computer program, EMPLIN, that calculated the voltages at the two ends of the power line. EMPLIN models the frequency domain field/power coupling theory found, for example, in Ianoz et al. The direction of the source, which is also one of the inputs to EMPLIN, was crudely determined from a three station time delay technique. The authors found reasonably good agreement between calculated and measured waveforms.

Mobile patient monitoring based on impedance-loaded SAW-sensors.

PubMed

Karilainen, Anna; Finnberg, Thomas; Uelzen, Thorsten; Dembowski, Klaus; Müller, Jörg

2004-11-01

A remotely requestable, passive, short-range sensor network for measuring small voltages is presented. The sensor system is able to simultaneously monitor six small voltages in millivolt-range, and it can be used for Holter-electrocardiogram (ECG) and other biopotential monitoring, or in industrial applications. The sensors are based on a surface acoustic wave (SAW) delay line with voltage-dependent, impedance loading on a reflector interdigital transducer (IDT). The load circuit impedance is varied by the capacitance of the voltage-controlled varactor. High resolution is achieved by developing a MOS-capacitor with a thin oxide, low flat-band voltage, and zero-voltage capacitance in the space-charge region, as well as a high-Q-microcoil by thick metal electroplating. Simultaneous monitoring of multiple potentials is realized by time-division-multiplexing of different sensor signals.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Nonlinear computations shaping temporal processing of precortical vision.

PubMed

Butts, Daniel A; Cui, Yuwei; Casti, Alexander R R

2016-09-01

Computations performed by the visual pathway are constructed by neural circuits distributed over multiple stages of processing, and thus it is challenging to determine how different stages contribute on the basis of recordings from single areas. In the current article, we address this problem in the lateral geniculate nucleus (LGN), using experiments combined with nonlinear modeling capable of isolating various circuit contributions. We recorded cat LGN neurons presented with temporally modulated spots of various sizes, which drove temporally precise LGN responses. We utilized simultaneously recorded S-potentials, corresponding to the primary retinal ganglion cell (RGC) input to each LGN cell, to distinguish the computations underlying temporal precision in the retina from those in the LGN. Nonlinear models with excitatory and delayed suppressive terms were sufficient to explain temporal precision in the LGN, and we found that models of the S-potentials were nearly identical, although with a lower threshold. To determine whether additional influences shaped the response at the level of the LGN, we extended this model to use the S-potential input in combination with stimulus-driven terms to predict the LGN response. We found that the S-potential input "explained away" the major excitatory and delayed suppressive terms responsible for temporal patterning of LGN spike trains but revealed additional contributions, largely PULL suppression, to the LGN response. Using this novel combination of recordings and modeling, we were thus able to dissect multiple circuit contributions to LGN temporal responses across retina and LGN, and set the foundation for targeted study of each stage. Copyright © 2016 the American Physiological Society.

42 CFR 84.95 - Service time test; open-circuit apparatus.

Code of Federal Regulations, 2013 CFR

2013-10-01

... classified according to the length of time it supplies air or oxygen to the breathing machine. (c) The... 42 Public Health 1 2013-10-01 2013-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be...

42 CFR 84.95 - Service time test; open-circuit apparatus.

Code of Federal Regulations, 2012 CFR

2012-10-01

... classified according to the length of time it supplies air or oxygen to the breathing machine. (c) The... 42 Public Health 1 2012-10-01 2012-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be...

42 CFR 84.95 - Service time test; open-circuit apparatus.

Code of Federal Regulations, 2014 CFR

2014-10-01

... classified according to the length of time it supplies air or oxygen to the breathing machine. (c) The... 42 Public Health 1 2014-10-01 2014-10-01 false Service time test; open-circuit apparatus. 84.95...-Contained Breathing Apparatus § 84.95 Service time test; open-circuit apparatus. (a) Service time will be...

Auditory cortex of newborn bats is prewired for echolocation.

PubMed

Kössl, Manfred; Voss, Cornelia; Mora, Emanuel C; Macias, Silvio; Foeller, Elisabeth; Vater, Marianne

2012-04-10

Neuronal computation of object distance from echo delay is an essential task that echolocating bats must master for spatial orientation and the capture of prey. In the dorsal auditory cortex of bats, neurons specifically respond to combinations of short frequency-modulated components of emitted call and delayed echo. These delay-tuned neurons are thought to serve in target range calculation. It is unknown whether neuronal correlates of active space perception are established by experience-dependent plasticity or by innate mechanisms. Here we demonstrate that in the first postnatal week, before onset of echolocation and flight, dorsal auditory cortex already contains functional circuits that calculate distance from the temporal separation of a simulated pulse and echo. This innate cortical implementation of a purely computational processing mechanism for sonar ranging should enhance survival of juvenile bats when they first engage in active echolocation behaviour and flight.

Mutations in KPTN Cause Macrocephaly, Neurodevelopmental Delay, and Seizures

PubMed Central

Baple, Emma L.; Maroofian, Reza; Chioza, Barry A.; Izadi, Maryam; Cross, Harold E.; Al-Turki, Saeed; Barwick, Katy; Skrzypiec, Anna; Pawlak, Robert; Wagner, Karin; Coblentz, Roselyn; Zainy, Tala; Patton, Michael A.; Mansour, Sahar; Rich, Phillip; Qualmann, Britta; Hurles, Matt E.; Kessels, Michael M.; Crosby, Andrew H.

2014-01-01

The proper development of neuronal circuits during neuromorphogenesis and neuronal-network formation is critically dependent on a coordinated and intricate series of molecular and cellular cues and responses. Although the cortical actin cytoskeleton is known to play a key role in neuromorphogenesis, relatively little is known about the specific molecules important for this process. Using linkage analysis and whole-exome sequencing on samples from families from the Amish community of Ohio, we have demonstrated that mutations in KPTN, encoding kaptin, cause a syndrome typified by macrocephaly, neurodevelopmental delay, and seizures. Our immunofluorescence analyses in primary neuronal cell cultures showed that endogenous and GFP-tagged kaptin associates with dynamic actin cytoskeletal structures and that this association is lost upon introduction of the identified mutations. Taken together, our studies have identified kaptin alterations responsible for macrocephaly and neurodevelopmental delay and define kaptin as a molecule crucial for normal human neuromorphogenesis. PMID:24239382

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations

NASA Astrophysics Data System (ADS)

Ibrahim, Walid; Beiu, Valeriu

As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nano-circuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design’s overall reliability, and identifying those (few) gates which impact the design’s reliability most significantly.

Generation of optical vortices in an integrated optical circuit

NASA Astrophysics Data System (ADS)

Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

2017-09-01

In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

A HWIL test facility of infrared imaging laser radar using direct signal injection

NASA Astrophysics Data System (ADS)

Wang, Qian; Lu, Wei; Wang, Chunhui; Wang, Qi

2005-01-01

Laser radar has been widely used these years and the hardware-in-the-loop (HWIL) testing of laser radar become important because of its low cost and high fidelity compare with On-the-Fly testing and whole digital simulation separately. Scene generation and projection two key technologies of hardware-in-the-loop testing of laser radar and is a complicated problem because the 3D images result from time delay. The scene generation process begins with the definition of the target geometry and reflectivity and range. The real-time 3D scene generation computer is a PC based hardware and the 3D target models were modeled using 3dsMAX. The scene generation software was written in C and OpenGL and is executed to extract the Z-buffer from the bit planes to main memory as range image. These pixels contain each target position x, y, z and its respective intensity and range value. Expensive optical injection technologies of scene projection such as LDP array, VCSEL array, DMD and associated scene generation is ongoing. But the optical scene projection is complicated and always unaffordable. In this paper a cheaper test facility was described that uses direct electronic injection to provide rang images for laser radar testing. The electronic delay and pulse shaping circuits inject the scenes directly into the seeker's signal processing unit.

Delay of gratification is associated with white matter connectivity in the dorsal prefrontal cortex: a diffusion tensor imaging study in chimpanzees (Pan troglodytes).

PubMed

Latzman, Robert D; Taglialatela, Jared P; Hopkins, William D

2015-06-22

Individual variability in delay of gratification (DG) is associated with a number of important outcomes in both non-human and human primates. Using diffusion tensor imaging (DTI), this study describes the relationship between probabilistic estimates of white matter tracts projecting from the caudate to the prefrontal cortex (PFC) and DG abilities in a sample of 49 captive chimpanzees (Pan troglodytes). After accounting for time between collection of DTI scans and DG measurement, age and sex, higher white matter connectivity between the caudate and right dorsal PFC was found to be significantly associated with the acquisition (i.e. training phase) but not the maintenance of DG abilities. No other associations were found to be significant. The integrity of white matter connectivity between regions of the striatum and the PFC appear to be associated with inhibitory control in chimpanzees, with perturbations on this circuit potentially leading to a variety of maladaptive outcomes. Additionally, results have potential translational implications for understanding the pathophysiology of a number of psychiatric and clinical outcomes in humans. © 2015 The Author(s) Published by the Royal Society. All rights reserved.

Evaluation the course of the vehicle braking process in case of hydraulic circuit malfunction

NASA Astrophysics Data System (ADS)

Szczypiński-Sala, W.; Lubas, J.

2016-09-01

In the paper, the results of the research were discussed, the aim of which was the evaluation of the vehicle braking performance efficiency and the course of this process with regard to the dysfunction which may occur in braking hydraulic circuit. As part of the research, on-road tests were conducted. During the research, the delay of the vehicle when braking was measured with the use of the set of sensors placed in the parallel and the perpendicular axis of the vehicle. All the tests were conducted on the same flat section of asphalt road with wet surface. Conditions of diminished tire-to-road adhesion were chosen in order to force the activity of anti-lock braking system. The research was conducted comparatively for the vehicle with acting anti-lock braking system and subsequently for the vehicle without the system. In both cases, there was a subsequent evaluation of the course of braking with efficient braking system and with the dysfunction of hydraulic circuit.

Survey Of High Speed Test Techniques

NASA Astrophysics Data System (ADS)

Gheewala, Tushar

1988-02-01

The emerging technologies for the characterization and production testing of high-speed devices and integrated circuits are reviewed. The continuing progress in the field of semiconductor technologies will, in the near future, demand test techniques to test 10ps to lOOps gate delays, 10 GHz to 100 GHz analog functions and 10,000 to 100,000 gates on a single chip. Clearly, no single test technique would provide a cost-effective answer to all the above demands. A divide-and-conquer approach based on a judicial selection of parametric, functional and high-speed tests will be required. In addition, design-for-test methods need to be pursued which will include on-chip test electronics as well as circuit techniques that minimize the circuit performance sensitivity to allowable process variations. The electron and laser beam based test technologies look very promising and may provide the much needed solutions to not only the high-speed test problem but also to the need for high levels of fault coverage during functional testing.

Design of a Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

NASA Astrophysics Data System (ADS)

Gao, W.; Liu, H.; Gan, B.; Wei, T.; Gao, D.; Hu, Y.

2014-10-01

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm3, the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Dynamic divisive normalization predicts time-varying value coding in decision-related circuits.

PubMed

Louie, Kenway; LoFaro, Thomas; Webb, Ryan; Glimcher, Paul W

2014-11-26

Normalization is a widespread neural computation, mediating divisive gain control in sensory processing and implementing a context-dependent value code in decision-related frontal and parietal cortices. Although decision-making is a dynamic process with complex temporal characteristics, most models of normalization are time-independent and little is known about the dynamic interaction of normalization and choice. Here, we show that a simple differential equation model of normalization explains the characteristic phasic-sustained pattern of cortical decision activity and predicts specific normalization dynamics: value coding during initial transients, time-varying value modulation, and delayed onset of contextual information. Empirically, we observe these predicted dynamics in saccade-related neurons in monkey lateral intraparietal cortex. Furthermore, such models naturally incorporate a time-weighted average of past activity, implementing an intrinsic reference-dependence in value coding. These results suggest that a single network mechanism can explain both transient and sustained decision activity, emphasizing the importance of a dynamic view of normalization in neural coding. Copyright © 2014 the authors 0270-6474/14/3416046-12$15.00/0.

A Computational Model for Predicting Gas Breakdown

NASA Astrophysics Data System (ADS)

Gill, Zachary

2017-10-01

Pulsed-inductive discharges are a common method of producing a plasma. They provide a mechanism for quickly and efficiently generating a large volume of plasma for rapid use and are seen in applications including propulsion, fusion power, and high-power lasers. However, some common designs see a delayed response time due to the plasma forming when the magnitude of the magnetic field in the thruster is at a minimum. New designs are difficult to evaluate due to the amount of time needed to construct a new geometry and the high monetary cost of changing the power generation circuit. To more quickly evaluate new designs and better understand the shortcomings of existing designs, a computational model is developed. This model uses a modified single-electron model as the basis for a Mathematica code to determine how the energy distribution in a system changes with regards to time and location. By analyzing this energy distribution, the approximate time and location of initial plasma breakdown can be predicted. The results from this code are then compared to existing data to show its validity and shortcomings. Missouri S&T APLab.

Displacement sensors using soft magnetostrictive alloys

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hristoforou, E.; Reilly, R.E.

1994-09-01

The authors report results on the response of a family of displacement sensors, which are based on the magnetostrictive delay line (MDL) technique, using current conductor orthogonal to the MDL. Such sensing technique is based on the change of the magnetic circuit and the acoustic stress point of origin due to the displacement of a soft magnetic material above it. Integrated arrays of sensors can be obtained due to the acoustic delay line technique and they can be used as tactile arrays, digitizers or devices for medical application (gait analysis etc.), while absence of hysteresis and low cost of manufacturingmore » make them competent in this sector of sensor market.« less

Experimental Chaos - Proceedings of the 3rd Conference

NASA Astrophysics Data System (ADS)

Harrison, Robert G.; Lu, Weiping; Ditto, William; Pecora, Lou; Spano, Mark; Vohra, Sandeep

1996-10-01

The Table of Contents for the full book PDF is as follows: * Preface * Spatiotemporal Chaos and Patterns * Scale Segregation via Formation of Domains in a Nonlinear Optical System * Laser Dynamics as Hydrodynamics * Spatiotemporal Dynamics of Human Epileptic Seizures * Experimental Transition to Chaos in a Quasi 1D Chain of Oscillators * Measuring Coupling in Spatiotemporal Dynamical Systems * Chaos in Vortex Breakdown * Dynamical Analysis * Radial Basis Function Modelling and Prediction of Time Series * Nonlinear Phenomena in Polyrhythmic Hand Movements * Using Models to Diagnose, Test and Control Chaotic Systems * New Real-Time Analysis of Time Series Data with Physical Wavelets * Control and Synchronization * Measuring and Controlling Chaotic Dynamics in a Slugging Fluidized Bed * Control of Chaos in a Laser with Feedback * Synchronization and Chaotic Diode Resonators * Control of Chaos by Continuous-time Feedback with Delay * A Framework for Communication using Chaos Sychronization * Control of Chaos in Switching Circuits * Astrophysics, Meteorology and Oceanography * Solar-Wind-Magnetospheric Dynamics via Satellite Data * Nonlinear Dynamics of the Solar Atmosphere * Fractal Dimension of Scalar and Vector Variables from Turbulence Measurements in the Atmospheric Surface Layer * Mechanics * Escape and Overturning: Subtle Transient Behavior in Nonlinear Mechanical Models * Organising Centres in the Dynamics of Parametrically Excited Double Pendulums * Intermittent Behaviour in a Heating System Driven by Phase Transitions * Hydrodynamics * Size Segregation in Couette Flow of Granular Material * Routes to Chaos in Rotational Taylor-Couette Flow * Experimental Study of the Laminar-Turbulent Transition in an Open Flow System * Chemistry * Order and Chaos in Excitable Media under External Forcing * A Chemical Wave Propagation with Accelerating Speed Accompanied by Hydrodynamic Flow * Optics * Instabilities in Semiconductor Lasers with Optical Injection * Spatio-Temporal Dynamics of a Bimode CO2 Laser with Saturable Absorber * Chaotic Homoclinic Phenomena in Opto-Thermal Devices * Observation and Characterisation of Low-Frequency Chaos in Semiconductor Lasers with External Feedback * Condensed Matter * The Application of Nonlinear Dynamics in the Study of Ferroelectric Materials * Cellular Convection in a Small Aspect Ratio Liquid Crystal Device * Driven Spin-Wave Dynamics in YIG Films * Quantum Chaology in Quartz * Small Signal Amplification Caused by Nonlinear Properties of Ferroelectrics * Composite Materials Evolved from Chaos * Electronics and Circuits * Controlling a Chaotic Array of Pulse-Coupled Fitzhugh-Nagumo Circuits * Experimental Observation of On-Off Intermittency * Phase Lock-In of Chaotic Relaxation Oscillators * Biology and Medicine * Singular Value Decomposition and Circuit Structure in Invertebrate Ganglia * Nonlinear Forecasting of Spike Trains from Neurons of a Mollusc * Ultradian Rhythm in the Sensitive Plants: Chaos or Coloured Noise? * Chaos and the Crayfish Sixth Ganglion * Hardware Coupled Nonlinear Oscillators as a Model of Retina

Study of feasibility of solid-state electric switch gear for aircraft and spacecraft

NASA Technical Reports Server (NTRS)

Buchanan, E.; Waddington, D.

1973-01-01

The design of a solid-state circuit breaker that can be interconnected to a second breaker to form a transfer switch is presented. The breaker operates on a nominal 270-V dc circuit and controls power to loads of up to 15 A. Automatic overload trip is provided as a function of excess energy measured through the breaker and/or excess current through the breaker. After an overload trip, up to nine preprogrammable attempts to reclose may be tried with programmable delays between each attempt. The breaker or switch is remotely controllable. Test data on performance in the laboratory over temperatures from -45 to 100 C are provided. The feasibility of solid-state switch gear has been established.

The feasibility of using a portable xenon delivery device to permit earlier xenon ventilation with therapeutic cooling of neonates during ambulance retrieval.

PubMed

Dingley, John; Liu, Xun; Gill, Hannah; Smit, Elisa; Sabir, Hemmen; Tooley, James; Chakkarapani, Ela; Windsor, David; Thoresen, Marianne

2015-06-01

Therapeutic hypothermia is the standard of care after perinatal asphyxia. Preclinical studies show 50% xenon improves outcome, if started early. During a 32-patient study randomized between hypothermia only and hypothermia with xenon, 5 neonates were given xenon during retrieval using a closed-circuit incubator-mounted system. Without xenon availability during retrieval, 50% of eligible infants exceeded the 5-hour treatment window. With the transportable system, 100% were recruited. Xenon delivery lasted 55 to 120 minutes, using 174 mL/h (117.5-193.2) (median [interquartile range]), after circuit priming (1300 mL). Xenon delivery during ambulance retrieval was feasible, reduced starting delays, and used very little gas.

Efficient reinforcement learning of a reservoir network model of parametric working memory achieved with a cluster population winner-take-all readout mechanism.

PubMed

Cheng, Zhenbo; Deng, Zhidong; Hu, Xiaolin; Zhang, Bo; Yang, Tianming

2015-12-01

The brain often has to make decisions based on information stored in working memory, but the neural circuitry underlying working memory is not fully understood. Many theoretical efforts have been focused on modeling the persistent delay period activity in the prefrontal areas that is believed to represent working memory. Recent experiments reveal that the delay period activity in the prefrontal cortex is neither static nor homogeneous as previously assumed. Models based on reservoir networks have been proposed to model such a dynamical activity pattern. The connections between neurons within a reservoir are random and do not require explicit tuning. Information storage does not depend on the stable states of the network. However, it is not clear how the encoded information can be retrieved for decision making with a biologically realistic algorithm. We therefore built a reservoir-based neural network to model the neuronal responses of the prefrontal cortex in a somatosensory delayed discrimination task. We first illustrate that the neurons in the reservoir exhibit a heterogeneous and dynamical delay period activity observed in previous experiments. Then we show that a cluster population circuit decodes the information from the reservoir with a winner-take-all mechanism and contributes to the decision making. Finally, we show that the model achieves a good performance rapidly by shaping only the readout with reinforcement learning. Our model reproduces important features of previous behavior and neurophysiology data. We illustrate for the first time how task-specific information stored in a reservoir network can be retrieved with a biologically plausible reinforcement learning training scheme. Copyright © 2015 the American Physiological Society.

Parallel processing using an optical delay-based reservoir computer

NASA Astrophysics Data System (ADS)

Van der Sande, Guy; Nguimdo, Romain Modeste; Verschaffelt, Guy

2016-04-01

Delay systems subject to delayed optical feedback have recently shown great potential in solving computationally hard tasks. By implementing a neuro-inspired computational scheme relying on the transient response to optical data injection, high processing speeds have been demonstrated. However, reservoir computing systems based on delay dynamics discussed in the literature are designed by coupling many different stand-alone components which lead to bulky, lack of long-term stability, non-monolithic systems. Here we numerically investigate the possibility of implementing reservoir computing schemes based on semiconductor ring lasers. Semiconductor ring lasers are semiconductor lasers where the laser cavity consists of a ring-shaped waveguide. SRLs are highly integrable and scalable, making them ideal candidates for key components in photonic integrated circuits. SRLs can generate light in two counterpropagating directions between which bistability has been demonstrated. We demonstrate that two independent machine learning tasks , even with different nature of inputs with different input data signals can be simultaneously computed using a single photonic nonlinear node relying on the parallelism offered by photonics. We illustrate the performance on simultaneous chaotic time series prediction and a classification of the Nonlinear Channel Equalization. We take advantage of different directional modes to process individual tasks. Each directional mode processes one individual task to mitigate possible crosstalk between the tasks. Our results indicate that prediction/classification with errors comparable to the state-of-the-art performance can be obtained even with noise despite the two tasks being computed simultaneously. We also find that a good performance is obtained for both tasks for a broad range of the parameters. The results are discussed in detail in [Nguimdo et al., IEEE Trans. Neural Netw. Learn. Syst. 26, pp. 3301-3307, 2015

Pharmacological reduction of adult hippocampal neurogenesis modifies functional brain circuits in mice exposed to a cocaine conditioned place preference paradigm.

PubMed

Castilla-Ortega, Estela; Blanco, Eduardo; Serrano, Antonia; Ladrón de Guevara-Miranda, David; Pedraz, María; Estivill-Torrús, Guillermo; Pavón, Francisco Javier; Rodríguez de Fonseca, Fernando; Santín, Luis J

2016-05-01

We investigated the role of adult hippocampal neurogenesis in cocaine-induced conditioned place preference (CPP) behaviour and the functional brain circuitry involved. Adult hippocampal neurogenesis was pharmacologically reduced with temozolomide (TMZ), and mice were tested for cocaine-induced CPP to study c-Fos expression in the hippocampus and in extrahippocampal addiction-related areas. Correlational and multivariate analysis revealed that, under normal conditions, the hippocampus showed widespread functional connectivity with other brain areas and strongly contributed to the functional brain module associated with CPP expression. However, the neurogenesis-reduced mice showed normal CPP acquisition but engaged an alternate brain circuit where the functional connectivity of the dentate gyrus was notably reduced and other areas (the medial prefrontal cortex, accumbens and paraventricular hypothalamic nucleus) were recruited instead of the hippocampus. A second experiment unveiled that mice acquiring the cocaine-induced CPP under neurogenesis-reduced conditions were delayed in extinguishing their drug-seeking behaviour. But if the inhibited neurons were generated after CPP acquisition, extinction was not affected but an enhanced long-term CPP retention was found, suggesting that some roles of the adult-born neurons may differ depending on whether they are generated before or after drug-contextual associations are established. Importantly, cocaine-induced reinstatement of CPP behaviour was increased in the TMZ mice, regardless of the time of neurogenesis inhibition. The results show that adult hippocampal neurogenesis sculpts the addiction-related functional brain circuits, and reduction of the adult-born hippocampal neurons increases cocaine seeking in the CPP model. © 2015 Society for the Study of Addiction.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.

With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in themore » photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an encrypting/scrambling algorithm based on a study of candidate encryption algorithms. Demonstration circuits show how these logic elements can be used to form NAND, NOR, and XOR functions. This paper also presents functional analysis of a serial, low gate count demonstration algorithm suitable for scrambling/encryption using S-SEED devices.« less

Scaling induced performance challenges/limitations of on-chip metal interconnects and comparisons with optical interconnects

NASA Astrophysics Data System (ADS)

Kapur, Pawan

The miniaturization paradigm for silicon integrated circuits has resulted in a tremendous cost and performance advantage. Aggressive shrinking of devices provides faster transistors and a greater functionality for circuit design. However, scaling induced smaller wire cross-sections coupled with longer lengths owing to larger chip areas, result in a steady deterioration of interconnects. This degradation in interconnect trends threatens to slow down the rapid growth along Moore's law. This work predicts that the situation is worse than anticipated. It shows that in the light of technology and reliability constraints, scaling induced increase in electron surface scattering, fractional cross section area occupied by the highly resistive barrier, and realistic interconnect operation temperature will lead to a significant rise in effective resistivity of modern copper based interconnects. We start by discussing various technology factors affecting copper resistivity. We, next, develop simulation tools to model these effects. Using these tools, we quantify the increase in realistic copper resistivity as a function of future technology nodes, under various technology assumptions. Subsequently, we evaluate the impact of these technology effects on delay and power dissipation of global signaling interconnects. Modern long on-chip wires use repeaters, which dramatically improves their delay and bandwidth. We quantify the repeated wire delays and power dissipation using realistic resistance trends at future nodes. With the motivation of reducing power, we formalize a methodology, which trades power with delay very efficiently for repeated wires. Using this method, we find that although the repeater power comes down, the total power dissipation due to wires is still found to be very large at future nodes. Finally, we explore optical interconnects as a possible substitute, for specific interconnect applications. We model an optical receiver and waveguides. Using this we assess future optical system performance. Finally, we compare the delay and power of future metal interconnects with that of optical interconnects for global signaling application. We also compare the power dissipation of the two approaches for an upper level clock distribution application. We find that for long on-chip communication links, optical interconnects have lower latencies than future metal interconnects at comparable levels of power dissipation.

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harold D. Anderson, John T. Williams

2009-07-01

The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Basedmore » on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens-of-nanoseconds delay to propagate across the FPGA. This paper discusses the design, installation, and testing of the proposed system upgrade, including failure statistics and modifications to the original design.« less

An Assessment of the Impact of the Department of Defense Very-High-Speed Integrated Circuit Program.

DTIC Science & Technology

1982-01-01

analysis, statistical inference, device physics and other such products of basic research. Examples of such information would be: analyses of properties of...TB , for a n-p-n silicon transitor with 1018 cm- 3 base-doping, TB = Wb 2/2Dw becomes 0.4 ps in this limit so that the base contributes little to delay

Energy and Timing Measurement with Time-Based Detector Readout for PET Applications: Principle and Validation with Discrete Circuit Components

PubMed Central

Sun, Xishan; Lan, Allan K.; Bircher, Chad; Deng, Zhi; Liu, Yinong; Shao, Yiping

2011-01-01

A new signal processing method for PET application has been developed, with discrete circuit components to measure energy and timing of a gamma interaction based solely on digital timing processing without using an amplitude-to-digital convertor (ADC) or a constant fraction discriminator (CFD). A single channel discrete component time-based readout (TBR) circuit was implemented in a PC board. Initial circuit functionality and performance evaluations have been conducted. Accuracy and linearity of signal amplitude measurement were excellent, as measured with test pulses. The measured timing accuracy from test pulses reached to less than 300 ps, a value limited mainly by the timing jitter of the prototype electronics circuit. Both suitable energy and coincidence timing resolutions (~18% and ~1.0 ns) have been achieved with 3 × 3 × 20 mm3 LYSO scintillator and photomultiplier tube-based detectors. With its relatively simple circuit and low cost, TBR is expected to be a suitable front-end signal readout electronics for compact PET or other radiation detectors requiring the reading of a large number of detector channels and demanding high performance for energy and timing measurement. PMID:21743761

LOGARITHMIC AMPLIFIER

DOEpatents

De Shong, J.A. Jr.

1957-12-31

A logarithmic current amplifier circuit having a high sensitivity and fast response is described. The inventor discovered the time constant of the input circuit of a system utilizing a feedback amplifier, ionization chamber, and a diode, is inversely proportional to the input current, and that the amplifier becomes unstable in amplifying signals in the upper frequency range when the amplifier's forward gain time constant equals the input circuit time constant. The described device incorporates impedance networks having low frequency response characteristic at various points in the circuit to change the forward gain of the amplifler at a rate of 0.7 of the gain magnitude for every two times increased in frequency. As a result of this improvement, the time constant of the input circuit is greatly reduced at high frequencies, and the amplifier response is increased.

Impacts of Carrier Transport and Deep Level Defects on Delayed Cathodoluminescence in Droop-Mitigating InGaN/GaN LEDs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhao, Zhibo; Singh, Akshay; Chesin, Jordan

Prevalent droop mitigation strategies in InGaN-based LEDs require structural and/or compositional changes in the active region but are accompanied by a detrimental reduction in external quantum efficiency (EQE) due to increased Shockley-Read-Hall recombination. Understanding the optoelectronic impacts of structural modifications in InGaN/GaN quantum wells (QW) remains critical for emerging high-power LEDs. In this work, we use a combination of electron microscopy tools along with standard electrical characterization to investigate a wide range of low-droop InGaN/GaN QW designs. We find that chip-scale EQE is uncorrelated with extended well-width fluctuations observed in scanning transmission electron microscopy. Further, we observe delayed cathodoluminescence (CL)more » response from designs in which calculated band profiles suggest facile carrier escape from individual QWs. Samples with the slowest CL responses also exhibit the lowest EQEs and highest QW defect densities in deep level optical spectroscopy. We propose a model in which the electron beam (i) passivates deep level defect states and (ii) drives charge carrier accumulation and subsequent reduction of the built-in field across the multi-QW active region, resulting in delayed radiative recombination. Finally, we correlate CL rise dynamics with capacitance-voltage measurements and show that certain early-time components of the CL dynamics reflect the open circuit carrier population within one or more QWs.« less

Functionally segregated neural substrates for arbitrary audiovisual paired-association learning.

PubMed

Tanabe, Hiroki C; Honda, Manabu; Sadato, Norihiro

2005-07-06

To clarify the neural substrates and their dynamics during crossmodal association learning, we conducted functional magnetic resonance imaging (MRI) during audiovisual paired-association learning of delayed matching-to-sample tasks. Thirty subjects were involved in the study; 15 performed an audiovisual paired-association learning task, and the remainder completed a control visuo-visual task. Each trial consisted of the successive presentation of a pair of stimuli. Subjects were asked to identify predefined audiovisual or visuo-visual pairs by trial and error. Feedback for each trial was given regardless of whether the response was correct or incorrect. During the delay period, several areas showed an increase in the MRI signal as learning proceeded: crossmodal activity increased in unimodal areas corresponding to visual or auditory areas, and polymodal responses increased in the occipitotemporal junction and parahippocampal gyrus. This pattern was not observed in the visuo-visual intramodal paired-association learning task, suggesting that crossmodal associations might be formed by binding unimodal sensory areas via polymodal regions. In both the audiovisual and visuo-visual tasks, the MRI signal in the superior temporal sulcus (STS) in response to the second stimulus and feedback peaked during the early phase of learning and then decreased, indicating that the STS might be key to the creation of paired associations, regardless of stimulus type. In contrast to the activity changes in the regions discussed above, there was constant activity in the frontoparietal circuit during the delay period in both tasks, implying that the neural substrates for the formation and storage of paired associates are distinct from working memory circuits.

Optical burst switching for the next generation Optical Internet

NASA Astrophysics Data System (ADS)

Yoo, Myungsik

2000-11-01

In recent years, Internet Protocol (IP) over Wavelength Division Multiplexing (WDM) networks for the next generation Internet (or the so-called Optical Internet) have received enormous attention. There are two main drivers for an Optical Internet. One is the explosion of Internet traffic, which seems to keep growing exponentially. The other driver is the rapid advance in the WDM optical networking technology. In this study, key issues in the optical (WDM) layer will be investigated. As a novel switching paradigm for Optical Internet, Optical Burst Switching (OBS) is discussed. By leveraging the attractive properties of optical communications and at the same time, taking into account its limitations, OBS can combine the best of optical circuit-switching and packet/cell switching. The general concept of JET-based OBS protocol is described, including offset time and delayed reservation. In the next generation Optical Internet, one must address how to support Quality of Service (QoS) at the WDM layer since current IP provides only best effort services. The offset-time- based QoS scheme is proposed as a way of supporting QoS at the WDM layer. Unlike existing QoS schemes, offset- time-based QoS scheme does not mandate the use of buffer to differentiate services. For the bufferless WDM switch, the performance of offset- time-based QoS scheme is evaluated in term of blocking probability. In addition, the extra offset time required for class isolation is quantified and the theoretical bounds on blocking probability are analyzed. The offset-time-based scheme is applied to WDM switch with limited fiber delay line (FDL) buffer. We evaluate the effect of having a FDL buffer on the QoS performance of the offset-time-based scheme in terms of the loss probability and queuing delay of bursts. Finally, in order to dimension the network resources in Optical Internet backbone networks, the performance of the offset-time-based QoS scheme is evaluated for the multi-hop case. In particular, we consider very high performance Backbone Network Service (vBNS) backbone network. Various policies such as drop, retransmission, deflection routing and buffering are considered for performance evaluation. The performance results obtained under these policies are compared to decide the most efficient policy for the WDM backbone network.

Solid state remote circuit selector switch

NASA Technical Reports Server (NTRS)

Peterson, V. S.

1970-01-01

Remote switching circuit utilizes voltage logic to switch on desired circuit. Circuit controls rotating multi-range pressure transducers in jet engine testing and can be used in coded remote circuit activator where sequence of switching has to occur in defined length of time to prevent false or undesired circuit activation.

Variable-pulse switching circuit accurately controls solenoid-valve actuations

NASA Technical Reports Server (NTRS)

Gillett, J. D.

1967-01-01

Solid state circuit generating adjustable square wave pulses of sufficient power operates a 28 volt dc solenoid valve at precise time intervals. This circuit is used for precise time control of fluid flow in combustion experiments.

Measurand transient signal suppressor

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr. (Inventor)

1994-01-01

A transient signal suppressor for use in a controls system which is adapted to respond to a change in a physical parameter whenever it crosses a predetermined threshold value in a selected direction of increasing or decreasing values with respect to the threshold value and is sustained for a selected discrete time interval is presented. The suppressor includes a sensor transducer for sensing the physical parameter and generating an electrical input signal whenever the sensed physical parameter crosses the threshold level in the selected direction. A manually operated switch is provided for adapting the suppressor to produce an output drive signal whenever the physical parameter crosses the threshold value in the selected direction of increasing or decreasing values. A time delay circuit is selectively adjustable for suppressing the transducer input signal for a preselected one of a plurality of available discrete suppression time and producing an output signal only if the input signal is sustained for a time greater than the selected suppression time. An electronic gate is coupled to receive the transducer input signal and the timer output signal and produce an output drive signal for energizing a control relay whenever the transducer input is a non-transient signal which is sustained beyond the selected time interval.

Method and apparatus for free-space quantum key distribution in daylight

DOEpatents

Hughes, Richard J.; Buttler, William T.; Lamoreaux, Steve K.; Morgan, George L.; Nordholt, Jane E.; Peterson, C. Glen; Kwiat, Paul G.

2004-06-08

A quantum cryptography apparatus securely generates a key to be used for secure transmission between a sender and a receiver connected by an atmospheric transmission link. A first laser outputs a timing bright light pulse; other lasers output polarized optical data pulses after having been enabled by a random bit generator. Output optics transmit output light from the lasers that is received by receiving optics. A first beam splitter receives light from the receiving optics, where a received timing bright light pulse is directed to a delay circuit for establishing a timing window for receiving light from the lasers and where an optical data pulse from one of the lasers has a probability of being either transmitted by the beam splitter or reflected by the beam splitter. A first polarizer receives transmitted optical data pulses to output one data bit value and a second polarizer receives reflected optical data pulses to output a second data bit value. A computer receives pulses representing receipt of a timing bright timing pulse and the first and second data bit values, where receipt of the first and second data bit values is indexed by the bright timing pulse.

Three-phase short circuit calculation method based on pre-computed surface for doubly fed induction generator

NASA Astrophysics Data System (ADS)

Ma, J.; Liu, Q.

2018-02-01

This paper presents an improved short circuit calculation method, based on pre-computed surface to determine the short circuit current of a distribution system with multiple doubly fed induction generators (DFIGs). The short circuit current, injected into power grid by DFIG, is determined by low voltage ride through (LVRT) control and protection under grid fault. However, the existing methods are difficult to calculate the short circuit current of DFIG in engineering practice due to its complexity. A short circuit calculation method, based on pre-computed surface, was proposed by developing the surface of short circuit current changing with the calculating impedance and the open circuit voltage. And the short circuit currents were derived by taking into account the rotor excitation and crowbar activation time. Finally, the pre-computed surfaces of short circuit current at different time were established, and the procedure of DFIG short circuit calculation considering its LVRT was designed. The correctness of proposed method was verified by simulation.

ADDER CIRCUIT

DOEpatents

Jacobsohn, D.H.; Merrill, L.C.

1959-01-20

An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

Dead-time compensation for a logarithmic display rate meter

DOEpatents

Larson, John A.; Krueger, Frederick P.

1988-09-20

An improved circuit is provided for application to a radiation survey meter that uses a detector that is subject to dead time. The circuit compensates for dead time over a wide range of count rates by producing a dead-time pulse for each detected event, a live-time pulse that spans the interval between dead-time pulses, and circuits that average the value of these pulses over time. The logarithm of each of these values is obtained and the logarithms are subtracted to provide a signal that is proportional to a count rate that is corrected for the effects of dead time. The circuit produces a meter indication and is also capable of producing an audible indication of detected events.

Dead-time compensation for a logarithmic display rate meter

DOEpatents

Larson, J.A.; Krueger, F.P.

1987-10-05

An improved circuit is provided for application to a radiation survey meter that uses a detector that is subject to dead time. The circuit compensates for dead time over a wide range of count rates by producing a dead-time pulse for each detected event, a live-time pulse that spans the interval between dead-time pulses, and circuits that average the value of these pulses over time. The logarithm of each of these values is obtained and the logarithms are subtracted to provide a signal that is proportional to a count rate that is corrected for the effects of dead time. The circuit produces a meter indication and is also capable of producing an audible indication of detected events. 5 figs.

Prolonged cortical silent period but normal sensorimotor plasticity in spinocerebellar ataxia 6.

PubMed

Teo, James T H; Schneider, Susanne A; Cheeran, Binith J; Fernandez-del-Olmo, Miguel; Giunti, Paola; Rothwell, John C; Bhatia, Kailash P

2008-02-15

Spinocerebellar ataxia 6 (SCA6) is a hereditary disease characterized by a trinucleotide repeat expansion in the CACNA1A gene and late-onset bilateral cerebellar atrophy. It is unclear if there is significant pathology outside of the cerebellum. We used transcranial magnetic stimulation to assess sensorimotor cortical circuits and cortical plasticity in 8 SCA6 patients and 8 age-matched controls. Behavioral performance was assessed using a rhythmic tapping task. Neurophysiological measures of SCA6 patients showed a prolonged cortical silent period (CSP) but normal MEP recruitment curve, short-latency afferent inhibition, long-latency afferent inhibition and ipsilateral silent period. Paired-associative stimulation induction also increased motor-evoked potentials normally. SCA6 patients had greater variability with cued rhythmic tapping than normals and deteriorated when the cue was removed; in comparison, normal subjects had similar variability between cued and uncued rhythmic tapping. Analysis using a Wing-Kristofferson timing model indicated that both clock variance and motor delay variance were abnormal. Conclusion. In SCA6, the circuits for sensorimotor integration and the mechanisms for LTP-like plasticity in the sensorimotor cortex are unimpaired. A prolonged CSP in SCA6 just like in other cerebellar atrophies would suggest that this neurophysiological change typifies cerebellar dysfunction. 2007 Movement Disorder Society

Neural Substrates Underlying Effort, Time, and Risk-Based Decision Making in Motivated Behavior

PubMed Central

Bailey, Matthew R.; Simpson, Eleanor H.; Balsam, Peter D

2016-01-01

All mobile organisms rely on adaptive motivated behavior to overcome the challenges of living in an environment in which essential resources may be limited. A variety of influences ranging from an organism’s environment, experiential history, and physiological state all influence a cost-benefit analysis which allows motivation to energize behavior and direct it toward specific goals. Here we review the substantial amount of research aimed at discovering the interconnected neural circuits which allow organisms to carry-out the cost-benefit computations which allow them to behave in adaptive ways. We specifically focus on how the brain deals with different types of costs, including effort requirements, delays to reward and payoff riskiness. An examination of this broad literature highlights the importance of the extended neural circuits which enable organisms to make decisions about these different types of costs. This involves Cortical Structures, including the Anterior Cingulate Cortex (ACC), the Orbital Frontal Cortex (OFC), the Infralimbic Cortex (IL), and prelimbic Cortex (PL), as well as the Baso-Lateral Amygdala (BLA), the Nucleus Accumbens (Nacc), the Ventral Pallidal (VP), the Sub Thalamic Nucleus (STN) among others. Some regions are involved in multiple aspects of cost-benefit computations while the involvement of other regions is restricted to information relating to specific types of costs. PMID:27427327

Neural substrates underlying effort, time, and risk-based decision making in motivated behavior.

PubMed

Bailey, Matthew R; Simpson, Eleanor H; Balsam, Peter D

2016-09-01

All mobile organisms rely on adaptive motivated behavior to overcome the challenges of living in an environment in which essential resources may be limited. A variety of influences ranging from an organism's environment, experiential history, and physiological state all influence a cost-benefit analysis which allows motivation to energize behavior and direct it toward specific goals. Here we review the substantial amount of research aimed at discovering the interconnected neural circuits which allow organisms to carry-out the cost-benefit computations which allow them to behave in adaptive ways. We specifically focus on how the brain deals with different types of costs, including effort requirements, delays to reward and payoff riskiness. An examination of this broad literature highlights the importance of the extended neural circuits which enable organisms to make decisions about these different types of costs. This involves Cortical Structures, including the Anterior Cingulate Cortex (ACC), the Orbital Frontal Cortex (OFC), the Infralimbic Cortex (IL), and prelimbic Cortex (PL), as well as the Baso-Lateral Amygdala (BLA), the Nucleus Accumbens (NAcc), the Ventral Pallidal (VP), the Sub Thalamic Nucleus (STN) among others. Some regions are involved in multiple aspects of cost-benefit computations while the involvement of other regions is restricted to information relating to specific types of costs. Copyright © 2016 Elsevier Inc. All rights reserved.

Multivariable harmonic balance analysis of the neuronal oscillator for leech swimming.

PubMed

Chen, Zhiyong; Zheng, Min; Friesen, W Otto; Iwasaki, Tetsuya

2008-12-01

Biological systems, and particularly neuronal circuits, embody a very high level of complexity. Mathematical modeling is therefore essential for understanding how large sets of neurons with complex multiple interconnections work as a functional system. With the increase in computing power, it is now possible to numerically integrate a model with many variables to simulate behavior. However, such analysis can be time-consuming and may not reveal the mechanisms underlying the observed phenomena. An alternative, complementary approach is mathematical analysis, which can demonstrate direct and explicit relationships between a property of interest and system parameters. This paper introduces a mathematical tool for analyzing neuronal oscillator circuits based on multivariable harmonic balance (MHB). The tool is applied to a model of the central pattern generator (CPG) for leech swimming, which comprises a chain of weakly coupled segmental oscillators. The results demonstrate the effectiveness of the MHB method and provide analytical explanations for some CPG properties. In particular, the intersegmental phase lag is estimated to be the sum of a nominal value and a perturbation, where the former depends on the structure and span of the neuronal connections and the latter is roughly proportional to the period gradient, communication delay, and the reciprocal of the intersegmental coupling strength.

Nonlinear relaxation algorithms for circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saleh, R.A.

Circuit simulation is an important Computer-Aided Design (CAD) tool in the design of Integrated Circuits (IC). However, the standard techniques used in programs such as SPICE result in very long computer-run times when applied to large problems. In order to reduce the overall run time, a number of new approaches to circuit simulation were developed and are described. These methods are based on nonlinear relaxation techniques and exploit the relative inactivity of large circuits. Simple waveform-processing techniques are described to determine the maximum possible speed improvement that can be obtained by exploiting this property of large circuits. Three simulation algorithmsmore » are described, two of which are based on the Iterated Timing Analysis (ITA) method and a third based on the Waveform-Relaxation Newton (WRN) method. New programs that incorporate these techniques were developed and used to simulate a variety of industrial circuits. The results from these simulations are provided. The techniques are shown to be much faster than the standard approach. In addition, a number of parallel aspects of these algorithms are described, and a general space-time model of parallel-task scheduling is developed.« less

A new method for blood velocity measurements using ultrasound FMCW signals.

PubMed

Kunita, Masanori; Sudo, Masamitsu; Inoue, Shinya; Akahane, Mutsuhiro

2010-05-01

The low peak power of frequency-modulated continuous wave (FMCW) radar makes it attractive for various applications, including vehicle collision warning systems and airborne radio altimeters. This paper describes a new ultrasound Doppler measurement system that measures blood flow velocity based on principles similar to those of FMCW radar. We propose a sinusoidal wave for FM modulation and introduce a new demodulation technique for obtaining Doppler information with high SNR and range resolution. Doppler signals are demodulated with a reference FMCW signal to adjust delay times so that they are equal to propagation times between the transmitter and the receiver. Analytical results suggest that Doppler signals can be obtained from a selected position, as with a sample volume in pulse wave Doppler systems, and that the resulting SNR is nearly identical to that obtained with continuous wave (CW) Doppler systems. Additionally, clutter power is less than that of CW Doppler systems. The analytical results were verified by experiments involving electronic circuits and Doppler ultrasound phantoms.

High-speed pulse-shape generator, pulse multiplexer

DOEpatents

Burkhart, Scott C.

2002-01-01

The invention combines arbitrary amplitude high-speed pulses for precision pulse shaping for the National Ignition Facility (NIF). The circuitry combines arbitrary height pulses which are generated by replicating scaled versions of a trigger pulse and summing them delayed in time on a pulse line. The combined electrical pulses are connected to an electro-optic modulator which modulates a laser beam. The circuit can also be adapted to combine multiple channels of high speed data into a single train of electrical pulses which generates the optical pulses for very high speed optical communication. The invention has application in laser pulse shaping for inertial confinement fusion, in optical data links for computers, telecommunications, and in laser pulse shaping for atomic excitation studies. The invention can be used to effect at least a 10.times. increase in all fiber communication lines. It allows a greatly increased data transfer rate between high-performance computers. The invention is inexpensive enough to bring high-speed video and data services to homes through a super modem.

Studies on a wearable, electronic, transdermal alcohol sensor.

PubMed

Swift, R M; Martin, C S; Swette, L; LaConti, A; Kackley, N

1992-08-01

The measurement of alcohol consumption over long time periods is important for monitoring treatment outcome and for research applications. Giner, Inc. has developed a wearable device that senses ethanol vapor at the surface of the skin, using an electrochemical cell that produces a continuous current signal proportional to ethanol concentration. A thermistor monitors continuous contact of the sensor with the skin, and a data-acquisition/logic circuit stores days of data recorded at 2- to 5-min intervals. Testing of this novel ethanol sensor/recorder was conducted on nonalcoholic human subjects consuming known quantities of ethanol and on intoxicated alcoholic subjects. The transdermal sensor signal closely follows the pattern of the blood alcohol concentration curve, although with a delay. This paper describes the concept of electrochemical ethanol measurement and presents some of the clinical data collected in support of the sensor/recorder development.

Computational Architecture of the Granular Layer of Cerebellum-Like Structures.

PubMed

Bratby, Peter; Sneyd, James; Montgomery, John

2017-02-01

In the adaptive filter model of the cerebellum, the granular layer performs a recoding which expands incoming mossy fibre signals into a temporally diverse set of basis signals. The underlying neural mechanism is not well understood, although various mechanisms have been proposed, including delay lines, spectral timing and echo state networks. Here, we develop a computational simulation based on a network of leaky integrator neurons, and an adaptive filter performance measure, which allows candidate mechanisms to be compared. We demonstrate that increasing the circuit complexity improves adaptive filter performance, and relate this to evolutionary innovations in the cerebellum and cerebellum-like structures in sharks and electric fish. We show how recurrence enables an increase in basis signal duration, which suggest a possible explanation for the explosion in granule cell numbers in the mammalian cerebellum.

A common stochastic accumulator with effector-dependent noise can explain eye-hand coordination

PubMed Central

Gopal, Atul; Viswanathan, Pooja

2015-01-01

The computational architecture that enables the flexible coupling between otherwise independent eye and hand effector systems is not understood. By using a drift diffusion framework, in which variability of the reaction time (RT) distribution scales with mean RT, we tested the ability of a common stochastic accumulator to explain eye-hand coordination. Using a combination of behavior, computational modeling and electromyography, we show how a single stochastic accumulator to threshold, followed by noisy effector-dependent delays, explains eye-hand RT distributions and their correlation, while an alternate independent, interactive eye and hand accumulator model does not. Interestingly, the common accumulator model did not explain the RT distributions of the same subjects when they made eye and hand movements in isolation. Taken together, these data suggest that a dedicated circuit underlies coordinated eye-hand planning. PMID:25568161

Memory feedback PID control for exponential synchronisation of chaotic Lur'e systems

NASA Astrophysics Data System (ADS)

Zhang, Ruimei; Zeng, Deqiang; Zhong, Shouming; Shi, Kaibo

2017-09-01

This paper studies the problem of exponential synchronisation of chaotic Lur'e systems (CLSs) via memory feedback proportional-integral-derivative (PID) control scheme. First, a novel augmented Lyapunov-Krasovskii functional (LKF) is constructed, which can make full use of the information on time delay and activation function. Second, improved synchronisation criteria are obtained by using new integral inequalities, which can provide much tighter bounds than what the existing integral inequalities can produce. In comparison with existing results, in which only proportional control or proportional derivative (PD) control is used, less conservative results are derived for CLSs by PID control. Third, the desired memory feedback controllers are designed in terms of the solution to linear matrix inequalities. Finally, numerical simulations of Chua's circuit and neural network are provided to show the effectiveness and advantages of the proposed results.

Versatile microsecond movie camera

NASA Astrophysics Data System (ADS)

Dreyfus, R. W.

1980-03-01

A laboratory-type movie camera is described which satisfies many requirements in the range 1 microsec to 1 sec. The camera consists of a He-Ne laser and compatible state-of-the-art components; the primary components are an acoustooptic modulator, an electromechanical beam deflector, and a video tape system. The present camera is distinct in its operation in that submicrosecond laser flashes freeze the image motion while still allowing the simplicity of electromechanical image deflection in the millisecond range. The gating and pulse delay circuits of an oscilloscope synchronize the modulator and scanner relative to the subject being photographed. The optical table construction and electronic control enhance the camera's versatility and adaptability. The instant replay video tape recording allows for easy synchronization and immediate viewing of the results. Economy is achieved by using off-the-shelf components, optical table construction, and short assembly time.

Communication and wiring in the cortical connectome

PubMed Central

Budd, Julian M. L.; Kisvárday, Zoltán F.

2012-01-01

In cerebral cortex, the huge mass of axonal wiring that carries information between near and distant neurons is thought to provide the neural substrate for cognitive and perceptual function. The goal of mapping the connectivity of cortical axons at different spatial scales, the cortical connectome, is to trace the paths of information flow in cerebral cortex. To appreciate the relationship between the connectome and cortical function, we need to discover the nature and purpose of the wiring principles underlying cortical connectivity. A popular explanation has been that axonal length is strictly minimized both within and between cortical regions. In contrast, we have hypothesized the existence of a multi-scale principle of cortical wiring where to optimize communication there is a trade-off between spatial (construction) and temporal (routing) costs. Here, using recent evidence concerning cortical spatial networks we critically evaluate this hypothesis at neuron, local circuit, and pathway scales. We report three main conclusions. First, the axonal and dendritic arbor morphology of single neocortical neurons may be governed by a similar wiring principle, one that balances the conservation of cellular material and conduction delay. Second, the same principle may be observed for fiber tracts connecting cortical regions. Third, the absence of sufficient local circuit data currently prohibits any meaningful assessment of the hypothesis at this scale of cortical organization. To avoid neglecting neuron and microcircuit levels of cortical organization, the connectome framework should incorporate more morphological description. In addition, structural analyses of temporal cost for cortical circuits should take account of both axonal conduction and neuronal integration delays, which appear mostly of the same order of magnitude. We conclude the hypothesized trade-off between spatial and temporal costs may potentially offer a powerful explanation for cortical wiring patterns. PMID:23087619

Local Stability of AIDS Epidemic Model Through Treatment and Vertical Transmission with Time Delay

NASA Astrophysics Data System (ADS)

Novi W, Cascarilla; Lestari, Dwi

2016-02-01

This study aims to explain stability of the spread of AIDS through treatment and vertical transmission model. Human with HIV need a time to positively suffer AIDS. The existence of a time, human with HIV until positively suffer AIDS can be delayed for a time so that the model acquired is the model with time delay. The model form is a nonlinear differential equation with time delay, SIPTA (susceptible-infected-pre AIDS-treatment-AIDS). Based on SIPTA model analysis results the disease free equilibrium point and the endemic equilibrium point. The disease free equilibrium point with and without time delay are local asymptotically stable if the basic reproduction number is less than one. The endemic equilibrium point will be local asymptotically stable if the time delay is less than the critical value of delay, unstable if the time delay is more than the critical value of delay, and bifurcation occurs if the time delay is equal to the critical value of delay.

Full circuit calculation for electromagnetic pulse transmission in a high current facility

NASA Astrophysics Data System (ADS)

Zou, Wenkang; Guo, Fan; Chen, Lin; Song, Shengyi; Wang, Meng; Xie, Weiping; Deng, Jianjun

2014-11-01

We describe herein for the first time a full circuit model for electromagnetic pulse transmission in the Primary Test Stand (PTS)—the first TW class pulsed power driver in China. The PTS is designed to generate 8-10 MA current into a z -pinch load in nearly 90 ns rise time for inertial confinement fusion and other high energy density physics research. The PTS facility has four conical magnetic insulation transmission lines, in which electron current loss exists during the establishment of magnetic insulation. At the same time, equivalent resistance of switches and equivalent inductance of pinch changes with time. However, none of these models are included in a commercially developed circuit code so far. Therefore, in order to characterize the electromagnetic transmission process in the PTS, a full circuit model, in which switch resistance, magnetic insulation transmission line current loss and a time-dependent load can be taken into account, was developed. Circuit topology and an equivalent circuit model of the facility were introduced. Pulse transmission calculation of shot 0057 was demonstrated with the corresponding code FAST (full-circuit analysis and simulation tool) by setting controllable parameters the same as in the experiment. Preliminary full circuit simulation results for electromagnetic pulse transmission to the load are presented. Although divergences exist between calculated and experimentally obtained waveforms before the vacuum section, consistency with load current is satisfactory, especially at the rising edge.

Design of An Energy Efficient Hydraulic Regenerative circuit

NASA Astrophysics Data System (ADS)

Ramesh, S.; Ashok, S. Denis; Nagaraj, Shanmukha; Adithyakumar, C. R.; Reddy, M. Lohith Kumar; Naulakha, Niranjan Kumar

2018-02-01

Increasing cost and power demand, leads to evaluation of new method to increase through productivity and help to solve the power demands. Many researchers have break through to increase the efficiency of a hydraulic power pack, one of the promising methods is the concept of regenerative. The objective of this research work is to increase the efficiency of a hydraulic circuit by introducing a concept of regenerative circuit. A Regenerative circuit is a system that is used to speed up the extension stroke of the double acting single rod hydraulic cylinder. The output is connected to the input in the directional control value. By this concept, increase in velocity of the piston and decrease the cycle time. For the research, a basic hydraulic circuit and a regenerative circuit are designated and compared both with their results. The analysis was based on their time taken for extension and retraction of the piston. From the detailed analysis of both the hydraulic circuits, it is found that the efficiency by introducing hydraulic regenerative circuit increased by is 5.3%. The obtained results conclude that, implementing hydraulic regenerative circuit in a hydraulic power pack decreases power consumption, reduces cycle time and increases productivity in a longer run.

The effects of the framing of time on delay discounting.

PubMed

DeHart, William Brady; Odum, Amy L

2015-01-01

We examined the effects of the framing of time on delay discounting. Delay discounting is the process by which delayed outcomes are devalued as a function of time. Time in a titrating delay discounting task is often framed in calendar units (e.g., as 1 week, 1 month, etc.). When time is framed as a specific date, delayed outcomes are discounted less compared to the calendar format. Other forms of framing time; however, have not been explored. All participants completed a titrating calendar unit delay-discounting task for money. Participants were also assigned to one of two delay discounting tasks: time as dates (e.g., June 1st, 2015) or time in units of days (e.g., 5000 days), using the same delay distribution as the calendar delay-discounting task. Time framed as dates resulted in less discounting compared to the calendar method, whereas time framed as days resulted in greater discounting compared to the calendar method. The hyperboloid model fit best compared to the hyperbola and exponential models. How time is framed may alter how participants attend to the delays as well as how the delayed outcome is valued. Altering how time is framed may serve to improve adherence to goals with delayed outcomes. © Society for the Experimental Analysis of Behavior.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Development of a Low-cost, FPGA-based, Delay Line Particle Detector for Satellite and Sounding Rocket Applications

NASA Astrophysics Data System (ADS)

Harrington, M.; Kujawski, J. T.; Adrian, M. L.; Weatherwax, A. T.

2013-12-01

Electrons are, by definition, a fundamental, chemical and electromagnetic constituent of any plasma. This is especially true within the partially ionized plasmas of Earth's ionosphere where electrons are a critical component of a vast array of plasma processes. Siena College is working on a novel method of processing information from electron spectrometer anodes using delay line techniques and inexpensive COTS electronics to track the movement of high-energy particles. Electron spectrometers use a variety of techniques to determine where an amplified electron cloud falls onto a collecting surface. One traditional method divides the collecting surface into sectors and uses a single detector for each sector. However, as the angular and spatial resolution increases, so does the number of detectors, increasing power consumption, cost, size, and weight of the system. An alternative approach is to connect each sector with a delay line built within the PCB material which is shielded from cross talk by a flooded ground plane. Only one pair of detectors (e.g., one at each end of the chain) are needed with the delay line technique which is different from traditional delay line detectors which use either Application Specific Integrated Circuits (ASICs) or very fast clocks. In this paper, we report on the implementation and testing of a delay line detector using a low-cost Xilinx FPGA and a thirty-two sector delay system. This Delay Line Detector has potential satellite and rocket flight applications due to its low cost, small size and power efficiency

Integration of myocardial scar identified by preoperative delayed contrast-enhanced MRI into a high-resolution mapping system for planning and guidance of VT ablation procedures

NASA Astrophysics Data System (ADS)

Rettmann, M. E.; Suzuki, A.; Wang, S.; Pottinger, N.; Arter, J.; Netzer, A.; Parker, K.; Viker, K.; Packer, D. L.

2017-03-01

Myocardial scarring creates a substrate for reentrant circuits which can lead to ventricular tachycardia. In ventricular catheter ablation therapy, regions of myocardial scarring are targeted to interrupt arrhythmic electrical pathways. Low voltage regions are a surrogate for myocardial scar and are identified by generating an electro anatomic map at the start of the procedure. Recent efforts have focussed on integration of preoperative scar information generated from delayed contrast-enhanced MR imaging to augment intraprocedural information. In this work, we describe an initial feasibility study of integration of a preoperative MRI derived scar maps into a high-resolution mapping system to improve planning and guidance of VT ablation procedures.