LOGARITHMIC AMPLIFIER

DOEpatents

De Shong, J.A. Jr.

1957-12-31

A logarithmic current amplifier circuit having a high sensitivity and fast response is described. The inventor discovered the time constant of the input circuit of a system utilizing a feedback amplifier, ionization chamber, and a diode, is inversely proportional to the input current, and that the amplifier becomes unstable in amplifying signals in the upper frequency range when the amplifier's forward gain time constant equals the input circuit time constant. The described device incorporates impedance networks having low frequency response characteristic at various points in the circuit to change the forward gain of the amplifler at a rate of 0.7 of the gain magnitude for every two times increased in frequency. As a result of this improvement, the time constant of the input circuit is greatly reduced at high frequencies, and the amplifier response is increased.

Solid state remote circuit selector switch

NASA Technical Reports Server (NTRS)

Peterson, V. S.

1970-01-01

Remote switching circuit utilizes voltage logic to switch on desired circuit. Circuit controls rotating multi-range pressure transducers in jet engine testing and can be used in coded remote circuit activator where sequence of switching has to occur in defined length of time to prevent false or undesired circuit activation.

Variable-pulse switching circuit accurately controls solenoid-valve actuations

NASA Technical Reports Server (NTRS)

Gillett, J. D.

1967-01-01

Solid state circuit generating adjustable square wave pulses of sufficient power operates a 28 volt dc solenoid valve at precise time intervals. This circuit is used for precise time control of fluid flow in combustion experiments.

Three-phase short circuit calculation method based on pre-computed surface for doubly fed induction generator

NASA Astrophysics Data System (ADS)

Ma, J.; Liu, Q.

2018-02-01

This paper presents an improved short circuit calculation method, based on pre-computed surface to determine the short circuit current of a distribution system with multiple doubly fed induction generators (DFIGs). The short circuit current, injected into power grid by DFIG, is determined by low voltage ride through (LVRT) control and protection under grid fault. However, the existing methods are difficult to calculate the short circuit current of DFIG in engineering practice due to its complexity. A short circuit calculation method, based on pre-computed surface, was proposed by developing the surface of short circuit current changing with the calculating impedance and the open circuit voltage. And the short circuit currents were derived by taking into account the rotor excitation and crowbar activation time. Finally, the pre-computed surfaces of short circuit current at different time were established, and the procedure of DFIG short circuit calculation considering its LVRT was designed. The correctness of proposed method was verified by simulation.

ADDER CIRCUIT

DOEpatents

Jacobsohn, D.H.; Merrill, L.C.

1959-01-20

An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.

Dead-time compensation for a logarithmic display rate meter

DOEpatents

Larson, John A.; Krueger, Frederick P.

1988-09-20

An improved circuit is provided for application to a radiation survey meter that uses a detector that is subject to dead time. The circuit compensates for dead time over a wide range of count rates by producing a dead-time pulse for each detected event, a live-time pulse that spans the interval between dead-time pulses, and circuits that average the value of these pulses over time. The logarithm of each of these values is obtained and the logarithms are subtracted to provide a signal that is proportional to a count rate that is corrected for the effects of dead time. The circuit produces a meter indication and is also capable of producing an audible indication of detected events.

Dead-time compensation for a logarithmic display rate meter

DOEpatents

Larson, J.A.; Krueger, F.P.

1987-10-05

An improved circuit is provided for application to a radiation survey meter that uses a detector that is subject to dead time. The circuit compensates for dead time over a wide range of count rates by producing a dead-time pulse for each detected event, a live-time pulse that spans the interval between dead-time pulses, and circuits that average the value of these pulses over time. The logarithm of each of these values is obtained and the logarithms are subtracted to provide a signal that is proportional to a count rate that is corrected for the effects of dead time. The circuit produces a meter indication and is also capable of producing an audible indication of detected events. 5 figs.

Nonlinear relaxation algorithms for circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saleh, R.A.

Circuit simulation is an important Computer-Aided Design (CAD) tool in the design of Integrated Circuits (IC). However, the standard techniques used in programs such as SPICE result in very long computer-run times when applied to large problems. In order to reduce the overall run time, a number of new approaches to circuit simulation were developed and are described. These methods are based on nonlinear relaxation techniques and exploit the relative inactivity of large circuits. Simple waveform-processing techniques are described to determine the maximum possible speed improvement that can be obtained by exploiting this property of large circuits. Three simulation algorithmsmore » are described, two of which are based on the Iterated Timing Analysis (ITA) method and a third based on the Waveform-Relaxation Newton (WRN) method. New programs that incorporate these techniques were developed and used to simulate a variety of industrial circuits. The results from these simulations are provided. The techniques are shown to be much faster than the standard approach. In addition, a number of parallel aspects of these algorithms are described, and a general space-time model of parallel-task scheduling is developed.« less

Full circuit calculation for electromagnetic pulse transmission in a high current facility

NASA Astrophysics Data System (ADS)

Zou, Wenkang; Guo, Fan; Chen, Lin; Song, Shengyi; Wang, Meng; Xie, Weiping; Deng, Jianjun

2014-11-01

We describe herein for the first time a full circuit model for electromagnetic pulse transmission in the Primary Test Stand (PTS)—the first TW class pulsed power driver in China. The PTS is designed to generate 8-10 MA current into a z -pinch load in nearly 90 ns rise time for inertial confinement fusion and other high energy density physics research. The PTS facility has four conical magnetic insulation transmission lines, in which electron current loss exists during the establishment of magnetic insulation. At the same time, equivalent resistance of switches and equivalent inductance of pinch changes with time. However, none of these models are included in a commercially developed circuit code so far. Therefore, in order to characterize the electromagnetic transmission process in the PTS, a full circuit model, in which switch resistance, magnetic insulation transmission line current loss and a time-dependent load can be taken into account, was developed. Circuit topology and an equivalent circuit model of the facility were introduced. Pulse transmission calculation of shot 0057 was demonstrated with the corresponding code FAST (full-circuit analysis and simulation tool) by setting controllable parameters the same as in the experiment. Preliminary full circuit simulation results for electromagnetic pulse transmission to the load are presented. Although divergences exist between calculated and experimentally obtained waveforms before the vacuum section, consistency with load current is satisfactory, especially at the rising edge.

Design of An Energy Efficient Hydraulic Regenerative circuit

NASA Astrophysics Data System (ADS)

Ramesh, S.; Ashok, S. Denis; Nagaraj, Shanmukha; Adithyakumar, C. R.; Reddy, M. Lohith Kumar; Naulakha, Niranjan Kumar

2018-02-01

Increasing cost and power demand, leads to evaluation of new method to increase through productivity and help to solve the power demands. Many researchers have break through to increase the efficiency of a hydraulic power pack, one of the promising methods is the concept of regenerative. The objective of this research work is to increase the efficiency of a hydraulic circuit by introducing a concept of regenerative circuit. A Regenerative circuit is a system that is used to speed up the extension stroke of the double acting single rod hydraulic cylinder. The output is connected to the input in the directional control value. By this concept, increase in velocity of the piston and decrease the cycle time. For the research, a basic hydraulic circuit and a regenerative circuit are designated and compared both with their results. The analysis was based on their time taken for extension and retraction of the piston. From the detailed analysis of both the hydraulic circuits, it is found that the efficiency by introducing hydraulic regenerative circuit increased by is 5.3%. The obtained results conclude that, implementing hydraulic regenerative circuit in a hydraulic power pack decreases power consumption, reduces cycle time and increases productivity in a longer run.

46 CFR 169.670 - Circuit breakers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... Gross Tons § 169.670 Circuit breakers. Each circuit breaker must be of the manually reset type designed for— (a) Inverse time delay; (b) Instantaneous short circuit protection; and (c) Repeated opening of... 46 Shipping 7 2010-10-01 2010-10-01 false Circuit breakers. 169.670 Section 169.670 Shipping COAST...

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

PubMed

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

Active quench and reset integrated circuit with novel hold-off time control logic for Geiger-mode avalanche photodiodes.

PubMed

Deng, Shijie; Morrison, Alan P

2012-09-15

This Letter presents an active quench-and-reset circuit for Geiger-mode avalanche photodiodes (GM-APDs). The integrated circuit was fabricated using a conventional 0.35 μm complementary metal oxide semiconductor process. Experimental results show that the circuit is capable of linearly setting the hold-off time from several nanoseconds to microseconds with a resolution of 6.5 ns. This allows the selection of the optimal afterpulse-free hold-off time for the GM-APD via external digital inputs or additional signal processing circuitry. Moreover, this circuit resets the APD automatically following the end of the hold-off period, thus simplifying the control for the end user. Results also show that a minimum dead time of 28.4 ns is achieved, demonstrating a saturated photon-counting rate of 35.2 Mcounts/s.

Quantum circuit dynamics via path integrals: Is there a classical action for discrete-time paths?

NASA Astrophysics Data System (ADS)

Penney, Mark D.; Enshan Koh, Dax; Spekkens, Robert W.

2017-07-01

It is straightforward to compute the transition amplitudes of a quantum circuit using the sum-over-paths methodology when the gates in the circuit are balanced, where a balanced gate is one for which all non-zero transition amplitudes are of equal magnitude. Here we consider the question of whether, for such circuits, the relative phases of different discrete-time paths through the configuration space can be defined in terms of a classical action, as they are for continuous-time paths. We show how to do so for certain kinds of quantum circuits, namely, Clifford circuits where the elementary systems are continuous-variable systems or discrete systems of odd-prime dimension. These types of circuit are distinguished by having phase-space representations that serve to define their classical counterparts. For discrete systems, the phase-space coordinates are also discrete variables. We show that for each gate in the generating set, one can associate a symplectomorphism on the phase-space and to each of these one can associate a generating function, defined on two copies of the configuration space. For discrete systems, the latter association is achieved using tools from algebraic geometry. Finally, we show that if the action functional for a discrete-time path through a sequence of gates is defined using the sum of the corresponding generating functions, then it yields the correct relative phases for the path-sum expression. These results are likely to be relevant for quantizing physical theories where time is fundamentally discrete, characterizing the classical limit of discrete-time quantum dynamics, and proving complexity results for quantum circuits.

New Concept Firefighting Agent Delivery System

DTIC Science & Technology

1992-05-01

timer circuit . The time to rupture could be determined by the interactive computer associated with the kazincher system based on range-to-target and...windage effects. The timer circuit considered was a simple resistance capacitance (RC) timing network wi:h a set rate of discharge. The capacito, would...circut -to the canister timing circuit would be separated at launch and could initir.te the timing sequence. A "g" switch could aiso be used to

Temporal learning in the cerebellum: The microcircuit model

NASA Technical Reports Server (NTRS)

Miles, Coe F.; Rogers, David

1990-01-01

The cerebellum is that part of the brain which coordinates motor reflex behavior. To perform effectively, it must learn to generate specific motor commands at the proper times. We propose a fundamental circuit, called the MicroCircuit, which is the minimal ensemble of neurons both necessary and sufficient to learn timing. We describe how learning takes place in the MicroCircuit, which then explains the global behavior of the cerebellum as coordinated MicroCircuit behavior.

Response characteristic of high-speed on/off valve with double voltage driving circuit

NASA Astrophysics Data System (ADS)

Li, P. X.; Su, M.; Zhang, D. B.

2017-07-01

High-speed on/off valve, an important part of turbocharging system, its quick response has a direct impact on the turbocharger pressure cycle. The methods of improving the response characteristic of high speed on/off valve include increasing the magnetic force of armature and the voltage, decreasing the mass and current of coil. The less coil number of turns, the solenoid force is smaller. The special armature structure and the magnetic material will raise cost. In this paper a new scheme of double voltage driving circuit is investigated, in which the original driving circuit of high-speed on/off valve is replaced by double voltage driving circuit. The detailed theoretical analysis and simulations were carried out on the double voltage driving circuit, it showed that the switching time and delay time of the valve respectively are 3.3ms, 5.3ms, 1.9ms and 1.8ms. When it is driven by the double voltage driving circuit, the switching time and delay time of this valve are reduced, optimizing its response characteristic. By the comparison related factors (such as duty cycle or working frequency) about influences on response characteristic, the superior of double voltage driving circuit has been further confirmed.

Predilution versus postdilution during continuous venovenous hemofiltration: a comparison of circuit thrombogenesis.

PubMed

de Pont, Anne-Cornélie J M; Bouman, Catherine S C; Bakhtiari, Kamran; Schaap, Marianne C L; Nieuwland, Rienk; Sturk, Augueste; Hutten, Barbara A; de Jonge, Evert; Vroom, Margreeth B; Meijers, Joost C M; Büller, Harry R

2006-01-01

During continuous venovenous hemofiltration, predilution can prolong circuit survival time, but the underlying mechanism has not been elucidated. The aim of the present study was to compare predilution with postdilution, with respect to circuit thrombogenesis. Eight critically ill patients were treated with both predilutional and postdilutional continuous venovenous hemofiltration in a crossover fashion. A filtration flow of 60 ml/min was used in both modes. We chose blood flows of 140 and 200 ml/min during predilution and postdilution, respectively, to keep the total flow through the hemofilter constant. Extracorporeal circuit pressures were measured hourly, and samples of blood and ultrafiltrate were collected at five different time points. Thrombin-antithrombin complexes and prothrombin fragments F1 + 2 were measured by ELISA, and platelet activation was assessed by flow cytometry. No signs of thrombin generation or platelet activation were found during either mode. During postdilution, baseline platelet count and maximal prefilter pressure had a linear relation, whereas both parameters were inversely related with circuit survival time. In summary, predilution and postdilution did not differ with respect to extracorporeal circuit thrombogenesis. During postdilution, baseline platelet count and maximal prefilter pressure were inversely related with circuit survival time.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nishimura, Takahiro, E-mail: t-nishimura@ist.osaka-u.ac.jp; Fujii, Ryo; Ogura, Yusuke

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on themore » DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.« less

Spike timing precision of neuronal circuits.

PubMed

Kilinc, Deniz; Demir, Alper

2018-06-01

Spike timing is believed to be a key factor in sensory information encoding and computations performed by the neurons and neuronal circuits. However, the considerable noise and variability, arising from the inherently stochastic mechanisms that exist in the neurons and the synapses, degrade spike timing precision. Computational modeling can help decipher the mechanisms utilized by the neuronal circuits in order to regulate timing precision. In this paper, we utilize semi-analytical techniques, which were adapted from previously developed methods for electronic circuits, for the stochastic characterization of neuronal circuits. These techniques, which are orders of magnitude faster than traditional Monte Carlo type simulations, can be used to directly compute the spike timing jitter variance, power spectral densities, correlation functions, and other stochastic characterizations of neuronal circuit operation. We consider three distinct neuronal circuit motifs: Feedback inhibition, synaptic integration, and synaptic coupling. First, we show that both the spike timing precision and the energy efficiency of a spiking neuron are improved with feedback inhibition. We unveil the underlying mechanism through which this is achieved. Then, we demonstrate that a neuron can improve on the timing precision of its synaptic inputs, coming from multiple sources, via synaptic integration: The phase of the output spikes of the integrator neuron has the same variance as that of the sample average of the phases of its inputs. Finally, we reveal that weak synaptic coupling among neurons, in a fully connected network, enables them to behave like a single neuron with a larger membrane area, resulting in an improvement in the timing precision through cooperation.

Sampling and Control Circuit Board for an Inertial Measurement Unit

NASA Technical Reports Server (NTRS)

Chelmins, David T (Inventor); Sands, Obed (Inventor); Powis, Richard T., Jr. (Inventor)

2016-01-01

A circuit board that serves as a control and sampling interface to an inertial measurement unit ("IMU") is provided. The circuit board is also configured to interface with a local oscillator and an external trigger pulse. The circuit board is further configured to receive the external trigger pulse from an external source that time aligns the local oscillator and initiates sampling of the inertial measurement device for data at precise time intervals based on pulses from the local oscillator. The sampled data may be synchronized by the circuit board with other sensors of a navigation system via the trigger pulse.

Multiplexer and time duration measuring circuit

DOEpatents

Gray, Jr., James

1980-01-01

A multiplexer device is provided for multiplexing data in the form of randomly developed, variable width pulses from a plurality of pulse sources to a master storage. The device includes a first multiplexer unit which includes a plurality of input circuits each coupled to one of the pulse sources, with all input circuits being disabled when one input circuit receives an input pulse so that only one input pulse is multiplexed by the multiplexer unit at any one time.

An electronic circuit that detects left ventricular ejection events by processing the arterial pressure waveform

NASA Technical Reports Server (NTRS)

Gebben, V. D.; Webb, J. A., Jr.

1972-01-01

An electronic circuit for processing arterial blood pressure waveform signals is described. The circuit detects blood pressure as the heart pumps blood through the aortic valve and the pressure distribution caused by aortic valve closure. From these measurements, timing signals for use in measuring the left ventricular ejection time is determined, and signals are provided for computer monitoring of the cardiovascular system. Illustrations are given of the circuit and pressure waveforms.

Influence of Time-Pickoff Circuit Parameters on LiDAR Range Precision

PubMed Central

Wang, Hongming; Yang, Bingwei; Huyan, Jiayue; Xu, Lijun

2017-01-01

A pulsed time-of-flight (TOF) measurement-based Light Detection and Ranging (LiDAR) system is more effective for medium-long range distances. As a key ranging unit, a time-pickoff circuit based on automatic gain control (AGC) and constant fraction discriminator (CFD) is designed to reduce the walk error and the timing jitter for obtaining the accurate time interval. Compared with Cramer–Rao lower bound (CRLB) and the estimation of the timing jitter, four parameters-based Monte Carlo simulations are established to show how the range precision is influenced by the parameters, including pulse amplitude, pulse width, attenuation fraction and delay time of the CFD. Experiments were carried out to verify the relationship between the range precision and three of the parameters, exclusing pulse width. It can be concluded that two parameters of the ranging circuit (attenuation fraction and delay time) were selected according to the ranging performance of the minimum pulse amplitude. The attenuation fraction should be selected in the range from 0.2 to 0.6 to achieve high range precision. The selection criterion of the time-pickoff circuit parameters is helpful for the ranging circuit design of TOF LiDAR system. PMID:29039772

PULSE RATE DIVIDER

DOEpatents

McDonald, H.C. Jr.

1962-12-18

A compact pulse-rate divider circuit affording low impedance output and high input pulse repetition rates is described. The circuit features a single secondary emission tube having a capacitor interposed between its dynode and its control grid. An output pulse is produced at the anode of the tube each time an incoming pulse at the control grid drives the tube above cutoff and the duration of each output pulse corresponds to the charging time of the capacitor. Pulses incoming during the time the grid bias established by the discharging capacitor is sufficiently negative that the pulses are unable to drive the tube above cutoff do not produce output pulses at the anode; these pulses are lost and a dividing action is thus produced by the circuit. The time constant of the discharge path may be vanied to vary in turn the division ratio of the circuit; the time constant of the charging circuit may be varied to vary the width of the output pulses. (AEC)

Differential transimpedance amplifier circuit for correlated differential amplification

DOEpatents

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Multiple channel programmable coincidence counter

DOEpatents

Arnone, Gaetano J.

1990-01-01

A programmable digital coincidence counter having multiple channels and featuring minimal dead time. Neutron detectors supply electrical pulses to a synchronizing circuit which in turn inputs derandomized pulses to an adding circuit. A random access memory circuit connected as a programmable length shift register receives and shifts the sum of the pulses, and outputs to a serializer. A counter is input by the adding circuit and downcounted by the seralizer, one pulse at a time. The decoded contents of the counter after each decrement is output to scalers.

Transient-Switch-Signal Suppressor

NASA Technical Reports Server (NTRS)

Bozeman, Richard J., Jr.

1995-01-01

Circuit delays transmission of switch-opening or switch-closing signal until after preset suppression time. Used to prevent transmission of undesired momentary switch signal. Basic mode of operation simple. Beginning of switch signal initiates timing sequence. If switch signal persists after preset suppression time, circuit transmits switch signal to external circuitry. If switch signal no longer present after suppression time, switch signal deemed transient, and circuit does not pass signal on to external circuitry, as though no transient switch signal. Suppression time preset at value large enough to allow for damping of underlying pressure wave or other mechanical transient.

High noise immunity one shot

NASA Technical Reports Server (NTRS)

Schaffer, G. L.

1972-01-01

Multivibrator circuit, which includes constant current source, isolates line noise from timing circuitry and field effect transistor controls circuit's operational modes. Circuit has high immunity to supply line noise.

Isolated thermocouple amplifier system for stirred fixed-bed gasifier

DOEpatents

Fasching, George E.

1992-01-01

A sensing system is provided for determining the bed temperature profile of the bed of a stirred, fixed-bed gasifier including a plurality of temperature sensors for sensing the bed temperature at different levels, a transmitter for transmitting data based on the outputs of the sensors to a remote operator's station, and a battery-based power supply. The system includes an isolation amplifier system comprising a plurality of isolation amplifier circuits for amplifying the outputs of the individual sensors. The isolation amplifier circuits each comprise an isolation operational amplifier connected to a sensor; a first "flying capacitor" circuit for, in operation, controlling the application of power from the power supply to the isolation amplifier; an output sample and hold circuit connected to the transmitter; a second "flying capacitor" circuit for, in operation, controlling the transfer of the output of the isolation amplifier to the sample and hold circuit; and a timing and control circuit for activating the first and second capacitor circuits in a predetermined timed sequence.

Another Nulling Hall-Effect Current-Measuring Circuit

NASA Technical Reports Server (NTRS)

Thibodeau, Phillip E.; Sullender, Craig C.

1993-01-01

Lightweight, low-power circuit provides noncontact measurement of alternating or direct current of many ampheres in main conductor. Advantages of circuit over other nulling Hall-effect current-measuring circuits is stability and accuracy increased by putting both analog-to-digital and digital-to-analog converters in nulling feedback loop. Converters and rest of circuit designed for operation at sampling rate of 100 kHz, but rate changed to alter time or frequency response of circuit.

A Global Circuit Diagram to Contrast the Behavior of the DC and AC Global Circuits

NASA Astrophysics Data System (ADS)

Williams, E.; Boldi, R. A.; Markson, R. J.

2017-12-01

The Earth-ionosphere cavity is home to both the classical DC and the AC (Schumann resonances) global circuits. The predominant source for the AC global circuit is lightning, but the sources for the DC global circuit source remains controversial. Separate measurements over many years have shown that the amplitude variation of global lightning and the AC global circuit is about twice that of the DC global circuit on both the diurnal and annual time scales. A global diagram is used to shed further light on this result and to explore the co-variation of the two global circuits. Actual measurements of the ionospheric potential (Vi) are plotted against the simultaneous global lightning flash rate F. The latter estimates are drawn from a global climatology of LIS/OTD satellite observations (Cecil et al., 2014) giving flash rate as a function of both Day of Year and UT time, and are used as best guesses for F at the time of the Vi observations. A least-squares linear fit through the data points on this diagram show a zero-flash-rate intercept for Vi that is more than half of the mean Vi ( 250 kV). This result suggests that electrified shower clouds (without lightning), possibly supplemented by convective transport of positive space charge in the marine boundary layer, are playing a greater role in driving the DC global circuit than previously suspected.

NASCOM network ground communications availability report

NASA Technical Reports Server (NTRS)

1983-01-01

A performance analysis of NASCOM Network circuits is presented. An objective of 99.80 percent availability has been established for all network circuits and an acceptable level of 99.50. A network narrative summary for the current month includes changes in network configurations, current month's totals for modes of service and trouble category losses, a discussion of trends, and significant losses that affected the performance indexes of individual or groups of circuits. A table and narrative summary of those circuits that failed to meet the objective of 99.80% availability for all network circuits and an acceptable level of 99.50. Lost time and interruption tables showing all circuits affected by outages, by trouble category, with their total time and events, scheduled operating hours, and individual availability indexes also are included. Selected circuits whose availabilities have or continue to affect the overall network availability are also analyzed.

Integrated neuron circuit for implementing neuromorphic system with synaptic device

NASA Astrophysics Data System (ADS)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

Monitoring Digital Closed-Loop Feedback Systems

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

Algorithms and architecture for multiprocessor based circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deutsch, J.T.

Accurate electrical simulation is critical to the design of high performance integrated circuits. Logic simulators can verify function and give first-order timing information. Switch level simulators are more effective at dealing with charge sharing than standard logic simulators, but cannot provide accurate timing information or discover DC problems. Delay estimation techniques and cell level simulation can be used in constrained design methods, but must be tuned for each application, and circuit simulation must still be used to generate the cell models. None of these methods has the guaranteed accuracy that many circuit designers desire, and none can provide detailed waveformmore » information. Detailed electrical-level simulation can predict circuit performance if devices and parasitics are modeled accurately. However, the computational requirements of conventional circuit simulators make it impractical to simulate current large circuits. In this dissertation, the implementation of Iterated Timing Analysis (ITA), a relaxation-based technique for accurate circuit simulation, on a special-purpose multiprocessor is presented. The ITA method is an SOR-Newton, relaxation-based method which uses event-driven analysis and selective trace to exploit the temporal sparsity of the electrical network. Because event-driven selective trace techniques are employed, this algorithm lends itself to implementation on a data-driven computer.« less

Energy-efficient neuron, synapse and STDP integrated circuits.

PubMed

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

A clocking discipline for two-phase digital integrated circuits

NASA Astrophysics Data System (ADS)

Noice, D. C.

1983-09-01

Sooner or later a designer of digital circuits must face the problem of timing verification so he can avoid errors caused by clock skew, critical races, and hazards. Unlike previous verification methods, such as timing simulation and timing analysis, the approach presented here guarantees correct operation despite uncertainty about delays in the circuit. The result is a clocking discipline that deals with timing abstractions only. It is not based on delay calculations; it is only concerned with the correct, synchronous operation at some clock rate. Accordingly, it may be used earlier in the design cycle, which is particularly important to integrated circuit designs. The clocking discipline consists of a notation of clocking types, and composition rules for using the types. Together, the notation and rules define a formal theory of two phase clocking. The notation defines the names and exact characteristics for different signals that are used in a two phase digital system. The notation makes it possible to develop rules for propagating the clocking types through particular circuits.

Design of high-linear CMOS circuit using a constant transconductance method for gamma-ray spectroscopy system

NASA Astrophysics Data System (ADS)

Jung, I. I.; Lee, J. H.; Lee, C. S.; Choi, Y.-W.

2011-02-01

We propose a novel circuit to be applied to the front-end integrated circuits of gamma-ray spectroscopy systems. Our circuit is designed as a type of current conveyor (ICON) employing a constant- gm (transconductance) method which can significantly improve the linearity in the amplified signals by using a large time constant and the time-invariant characteristics of an amplifier. The constant- gm method is obtained by a feedback control which keeps the transconductance of the input transistor constant. To verify the performance of the propose circuit, the time constant variations for the channel resistances are simulated with the TSMC 0.18 μm transistor parameters using HSPICE, and then compared with those of a conventional ICON. As a result, the proposed ICON shows only 0.02% output linearity variation and 0.19% time constant variation for the input amplitude up to 100 mV. These are significantly small values compared to a conventional ICON's 1.39% and 19.43%, respectively, for the same conditions.

Connecting Time and Frequency in the RC Circuit

NASA Astrophysics Data System (ADS)

Moya, A. A.

2017-04-01

Charging and discharging processes of a capacitor through a resistor, as well as the concept of impedance in alternating current circuits, are topics covered in introductory physics courses. The experimental study of the charge and discharge of a capacitor through a resistor is a well-established lab exercise that is used to introduce concepts such as exponential increase or decrease and time constant. Determining the time constant of the RC circuit has important practical applications because, for example, it can be used to measure unknown values of resistance or capacitance. The transient experiment can be done by using a voltmeter and stopwatch, signal generator and oscilloscope, or even low-cost data acquisition systems such as Arduino. An equivalent topic when studying alternating current circuits arises from the characterization of the impedance of the series or parallel combination of the capacitor and the resistor as a function of frequency. Determining the time constant of the RC circuit by means of impedance measurements for different frequencies is a known experimental technique that can be done using not only LCR meters but also basic instrumentation in the physics lab such as a signal generator, frequency counter, and multimeter. However, lab exercises dealing with RC circuits in alternating current usually focus on their use as filters, and the potential applications in the field of the electrical characterization of material systems are ignored. In this work, we describe a simple exercise showing how the time constant of the RC circuit can easily be determined in the introductory physics lab by means of impedance measurements as a function of frequency. This exercise allows students to learn experimental techniques that find application to characterize the time constants of the charge transport processes in material systems. Moreover, comparison of the time constants obtained from transient and frequency analysis allows us to relate the time and frequency domains, which plays a central role in the advanced analysis of electric circuits, once the concept of Laplace transform has been introduced in order to simplify the problem of dealing with differential equations in the time domain by converting them into algebraic equations within the frequency domain.

Circuit for measuring time differences among events

DOEpatents

Romrell, Delwin M.

1977-01-01

An electronic circuit has a plurality of input terminals. Application of a first input signal to any one of the terminals initiates a timing sequence. Later inputs to the same terminal are ignored but a later input to any other terminal of the plurality generates a signal which can be used to measure the time difference between the later input and the first input signal. Also, such time differences may be measured between the first input signal and an input signal to any other terminal of the plurality or the circuit may be reset at any time by an external reset signal.

Mechanisms of interactive specialization and emergence of functional brain circuits supporting cognitive development in children

NASA Astrophysics Data System (ADS)

Battista, Christian; Evans, Tanya M.; Ngoon, Tricia J.; Chen, Tianwen; Chen, Lang; Kochalka, John; Menon, Vinod

2018-01-01

Cognitive development is thought to depend on the refinement and specialization of functional circuits over time, yet little is known about how this process unfolds over the course of childhood. Here we investigated growth trajectories of functional brain circuits and tested an interactive specialization model of neurocognitive development which posits that the refinement of task-related functional networks is driven by a shared history of co-activation between cortical regions. We tested this model in a longitudinal cohort of 30 children with behavioral and task-related functional brain imaging data at multiple time points spanning childhood and adolescence, focusing on the maturation of parietal circuits associated with numerical problem solving and learning. Hierarchical linear modeling revealed selective strengthening as well as weakening of functional brain circuits. Connectivity between parietal and prefrontal cortex decreased over time, while connectivity within posterior brain regions, including intra-hemispheric and inter-hemispheric parietal connectivity, as well as parietal connectivity with ventral temporal occipital cortex regions implicated in quantity manipulation and numerical symbol recognition, increased over time. Our study provides insights into the longitudinal maturation of functional circuits in the human brain and the mechanisms by which interactive specialization shapes children's cognitive development and learning.

RADC SCAT automated sneak circuit analysis tool

NASA Astrophysics Data System (ADS)

Depalma, Edward L.

The sneak circuit analysis tool (SCAT) provides a PC-based system for real-time identification (during the design phase) of sneak paths and design concerns. The tool utilizes an expert system shell to assist the analyst so that prior experience with sneak analysis is not necessary for performance. Both sneak circuits and design concerns are targeted by this tool, with both digital and analog circuits being examined. SCAT focuses the analysis at the assembly level, rather than the entire system, so that most sneak problems can be identified and corrected by the responsible design engineer in a timely manner. The SCAT program identifies the sneak circuits to the designer, who then decides what course of action is necessary.

Insertion side, body position and circuit life during continuous renal replacement therapy with femoral vein access.

PubMed

Kim, In Byung; Fealy, Nigel; Baldwin, Ian; Bellomo, Rinaldo

2011-01-01

Choice of insertion side and patient position during continuous renal replacement therapy (CRRT) with femoral vein vascular access may affect circuit life. We investigated if there is an association between choice of insertion side and body position and its changes and circuit life during CRRT with femoral vein access. We studied 50 patients receiving CRRT via femoral vein access with a sequential retrospective study in a tertiary intensive care unit. We defined two groups: patients with right or left femoral vein access. We then obtained information on age, gender, circuit life, total heparin dose, hemoglobin concentration and coagulation variables (platelet count, international normalized ratio, and activated partial thromboplastin time) and percentage of time each patient spent in the supine, left lying, right lying, and sitting position during treatment. We studied 341 circuits in 50 patients. Mean circuit life was 13.9 h. Of these circuits, 251 (73.6%) were treated with right femoral vein access. Mean circuit life in this group was significantly longer compared with left femoral vein access (15.0 ± 14.3 vs. 10.6 ± 7.4; p = 0.019). Percentage spent in a particular position during CRRT was not significantly different between two groups. On multivariable linear regression analysis, mean circuit life was significantly and positively correlated with right vascular access site (p = 0.03) and lower platelet count (p = 0.03), but not with patient position. Right-sided insertion but not time spent in a particular position significantly affects circuit life during CRRT with femoral vein access. Copyright © 2010 S. Karger AG, Basel.

Tunnel diode circuit used as nanosecond-range time marker

NASA Technical Reports Server (NTRS)

Larsen, R. N.; Shear, E. B.

1968-01-01

Simple tunnel diode time marker circuit determines the time at which an event occurs in a scintillation crystal. It is capable of triggering at voltages as low as the noise level of a 10-stage PM tube.

Crosstalk-free operation of multielement superconducting nanowire single-photon detector array integrated with single-flux-quantum circuit in a 0.1 W Gifford-McMahon cryocooler.

PubMed

Yamashita, Taro; Miki, Shigehito; Terai, Hirotaka; Makise, Kazumasa; Wang, Zhen

2012-07-15

We demonstrate the successful operation of a multielement superconducting nanowire single-photon detector (SSPD) array integrated with a single-flux-quantum (SFQ) readout circuit in a compact 0.1 W Gifford-McMahon cryocooler. A time-resolved readout technique, where output signals from each element enter the SFQ readout circuit with finite time intervals, revealed crosstalk-free operation of the four-element SSPD array connected with the SFQ readout circuit. The timing jitter and the system detection efficiency were measured to be 50 ps and 11.4%, respectively, which were comparable to the performance of practical single-pixel SSPD systems.

Detonation control

DOEpatents

Mace, Jonathan L.; Seitz, Gerald J.; Bronisz, Lawrence E.

2016-10-25

Detonation control modules and detonation control circuits are provided herein. A trigger input signal can cause a detonation control module to trigger a detonator. A detonation control module can include a timing circuit, a light-producing diode such as a laser diode, an optically triggered diode, and a high-voltage capacitor. The trigger input signal can activate the timing circuit. The timing circuit can control activation of the light-producing diode. Activation of the light-producing diode illuminates and activates the optically triggered diode. The optically triggered diode can be coupled between the high-voltage capacitor and the detonator. Activation of the optically triggered diode causes a power pulse to be released from the high-voltage capacitor that triggers the detonator.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

People with stroke spend more time in active task practice, but similar time in walking practice, when physiotherapy rehabilitation is provided in circuit classes compared to individual therapy sessions: an observational study.

PubMed

English, Coralie; Hillier, Susan; Kaur, Gurpreet; Hundertmark, Laura

2014-03-01

Do people with stroke spend more time in active task practice during circuit class therapy sessions versus individual physiotherapy sessions? Do people with stroke practise different tasks during circuit class therapy sessions versus individual physiotherapy sessions? Prospective, observational study. Twenty-nine people with stroke in inpatient rehabilitation settings. Individual therapy sessions and circuit class therapy sessions provided within a larger randomised controlled trial. Seventy-nine therapy sessions were video-recorded and the footage was analysed for time spent engaged in various categories of activity. In a subsample of 28 videos, the number of steps taken by people with stroke per therapy session was counted. Circuit class therapy sessions were of a longer duration (mean difference 38.0minutes, 95% CI 29.9 to 46.1), and participants spent more time engaged in active task practice (mean difference 23.8minutes, 95% CI 16.1 to 31.4) compared with individual sessions. A greater percentage of time in circuit class therapy sessions was spent practising tasks in sitting (mean difference 5.3%, 95% CI 2.4 to 8.2) and in sit-to-stand practice (mean difference 2.7%, 95% CI 1.4 to 4.1), and a lower percentage of time in walking practice (mean difference 19.1%, 95% CI 10.0 to 28.1) compared with individual sessions. PARTICIPANTS took an average of 371 steps (SD 418) during therapy sessions and this did not differ significantly between group and individual sessions. People with stroke spent more time in active task practice, but a similar amount of time in walking practice when physiotherapy was offered in circuit class therapy sessions versus individual therapy sessions. There is a need for effective strategies to increase the amount of walking practice during physiotherapy sessions for people after stroke. Copyright © 2014 Australian Physiotherapy Association. Published by Elsevier B.V. All rights reserved.

Ladder-Type Circuits Revisited

ERIC Educational Resources Information Center

Yoon, Sung Hyun

2007-01-01

Ladder-type circuits where a given unit is repeated infinitely many times are dealt with in many textbooks on electromagnetism as examples of filter circuits. Determining the impedance of such circuits seems to be regarded as simple, which may be due to the fact that the invariance of the infinite system under the operation of adding one more unit…

Design and implementation of a simple acousto optic dual control circuit

NASA Astrophysics Data System (ADS)

Li, Biqing; Li, Zhao

2017-04-01

This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.

Retrieving fear memories, as time goes by…

PubMed Central

Do Monte, Fabricio H.; Quirk, Gregory J.; Li, Bo; Penzo, Mario A.

2016-01-01

Fear conditioning researches have led to a comprehensive picture of the neuronal circuit underlying the formation of fear memories. In contrast, knowledge about the retrieval of fear memories is much more limited. This disparity may stem from the fact that fear memories are not rigid, but reorganize over time. To bring clarity and raise awareness on the time-dependent dynamics of retrieval circuits, we review current evidence on the neuronal circuitry participating in fear memory retrieval at both early and late time points after conditioning. We focus on the temporal recruitment of the paraventricular nucleus of the thalamus, and its BDNFergic efferents to the central nucleus of the amygdala, for the retrieval and maintenance of fear memories. Finally, we speculate as to why retrieval circuits change across time, and the functional benefits of recruiting structures such as the paraventricular nucleus into the retrieval circuit. PMID:27217148

Variable-pulse-shape pulsed-power accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stoltzfus, Brian S.; Austin, Kevin; Hutsel, Brian Thomas

A variable-pulse-shape pulsed-power accelerator is driven by a large number of independent LC drive circuits. Each LC circuit drives one or more coaxial transmission lines that deliver the circuit's output power to several water-insulated radial transmission lines that are connected in parallel at small radius by a water-insulated post-hole convolute. The accelerator can be impedance matched throughout. The coaxial transmission lines are sufficiently long to transit-time isolate the LC drive circuits from the water-insulated transmission lines, which allows each LC drive circuit to be operated without being affected by the other circuits. This enables the creation of any power pulsemore » that can be mathematically described as a time-shifted linear combination of the pulses of the individual LC drive circuits. Therefore, the output power of the convolute can provide a variable pulse shape to a load that can be used for magnetically driven, quasi-isentropic compression experiments and other applications.« less

Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration

NASA Astrophysics Data System (ADS)

Zainudin, M. F.; Hussin, H.; Halim, A. K.; Karim, J.

2018-03-01

A mechanism known as Negative-bias Temperature Instability (NBTI) degrades a main electrical parameters of a circuit especially in terms of performance. So far, the circuit design available at present are only focussed on high performance circuit without considering the circuit reliability and robustness. In this paper, the main circuit performances of high performance FinFET flip-flop such as delay time, and power were studied with the presence of the NBTI degradation. The aging analysis was verified using a 16nm High Performance Predictive Technology Model (PTM) based on different commands available at Synopsys HSPICE. The results shown that the circuit under the longer dynamic NBTI simulation produces the highest impact in the increasing of gate delay and decrease in the average power reduction from a fresh simulation until the aged stress time under a nominal condition. In addition, the circuit performance under a varied stress condition such as temperature and negative stress gate bias were also studied.

Automated Design Tools for Integrated Mixed-Signal Microsystems (NeoCAD)

DTIC Science & Technology

2005-02-01

method, Model Order Reduction (MOR) tools, system-level, mixed-signal circuit synthesis and optimization tools, and parsitic extraction tools. A unique...Mission Area: Command and Control mixed signal circuit simulation parasitic extraction time-domain simulation IC design flow model order reduction... Extraction 1.2 Overall Program Milestones CHAPTER 2 FAST TIME DOMAIN MIXED-SIGNAL CIRCUIT SIMULATION 2.1 HAARSPICE Algorithms 2.1.1 Mathematical Background

Development of capacitive multiplexing circuit for SiPM-based time-of-flight (TOF) PET detector

NASA Astrophysics Data System (ADS)

Choe, Hyeok-Jun; Choi, Yong; Hu, Wei; Yan, Jianhua; Jung, Jin Ho

2017-04-01

There has been great interest in developing a time-of-flight (TOF) PET to improve the signal-to-noise ratio of PET image relative to that of non-TOF PET. Silicon photomultiplier (SiPM) arrays have attracted attention for use as a fast TOF PET photosensor. Since numerous SiPM arrays are needed to construct a modern human PET, a multiplexing method providing both good timing performance and high channel reduction capability is required to develop a SiPM-based TOF PET. The purpose of this study was to develop a capacitive multiplexing circuit for the SiPM-based TOF PET. The proposed multiplexing circuit was evaluated by measuring the coincidence resolving time (CRT) and the energy resolution as a function of the overvoltage using three different capacitor values of 15, 30, and 51 pF. A flood histogram was also obtained and quantitatively assessed. Experiments were performed using a 4× 4 array of 3× 3 mm2 SiPMs. Regarding the capacitor values, the multiplexing circuit using a smaller capacitor value showed the best timing performance. On the other hand, the energy resolution and flood histogram quality of the multiplexing circuit deteriorated as the capacitor value became smaller. The proposed circuit was able to achieve a CRT of 260+/- 4 ps FWHM and an energy resolution of 17.1 % with a pair of 2× 2× 20 mm3 LYSO crystals using a capacitor value of 30 pF at an overvoltage of 3.0 V. It was also possible to clearly resolve a 6× 6 array of LYSO crystals in the flood histogram using the multiplexing circuit. The experiment results indicate that the proposed capacitive multiplexing circuit is useful to obtain an excellent timing performance and a crystal-resolving capability in the flood histogram with a minimal degradation of the energy resolution, as well as to reduce the number of the readout channels of the SiPM-based TOF PET detector.

Frequency discriminator/phase detector

NASA Technical Reports Server (NTRS)

Crow, R. B.

1974-01-01

Circuit provides dual function of frequency discriminator/phase detector which reduces frequency acquisition time without adding to circuit complexity. Both frequency discriminators, in evaluated frequency discriminator/phase detector circuits, are effective two decades above and below center frequency.

Scaling up digital circuit computation with DNA strand displacement cascades.

PubMed

Qian, Lulu; Winfree, Erik

2011-06-03

To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Resonant circuit which provides dual frequency excitation for rapid cycling of an electromagnet

DOEpatents

Praeg, Walter F.

1984-01-01

Disclosed is a ring magnet control circuit that permits synchrotron repetition rates much higher than the frequency of the cosinusoidal guide field of the ring magnet during particle acceleration. the control circuit generates cosinusoidal excitation currents of different frequencies in the half waves. During radio frequency acceleration of the particles in the synchrotron, the control circuit operates with a lower frequency cosine wave and thereafter the electromagnets are reset with a higher frequency half cosine wave. Flat-bottom and flat-top wave shaping circuits maintain the magnetic guide field in a relatively time-invariant mode during times when the particles are being injected into the ring magnets and when the particles are being ejected from the ring magnets.

NASCOM network: Ground communications reliability report

NASA Technical Reports Server (NTRS)

1973-01-01

A reliability performance analysis of the NASCOM Network circuits is reported. Network performance narrative summary is presented to include significant changes in circuit configurations, current figures, and trends in each trouble category with notable circuit totals specified. Lost time and interruption tables listing circuits which were affected by outages showing their totals category are submitted. A special analysis of circuits with low reliabilities is developed with tables depicting the performance and graphs for individual reliabilities.

Simple photometer circuits using modular electronic components

NASA Technical Reports Server (NTRS)

Wampler, J. E.

1975-01-01

Operational and peak holding amplifiers are discussed as useful circuits for bioluminescence assays. Circuit diagrams are provided. While analog methods can give a good integration on short time scales, digital methods were found best for long term integration in bioluminescence assays. Power supplies, a general photometer circuit with ratio capability, and variations in the basic photometer design are also considered.

Geologic fracturing method and resulting fractured geologic structure

DOEpatents

Mace, Jonathan L.; Bradley, Christopher R.; Greening, Doran R.; Steedman, David W.

2016-11-08

Detonation control modules and detonation control circuits are provided herein. A trigger input signal can cause a detonation control module to trigger a detonator. A detonation control module can include a timing circuit, a light-producing diode such as a laser diode, an optically triggered diode, and a high-voltage capacitor. The trigger input signal can activate the timing circuit. The timing circuit can control activation of the light-producing diode. Activation of the light-producing diode illuminates and activates the optically triggered diode. The optically triggered diode can be coupled between the high-voltage capacitor and the detonator. Activation of the optically triggered diode causes a power pulse to be released from the high-voltage capacitor that triggers the detonator.

Resonance Frequency Readout Circuit for a 900 MHz SAW Device

PubMed Central

Liu, Heng; Zhang, Chun; Weng, Zhaoyang; Guo, Yanshu; Wang, Zhihua

2017-01-01

A monolithic resonance frequency readout circuit with high resolution and short measurement time is presented for a 900 MHz RF surface acoustic wave (SAW) sensor. The readout circuit is composed of a fractional-N phase-locked loop (PLL) as the stimulus source to the SAW device and a phase-based resonance frequency detecting circuit using successive approximation (SAR). A new resonance frequency searching strategy has been proposed based on the fact that the SAW device phase-frequency response crosses zero monotonically around the resonance frequency. A dedicated instant phase difference detecting circuit is adopted to facilitate the fast SAR operation for resonance frequency searching. The readout circuit has been implemented in 180 nm CMOS technology with a core area of 3.24 mm2. In the experiment, it works with a 900 MHz SAW resonator with a quality factor of Q = 130. Experimental results show that the readout circuit consumes 7 mW power from 1.6 V supply. The frequency resolution is 733 Hz, and the relative accuracy is 0.82 ppm, and it takes 0.48 ms to complete one measurement. Compared to the previous results in the literature, this work has achieved the shortest measurement time with a trade-off between measurement accuracy and measurement time. PMID:28914799

Resonance Frequency Readout Circuit for a 900 MHz SAW Device.

PubMed

Liu, Heng; Zhang, Chun; Weng, Zhaoyang; Guo, Yanshu; Wang, Zhihua

2017-09-15

A monolithic resonance frequency readout circuit with high resolution and short measurement time is presented for a 900 MHz RF surface acoustic wave (SAW) sensor. The readout circuit is composed of a fractional-N phase-locked loop (PLL) as the stimulus source to the SAW device and a phase-based resonance frequency detecting circuit using successive approximation (SAR). A new resonance frequency searching strategy has been proposed based on the fact that the SAW device phase-frequency response crosses zero monotonically around the resonance frequency. A dedicated instant phase difference detecting circuit is adopted to facilitate the fast SAR operation for resonance frequency searching. The readout circuit has been implemented in 180 nm CMOS technology with a core area of 3.24 mm². In the experiment, it works with a 900 MHz SAW resonator with a quality factor of Q = 130. Experimental results show that the readout circuit consumes 7 mW power from 1.6 V supply. The frequency resolution is 733 Hz, and the relative accuracy is 0.82 ppm, and it takes 0.48 ms to complete one measurement. Compared to the previous results in the literature, this work has achieved the shortest measurement time with a trade-off between measurement accuracy and measurement time.

Count-doubling time safety circuit

DOEpatents

Rusch, Gordon K.; Keefe, Donald J.; McDowell, William P.

1981-01-01

There is provided a nuclear reactor count-factor-increase time monitoring circuit which includes a pulse-type neutron detector, and means for counting the number of detected pulses during specific time periods. Counts are compared and the comparison is utilized to develop a reactor scram signal, if necessary.

Design of surface acoustic wave filters for the multiplex transmission system of multilevel inverter circuits

NASA Astrophysics Data System (ADS)

Kubo, Keita; Kanai, Nanae; Kobayashi, Fumiya; Goka, Shigeyoshi; Wada, Keiji; Kakio, Shoji

2017-07-01

We designed surface acoustic wave (SAW) filters for a multiplex transmission system of multilevel inverter circuits, and applied them to a single-phase three-level inverter. To reduce the transmission delay time of the SAW filters, a four-channel SAW filter array was fabricated and its characteristics were measured. The delay time of the SAW filters was <350 ns, and the delay time difference was reduced to ≤184 ns, less than half that previously reported. The SAW filters withstood up to 990 V, which is sufficient for the inverters used in most domestic appliances. A single-phase three-level inverter with the fabricated SAW filters worked with a total delay time shorter than our target delay time of 2.5 µs. The delay time difference of the proposed system was 0.26 µs, which is sufficient for preventing the inverter circuit from short-circuiting. The SAW filters controlled a multilevel inverter system with simple signal wiring and high dielectric withstanding voltages.

Bidirectional automatic release of reserve for low voltage network made with low capacity PLCs

NASA Astrophysics Data System (ADS)

Popa, I.; Popa, G. N.; Diniş, C. M.; Deaconu, S. I.

2018-01-01

The article presents the design of a bidirectional automatic release of reserve made on two types low capacity programmable logic controllers: PS-3 from Klöckner-Moeller and Zelio from Schneider. It analyses the electronic timing circuits that can be used for making the bidirectional automatic release of reserve: time-on delay circuit and time-off delay circuit (two types). In the paper are present the sequences code for timing performed on the PS-3 PLC, the logical functions for the bidirectional automatic release of reserve, the classical control electrical diagram (with contacts, relays, and time relays), the electronic control diagram (with logical gates and timing circuits), the code (in IL language) made for the PS-3 PLC, and the code (in FBD language) made for Zelio PLC. A comparative analysis will be carried out on the use of the two types of PLC and will be present the advantages of using PLCs.

Coating of human decay accelerating factor (hDAF) onto medical devices to improve biocompatibility.

PubMed

Watkins, N J; Braidley, P; Bray, C J; Savill, C M; White, D J

1997-12-01

In passing blood through an artificial circulatory system, the blood is exposed to surfaces that result in activation of the complement system. The consequences of the activation of complement can be extremely serious for the patient ranging from mild discomfort to respiratory distress and even anaphylaxis. An entirely novel approach was to express recombinant GPI anchored human decay accelerating factor (hDAF) using the baculovirus system and then coat the recombinant protein onto the surfaces of these materials to reduce complement activation. Expression of hDAF in Sf9 cells was shown by ELISA, FACS analysis, and Western blot. Functional activity was tested by CH50 assay. For the coating experiments a small scale model of a cardiovascular bypass circuit constructed from COBE tubing was used. hDAF was either coated onto the circuit using adsorption or covalently linked via the photoreactive crosslinker, p-azidobenzoyl hydrazide. After coating, heparinised human blood was pumped around the circuit and samples were collected into EDTA collection tubes at different time points. Complement activation was measured using a Quidel C3a-des-arg EIA. The photolinked circuits gave a reduction in C3a production of 20-50%, compared to 10-20% seen with an absorbed hDAF circuit. Furthermore, the inhibition of complement was seen over the whole time scale of the photolinked circuit, 60-90 min, whilst in the adsorbed circuit inhibition was not seen to a significant degree after 60 min. The time scale of a standard cardiac bypass is 45-90 min, therefore, the photolinked circuit results are encouraging, as significant inhibition of complement activation is seen within this time frame.

Wavelet analysis of near-resonant series RLC circuit with time-dependent forcing frequency

NASA Astrophysics Data System (ADS)

Caccamo, M. T.; Cannuli, A.; Magazù, S.

2018-07-01

In this work, the results of an analysis of the response of a near-resonant series resistance‑inductance‑capacitance (RLC) electric circuit with time-dependent forcing frequency by means of a wavelet cross-correlation approach are reported. In particular, it is shown how the wavelet approach enables frequency and time analysis of the circuit response to be carried out simultaneously—this procedure not being possible by Fourier transform, since the frequency is not stationary in time. A series RLC circuit simulation is performed by using the Simulation Program with Integrated Circuits Emphasis (SPICE), in which an oscillatory sinusoidal voltage drive signal of constant amplitude is swept through the resonant condition by progressively increasing the frequency over a 20-second time window, linearly, from 0.32 Hz to 6.69 Hz. It is shown that the wavelet cross-correlation procedure quantifies the common power between the input signal (represented by the electromotive force) and the output signal, which in the present case is a current, highlighting not only which frequencies are present but also when they occur, i.e. providing a simultaneous time-frequency analysis. The work is directed toward graduate Physics, Engineering and Mathematics students, with the main intention of introducing wavelet analysis into their data analysis toolkit.

On the SCTC-OCTC Method for the Analysis and Design of Circuits

ERIC Educational Resources Information Center

Salvatori, S.; Conte, G.

2009-01-01

This paper discusses guidelines that emphasize the relevance of short-circuit- and open-circuit-time constant (SCTC and OCTC, respectively) methods in the analysis and design of electronic amplifiers. It is demonstrated that it is only necessary to grasp a few concepts in order to understand that the two short- and open-circuit cases fall into a…

Analog Binaural Circuits for Detecting and Locating Leaks

NASA Technical Reports Server (NTRS)

Hartley, Frank T.

2003-01-01

Very-large-scale integrated (VLSI) analog binaural signal-processing circuits have been proposed for use in detecting and locating leaks that emit noise in the ultrasonic frequency range. These circuits would be designed to function even in the presence of intense lower-frequency background noise that could include sounds associated with flow and pumping. Each of the proposed circuits would include the approximate electronic equivalent of a right and a left cochlea plus correlator circuits. A pair of transducers (microphones or accelerometers), corresponding to right and left ears, would provide the inputs to their respective cochleas from different locations (e.g., from different positions along a pipe). The correlation circuits plus some additional external circuits would determine the difference between the times of arrival of a common leak sound at the two transducers. Then the distance along the pipe from either transducer to the leak could be estimated from the time difference and the speed of sound along the pipe. If three or more pairs of transducers and cochlear/correlator circuits were available and could suitably be positioned, it should be possible to locate a leak in three dimensions by use of sound propagating through air.

Polynomial time blackbox identity testers for depth-3 circuits : the field doesn't matter.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seshadhri, Comandur; Saxena, Nitin

Let C be a depth-3 circuit with n variables, degree d and top fanin k (called {Sigma}{Pi}{Sigma}(k, d, n) circuits) over base field F. It is a major open problem to design a deterministic polynomial time blackbox algorithm that tests if C is identically zero. Klivans & Spielman (STOC 2001) observed that the problem is open even when k is a constant. This case has been subjected to a serious study over the past few years, starting from the work of Dvir & Shpilka (STOC 2005). We give the first polynomial time blackbox algorithm for this problem. Our algorithm runsmore » in time poly(n)d{sup k}, regardless of the base field. The only field for which polynomial time algorithms were previously known is F = Q (Kayal & Saraf, FOCS 2009, and Saxena & Seshadhri, FOCS 2010). This is the first blackbox algorithm for depth-3 circuits that does not use the rank based approaches of Karnin & Shpilka (CCC 2008). We prove an important tool for the study of depth-3 identities. We design a blackbox polynomial time transformation that reduces the number of variables in a {Sigma}{Pi}{Sigma}(k, d, n) circuit to k variables, but preserves the identity structure. Polynomial identity testing (PIT) is a major open problem in theoretical computer science. The input is an arithmetic circuit that computes a polynomial p(x{sub 1}, x{sub 2},..., x{sub n}) over a base field F. We wish to check if p is the zero polynomial, or in other words, is identically zero. We may be provided with an explicit circuit, or may only have blackbox access. In the latter case, we can only evaluate the polynomial p at various domain points. The main goal is to devise a deterministic blackbox polynomial time algorithm for PIT.« less

Unidirectional invisibility induced by parity-time symmetric circuit

NASA Astrophysics Data System (ADS)

Lv, Bo; Fu, Jiahui; Wu, Bian; Li, Rujiang; Zeng, Qingsheng; Yin, Xinhua; Wu, Qun; Gao, Lei; Chen, Wan; Wang, Zhefei; Liang, Zhiming; Li, Ao; Ma, Ruyu

2017-01-01

Parity-time (PT) symmetric structures present the unidirectional invisibility at the spontaneous PT-symmetry breaking point. In this paper, we propose a PT-symmetric circuit consisting of a resistor and a microwave tunnel diode (TD) which represent the attenuation and amplification, respectively. Based on the scattering matrix method, the circuit can exhibit an ideal unidirectional performance at the spontaneous PT-symmetry breaking point by tuning the transmission lines between the lumped elements. Additionally, the resistance of the reactance component can alter the bandwidth of the unidirectional invisibility flexibly. Furthermore, the electromagnetic simulation for the proposed circuit validates the unidirectional invisibility and the synchronization with the input energy well. Our work not only provides an unidirectional invisible circuit based on PT-symmetry, but also proposes a potential solution for the extremely selective filter or cloaking applications.

Phase-synchroniser based on gm-C all-pass filter chain with sliding mode control

NASA Astrophysics Data System (ADS)

Mitić, Darko B.; Jovanović, Goran S.; Stojčev, Mile K.; Antić, Dragan S.

2015-03-01

Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on.

High-Speed Integrated Circuits for Military Applications.

DTIC Science & Technology

1979-11-01

1.5 pm circuits at the present time. " Market economics do not justify these circuits in the time frame of the VHSI program." See also Ref. 9. 7 per...on microprocessors currently in production, but the huge commercial market that is thought to exist for these devices when they can at last be...Subsection I, below). The single-chip microprocessor dominates the commercial market and those military applications for which their through- put is

Design, development and evaluation of a resistor-based multiplexing circuit for a 20×20 SiPM array

NASA Astrophysics Data System (ADS)

Wang, Zhonghai; Sun, Xishan; Lou, Kai; Meier, Joseph; Zhou, Rong; Yang, Chaowen; Zhu, Xiaorong; Shao, Yiping

2016-04-01

One technical challenge in developing a large-size scintillator detector with multiple Silicon Photomultiplier (SiPM) arrays is to read out a large number of detector output channels. To achieve this, different signal multiplexing circuits have been studied and applied with different performances and cost-effective tradeoffs. Resistor-based multiplexing circuits exhibit simplicity and signal integrity, but also present the disadvantage of timing shift among different channels. In this study, a resistor-based multiplexing circuit for a large-sized SiPM array readout was developed and evaluated by simulation and experimental studies. Similarly to a multiplexing circuit used for multi-anode PMT, grounding and branching resistors were connected to each SiPM output channel. The grounding resistor was used to simultaneously reduce the signal crosstalk among different channels and to improve timing performance. Both grounding and branching resistor values were optimized to maintain a balanced performance of the event energy, timing, and positioning. A multiplexing circuit was implemented on a compact PCB and applied for a flat-panel detector which consisted of a 32×32 LYSO scintillator crystals optically coupled to 5×5 SiPM arrays for a total 20×20 output channels. Test results showed excellent crystal identification for all 1024 LYSO crystals (each with 2×2×30 mm3 size) with 22Na flood-source irradiation. The measured peak-to-valley ratio from typical crystal map profile is around 3:1 to 6.6:1, an average single crystal energy resolution of about 17.3%, and an average single crystal timing resolution of about 2 ns. Timing shift among different crystals, as reported in some other resistor-based multiplexing circuit designs, was not observed. In summary, we have designed and implemented a practical resistor-based multiplexing circuit that can be readily applied for reading out a large SiPM array with good detector performance.

Pulse transmission receiver with higher-order time derivative pulse generator

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-08-12

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission receiver includes: a front-end amplification/processing circuit; a synchronization circuit coupled to the front-end amplification/processing circuit; a clock coupled to the synchronization circuit; a trigger signal generator coupled to the clock; and at least one higher-order time derivative pulse generator coupled to the trigger signal generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Study on Power Loss Reduction Considering Load Variation with Large Penetration of Distributed Generation in Smart Grid

NASA Astrophysics Data System (ADS)

Liu, Chang; Lv, Xiangyu; Guo, Li; Cai, Lixia; Jie, Jinxing; Su, Kuo

2017-05-01

With the increasing of penetration of distributed in the smart grid, the problems that the power loss increasing and short circuit capacity beyond the rated capicity of circuit breaker will become more serious. In this paper, a methodology (Modified BPSO) is presented for network reconfiguration which is based on hybrid approach of Tabu Search and BPSO algorithms to prevent the local convergence and to decrease the calculation time using double fitnesses to consider the constraints. Moreover, an average load simulated method (ALS method) load variation considered is proposed that the average load value is used to instead of the actual load to calculation. Finally, from a case study, the results of simulation certify the approaches will decrease drastically the losses and improve the voltage profiles obviously, at the same time, the short circuit capacity is also decreased into less the shut-off capacity of circuit breaker. The power losses won’t be increased too much even if the short circuit capacity constraint is considered; voltage profiles are better with the constraint of short circuit capacity considering. The ALS method is simple and calculated time is speed.

Sequential Polarity-Reversing Circuit

NASA Technical Reports Server (NTRS)

Labaw, Clayton C.

1994-01-01

Proposed circuit reverses polarity of electric power supplied to bidirectional dc motor, reversible electro-mechanical actuator, or other device operating in direction depending on polarity. Circuit reverses polarity each time power turned on, without need for additional polarity-reversing or direction signals and circuitry to process them.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chertkov, Michael; Turitsyn, Konstantin; Sulc, Petr

The anticipated increase in the number of plug-in electric vehicles (EV) will put additional strain on electrical distribution circuits. Many control schemes have been proposed to control EV charging. Here, we develop control algorithms based on randomized EV charging start times and simple one-way broadcast communication allowing for a time delay between communication events. Using arguments from queuing theory and statistical analysis, we seek to maximize the utilization of excess distribution circuit capacity while keeping the probability of a circuit overload negligible.

Configuration of dishwasher to improve energy efficiency of water heating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gluesenkamp, Kyle R.

A washing machine includes a sealed tub for accepting articles to be washed. A liquid circulation circuit sprays a pressurized liquid (e.g. water, detergent, solvent) around the articles to clean them. The liquid circulation circuit is in thermal contact with a hot side of a thermoelectric device. A heat sink is in thermal contact with both a cold side of the thermoelectric device and a heat sink charging circuit. A liquid is successively directed one or more times through the liquid circulation circuit with the thermoelectric device powered on, and then directed one or more times through the heat sinkmore » charging circuit with the thermoelectric device powered off. Finally, the liquid is discharged from the tub after having its temperature lowered by heat exchange to the heat sink.« less

Automatic recloser circuit breaker integrated with GSM technology for power system notification

NASA Astrophysics Data System (ADS)

Lada, M. Y.; Khiar, M. S. A.; Ghani, S. A.; Nawawi, M. R. M.; Rahim, N. H.; Sinar, L. O. M.

2015-05-01

Lightning is one type of transient faults that usually cause the circuit breaker in the distribution board trip due to overload current detection. The instant tripping condition in the circuit breakers clears the fault in the system. Unfortunately most circuit breakers system is manually operated. The power line will be effectively re-energized after the clearing fault process is finished. Auto-reclose circuit is used on the transmission line to carry out the duty of supplying quality electrical power to customers. In this project, an automatic reclose circuit breaker for low voltage usage is designed. The product description is the Auto Reclose Circuit Breaker (ARCB) will trip if the current sensor detects high current which exceeds the rated current for the miniature circuit breaker (MCB) used. Then the fault condition will be cleared automatically and return the power line to normal condition. The Global System for Mobile Communication (GSM) system will send SMS to the person in charge if the tripping occurs. If the over current occurs in three times, the system will fully trip (open circuit) and at the same time will send an SMS to the person in charge. In this project a 1 A is set as the rated current and any current exceeding a 1 A will cause the system to trip or interrupted. This system also provides an additional notification for user such as the emergency light and warning system.

Temporal integration and 1/f power scaling in a circuit model of cerebellar interneurons.

PubMed

Maex, Reinoud; Gutkin, Boris

2017-07-01

Inhibitory interneurons interconnected via electrical and chemical (GABA A receptor) synapses form extensive circuits in several brain regions. They are thought to be involved in timing and synchronization through fast feedforward control of principal neurons. Theoretical studies have shown, however, that whereas self-inhibition does indeed reduce response duration, lateral inhibition, in contrast, may generate slow response components through a process of gradual disinhibition. Here we simulated a circuit of interneurons (stellate and basket cells) of the molecular layer of the cerebellar cortex and observed circuit time constants that could rise, depending on parameter values, to >1 s. The integration time scaled both with the strength of inhibition, vanishing completely when inhibition was blocked, and with the average connection distance, which determined the balance between lateral and self-inhibition. Electrical synapses could further enhance the integration time by limiting heterogeneity among the interneurons and by introducing a slow capacitive current. The model can explain several observations, such as the slow time course of OFF-beam inhibition, the phase lag of interneurons during vestibular rotation, or the phase lead of Purkinje cells. Interestingly, the interneuron spike trains displayed power that scaled approximately as 1/ f at low frequencies. In conclusion, stellate and basket cells in cerebellar cortex, and interneuron circuits in general, may not only provide fast inhibition to principal cells but also act as temporal integrators that build a very short-term memory. NEW & NOTEWORTHY The most common function attributed to inhibitory interneurons is feedforward control of principal neurons. In many brain regions, however, the interneurons are densely interconnected via both chemical and electrical synapses but the function of this coupling is largely unknown. Based on large-scale simulations of an interneuron circuit of cerebellar cortex, we propose that this coupling enhances the integration time constant, and hence the memory trace, of the circuit. Copyright © 2017 the American Physiological Society.

Circuit Motifs for Contrast-Adaptive Differentiation in Early Sensory Systems: The Role of Presynaptic Inhibition and Short-Term Plasticity

PubMed Central

Zhang, Danke; Wu, Si; Rasch, Malte J.

2015-01-01

In natural signals, such as the luminance value across of a visual scene, abrupt changes in intensity value are often more relevant to an organism than intensity values at other positions and times. Thus to reduce redundancy, sensory systems are specialized to detect the times and amplitudes of informative abrupt changes in the input stream rather than coding the intensity values at all times. In theory, a system that responds transiently to fast changes is called a differentiator. In principle, several different neural circuit mechanisms exist that are capable of responding transiently to abrupt input changes. However, it is unclear which circuit would be best suited for early sensory systems, where the dynamic range of the natural input signals can be very wide. We here compare the properties of different simple neural circuit motifs for implementing signal differentiation. We found that a circuit motif based on presynaptic inhibition (PI) is unique in a sense that the vesicle resources in the presynaptic site can be stably maintained over a wide range of stimulus intensities, making PI a biophysically plausible mechanism to implement a differentiator with a very wide dynamical range. Moreover, by additionally considering short-term plasticity (STP), differentiation becomes contrast adaptive in the PI-circuit but not in other potential neural circuit motifs. Numerical simulations show that the behavior of the adaptive PI-circuit is consistent with experimental observations suggesting that adaptive presynaptic inhibition might be a good candidate neural mechanism to achieve differentiation in early sensory systems. PMID:25723493

Circuit motifs for contrast-adaptive differentiation in early sensory systems: the role of presynaptic inhibition and short-term plasticity.

PubMed

Zhang, Danke; Wu, Si; Rasch, Malte J

2015-01-01

In natural signals, such as the luminance value across of a visual scene, abrupt changes in intensity value are often more relevant to an organism than intensity values at other positions and times. Thus to reduce redundancy, sensory systems are specialized to detect the times and amplitudes of informative abrupt changes in the input stream rather than coding the intensity values at all times. In theory, a system that responds transiently to fast changes is called a differentiator. In principle, several different neural circuit mechanisms exist that are capable of responding transiently to abrupt input changes. However, it is unclear which circuit would be best suited for early sensory systems, where the dynamic range of the natural input signals can be very wide. We here compare the properties of different simple neural circuit motifs for implementing signal differentiation. We found that a circuit motif based on presynaptic inhibition (PI) is unique in a sense that the vesicle resources in the presynaptic site can be stably maintained over a wide range of stimulus intensities, making PI a biophysically plausible mechanism to implement a differentiator with a very wide dynamical range. Moreover, by additionally considering short-term plasticity (STP), differentiation becomes contrast adaptive in the PI-circuit but not in other potential neural circuit motifs. Numerical simulations show that the behavior of the adaptive PI-circuit is consistent with experimental observations suggesting that adaptive presynaptic inhibition might be a good candidate neural mechanism to achieve differentiation in early sensory systems.

In vitro effects of an extracorporeal membrane oxygenation circuit on the sequestration of ϵ-aminocaproic acid.

PubMed

Wagner, Deborah; Caraballo, Miguel; Waldvogel, John; Peterson, Yuki; Sun, Duxin

2017-04-01

To assess the in vitro effects of drug sequestration in extracorporeal membrane oxygenation (ECMO) on ϵ-aminocaproic acid (EACA) concentrations. This in vitro study will determine changes in EACA concentration over time in ECMO circuits. A pediatric dose of 2,500 mg was administered to whole expired blood in the simulated pediatric ECMO circuit. Blood samples were collected at 0, 30, 60, 360 and 1440-minute intervals after initial administration equilibration from three different sites of the circuit: pre-oxygenator (PRE), post-oxygenator (POST) and PVC tubing (PVC) to determine the predominant site of drug loss. The circuit was maintained for two consecutive days with a re-dose at 24 hours to establish a comparison between unsaturated (New) and saturated (Old) oxygenator membranes. Comparisons between sample sites, sample times and New versus Old membranes were statistically analyzed by a linear mixed-effects model with significance defined as a p-value <0.05. There were no significant differences in EACA concentration with respect to sample site, with PRE and POST samples demonstrating respective mean differences of 0.30 mg/ml and 0.34 mg/ml as compared to PVC, resulting in non-significant p-values of 0.373 [95% CI (-0.37, 0.98)] and 0.324 [95% CI (-0.34, 1.01)], respectively. The comparison of New vs. Old ECMO circuits resulted in non-significant changes from baseline, with a mean difference of 0.50 mg/ml, 95% CI (-0.65, 1.65), p=0.315. The findings of this study did not show any significant changes in drug concentration that can be attributed to sequestration within the ECMO circuit. Mean concentrations between ECMO circuit sample sites did not differ significantly. Comparison between New and Old circuits also did not differ significantly in the change from baseline concentration over time. Sequestration within ECMO circuits appears not to be a considerable factor for EACA administration.

Electrical circuit modeling and analysis of microwave acoustic interaction with biological tissues.

PubMed

Gao, Fei; Zheng, Qian; Zheng, Yuanjin

2014-05-01

Numerical study of microwave imaging and microwave-induced thermoacoustic imaging utilizes finite difference time domain (FDTD) analysis for simulation of microwave and acoustic interaction with biological tissues, which is time consuming due to complex grid-segmentation and numerous calculations, not straightforward due to no analytical solution and physical explanation, and incompatible with hardware development requiring circuit simulator such as SPICE. In this paper, instead of conventional FDTD numerical simulation, an equivalent electrical circuit model is proposed to model the microwave acoustic interaction with biological tissues for fast simulation and quantitative analysis in both one and two dimensions (2D). The equivalent circuit of ideal point-like tissue for microwave-acoustic interaction is proposed including transmission line, voltage-controlled current source, envelop detector, and resistor-inductor-capacitor (RLC) network, to model the microwave scattering, thermal expansion, and acoustic generation. Based on which, two-port network of the point-like tissue is built and characterized using pseudo S-parameters and transducer gain. Two dimensional circuit network including acoustic scatterer and acoustic channel is also constructed to model the 2D spatial information and acoustic scattering effect in heterogeneous medium. Both FDTD simulation, circuit simulation, and experimental measurement are performed to compare the results in terms of time domain, frequency domain, and pseudo S-parameters characterization. 2D circuit network simulation is also performed under different scenarios including different sizes of tumors and the effect of acoustic scatterer. The proposed circuit model of microwave acoustic interaction with biological tissue could give good agreement with FDTD simulated and experimental measured results. The pseudo S-parameters and characteristic gain could globally evaluate the performance of tumor detection. The 2D circuit network enables the potential to combine the quasi-numerical simulation and circuit simulation in a uniform simulator for codesign and simulation of a microwave acoustic imaging system, bridging bioeffect study and hardware development seamlessly.

Electronic circuit detects left ventricular ejection events in cardiovascular system

NASA Technical Reports Server (NTRS)

Gebben, V. D.; Webb, J. A., Jr.

1972-01-01

Electronic circuit processes arterial blood pressure waveform to produce discrete signals that coincide with beginning and end of left ventricular ejection. Output signals provide timing signals for computers that monitor cardiovascular systems. Circuit operates reliably for heart rates between 50 and 200 beats per minute.

CIRCUS--A digital computer program for transient analysis of electronic circuits

NASA Technical Reports Server (NTRS)

Moore, W. T.; Steinbert, L. L.

1968-01-01

Computer program simulates the time domain response of an electronic circuit to an arbitrary forcing function. CIRCUS uses a charge-control parameter model to represent each semiconductor device. Given the primary photocurrent, the transient behavior of a circuit in a radiation environment is determined.

Unfractionated heparin activity measured by anti-factor Xa levels is associated with the need for extracorporeal membrane oxygenation circuit/membrane oxygenator change: a retrospective pediatric study.

PubMed

Irby, Katherine; Swearingen, Christopher; Byrnes, Jonathan; Bryant, Joshua; Prodhan, Parthak; Fiser, Richard

2014-05-01

Investigate whether anti-Factor Xa levels are associated with the need for change of circuit/membrane oxygenator secondary to thrombus formation in pediatric patients. Retrospective single institution study. Retrospective record review of 62 pediatric patients supported with extracorporeal membrane oxygenation from 2009 to 2011. Data on standard demographic characteristics, indications for extracorporeal membrane oxygenation, duration of extracorporeal membrane oxygenation, activated clotting time measurements, anti-Factor Xa measurements, and heparin infusion rate were collected. Generalized linear models were used to associate anti-Factor Xa concentrations and need for change of either entire circuit/membrane oxygenator secondary to thrombus formation. Sixty-two patients met study inclusion criteria. No-circuit change was required in 45 of 62 patients. Of 62 patients, 17 required change of circuit/membrane oxygenator due to thrombus formation. Multivariate analysis of daily anti-Factor Xa measurements throughout duration of extracorporeal membrane oxygenation support estimated a mean anti-Factor Xa concentration of 0.20 IU/mL (95% CI, 0.16, 0.24) in no-complete-circuit group that was significantly higher than the estimated concentration of 0.13 IU/mL (95% CI, 0.12, 0.14) in complete-circuit group (p = 0.001). A 0.01 IU/mL decrease in anti-Factor Xa increased odds of need for circuit/membrane oxygenator change by 5% (odds ratio = 1.105; 95% CI, 1.00, 1.10; p = 0.044). Based on the observed anti-Factor Xa concentrations, complete-circuit group had 41% increased odds for requiring circuit/membrane oxygenator change compared with no-complete-circuit group (odds ratio = 1.41; 95% CI, 1.01, 1.96; p = 0.044). Mean daily activated clotting time measurement (p = 0.192) was not different between groups, but mean daily heparin infusion rate (p < 0.001) was significantly different between the two groups. Higher anti-Factor Xa concentrations were associated with freedom from circuit/membrane oxygenator change due to thrombus formation in pediatric patients during extracorporeal membrane oxygenation support. Activated clotting time measurements did not differ significantly between groups with or without circuit/membrane oxygenator change. This is the first study to link anti-Factor Xa concentrations with a clinically relevant measure of thrombosis in pediatric patients during extracorporeal membrane oxygenation support. Further prospective study is warranted.

Reduction of characteristic RL time for fast, efficient magnetic levitation

NASA Astrophysics Data System (ADS)

Li, Yuqing; Feng, Guosheng; Wang, Xiaofeng; Wu, Jizhou; Ma, Jie; Xiao, Liantuan; Jia, Suotang

2017-09-01

We demonstrate the reduction of characteristic time in resistor-inductor (RL) circuit for fast, efficient magnetic levitation according to Kirchhoff's circuit laws. The loading time is reduced by a factor of ˜4 when a high-power resistor is added in series with the coils. By using the controllable output voltage of power supply and voltage of feedback circuit, the loading time is further reduced by ˜ 3 times. The overshoot loading in advance of the scheduled magnetic field gradient is equivalent to continuously adding a resistor without heating. The magnetic field gradient with the reduced loading time is used to form the upward magnetic force against to the gravity of the cooled Cs atoms, and we obtain an effectively levitated loading of the Cs atoms to a crossed optical dipole trap.

Four-junction superconducting circuit

PubMed Central

Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

2016-01-01

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

A design of driving circuit for star sensor imaging camera

NASA Astrophysics Data System (ADS)

Li, Da-wei; Yang, Xiao-xu; Han, Jun-feng; Liu, Zhao-hui

2016-01-01

The star sensor is a high-precision attitude sensitive measuring instruments, which determine spacecraft attitude by detecting different positions on the celestial sphere. Imaging camera is an important portion of star sensor. The purpose of this study is to design a driving circuit based on Kodak CCD sensor. The design of driving circuit based on Kodak KAI-04022 is discussed, and the timing of this CCD sensor is analyzed. By the driving circuit testing laboratory and imaging experiments, it is found that the driving circuits can meet the requirements of Kodak CCD sensor.

A fast-locking PLL with all-digital locked-aid circuit

NASA Astrophysics Data System (ADS)

Kao, Shao-Ku; Hsieh, Fu-Jen

2013-02-01

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35 µm CMOS process with a 3.3 V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.

Optimizing the switching time for 400 kV SF6 circuit breakers

NASA Astrophysics Data System (ADS)

Ciulica, D.

2018-01-01

This paper presents real-time voltage and current analysis for optimizing the wave switching point of the circuit breaker SF6. Circuit Breaker plays an important role in power systems. It provides protection for equipment in embedded stations in transport networks. SF6 Circuit Breaker is very important equipment in Power Systems, which is used for up to 400 kV due to its excellent performance. The controlled switching is used to eliminate transient modes and electrodynamic and dielectric charges in the network at manual switching of capacitor, shunt reactors and power transformers. These effects reduce the reliability and lifetime of the equipment installed on the network, or may lead to erroneous protection.

Drive and protection circuit for converter module of cascaded H-bridge STATCOM

NASA Astrophysics Data System (ADS)

Wang, Xuan; Yuan, Hongliang; Wang, Xiaoxing; Wang, Shuai; Fu, Yongsheng

2018-04-01

Drive and protection circuit is an important part of power electronics, which is related to safe and stable operation issues in the power electronics. The drive and protection circuit is designed for the cascaded H-bridge STATCOM. This circuit can realize flexible dead-time setting, operation status self-detection, fault priority protection and detailed fault status uploading. It can help to improve the reliability of STATCOM's operation. Finally, the proposed circuit is tested and analyzed by power electronic simulation software PSPICE (Simulation Program with IC Emphasis) and a series of experiments. Further studies showed that the proposed circuit can realize drive and control of H-bridge circuit, meanwhile it also can realize fast processing faults and have advantage of high reliability.

Simple tunnel diode circuit for accurate zero crossing timing

NASA Technical Reports Server (NTRS)

Metz, A. J.

1969-01-01

Tunnel diode circuit, capable of timing the zero crossing point of bipolar pulses, provides effective design for a fast crossing detector. It combines a nonlinear load line with the diode to detect the zero crossing of a wide range of input waveshapes.

Trigger Circuit.

DTIC Science & Technology

A wire of Nitinol can be stretched up to a given amount and will remain in this stretched state until heated to a critical temperature. When heated...circuit of this invention provides a current pulse for the required time period to heat the Nitinol wire to its critical temperature to thereby restore the...wire to its original length. The circuit includes a high power transistor which is gated on for a controlled time to provide the required power to heat the Nitinol wire to its critical temperature. (Author)

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

Neutron camera employing row and column summations

DOEpatents

Clonts, Lloyd G.; Diawara, Yacouba; Donahue, Jr, Cornelius; Montcalm, Christopher A.; Riedel, Richard A.; Visscher, Theodore

2016-06-14

For each photomultiplier tube in an Anger camera, an R.times.S array of preamplifiers is provided to detect electrons generated within the photomultiplier tube. The outputs of the preamplifiers are digitized to measure the magnitude of the signals from each preamplifier. For each photomultiplier tube, a corresponding summation circuitry including R row summation circuits and S column summation circuits numerically add the magnitudes of the signals from preamplifiers for each row and for each column to generate histograms. For a P.times.Q array of photomultiplier tubes, P.times.Q summation circuitries generate P.times.Q row histograms including R entries and P.times.Q column histograms including S entries. The total set of histograms include P.times.Q.times.(R+S) entries, which can be analyzed by a position calculation circuit to determine the locations of events (detection of a neutron).

46 CFR 111.52-3 - Systems below 1500 kilowatts.

Code of Federal Regulations, 2010 CFR

2010-10-01

...-GENERAL REQUIREMENTS Calculation of Short-Circuit Currents § 111.52-3 Systems below 1500 kilowatts. The following short-circuit assumptions must be made for a system with an aggregate generating capacity below... maximum short-circuit current of a direct current system must be assumed to be 10 times the aggregate...

Module Eleven: Capacitance; Basic Electricity and Electronics Individualized Learning System.

ERIC Educational Resources Information Center

Bureau of Naval Personnel, Washington, DC.

In this module the student will learn about another circuit quantity, capacitance, and discover the effects of this component on circuit current, voltage, and power. The module is divided into seven lessons: the capacitor, theory of capacitance, total capacitance, RC (resistive-capacitive circuit) time constant, capacitive reactance, phase and…

A Novel Approach to Chemical Communications

DTIC Science & Technology

2010-06-17

of droplets in the microfludic circuit. Figure 4. Generation of droplets in the microfludic circuit. Figure 5. Space-time plots showing anti-phase... microfludic circuit. Final Report W911NF-07-1-0639 Page 11 Table 2. A sampling of microfluidics experiments Fluid1 for drop genera- tion Fluid2

Pulse shaping circuit for active counting of superheated emulsion

NASA Astrophysics Data System (ADS)

Murai, Ikuo; Sawamura, Teruko

2005-08-01

A pulse shaping circuit for active counting of superheated emulsions is described. A piezoelectric transducer is used for sensing bubble formation acoustically and the acoustic signal is transformed to a shaping pulse for counting. The circuit has a short signal processing time in the order of 10 ms.

Low-power integrated-circuit driver for ferrite-memory word lines

NASA Technical Reports Server (NTRS)

Katz, S.

1970-01-01

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Fault-tolerant, high-level quantum circuits: form, compilation and description

NASA Astrophysics Data System (ADS)

Paler, Alexandru; Polian, Ilia; Nemoto, Kae; Devitt, Simon J.

2017-06-01

Fault-tolerant quantum error correction is a necessity for any quantum architecture destined to tackle interesting, large-scale problems. Its theoretical formalism has been well founded for nearly two decades. However, we still do not have an appropriate compiler to produce a fault-tolerant, error-corrected description from a higher-level quantum circuit for state-of the-art hardware models. There are many technical hurdles, including dynamic circuit constructions that occur when constructing fault-tolerant circuits with commonly used error correcting codes. We introduce a package that converts high-level quantum circuits consisting of commonly used gates into a form employing all decompositions and ancillary protocols needed for fault-tolerant error correction. We call this form the (I)initialisation, (C)NOT, (M)measurement form (ICM) and consists of an initialisation layer of qubits into one of four distinct states, a massive, deterministic array of CNOT operations and a series of time-ordered X- or Z-basis measurements. The form allows a more flexible approach towards circuit optimisation. At the same time, the package outputs a standard circuit or a canonical geometric description which is a necessity for operating current state-of-the-art hardware architectures using topological quantum codes.

Design and Analysis of Compact DNA Strand Displacement Circuits for Analog Computation Using Autocatalytic Amplifiers.

PubMed

Song, Tianqi; Garg, Sudhanshu; Mokhtar, Reem; Bui, Hieu; Reif, John

2018-01-19

A main goal in DNA computing is to build DNA circuits to compute designated functions using a minimal number of DNA strands. Here, we propose a novel architecture to build compact DNA strand displacement circuits to compute a broad scope of functions in an analog fashion. A circuit by this architecture is composed of three autocatalytic amplifiers, and the amplifiers interact to perform computation. We show DNA circuits to compute functions sqrt(x), ln(x) and exp(x) for x in tunable ranges with simulation results. A key innovation in our architecture, inspired by Napier's use of logarithm transforms to compute square roots on a slide rule, is to make use of autocatalytic amplifiers to do logarithmic and exponential transforms in concentration and time. In particular, we convert from the input that is encoded by the initial concentration of the input DNA strand, to time, and then back again to the output encoded by the concentration of the output DNA strand at equilibrium. This combined use of strand-concentration and time encoding of computational values may have impact on other forms of molecular computation.

Computer Simulation of Microwave Devices

NASA Technical Reports Server (NTRS)

Kory, Carol L.

1997-01-01

The accurate simulation of cold-test results including dispersion, on-axis beam interaction impedance, and attenuation of a helix traveling-wave tube (TWT) slow-wave circuit using the three-dimensional code MAFIA (Maxwell's Equations Solved by the Finite Integration Algorithm) was demonstrated for the first time. Obtaining these results is a critical step in the design of TWT's. A well-established procedure to acquire these parameters is to actually build and test a model or a scale model of the circuit. However, this procedure is time-consuming and expensive, and it limits freedom to examine new variations to the basic circuit. These limitations make the need for computational methods crucial since they can lower costs, reduce tube development time, and lessen limitations on novel designs. Computer simulation has been used to accurately obtain cold-test parameters for several slow-wave circuits. Although the helix slow-wave circuit remains the mainstay of the TWT industry because of its exceptionally wide bandwidth, until recently it has been impossible to accurately analyze a helical TWT using its exact dimensions because of the complexity of its geometrical structure. A new computer modeling technique developed at the NASA Lewis Research Center overcomes these difficulties. The MAFIA three-dimensional mesh for a C-band helix slow-wave circuit is shown.

Single chip camera device having double sampling operation

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

2002-01-01

A single chip camera device is formed on a single substrate including an image acquisition portion for control portion and the timing circuit formed on the substrate. The timing circuit also controls the photoreceptors in a double sampling mode in which are reset level is first read and then after an integration time a charged level is read.

Full Wave Analysis of Passive Microwave Monolithic Integrated Circuit Devices Using a Generalized Finite Difference Time Domain (GFDTD) Algorithm

NASA Technical Reports Server (NTRS)

Lansing, Faiza S.; Rascoe, Daniel L.

1993-01-01

This paper presents a modified Finite-Difference Time-Domain (FDTD) technique using a generalized conformed orthogonal grid. The use of the Conformed Orthogonal Grid, Finite Difference Time Domain (GFDTD) enables the designer to match all the circuit dimensions, hence eliminating a major source o error in the analysis.

Fundamentals of Digital Engineering: Designing for Reliability

NASA Technical Reports Server (NTRS)

Katz, R.; Day, John H. (Technical Monitor)

2001-01-01

The concept of designing for reliability will be introduced along with a brief overview of reliability, redundancy and traditional methods of fault tolerance is presented, as applied to current logic devices. The fundamentals of advanced circuit design and analysis techniques will be the primary focus. The introduction will cover the definitions of key device parameters and how analysis is used to prove circuit correctness. Basic design techniques such as synchronous vs asynchronous design, metastable state resolution time/arbiter design, and finite state machine structure/implementation will be reviewed. Advanced topics will be explored such as skew-tolerant circuit design, the use of triple-modular redundancy and circuit hazards, device transients and preventative circuit design, lock-up states in finite state machines generated by logic synthesizers, device transient characteristics, radiation mitigation techniques. worst-case analysis, the use of timing analyzer and simulators, and others. Case studies and lessons learned from spaceflight designs will be given as examples

A Generalized Fast Frequency Sweep Algorithm for Coupled Circuit-EM Simulations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rockway, J D; Champagne, N J; Sharpe, R M

2004-01-14

Frequency domain techniques are popular for analyzing electromagnetics (EM) and coupled circuit-EM problems. These techniques, such as the method of moments (MoM) and the finite element method (FEM), are used to determine the response of the EM portion of the problem at a single frequency. Since only one frequency is solved at a time, it may take a long time to calculate the parameters for wideband devices. In this paper, a fast frequency sweep based on the Asymptotic Wave Expansion (AWE) method is developed and applied to generalized mixed circuit-EM problems. The AWE method, which was originally developed for lumped-loadmore » circuit simulations, has recently been shown to be effective at quasi-static and low frequency full-wave simulations. Here it is applied to a full-wave MoM solver, capable of solving for metals, dielectrics, and coupled circuit-EM problems.« less

Circuit for echo and noise suppression of accoustic signals transmitted through a drill string

DOEpatents

Drumheller, Douglas S.; Scott, Douglas D.

1993-01-01

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output.

Tunable Low Energy, Compact and High Performance Neuromorphic Circuit for Spike-Based Synaptic Plasticity

PubMed Central

Rahimi Azghadi, Mostafa; Iannella, Nicolangelo; Al-Sarawi, Said; Abbott, Derek

2014-01-01

Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities. PMID:24551089

Tunable low energy, compact and high performance neuromorphic circuit for spike-based synaptic plasticity.

PubMed

Rahimi Azghadi, Mostafa; Iannella, Nicolangelo; Al-Sarawi, Said; Abbott, Derek

2014-01-01

Cortical circuits in the brain have long been recognised for their information processing capabilities and have been studied both experimentally and theoretically via spiking neural networks. Neuromorphic engineers are primarily concerned with translating the computational capabilities of biological cortical circuits, using the Spiking Neural Network (SNN) paradigm, into in silico applications that can mimic the behaviour and capabilities of real biological circuits/systems. These capabilities include low power consumption, compactness, and relevant dynamics. In this paper, we propose a new accelerated-time circuit that has several advantages over its previous neuromorphic counterparts in terms of compactness, power consumption, and capability to mimic the outcomes of biological experiments. The presented circuit simulation results demonstrate that, in comparing the new circuit to previous published synaptic plasticity circuits, reduced silicon area and lower energy consumption for processing each spike is achieved. In addition, it can be tuned in order to closely mimic the outcomes of various spike timing- and rate-based synaptic plasticity experiments. The proposed circuit is also investigated and compared to other designs in terms of tolerance to mismatch and process variation. Monte Carlo simulation results show that the proposed design is much more stable than its previous counterparts in terms of vulnerability to transistor mismatch, which is a significant challenge in analog neuromorphic design. All these features make the proposed design an ideal circuit for use in large scale SNNs, which aim at implementing neuromorphic systems with an inherent capability that can adapt to a continuously changing environment, thus leading to systems with significant learning and computational abilities.

Optimization of the Switch Mechanism in a Circuit Breaker Using MBD Based Simulation

PubMed Central

Jang, Jin-Seok; Yoon, Chang-Gyu; Ryu, Chi-Young; Kim, Hyun-Woo; Bae, Byung-Tae; Yoo, Wan-Suk

2015-01-01

A circuit breaker is widely used to protect electric power system from fault currents or system errors; in particular, the opening mechanism in a circuit breaker is important to protect current overflow in the electric system. In this paper, multibody dynamic model of a circuit breaker including switch mechanism was developed including the electromagnetic actuator system. Since the opening mechanism operates sequentially, optimization of the switch mechanism was carried out to improve the current breaking time. In the optimization process, design parameters were selected from length and shape of each latch, which changes pivot points of bearings to shorten the breaking time. To validate optimization results, computational results were compared to physical tests with a high speed camera. Opening time of the optimized mechanism was decreased by 2.3 ms, which was proved by experiments. Switch mechanism design process can be improved including contact-latch system by using this process. PMID:25918740

Delay grid multiplexing: simple time-based multiplexing and readout method for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Won, Jun Yeon; Ko, Guen Bae; Lee, Jae Sung

2016-10-01

In this paper, we propose a fully time-based multiplexing and readout method that uses the principle of the global positioning system. Time-based multiplexing allows simplifying the multiplexing circuits where the only innate traces that connect the signal pins of the silicon photomultiplier (SiPM) channels to the readout channels are used as the multiplexing circuit. Every SiPM channel is connected to the delay grid that consists of the traces on a printed circuit board, and the inherent transit times from each SiPM channel to the readout channels encode the position information uniquely. Thus, the position of each SiPM can be identified using the time difference of arrival (TDOA) measurements. The proposed multiplexing can also allow simplification of the readout circuit using the time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA), where the time-over-threshold (ToT) is used to extract the energy information after multiplexing. In order to verify the proposed multiplexing method, we built a positron emission tomography (PET) detector that consisted of an array of 4  ×  4 LGSO crystals, each with a dimension of 3  ×  3  ×  20 mm3, and one- to-one coupled SiPM channels. We first employed the waveform sampler as an initial study, and then replaced the waveform sampler with an FPGA-TDC to further simplify the readout circuits. The 16 crystals were clearly resolved using only the time information obtained from the four readout channels. The coincidence resolving times (CRTs) were 382 and 406 ps FWHM when using the waveform sampler and the FPGA-TDC, respectively. The proposed simple multiplexing and readout methods can be useful for time-of-flight (TOF) PET scanners.

Measurement of luminescence decays: High performance at low cost

NASA Astrophysics Data System (ADS)

Sulkes, Mark; Sulkes, Zoe

2011-11-01

The availability of inexpensive ultra bright LEDs spanning the visible and near-ultraviolet combined with the availability of inexpensive electronics equipment makes it possible to construct a high performance luminescence lifetime apparatus (˜5 ns instrumental response or better) at low cost. A central need for time domain measurement systems is the ability to obtain short (˜1 ns or less) excitation light pulses from the LEDs. It is possible to build the necessary LED driver using a simple avalanche transistor circuit. We describe first a circuit to test for small signal NPN transistors that can avalanche. We then describe a final optimized avalanche mode circuit that we developed on a prototyping board by measuring driven light pulse duration as a function of the circuit on the board and passive component values. We demonstrate that the combination of the LED pulser and a 1P28 photomultiplier tube used in decay waveform acquisition has a time response that allows for detection and lifetime determination of luminescence decays down to ˜5 ns. The time response and data quality afforded with the same components in time-correlated single photon counting are even better. For time-correlated single photon counting an even simpler NAND-gate based LED driver circuit is also applicable. We also demonstrate the possible utility of a simple frequency domain method for luminescence lifetime determinations.

Ultrastable automatic frequency control

NASA Technical Reports Server (NTRS)

Sabourin, D. J.; Furiga, A.

1981-01-01

Center frequency of wideband AFC circuit drifts only hundredths of percent per day. Since circuit responds only to slow frequency drifts and modulation signal has high-pass characteristics, AFC does not interfere with normal FM operation. Stable oscillator, reset circuit, and pulse generator constitute time-averaging discriminator; digital counter in pulse generator replaces usual monostable multivibrator.

42 CFR 84.94 - Gas flow test; closed-circuit apparatus.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 42 Public Health 1 2011-10-01 2011-10-01 false Gas flow test; closed-circuit apparatus. 84.94...-Contained Breathing Apparatus § 84.94 Gas flow test; closed-circuit apparatus. (a) Where oxygen is supplied... rated service time of the apparatus. (b) Where constant flow is used in conjunction with demand flow...

42 CFR 84.94 - Gas flow test; closed-circuit apparatus.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 42 Public Health 1 2010-10-01 2010-10-01 false Gas flow test; closed-circuit apparatus. 84.94...-Contained Breathing Apparatus § 84.94 Gas flow test; closed-circuit apparatus. (a) Where oxygen is supplied... rated service time of the apparatus. (b) Where constant flow is used in conjunction with demand flow...

Integrated coherent matter wave circuits

DOE PAGES

Ryu, C.; Boshier, M. G.

2015-09-21

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

NASA Astrophysics Data System (ADS)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

Temperature gradient measurements by using thermoelectric effect in CNTs-silicone adhesive composite.

PubMed

Chani, Muhammad Tariq Saeed; Karimov, Kh S; Asiri, Abdullah M; Ahmed, Nisar; Bashir, Muhammad Mehran; Khan, Sher Bahadar; Rub, Malik Abdul; Azum, Naved

2014-01-01

This work presents the fabrication and investigation of thermoelectric cells based on composite of carbon nanotubes (CNT) and silicone adhesive. The composite contains CNT and silicon adhesive 1∶1 by weight. The current-voltage characteristics and dependences of voltage, current and Seebeck coefficient on the temperature gradient of cell were studied. It was observed that with increase in temperature gradient the open circuit voltage, short circuit current and the Seebeck coefficient of the cells increase. Approximately 7 times increase in temperature gradient increases the open circuit voltage and short circuit current up to 40 and 5 times, respectively. The simulation of experimental results is also carried out; the simulated results are well matched with experimental results.

Temperature Gradient Measurements by Using Thermoelectric Effect in CNTs-Silicone Adhesive Composite

PubMed Central

Chani, Muhammad Tariq Saeed; Karimov, Kh. S.; Asiri, Abdullah M.; Ahmed, Nisar; Bashir, Muhammad Mehran; Khan, Sher Bahadar; Rub, Malik Abdul; Azum, Naved

2014-01-01

This work presents the fabrication and investigation of thermoelectric cells based on composite of carbon nanotubes (CNT) and silicone adhesive. The composite contains CNT and silicon adhesive 1∶1 by weight. The current-voltage characteristics and dependences of voltage, current and Seebeck coefficient on the temperature gradient of cell were studied. It was observed that with increase in temperature gradient the open circuit voltage, short circuit current and the Seebeck coefficient of the cells increase. Approximately 7 times increase in temperature gradient increases the open circuit voltage and short circuit current up to 40 and 5 times, respectively. The simulation of experimental results is also carried out; the simulated results are well matched with experimental results. PMID:24748375

High speed, long distance, data transmission multiplexing circuit

DOEpatents

Mariotti, Razvan

1991-01-01

A high speed serial data transmission multiplexing circuit, which is operable to accurately transmit data over long distances (up to 3 Km), and to multiplex, select and continuously display real time analog signals in a bandwidth from DC to 100 Khz. The circuit is made fault tolerant by use of a programmable flywheel algorithm, which enables the circuit to tolerate one transmission error before losing synchronization of the transmitted frames of data. A method of encoding and framing captured and transmitted data is used which has a low overhead and prevents some particular transmitted data patterns from locking an included detector/decoder circuit.

ELECTRICAL CIRCUITS USING COLD-CATHODE TRIODE VALVES

DOEpatents

Goulding, F.S.

1957-11-26

An electrical circuit which may be utilized as a pulse generator or voltage stabilizer is presented. The circuit employs a cold-cathode triode valve arranged to oscillate between its on and off stages by the use of selected resistance-capacitance time constant components in the plate and trigger grid circuits. The magnitude of the d-c voltage applied to the trigger grid circuit effectively controls the repetition rate of the output pulses. In the voltage stabilizer arrangement the d-c control voltage is a portion of the supply voltage and the rectified output voltage is substantially constant.

Submicrosecond Power-Switching Test Circuit

NASA Technical Reports Server (NTRS)

Folk, Eric N.

2006-01-01

A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a repetitive waveform from a signal generator, momentary closure of a push-button switch, or closure or opening of a manually operated on/off switch. In the case of a signal generator, one can adjust the frequency and duty cycle as needed to obtain the desired AC power-supply response, which one could display on an oscilloscope. Momentary switch closure could be useful for obtaining (and, if desired, displaying on an oscilloscope set to trigger on an event) the response of a power supply to a single load transient. The on/off switch can be used to switch between load states in which static-load regulation measurements are performed.

Circuit for echo and noise suppression of acoustic signals transmitted through a drill string

DOEpatents

Drumheller, D.S.; Scott, D.D.

1993-12-28

An electronic circuit for digitally processing analog electrical signals produced by at least one acoustic transducer is presented. In a preferred embodiment of the present invention, a novel digital time delay circuit is utilized which employs an array of First-in-First-out (FiFo) microchips. Also, a bandpass filter is used at the input to this circuit for isolating drill string noise and eliminating high frequency output. 20 figures.

VARIABLE TIME-INTERVAL GENERATOR

DOEpatents

Gross, J.E.

1959-10-31

This patent relates to a pulse generator and more particularly to a time interval generator wherein the time interval between pulses is precisely determined. The variable time generator comprises two oscillators with one having a variable frequency output and the other a fixed frequency output. A frequency divider is connected to the variable oscillator for dividing its frequency by a selected factor and a counter is used for counting the periods of the fixed oscillator occurring during a cycle of the divided frequency of the variable oscillator. This defines the period of the variable oscillator in terms of that of the fixed oscillator. A circuit is provided for selecting as a time interval a predetermined number of periods of the variable oscillator. The output of the generator consists of a first pulse produced by a trigger circuit at the start of the time interval and a second pulse marking the end of the time interval produced by the same trigger circuit.

Pneumatic oscillator circuits for timing and control of integrated microfluidics.

PubMed

Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

2013-11-05

Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

Digital time delay

DOEpatents

Martin, A.D.

1986-05-09

Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay provides a first output signal at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits latch the high resolution data to form a first synchronizing data set. A selected time interval has been preset to internal counters and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses count down the counters to generate an internal pulse delayed by an internal which is functionally related to the preset time interval. A second LCD corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD to generate a second set of synchronizing data which is complementary with the first set of synchronizing data for presentation to logic circuits. The logic circuits further delay the internal output signal with the internal pulses. The final delayed output signal thereafter enables the output pulse generator to produce the desired output pulse at the preset time delay interval following input of the trigger pulse.

Genetic circuit design automation.

PubMed

Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A

2016-04-01

Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization. Copyright © 2016, American Association for the Advancement of Science.

16 CFR 1610.5 - Test apparatus and materials.

Code of Federal Regulations, 2012 CFR

2012-01-01

... electronic circuits, in addition to miscellaneous custom made cams and rods, shock absorbing linkages, and... burn time to 0.1 second. An electronic or mechanical timer can be used to record the burn time, and electro-mechanical devices (i.e., servo-motors, solenoids, micro-switches, and electronic circuits, in...

16 CFR 1610.5 - Test apparatus and materials.

Code of Federal Regulations, 2014 CFR

2014-01-01

... electronic circuits, in addition to miscellaneous custom made cams and rods, shock absorbing linkages, and... burn time to 0.1 second. An electronic or mechanical timer can be used to record the burn time, and electro-mechanical devices (i.e., servo-motors, solenoids, micro-switches, and electronic circuits, in...

16 CFR § 1610.5 - Test apparatus and materials.

Code of Federal Regulations, 2013 CFR

2013-01-01

... electronic circuits, in addition to miscellaneous custom made cams and rods, shock absorbing linkages, and... burn time to 0.1 second. An electronic or mechanical timer can be used to record the burn time, and electro-mechanical devices (i.e., servo-motors, solenoids, micro-switches, and electronic circuits, in...

PC based graphic display real-time particle beam uniformity

NASA Technical Reports Server (NTRS)

Huebner, M. A.; Malone, C. J.; Smith, L. S.; Soli, G. A.

1989-01-01

A technique has been developed to support the study of the effects of cosmic rays on integrated circuits. The system is designed to determine the particle distribution across the surface of an integrated circuit accurately while the circuit is bombarded by a particle beam. The system uses photomultiplier tubes, an octal discriminator, a computer-controlled NIM quad counter, and an IBM PC. It provides real-time operator feedback for fast beam tuning and monitors momentary fluctuations in the particle beam. The hardware, software, and system performance are described.

Efficient Probabilistic Diagnostics for Electrical Power Systems

NASA Technical Reports Server (NTRS)

Mengshoel, Ole J.; Chavira, Mark; Cascio, Keith; Poll, Scott; Darwiche, Adnan; Uckun, Serdar

2008-01-01

We consider in this work the probabilistic approach to model-based diagnosis when applied to electrical power systems (EPSs). Our probabilistic approach is formally well-founded, as it based on Bayesian networks and arithmetic circuits. We investigate the diagnostic task known as fault isolation, and pay special attention to meeting two of the main challenges . model development and real-time reasoning . often associated with real-world application of model-based diagnosis technologies. To address the challenge of model development, we develop a systematic approach to representing electrical power systems as Bayesian networks, supported by an easy-to-use speci.cation language. To address the real-time reasoning challenge, we compile Bayesian networks into arithmetic circuits. Arithmetic circuit evaluation supports real-time diagnosis by being predictable and fast. In essence, we introduce a high-level EPS speci.cation language from which Bayesian networks that can diagnose multiple simultaneous failures are auto-generated, and we illustrate the feasibility of using arithmetic circuits, compiled from Bayesian networks, for real-time diagnosis on real-world EPSs of interest to NASA. The experimental system is a real-world EPS, namely the Advanced Diagnostic and Prognostic Testbed (ADAPT) located at the NASA Ames Research Center. In experiments with the ADAPT Bayesian network, which currently contains 503 discrete nodes and 579 edges, we .nd high diagnostic accuracy in scenarios where one to three faults, both in components and sensors, were inserted. The time taken to compute the most probable explanation using arithmetic circuits has a small mean of 0.2625 milliseconds and standard deviation of 0.2028 milliseconds. In experiments with data from ADAPT we also show that arithmetic circuit evaluation substantially outperforms joint tree propagation and variable elimination, two alternative algorithms for diagnosis using Bayesian network inference.

Apparatus for and method of testing an electrical ground fault circuit interrupt device

DOEpatents

Andrews, L.B.

1998-08-18

An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

Apparatus for and method of testing an electrical ground fault circuit interrupt device

DOEpatents

Andrews, Lowell B.

1998-01-01

An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

Corticostriatal circuit mechanisms of value-based action selection: Implementation of reinforcement learning algorithms and beyond.

PubMed

Morita, Kenji; Jitsev, Jenia; Morrison, Abigail

2016-09-15

Value-based action selection has been suggested to be realized in the corticostriatal local circuits through competition among neural populations. In this article, we review theoretical and experimental studies that have constructed and verified this notion, and provide new perspectives on how the local-circuit selection mechanisms implement reinforcement learning (RL) algorithms and computations beyond them. The striatal neurons are mostly inhibitory, and lateral inhibition among them has been classically proposed to realize "Winner-Take-All (WTA)" selection of the maximum-valued action (i.e., 'max' operation). Although this view has been challenged by the revealed weakness, sparseness, and asymmetry of lateral inhibition, which suggest more complex dynamics, WTA-like competition could still occur on short time scales. Unlike the striatal circuit, the cortical circuit contains recurrent excitation, which may enable retention or temporal integration of information and probabilistic "soft-max" selection. The striatal "max" circuit and the cortical "soft-max" circuit might co-implement an RL algorithm called Q-learning; the cortical circuit might also similarly serve for other algorithms such as SARSA. In these implementations, the cortical circuit presumably sustains activity representing the executed action, which negatively impacts dopamine neurons so that they can calculate reward-prediction-error. Regarding the suggested more complex dynamics of striatal, as well as cortical, circuits on long time scales, which could be viewed as a sequence of short WTA fragments, computational roles remain open: such a sequence might represent (1) sequential state-action-state transitions, constituting replay or simulation of the internal model, (2) a single state/action by the whole trajectory, or (3) probabilistic sampling of state/action. Copyright © 2016. Published by Elsevier B.V.

Soft switching circuit to improve efficiency of all solid-state Marx modulator for DBDs

NASA Astrophysics Data System (ADS)

Liqing, TONG; Kefu, LIU; Yonggang, WANG

2018-02-01

For an all solid-state Marx modulator applied in dielectric barrier discharges (DBDs), hard switching results in a very low efficiency. In this paper, a series resonant soft switching circuit, which series an inductance with DBD capacitor, is proposed to reduce the power loss. The power loss of the all circuit status with hard switching was analyzed, and the maximum power loss occurred during discharging at the rising and falling edges. The power loss of the series resonant soft switching circuit was also presented. A comparative analysis of the two circuits determined that the soft switching circuit greatly reduced power loss. The experimental results also demonstrated that the soft switching circuit improved the power transmission efficiency of an all solid-state Marx modulator for DBDs by up to 3 times.

Noise in Neuronal and Electronic Circuits: A General Modeling Framework and Non-Monte Carlo Simulation Techniques.

PubMed

Kilinc, Deniz; Demir, Alper

2017-08-01

The brain is extremely energy efficient and remarkably robust in what it does despite the considerable variability and noise caused by the stochastic mechanisms in neurons and synapses. Computational modeling is a powerful tool that can help us gain insight into this important aspect of brain mechanism. A deep understanding and computational design tools can help develop robust neuromorphic electronic circuits and hybrid neuroelectronic systems. In this paper, we present a general modeling framework for biological neuronal circuits that systematically captures the nonstationary stochastic behavior of ion channels and synaptic processes. In this framework, fine-grained, discrete-state, continuous-time Markov chain models of both ion channels and synaptic processes are treated in a unified manner. Our modeling framework features a mechanism for the automatic generation of the corresponding coarse-grained, continuous-state, continuous-time stochastic differential equation models for neuronal variability and noise. Furthermore, we repurpose non-Monte Carlo noise analysis techniques, which were previously developed for analog electronic circuits, for the stochastic characterization of neuronal circuits both in time and frequency domain. We verify that the fast non-Monte Carlo analysis methods produce results with the same accuracy as computationally expensive Monte Carlo simulations. We have implemented the proposed techniques in a prototype simulator, where both biological neuronal and analog electronic circuits can be simulated together in a coupled manner.

Starting Circuit For Erasable Programmable Logic Device

NASA Technical Reports Server (NTRS)

Cole, Steven W.

1990-01-01

Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

Fast, Low-Power, Hysteretic Level-Detector Circuit

NASA Technical Reports Server (NTRS)

Arditti, Mordechai

1993-01-01

Circuit for detection of preset levels of voltage or current intended to replace standard fast voltage comparator. Hysteretic analog/digital level detector operates at unusually low power with little sacrifice of speed. Comprises low-power analog circuit and complementary metal oxide/semiconductor (CMOS) digital circuit connected in overall closed feedback loop to decrease rise and fall times, provide hysteresis, and trip-level control. Contains multiple subloops combining linear and digital feedback. Levels of sensed signals and hysteresis level easily adjusted by selection of components to suit specific application.

Digital Systems Validation Handbook. Volume 2

DTIC Science & Technology

1989-02-01

power. 2. A grid of wires, solid sheet, or foil. 3. A wire from circuit to grounding block or case. 4. A wire from circuit to structure. 5. Shield...RETURN. (11) 1. Structure, for power, fault, and "discrete" circuits. 2. A grid of wires, solid sheet, or foil. 3. A wire from circuit load back to...TV (14) Television TWTD (13) Thin Wire Time Domain TX (5) Transmit U.K. (13,141 United Kingdom U.S. (14) United States UART (15) Universal Asynchronous

ONE SHAKE GATE FORMER

DOEpatents

Kalibjian, R.; Perez-Mendez, V.

1957-08-20

An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

Simulated Laboratory in Digital Logic.

ERIC Educational Resources Information Center

Cleaver, Thomas G.

Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

Capacitive charge generation apparatus and method for testing circuits

DOEpatents

Cole, E.I. Jr.; Peterson, K.A.; Barton, D.L.

1998-07-14

An electron beam apparatus and method for testing a circuit are disclosed. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 {micro}m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits. 7 figs.

Capacitive charge generation apparatus and method for testing circuits

DOEpatents

Cole, Jr., Edward I.; Peterson, Kenneth A.; Barton, Daniel L.

1998-01-01

An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

Design and implementation of GaAs HBT circuits with ACME

NASA Technical Reports Server (NTRS)

Hutchings, Brad L.; Carter, Tony M.

1993-01-01

GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

Refinements in the short-circuit technique and its application to active potassium transport across the cecropia midgut.

PubMed

Wood, J L; Moreton, R B

1978-12-01

1. The conventional, two-electrode method for measuring potential difference across an epithelium is subject to error due to potential gradients caused by current flow in the bathing medium. Mathematical analysis shows that the error in measuring short-circuit current is proportional to the resistivity of the bathing medium and to the separation of the two recording electrodes. It is particularly serious for the insect larval midgut, where the resistivity of the medium is high, and that of the tissue is low. 2. A system has been devised, which uses a third recording electrode to monitor directly the potential gradient in the bathing medium. By suitable electrical connexions, the gradient can be automatically compensated, leaving a residual error which depends on the thickness of the tissue, but not on the electrode separation. Because the thicknesses of most epithelia are smaller than the smallest practical electrode spacing, this error is smaller than that inherent in a two-electrode system. 3. Since voltage-gradients are automatically compensated, it is possible to obtain continuous readings of potential and current. A 'voltage-clamp' circuit is described, which allows the time-course of the short-circuit current to be studied. 4.The three-electrode system has been used to study the larval midgut of Hyalophora cecropia. The average results from five experiments were: initial potential difference (open-circuit): 98+/-11 mV (S.E.M.); short-circuit current at time 60 min: 498+/-160 microA cm=2; 'steady-state' resistance at 60 min: 150+/-26 omega cm2. The current is equivalent to a net potassium transport of 18.6 mu-equiv cm-2 h-1. 5. The electrical parameters of the midgut change rapidly with time. The potential difference decays with a half-time of about 158 min, the resistance increases with a half-time of about 16 min, and the short-circuit current decays as the sum of two exponential terms, with half-times of about 16 and 158 min respectively. In addition, potential and short-circuit current show transient responses to step changes. 6. The properties of the midgut are compared with those of other transporting epithelia, and their dependence on the degree of folding of the preparation is discussed. Their time-dependence is discussed in the context of changes in potassium content of the tissue, and the implications for measurements depending on the assumption of a steady state are outlined.

niSWAP and NTCP gates realized in a circuit QED system

NASA Astrophysics Data System (ADS)

Essammouni, K.; Chouikh, A.; Said, T.; Bennai, M.

Based on superconducting qubit coupled to a resonator driven by a strong microwave field, we propose a method to implement two quantum logic gates (niSWAP and NTCP gates) of one qubit simultaneously controlling n qubits selected from N qubits in a circuit QED (1 < n < N) by introducing qubit-qubit interaction. The interaction between the qubits and the circuit QED can be achieved by tuning the gate voltage and the external flux. The operation times of the logic gates are much smaller than the decoherence time and dephasing time. Moreover, the numerical simulation under the influence of the gates operations shows that the scheme could be achieved efficiently with presently available techniques.

Transient response to three-phase faults on a wind turbine generator. Ph.D. Thesis - Toledo Univ.

NASA Technical Reports Server (NTRS)

Gilbert, L. J.

1978-01-01

In order to obtain a measure of its responses to short circuits a large horizontal axis wind turbine generator was modeled and its performance was simulated on a digital computer. Simulation of short circuit faults on the synchronous alternator of a wind turbine generator, without resort to the classical assumptions generally made for that analysis, indicates that maximum clearing times for the system tied to an infinite bus are longer than the typical clearing times for equivalent capacity conventional machines. Also, maximum clearing times are independent of tower shadow and wind shear. Variation of circuit conditions produce the modifications in the transient response predicted by analysis.

A New Test Method of Circuit Breaker Spring Telescopic Characteristics Based Image Processing

NASA Astrophysics Data System (ADS)

Huang, Huimin; Wang, Feifeng; Lu, Yufeng; Xia, Xiaofei; Su, Yi

2018-06-01

This paper applied computer vision technology to the fatigue condition monitoring of springs, and a new telescopic characteristics test method is proposed for circuit breaker operating mechanism spring based on image processing technology. High-speed camera is utilized to capture spring movement image sequences when high voltage circuit breaker operated. Then the image-matching method is used to obtain the deformation-time curve and speed-time curve, and the spring expansion and deformation parameters are extracted from it, which will lay a foundation for subsequent spring force analysis and matching state evaluation. After performing simulation tests at the experimental site, this image analyzing method could solve the complex problems of traditional mechanical sensor installation and monitoring online, status assessment of the circuit breaker spring.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Universal power transistor base drive control unit

DOEpatents

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Universal power transistor base drive control unit

DOEpatents

Gale, A.R.; Gritter, D.J.

1988-06-07

A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

Faster Evolution of More Multifunctional Logic Circuits

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.

Automatic sweep circuit

DOEpatents

Keefe, Donald J.

1980-01-01

An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

Classical verification of quantum circuits containing few basis changes

NASA Astrophysics Data System (ADS)

Demarie, Tommaso F.; Ouyang, Yingkai; Fitzsimons, Joseph F.

2018-04-01

We consider the task of verifying the correctness of quantum computation for a restricted class of circuits which contain at most two basis changes. This contains circuits giving rise to the second level of the Fourier hierarchy, the lowest level for which there is an established quantum advantage. We show that when the circuit has an outcome with probability at least the inverse of some polynomial in the circuit size, the outcome can be checked in polynomial time with bounded error by a completely classical verifier. This verification procedure is based on random sampling of computational paths and is only possible given knowledge of the likely outcome.

Electronic Circuit Experiments and SPICE Simulation of Double Covering Bifurcation of 2-Torus Quasi-Periodic Flow in Phase-Locked Loop Circuit

NASA Astrophysics Data System (ADS)

Kamiyama, Kyohei; Endo, Tetsuro; Imai, Isao; Komuro, Motomasa

2016-06-01

Double covering (DC) bifurcation of a 2-torus quasi-periodic flow in a phase-locked loop circuit was experimentally investigated using an electronic circuit and via SPICE simulation; in the circuit, the input radio-frequency signal was frequency modulated by the sum of two asynchronous sinusoidal baseband signals. We observed both DC and period-doubling bifurcations of a discrete map on two Poincaré sections, which were realized by changing the sample timing from one baseband sinusoidal signal to the other. The results confirm the DC bifurcation of the original flow.

Compact, high-speed algorithm for laying out printed circuit board runs

NASA Astrophysics Data System (ADS)

Zapolotskiy, D. Y.

1985-09-01

A high speed printed circuit connection layout algorithm is described which was developed within the framework of an interactive system for designing two-sided printed circuit broads. For this reason, algorithm speed was considered, a priori, as a requirement equally as important as the inherent demand for minimizing circuit run lengths and the number of junction openings. This resulted from the fact that, in order to provide psychological man/machine compatibility in the design process, real-time dialog during the layout phase is possible only within limited time frames (on the order of several seconds) for each circuit run. The work was carried out for use on an ARM-R automated work site complex based on an SM-4 minicomputer with a 32K-word memory. This limited memory capacity heightened the demand for algorithm speed and also tightened data file structure and size requirements. The layout algorithm's design logic is analyzed. The structure and organization of the data files are described.

Method and apparatus for granting processors access to a resource

DOEpatents

Blumrich, Matthias A.; Salapura, Valentina

2010-03-16

An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals, and, generating a set of first_request signals based on the priorities assigned. One or more priority select circuits for receiving the set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during the predetermined time interval. A second circuit device receives the one or more fixed grant signals generates one or more grant signals associated with one or more highest priority request signals assigned, the grant signals for enabling one or more respective requesting entities access to the resource in the predetermined time interval, wherein the priority assigned to the one or more request signals changes each successive predetermined time interval. In one embodiment, the assigned priority is based on a numerical pattern, the first circuit changing the numerical pattern with respect to the first_request signals generated at each successive predetermined time interval.

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Solid state control system for oil well bailer pump

DOE Office of Scientific and Technical Information (OSTI.GOV)

Senghaas, K. A.; Senghaas, P.

1985-05-14

A solid state switching controller for use with various types of oil well bailer pumps. Individually programmable steps with lockouts provide multiple mutual exclusivity between various circuit operations. A trickle charge battery system powers the control circuits. A tank overflow float protects against oil spillage. An automatic production rate adjustment circuit is provided which increases cycle time in proportion to the rate of production. The circuit includes a low power voltage detector for disabling the control circuits until the line voltage is acceptable. A three-phase power and control system with an isolation transformer for the controls avoids unreliable ground connections.more » The timers include a dividing circuit with an RC circuit. All power actuated apparatus are actuated by triac switches which are controlled by an opto driver. The bailer brake is pulse actuated for allowing the bailer to sink into crude oil without excess cable looseness.« less

A spatially localized architecture for fast and modular DNA computing

NASA Astrophysics Data System (ADS)

Chatterjee, Gourab; Dalchau, Neil; Muscat, Richard A.; Phillips, Andrew; Seelig, Georg

2017-09-01

Cells use spatial constraints to control and accelerate the flow of information in enzyme cascades and signalling networks. Synthetic silicon-based circuitry similarly relies on spatial constraints to process information. Here, we show that spatial organization can be a similarly powerful design principle for overcoming limitations of speed and modularity in engineered molecular circuits. We create logic gates and signal transmission lines by spatially arranging reactive DNA hairpins on a DNA origami. Signal propagation is demonstrated across transmission lines of different lengths and orientations and logic gates are modularly combined into circuits that establish the universality of our approach. Because reactions preferentially occur between neighbours, identical DNA hairpins can be reused across circuits. Co-localization of circuit elements decreases computation time from hours to minutes compared to circuits with diffusible components. Detailed computational models enable predictive circuit design. We anticipate our approach will motivate using spatial constraints for future molecular control circuit designs.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

VLSI circuits implementing computational models of neocortical circuits.

PubMed

Wijekoon, Jayawan H B; Dudek, Piotr

2012-09-15

This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. Copyright © 2012 Elsevier B.V. All rights reserved.

MULTI-ELECTRODE TUBE PULSE MEMORY CIRCUIT

DOEpatents

Gundlach, J.C.; Reeves, J.B.

1958-05-20

Control circuits are described for pulse memory devices for scalers and the like, and more particularly to a driving or energizing circuit for a polycathode gaseous discharge tube having an elongated anode and a successive series of cathodes spaced opposite the anode along its length. The circuit is so arranged as to utilize an arc discharge between the anode and a cathode to count a series of pulses. Upon application of an input pulse the discharge is made to occur between the anode and the next successive cathode, and an output pulse is produced when a particular subsequent cathode is reached. The circuit means for transfering the discharge by altering the anode potential and potential of the cathodes and interconnecting the cathodes constitutes the novel aspects of the invention. A low response time and reduced number of circuit components are the practical advantages of the described circuit.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ryu, C.; Boshier, M. G.

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Procedures for Instructional Systems Development

DTIC Science & Technology

1981-09-18

single faults to the circuit and components level. (JTI Task No. TCB-01). Figure III-ll.--Example of a Module Page of a Curriculum Outline. 3 - 80...semiconductor trapezoidal wave generator circuit , multimeter, and oscilloscope measure the output amplitude, rise time, and jump voltage within +/- 10...accuracy. Given a trainer having a semiconductor trapezoidal wave generator circuit , multimeter, and oscilloscope - CONDITION (C) . measure the output

Novel high-frequency, high-power, pulsed oscillator based on a transmission line transformer.

PubMed

Burdt, R; Curry, R D

2007-07-01

Recent analysis and experiments have demonstrated the potential for transmission line transformers to be employed as compact, high-frequency, high-power, pulsed oscillators with variable rise time, high output impedance, and high operating efficiency. A prototype system was fabricated and tested that generates a damped sinusoidal wave form at a center frequency of 4 MHz into a 200 Omega load, with operating efficiency above 90% and peak power on the order of 10 MW. The initial rise time of the pulse is variable and two experiments were conducted to demonstrate initial rise times of 12 and 3 ns, corresponding to a spectral content from 4-30 and from 4-100 MHz, respectively. A SPICE model has been developed to accurately predict the circuit behavior and scaling laws have been identified to allow for circuit design at higher frequencies and higher peak power. The applications, circuit analysis, test stand, experimental results, circuit modeling, and design of future systems are all discussed.

Supervised Learning Using Spike-Timing-Dependent Plasticity of Memristive Synapses.

PubMed

Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito

2015-12-01

We propose a supervised learning model that enables error backpropagation for spiking neural network hardware. The method is modeled by modifying an existing model to suit the hardware implementation. An example of a network circuit for the model is also presented. In this circuit, a three-terminal ferroelectric memristor (3T-FeMEM), which is a field-effect transistor with a gate insulator composed of ferroelectric materials, is used as an electric synapse device to store the analog synaptic weight. Our model can be implemented by reflecting the network error to the write voltage of the 3T-FeMEMs and introducing a spike-timing-dependent learning function to the device. An XOR problem was successfully demonstrated as a benchmark learning by numerical simulations using the circuit properties to estimate the learning performance. In principle, the learning time per step of this supervised learning model and the circuit is independent of the number of neurons in each layer, promising a high-speed and low-power calculation in large-scale neural networks.

Algebraic method for parameter identification of circuit models for batteries under non-zero initial condition

NASA Astrophysics Data System (ADS)

Devarakonda, Lalitha; Hu, Tingshu

2014-12-01

This paper presents an algebraic method for parameter identification of Thevenin's equivalent circuit models for batteries under non-zero initial condition. In traditional methods, it was assumed that all capacitor voltages have zero initial conditions at the beginning of each charging/discharging test. This would require a long rest time between two tests, leading to very lengthy tests for a charging/discharging cycle. In this paper, we propose an algebraic method which can extract the circuit parameters together with initial conditions. This would theoretically reduce the rest time to 0 and substantially accelerate the testing cycles.

Multiple channel coincidence detector and controller for microseismic data analysis

DOEpatents

Fasching, George E.

1976-11-16

A multiple channel coincidence detector circuit is provided for analyzing data either in real time or recorded data on a magnetic tape during an experiment for determining location and progression of fractures in an oil field or the like while water is being injected at high pressure in wells located in the field. The circuit is based upon the utilization of a set of parity generator trees combined with monostable multivibrators to detect the occurrence of two events at any pair of channel input terminals that are within a preselected time frame and have an amplitude above a preselected magnitude. The parity generators perform an exclusive OR function in a timing circuit composed of monostable multivibrators that serve to yield an output when two events are present in the preselected time frame. Any coincidences falling outside this time frame are considered either noise or not otherwise useful in the analysis of the recorded data. Input pulses of absolute magnitude below the low-level threshold setting of a bipolar low-level threshold detector are unwanted and therefore rejected. A control output is provided for a utilization device from a coincidence hold circuit that may be used to halt a tape search unit at the time of coincidence or perform other useful control functions.

High-performance integrated pick-up circuit for SPAD arrays in time-correlated single photon counting

NASA Astrophysics Data System (ADS)

Acconcia, Giulia; Cominelli, Alessandro; Peronio, Pietro; Rech, Ivan; Ghioni, Massimo

2017-05-01

The analysis of optical signals by means of Single Photon Avalanche Diodes (SPADs) has been subject to a widespread interest in recent years. The development of multichannel high-performance Time Correlated Single Photon Counting (TCSPC) acquisition systems has undergone a fast trend. Concerning the detector performance, best in class results have been obtained resorting to custom technologies leading also to a strong dependence of the detector timing jitter from the threshold used to determine the onset of the photogenerated current flow. In this scenario, the avalanche current pick-up circuit plays a key role in determining the timing performance of the TCSPC acquisition system, especially with a large array of SPAD detectors because of electrical crosstalk issues. We developed a new current pick-up circuit based on a transimpedance amplifier structure able to extract the timing information from a 50-μm-diameter custom technology SPAD with a state-of-art timing jitter as low as 32ps and suitable to be exploited with SPAD arrays. In this paper we discuss the key features of this structure and we present a new version of the pick-up circuit that also provides quenching capabilities in order to minimize the number of interconnections required, an aspect that becomes more and more crucial in densely integrated systems.

Fully chip-embedded automation of a multi-step lab-on-a-chip process using a modularized timer circuit.

PubMed

Kang, Junsu; Lee, Donghyeon; Heo, Young Jin; Chung, Wan Kyun

2017-11-07

For highly-integrated microfluidic systems, an actuation system is necessary to control the flow; however, the bulk of actuation devices including pumps or valves has impeded the broad application of integrated microfluidic systems. Here, we suggest a microfluidic process control method based on built-in microfluidic circuits. The circuit is composed of a fluidic timer circuit and a pneumatic logic circuit. The fluidic timer circuit is a serial connection of modularized timer units, which sequentially pass high pressure to the pneumatic logic circuit. The pneumatic logic circuit is a NOR gate array designed to control the liquid-controlling process. By using the timer circuit as a built-in signal generator, multi-step processes could be done totally inside the microchip without any external controller. The timer circuit uses only two valves per unit, and the number of process steps can be extended without limitation by adding timer units. As a demonstration, an automation chip has been designed for a six-step droplet treatment, which entails 1) loading, 2) separation, 3) reagent injection, 4) incubation, 5) clearing and 6) unloading. Each process was successfully performed for a pre-defined step-time without any external control device.

Circuit for high resolution decoding of multi-anode microchannel array detectors

NASA Technical Reports Server (NTRS)

Kasle, David B. (Inventor)

1995-01-01

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Interpolator for numerically controlled machine tools

DOEpatents

Bowers, Gary L.; Davenport, Clyde M.; Stephens, Albert E.

1976-01-01

A digital differential analyzer circuit is provided that depending on the embodiment chosen can carry out linear, parabolic, circular or cubic interpolation. In the embodiment for parabolic interpolations, the circuit provides pulse trains for the X and Y slide motors of a two-axis machine to effect tool motion along a parabolic path. The pulse trains are generated by the circuit in such a way that parabolic tool motion is obtained from information contained in only one block of binary input data. A part contour may be approximated by one or more parabolic arcs. Acceleration and initial velocity values from a data block are set in fixed bit size registers for each axis separately but simultaneously and the values are integrated to obtain the movement along the respective axis as a function of time. Integration is performed by continual addition at a specified rate of an integrand value stored in one register to the remainder temporarily stored in another identical size register. Overflows from the addition process are indicative of the integral. The overflow output pulses from the second integration may be applied to motors which position the respective machine slides according to a parabolic motion in time to produce a parabolic machine tool motion in space. An additional register for each axis is provided in the circuit to allow "floating" of the radix points of the integrand registers and the velocity increment to improve position accuracy and to reduce errors encountered when the acceleration integrand magnitudes are small when compared to the velocity integrands. A divider circuit is provided in the output of the circuit to smooth the output pulse spacing and prevent motor stall, because the overflow pulses produced in the binary addition process are spaced unevenly in time. The divider has the effect of passing only every nth motor drive pulse, with n being specifiable. The circuit inputs (integrands, rates, etc.) are scaled to give exactly n times the desired number of pulses out, in order to compensate for the divider.

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

46 CFR 169.683 - Overcurrent protection, general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... time delay; (2) Instantaneous short circuit protection; and (3) Repeated opening of the circuit in... above the full-load rating for continuous rated machines or the overload rating for special rated machines. ...

A real time status monitor for transistor bank driver power limit resistor in boost injection kicker power supply

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, J.; Tan, Y.; Zhang, W.

2011-03-28

For years suffering of Booster Injection Kicker transistor bank driver regulator troubleshooting, a new real time monitor system has been developed. A simple and floating circuit has been designed and tested. This circuit monitor system can monitor the driver regulator power limit resistor status in real time and warn machine operator if the power limit resistor changes values. This paper will mainly introduce the power supply and the new designed monitoring system. This real time resistor monitor circuit shows a useful method to monitor some critical parts in the booster pulse power supply. After two years accelerator operation, it showsmore » that this monitor works well. Previously, we spent a lot of time in booster machine trouble shooting. We will reinstall all 4 PCB into Euro Card Standard Chassis when the power supply system will be updated.« less

The persistent current and energy spectrum on a driven mesoscopic LC-circuit with Josephson junction

NASA Astrophysics Data System (ADS)

Pahlavanias, Hassan

2018-03-01

The quantum theory for a mesoscopic electric circuit including a Josephson junction with charge discreteness is studied. By considering coupling energy of the mesoscopic capacitor in Josephson junction device, a Hamiltonian describing the dynamics of a quantum mesoscopic electric LC-circuit with charge discreteness is introduced. We first calculate the persistent current on a quantum driven ring including Josephson junction. Then we obtain the persistent current and energy spectrum of a quantum mesoscopic electrical circuit which includes capacitor, inductor, time-dependent external source and Josephson junction.

Biasing and fast degaussing circuit for magnetic materials

DOEpatents

Dress, Jr., William B.; McNeilly, David R.

1984-01-01

A dual-function circuit is provided which may be used to both magnetically bias and alternately, quickly degauss a magnetic device. The circuit may be magnetically coupled or directly connected electrically to a magnetic device, such as a magnetostrictive transducer, to magnetically bias the device by applying a d.c. current and alternately apply a selectively damped a.c. current to the device to degauss the device. The circuit is of particular value in many systems which use magnetostrictive transducers for ultrasonic transmission in different propagation modes over very short time periods.

Biasing and fast degaussing circuit for magnetic materials

DOEpatents

Dress, W.B. Jr.; McNeilly, D.R.

1983-10-04

A dual-function circuit is provided which may be used to both magnetically bias and alternately, quickly degauss a magnetic device. The circuit may be magnetically coupled or directly connected electrically to a magnetic device, such as a magnetostrictive transducer, to magnetically bias the device by applying a dc current and alternately apply a selectively damped ac current to the device to degauss the device. The circuit is of particular value in many systems which use magnetostrictive transducers for ultrasonic transmission in different propagation modes over very short time periods.

Energy pumping in electrical circuits under avalanche noise.

PubMed

Kanazawa, Kiyoshi; Sagawa, Takahiro; Hayakawa, Hisao

2014-07-01

We theoretically study energy pumping processes in an electrical circuit with avalanche diodes, where non-Gaussian athermal noise plays a crucial role. We show that a positive amount of energy (work) can be extracted by an external manipulation of the circuit in a cyclic way, even when the system is spatially symmetric. We discuss the properties of the energy pumping process for both quasistatic and finite-time cases, and analytically obtain formulas for the amounts of the work and the power. Our results demonstrate the significance of the non-Gaussianity in energetics of electrical circuits.

Overload protection circuit for output driver

DOEpatents

Stewart, Roger G.

1982-05-11

A protection circuit for preventing excessive power dissipation in an output transistor whose conduction path is connected between a power terminal and an output terminal. The protection circuit includes means for sensing the application of a turn on signal to the output transistor and the voltage at the output terminal. When the turn on signal is maintained for a period of time greater than a given period without the voltage at the output terminal reaching a predetermined value, the protection circuit decreases the turn on signal to, and the current conduction through, the output transistor.

The design of preamplifier and ADC circuit base on weak e-optical signal

NASA Astrophysics Data System (ADS)

Fen, Leng; Ying-ping, Yang; Ya-nan, Yu; Xiao-ying, Xu

2011-02-01

Combined with the demand of the process of weak e-optical signal in QPD detection system, the article introduced the circuit principle of deigning preamplifier and ADC circuit with I/V conversion, instrumentation amplifier, low-pass filter and 16-bit A/D transformation. At the same time the article discussed the circuit's noise suppression and isolation according to the characteristics of the weak signal, and gave the method of software rectification. Finally, tested the weak signal with keithley2000, and got a good effect.

A Printed Organic Circuit System for Wearable Amperometric Electrochemical Sensors.

PubMed

Shiwaku, Rei; Matsui, Hiroyuki; Nagamine, Kuniaki; Uematsu, Mayu; Mano, Taisei; Maruyama, Yuki; Nomura, Ayako; Tsuchiya, Kazuhiko; Hayasaka, Kazuma; Takeda, Yasunori; Fukuda, Takashi; Kumaki, Daisuke; Tokito, Shizuo

2018-04-23

Wearable sensor device technologies, which enable continuous monitoring of biological information from the human body, are promising in the fields of sports, healthcare, and medical applications. Further thinness, light weight, flexibility and low-cost are significant requirements for making the devices attachable onto human tissues or clothes like a patch. Here we demonstrate a flexible and printed circuit system consisting of an enzyme-based amperometric sensor, feedback control and amplification circuits based on organic thin-film transistors. The feedback control and amplification circuits based on pseudo-CMOS inverters were successfuly integrated by printing methods on a plastic film. This simple system worked very well like a potentiostat for electrochemical measurements, and enabled the quantitative and real-time measurement of lactate concentration with high sensitivity of 1 V/mM and a short response time of a hundred seconds.

Inverter Circuits using Pentacene and ZnO Transistors

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2007-04-01

We report two types of integrated circuits based on a pentacene static-induction transistor (SIT), a pentacene thin-film transistor (TFT) and a zinc oxide (ZnO) TFT. The operating characteristics of a p-p inverter using pentacene SITs and a complementary inverter using a p-channel pentacene TFT and an n-channel ZnO TFT are described. The basic operation of logic circuits at a low voltage was achieved for the first time using the pentacene SIT inverter and complementary circuits with hybrid inorganic and organic materials. Furthermore, we describe the electrical properties of the ZnO films depending on sputtering conditions, and the complementary circuits using ZnO and pentacene TFTs.

Focal plane infrared readout circuit

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2002-01-01

An infrared imager, such as a spectrometer, includes multiple infrared photodetectors and readout circuits for reading out signals from the photodetectors. Each readout circuit includes a buffered direct injection input circuit including a differential amplifier with active feedback provided through an injection transistor. The differential amplifier includes a pair of input transistors, a pair of cascode transistors and a current mirror load. Photocurrent from a photodetector can be injected onto an integration capacitor in the readout circuit with high injection efficiency at high speed. A high speed, low noise, wide dynamic range linear infrared multiplexer array for reading out infrared detectors with large capacitances can be achieved even when short exposure times are used. The effect of image lag can be reduced.

Overload protection system for power inverter

NASA Technical Reports Server (NTRS)

Nagano, S. (Inventor)

1977-01-01

An overload protection system for a power inverter utilized a first circuit for monitoring current to the load from the power inverter to detect an overload and a control circuit to shut off the power inverter, when an overload condition was detected. At the same time, a monitoring current inverter was turned on to deliver current to the load at a very low power level. A second circuit monitored current to the load, from the monitoring current inverter, to hold the power inverter off through the control circuit, until the overload condition was cleared so that the control circuit may be deactivated in order for the power inverter to be restored after the monitoring current inverter is turned off completely.

Note: Fully integrated active quenching circuit achieving 100 MHz count rate with custom technology single photon avalanche diodes.

PubMed

Acconcia, G; Labanca, I; Rech, I; Gulinatti, A; Ghioni, M

2017-02-01

The minimization of Single Photon Avalanche Diodes (SPADs) dead time is a key factor to speed up photon counting and timing measurements. We present a fully integrated Active Quenching Circuit (AQC) able to provide a count rate as high as 100 MHz with custom technology SPAD detectors. The AQC can also operate the new red enhanced SPAD and provide the timing information with a timing jitter Full Width at Half Maximum (FWHM) as low as 160 ps.

Combined Effects of Radio Frequency and Electron Radiation on CMOS Inverters

DTIC Science & Technology

2011-03-01

equipment that comes from taking real- time , in-situ measurements. To overcome this, a test circuit was designed and built to allow for real- time in...situ measurement of the output voltage, current and the inverter power. This test circuit provides real– time measurement of the inverter’s...now. To the “Operator of the Dynamitron at WSU”, thank you for your time , advice, and patience with all of my “why and how” questions. LTC McClory

High-Speed, High-Resolution Time-to-Digital Conversion

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor; Garcia, Rafael

2013-01-01

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Braiman, Yehuda; Neschke, Brendan; Nair, Niketh S.

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

PubMed

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

Open-loop digital frequency multiplier

NASA Technical Reports Server (NTRS)

Moore, R. C.

1977-01-01

Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.

Basic guidelines to introduce electric circuit simulation software in a general physics course

NASA Astrophysics Data System (ADS)

Moya, A. A.

2018-05-01

The introduction of electric circuit simulation software for undergraduate students in a general physics course is proposed in order to contribute to the constructive learning of electric circuit theory. This work focuses on the lab exercises based on dc, transient and ac analysis in electric circuits found in introductory physics courses, and shows how students can use the simulation software to do simple activities associated with a lab exercise itself and with related topics. By introducing electric circuit simulation programs in a general physics course as a brief activitiy complementing lab exercise, students develop basic skills in using simulation software, improve their knowledge on the topology of electric circuits and perceive that the technology contributes to their learning, all without reducing the time spent on the actual content of the course.

Low Insertion HVDC Circuit Breaker: Magnetically Pulsed Hybrid Breaker for HVDC Power Distribution Protection

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2012-01-09

GENI Project: General Atomics is developing a direct current (DC) circuit breaker that could protect the grid from faults 100 times faster than its alternating current (AC) counterparts. Circuit breakers are critical elements in any electrical system. At the grid level, their main function is to isolate parts of the grid where a fault has occurred—such as a downed power line or a transformer explosion—from the rest of the system. DC circuit breakers must interrupt the system during a fault much faster than AC circuit breakers to prevent possible damage to cables, converters and other grid-level components. General Atomics’ high-voltagemore » DC circuit breaker would react in less than 1/1,000th of a second to interrupt current during a fault, preventing potential hazards to people and equipment.« less

Neuroelectric Tuning of Cortical Oscillations by Apical Dendrites in Loop Circuits

PubMed Central

LaBerge, David; Kasevich, Ray S.

2017-01-01

Bundles of relatively long apical dendrites dominate the neurons that make up the thickness of the cerebral cortex. It is proposed that a major function of the apical dendrite is to produce sustained oscillations at a specific frequency that can serve as a common timing unit for the processing of information in circuits connected to that apical dendrite. Many layer 5 and 6 pyramidal neurons are connected to thalamic neurons in loop circuits. A model of the apical dendrites of these pyramidal neurons has been used to simulate the electric activity of the apical dendrite. The results of that simulation demonstrated that subthreshold electric pulses in these apical dendrites can be tuned to specific frequencies and also can be fine-tuned to narrow bandwidths of less than one Hertz (1 Hz). Synchronous pulse outputs from the circuit loops containing apical dendrites can tune subthreshold membrane oscillations of neurons they contact. When the pulse outputs are finely tuned, they function as a local “clock,” which enables the contacted neurons to synchronously communicate with each other. Thus, a shared tuning frequency can select neurons for membership in a circuit. Unlike layer 6 apical dendrites, layer 5 apical dendrites can produce burst firing in many of their neurons, which increases the amplitude of signals in the neurons they contact. This difference in amplitude of signals serves as basis of selecting a sub-circuit for specialized processing (e.g., sustained attention) within the typically larger layer 6-based circuit. After examining the sustaining of oscillations in loop circuits and the processing of spikes in network circuits, we propose that cortical functioning can be globally viewed as two systems: a loop system and a network system. The loop system oscillations influence the network system’s timing and amplitude of pulse signals, both of which can select circuits that are momentarily dominant in cortical activity. PMID:28659768

Neuroelectric Tuning of Cortical Oscillations by Apical Dendrites in Loop Circuits.

PubMed

LaBerge, David; Kasevich, Ray S

2017-01-01

Bundles of relatively long apical dendrites dominate the neurons that make up the thickness of the cerebral cortex. It is proposed that a major function of the apical dendrite is to produce sustained oscillations at a specific frequency that can serve as a common timing unit for the processing of information in circuits connected to that apical dendrite. Many layer 5 and 6 pyramidal neurons are connected to thalamic neurons in loop circuits. A model of the apical dendrites of these pyramidal neurons has been used to simulate the electric activity of the apical dendrite. The results of that simulation demonstrated that subthreshold electric pulses in these apical dendrites can be tuned to specific frequencies and also can be fine-tuned to narrow bandwidths of less than one Hertz (1 Hz). Synchronous pulse outputs from the circuit loops containing apical dendrites can tune subthreshold membrane oscillations of neurons they contact. When the pulse outputs are finely tuned, they function as a local "clock," which enables the contacted neurons to synchronously communicate with each other. Thus, a shared tuning frequency can select neurons for membership in a circuit. Unlike layer 6 apical dendrites, layer 5 apical dendrites can produce burst firing in many of their neurons, which increases the amplitude of signals in the neurons they contact. This difference in amplitude of signals serves as basis of selecting a sub-circuit for specialized processing (e.g., sustained attention) within the typically larger layer 6-based circuit. After examining the sustaining of oscillations in loop circuits and the processing of spikes in network circuits, we propose that cortical functioning can be globally viewed as two systems: a loop system and a network system. The loop system oscillations influence the network system's timing and amplitude of pulse signals, both of which can select circuits that are momentarily dominant in cortical activity.

A parallel algorithm for switch-level timing simulation on a hypercube multiprocessor

NASA Technical Reports Server (NTRS)

Rao, Hariprasad Nannapaneni

1989-01-01

The parallel approach to speeding up simulation is studied, specifically the simulation of digital LSI MOS circuitry on the Intel iPSC/2 hypercube. The simulation algorithm is based on RSIM, an event driven switch-level simulator that incorporates a linear transistor model for simulating digital MOS circuits. Parallel processing techniques based on the concepts of Virtual Time and rollback are utilized so that portions of the circuit may be simulated on separate processors, in parallel for as large an increase in speed as possible. A partitioning algorithm is also developed in order to subdivide the circuit for parallel processing.

Using Movies to Analyse Gene Circuit Dynamics in Single Cells

PubMed Central

Locke, James CW; Elowitz, Michael B

2010-01-01

Preface Many bacterial systems rely on dynamic genetic circuits to control critical processes. A major goal of systems biology is to understand these behaviours in terms of individual genes and their interactions. However, traditional techniques based on population averages wash out critical dynamics that are either unsynchronized between cells or driven by fluctuations, or ‘noise,’ in cellular components. Recently, the combination of time-lapse microscopy, quantitative image analysis, and fluorescent protein reporters has enabled direct observation of multiple cellular components over time in individual cells. In conjunction with mathematical modelling, these techniques are now providing powerful insights into genetic circuit behaviour in diverse microbial systems. PMID:19369953

An educational laboratory virtual instrumentation suite assisted experiment for studying fundamentals of series resistance-inductance-capacitance circuit

NASA Astrophysics Data System (ADS)

Rana, K. P. S.; Kumar, Vineet; Mendiratta, Jatin

2017-11-01

One of the most elementary concepts in freshmen Electrical Engineering subject comprises the Resistance-Inductance-Capacitance (RLC) circuit fundamentals, that is, their time and frequency domain responses. For a beginner, generally, it is difficult to understand and appreciate the step and the frequency responses, particularly the resonance. This paper proposes a student-friendly teaching and learning approach by inculcating the multifaceted versatile software LabVIEWTM along with the educational laboratory virtual instrumentation suite hardware, for studying the RLC circuit time and frequency domain responses. The proposed approach has offered an interactive laboratory experiment where students can model circuits in simulation and hardware circuits on prototype board, and then compare their performances. The theoretical simulations and the obtained experimental data are found to be in very close agreement, thereby enhancing the conviction of students. Finally, the proposed methodology was also subjected to the assessment of learning outcomes based on student feedback, and an average score of 8.05 out of 10 with a standard deviation of 0.471 was received, indicating the overall satisfaction of the students.

Bio-inspired feedback-circuit implementation of discrete, free energy optimizing, winner-take-all computations.

PubMed

Genewein, Tim; Braun, Daniel A

2016-06-01

Bayesian inference and bounded rational decision-making require the accumulation of evidence or utility, respectively, to transform a prior belief or strategy into a posterior probability distribution over hypotheses or actions. Crucially, this process cannot be simply realized by independent integrators, since the different hypotheses and actions also compete with each other. In continuous time, this competitive integration process can be described by a special case of the replicator equation. Here we investigate simple analog electric circuits that implement the underlying differential equation under the constraint that we only permit a limited set of building blocks that we regard as biologically interpretable, such as capacitors, resistors, voltage-dependent conductances and voltage- or current-controlled current and voltage sources. The appeal of these circuits is that they intrinsically perform normalization without requiring an explicit divisive normalization. However, even in idealized simulations, we find that these circuits are very sensitive to internal noise as they accumulate error over time. We discuss in how far neural circuits could implement these operations that might provide a generic competitive principle underlying both perception and action.

Circuit-based versus full-wave modelling of active microwave circuits

NASA Astrophysics Data System (ADS)

Bukvić, Branko; Ilić, Andjelija Ž.; Ilić, Milan M.

2018-03-01

Modern full-wave computational tools enable rigorous simulations of linear parts of complex microwave circuits within minutes, taking into account all physical electromagnetic (EM) phenomena. Non-linear components and other discrete elements of the hybrid microwave circuit are then easily added within the circuit simulator. This combined full-wave and circuit-based analysis is a must in the final stages of the circuit design, although initial designs and optimisations are still faster and more comfortably done completely in the circuit-based environment, which offers real-time solutions at the expense of accuracy. However, due to insufficient information and general lack of specific case studies, practitioners still struggle when choosing an appropriate analysis method, or a component model, because different choices lead to different solutions, often with uncertain accuracy and unexplained discrepancies arising between the simulations and measurements. We here design a reconfigurable power amplifier, as a case study, using both circuit-based solver and a full-wave EM solver. We compare numerical simulations with measurements on the manufactured prototypes, discussing the obtained differences, pointing out the importance of measured parameters de-embedding, appropriate modelling of discrete components and giving specific recipes for good modelling practices.

Gate drive latching circuit for an auxiliary resonant commutation circuit

NASA Technical Reports Server (NTRS)

Delgado, Eladio Clemente (Inventor); Kheraluwala, Mustansir Hussainy (Inventor)

1999-01-01

A gate drive latching circuit for an auxiliary resonant commutation circuit for a power switching inverter includes a current monitor circuit providing a current signal to a pair of analog comparators to implement latching of one of a pair of auxiliary switching devices which are used to provide commutation current for commutating switching inverters in the circuit. Each of the pair of comparators feeds a latching circuit which responds to an active one of the comparators for latching the associated gate drive circuit for one of the pair of auxiliary commutating switches. An initial firing signal is applied to each of the commutating switches to gate each into conduction and the resulting current is monitored to determine current direction and therefore the one of the switches which is carrying current. The comparator provides a latching signal to the one of the auxiliary power switches which is actually conducting current and latches that particular power switch into an on state for the duration of current through the device. The latching circuit is so designed that the only time one of the auxiliary switching devices can be latched on is during the duration of an initial firing command signal.

Thermally-induced voltage alteration for integrated circuit analysis

DOEpatents

Cole, Jr., Edward I.

2000-01-01

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

High voltage pulse generator

DOEpatents

Fasching, George E.

1977-03-08

An improved high-voltage pulse generator has been provided which is especially useful in ultrasonic testing of rock core samples. An N number of capacitors are charged in parallel to V volts and at the proper instance are coupled in series to produce a high-voltage pulse of N times V volts. Rapid switching of the capacitors from the paralleled charging configuration to the series discharging configuration is accomplished by using silicon-controlled rectifiers which are chain self-triggered following the initial triggering of a first one of the rectifiers connected between the first and second of the plurality of charging capacitors. A timing and triggering circuit is provided to properly synchronize triggering pulses to the first SCR at a time when the charging voltage is not being applied to the parallel-connected charging capacitors. Alternate circuits are provided for controlling the application of the charging voltage from a charging circuit to be applied to the parallel capacitors which provides a selection of at least two different intervals in which the charging voltage is turned "off" to allow the SCR's connecting the capacitors in series to turn "off" before recharging begins. The high-voltage pulse-generating circuit including the N capacitors and corresponding SCR's which connect the capacitors in series when triggered "on" further includes diodes and series-connected inductors between the parallel-connected charging capacitors which allow sufficiently fast charging of the capacitors for a high pulse repetition rate and yet allow considerable control of the decay time of the high-voltage pulses from the pulse-generating circuit.

CHEETAH: circuit-switched high-speed end-to-end transport architecture

NASA Astrophysics Data System (ADS)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

ADJUSTABLE DOUBLE PULSE GENERATOR

DOEpatents

Gratian, J.W.; Gratian, A.C.

1961-08-01

>A modulator pulse source having adjustable pulse width and adjustable pulse spacing is described. The generator consists of a cross coupled multivibrator having adjustable time constant circuitry in each leg, an adjustable differentiating circuit in the output of each leg, a mixing and rectifying circuit for combining the differentiated pulses and generating in its output a resultant sequence of negative pulses, and a final amplifying circuit for inverting and square-topping the pulses. (AEC)

Circadian variations in biologically closed electrochemical circuits in Aloe vera and Mimosa pudica.

PubMed

Volkov, Alexander G; Baker, Kara; Foster, Justin C; Clemmons, Jacqueline; Jovanov, Emil; Markin, Vladislav S

2011-04-01

The circadian clock regulates a wide range of electrophysiological and developmental processes in plants. This paper presents, for the first time, the direct influence of a circadian clock on biologically closed electrochemical circuits in vivo. Here we show circadian variation of the plant responses to electrical stimulation. The biologically closed electrochemical circuits in the leaves of Aloe vera and Mimosa pudica, which regulate their physiology, were analyzed using the charge stimulation method. The electrostimulation was provided with different timing and different voltages. Resistance between Ag/AgCl electrodes in the leaf of Aloe vera was higher during the day than at night. Discharge of the capacitor in Aloe vera at night was faster than during the day. Discharge of the capacitor in a pulvinus of Mimosa pudica was faster during the day. The biologically closed electrical circuits with voltage gated ion channels in Mimosa pudica are also activated the next day, even in the darkness. These results show that the circadian clock can be maintained endogenously and has electrochemical oscillators, which can activate ion channels in biologically closed electrochemical circuits. We present the equivalent electrical circuits in both plants and their circadian variation to explain the experimental data. Copyright © 2011 Elsevier B.V. All rights reserved.

The Induction of Chaos in Electronic Circuits Final Report-October 1, 2001

DOE Office of Scientific and Technical Information (OSTI.GOV)

R.M.Wheat, Jr.

2003-04-01

This project, now known by the name ''Chaos in Electronic Circuits,'' was originally tasked as a two-year project to examine various ''fault'' or ''non-normal'' operational states of common electronic circuits with some focus on determining the feasibility of exploiting these states. Efforts over the two-year duration of this project have been dominated by the study of the chaotic behavior of electronic circuits. These efforts have included setting up laboratory space and hardware for conducting laboratory tests and experiments, acquiring and developing computer simulation and analysis capabilities, conducting literature surveys, developing test circuitry and computer models to exercise and test ourmore » capabilities, and experimenting with and studying the use of RF injection as a means of inducing chaotic behavior in electronics. An extensive array of nonlinear time series analysis tools have been developed and integrated into a package named ''After Acquisition'' (AA), including capabilities such as Delayed Coordinate Embedding Mapping (DCEM), Time Resolved (3-D) Fourier Transform, and several other phase space re-creation methods. Many computer models have been developed for Spice and for the ATP (Alternative Transients Program), modeling the several working circuits that have been developed for use in the laboratory. And finally, methods of induction of chaos in electronic circuits have been explored.« less

Energy saving in ac generators

NASA Technical Reports Server (NTRS)

Nola, F. J.

1980-01-01

Circuit cuts no-load losses, without sacrificing full-load power. Phase-contro circuit includes gate-controlled semiconductor switch that cuts off applied voltage for most of ac cycle if generator idling. Switch "on" time increases when generator is in operation.

Study of mathematical modeling of communication systems transponders and receivers

NASA Technical Reports Server (NTRS)

Walsh, J. R.

1972-01-01

The modeling of communication receivers is described at both the circuit detail level and at the block level. The largest effort was devoted to developing new models at the block modeling level. The available effort did not permit full development of all of the block modeling concepts envisioned, but idealized blocks were developed for signal sources, a variety of filters, limiters, amplifiers, mixers, and demodulators. These blocks were organized into an operational computer simulation of communications receiver circuits identified as the frequency and time circuit analysis technique (FATCAT). The simulation operates in both the time and frequency domains, and permits output plots or listings of either frequency spectra or time waveforms from any model block. Transfer between domains is handled with a fast Fourier transform algorithm.

Reduced circuit implementation of encoder and syndrome generator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Trager, Barry M; Winograd, Shmuel

An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(2.sup.8) which has 72 symbols, three (3) blocks of addresses which differ by a cubemore » root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.« less

SEMICONDUCTOR INTEGRATED CIRCUITS: A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

NASA Astrophysics Data System (ADS)

Jizhi, Liu; Xingbi, Chen

2009-12-01

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.

Hybrid Circuit QED with Electrons on Helium

NASA Astrophysics Data System (ADS)

Yang, Ge

Electrons on helium (eHe) is a 2-dimensional system that forms naturally at the interface between superfluid helium and vacuum. It has the highest measured electron mobility, and long predicted spin coherence time. In this talk, we will first review various quantum computer architecture proposals that take advantage of these exceptional properties. In particular, we describe how electrons on helium can be combined with superconducting microwave circuits to take advantage of the recent progress in the field of circuit quantum electrodynamics (cQED). We will then demonstrate how to reliably trap electrons on these devices hours at a time, at millikelvin temperatures inside a dilution refrigerator. The coupling between the electrons and the microwave resonator exceeds 1 MHz, and can be reproduced from the design geometry using our numerical simulation. Finally, we will present our progress on isolating individual electrons in such circuits, to build single-electron quantum dots with electrons on helium.

Efficient quantum walk on a quantum processor

PubMed Central

Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

2016-01-01

The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

LINEAR COUNT-RATE METER

DOEpatents

Henry, J.J.

1961-09-01

A linear count-rate meter is designed to provide a highly linear output while receiving counting rates from one cycle per second to 100,000 cycles per second. Input pulses enter a linear discriminator and then are fed to a trigger circuit which produces positive pulses of uniform width and amplitude. The trigger circuit is connected to a one-shot multivibrator. The multivibrator output pulses have a selected width. Feedback means are provided for preventing transistor saturation in the multivibrator which improves the rise and decay times of the output pulses. The multivibrator is connected to a diode-switched, constant current metering circuit. A selected constant current is switched to an averaging circuit for each pulse received, and for a time determined by the received pulse width. The average output meter current is proportional to the product of the counting rate, the constant current, and the multivibrator output pulse width.

Research on Mechanical Fault Prediction Algorithm for Circuit Breaker Based on Sliding Time Window and ANN

NASA Astrophysics Data System (ADS)

Wang, Xiaohua; Rong, Mingzhe; Qiu, Juan; Liu, Dingxin; Su, Biao; Wu, Yi

A new type of algorithm for predicting the mechanical faults of a vacuum circuit breaker (VCB) based on an artificial neural network (ANN) is proposed in this paper. There are two types of mechanical faults in a VCB: operation mechanism faults and tripping circuit faults. An angle displacement sensor is used to measure the main axle angle displacement which reflects the displacement of the moving contact, to obtain the state of the operation mechanism in the VCB, while a Hall current sensor is used to measure the trip coil current, which reflects the operation state of the tripping circuit. Then an ANN prediction algorithm based on a sliding time window is proposed in this paper and successfully used to predict mechanical faults in a VCB. The research results in this paper provide a theoretical basis for the realization of online monitoring and fault diagnosis of a VCB.

SENARIET, A Programme To Solve Transient Flows Of Liquids In Complex Circuits

NASA Astrophysics Data System (ADS)

Vargas-Munoz, M.; Rodriguez-Fernandez, M.; Perena-Tapiador, A.

2011-05-01

SENARIET is a programme to study fluid transients in pipeline systems in order to obtain pressure and velocity distributions along a circuit. When a transient process occurs in periods of the same order of the pressure waves’ travelling time along a circuit (the order of the circuit length divided by the effective propagation speed), the compressibility effects in liquids have to be considered. Taking this effect into account, the appropriate equations of continuity and momentum are solved by the method of characteristics, to obtain pressure and velocity along pipes as a function of time. The simulated results have been compared to theoretical and experimental ones to validate and evaluate the precision of the software. The results help to perform efficient and accurate predictions in order to define the propulsion sub-system. This type of analysis is very important in order to evaluate the water hammer effects in propulsion systems used on spacecrafts and launchers.

Circuit for monitoring temperature of high-voltage equipment

DOEpatents

Jacobs, Martin E.

1976-01-01

This invention relates to an improved circuit for measuring temperature in a region at high electric potential and generating a read-out of the same in a region at lower potential. The circuit is specially designed to combine high sensitivity, stability, and accuracy. A major portion of the circuit situated in the high-potential region can take the form of an integrated circuit. The preferred form of the circuit includes an input section which is situated in the high-potential region and comprises a temperature-compensated thermocouple circuit for sensing temperature, an oscillator circuit for generating a train of ramp voltages whose rise time varies inversely with the thermocouple output, a comparator and switching circuit for converting the oscillator output to pulses whose frequency is proportional to the thermocouple output, and a light-emitting diode which is energized by these pulses. An optical coupling transmits the light pulses generated by the diode to an output section of the circuit, situated in a region at ground. The output section comprises means for converting the transmitted pulses to electrical pulses of corresponding frequency, means for amplifying the electrical pulses, and means for displaying the frequency of the same. The preferred embodiment of the overall circuit is designed so that the frequency of the output signal in hertz and tenths of hertz is equal to the sensed temperature in degrees and tenths of degrees.

Parameter space of experimental chaotic circuits with high-precision control parameters.

PubMed

de Sousa, Francisco F G; Rubinger, Rero M; Sartorelli, José C; Albuquerque, Holokx A; Baptista, Murilo S

2016-08-01

We report high-resolution measurements that experimentally confirm a spiral cascade structure and a scaling relationship of shrimps in the Chua's circuit. Circuits constructed using this component allow for a comprehensive characterization of the circuit behaviors through high resolution parameter spaces. To illustrate the power of our technological development for the creation and the study of chaotic circuits, we constructed a Chua circuit and study its high resolution parameter space. The reliability and stability of the designed component allowed us to obtain data for long periods of time (∼21 weeks), a data set from which an accurate estimation of Lyapunov exponents for the circuit characterization was possible. Moreover, this data, rigorously characterized by the Lyapunov exponents, allows us to reassure experimentally that the shrimps, stable islands embedded in a domain of chaos in the parameter spaces, can be observed in the laboratory. Finally, we confirm that their sizes decay exponentially with the period of the attractor, a result expected to be found in maps of the quadratic family.

Assessment of Systematic Measurement Errors for Acoustic Travel-Time Tomography of the Atmosphere

DTIC Science & Technology

2013-01-01

measurements include assess- ment of the time delays in electronic circuits and mechanical hardware (e.g., drivers and microphones) of a tomography array ...hardware and electronic circuits of the tomography array and errors in synchronization of the transmitted and recorded signals. For example, if...coordinates can be as large as 30 cm. These errors are equivalent to the systematic errors in the travel times of 0.9 ms. Third, loudspeakers which are used

Equivalent circuit consideration of frequency-shift-type acceleration sensor

NASA Astrophysics Data System (ADS)

Sasaki, Yoshifumi; Sugawara, Sumio; Kudo, Subaru

2018-07-01

In this paper, an electrical equivalent circuit for the piezoelectrically driven frequency-shift-type acceleration sensor model is represented, and the equivalent circuit constants including the effect of the axial force are clarified for the first time. The results calculated by the finite element method are compared with the experimentally measured ones of the one-axis sensor of trial production. The result shows that the analyzed values almost agree with the measured ones, and that the equivalent circuit representation of the sensor is useful for electrical engineers in order to easily analyze the characteristics of the sensors.

Slow-wave propagation on monolithic microwave integrated circuits with layered and non-layered structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tzuang, C.K.C.

1986-01-01

Various MMIC (monolithic microwave integrated circuit) planar waveguides have shown possible existence of a slow-wave propagation. In many practical applications of these slow-wave circuits, the semiconductor devices have nonuniform material properties that may affect the slow-wave propagation. In the first part of the dissertation, the effects of the nonuniform material properties are studied by a finite-element method. In addition, the transient pulse excitations of these slow-wave circuits also have great theoretical and practical interests. In the second part, the time-domain analysis of a slow-wave coplanar waveguide is presented.

Simulation of TunneLadder traveling-wave tube cold-test characteristics: Implementation of the three-dimensional, electromagnetic circuit analysis code micro-SOS

NASA Technical Reports Server (NTRS)

Kory, Carol L.; Wilson, Jeffrey D.

1993-01-01

The three-dimensional, electromagnetic circuit analysis code, Micro-SOS, can be used to reduce expensive time-consuming experimental 'cold-testing' of traveling-wave tube (TWT) circuits. The frequency-phase dispersion characteristics and beam interaction impedance of a TunneLadder traveling-wave tube slow-wave structure were simulated using the code. When reasonable dimensional adjustments are made, computer results agree closely with experimental data. Modifications to the circuit geometry that would make the TunneLadder TWT easier to fabricate for higher frequency operation are explored.

Logic circuits based on molecular spider systems.

PubMed

Mo, Dandan; Lakin, Matthew R; Stefanovic, Darko

2016-08-01

Spatial locality brings the advantages of computation speed-up and sequence reuse to molecular computing. In particular, molecular walkers that undergo localized reactions are of interest for implementing logic computations at the nanoscale. We use molecular spider walkers to implement logic circuits. We develop an extended multi-spider model with a dynamic environment wherein signal transmission is triggered via localized reactions, and use this model to implement three basic gates (AND, OR, NOT) and a cascading mechanism. We develop an algorithm to automatically generate the layout of the circuit. We use a kinetic Monte Carlo algorithm to simulate circuit computations, and we analyze circuit complexity: our design scales linearly with formula size and has a logarithmic time complexity. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Nucleic acids for the rational design of reaction circuits.

PubMed

Padirac, Adrien; Fujii, Teruo; Rondelez, Yannick

2013-08-01

Nucleic acid-based circuits are rationally designed in vitro assemblies that can perform complex preencoded programs. They can be used to mimic in silico computations. Recent works emphasized the modularity and robustness of these circuits, which allow their scaling-up. Another new development has led to dynamic, time-responsive systems that can display emergent behaviors like oscillations. These are closely related to biological architectures and provide an in vitro model of in vivo information processing. Nucleic acid circuits have already been used to handle various processes for technological or biotechnological purposes. Future applications of these chemical smart systems will benefit from the rapidly growing ability to design, construct, and model nucleic acid circuits of increasing size. Copyright © 2012 Elsevier Ltd. All rights reserved.

Josephson junction in the quantum mesoscopic electric circuits with charge discreteness

NASA Astrophysics Data System (ADS)

Pahlavani, H.

2018-04-01

A quantum mesoscopic electrical LC-circuit with charge discreteness including a Josephson junction is considered and a nonlinear Hamiltonian that describing the dynamic of such circuit is introduced. The quantum dynamical behavior (persistent current probability) is studied in the charge and phase regimes by numerical solution approaches. The time evolution of charge and current, number-difference and the bosonic phase and also the energy spectrum of a quantum mesoscopic electric LC-circuit with charge discreteness that coupled with a Josephson junction device are investigated. We show the role of the coupling energy and the electrostatic Coulomb energy of the Josephson junction in description of the quantum behavior and the spectral properties of a quantum mesoscopic electrical LC-circuits with charge discreteness.

An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

NASA Astrophysics Data System (ADS)

McEwan, Alistair; van Schaik, André

2003-12-01

The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing

PubMed Central

Chen, Szi-Wen; Chen, Yuan-Ho

2015-01-01

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz. PMID:26501290

Hardware design and implementation of a wavelet de-noising procedure for medical signal preprocessing.

PubMed

Chen, Szi-Wen; Chen, Yuan-Ho

2015-10-16

In this paper, a discrete wavelet transform (DWT) based de-noising with its applications into the noise reduction for medical signal preprocessing is introduced. This work focuses on the hardware realization of a real-time wavelet de-noising procedure. The proposed de-noising circuit mainly consists of three modules: a DWT, a thresholding, and an inverse DWT (IDWT) modular circuits. We also proposed a novel adaptive thresholding scheme and incorporated it into our wavelet de-noising procedure. Performance was then evaluated on both the architectural designs of the software and. In addition, the de-noising circuit was also implemented by downloading the Verilog codes to a field programmable gate array (FPGA) based platform so that its ability in noise reduction may be further validated in actual practice. Simulation experiment results produced by applying a set of simulated noise-contaminated electrocardiogram (ECG) signals into the de-noising circuit showed that the circuit could not only desirably meet the requirement of real-time processing, but also achieve satisfactory performance for noise reduction, while the sharp features of the ECG signals can be well preserved. The proposed de-noising circuit was further synthesized using the Synopsys Design Compiler with an Artisan Taiwan Semiconductor Manufacturing Company (TSMC, Hsinchu, Taiwan) 40 nm standard cell library. The integrated circuit (IC) synthesis simulation results showed that the proposed design can achieve a clock frequency of 200 MHz and the power consumption was only 17.4 mW, when operated at 200 MHz.

Characterization of CNRS Fizeau wedge laser tuner

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

A fringe detection and measurement system was constructed for use with the CNRS Fizeau wedge laser tuner, consisting of three circuit boards. The first board is a standard Reticon RC-100 B motherboard which is used to provide the timing, video processing, and housekeeping functions required by the Reticon RL-512 G photodiode array used in the system. The sampled and held video signal from the motherboard is processed by a second, custom-fabricated circuit board which contains a high-speed fringe detection and locating circuit. This board includes a dc level-discriminator-type fringe detector, a counter circuit to determine fringe center, a pulsed lasermore » triggering circuit, and a control circuit to operate the shutter for the He-Ne reference laser beam. The fringe center information is supplied to the third board, a commercial single board computer, which governs the data-collection process and interprets the results.« less

Quantum realization of the nearest-neighbor interpolation method for FRQI and NEQR

NASA Astrophysics Data System (ADS)

Sang, Jianzhi; Wang, Shen; Niu, Xiamu

2016-01-01

This paper is concerned with the feasibility of the classical nearest-neighbor interpolation based on flexible representation of quantum images (FRQI) and novel enhanced quantum representation (NEQR). Firstly, the feasibility of the classical image nearest-neighbor interpolation for quantum images of FRQI and NEQR is proven. Then, by defining the halving operation and by making use of quantum rotation gates, the concrete quantum circuit of the nearest-neighbor interpolation for FRQI is designed for the first time. Furthermore, quantum circuit of the nearest-neighbor interpolation for NEQR is given. The merit of the proposed NEQR circuit lies in their low complexity, which is achieved by utilizing the halving operation and the quantum oracle operator. Finally, in order to further improve the performance of the former circuits, new interpolation circuits for FRQI and NEQR are presented by using Control-NOT gates instead of a halving operation. Simulation results show the effectiveness of the proposed circuits.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

Demultiplexer circuit for neural stimulation

DOEpatents

Wessendorf, Kurt O; Okandan, Murat; Pearson, Sean

2012-10-09

A demultiplexer circuit is disclosed which can be used with a conventional neural stimulator to extend the number of electrodes which can be activated. The demultiplexer circuit, which is formed on a semiconductor substrate containing a power supply that provides all the dc electrical power for operation of the circuit, includes digital latches that receive and store addressing information from the neural stimulator one bit at a time. This addressing information is used to program one or more 1:2.sup.N demultiplexers in the demultiplexer circuit which then route neural stimulation signals from the neural stimulator to an electrode array which is connected to the outputs of the 1:2.sup.N demultiplexer. The demultiplexer circuit allows the number of individual electrodes in the electrode array to be increased by a factor of 2.sup.N with N generally being in a range of 2-4.

Characterization of CNRS Fizeau wedge laser tuner

NASA Technical Reports Server (NTRS)

1984-01-01

A fringe detection and measurement system was constructed for use with the CNRS Fizeau wedge laser tuner, consisting of three circuit boards. The first board is a standard Reticon RC-100 B motherboard which is used to provide the timing, video processing, and housekeeping functions required by the Reticon RL-512 G photodiode array used in the system. The sampled and held video signal from the motherboard is processed by a second, custom fabricated circuit board which contains a high speed fringe detection and locating circuit. This board includes a dc level discriminator type fringe detector, a counter circuit to determine fringe center, a pulsed laser triggering circuit, and a control circuit to operate the shutter for the He-Ne reference laser beam. The fringe center information is supplied to the third board, a commercial single board computer, which governs the data collection process and interprets the results.

Method and apparatus for linear low-frequency feedback in monolithic low-noise charge amplifiers

DOEpatents

DeGeronimo, Gianluigi

2006-02-14

A charge amplifier includes an amplifier, feedback circuit, and cancellation circuit. The feedback circuit includes a capacitor, inverter, and current mirror. The capacitor is coupled across the signal amplifier, the inverter is coupled to the output of the signal amplifier, and the current mirror is coupled to the input of the signal amplifier. The cancellation circuit is coupled to the output of the signal amplifier. A method of charge amplification includes providing a signal amplifier; coupling a first capacitor across the signal amplifier; coupling an inverter to the output of the signal amplifier; coupling a current mirror to the input of the signal amplifier; and coupling a cancellation circuit to the output of the signal amplifier. A front-end system for use with radiation sensors includes a charge amplifier and a current amplifier, shaping amplifier, baseline stabilizer, discriminator, peak detector, timing detector, and logic circuit coupled to the charge amplifier.

Trading Speed and Accuracy by Coding Time: A Coupled-circuit Cortical Model

PubMed Central

Standage, Dominic; You, Hongzhi; Wang, Da-Hui; Dorris, Michael C.

2013-01-01

Our actions take place in space and time, but despite the role of time in decision theory and the growing acknowledgement that the encoding of time is crucial to behaviour, few studies have considered the interactions between neural codes for objects in space and for elapsed time during perceptual decisions. The speed-accuracy trade-off (SAT) provides a window into spatiotemporal interactions. Our hypothesis is that temporal coding determines the rate at which spatial evidence is integrated, controlling the SAT by gain modulation. Here, we propose that local cortical circuits are inherently suited to the relevant spatial and temporal coding. In simulations of an interval estimation task, we use a generic local-circuit model to encode time by ‘climbing’ activity, seen in cortex during tasks with a timing requirement. The model is a network of simulated pyramidal cells and inhibitory interneurons, connected by conductance synapses. A simple learning rule enables the network to quickly produce new interval estimates, which show signature characteristics of estimates by experimental subjects. Analysis of network dynamics formally characterizes this generic, local-circuit timing mechanism. In simulations of a perceptual decision task, we couple two such networks. Network function is determined only by spatial selectivity and NMDA receptor conductance strength; all other parameters are identical. To trade speed and accuracy, the timing network simply learns longer or shorter intervals, driving the rate of downstream decision processing by spatially non-selective input, an established form of gain modulation. Like the timing network's interval estimates, decision times show signature characteristics of those by experimental subjects. Overall, we propose, demonstrate and analyse a generic mechanism for timing, a generic mechanism for modulation of decision processing by temporal codes, and we make predictions for experimental verification. PMID:23592967

High resolution digital delay timer

DOEpatents

Martin, Albert D.

1988-01-01

Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay (20) provides a first output signal (24) at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits (26, 28) latch the high resolution data (24) to form a first synchronizing data set (60). A selected time interval has been preset to internal counters (142, 146, 154) and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses (32, 34) count down the counters to generate an internal pulse delayed by an interval which is functionally related to the preset time interval. A second LCD (184) corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD (74) to generate a second set of synchronizing data (76) which is complementary with the first set of synchronizing data (60) for presentation to logic circuits (64). The logic circuits (64) further delay the internal output signal (72) to obtain a proper phase relationship of an output signal (80) with the internal pulses (32, 34). The final delayed output signal (80) thereafter enables the output pulse generator (82) to produce the desired output pulse (84) at the preset time delay interval following input of the trigger pulse (10, 12).

TOFPET 2: A high-performance circuit for PET time-of-flight

NASA Astrophysics Data System (ADS)

Di Francesco, Agostino; Bugalho, Ricardo; Oliveira, Luis; Rivetti, Angelo; Rolo, Manuel; Silva, Jose C.; Varela, Joao

2016-07-01

We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.

System for a displaying at a remote station data generated at a central station and for powering the remote station from the central station

NASA Technical Reports Server (NTRS)

Perry, J. C. (Inventor)

1980-01-01

A system for displaying at a remote station data generated at a central station and for powering the remote station from the central station is presented. A power signal is generated at the central station and time multiplexed with the data and then transmitted to the remote station. An energy storage device at the remote station is responsive to the transmitted power signal to provide energizing power for the circuits at the remote station during the time interval data is being transmitted to the remote station. Energizing power for the circuits at the remote station is provided by the power signal itself during the time this signal is transmitted. Preferably the energy storage device is a capacitor which is charged by the power signal during the time the power is transmitted and is slightly discharged during the time the data is transmitted to energize the circuits at the remote station.

Facile fabrication of networked patterns and their superior application to realize the virus immobilized networked pattern circuit.

PubMed

Choi, Kyung Min; Lee, Seok Jae; Choi, Jung Hoon; Park, Tae Jung; Park, Jong Wan; Shin, Weon Ho; Kang, Jeung Ku

2010-12-07

A facile route to fabricate a protein-immobilized network pattern circuit for rapid and highly sensitive diagnosis was developed via the evaporation directed impromptu patterning method and selective avian influenza virus (AIV) immobilization. The response to the 10 fg mL(-1) anti-AI antibody demonstrates that this easy and simple circuit has about 1000 times higher sensitivity compared to those of conventional approaches.

Operational Characteristics of an SCR-Based Pulse Generating Circuit

DTIC Science & Technology

2014-12-01

of OUTC can further be explained by the RC time constants involved in the charging and discharging of OUTC during each pulse . When the SCR is...CHARACTERISTICS OF AN SCR-BASED PULSE GENERATING CIRCUIT by Wing Chien Christopher Chang December 2014 Thesis Advisor: Gamani Karunasiri Co...COVERED December 20 14 Master ’s Thesis 4. TITLE AND SUBTITLE 5. FUNDING NUMBERS OPERATIONAL CHARACTERISTICS OF AN SCR-BASED PULSE GENERATING CIRCUIT 6

Potential drug sequestration during extracorporeal membrane oxygenation: results from an ex vivo experiment.

PubMed

Mehta, Nilesh M; Halwick, David R; Dodson, Brenda L; Thompson, John E; Arnold, John H

2007-06-01

Using an ex vivo simulation model we set out to estimate the amount of drug lost due to sequestration within the extracorporeal circuit over time. Simulated closed-loop extracorporeal membrane oxygenation (ECMO) circuits were prepared using a 1.5-m2 silicone membrane oxygenator. Group A consisted of heparin, dopamine, ampicillin, vancomycin, phenobarbital and fentanyl. Group B consisted of epinephrine, cefazolin, hydrocortisone, fosphenytoin and morphine. Drugs were tested in crystalloid and blood-primed circuits. After administration of a one-time dose of drugs in the priming fluid, baseline drug concentrations were obtained (P0). A simultaneous specimen was stored for stability testing at 24 h (P4). Serial post-membrane drug concentrations were then obtained at 30 min (P1), 3 h (P2) and 24 h (P3) from circuit fluid. One hundred and one samples were analyzed. At the end of 24 h in crystalloid-primed circuits, 71.8% of ampicillin, 96.7% of epinephrine, 17.6% of fosphenytoin, 33.3% of heparin, 17.5% of morphine and 87% of fentanyl was lost. At the end of 24 h in blood-primed extracorporeal circuits, 15.4% of ampicillin, 21% of cefazolin, 71% of voriconazole, 31.4% of fosphenytoin, 53.3% of heparin and 100% of fentanyl was lost. There was a significant decrease in overall drug concentrations from 30 min to 24 h for both crystalloid-primed circuits (p = 0.023) and blood-primed circuits (p = 0.04). Our ex vivo study demonstrates serial losses of several drugs commonly used during ECMO therapy. Therapeutic concentrations of fentanyl, voriconazole, antimicrobials and heparin cannot be guaranteed in patients on ECMO.

Experimental Validation of Lightning-Induced Electromagnetic (Indirect) Coupling to Short Monopole Antennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crull, E W; Brown Jr., C G; Perkins, M P

2008-07-30

For short monopoles in this low-power case, it has been shown that a simple circuit model is capable of accurate predictions for the shape and magnitude of the antenna response to lightning-generated electric field coupling effects, provided that the elements of the circuit model have accurate values. Numerical EM simulation can be used to provide more accurate values for the circuit elements than the simple analytical formulas, since the analytical formulas are used outside of their region of validity. However, even with the approximate analytical formulas the simple circuit model produces reasonable results, which would improve if more accurate analyticalmore » models were used. This report discusses the coupling analysis approaches taken to understand the interaction between a time-varying EM field and a short monopole antenna, within the context of lightning safety for nuclear weapons at DOE facilities. It describes the validation of a simple circuit model using laboratory study in order to understand the indirect coupling of energy into a part, and the resulting voltage. Results show that in this low-power case, the circuit model predicts peak voltages within approximately 32% using circuit component values obtained from analytical formulas and about 13% using circuit component values obtained from numerical EM simulation. We note that the analytical formulas are used outside of their region of validity. First, the antenna is insulated and not a bare wire and there are perhaps fringing field effects near the termination of the outer conductor that the formula does not take into account. Also, the effective height formula is for a monopole directly over a ground plane, while in the time-domain measurement setup the monopole is elevated above the ground plane by about 1.5-inch (refer to Figure 5).« less

Transnational migration of Mexican scientists: A circuit between Mexico and the EEUU

NASA Astrophysics Data System (ADS)

Tinoco Herrera, Mario Luis

The experience and meaning of migration for a group of Mexican scientists participating in the construction of a migratory circuit between Mexico and US within the field of agricultural sciences is the object of this study. I define this migratory circuit of scientists as a social, historical and cultural process, and draw from transnational migration theories to analyze it. From this perspective, I view the migratory circuit of Mexican scientists to be a field of social relationships extended across Mexico and the US. In studying the migratory experience and its significance, I draw upon the methods of historical reconstruction of the circuit of scientists between Mexico and the US, participatory observation, informal narratives, testimonies and their analysis. This study focuses on three crucial moments of their migratory experience: (1) the moment prior to their trip to the US; (2) their academic training at a research center in the US; and (3) their return to a research center in Mexico. At the same time, this study highlights three key factors that determine and ascribe different meanings to the experiences of this migratory circuit: gender, academic trajectory, and the belonging to a migratory circuit. The findings from this study have shown that the experiences of migration and their multiple meanings are complex, heterogeneous and paradoxical. The complexity lies in the challenges of academic responsibilities and their near total integration and transformation of the participants' social life, as well as family life. These migratory experiences are further differentiated and problematic because of the various perceptions and sense of value that are mediated by gender, academic trajectory, and belonging to a circuit of migration; and, they are paradoxical because even though the experiences, perceptions and meanings are different and, at times, challenging, every single participant has described their experience as positive.

Short-Circuit Fault Detection and Classification Using Empirical Wavelet Transform and Local Energy for Electric Transmission Line.

PubMed

Huang, Nantian; Qi, Jiajin; Li, Fuqing; Yang, Dongfeng; Cai, Guowei; Huang, Guilin; Zheng, Jian; Li, Zhenxin

2017-09-16

In order to improve the classification accuracy of recognizing short-circuit faults in electric transmission lines, a novel detection and diagnosis method based on empirical wavelet transform (EWT) and local energy (LE) is proposed. First, EWT is used to deal with the original short-circuit fault signals from photoelectric voltage transformers, before the amplitude modulated-frequency modulated (AM-FM) mode with a compactly supported Fourier spectrum is extracted. Subsequently, the fault occurrence time is detected according to the modulus maxima of intrinsic mode function (IMF₂) from three-phase voltage signals processed by EWT. After this process, the feature vectors are constructed by calculating the LE of the fundamental frequency based on the three-phase voltage signals of one period after the fault occurred. Finally, the classifier based on support vector machine (SVM) which was constructed with the LE feature vectors is used to classify 10 types of short-circuit fault signals. Compared with complementary ensemble empirical mode decomposition with adaptive noise (CEEMDAN) and improved CEEMDAN methods, the new method using EWT has a better ability to present the frequency in time. The difference in the characteristics of the energy distribution in the time domain between different types of short-circuit faults can be presented by the feature vectors of LE. Together, simulation and real signals experiment demonstrate the validity and effectiveness of the new approach.

Short-Circuit Fault Detection and Classification Using Empirical Wavelet Transform and Local Energy for Electric Transmission Line

PubMed Central

Huang, Nantian; Qi, Jiajin; Li, Fuqing; Yang, Dongfeng; Cai, Guowei; Huang, Guilin; Zheng, Jian; Li, Zhenxin

2017-01-01

In order to improve the classification accuracy of recognizing short-circuit faults in electric transmission lines, a novel detection and diagnosis method based on empirical wavelet transform (EWT) and local energy (LE) is proposed. First, EWT is used to deal with the original short-circuit fault signals from photoelectric voltage transformers, before the amplitude modulated-frequency modulated (AM-FM) mode with a compactly supported Fourier spectrum is extracted. Subsequently, the fault occurrence time is detected according to the modulus maxima of intrinsic mode function (IMF2) from three-phase voltage signals processed by EWT. After this process, the feature vectors are constructed by calculating the LE of the fundamental frequency based on the three-phase voltage signals of one period after the fault occurred. Finally, the classifier based on support vector machine (SVM) which was constructed with the LE feature vectors is used to classify 10 types of short-circuit fault signals. Compared with complementary ensemble empirical mode decomposition with adaptive noise (CEEMDAN) and improved CEEMDAN methods, the new method using EWT has a better ability to present the frequency in time. The difference in the characteristics of the energy distribution in the time domain between different types of short-circuit faults can be presented by the feature vectors of LE. Together, simulation and real signals experiment demonstrate the validity and effectiveness of the new approach. PMID:28926953

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

PubMed Central

Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

Battery Charge Equalizer with Transformer Array

NASA Technical Reports Server (NTRS)

Davies, Francis

2013-01-01

High-power batteries generally consist of a series connection of many cells or cell banks. In order to maintain high performance over battery life, it is desirable to keep the state of charge of all the cell banks equal. A method provides individual charging for battery cells in a large, high-voltage battery array with a minimum number of transformers while maintaining reasonable efficiency. This is designed to augment a simple highcurrent charger that supplies the main charge energy. The innovation will form part of a larger battery charge system. It consists of a transformer array connected to the battery array through rectification and filtering circuits. The transformer array is connected to a drive circuit and a timing and control circuit that allow individual battery cells or cell banks to be charged. The timing circuit and control circuit connect to a charge controller that uses battery instrumentation to determine which battery bank to charge. It is important to note that the innovation can charge an individual cell bank at the same time that the main battery charger is charging the high-voltage battery. The fact that the battery cell banks are at a non-zero voltage, and that they are all at similar voltages, can be used to allow charging of individual cell banks. A set of transformers can be connected with secondary windings in series to make weighted sums of the voltages on the primaries.

Circuit model for single-energy-level trap centers in FETs

NASA Astrophysics Data System (ADS)

Albahrani, Sayed Ali; Parker, Anthony; Heimlich, Michael

2016-12-01

A circuit implementation of a single-energy-level trap center in an FET is presented. When included in transistor models it explains the temperature-potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time-domain and harmonic-balance simulations. The proposed model is based on the Shockley-Read-Hall (SRH) statistics of the trapping process. The results of isothermal pulse measurements performed on a GaN HEMT are presented. These measurement allow characterizing charge trapping in isolation from the effect of self-heating. These results are used to obtain the parameters of the proposed model.

Repeater For A Digital-Communication Bus

NASA Technical Reports Server (NTRS)

Torres-Guzman, Esteban; Olson, Stephen; Heaps, Tim

1993-01-01

Digital repeater circuit designed to extend range of communication on MIL-STD-1553 bus beyond original maximum allowable length of 300 ft. Circuit provides two-way communication, one way at time, and conforms to specifications of MIL-STD-1553. Crosstalk and instability eliminated.

Fault diagnosis for analog circuits utilizing time-frequency features and improved VVRKFA

NASA Astrophysics Data System (ADS)

He, Wei; He, Yigang; Luo, Qiwu; Zhang, Chaolong

2018-04-01

This paper proposes a novel scheme for analog circuit fault diagnosis utilizing features extracted from the time-frequency representations of signals and an improved vector-valued regularized kernel function approximation (VVRKFA). First, the cross-wavelet transform is employed to yield the energy-phase distribution of the fault signals over the time and frequency domain. Since the distribution is high-dimensional, a supervised dimensionality reduction technique—the bilateral 2D linear discriminant analysis—is applied to build a concise feature set from the distributions. Finally, VVRKFA is utilized to locate the fault. In order to improve the classification performance, the quantum-behaved particle swarm optimization technique is employed to gradually tune the learning parameter of the VVRKFA classifier. The experimental results for the analog circuit faults classification have demonstrated that the proposed diagnosis scheme has an advantage over other approaches.

Candle Soot-Driven Performance Enhancement in Pyroelectric Energy Conversion

NASA Astrophysics Data System (ADS)

Azad, Puneet; Singh, V. P.; Vaish, Rahul

2018-05-01

We observed substantial enhancement in pyroelectric output with the help of candle soot coating on the surface of lead zirconate titanate (PZT). Candle soot of varying thicknesses was coated by directly exposing pyroelectric material to the candle flame. The open-circuit pyroelectric voltage and closed-circuit pyroelectric current were recorded while applying infrared heating across the uncoated and candle soot-coated samples for different heating and cooling cycles. In comparison to the uncoated sample, the maximum open-circuit voltage improves seven times for the candle soot-coated sample and electric current increases by eight times across a resistance of 10Å. Moreover, the harvested energy is enhanced by 50 times for candle soot-coated sample. Results indicate that candle soot coating is an effective and economic method to improve infrared sensing performance of pyroelectric materials.

Protection circuits for very high frequency ultrasound systems.

PubMed

Choi, Hojong; Shung, K Kirk

2014-04-01

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (-1.0 dB), THD (-69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications.

Protection Circuits for Very High Frequency Ultrasound Systems

PubMed Central

Shung, K. Kirk

2014-01-01

The purpose of protection circuits in ultrasound applications is to block noise signals from the transmitter from reaching the transducer and also to prevent unwanted high voltage signals from reaching the receiver. The protection circuit using a resistor and diode pair is widely used due to its simple architecture, however, it may not be suitable for very high frequency (VHF) ultrasound transducer applications (>100 MHz) because of its limited bandwidth. Therefore, a protection circuit using MOSFET devices with unique structure is proposed in this paper. The performance of the designed protection circuit was compared with that of other traditional protection schemes. The performance characteristics measured were the insertion loss (IL), total harmonic distortion (THD) and transient response time (TRT). The new protection scheme offers the lowest IL (−1.0 dB), THD (−69.8 dB) and TRT (78 ns) at 120 MHz. The pulse-echo response using a 120 MHz LiNbO3 transducer with each protection circuit was measured to validate the feasibility of the protection circuits in VHF ultrasound applications. The sensitivity and bandwidth of the transducer using the new protection circuit improved by 252.1 and 50.9 %, respectively with respect to the protection circuit using a resistor and diode pair. These results demonstrated that the new protection circuit design minimizes the IL, THD and TRT for VHF ultrasound transducer applications. PMID:24682684

DOE Office of Scientific and Technical Information (OSTI.GOV)

Silva, E.R.C. da; Filho, B.J.C.

This paper presents a PWM current clamping circuit for improving a series resonant DC link converter. This circuit is capable of reducing current peaks to about 1.2--1.4 times the DC bias current. When desired, resonant transition creates notches in the dc link current, allowing the converter`s switches to synchronize with external PWM strategy. A regulated DC current source may be obtained--by using a conventional rectifier source--to feed a DC load or a current source inverter. Phase plane approach makes ease the understanding the operation, control and design procedure of the circuit. Another topology is derived and its features compared tomore » the first circuit. Simulation results for the simplified circuit and for a three-phase induction motor driven by such inverter will be presented. Moreover, the principle is corroborated by experimental results.« less

STICAP: A linear circuit analysis program with stiff systems capability. Volume 1: Theory manual. [network analysis

NASA Technical Reports Server (NTRS)

Cooke, C. H.

1975-01-01

STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.

Design and application of cotranscriptional non-enzymatic RNA circuits and signal transducers

PubMed Central

Bhadra, Sanchita; Ellington, Andrew D.

2014-01-01

Nucleic acid circuits are finding increasing real-life applications in diagnostics and synthetic biology. Although DNA has been the main operator in most nucleic acid circuits, transcriptionally produced RNA circuits could provide powerful alternatives for reagent production and their use in cells. Towards these goals, we have implemented a particular nucleic acid circuit, catalytic hairpin assembly, using RNA for both information storage and processing. Our results demonstrated that the design principles developed for DNA circuits could be readily translated to engineering RNA circuits that operated with similar kinetics and sensitivities of detection. Not only could purified RNA hairpins perform amplification reactions but RNA hairpins transcribed in vitro also mediated amplification, even without purification. Moreover, we could read the results of the non-enzymatic amplification reactions using a fluorescent RNA aptamer ‘Spinach’ that was engineered to undergo sequence-specific conformational changes. These advances were applied to the end-point and real-time detection of the isothermal strand displacement amplification reaction that produces single-stranded DNAs as part of its amplification cycle. We were also able to readily engineer gate structures with RNA similar to those that have previously formed the basis of DNA circuit computations. Taken together, these results validate an entirely new chemistry for the implementation of nucleic acid circuits. PMID:24493736

Ground Isolation Circuit for Isolating a Transmission Line from Ground Interference

NASA Technical Reports Server (NTRS)

Davidson, Craig A. (Inventor)

1996-01-01

This invention relates generally to a system for isolating ground interference from a transmission line, e.g., a ground isolation circuit for isolating a wideband transmission signal (such as a video signal) from ground by modulating the base signal on a carrier signal to permit the transmission signal to be isolated. In one embodiment, the circuit includes a pair of matched mixer circuits, each of which receives a carrier signal from the same oscillator circuit. The first mixer circuit also receives the baseband signal input, after appropriate conditioning, and modulates the baseband signal onto the carrier signal. In a preferred embodiment the carrier signal has a predetermined frequency which is at least two times the frequency of the baseband signal. The modulated signal (which can comprise an rf signal) is transmitted via an rf transmission line to the second mixer, which demodulates the rf signal to recover the baseband signal. Each port of the mixer connects to an isolation transformer to ensure isolation from ground interference. The circuit is considered to be of commercial value in that it can provide isolation between transmitting and receiving circuits, e.g., ground isolation for television circuits or high frequency transmitters, without the need for video transformers or optical isolators, thereby reducing the complexity, power consumption, and weight of the system.

Characteristic and intermingled neocortical circuits encode different visual object discriminations.

PubMed

Zhang, Guo-Rong; Zhao, Hua; Cook, Nathan; Svestka, Michael; Choi, Eui M; Jan, Mary; Cook, Robert G; Geller, Alfred I

2017-07-28

Synaptic plasticity and neural network theories hypothesize that the essential information for advanced cognitive tasks is encoded in specific circuits and neurons within distributed neocortical networks. However, these circuits are incompletely characterized, and we do not know if a specific discrimination is encoded in characteristic circuits among multiple animals. Here, we determined the spatial distribution of active neurons for a circuit that encodes some of the essential information for a cognitive task. We genetically activated protein kinase C pathways in several hundred spatially-grouped glutamatergic and GABAergic neurons in rat postrhinal cortex, a multimodal associative area that is part of a distributed circuit that encodes visual object discriminations. We previously established that this intervention enhances accuracy for specific discriminations. Moreover, the genetically-modified, local circuit in POR cortex encodes some of the essential information, and this local circuit is preferentially activated during performance, as shown by activity-dependent gene imaging. Here, we mapped the positions of the active neurons, which revealed that two image sets are encoded in characteristic and different circuits. While characteristic circuits are known to process sensory information, in sensory areas, this is the first demonstration that characteristic circuits encode specific discriminations, in a multimodal associative area. Further, the circuits encoding the two image sets are intermingled, and likely overlapping, enabling efficient encoding. Consistent with reconsolidation theories, intermingled and overlapping encoding could facilitate formation of associations between related discriminations, including visually similar discriminations or discriminations learned at the same time or place. Copyright © 2017 Elsevier B.V. All rights reserved.

HEMT Amplifiers and Equipment for their On-Wafer Testing

NASA Technical Reports Server (NTRS)

Fung, King man; Gaier, Todd; Samoska, Lorene; Deal, William; Radisic, Vesna; Mei, Xiaobing; Lai, Richard

2008-01-01

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

DC isolation and protection system and circuit

NASA Technical Reports Server (NTRS)

Wagner, Charles A. (Inventor); Kellogg, Gary V. (Inventor)

1991-01-01

A precision analog electronic circuit that is capable of sending accurate signals to an external device that has hostile electric characteristics, including the presence of very large common mode voltages. The circuit is also capable of surviving applications of normal mode overvoltages of up to 120 VAC/VDC for unlimited periods of time without damage or degradation. First, the circuit isolates the DC signal output from the computer. Means are then provided for amplifying the isolated DC signal. Further means are provided for stabilizing and protecting the isolating and amplifying means, and the isolated and amplified DC signal which is output to the external device, against overvoltages and overcurrents.

NbN A/D Conversion of IR Focal Plane Sensor Signal at 10 K

NASA Technical Reports Server (NTRS)

Eaton, L.; Durand, D.; Sandell, R.; Spargo, J.; Krabach, T.

1994-01-01

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.

BLOCKING OSCILLATOR DOUBLE PULSE GENERATOR CIRCUIT

DOEpatents

Haase, J.A.

1961-01-24

A double-pulse generator, particuiarly a double-pulse generator comprising a blocking oscillator utilizing a feedback circuit to provide means for producing a second pulse within the recovery time of the blocking oscillator, is described. The invention utilized a passive network which permits adjustment of the spacing between the original pulses derived from the blocking oscillator and further utilizes the original pulses to trigger a circuit from which other pulses are initiated. These other pulses are delayed and then applied to the input of the blocking oscillator, with the result that the output from the oscillator circuit contains twice the number of pulses originally initiated by the blocking oscillator itself.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

NASA Astrophysics Data System (ADS)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Optimization Methods for Spiking Neurons and Networks

PubMed Central

Russell, Alexander; Orchard, Garrick; Dong, Yi; Mihalaş, Ştefan; Niebur, Ernst; Tapson, Jonathan; Etienne-Cummings, Ralph

2011-01-01

Spiking neurons and spiking neural circuits are finding uses in a multitude of tasks such as robotic locomotion control, neuroprosthetics, visual sensory processing, and audition. The desired neural output is achieved through the use of complex neuron models, or by combining multiple simple neurons into a network. In either case, a means for configuring the neuron or neural circuit is required. Manual manipulation of parameters is both time consuming and non-intuitive due to the nonlinear relationship between parameters and the neuron’s output. The complexity rises even further as the neurons are networked and the systems often become mathematically intractable. In large circuits, the desired behavior and timing of action potential trains may be known but the timing of the individual action potentials is unknown and unimportant, whereas in single neuron systems the timing of individual action potentials is critical. In this paper, we automate the process of finding parameters. To configure a single neuron we derive a maximum likelihood method for configuring a neuron model, specifically the Mihalas–Niebur Neuron. Similarly, to configure neural circuits, we show how we use genetic algorithms (GAs) to configure parameters for a network of simple integrate and fire with adaptation neurons. The GA approach is demonstrated both in software simulation and hardware implementation on a reconfigurable custom very large scale integration chip. PMID:20959265

Speed-Up Techniques for Complementary Metal Oxide Semiconductor Very Large Scale Integration.

DTIC Science & Technology

1984-12-14

The input voltage at which the two transistors are in the constant current region at the same time marks the active operating region of the inverter...decoder precharge configurations. One circuit displayed a marked enhancement in operation while the other precharged circuit displyed degraded operation due...34 IEEE Journal of Solid State Circuits, SC-18: 457-462 (October 1983). 19. Cobbold , R. Theory and Applications of Field Effect Transistors, New York: John

Direct Digital Boiler Control Systems for the Navy Small Boiler Equipment.

DTIC Science & Technology

1983-02-01

Hardware. Each full-size ACU a 6 caculation modules 30 arrme, modufes sation for dead time lag contains input/output circuit a 16 control mo uies a...along with lather modules of the DCS-1000 family. ’The complete instrument consists of plug-in circuit boards that allow easy Teplacement of a...Maintenance-Most systems indicate trouble areas with diagnostic routines or integral LED indicators so that circuit boards can be replaced to correct

Adaptable Transponder for Multiple Telemetry Systems

NASA Technical Reports Server (NTRS)

Sims, William Herbert, III (Inventor); Varnavas, Kosta A. (Inventor)

2014-01-01

The present invention is a stackable telemetry circuit board for use in telemetry systems for satellites and other purposes. The present invention incorporates previously-qualified interchangeable circuit boards, or "decks," that perform functions such as power, signal receiving and transmission, and processing. Each deck is adapted to serve a range of telemetry applications. This provides flexibility in the construction of the stackable telemetry circuit board and significantly reduces the cost and time necessary to develop a telemetry system.

Mouse Visual Neocortex Supports Multiple Stereotyped Patterns of Microcircuit Activity

PubMed Central

Sadovsky, Alexander J.

2014-01-01

Spiking correlations between neocortical neurons provide insight into the underlying synaptic connectivity that defines cortical microcircuitry. Here, using two-photon calcium fluorescence imaging, we observed the simultaneous dynamics of hundreds of neurons in slices of mouse primary visual cortex (V1). Consistent with a balance of excitation and inhibition, V1 dynamics were characterized by a linear scaling between firing rate and circuit size. Using lagged firing correlations between neurons, we generated functional wiring diagrams to evaluate the topological features of V1 microcircuitry. We found that circuit connectivity exhibited both cyclic graph motifs, indicating recurrent wiring, and acyclic graph motifs, indicating feedforward wiring. After overlaying the functional wiring diagrams onto the imaged field of view, we found properties consistent with Rentian scaling: wiring diagrams were topologically efficient because they minimized wiring with a modular architecture. Within single imaged fields of view, V1 contained multiple discrete circuits that were overlapping and highly interdigitated but were still distinct from one another. The majority of neurons that were shared between circuits displayed peri-event spiking activity whose timing was specific to the active circuit, whereas spike times for a smaller percentage of neurons were invariant to circuit identity. These data provide evidence that V1 microcircuitry exhibits balanced dynamics, is efficiently arranged in anatomical space, and is capable of supporting a diversity of multineuron spike firing patterns from overlapping sets of neurons. PMID:24899701

Monostable circuit with tunnel diode has fast recovery

NASA Technical Reports Server (NTRS)

Heffner, P.

1964-01-01

A monostable multivibrator circuit using a tunnel diode makes it possible for the MSMV to exceed the performance of present multivibrators in two respects. The rise time of the output voltage is faster and the duty cycle is raised to approximately 95 percent.

Developmental metaplasticity in neural circuit codes of firing and structure.

PubMed

Baram, Yoram

2017-01-01

Firing-rate dynamics have been hypothesized to mediate inter-neural information transfer in the brain. While the Hebbian paradigm, relating learning and memory to firing activity, has put synaptic efficacy variation at the center of cortical plasticity, we suggest that the external expression of plasticity by changes in the firing-rate dynamics represents a more general notion of plasticity. Hypothesizing that time constants of plasticity and firing dynamics increase with age, and employing the filtering property of the neuron, we obtain the elementary code of global attractors associated with the firing-rate dynamics in each developmental stage. We define a neural circuit connectivity code as an indivisible set of circuit structures generated by membrane and synapse activation and silencing. Synchronous firing patterns under parameter uniformity, and asynchronous circuit firing are shown to be driven, respectively, by membrane and synapse silencing and reactivation, and maintained by the neuronal filtering property. Analytic, graphical and simulation representation of the discrete iteration maps and of the global attractor codes of neural firing rate are found to be consistent with previous empirical neurobiological findings, which have lacked, however, a specific correspondence between firing modes, time constants, circuit connectivity and cortical developmental stages. Copyright © 2016 Elsevier Ltd. All rights reserved.

Using of explosive technologies for development of a compact current-limiting device for operation on 110 kV class systems

NASA Astrophysics Data System (ADS)

Shurupov, A. V.; Shurupov, M. A.; Kozlov, A. A.; Kotov, A. V.

2016-11-01

This paper considers the possibility of creating on new physical principles a highspeed current-limiting device (CLD) for the networks with voltage of 110 kV, namely, on the basis of the explosive switching elements. The device is designed to limit the steady short-circuit current to acceptable values for the time does not exceed 3 ms at electric power facilities. The paper presents an analysis of the electrical circuit of CLD. The main features of the scheme are: a new high-speed switching element with high regenerating voltage; fusible switching element that enables to limit the overvoltage after sudden breakage of network of the explosive switch; non-inductive resistor with a high heat capacity and a special reactor with operating time less than 1 s. We analyzed the work of the CLD with help of special software PSPICE, which is based on the equivalent circuit of single-phase short circuit to ground in 110 kV network. Analysis of the equivalent circuit operation CLD shows its efficiency and determines the CLD as a perspective direction of the current-limiting devices of new generation.

The time-course of red blood cell intracellular pH recovery following short-circuiting in relation to venous transit times in rainbow trout, Oncorhynchus mykiss.

PubMed

Harter, Till Sebastian; May, Alexandra G; Federspiel, William J; Supuran, Claudiu T; Brauner, Colin J

2018-04-11

Accumulating evidence is highlighting the importance of a system of enhanced hemoglobin-oxygen (Hb-O 2 ) unloading for cardiovascular O 2 transport in teleosts. Adrenergically stimulated sodium-proton-exchangers (β-NHE) create H + gradients across the red blood cell (RBC) membrane that are short-circuited in the presence of plasma-accessible carbonic anhydrase (paCA) at the tissues; the result is a large arterial-venous pH shift that greatly enhances O 2 unloading from pH-sensitive Hb. However, RBC intracellular pH (pH i ) must recover during venous transit (31-90 s), to enable O 2 -loading at the gills. The halftimes (t 1/2 ) and magnitudes of RBC β-adrenergic stimulation, short-circuiting with paCA and recovery of RBC pH i , were assessed in vitro, on rainbow trout whole blood, and using changes in closed-system PO 2 as a sensitive indicator for changes in RBC pH i . In addition, the recovery rate of RBC pH i was assessed in a continuous-flow apparatus that more closely mimics RBC transit though the circulation. Results indicate that: i) the t 1/2 of CA short-circuiting is likely within the residence time of blood in the capillaries; ii) the t 1/2 of RBC pH i recovery is 17 s and within the time of RBC venous transit; and iii) after short-circuiting RBCs re-establish the initial H + gradient across the membrane and can potentially undergo repeated cycles of short-circuiting and recovery. Thus, teleosts have evolved a system that greatly enhances O 2 unloading from pH-sensitive Hb at the tissues, while protecting O 2 loading at the gills; the resulting increase in O 2 transport per unit of blood flow may enable the tremendous athletic ability of salmonids.

A Circuit Model of Real Time Human Body Hydration.

PubMed

Asogwa, Clement Ogugua; Teshome, Assefa K; Collins, Stephen F; Lai, Daniel T H

2016-06-01

Changes in human body hydration leading to excess fluid losses or overload affects the body fluid's ability to provide the necessary support for healthy living. We propose a time-dependent circuit model of real-time human body hydration, which models the human body tissue as a signal transmission medium. The circuit model predicts the attenuation of a propagating electrical signal. Hydration rates are modeled by a time constant τ, which characterizes the individual specific metabolic function of the body part measured. We define a surrogate human body anthropometric parameter θ by the muscle-fat ratio and comparing it with the body mass index (BMI), we find theoretically, the rate of hydration varying from 1.73 dB/min, for high θ and low τ to 0.05 dB/min for low θ and high τ. We compare these theoretical values with empirical measurements and show that real-time changes in human body hydration can be observed by measuring signal attenuation. We took empirical measurements using a vector network analyzer and obtained different hydration rates for various BMI, ranging from 0.6 dB/min for 22.7 [Formula: see text] down to 0.04 dB/min for 41.2 [Formula: see text]. We conclude that the galvanic coupling circuit model can predict changes in the volume of the body fluid, which are essential in diagnosing and monitoring treatment of body fluid disorder. Individuals with high BMI would have higher time-dependent biological characteristic, lower metabolic rate, and lower rate of hydration.

Circuit design for the retina-like image sensor based on space-variant lens array

NASA Astrophysics Data System (ADS)

Gao, Hongxun; Hao, Qun; Jin, Xuefeng; Cao, Jie; Liu, Yue; Song, Yong; Fan, Fan

2013-12-01

Retina-like image sensor is based on the non-uniformity of the human eyes and the log-polar coordinate theory. It has advantages of high-quality data compression and redundant information elimination. However, retina-like image sensors based on the CMOS craft have drawbacks such as high cost, low sensitivity and signal outputting efficiency and updating inconvenience. Therefore, this paper proposes a retina-like image sensor based on space-variant lens array, focusing on the circuit design to provide circuit support to the whole system. The circuit includes the following parts: (1) A photo-detector array with a lens array to convert optical signals to electrical signals; (2) a strobe circuit for time-gating of the pixels and parallel paths for high-speed transmission of the data; (3) a high-precision digital potentiometer for the I-V conversion, ratio normalization and sensitivity adjustment, a programmable gain amplifier for automatic generation control(AGC), and a A/D converter for the A/D conversion in every path; (4) the digital data is displayed on LCD and stored temporarily in DDR2 SDRAM; (5) a USB port to transfer the data to PC; (6) the whole system is controlled by FPGA. This circuit has advantages as lower cost, larger pixels, updating convenience and higher signal outputting efficiency. Experiments have proved that the grayscale output of every pixel basically matches the target and a non-uniform image of the target is ideally achieved in real time. The circuit can provide adequate technical support to retina-like image sensors based on space-variant lens array.

Global Electric Circuit Diurnal Variation Derived from Storm Overflight and Satellite Optical Lightning Datasets

NASA Technical Reports Server (NTRS)

Mach, Douglas M.; Blakeslee, R. J.; Bateman, M. J.; Bailey, J. C.

2011-01-01

We have combined analyses of over 1000 high altitude aircraft observations of electrified clouds with diurnal lightning statistics from the Lightning Imaging Sensor (LIS) and Optical Transient Detector (OTD) to produce an estimate of the diurnal variation in the global electric circuit. Using basic assumptions about the mean storm currents as a function of flash rate and location, and the global electric circuit, our estimate of the current in the global electric circuit matches the Carnegie curve diurnal variation to within 4% for all but two short periods of time. The agreement with the Carnegie curve was obtained without any tuning or adjustment of the satellite or aircraft data. Mean contributions to the global electric circuit from land and ocean thunderstorms are 1.1 kA (land) and 0.7 kA (ocean). Contributions to the global electric circuit from ESCs are 0.22 kA for ocean storms and 0.04 kA for land storms. Using our analysis, the mean total conduction current for the global electric circuit is 2.0 kA.

Capillarics: pre-programmed, self-powered microfluidic circuits built from capillary elements.

PubMed

Safavieh, Roozbeh; Juncker, David

2013-11-07

Microfluidic capillary systems employ surface tension effects to manipulate liquids, and are thus self-powered and self-regulated as liquid handling is structurally and chemically encoded in microscale conduits. However, capillary systems have been limited to perform simple fluidic operations. Here, we introduce complex capillary flow circuits that encode sequential flow of multiple liquids with distinct flow rates and flow reversal. We first introduce two novel microfluidic capillary elements including (i) retention burst valves and (ii) robust low aspect ratio trigger valves. These elements are combined with flow resistors, capillary retention valves, capillary pumps, and open and closed reservoirs to build a capillary circuit that, following sample addition, autonomously delivers a defined sequence of multiple chemicals according to a preprogrammed and predetermined flow rate and time. Such a circuit was used to measure the concentration of C-reactive protein. This work illustrates that as in electronics, complex capillary circuits may be built by combining simple capillary elements. We define such circuits as "capillarics", and introduce symbolic representations. We believe that more complex circuits will become possible by expanding the library of building elements and formulating abstract design rules.

Zero-crossing detector with sub-microsecond jitter and crosstalk

NASA Technical Reports Server (NTRS)

Dick, G. John; Kuhnle, Paul F.; Sydnor, Richard L.

1990-01-01

A zero-crossing detector (ZCD) was built and tested with a new circuit design which gives reduced time jitter compared to previous designs. With the new design, time jitter is reduced for the first time to a value which approaches that due to noise in the input amplifying stage. Additionally, with fiber-optic transmission of the output signal, crosstalk between units has been eliminated. The measured values are in good agreement with circuit noise calculations and approximately ten times lower than that for ZCD's presently installed in the JPL test facility. Crosstalk between adjacent units was reduced even more than the jitter.

New Methods for Understanding Systems Consolidation

ERIC Educational Resources Information Center

Tayler, Kaycie K.; Wiltgen, Brian J.

2013-01-01

According to the standard model of systems consolidation (SMC), neocortical circuits are reactivated during the retrieval of declarative memories. This process initially requires the hippocampus. However, with the passage of time, neocortical circuits become strengthened and can eventually retrieve memory without input from the hippocampus.…

Dual redundant core memory systems

NASA Technical Reports Server (NTRS)

Hull, F. E.

1972-01-01

Electronic memory system consisting of series redundant drive switch circuits, triple redundant majority voted memory timing functions, and two data registers to provide functional dual redundancy is described. Signal flow through the circuits is illustrated and equence of events which occur within the memory system is explained.

Driver Circuit For High-Power MOSFET's

NASA Technical Reports Server (NTRS)

Letzer, Kevin A.

1991-01-01

Driver circuit generates rapid-voltage-transition pulses needed to switch high-power metal oxide/semiconductor field-effect transistor (MOSFET) modules rapidly between full "on" and full "off". Rapid switching reduces time of overlap between appreciable current through and appreciable voltage across such modules, thereby increasing power efficiency.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wong, Melissa; Bolovan-Fritts, Cynthia; Dar, Roy D.

Signal transduction circuits have long been known to differentiate between signals by amplifying inputs to different levels. Here, we describe a novel transcriptional circuitry that dynamically converts greater input levels into faster rates, without increasing the final equilibrium level (i.e. a rate amplifier). We utilize time-lapse microscopy to study human herpesvirus (cytomegalovirus) infection of live cells in real time. Strikingly, our results show that transcriptional activators accelerate viral gene expression in single cells without amplifying the steady-state levels of gene products in these cells. Experiment and modeling show that rate amplification operates by dynamically manipulating the traditional gain-bandwidth feedback relationshipmore » from electrical circuit theory to convert greater input levels into faster rates, and is driven by highly self-cooperative transcriptional feedback encoded by the virus s essential transactivator, IE2. This transcriptional rate-amplifier provides a significant fitness advantage for the virus and for minimal synthetic circuits. In general, rate-amplifiers may provide a mechanism for signal-transduction circuits to respond quickly to external signals without increasing steady-state levels of potentially cytotoxic molecules.« less

Theoretical investigation of dielectric corona pre-ionization TEA nitrogen laser based on transmission line method

NASA Astrophysics Data System (ADS)

Bahrampour, Alireza; Fallah, Robabeh; Ganjovi, Alireza A.; Bahrampour, Abolfazl

2007-07-01

This paper models the dielectric corona pre-ionization, capacitor transfer type of flat-plane transmission line traveling wave transverse excited atmospheric pressure nitrogen laser by a non-linear lumped RLC electric circuit. The flat-plane transmission line and the pre-ionizer dielectric are modeled by a lumped linear RLC and time-dependent non-linear RC circuit, respectively. The main discharge region is considered as a time-dependent non-linear RLC circuit where its resistance value is also depends on the radiated pre-ionization ultra violet (UV) intensity. The UV radiation is radiated by the resistance due to the surface plasma on the pre-ionizer dielectric. The theoretical predictions are in a very good agreement with the experimental observations. The electric circuit equations (including the ionization rate equations), the equations of laser levels population densities and propagation equation of laser intensities, are solved numerically. As a result, the effects of pre-ionizer dielectric parameters on the electrical behavior and output laser intensity are obtained.

Spatial gradients and multidimensional dynamics in a neural integrator circuit

PubMed Central

Miri, Andrew; Daie, Kayvon; Arrenberg, Aristides B.; Baier, Herwig; Aksay, Emre; Tank, David W.

2011-01-01

In a neural integrator, the variability and topographical organization of neuronal firing rate persistence can provide information about the circuit’s functional architecture. Here we use optical recording to measure the time constant of decay of persistent firing (“persistence time”) across a population of neurons comprising the larval zebrafish oculomotor velocity-to-position neural integrator. We find extensive persistence time variation (10-fold; coefficients of variation 0.58–1.20) across cells within individual larvae. We also find that the similarity in firing between two neurons decreased as the distance between them increased and that a gradient in persistence time was mapped along the rostrocaudal and dorsoventral axes. This topography is consistent with the emergence of persistence time heterogeneity from a circuit architecture in which nearby neurons are more strongly interconnected than distant ones. Collectively, our results can be accounted for by integrator circuit models characterized by multiple dimensions of slow firing rate dynamics. PMID:21857656

Development of a Converter-Based Transmission Line Emulator with Three-Phase Short-Circuit Fault Emulation Capability

DOE PAGES

Zhang, Shuoting; Liu, Bo; Zheng, Sheng; ...

2018-01-01

A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage source converter (VSC)-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. Here, this paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault statemore » and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.« less

Persistent activity in a recurrent circuit underlies courtship memory in Drosophila.

PubMed

Zhao, Xiaoliang; Lenek, Daniela; Dag, Ugur; Dickson, Barry J; Keleman, Krystyna

2018-01-11

Recurrent connections are thought to be a common feature of the neural circuits that encode memories, but how memories are laid down in such circuits is not fully understood. Here we present evidence that courtship memory in Drosophila relies on the recurrent circuit between mushroom body gamma (MBγ), M6 output, and aSP13 dopaminergic neurons. We demonstrate persistent neuronal activity of aSP13 neurons and show that it transiently potentiates synaptic transmission from MBγ>M6 neurons. M6 neurons in turn provide input to aSP13 neurons, prolonging potentiation of MB γ >M6 synapses over time periods that match short-term memory. These data support a model in which persistent aSP13 activity within a recurrent circuit lays the foundation for a short-term memory. © 2018, Zhao et al.

Photomultiplier circuit including means for rapidly reducing the sensitivity thereof. [and protection from radiation damage

NASA Technical Reports Server (NTRS)

Mcclenahan, J. O. (Inventor)

1974-01-01

A simple, reliable and inexpensive control circuit is described for rapidly reducing the bias voltage across one or more of the dynode stages of a photomultiplier, to substantially decrease its sensitivity to incoming light at those times where excess light intensity might damage the tube. The control circuit comprises a switching device, such as a silicon controlled rectifier (SCR), coupled between a pair of the electrodes in the tube, preferably the cathode and first dynode, or the first and second dynodes, the switching device operating in response to a trigger pulse applied to its gate to short circuit the two electrodes. To insure the desired reduction in sensitivity, two switching stages, the devices be employed between two of the electrode stages, the devices being operated simultaneously to short circuit both stages.

Identifying behavioral circuits in Drosophila melanogaster: moving targets in a flying insect.

PubMed

Griffith, Leslie C

2012-08-01

Drosophila melanogaster has historically been the premier model system for understanding the molecular and genetic bases of complex behaviors. In the last decade technical advances, in the form of new genetic tools and electrophysiological and optical methods, have allowed investigators to begin to dissect the neuronal circuits that generate behavior in the adult. The blossoming of circuit analysis in this organism has also reinforced our appreciation of the inadequacy of wiring diagrams for specifying complex behavior. Neuromodulation and neuronal plasticity act to reconfigure circuits on both short and long time scales. These processes act on the connectome, providing context by integrating external and internal cues that are relevant for behavioral choices. New approaches in the fly are providing insight into these basic principles of circuit function. Copyright © 2012 Elsevier Ltd. All rights reserved.

Development of a Converter-Based Transmission Line Emulator with Three-Phase Short-Circuit Fault Emulation Capability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Shuoting; Liu, Bo; Zheng, Sheng

A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage source converter (VSC)-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. Here, this paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault statemore » and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.« less

Persistent activity in a recurrent circuit underlies courtship memory in Drosophila

PubMed Central

Zhao, Xiaoliang; Lenek, Daniela; Dag, Ugur; Dickson, Barry J

2018-01-01

Recurrent connections are thought to be a common feature of the neural circuits that encode memories, but how memories are laid down in such circuits is not fully understood. Here we present evidence that courtship memory in Drosophila relies on the recurrent circuit between mushroom body gamma (MBγ), M6 output, and aSP13 dopaminergic neurons. We demonstrate persistent neuronal activity of aSP13 neurons and show that it transiently potentiates synaptic transmission from MBγ>M6 neurons. M6 neurons in turn provide input to aSP13 neurons, prolonging potentiation of MBγ>M6 synapses over time periods that match short-term memory. These data support a model in which persistent aSP13 activity within a recurrent circuit lays the foundation for a short-term memory. PMID:29322941

A neuromorphic circuit mimicking biological short-term memory.

PubMed

Barzegarjalali, Saeid; Parker, Alice C

2016-08-01

Research shows that the way we remember things for a few seconds is a different mechanism from the way we remember things for a longer time. Short-term memory is based on persistently firing neurons, whereas storing information for a longer time is based on strengthening the synapses or even forming new neural connections. Information about location and appearance of an object is segregated and processed by separate neurons. Furthermore neurons can continue firing using different mechanisms. Here, we have designed a biomimetic neuromorphic circuit that mimics short-term memory by firing neurons, using biological mechanisms to remember location and shape of an object. Our neuromorphic circuit has a hybrid architecture. Neurons are designed with CMOS 45nm technology and synapses are designed with carbon nanotubes (CNT).

Investigation of Fully Three-Dimensional Helical RF Field Effects on TWT Beam/Circuit Interaction

NASA Technical Reports Server (NTRS)

Kory, Carol L.

2000-01-01

A fully three-dimensional (3D), time-dependent, helical traveling wave-tube (TWT) interaction model has been developed using the electromagnetic particle-in-cell (PIC) code MAFIA. The model includes a short section of helical slow-wave circuit with excitation fed by RF input/output couplers, and electron beam contained by periodic permanent magnet (PPM) focusing. All components of the model are simulated in three dimensions allowing the effects of the fully 3D helical fields on RF circuit/beam interaction to be investigated for the first time. The development of the interaction model is presented, and predicted TWT performance using 2.5D and 3D models is compared to investigate the effect of conventional approximations used in TWT analyses.

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

PubMed

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

Control Circuit For Two Stepping Motors

NASA Technical Reports Server (NTRS)

Ratliff, Roger; Rehmann, Kenneth; Backus, Charles

1990-01-01

Control circuit operates two independent stepping motors, one at a time. Provides following operating features: After selected motor stepped to chosen position, power turned off to reduce dissipation; Includes two up/down counters that remember at which one of eight steps each motor set. For selected motor, step indicated by illumination of one of eight light-emitting diodes (LED's) in ring; Selected motor advanced one step at time or repeatedly at rate controlled; Motor current - 30 mA at 90 degree positions, 60 mA at 45 degree positions - indicated by high or low intensity of LED that serves as motor-current monitor; Power-on reset feature provides trouble-free starts; To maintain synchronism between control circuit and motors, stepping of counters inhibited when motor power turned off.

33 Years of Continuous Solar Radio Flux Observations

NASA Astrophysics Data System (ADS)

Monstein, Christian

2015-10-01

In 1982, after development and testing of several analog receiver concepts, I started continuous solar radio flux observations at 230 MHz. My instruments for the observations were based on cheap commercial components out of consumer TV electronics. The main components included a TV-tuner (at that time analog), intermediate frequency (IF) amplifier and video-detector taken from used TV sets. The 5.5 MHz wide video signal was fed into an integrating circuit, in fact a low pass filter, followed by dc-offset circuit and dc-amplifier built with four ua741 and CA3140 operational amplifier integrated circuits. At that time the signal was recorded with a Heathkit stripchart recorder and ink pen; an example is shown in figure 1.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

A Formal Algorithm for Routing Traces on a Printed Circuit Board

NASA Technical Reports Server (NTRS)

Hedgley, David R., Jr.

1996-01-01

This paper addresses the classical problem of printed circuit board routing: that is, the problem of automatic routing by a computer other than by brute force that causes the execution time to grow exponentially as a function of the complexity. Most of the present solutions are either inexpensive but not efficient and fast, or efficient and fast but very costly. Many solutions are proprietary, so not much is written or known about the actual algorithms upon which these solutions are based. This paper presents a formal algorithm for routing traces on a print- ed circuit board. The solution presented is very fast and efficient and for the first time speaks to the question eloquently by way of symbolic statements.

A Basic Research for the Development and Evaluation of Novel MEMS Digital Accelerometers

DTIC Science & Technology

2013-02-01

that timing differences as measured by the circuit are linearly dependent on the measured capacitance changes. As such, the circuit’s readout is...error in the electronic measurement to refine the technique. An additional capability of the circuit is the ability to observe the impact of cold...low resistivity on (ɘ.01 Ω-cm) silicon on insulator wafers (SOI). The beams are fabricated in a 0.3 cm by 0.3 cm die which is then packaged and wire

SHORT PULSE STRETCHER

DOEpatents

Branum, D.R.; Cummins, W.F.

1962-12-01

>A short pulse stretching circuit capable of stretching a short puise to enable it to be displayed on a relatively slow sweeping oscilloscope is described. Moreover, the duration of the pulse is increased by charging a capacitor through a diode and thereafter discharging the capacitor at such time as is desired. In the circuit the trigger pulse alone passes through a delay line, whereas the main signal passes through the diode only, and results in over-all circuit losses which are proportional to the low losses of the diode only. (AEC)

Bridging the Hardware-Software Gap: A Proof Carrying Approach for Computer Systems Trust Evaluation (5.3.5)

DTIC Science & Technology

2017-08-22

has significantly lowered the design cost and shortened the time-to- market (TTM) of Integrated Circuits (ICs) in the electronic industry. Over the...semiconductor companies have focused on high-profit phases such as design, marketing , and sales and have outsourced chip manufacturing, wafer fabrication...supply chain has significantly lowered the design cost and shortened the time- to- market (TTM) of integrated circuits (ICs) in the electronic

RF waveguide phase-directed power combiners

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nantista, Christopher D.; Dolgashev, Valery A.; Tantawi, Sami G.

2017-05-02

High power RF phase-directed power combiners include magic H hybrid and/or superhybrid circuits oriented in orthogonal H-planes and connected using E-plane bends and/or twists to produce compact 3D waveguide circuits, including 8.times.8 and 16.times.16 combiners. Using phase control at the input ports, RF power can be directed to a single output port, enabling fast switching between output ports for applications such as multi-angle radiation therapy.

Superconducting flux flow digital circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.

1993-03-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-[mu]m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps,more » and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic.« less

Simulation of 100-300 GHz solid-state harmonic sources

NASA Technical Reports Server (NTRS)

Zybura, Michael F.; Jones, J. Robert; Jones, Stephen H.; Tait, Gregory B.

1995-01-01

Accurate and efficient simulations of the large-signal time-dependent characteristics of second-harmonic Transferred Electron Oscillators (TEO's) and Heterostructure Barrier Varactor (HBV) frequency triplers have been obtained. This is accomplished by using a novel and efficient harmonic-balance circuit analysis technique which facilitates the integration of physics-based hydrodynamic device simulators. The integrated hydrodynamic device/harmonic-balance circuit simulators allow TEO and HBV circuits to be co-designed from both a device and a circuit point of view. Comparisons have been made with published experimental data for both TEO's and HBV's. For TEO's, excellent correlation has been obtained at 140 GHz and 188 GHz in second-harmonic operation. Excellent correlation has also been obtained for HBV frequency triplers operating near 200 GHz. For HBV's, both a lumped quasi-static equivalent circuit model and the hydrodynamic device simulator have been linked to the harmonic-balance circuit simulator. This comparison illustrates the importance of representing active devices with physics-based numerical device models rather than analytical device models.

Variability-aware double-patterning layout optimization for analog circuits

NASA Astrophysics Data System (ADS)

Li, Yongfu; Perez, Valerio; Tripathi, Vikas; Lee, Zhao Chuan; Tseng, I.-Lun; Ong, Jonathan Yoong Seang

2018-03-01

The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit's mismatch. To overcome the problem and improve the turn-around time, we proposed our smart "anchoring" placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.

Microfluidic Serial Dilution Circuit

PubMed Central

Paegel, Brian M.; Grover, William H.; Skelley, Alison M.; Mathies, Richard A.; Joyce, Gerald F.

2008-01-01

In vitro evolution of RNA molecules requires a method for executing many consecutive serial dilutions. To solve this problem, a microfluidic circuit has been fabricated in a three-layer glass-PDMS-glass device. The 400-nL serial dilution circuit contains five integrated membrane valves: three two-way valves arranged in a loop to drive cyclic mixing of the diluent and carryover, and two bus valves to control fluidic access to the circuit through input and output channels. By varying the valve placement in the circuit, carryover fractions from 0.04 to 0.2 were obtained. Each dilution process, which is comprised of a diluent flush cycle followed by a mixing cycle, is carried out with no pipeting, and a sample volume of 400 nL is sufficient for conducting an arbitrary number of serial dilutions. Mixing is precisely controlled by changing the cyclic pumping rate, with a minimum mixing time of 22 s. This microfluidic circuit is generally applicable for integrating automated serial dilution and sample preparation in almost any microfluidic architecture. PMID:17073422

Design and simulation of the circuit of SWIR hyper-spectral imaging spectrometer

NASA Astrophysics Data System (ADS)

Ren, Bin; Li, Zi-tian; Meng, Nan

2009-07-01

With the requirement of the SWIR Hyper-spectral Imaging Spectrometer, this article describes a project of SWIR image circuit based on IRFPA detector. First, the structure of the SWIR Hyper-spectral Imaging Spectrometer is introduced in this paper, and then the infrared imaging circuit design is proposed, which is based on MCT SWIR FPA with 500*256 pixels, the detector NEPTURN, in Safradir Company. According to the scheme, several key technologies have been studied in particular, such as driving circuit, time control circuit, high-speed A/D converter, LVDS (Low Voltage Differential Signaling) transmission circuit. At last, An improved two-point Correction Method was chosen to correct the Non-uniformity of image. The simulation results demonstrate that the proposed method can effectively suppress noises and work with low power consumption. The electric system not only has the advantages of simplicity and compactness but also can work stably, providing 500×256 image at the frame frequency of 200 Hz in good quality.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sousa, Francisco F. G. de; Rubinger, Rero M.; Sartorelli, José C., E-mail: sartorelli@if.usp.br

We report high-resolution measurements that experimentally confirm a spiral cascade structure and a scaling relationship of shrimps in the Chua's circuit. Circuits constructed using this component allow for a comprehensive characterization of the circuit behaviors through high resolution parameter spaces. To illustrate the power of our technological development for the creation and the study of chaotic circuits, we constructed a Chua circuit and study its high resolution parameter space. The reliability and stability of the designed component allowed us to obtain data for long periods of time (∼21 weeks), a data set from which an accurate estimation of Lyapunov exponentsmore » for the circuit characterization was possible. Moreover, this data, rigorously characterized by the Lyapunov exponents, allows us to reassure experimentally that the shrimps, stable islands embedded in a domain of chaos in the parameter spaces, can be observed in the laboratory. Finally, we confirm that their sizes decay exponentially with the period of the attractor, a result expected to be found in maps of the quadratic family.« less

Plug-and-Play Multicellular Circuits with Time-Dependent Dynamic Responses.

PubMed

Urrios, Arturo; Gonzalez-Flo, Eva; Canadell, David; de Nadal, Eulàlia; Macia, Javier; Posas, Francesc

2018-04-20

Synthetic biology studies aim to develop cellular devices for biomedical applications. These devices, based on living instead of electronic or electromechanic technology, might provide alternative treatments for a wide range of diseases. However, the feasibility of these devices depends, in many cases, on complex genetic circuits that must fulfill physiological requirements. In this work, we explored the potential of multicellular architectures to act as an alternative to complex circuits for implementation of new devices. As a proof of concept, we developed specific circuits for insulin or glucagon production in response to different glucose levels. Here, we show that fundamental features, such as circuit's affinity or sensitivity, are dependent on the specific configuration of the multicellular consortia, providing a method for tuning these properties without genetic engineering. As an example, we have designed and built circuits with an incoherent feed-forward loop architecture (FFL) that can be easily adjusted to generate single pulse responses. Our results might serve as a blueprint for future development of cellular devices for glycemia regulation in diabetic patients.

Systematic Computation of Nonlinear Cellular and Molecular Dynamics with Low-Power CytoMimetic Circuits: A Simulation Study

PubMed Central

Papadimitriou, Konstantinos I.; Stan, Guy-Bart V.; Drakakis, Emmanuel M.

2013-01-01

This paper presents a novel method for the systematic implementation of low-power microelectronic circuits aimed at computing nonlinear cellular and molecular dynamics. The method proposed is based on the Nonlinear Bernoulli Cell Formalism (NBCF), an advanced mathematical framework stemming from the Bernoulli Cell Formalism (BCF) originally exploited for the modular synthesis and analysis of linear, time-invariant, high dynamic range, logarithmic filters. Our approach identifies and exploits the striking similarities existing between the NBCF and coupled nonlinear ordinary differential equations (ODEs) typically appearing in models of naturally encountered biochemical systems. The resulting continuous-time, continuous-value, low-power CytoMimetic electronic circuits succeed in simulating fast and with good accuracy cellular and molecular dynamics. The application of the method is illustrated by synthesising for the first time microelectronic CytoMimetic topologies which simulate successfully: 1) a nonlinear intracellular calcium oscillations model for several Hill coefficient values and 2) a gene-protein regulatory system model. The dynamic behaviours generated by the proposed CytoMimetic circuits are compared and found to be in very good agreement with their biological counterparts. The circuits exploit the exponential law codifying the low-power subthreshold operation regime and have been simulated with realistic parameters from a commercially available CMOS process. They occupy an area of a fraction of a square-millimetre, while consuming between 1 and 12 microwatts of power. Simulations of fabrication-related variability results are also presented. PMID:23393550

What is this chocolate milk in my circuit? A cause of acute clotting of a continuous renal replacement circuit: Questions.

PubMed

Kakajiwala, Aadil; Chiotos, Kathleen; Brothers, Julie; Lederman, April; Amaral, Sandra

2016-12-01

One of the greatest problems associated with continuous renal replacement therapy (CRRT) is the early clotting of filters. A literature search revealed three case reports of lipemic blood causing recurrent clotting and reduced CRRT circuit survival time in adult patients, but no reports of cases in children. A 23-month-old male infant with Martinez-Frias syndrome and multivisceral transplant was admitted to the hospital with severe sepsis and hemolytic anemia. He developed acute kidney injury, fluid overload and electrolyte imbalances requiring CRRT and was also administered total parenteral nutrition (TPN) and fat emulsion. The first circuit lasted 60 h before routine change was required. The second circuit showed acute clotting after only 18 h, and brownish-milky fluid was found in the circuit tubing layered between the clotted blood. The patient's serum triglyceride levels were elevated at 988 mg/dL. The lipid infusion was stopped and CRRT restarted. Serum triglyceride levels improved to 363 mg/dL. The new circuit lasted 63 h before routine change was required. Clotting of CRRT circuits due to elevated triglyceride levels is rare and has not been reported in the pediatric population. Physicians should be mindful of this risk in patients receiving TPN who have unexpected clotting of CRRT circuits.

46 CFR 111.52-3 - Systems below 1500 kilowatts.

Code of Federal Regulations, 2011 CFR

2011-10-01

... Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) ELECTRICAL ENGINEERING ELECTRIC SYSTEMS-GENERAL REQUIREMENTS Calculation of Short-Circuit Currents § 111.52-3 Systems below 1500 kilowatts. The... maximum short-circuit current of a direct current system must be assumed to be 10 times the aggregate...

46 CFR 111.52-3 - Systems below 1500 kilowatts.

Code of Federal Regulations, 2014 CFR

2014-10-01

... Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) ELECTRICAL ENGINEERING ELECTRIC SYSTEMS-GENERAL REQUIREMENTS Calculation of Short-Circuit Currents § 111.52-3 Systems below 1500 kilowatts. The... maximum short-circuit current of a direct current system must be assumed to be 10 times the aggregate...

Fast Clock Recovery for Digital Communications

NASA Technical Reports Server (NTRS)

Tell, R. G.

1985-01-01

Circuit extracts clock signal from random non-return-to-zero data stream, locking onto clock within one bit period at 1-gigabitper-second data rate. Circuit used for synchronization in opticalfiber communications. Derives speed from very short response time of gallium arsenide metal/semiconductor field-effect transistors (MESFET's).

Ferruleless coupled-cavity traveling-wave tube cold-test characteristics simulated with micro-SOS

NASA Technical Reports Server (NTRS)

Schroeder, Dana L.; Wilson, Jeffrey D.

1993-01-01

The three-dimensional, electromagnetic circuit analysis code, Micro-SOS, can be used to reduce expensive and time consuming experimental 'cold-testing' of traveling-wave tube (TWT) circuits. The frequency-phase dispersion and beam interaction impedance characteristics of a ferruleless coupled-cavity traveling-wave tube slow-wave circuit were simulated using the code. Computer results agree closely with experimental data. Variations in the cavity geometry dimensions of period length and gap-to-period ratio were modeled. These variations can be used in velocity taper designs to reduce the radiofrequency (RF) phase velocity in synchronism with the decelerating electron beam. Such circuit designs can result in enhanced TWT power and efficiency.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

NASA Astrophysics Data System (ADS)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

Suppression of Instability of High Pressure DC Microplasma Operating in the Negative Differential Resistance (NDR) Regime

NASA Astrophysics Data System (ADS)

Mahamud, Rajib; Farouk, Tanvir I.

2015-09-01

Microplasma devices have been the subject of considerable interest and research during the last decade. In a DC system most of the operation regime of the plasma discharges studied fall in the ``abnormal,'' ``normal'' and ``corona'' modes - where a quasi-steady state is achieved. It is well known that even in a DC system the negative differential resistance (NDR) regime can trigger self pulsing discharges. These pulsations are initiated by the parasitic capacitance of the system hence governed by the response time of the power circuit. The circuit response time is required to be larger than the ion transit time to initiate the oscillations. In this present study a suppressor circuit element in the form of an inductor is used to restrain the plasma from switching to a self pulsing mode. It has been identified that the combined response time of the inductor and the plasma discharge (L/Rplasma) has to be larger than the power circuit time constant (RC) to achieve suppression. Inhibition of oscillation has been observed in both experiments and numerical simulations. The obtained voltage-current characteristics show that the inductor element extends the normal glow regime to lower current. Additional parametric simulations are conducted to map out a ``stable'' operation regime. The author would like to thank DARPA (ARO Grant No. W911NF1210007) and University of South Carolina (USC) for the financial support of the work.

Healing Voids In Interconnections In Integrated Circuits

NASA Technical Reports Server (NTRS)

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

1989-01-01

Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

DTIC Science & Technology

2016-09-01

design to control the phase shifters was complex, and the calibration process was time consuming. During the redesign process, we carried out...signals in time domain with a maximum sampling frequency of 20 Giga samples per second. In the previous tests of the design , the performance of...PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION by Chew K. Tan

Basic Mechanisms of Radiation Effects on Electronic Materials, Devices, and Integrated Circuits

DTIC Science & Technology

1982-08-01

recovery time versus reciprocal tempera- ture derived from data of the type shown in Figure 18. . . .31 20 Several ways to alter the charje state of...and long-term recovery processes that occUr in neutron-irradiated silicon ........ 40 29 Annealing factor versus time for 11 ohm-cm p-type bulk silicon...radioactive ele- ments (such as uranium and thorium) which, when incorporated in packaged integrated circuits, can cause occasional transient upsets

Wireless Sensing System Using Open-circuit, Electrically-conductive Spiral-trace Sensor

NASA Technical Reports Server (NTRS)

Woodard, Stanley E. (Inventor); Taylor, Bryant D. (Inventor)

2013-01-01

A wireless sensing system includes a sensor made from an electrical conductor shaped to form an open-circuit, electrically-conductive spiral trace having inductance and capacitance. In the presence of a time-varying magnetic field, the sensor resonates to generate a harmonic response having a frequency, amplitude and bandwidth. A magnetic field response recorder wirelessly transmits the time-varying magnetic field to the sensor and wirelessly detects the sensor's response frequency, amplitude and bandwidth.

Directly writing resistor, inductor and capacitor to composite functional circuits: a super-simple way for alternative electronics.

PubMed

Gao, Yunxia; Li, Haiyan; Liu, Jing

2013-01-01

The current strategies for making electronic devices are generally time, water, material and energy consuming. Here, the direct writing of composite functional circuits through comprehensive use of GaIn10-based liquid metal inks and matching material is proposed and investigated, which is a rather easy going and cost effective electronics fabrication way compared with the conventional approaches. Owing to its excellent adhesion and electrical properties, the liquid metal ink was demonstrated as a generalist in directly making various basic electronic components such as planar resistor, inductor and capacitor or their combination and thus composing circuits with expected electrical functions. For a precise control of the geometric sizes of the writing, a mask with a designed pattern was employed and demonstrated. Mechanisms for justifying the chemical components of the inks and the magnitudes of the target electronic elements so as to compose various practical circuits were disclosed. Fundamental tests on the electrical components including capacitor and inductor directly written on paper with working time up to 48 h and elevated temperature demonstrated their good stability and potential widespread adaptability especially when used in some high frequency circuits. As the first proof-of-concept experiment, a typical functional oscillating circuit including an integrated chip of 74HC04 with a supply voltage of 5 V, a capacitor of 10 nF and two resistors of 5 kΩ and 1 kΩ respectively was directly composed on paper through integrating specific electrical elements together, which presented an oscillation frequency of 8.8 kHz. The present method significantly extends the roles of the metal ink in recent works serving as only a single electrical conductor or interconnecting wires. It opens the way for directly writing out complex functional circuits or devices on different substrates. Such circuit composition strategy has generalized purpose and can be extended to more areas, even daily pervasive electronics.

Directly Writing Resistor, Inductor and Capacitor to Composite Functional Circuits: A Super-Simple Way for Alternative Electronics

PubMed Central

Gao, Yunxia; Li, Haiyan; Liu, Jing

2013-01-01

Background The current strategies for making electronic devices are generally time, water, material and energy consuming. Here, the direct writing of composite functional circuits through comprehensive use of GaIn10-based liquid metal inks and matching material is proposed and investigated, which is a rather easy going and cost effective electronics fabrication way compared with the conventional approaches. Methods Owing to its excellent adhesion and electrical properties, the liquid metal ink was demonstrated as a generalist in directly making various basic electronic components such as planar resistor, inductor and capacitor or their combination and thus composing circuits with expected electrical functions. For a precise control of the geometric sizes of the writing, a mask with a designed pattern was employed and demonstrated. Mechanisms for justifying the chemical components of the inks and the magnitudes of the target electronic elements so as to compose various practical circuits were disclosed. Results Fundamental tests on the electrical components including capacitor and inductor directly written on paper with working time up to 48 h and elevated temperature demonstrated their good stability and potential widespread adaptability especially when used in some high frequency circuits. As the first proof-of-concept experiment, a typical functional oscillating circuit including an integrated chip of 74HC04 with a supply voltage of 5 V, a capacitor of 10 nF and two resistors of 5 kΩ and 1 kΩ respectively was directly composed on paper through integrating specific electrical elements together, which presented an oscillation frequency of 8.8 kHz. Conclusions The present method significantly extends the roles of the metal ink in recent works serving as only a single electrical conductor or interconnecting wires. It opens the way for directly writing out complex functional circuits or devices on different substrates. Such circuit composition strategy has generalized purpose and can be extended to more areas, even daily pervasive electronics. PMID:23936349

Magnetophoretic circuits for digital control of single particles and cells

NASA Astrophysics Data System (ADS)

Lim, Byeonghwa; Reddy, Venu; Hu, Xinghao; Kim, Kunwoo; Jadhav, Mital; Abedini-Nassab, Roozbeh; Noh, Young-Woock; Lim, Yong Taik; Yellen, Benjamin B.; Kim, Cheolgi

2014-05-01

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

Maximizing the short circuit current of organic solar cells by partial decoupling of electrical and optical properties

NASA Astrophysics Data System (ADS)

Qarony, Wayesh; Hossain, Mohammad I.; Jovanov, Vladislav; Knipp, Dietmar; Tsang, Yuen Hong

2018-03-01

The partial decoupling of electronic and optical properties of organic solar cells allows for realizing solar cells with increased short circuit current and energy conversion efficiency. The proposed device consists of an organic solar cell conformally prepared on the surface of an array of single and double textured pyramids. The device geometry allows for increasing the optical thickness of the organic solar cell, while the electrical thickness is equal to the nominal thickness of the solar cell. By increasing the optical thickness of the solar cell, the short circuit current is distinctly increased. The quantum efficiency and short circuit current are determined using finite-difference time-domain simulations of the 3D solar cell structure. The influence of different solar cell designs on the quantum efficiency and short circuit current is discussed and optimal device dimensions are proposed.

A Charge-Based Low-Power High-SNR Capacitive Sensing Interface Circuit

PubMed Central

Peng, Sheng-Yu; Qureshi, Muhammad S.; Hasler, Paul E.; Basu, Arindam; Degertekin, F. L.

2008-01-01

This paper describes a low-power approach to capacitive sensing that achieves a high signal-to-noise ratio. The circuit is composed of a capacitive feedback charge amplifier and a charge adaptation circuit. Without the adaptation circuit, the charge amplifier only consumes 1 μW to achieve the audio band SNR of 69.34dB. An adaptation scheme using Fowler-Nordheim tunneling and channel hot electron injection mechanisms to stabilize the DC output voltage is demonstrated. This scheme provides a very low frequency pole at 0.2Hz. The measured noise spectrums show that this slow-time scale adaptation does not degrade the circuit performance. The DC path can also be provided by a large feedback resistance without causing extra power consumption. A charge amplifier with a MOS-bipolar pseudo-resistor feedback scheme is interfaced with a capacitive micromachined ultrasonic transducer to demonstrate the feasibility of this approach for ultrasound applications. PMID:18787650

Design of rapid prototype of UAV line-of-sight stabilized control system

NASA Astrophysics Data System (ADS)

Huang, Gang; Zhao, Liting; Li, Yinlong; Yu, Fei; Lin, Zhe

2018-01-01

The line-of-sight (LOS) stable platform is the most important technology of UAV (unmanned aerial vehicle), which can reduce the effect to imaging quality from vibration and maneuvering of the aircraft. According to the requirement of LOS stability system (inertial and optical-mechanical combined method) and UAV's structure, a rapid prototype is designed using based on industrial computer using Peripheral Component Interconnect (PCI) and Windows RTX to exchange information. The paper shows the control structure, and circuit system including the inertial stability control circuit with gyro and voice coil motor driven circuit, the optical-mechanical stability control circuit with fast-steering-mirror (FSM) driven circuit and image-deviation-obtained system, outer frame rotary follower, and information-exchange system on PC. Test results show the stability accuracy reaches 5μrad, and prove the effectiveness of the combined line-of-sight stabilization control system, and the real-time rapid prototype runs stable.

Design, Simulation and Characteristics Research of the Interface Circuit based on nano-polysilicon thin films pressure sensor

NASA Astrophysics Data System (ADS)

Zhao, Xiaosong; Zhao, Xiaofeng; Yin, Liang

2018-03-01

This paper presents a interface circuit for nano-polysilicon thin films pressure sensor. The interface circuit includes consist of instrument amplifier and Analog-to-Digital converter (ADC). The instrumentation amplifier with a high common mode rejection ratio (CMRR) is implemented by three stages current feedback structure. At the same time, in order to satisfy the high precision requirements of pressure sensor measure system, the 1/f noise corner of 26.5 mHz can be achieved through chopping technology at a noise density of 38.2 nV/sqrt(Hz).Ripple introduced by chopping technology adopt continuous ripple reduce circuit (RRL), which achieves the output ripple level is lower than noise. The ADC achieves 16 bits significant digit by adopting sigma-delta modulator with fourth-order single-bit structure and digital decimation filter, and finally achieves high precision integrated pressure sensor interface circuit.

A ‘tool box’ for deciphering neuronal circuits in the developing chick spinal cord

PubMed Central

Hadas, Yoav; Etlin, Alex; Falk, Haya; Avraham, Oshri; Kobiler, Oren; Panet, Amos; Lev-Tov, Aharon; Klar, Avihu

2014-01-01

The genetic dissection of spinal circuits is an essential new means for understanding the neural basis of mammalian behavior. Molecular targeting of specific neuronal populations, a key instrument in the genetic dissection of neuronal circuits in the mouse model, is a complex and time-demanding process. Here we present a circuit-deciphering ‘tool box’ for fast, reliable and cheap genetic targeting of neuronal circuits in the developing spinal cord of the chick. We demonstrate targeting of motoneurons and spinal interneurons, mapping of axonal trajectories and synaptic targeting in both single and populations of spinal interneurons, and viral vector-mediated labeling of pre-motoneurons. We also demonstrate fluorescent imaging of the activity pattern of defined spinal neurons during rhythmic motor behavior, and assess the role of channel rhodopsin-targeted population of interneurons in rhythmic behavior using specific photoactivation. PMID:25147209

Selection of airgap layers for circuit timing optimization

NASA Astrophysics Data System (ADS)

Hyun, Daijoon; Shin, Youngsoo

2017-03-01

Airgap refers to a void formed in place of some inter metal dielectric (IMD). It brings about the reduction in coupling capacitance, which may contribute to improvement in circuit performance. We introduce two problems in this context. First is to choose the layers, where airgap should be applied, in such a way that total negative slack (TNS) is minimized for a given circuit. This has been motivated by the fact that best choice of airgap layers is different for different circuits. An algorithm is proposed to solve the problem, and is assessed against a naive approach in which airgap layers are simply fixed; additional 8% TNS reduction, on average of a few test circuits, is demonstrated. In the second problem, some wires of critical paths that are on non-airgap layers are reassigned to airgap layers such that TNS is further reduced; additional 3 to 14% of TNS reduction is observed.

Analysis and modeling of a family of two-transistor parallel inverters

NASA Technical Reports Server (NTRS)

Lee, F. C. Y.; Wilson, T. G.

1973-01-01

A family of five static dc-to-square-wave inverters, each employing a square-loop magnetic core in conjunction with two switching transistors, is analyzed using piecewise-linear models for the nonlinear characteristics of the transistors, diodes, and saturable-core devices. Four of the inverters are analyzed in detail for the first time. These analyses show that, by proper choice of a frame of reference, each of the five quite differently appearing inverter circuits can be described by a common equivalent circuit. This equivalent circuit consists of a five-segment nonlinear resistor, a nonlinear saturable reactor, and a linear capacitor. Thus, by proper interpretation and identification of the parameters in the different circuits, the results of a detailed solution for one of the inverter circuits provide similar information and insight into the local and global behavior of each inverter in the family.

Design of replica bit line control circuit to optimize power for SRAM

NASA Astrophysics Data System (ADS)

Pengjun, Wang; Keji, Zhou; Huihong, Zhang; Daohui, Gong

2016-12-01

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002, 61474068), and the K. C. Wong Magna Fund in Ningbo University.

A framework for scalable parameter estimation of gene circuit models using structural information.

PubMed

Kuwahara, Hiroyuki; Fan, Ming; Wang, Suojin; Gao, Xin

2013-07-01

Systematic and scalable parameter estimation is a key to construct complex gene regulatory models and to ultimately facilitate an integrative systems biology approach to quantitatively understand the molecular mechanisms underpinning gene regulation. Here, we report a novel framework for efficient and scalable parameter estimation that focuses specifically on modeling of gene circuits. Exploiting the structure commonly found in gene circuit models, this framework decomposes a system of coupled rate equations into individual ones and efficiently integrates them separately to reconstruct the mean time evolution of the gene products. The accuracy of the parameter estimates is refined by iteratively increasing the accuracy of numerical integration using the model structure. As a case study, we applied our framework to four gene circuit models with complex dynamics based on three synthetic datasets and one time series microarray data set. We compared our framework to three state-of-the-art parameter estimation methods and found that our approach consistently generated higher quality parameter solutions efficiently. Although many general-purpose parameter estimation methods have been applied for modeling of gene circuits, our results suggest that the use of more tailored approaches to use domain-specific information may be a key to reverse engineering of complex biological systems. http://sfb.kaust.edu.sa/Pages/Software.aspx. Supplementary data are available at Bioinformatics online.

Synthesis of a fully-integrated digital signal source for communications from chaotic dynamics-based oscillations

NASA Astrophysics Data System (ADS)

Glenn, Chance Michael, Sr.

This work is the conceptualization, derivation, analysis, and fabrication of a fully practical digital signal source designed from a chaotic oscillator. In it we show how a simple electronic circuit based upon the Colpitts oscillator, can be made to produce highly complex signals capable of carrying digital information. We show a direct relationship between the continuous-time chaotic oscillations produced by the circuit and the logistic map, which is discrete-time, one-dimensional map that is a fundamental paradigm for the study of chaotic systems. We demonstrate the direct encoding of binary information into the oscillations of the chaotic circuit. We demonstrate a new concept in power amplification, called syncrodyne amplification , which uses fundamental properties of chaotic oscillators to provide high-efficiency, high gain amplification of standard communication waveforms as well as typical chaotic oscillations. We show modeling results of this system providing nearly 60-dB power gain and 80% PAE for communications waveforms conforming to GMSK modulation. Finally we show results from a fabricated syncrodyne amplifier circuit operating at 2 MHz, providing over 40-dB power gain and 72% PAE, and propose design criteria for an 824--850 MHz circuit utilizing heterojunction bipolar transistors (HBTs), providing the basis for microwave frequency realization.

Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

PubMed

Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki

2016-07-20

We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

Building and validation of a prognostic model for predicting extracorporeal circuit clotting in patients with continuous renal replacement therapy.

PubMed

Fu, Xia; Liang, Xinling; Song, Li; Huang, Huigen; Wang, Jing; Chen, Yuanhan; Zhang, Li; Quan, Zilin; Shi, Wei

2014-04-01

To develop a predictive model for circuit clotting in patients with continuous renal replacement therapy (CRRT). A total of 425 cases were selected. 302 cases were used to develop a predictive model of extracorporeal circuit life span during CRRT without citrate anticoagulation in 24 h, and 123 cases were used to validate the model. The prediction formula was developed using multivariate Cox proportional-hazards regression analysis, from which a risk score was assigned. The mean survival time of the circuit was 15.0 ± 1.3 h, and the rate of circuit clotting was 66.6 % during 24 h of CRRT. Five significant variables were assigned a predicting score according to the regression coefficient: insufficient blood flow, no anticoagulation, hematocrit ≥0.37, lactic acid of arterial blood gas analysis ≤3 mmol/L and APTT < 44.2 s. The Hosmer-Lemeshow test showed no significant difference between the predicted and actual circuit clotting (R (2) = 0.232; P = 0.301). A risk score that includes the five above-mentioned variables can be used to predict the likelihood of extracorporeal circuit clotting in patients undergoing CRRT.

High-voltage isolation transformer for sub-nanosecond rise time pulses constructed with annular parallel-strip transmission lines.

PubMed

Homma, Akira

2011-07-01

A novel annular parallel-strip transmission line was devised to construct high-voltage high-speed pulse isolation transformers. The transmission lines can easily realize stable high-voltage operation and good impedance matching between primary and secondary circuits. The time constant for the step response of the transformer was calculated by introducing a simple low-frequency equivalent circuit model. Results show that the relation between the time constant and low-cut-off frequency of the transformer conforms to the theory of the general first-order linear time-invariant system. Results also show that the test transformer composed of the new transmission lines can transmit about 600 ps rise time pulses across the dc potential difference of more than 150 kV with insertion loss of -2.5 dB. The measured effective time constant of 12 ns agreed exactly with the theoretically predicted value. For practical applications involving the delivery of synchronized trigger signals to a dc high-voltage electron gun station, the transformer described in this paper exhibited advantages over methods using fiber optic cables for the signal transfer system. This transformer has no jitter or breakdown problems that invariably occur in active circuit components.

The research of digital circuit system for high accuracy CCD of portable Raman spectrometer

NASA Astrophysics Data System (ADS)

Yin, Yu; Cui, Yongsheng; Zhang, Xiuda; Yan, Huimin

2013-08-01

The Raman spectrum technology is widely used for it can identify various types of molecular structure and material. The portable Raman spectrometer has become a hot direction of the spectrometer development nowadays for its convenience in handheld operation and real-time detection which is superior to traditional Raman spectrometer with heavy weight and bulky size. But there is still a gap for its measurement sensitivity between portable and traditional devices. However, portable Raman Spectrometer with Shell-Isolated Nanoparticle-Enhanced Raman Spectroscopy (SHINERS) technology can enhance the Raman signal significantly by several orders of magnitude, giving consideration in both measurement sensitivity and mobility. This paper proposed a design and implementation of driver and digital circuit for high accuracy CCD sensor, which is core part of portable spectrometer. The main target of the whole design is to reduce the dark current generation rate and increase signal sensitivity during the long integration time, and in the weak signal environment. In this case, we use back-thinned CCD image sensor from Hamamatsu Corporation with high sensitivity, low noise and large dynamic range. In order to maximize this CCD sensor's performance and minimize the whole size of the device simultaneously to achieve the project indicators, we delicately designed a peripheral circuit for the CCD sensor. The design is mainly composed with multi-voltage circuit, sequential generation circuit, driving circuit and A/D transition parts. As the most important power supply circuit, the multi-voltage circuits with 12 independent voltages are designed with reference power supply IC and set to specified voltage value by the amplifier making up the low-pass filter, which allows the user to obtain a highly stable and accurate voltage with low noise. What's more, to make our design easy to debug, CPLD is selected to generate sequential signal. The A/D converter chip consists of a correlated double sampler; a digitally controlled variable gain amplifier and a 16-bit A/D converter which can help improve the data quality. And the acquired digital signals are transmitted into the computer via USB 2.0 data port. Our spectrometer with SHINERS technology can acquire the Raman spectrum signals efficiently in long time integration and weak signal environment, and the size of our system is well controlled for portable application.

A 4-Week Intervention Involving Mobile-Based Daily 6-Minute Micro-Sessions of Functional High-Intensity Circuit Training Improves Strength and Quality of Life, but Not Cardio-Respiratory Fitness of Young Untrained Adults.

PubMed

Sperlich, Billy; Hahn, Lea-Sofie; Edel, Antonia; Behr, Tino; Helmprobst, Julian; Leppich, Robert; Wallmann-Sperlich, Birgit; Holmberg, Hans-Christer

2018-01-01

The present study was designed to assess the psycho-physiological responses of physically untrained individuals to mobile-based multi-stimulating, circuit-like, multiple-joint conditioning (Circuit HIIT ) performed either once (1xCircuit HIIT ) or twice (2xCircuit HIIT ) daily for 4 weeks. In this single-center, two-arm randomized, controlled study, 24 men and women (age: 25 ± 5 years) first received no training instructions for 4 weeks and then performed 4 weeks of either 1xCircuit HIIT or 2xCircuit HIIT (5 men and 7 women in each group) daily. The 1xCircuit HIIT and 2xCircuit HIIT participants carried out 90.7 and 85.7% of all planned training sessions, respectively, with average heart rates during the 6-min sessions of 74.3 and 70.8% of maximal heart rate. Body, fat and fat-free mass, and metabolic rate at rest did not differ between the groups or between time-points of measurement. Heart rate while running at 6 km⋅h -1 declined after the intervention in both groups. Submaximal and peak oxygen uptake, the respiratory exchange ratio and heart rate recovery were not altered by either intervention. The maximal numbers of push-ups, leg-levers, burpees, 45°-one-legged squats and 30-s skipping, as well as perception of general health improved in both groups. Our 1xCircuit HIIT or 2xCircuit HIIT interventions improved certain parameters of functional strength and certain dimensions of quality of life in young untrained individuals. However, they were not sufficient to enhance cardio-respiratory fitness, in particular peak oxygen uptake.

Study of switching electric circuits with DC hybrid breaker, one stage

NASA Astrophysics Data System (ADS)

Niculescu, T.; Marcu, M.; Popescu, F. G.

2016-06-01

The paper presents a method of extinguishing the electric arc that occurs between the contacts of direct current breakers. The method consists of using an LC type extinguishing group to be optimally sized. From this point of view is presented a theoretical approach to the phenomena that occurs immediately after disconnecting the load and the specific diagrams are drawn. Using these, the elements extinguishing group we can choose. At the second part of the paper there is presented an analyses of the circuit switching process by decomposing the process in particular time sequences. For every time interval there was conceived a numerical simulation model in MATLAB-SIMULINK medium which integrates the characteristic differential equation and plots the capacitor voltage variation diagram and the circuit dumping current diagram.

Engrams and Circuits Crucial for Systems Consolidation of a Memory

PubMed Central

Kitamura, Takashi; Ogawa, Sachie K.; Roy, Dheeraj S.; Okuyama, Teruhiro; Morrissey, Mark D.; Smith, Lillian M.; Redondo, Roger L.; Tonegawa, Susumu

2017-01-01

Episodic memories initially require rapid synaptic plasticity within the hippocampus for their formation and are gradually consolidated in neocortical networks for permanent storage. However, the engrams and circuits that support neocortical memory consolidation remain unknown. We found that neocortical prefrontal memory engram cells, critical for remote contextual fear memory, were rapidly generated during initial learning via inputs from both hippocampal-entorhinal cortex and basolateral amygdala. After their generation, the prefrontal engram cells, with support from hippocampal memory engram cells, became functionally mature with time. Whereas hippocampal engram cells gradually became silent with time, engram cells in the basolateral amygdala, which were necessary for fear memory, are maintained. Our data provide new insights into the functional reorganization of engrams and circuits underlying systems consolidation of memory. PMID:28386011

Temporal Information of Directed Causal Connectivity in Multi-Trial ERP Data using Partial Granger Causality.

PubMed

Youssofzadeh, Vahab; Prasad, Girijesh; Naeem, Muhammad; Wong-Lin, KongFatt

2016-01-01

Partial Granger causality (PGC) has been applied to analyse causal functional neural connectivity after effectively mitigating confounding influences caused by endogenous latent variables and exogenous environmental inputs. However, it is not known how this connectivity obtained from PGC evolves over time. Furthermore, PGC has yet to be tested on realistic nonlinear neural circuit models and multi-trial event-related potentials (ERPs) data. In this work, we first applied a time-domain PGC technique to evaluate simulated neural circuit models, and demonstrated that the PGC measure is more accurate and robust in detecting connectivity patterns as compared to conditional Granger causality and partial directed coherence, especially when the circuit is intrinsically nonlinear. Moreover, the connectivity in PGC settles faster into a stable and correct configuration over time. After method verification, we applied PGC to reveal the causal connections of ERP trials of a mismatch negativity auditory oddball paradigm. The PGC analysis revealed a significant bilateral but asymmetrical localised activity in the temporal lobe close to the auditory cortex, and causal influences in the frontal, parietal and cingulate cortical areas, consistent with previous studies. Interestingly, the time to reach a stable connectivity configuration (~250–300 ms) coincides with the deviation of ensemble ERPs of oddball from standard tones. Finally, using a sliding time window, we showed higher resolution dynamics of causal connectivity within an ERP trial. In summary, time-domain PGC is promising in deciphering directed functional connectivity in nonlinear and ERP trials accurately, and at a sufficiently early stage. This data-driven approach can reduce computational time, and determine the key architecture for neural circuit modeling.

Tachometers Derived From a Brushless DC Motor

NASA Technical Reports Server (NTRS)

Howard, David E.; Smith, Dennis A.

2007-01-01

The upper part of the figure illustrates the major functional blocks of a direction-sensitive analog tachometer circuit based on the use of an unexcited two-phase brushless dc motor as a rotation transducer. The primary advantages of this circuit over many older tachometer circuits include the following: Its output inherently varies linearly with the rate of rotation of the shaft. Unlike some tachometer circuits that rely on differentiation of voltages with respect to time, this circuit relies on integration, which results in signals that are less noisy. There is no need for an additional shaft-angle sensor, nor is there any need to supply electrical excitation to a shaft-angle sensor. There is no need for mechanical brushes (which tend to act as sources of electrical noise). The underlying concept and electrical design are relatively simple. This circuit processes the back-electromagnetic force (back-emf) outputs of the two motor phases into a voltage directly proportional to the instantaneous rate (sign magnitude) of rotation of the shaft. The processing in this circuit effects a straightforward combination of mathematical operations leading to a final operation based on the well-known trigonometric identity (sin x)2 + (cos x)2 = 1 for any value of x. The principle of operation of this circuit is closely related to that of the tachometer circuit described in Tachometer Derived From Brushless Shaft-Angle Resolver (MFS-28845), NASA Tech Briefs, Vol. 19, No. 3 (March 1995), page 39. However, the present circuit is simpler in some respects because there is no need for sinusoidal excitation of shaftangle- resolver windings.

NASA direct detection laser diode driver

NASA Technical Reports Server (NTRS)

Seery, B. D.; Hornbuckle, C. A.

1989-01-01

TRW has developed a prototype driver circuit for GaAs laser diodes as part of the NASA/Goddard Space Flight Center's Direct Detection Laser Transceiver (DDLT) program. The circuit is designed to drive the laser diode over a range of user-selectable data rates from 1.7 to 220 Mbps, Manchester-encoded, while ensuring compatibility with 8-bit and quaternary pulse position modulation (QPPM) formats for simulating deep space communications. The resulting hybrid circuit has demonstrated 10 to 90 percent rise and fall times of less than 300 ps at peak currents exceeding 100 mA.

Minimal Power Latch for Single-Slope ADCs

NASA Technical Reports Server (NTRS)

Hancock, Bruce R. (Inventor)

2015-01-01

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.

Apparatus for controlling the firing of rectifiers in polyphase rectifying circuits

DOEpatents

Yarema, R.J.

1979-09-18

A polyphase rectifier is controlled with precision by a circuit that filters and shifts a reference signal associated with each phase and that starts a ramp signal at a zero crossing of the shifted reference signal. The difference between the ramp signal and an external trigger signal is used to generate a pulse that switches power rectifiers into conduction. The circuit reduces effects of variations that introduce subharmonics into a rectified signal and it can be used for constant or time-varying external trigger signals.

Learning Abstract Physical Concepts from Experience: Design and Use of an RC Circuit

NASA Astrophysics Data System (ADS)

Parra, Alfredo; Ordenes, Jorge; de la Fuente, Milton

2018-05-01

Science learning for undergraduate students requires grasping a great number of theoretical concepts in a rather short time. In our experience, this is especially difficult when students are required to simultaneously use abstract concepts, mathematical reasoning, and graphical analysis, such as occurs when learning about RC circuits. We present a simple experimental model in this work that allows students to easily design, build, and analyze RC circuits, thus providing an opportunity to test personal ideas, build graphical descriptions, and explore the meaning of the respective mathematical models, ultimately gaining a better grasp of the concepts involved. The result suggests that the simple setup indeed helps untrained students to visualize the essential points of this kind of circuit.

Three-Dimensional Simulation of Traveling-Wave Tube Cold-Test Characteristics Using MAFIA

NASA Technical Reports Server (NTRS)

Kory, Carol L.; Wilson, Jeffrey D.

1995-01-01

The three-dimensional simulation code MAFIA was used to compute the cold-test parameters - frequency-phase dispersion, beam on-axis interaction impedance, and attenuation - for two types of traveling-wave tube (TWT) slow-wave circuits. The potential for this electromagnetic computer modeling code to reduce the time and cost of TWT development is demonstrated by the high degree of accuracy achieved in calculating these parameters. Generalized input files were developed for ferruled coupled-cavity and TunneLadder slow-wave circuits. These files make it easy to model circuits of arbitrary dimensions. The utility of these files was tested by applying each to a specific TWT slow-wave circuit and comparing the results with experimental data. Excellent agreement was obtained.

High frequency, high time resolution time-to-digital converter employing passive resonating circuits.

PubMed

Ripamonti, Giancarlo; Abba, Andrea; Geraci, Angelo

2010-05-01

A method for measuring time intervals accurate to the picosecond range is based on phase measurements of oscillating waveforms synchronous with their beginning and/or end. The oscillation is generated by triggering an LC resonant circuit, whose capacitance is precharged. By using high Q resonators and a final active quenching of the oscillation, it is possible to conjugate high time resolution and a small measurement time, which allows a high measurement rate. Methods for fast analysis of the data are considered and discussed with reference to computing resource requirements, speed, and accuracy. Experimental tests show the feasibility of the method and a time accuracy better than 4 ps rms. Methods aimed at further reducing hardware resources are finally discussed.

Physical employment standard for Canadian wildland firefighters: examining test-retest reliability and the impact of familiarisation and physical fitness training.

PubMed

Gumieniak, Robert J; Gledhill, Norman; Jamnik, Veronica K

2018-05-04

To assess the impact of repeat performances (familiarisation) plus exercise training on completion time for the Ontario Wildland Firefighter (WFF) Fitness Test circuit (WFX-FIT), normally active general population participants (n = 145) were familiarised to the protocol then randomised into (i) exercise training, (ii) circuit only weekly performances or (iii) controls. At Baseline, the WFX-FIT pass rate for all groups combined was 11% for females and 73% for males, indicating that the Ontario WFX-FIT standard had a possible adverse impact on females. Following test familiarisation, mean circuit completion times improved by 11.9% and 10.2% for females and males, respectively. There were significant improvements in completion time for females (19.8%) and males (16.9%) who trained, plus females (12.2%) and males (9.8%) who performed the circuit only, while control participants were unchanged. Post training, the pass rate of the training group was 80% for females and 100% for males. Practitioner Summary: This paper details the impact of familiarisation plus exercise training as accommodation to mitigate potential adverse impact on initial attack wildland firefighter test performance. The results underscore the importance of test familiarisation opportunities and physical fitness training programmes that are specific to the demands of the job.

Self-powered monitoring of repeated head impacts using time-dilation energy measurement circuit.

PubMed

Feng, Tao; Aono, Kenji; Covassin, Tracey; Chakrabartty, Shantanu

2015-04-01

Due to the current epidemic levels of sport-related concussions (SRC) in the U.S., there is a pressing need for technologies that can facilitate long-term and continuous monitoring of head impacts. Existing helmet-sensor technology is inconsistent, inaccurate, and is not economically or logistically practical for large-scale human studies. In this paper, we present the design of a miniature, battery-less, self-powered sensor that can be embedded inside sport helmets and can continuously monitor and store different spatial and temporal statistics of the helmet impacts. At the core of the proposed sensor is a novel time-dilation circuit that allows measurement of a wide-range of impact energies. In this paper an array of linear piezo-floating-gate (PFG) injectors has been used for self-powered sensing and storage of linear and rotational head-impact statistics. The stored statistics are then retrieved using a plug-and-play reader and has been used for offline data analysis. We report simulation and measurement results validating the functionality of the time-dilation circuit for different levels of impact energies. Also, using prototypes of linear PFG integrated circuits fabricated in a 0.5 μm CMOS process, we demonstrate the functionality of the proposed helmet-sensors using controlled drop tests.

Polysilicon photoconductor for integrated circuits

DOEpatents

Hammond, Robert B.; Bowman, Douglas R.

1989-01-01

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Polysilicon photoconductor for integrated circuits

DOEpatents

Hammond, Robert B.; Bowman, Douglas R.

1990-01-01

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

DTIC Science & Technology

2016-01-20

Figure 7 4×4 GMAPD array wire bonded to CMOS timing circuits Figure 8 Low‐fill‐factor APD design used in lidar sensors The APD doping...epitaxial growth and the pixels are isolated by mesa etch. 128×32 lidar image sensors were built by bump bonding the APD arrays to a CMOS timing...passive image sensor with this large a format based on hybridization of a GMAPD array to a CMOS readout. Fig. 14 shows one of the first images taken

The suppression of charged-particle-induced noise in infrared detectors

NASA Technical Reports Server (NTRS)

Houck, J. R.; Briotta, D. A., Jr.

1982-01-01

A d.c.-coupled transimpedance amplifier/pulse suppression circuit designed to remove charged-particle-induced noise from infrared detectors is described. Noise spikes produced by single particle events are large and have short rise times, and can degrade the performance of an infrared detector in moderate radiation environments. The use of the suppression circuit improves the signal-to-noise ratio by a factor of 1.6:1, which corresponds to a reduction in required observing time by a factor of about 2.6.

Polysilicon photoconductor for integrated circuits

DOEpatents

Hammond, R.B.; Bowman, D.R.

1989-04-11

A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

Continuous-variable gate decomposition for the Bose-Hubbard model

NASA Astrophysics Data System (ADS)

Kalajdzievski, Timjan; Weedbrook, Christian; Rebentrost, Patrick

2018-06-01

In this work, we decompose the time evolution of the Bose-Hubbard model into a sequence of logic gates that can be implemented on a continuous-variable photonic quantum computer. We examine the structure of the circuit that represents this time evolution for one-dimensional and two-dimensional lattices. The elementary gates needed for the implementation are counted as a function of lattice size. We also include the contribution of the leading dipole interaction term which may be added to the Hamiltonian and its corresponding circuit.

Powerplexer

NASA Technical Reports Server (NTRS)

Woods, J. M. (Inventor)

1973-01-01

An electrical power distribution system is described for use in providing different dc voltage levels. A circuit is supplied with DC voltage levels and commutates pulses for timed intervals onto a pair of distribution wires. The circuit is driven by a command generator which places pulses on the wires in a timed sequence. The pair of wires extend to voltage strippers connected to the various loads. The voltage strippers each respond to the pulse dc levels on the pair of wires and form different output voltages communicated to each load.

Logic circuits from zero forcing.

PubMed

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

RF lockout circuit for electronic locking system

NASA Astrophysics Data System (ADS)

Becker, Earl M., Jr.; Miller, Allen

1991-02-01

An electronics lockout circuit was invented that includes an antenna adapted to receive radio frequency signals from a transmitter, and a radio frequency detector circuit which converts the radio frequency signals into a first direct current voltage indicative of the relative strength of the field resulting from the radio frequency signals. The first direct current voltage is supplied to a trigger circuit which compares this direct current voltage to an adjustable direct current reference voltage. This provides a second direct current voltage at the output whenever the amplitude of the first direct current voltage exceeds the amplitude of the reference voltage provided by the comparator circuit. This is supplied to a disconnect relay circuit which, upon receiving a signal from the electronic control unit of an electronic combination lock during the time period at which the second direct current voltage is present, isolates the door strike coil of a security door from the electronic control unit. This prevents signals falsely generated by the electronic control unit because of radio frequency signals in the vicinity of the electronic control unit energizing the door strike coil and accidentally opening a security door.

Student Learning in an Electric Circuit Theory Course: Critical Aspects and Task Design

ERIC Educational Resources Information Center

Carstensen, Anna-Karin; Bernhard, Jonte

2009-01-01

Understanding time-dependent responses, such as transients, is important in electric circuit theory and other branches of engineering. However, transient response is considered difficult to learn since familiarity with advanced mathematical tools such as Laplace transforms is required. Here, we analyse and describe a novel learning environment…

Further Development, Fabrication, and Testing of XM36E1 Fuze Setter

DTIC Science & Technology

1978-08-01

primary func- tion of this circuit, has the same timing characteristics as the original circuit: Half-period pulses are required to be greater than...temperature of -40 0 C. 9 The following corrective action was taken for this mal- fuction : (1) The batteries were replaced, and an investigation of battery

78 FR 21657 - Self-Regulatory Organizations; International Securities Exchange LLC; Order Approving, on an...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-11

... securities suddenly declining by significant amounts in a very short time period before suddenly reversing to... circuit breaker pilot program, which was implemented through a series of rule filings by the equity exchanges and by FINRA.\\9\\ The single-stock circuit breaker was designed to reduce extraordinary market...

Testing Services

NASA Technical Reports Server (NTRS)

1993-01-01

Trace Laboratories is an independent testing laboratory specializing in testing printed circuit boards, automotive products and military hardware. Technical information from NASA Tech Briefs and two subsequent JPL Technical Support packages have assisted Trace in testing surface insulation resistance on printed circuit board materials. Testing time was reduced and customer service was improved because of Jet Propulsion Laboratory technical support packages.

Connecting Time and Frequency in the RC Circuit

ERIC Educational Resources Information Center

Moya, A. A.

2017-01-01

Charging and discharging processes of a capacitor through a resistor, as well as the concept of impedance in alternating current circuits, are topics covered in introductory physics courses. The experimental study of the charge and discharge of a capacitor through a resistor is a well-established lab exercise that is used to introduce concepts…

Photogate Timing with a Smartphone

ERIC Educational Resources Information Center

Forinash, Kyle; Wisman, Raymond F.

2015-01-01

In a previous article we demonstrated that a simple, passive external circuit incorporating a thermistor, connected to a mobile device through the headset jack, can be used to collect temperature data. The basic approach is to output a sine wave signal to the headset port, through the circuit, and input the resulting signal from the headset…

78 FR 21675 - Self-Regulatory Organizations; The NASDAQ Stock Market LLC; Order Approving, on an Accelerated...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-11

... by significant amounts in a very short time period before suddenly reversing to prices consistent... circuit breaker pilot program, which was implemented through a series of rule filings by the equity exchanges and by FINRA.\\6\\ The single-stock circuit breaker was designed to reduce extraordinary market...

78 FR 21642 - Self-Regulatory Organizations; Chicago Board Options Exchange, Incorporated; Order Granting...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-11

... securities suddenly declining by significant amounts in a very short time period before suddenly reversing to... circuit breaker pilot program, which was implemented through a series of rule filings by the equity exchanges and by FINRA.\\8\\ The single-stock circuit breaker was designed to reduce extraordinary market...

SNDR Limits of Oscillator-Based Sensor Readout Circuits.

PubMed

Cardes, Fernando; Quintero, Andres; Gutierrez, Eric; Buffa, Cesare; Wiesbauer, Andreas; Hernandez, Luis

2018-02-03

This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.

Effects of a parallel resistor on electrical characteristics of a piezoelectric transformer in open-circuit transient state.

PubMed

Chang, Kuo-Tsai

2007-01-01

This paper investigates electrical transient characteristics of a Rosen-type piezoelectric transformer (PT), including maximum voltages, time constants, energy losses and average powers, and their improvements immediately after turning OFF. A parallel resistor connected to both input terminals of the PT is needed to improve the transient characteristics. An equivalent circuit for the PT is first given. Then, an open-circuit voltage, involving a direct current (DC) component and an alternating current (AC) component, and its related energy losses are derived from the equivalent circuit with initial conditions. Moreover, an AC power control system, including a DC-to-AC resonant inverter, a control switch and electronic instruments, is constructed to determine the electrical characteristics of the OFF transient state. Furthermore, the effects of the parallel resistor on the transient characteristics at different parallel resistances are measured. The advantages of adding the parallel resistor also are discussed. From the measured results, the DC time constant is greatly decreased from 9 to 0.04 ms by a 10 k(omega) parallel resistance under open output.

Coupling p+n Field-Effect Transistor Circuits for Low Concentration Methane Gas Detection

PubMed Central

Zhou, Xinyuan; Yang, Liping; Bian, Yuzhi; Ma, Xiang; Chen, Yunfa

2018-01-01

Nowadays, the detection of low concentration combustible methane gas has attracted great concern. In this paper, a coupling p+n field effect transistor (FET) amplification circuit is designed to detect methane gas. By optimizing the load resistance (RL), the response to methane of the commercial MP-4 sensor can be magnified ~15 times using this coupling circuit. At the same time, it decreases the limit of detection (LOD) from several hundred ppm to ~10 ppm methane, with the apparent response of 7.0 ± 0.2 and voltage signal of 1.1 ± 0.1 V. This is promising for the detection of trace concentrations of methane gas to avoid an accidental explosion because its lower explosion limit (LEL) is ~5%. The mechanism of this coupling circuit is that the n-type FET firstly generates an output voltage (VOUT) amplification process caused by the gate voltage-induced resistance change of the FET. Then, the p-type FET continues to amplify the signal based on the previous VOUT amplification process. PMID:29509659

Coupling p+n Field-Effect Transistor Circuits for Low Concentration Methane Gas Detection.

PubMed

Zhou, Xinyuan; Yang, Liping; Bian, Yuzhi; Ma, Xiang; Han, Ning; Chen, Yunfa

2018-03-06

Nowadays, the detection of low concentration combustible methane gas has attracted great concern. In this paper, a coupling p+n field effect transistor (FET) amplification circuit is designed to detect methane gas. By optimizing the load resistance ( R L ), the response to methane of the commercial MP-4 sensor can be magnified ~15 times using this coupling circuit. At the same time, it decreases the limit of detection (LOD) from several hundred ppm to ~10 ppm methane, with the apparent response of 7.0 ± 0.2 and voltage signal of 1.1 ± 0.1 V. This is promising for the detection of trace concentrations of methane gas to avoid an accidental explosion because its lower explosion limit (LEL) is ~5%. The mechanism of this coupling circuit is that the n-type FET firstly generates an output voltage ( V OUT ) amplification process caused by the gate voltage-induced resistance change of the FET. Then, the p-type FET continues to amplify the signal based on the previous V OUT amplification process.

Expediting analog design retargeting by design knowledge re-use and circuit synthesis: a practical example on a Delta-Sigma modulator

NASA Astrophysics Data System (ADS)

Webb, Matthew; Tang, Hua

2016-08-01

In the past decade or two, due to constant and rapid technology changes, analog design re-use or design retargeting to newer technologies has been brought to the table in order to expedite the design process and improve time-to-market. If properly conducted, analog design retargeting could significantly cut down design cycle compared to designs starting from the scratch. In this article, we present an empirical and general method for efficient analog design retargeting by design knowledge re-use and circuit synthesis (CS). The method first identifies circuit blocks that compose the source system and extracts the performance parameter specifications of each circuit block. Then, for each circuit block, it scales the values of design variables (DV) from the source design to derive an initial design in the target technology. Depending on the performance of this initial target design, a design space is defined for synthesis. Subsequently, each circuit block is automatically synthesised using state-of-art analog synthesis tools based on a combination of global and local optimisation techniques to achieve comparable performance specifications to those extracted from the source system. Finally, the overall system is composed of those synthesised circuit blocks in the target technology. We illustrate the method using a practical example of a complex Delta-Sigma modulator (DSM) circuit.

Computer simulations of stimulus dependent state switching in basic circuits of bursting neurons

NASA Astrophysics Data System (ADS)

Rabinovich, Mikhail; Huerta, Ramón; Bazhenov, Maxim; Kozlov, Alexander K.; Abarbanel, Henry D. I.

1998-11-01

We investigate the ability of oscillating neural circuits to switch between different states of oscillation in two basic neural circuits. We model two quite distinct small neural circuits. The first circuit is based on invertebrate central pattern generator (CPG) studies [A. I. Selverston and M. Moulins, The Crustacean Stomatogastric System (Springer-Verlag, Berlin, 1987)] and is composed of two neurons coupled via both gap junction and inhibitory synapses. The second consists of coupled pairs of interconnected thalamocortical relay and thalamic reticular neurons with both inhibitory and excitatory synaptic coupling. The latter is an elementary unit of the thalamic networks passing sensory information to the cerebral cortex [M. Steriade, D. A. McCormick, and T. J. Sejnowski, Science 262, 679 (1993)]. Both circuits have contradictory coupling between symmetric parts. The thalamocortical model has excitatory and inhibitory connections and the CPG has reciprocal inhibitory and electrical coupling. We describe the dynamics of the individual neurons in these circuits by conductance based ordinary differential equations of Hodgkin-Huxley type [J. Physiol. (London) 117, 500 (1952)]. Both model circuits exhibit bistability and hysteresis in a wide region of coupling strengths. The two main modes of behavior are in-phase and out-of-phase oscillations of the symmetric parts of the network. We investigate the response of these circuits, while they are operating in bistable regimes, to externally imposed excitatory spike trains with varying interspike timing and small amplitude pulses. These are meant to represent spike trains received by the basic circuits from sensory neurons. Circuits operating in a bistable region are sensitive to the frequency of these excitatory inputs. Frequency variations lead to changes from in-phase to out-of-phase coordination or vice versa. The signaling information contained in a spike train driving the network can place the circuit into one or another state depending on the interspike interval and this happens within a few spikes. These states are maintained by the basic circuit after the input signal is ended. When a new signal of the correct frequency enters the circuit, it can be switched to another state with the same ease.

An Efficient and Effective Design of InP Nanowires for Maximal Solar Energy Harvesting.

PubMed

Wu, Dan; Tang, Xiaohong; Wang, Kai; He, Zhubing; Li, Xianqiang

2017-11-25

Solar cells based on subwavelength-dimensions semiconductor nanowire (NW) arrays promise a comparable or better performance than their planar counterparts by taking the advantages of strong light coupling and light trapping. In this paper, we present an accurate and time-saving analytical design for optimal geometrical parameters of vertically aligned InP NWs for maximal solar energy absorption. Short-circuit current densities are calculated for each NW array with different geometrical dimensions under solar illumination. Optimal geometrical dimensions are quantitatively presented for single, double, and multiple diameters of the NW arrays arranged both squarely and hexagonal achieving the maximal short-circuit current density of 33.13 mA/cm 2 . At the same time, intensive finite-difference time-domain numerical simulations are performed to investigate the same NW arrays for the highest light absorption. Compared with time-consuming simulations and experimental results, the predicted maximal short-circuit current densities have tolerances of below 2.2% for all cases. These results unambiguously demonstrate that this analytical method provides a fast and accurate route to guide high performance InP NW-based solar cell design.

An Efficient and Effective Design of InP Nanowires for Maximal Solar Energy Harvesting

NASA Astrophysics Data System (ADS)

Wu, Dan; Tang, Xiaohong; Wang, Kai; He, Zhubing; Li, Xianqiang

2017-11-01

Solar cells based on subwavelength-dimensions semiconductor nanowire (NW) arrays promise a comparable or better performance than their planar counterparts by taking the advantages of strong light coupling and light trapping. In this paper, we present an accurate and time-saving analytical design for optimal geometrical parameters of vertically aligned InP NWs for maximal solar energy absorption. Short-circuit current densities are calculated for each NW array with different geometrical dimensions under solar illumination. Optimal geometrical dimensions are quantitatively presented for single, double, and multiple diameters of the NW arrays arranged both squarely and hexagonal achieving the maximal short-circuit current density of 33.13 mA/cm2. At the same time, intensive finite-difference time-domain numerical simulations are performed to investigate the same NW arrays for the highest light absorption. Compared with time-consuming simulations and experimental results, the predicted maximal short-circuit current densities have tolerances of below 2.2% for all cases. These results unambiguously demonstrate that this analytical method provides a fast and accurate route to guide high performance InP NW-based solar cell design.

Modeling the transport of nitrogen in an NPP-2006 reactor circuit

NASA Astrophysics Data System (ADS)

Stepanov, O. E.; Galkin, I. Yu.; Sledkov, R. M.; Melekh, S. S.; Strebnev, N. A.

2016-07-01

Efficient radiation protection of the public and personnel requires detecting an accident-initiating event quickly. Specifically, if a heat-exchange tube in a steam generator is ruptured, the 16N radioactive nitrogen isotope, which contributes to a sharp increase in the steam activity before the turbine, may serve as the signaling component. This isotope is produced in the core coolant and is transported along the circulation circuit. The aim of the present study was to model the transport of 16N in the primary and the secondary circuits of a VVER-1000 reactor facility (RF) under nominal operation conditions. KORSAR/GP and RELAP5/Mod.3.2 codes were used to perform the calculations. Computational models incorporating the major components of the primary and the secondary circuits of an NPP-2006 RF were constructed. These computational models were subjected to cross-verification, and the calculation results were compared to the experimental data on the distribution of the void fraction over the steam generator height. The models were proven to be valid. It was found that the time of nitrogen transport from the core to the heat-exchange tube leak was no longer than 1 s under RF operation at a power level of 100% N nom with all primary circuit pumps activated. The time of nitrogen transport from the leak to the γ-radiation detection unit under the same operating conditions was no longer than 9 s, and the nitrogen concentration in steam was no less than 1.4% (by mass) of its concentration at the reactor outlet. These values were obtained using conservative approaches to estimating the leak flow and the transport time, but the radioactive decay of nitrogen was not taken into account. Further research concerned with the calculation of thermohydraulic processes should be focused on modeling the transport of nitrogen under RF operation with some primary circuit pumps deactivated.

High voltage pulse generator. [Patent application

DOEpatents

Fasching, G.E.

1975-06-12

An improved high-voltage pulse generator is described which is especially useful in ultrasonic testing of rock core samples. An N number of capacitors are charged in parallel to V volts and at the proper instance are coupled in series to produce a high-voltage pulse of N times V volts. Rapid switching of the capacitors from the paralleled charging configuration to the series discharging configuration is accomplished by using silicon-controlled rectifiers which are chain self-triggered following the initial triggering of the first rectifier connected between the first and second capacitors. A timing and triggering circuit is provided to properly synchronize triggering pulses to the first SCR at a time when the charging voltage is not being applied to the parallel-connected charging capacitors. The output voltage can be readily increased by adding additional charging networks. The circuit allows the peak level of the output to be easily varied over a wide range by using a variable autotransformer in the charging circuit.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2017-01-01

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Antimonotonicity, Chaos and Multiple Attractors in a Novel Autonomous Jerk Circuit

NASA Astrophysics Data System (ADS)

Kengne, J.; Negou, A. Nguomkam; Njitacke, Z. T.

2017-06-01

We perform a systematic analysis of a system consisting of a novel jerk circuit obtained by replacing the single semiconductor diode of the original jerk circuit described in [Sprott, 2011a] with a pair of semiconductor diodes connected in antiparallel. The model is described by a continuous time three-dimensional autonomous system with hyperbolic sine nonlinearity, and may be viewed as a control system with nonlinear velocity feedback. The stability of the (unique) fixed point, the local bifurcations, and the discrete symmetries of the model equations are discussed. The complex behavior of the system is categorized in terms of its parameters by using bifurcation diagrams, Lyapunov exponents, time series, Poincaré sections, and basins of attraction. Antimonotonicity, period doubling bifurcation, symmetry restoring crises, chaos, and coexisting bifurcations are reported. More interestingly, one of the key contributions of this work is the finding of various regions in the parameters’ space in which the proposed (“elegant”) jerk circuit experiences the unusual phenomenon of multiple competing attractors (i.e. coexistence of four disconnected periodic and chaotic attractors). The basins of attraction of various coexisting attractors display complexity (i.e. fractal basins boundaries), thus suggesting possible jumps between coexisting attractors in experiment. Results of theoretical analyses are perfectly traced by laboratory experimental measurements. To the best of the authors’ knowledge, the jerk circuit/system introduced in this work represents the simplest electrical circuit (only a quadruple op amplifier chip without any analog multiplier chip) reported to date capable of four disconnected periodic and chaotic attractors for the same parameters setting.

Refinement and Pattern Formation in Neural Circuits by the Interaction of Traveling Waves with Spike-Timing Dependent Plasticity

PubMed Central

Bennett, James E. M.; Bair, Wyeth

2015-01-01

Traveling waves in the developing brain are a prominent source of highly correlated spiking activity that may instruct the refinement of neural circuits. A candidate mechanism for mediating such refinement is spike-timing dependent plasticity (STDP), which translates correlated activity patterns into changes in synaptic strength. To assess the potential of these phenomena to build useful structure in developing neural circuits, we examined the interaction of wave activity with STDP rules in simple, biologically plausible models of spiking neurons. We derive an expression for the synaptic strength dynamics showing that, by mapping the time dependence of STDP into spatial interactions, traveling waves can build periodic synaptic connectivity patterns into feedforward circuits with a broad class of experimentally observed STDP rules. The spatial scale of the connectivity patterns increases with wave speed and STDP time constants. We verify these results with simulations and demonstrate their robustness to likely sources of noise. We show how this pattern formation ability, which is analogous to solutions of reaction-diffusion systems that have been widely applied to biological pattern formation, can be harnessed to instruct the refinement of postsynaptic receptive fields. Our results hold for rich, complex wave patterns in two dimensions and over several orders of magnitude in wave speeds and STDP time constants, and they provide predictions that can be tested under existing experimental paradigms. Our model generalizes across brain areas and STDP rules, allowing broad application to the ubiquitous occurrence of traveling waves and to wave-like activity patterns induced by moving stimuli. PMID:26308406

Refinement and Pattern Formation in Neural Circuits by the Interaction of Traveling Waves with Spike-Timing Dependent Plasticity.

PubMed

Bennett, James E M; Bair, Wyeth

2015-08-01

Traveling waves in the developing brain are a prominent source of highly correlated spiking activity that may instruct the refinement of neural circuits. A candidate mechanism for mediating such refinement is spike-timing dependent plasticity (STDP), which translates correlated activity patterns into changes in synaptic strength. To assess the potential of these phenomena to build useful structure in developing neural circuits, we examined the interaction of wave activity with STDP rules in simple, biologically plausible models of spiking neurons. We derive an expression for the synaptic strength dynamics showing that, by mapping the time dependence of STDP into spatial interactions, traveling waves can build periodic synaptic connectivity patterns into feedforward circuits with a broad class of experimentally observed STDP rules. The spatial scale of the connectivity patterns increases with wave speed and STDP time constants. We verify these results with simulations and demonstrate their robustness to likely sources of noise. We show how this pattern formation ability, which is analogous to solutions of reaction-diffusion systems that have been widely applied to biological pattern formation, can be harnessed to instruct the refinement of postsynaptic receptive fields. Our results hold for rich, complex wave patterns in two dimensions and over several orders of magnitude in wave speeds and STDP time constants, and they provide predictions that can be tested under existing experimental paradigms. Our model generalizes across brain areas and STDP rules, allowing broad application to the ubiquitous occurrence of traveling waves and to wave-like activity patterns induced by moving stimuli.

High resolution time interval counter

DOEpatents

Condreva, Kenneth J.

1994-01-01

A high resolution counter circuit measures the time interval between the occurrence of an initial and a subsequent electrical pulse to two nanoseconds resolution using an eight megahertz clock. The circuit includes a main counter for receiving electrical pulses and generating a binary word--a measure of the number of eight megahertz clock pulses occurring between the signals. A pair of first and second pulse stretchers receive the signal and generate a pair of output signals whose widths are approximately sixty-four times the time between the receipt of the signals by the respective pulse stretchers and the receipt by the respective pulse stretchers of a second subsequent clock pulse. Output signals are thereafter supplied to a pair of start and stop counters operable to generate a pair of binary output words representative of the measure of the width of the pulses to a resolution of two nanoseconds. Errors associated with the pulse stretchers are corrected by providing calibration data to both stretcher circuits, and recording start and stop counter values. Stretched initial and subsequent signals are combined with autocalibration data and supplied to an arithmetic logic unit to determine the time interval in nanoseconds between the pair of electrical pulses being measured.

High resolution time interval counter

DOEpatents

Condreva, K.J.

1994-07-26

A high resolution counter circuit measures the time interval between the occurrence of an initial and a subsequent electrical pulse to two nanoseconds resolution using an eight megahertz clock. The circuit includes a main counter for receiving electrical pulses and generating a binary word--a measure of the number of eight megahertz clock pulses occurring between the signals. A pair of first and second pulse stretchers receive the signal and generate a pair of output signals whose widths are approximately sixty-four times the time between the receipt of the signals by the respective pulse stretchers and the receipt by the respective pulse stretchers of a second subsequent clock pulse. Output signals are thereafter supplied to a pair of start and stop counters operable to generate a pair of binary output words representative of the measure of the width of the pulses to a resolution of two nanoseconds. Errors associated with the pulse stretchers are corrected by providing calibration data to both stretcher circuits, and recording start and stop counter values. Stretched initial and subsequent signals are combined with autocalibration data and supplied to an arithmetic logic unit to determine the time interval in nanoseconds between the pair of electrical pulses being measured. 3 figs.

Radar studies of arctic ice and development of a real-time Arctic ice type identification system

NASA Technical Reports Server (NTRS)

Rouse, J. W., Jr.; Schell, J. A.; Permenter, J. A.

1973-01-01

Studies were conducted to develop a real-time Arctic ice type identification system. Data obtained by NASA Mission 126, conducted at Pt. Barrow, Alaska (Site 93) in April 1970 was analyzed in detail to more clearly define the major mechanisms at work affecting the radar energy illuminating a terrain cell of sea ice. General techniques for reduction of the scatterometer data to a form suitable for application of ice type decision criteria were investigated, and the electronic circuit requirements for implementation of these techniques were determined. Also, consideration of circuit requirements are extended to include the electronics necessary for analog programming of ice type decision algorithms. After completing the basic circuit designs a laboratory model was constructed and a preliminary evaluation performed. Several system modifications for improved performance are suggested. (Modified author abstract)

Design of a 9-loop quasi-exponential waveform generator

NASA Astrophysics Data System (ADS)

Banerjee, Partha; Shukla, Rohit; Shyam, Anurag

2015-12-01

We know in an under-damped L-C-R series circuit, current follows a damped sinusoidal waveform. But if a number of sinusoidal waveforms of decreasing time period, generated in an L-C-R circuit, be combined in first quarter cycle of time period, then a quasi-exponential nature of output current waveform can be achieved. In an L-C-R series circuit, quasi-exponential current waveform shows a rising current derivative and thereby finds many applications in pulsed power. Here, we have described design and experiment details of a 9-loop quasi-exponential waveform generator. In that, design details of magnetic switches have also been described. In the experiment, output current of 26 kA has been achieved. It has been shown that how well the experimentally obtained output current profile matches with the numerically computed output.

Faraday's law, Lenz's law, and conservation of energy

NASA Astrophysics Data System (ADS)

Wood, Lowell T.; Rottmann, Ray M.; Barrera, Regina

2004-03-01

We describe an experiment in which the induced electromotive force in a coil caused by an accelerating magnet and the position of the moving magnet are measured as a function of the time. When the circuit is completed by adding an appropriate load resistor, a current that opposes the flux change is generated in the coil. This current causes a magnetic field in the coil which decreases the acceleration of the rising magnet, as is evident from the position versus time data. The circuit provides a direct observation of effects that are a consequence of Lenz's law. The energy dissipated by the resistance in the circuit is shown to equal the loss in mechanical energy of the system to within experimental error, thus demonstrating conservation of energy. Students in introductory physics courses have performed this experiment successfully.

Design of a 9-loop quasi-exponential waveform generator.

PubMed

Banerjee, Partha; Shukla, Rohit; Shyam, Anurag

2015-12-01

We know in an under-damped L-C-R series circuit, current follows a damped sinusoidal waveform. But if a number of sinusoidal waveforms of decreasing time period, generated in an L-C-R circuit, be combined in first quarter cycle of time period, then a quasi-exponential nature of output current waveform can be achieved. In an L-C-R series circuit, quasi-exponential current waveform shows a rising current derivative and thereby finds many applications in pulsed power. Here, we have described design and experiment details of a 9-loop quasi-exponential waveform generator. In that, design details of magnetic switches have also been described. In the experiment, output current of 26 kA has been achieved. It has been shown that how well the experimentally obtained output current profile matches with the numerically computed output.

Improved environmental impact with diversion of perfusion bypass circuit to municipal solid waste.

PubMed

Debois, William; Prata, Jessica; Elmer, Barbara; Liu, Junli; Fominyam, Edward; Salemi, Arash

2013-06-01

The project goal was to reduce waste disposal volume, costs and minimize the negative impact that regulated waste treatment and disposal has on the environment. This was accomplished by diverting bypass circuits from the traditional regulated medical waste (RMW) to clear bag waste, or municipal solid waste (MSW). To qualify circuits to be disposed of through MSW stream, the circuits needed to be void of any free-flowing blood and be "responsibly clear." Traditionally the perfusion bypass circuit was emptied through the cardioplegia pump starting shortly after decannulation and heparin reversal. Up to 2000 mL of additional prime solution was added until the bypass circuit was rinsed clear. Three hundred sixty of 400 procedures (90%) had a complete circuit rinse and successful diversion to MSW. An additional 240 mL of processed cell salvage blood was available for transfusion. No additional time was spent in the operating room as a result of this procedure. Based on our procedure case volume and circuit weight of 15 pounds, almost 15,000 pounds (7.5 tons) of trash will be diverted from RMW. This technique represents another way for perfusionists to participate in sustainability efforts. Diverting the bypass circuit to clear bag waste results in a reduced environmental impact and annual cost savings. The treatment of RMW is associated with various environmental implications. MSW, or clear bag waste, on the other hand can now be disposed of in waste-to-energy facilities. This process not only releases a significantly less amount of carbon dioxide into the environment, but also helps generate renewable energy. Therefore, the bypass circuit diversion pilot project effectively demonstrates decreases in the carbon footprint of our organization and overall operating costs.

Superior model for fault tolerance computation in designing nano-sized circuit systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, N. S. S., E-mail: narinderjit@petronas.com.my; Muthuvalu, M. S., E-mail: msmuthuvalu@gmail.com; Asirvadam, V. S., E-mail: vijanth-sagayan@petronas.com.my

2014-10-24

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalizationmore » of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.« less

Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Oral Presentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Araya, Million

2015-08-25

SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hzmore » 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervalswhere the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design.« less

Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System - Final Paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Araya, Million

2015-08-21

SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hzmore » 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervals-where the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design.« less

The high accuracy data processing system of laser interferometry signals based on MSP430

NASA Astrophysics Data System (ADS)

Qi, Yong-yue; Lin, Yu-chi; Zhao, Mei-rong

2009-07-01

Generally speaking there are two orthogonal signals used in single-frequency laser interferometer for differentiating direction and electronic subdivision. However there usually exist three errors with the interferential signals: zero offsets error, unequal amplitude error and quadrature phase shift error. These three errors have a serious impact on subdivision precision. Based on Heydemann error compensation algorithm, it is proposed to achieve compensation of the three errors. Due to complicated operation of the Heydemann mode, a improved arithmetic is advanced to decrease the calculating time effectively in accordance with the special characteristic that only one item of data will be changed in each fitting algorithm operation. Then a real-time and dynamic compensatory circuit is designed. Taking microchip MSP430 as the core of hardware system, two input signals with the three errors are turned into digital quantity by the AD7862. After data processing in line with improved arithmetic, two ideal signals without errors are output by the AD7225. At the same time two original signals are turned into relevant square wave and imported to the differentiating direction circuit. The impulse exported from the distinguishing direction circuit is counted by the timer of the microchip. According to the number of the pulse and the soft subdivision the final result is showed by LED. The arithmetic and the circuit are adopted to test the capability of a laser interferometer with 8 times optical path difference and the measuring accuracy of 12-14nm is achieved.

Reduction in maximum time uncertainty of paired time signals

DOEpatents

Theodosiou, G.E.; Dawson, J.W.

1983-10-04

Reduction in the maximum time uncertainty (t[sub max]--t[sub min]) of a series of paired time signals t[sub 1] and t[sub 2] varying between two input terminals and representative of a series of single events where t[sub 1][<=]t[sub 2] and t[sub 1]+t[sub 2] equals a constant, is carried out with a circuit utilizing a combination of OR and AND gates as signal selecting means and one or more time delays to increase the minimum value (t[sub min]) of the first signal t[sub 1] closer to t[sub max] and thereby reduce the difference. The circuit may utilize a plurality of stages to reduce the uncertainty by factors of 20--800. 6 figs.

Implementing N-quantum phase gate via circuit QED with qubit-qubit interaction

NASA Astrophysics Data System (ADS)

Said, T.; Chouikh, A.; Essammouni, K.; Bennai, M.

2016-02-01

We propose a method for realizing a quantum phase gate of one qubit simultaneously controlling N target qubits based on the qubit-qubit interaction. We show how to implement the proposed gate with one transmon qubit simultaneously controlling N transmon qubits in a circuit QED driven by a strong microwave field. In our scheme, the operation time of this phase gate is independent of the number N of qubits. On the other hand, this gate can be realized in a time of nanosecond-scale much smaller than the decoherence time and dephasing time both being the time of microsecond-scale. Numerical simulation of the occupation probabilities of the second excited lever shows that the scheme could be achieved efficiently within current technology.

Reduction in maximum time uncertainty of paired time signals

DOEpatents

Theodosiou, George E.; Dawson, John W.

1983-01-01

Reduction in the maximum time uncertainty (t.sub.max -t.sub.min) of a series of paired time signals t.sub.1 and t.sub.2 varying between two input terminals and representative of a series of single events where t.sub.1 .ltoreq.t.sub.2 and t.sub.1 +t.sub.2 equals a constant, is carried out with a circuit utilizing a combination of OR and AND gates as signal selecting means and one or more time delays to increase the minimum value (t.sub.min) of the first signal t.sub.1 closer to t.sub.max and thereby reduce the difference. The circuit may utilize a plurality of stages to reduce the uncertainty by factors of 20-800.

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

NASA Technical Reports Server (NTRS)

Kaplan, Steven B.; Pylov, Sergey V.; Pambianchi, Michael

2003-01-01

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Delay test generation for synchronous sequential circuits

NASA Astrophysics Data System (ADS)

Devadas, Srinivas

1989-05-01

We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented.

In vitro and in vivo evaluation of Dideco's paediatric cardiopulmonary circuit for neonates weighing less than five kilograms.

PubMed

Thiara, A S; Eggereide, V; Pedersen, T; Lindberg, H; Fiane, A E

2010-07-01

The neonate cardiopulmonary bypass (CPB) circuit, including a KIDS D100 oxygenator (The Sorin Group, Mirandola, Italy) and a D130 arterial filter (The Sorin Group), was evaluated in vitro with respect to the removal of free micro gas bubbles. No gas bubbles > 40microm were measured after the arterial filter D130 upon manual introduction of 10 ml of air into the venous line or during the use of vacuum-assisted venous drainage (VAVD). The D130 arterial filter removed 88 % of gas bubbles < 40 microm during manual introduction of air into the venous line; however, only 50 % of gas bubbles < 40 microm were removed during the use of VAVD. The same CPB circuit was evaluated in vivo to compare with another CPB circuit, including a D901 oxygenator (The Sorin Group) and arterial filter D736 (The Sorin Group), in 155 neonates weighing < or =5 kg. The D100 circuit required significantly less priming volume than the D901 circuit. Postoperative haemoglobin was significantly higher, artificial ventilation time was significantly shorter and postoperative bleeding was significantly less in the D100 group. This neonate CPB circuit effectively removed the gas bubbles and required up to 37% less priming volume and, thus, decreased the need for blood transfusion.

Synthesis of Arbitrary Quantum Circuits to Topological Assembly: Systematic, Online and Compact.

PubMed

Paler, Alexandru; Fowler, Austin G; Wille, Robert

2017-09-05

It is challenging to transform an arbitrary quantum circuit into a form protected by surface code quantum error correcting codes (a variant of topological quantum error correction), especially if the goal is to minimise overhead. One of the issues is the efficient placement of magic state distillation sub circuits, so-called distillation boxes, in the space-time volume that abstracts the computation's required resources. This work presents a general, systematic, online method for the synthesis of such circuits. Distillation box placement is controlled by so-called schedulers. The work introduces a greedy scheduler generating compact box placements. The implemented software, whose source code is available at www.github.com/alexandrupaler/tqec, is used to illustrate and discuss synthesis examples. Synthesis and optimisation improvements are proposed.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Peak holding circuit for extremely narrow pulses

NASA Technical Reports Server (NTRS)

Oneill, R. W. (Inventor)

1975-01-01

An improved pulse stretching circuit comprising: a high speed wide-band amplifier connected in a fast charge integrator configuration; a holding circuit including a capacitor connected in parallel with a discharging network which employs a resistor and an FET; and an output buffer amplifier. Input pulses of very short duration are applied to the integrator charging the capacitor to a value proportional to the input pulse amplitude. After a predetermined period of time, conventional circuitry generates a dump pulse which is applied to the gate of the FET making a low resistance path to ground which discharges the capacitor. When the dump pulse terminates, the circuit is ready to accept another pulse to be stretched. The very short input pulses are thus stretched in width so that they may be analyzed by conventional pulse height analyzers.

Circularly polarized microwaves for magnetic resonance study in the GHz range: Application to nitrogen-vacancy in diamonds

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mrózek, M., E-mail: mariusz.mrozek@uj.edu.pl; Rudnicki, D. S.; Gawlik, W.

2015-07-06

The ability to create time-dependent magnetic fields of controlled polarization is essential for many experiments with magnetic resonance. We describe a microstrip circuit that allows us to generate strong magnetic field at microwave frequencies with arbitrary adjusted polarization. The circuit performance is demonstrated by applying it to an optically detected magnetic resonance and Rabi nutation experiments in nitrogen-vacancy color centers in diamond. Thanks to high efficiency of the proposed microstrip circuit and degree of circular polarization of 85%; it is possible to address the specific spin states of a diamond sample using a low power microwave generator. The circuit maymore » be applied to a wide range of magnetic resonance experiments with a well-controlled polarization of microwaves.« less

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-08

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

MEMS 3-DoF gyroscope design, modeling and simulation through equivalent circuit lumped parameter model

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mian, Muhammad Umer, E-mail: umermian@gmail.com; Khir, M. H. Md.; Tang, T. B.

Pre-fabrication, behavioural and performance analysis with computer aided design (CAD) tools is a common and fabrication cost effective practice. In light of this we present a simulation methodology for a dual-mass oscillator based 3 Degree of Freedom (3-DoF) MEMS gyroscope. 3-DoF Gyroscope is modeled through lumped parameter models using equivalent circuit elements. These equivalent circuits consist of elementary components which are counterpart of their respective mechanical components, used to design and fabricate 3-DoF MEMS gyroscope. Complete designing of equivalent circuit model, mathematical modeling and simulation are being presented in this paper. Behaviors of the equivalent lumped models derived for themore » proposed device design are simulated in MEMSPRO T-SPICE software. Simulations are carried out with the design specifications following design rules of the MetalMUMPS fabrication process. Drive mass resonant frequencies simulated by this technique are 1.59 kHz and 2.05 kHz respectively, which are close to the resonant frequencies found by the analytical formulation of the gyroscope. The lumped equivalent circuit modeling technique proved to be a time efficient modeling technique for the analysis of complex MEMS devices like 3-DoF gyroscopes. The technique proves to be an alternative approach to the complex and time consuming couple field analysis Finite Element Analysis (FEA) previously used.« less

Limbic control of aggression in the cat.

PubMed

Adamec, R E; Stark-Adamec, C I

1983-01-01

Over a decade of work by Flynn and colleagues has delineated a network of limbic circuits which function to modulate the expression of predatory aggression and defence in the cat, and aspects of this work are reviewed. In particular, Flynn's work revealed a circuit involving the basomedial amygdala which functions to suppress attack, and at the same time facilitates defence. A second circuit, involving the ventral hippocampus, is involved in attack facilitation. Studies relating stable differences in excitability in these two circuits to developmentally determined behavioural dispositions toward aggression or defence are summarized. Finally, the impact of experimentally induced limbic seizures on interictally maintained expression of aggression and defence behaviourally, and on limbic excitability are reviewed. Taken together, the data indicate that the behavioural balance of attack and defence is under the tonic control of opponent limbic circuits, which are themselves biased in a measureable manner. Developmental studies indicate that adult defensiveness is determined early in life, so early as to suggest some pre-programmed neuro-developmental process. Experimentally induced seizures alter behaviour lastingly, producing an increase in defensive disposition. At the same time there is an equally lasting potentiation of interictal transmission of neural activity from the amygdala to the hypothalamus. Moreover, seizures may reduce interictal transmission of activity through the ventral hippocampus by potentiating recurrent inhibition. These effects of seizures are of interest since seizures reproduce naturally occurring differences in limbic excitability seen in naturally defensive cats.

Simple proof of equivalence between adiabatic quantum computation and the circuit model.

PubMed

Mizel, Ari; Lidar, Daniel A; Mitchell, Morgan

2007-08-17

We prove the equivalence between adiabatic quantum computation and quantum computation in the circuit model. An explicit adiabatic computation procedure is given that generates a ground state from which the answer can be extracted. The amount of time needed is evaluated by computing the gap. We show that the procedure is computationally efficient.

Laser Scanner Tests For Single-Event Upsets

NASA Technical Reports Server (NTRS)

Kim, Quiesup; Soli, George A.; Schwartz, Harvey R.

1992-01-01

Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.

An Educational Laboratory Virtual Instrumentation Suite Assisted Experiment for Studying Fundamentals of Series Resistance-Inductance-Capacitance Circuit

ERIC Educational Resources Information Center

Rana, K. P. S.; Kumar, Vineet; Mendiratta, Jatin

2017-01-01

One of the most elementary concepts in freshmen Electrical Engineering subject comprises the Resistance-Inductance-Capacitance (RLC) circuit fundamentals, that is, their time and frequency domain responses. For a beginner, generally, it is difficult to understand and appreciate the step and the frequency responses, particularly the resonance. This…

LSI logic for phase-control rectifiers

NASA Technical Reports Server (NTRS)

Dolland, C.

1980-01-01

Signals for controlling phase-controlled rectifier circuit are generated by combinatorial logic than can be implemented in large-scale integration (LSI). LSI circuit saves space, weight, and assembly time compared to previous controls that employ one-shot multivibrators, latches, and capacitors. LSI logic functions by sensing three phases of ac power source and by comparing actual currents with intended currents.

Implantable Biomedical Microsystems: A New Graduate Course in Biomedical Circuits and Systems

ERIC Educational Resources Information Center

Sodagar, Amir M.

2014-01-01

After more than two decades of research on the design and development of implantable biomedical microsystems, it is time now to organize research achievements in this area in a consolidated and pedagogical form. This paper introduces a new graduate course in advanced biomedical circuits and systems. Designed for graduate students with electrical…

Parallel reduced-instruction-set-computer architecture for real-time symbolic pattern matching

NASA Astrophysics Data System (ADS)

Parson, Dale E.

1991-03-01

This report discusses ongoing work on a parallel reduced-instruction- set-computer (RISC) architecture for automatic production matching. The PRIOPS compiler takes advantage of the memoryless character of automatic processing by translating a program's collection of automatic production tests into an equivalent combinational circuit-a digital circuit without memory, whose outputs are immediate functions of its inputs. The circuit provides a highly parallel, fine-grain model of automatic matching. The compiler then maps the combinational circuit onto RISC hardware. The heart of the processor is an array of comparators capable of testing production conditions in parallel, Each comparator attaches to private memory that contains virtual circuit nodes-records of the current state of nodes and busses in the combinational circuit. All comparator memories hold identical information, allowing simultaneous update for a single changing circuit node and simultaneous retrieval of different circuit nodes by different comparators. Along with the comparator-based logic unit is a sequencer that determines the current combination of production-derived comparisons to try, based on the combined success and failure of previous combinations of comparisons. The memoryless nature of automatic matching allows the compiler to designate invariant memory addresses for virtual circuit nodes, and to generate the most effective sequences of comparison test combinations. The result is maximal utilization of parallel hardware, indicating speed increases and scalability beyond that found for course-grain, multiprocessor approaches to concurrent Rete matching. Future work will consider application of this RISC architecture to the standard (controlled) Rete algorithm, where search through memory dominates portions of matching.

Faster Blood Flow Rate Does Not Improve Circuit Life in Continuous Renal Replacement Therapy: A Randomized Controlled Trial.

PubMed

Fealy, Nigel; Aitken, Leanne; du Toit, Eugene; Lo, Serigne; Baldwin, Ian

2017-10-01

To determine whether blood flow rate influences circuit life in continuous renal replacement therapy. Prospective randomized controlled trial. Single center tertiary level ICU. Critically ill adults requiring continuous renal replacement therapy. Patients were randomized to receive one of two blood flow rates: 150 or 250 mL/min. The primary outcome was circuit life measured in hours. Circuit and patient data were collected until each circuit clotted or was ceased electively for nonclotting reasons. Data for clotted circuits are presented as median (interquartile range) and compared using the Mann-Whitney U test. Survival probability for clotted circuits was compared using log-rank test. Circuit clotting data were analyzed for repeated events using hazards ratio. One hundred patients were randomized with 96 completing the study (150 mL/min, n = 49; 250 mL/min, n = 47) using 462 circuits (245 run at 150 mL/min and 217 run at 250 mL/min). Median circuit life for first circuit (clotted) was similar for both groups (150 mL/min: 9.1 hr [5.5-26 hr] vs 10 hr [4.2-17 hr]; p = 0.37). Continuous renal replacement therapy using blood flow rate set at 250 mL/min was not more likely to cause clotting compared with 150 mL/min (hazards ratio, 1.00 [0.60-1.69]; p = 0.68). Gender, body mass index, weight, vascular access type, length, site, and mode of continuous renal replacement therapy or international normalized ratio had no effect on clotting risk. Continuous renal replacement therapy without anticoagulation was more likely to cause clotting compared with use of heparin strategies (hazards ratio, 1.62; p = 0.003). Longer activated partial thromboplastin time (hazards ratio, 0.98; p = 0.002) and decreased platelet count (hazards ratio, 1.19; p = 0.03) were associated with a reduced likelihood of circuit clotting. There was no difference in circuit life whether using blood flow rates of 250 or 150 mL/min during continuous renal replacement therapy.

Method for Evaluating the Corrosion Resistance of Aluminum Metallization of Integrated Circuits under Multifactorial Influence

NASA Astrophysics Data System (ADS)

Kolomiets, V. I.

2018-03-01

The influence of complex influence of climatic factors (temperature, humidity) and electric mode (supply voltage) on the corrosion resistance of metallization of integrated circuits has been considered. The regression dependence of the average time of trouble-free operation t on the mentioned factors has been established in the form of a modified Arrhenius equation that is adequate in a wide range of factor values and is suitable for selecting accelerated test modes. A technique for evaluating the corrosion resistance of aluminum metallization of depressurized CMOS integrated circuits has been proposed.

De-Trending Techniques: Methods for Cleaning Questionable Shock Data

NASA Technical Reports Server (NTRS)

Grillo, Vincent J.

2010-01-01

Not all zero shifted acceleration data can De-trended using this technique. DC shifts, improper AC coupling, Circuit noise/EMI/EMR, Equivalent RC circuit gain response/Circuit saturation(Slew Rate Limited), fixture grounding and wiring losses can all contribute to bad shock data being recorded. Some data that is zero-shifted or exhibit large instantaneous velocity shifts is inherently bad and a retest is warranted. Clean Acceleration-Time history data can be bad upon examining the Velocity & Displacement profiles. Laser Vibrometers provide a high level of accuracy for pyrotechnic shock testing. Engineering judgment and experience will determine the validity of Shock data.

Investigation for connecting waveguide in off-planar integrated circuits.

PubMed

Lin, Jie; Feng, Zhifang

2017-09-01

The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

NASA Technical Reports Server (NTRS)

Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

2007-01-01

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

Theory and Circuit Model for Lossy Coaxial Transmission Line

DOE Office of Scientific and Technical Information (OSTI.GOV)

Genoni, T. C.; Anderson, C. N.; Clark, R. E.

2017-04-01

The theory of signal propagation in lossy coaxial transmission lines is revisited and new approximate analytic formulas for the line impedance and attenuation are derived. The accuracy of these formulas from DC to 100 GHz is demonstrated by comparison to numerical solutions of the exact field equations. Based on this analysis, a new circuit model is described which accurately reproduces the line response over the entire frequency range. Circuit model calculations are in excellent agreement with the numerical and analytic results, and with finite-difference-time-domain simulations which resolve the skindepths of the conducting walls.

BINARY STORAGE ELEMENT

DOEpatents

Chu, J.C.

1958-06-10

A binary storage device is described comprising a toggle provided with associsted improved driver circuits adapted to produce reliable action of the toggle during clearing of the toggle to one of its two states. or transferring information into and out of the toggle. The invention resides in the development of a self-regulating driver circuit to minimize the fluctuation of the driving voltages for the toggle. The disclosed driver circuit produces two pulses in response to an input pulse: a first or ''clear'' pulse beginning nt substantially the same time but endlrg slightly sooner than the second or ''transfer'' output pulse.

Graphene-hexagonal boron nitride resonant tunneling diodes as high-frequency oscillators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaskell, J.; Fromhold, T. M.; Greenaway, M. T.

We assess the potential of two-terminal graphene-hexagonal boron nitride-graphene resonant tunneling diodes as high-frequency oscillators, using self-consistent quantum transport and electrostatic simulations to determine the time-dependent response of the diodes in a resonant circuit. We quantify how the frequency and power of the current oscillations depend on the diode and circuit parameters including the doping of the graphene electrodes, device geometry, alignment of the graphene lattices, and the circuit impedances. Our results indicate that current oscillations with frequencies of up to several hundred GHz should be achievable.

A real-time spectrum acquisition system design based on quantum dots-quantum well detector

NASA Astrophysics Data System (ADS)

Zhang, S. H.; Guo, F. M.

2016-01-01

In this paper, we studied the structure characteristics of quantum dots-quantum well photodetector with response wavelength range from 400 nm to 1000 nm. It has the characteristics of high sensitivity, low dark current and the high conductance gain. According to the properties of the quantum dots-quantum well photodetectors, we designed a new type of capacitive transimpedence amplifier (CTIA) readout circuit structure with the advantages of adjustable gain, wide bandwidth and high driving ability. We have implemented the chip packaging between CTIA-CDS structure readout circuit and quantum dots detector and tested the readout response characteristics. According to the timing signals requirements of our readout circuit, we designed a real-time spectral data acquisition system based on FPGA and ARM. Parallel processing mode of programmable devices makes the system has high sensitivity and high transmission rate. In addition, we realized blind pixel compensation and smoothing filter algorithm processing to the real time spectrum data by using C++. Through the fluorescence spectrum measurement of carbon quantum dots and the signal acquisition system and computer software system to realize the collection of the spectrum signal processing and analysis, we verified the excellent characteristics of detector. It meets the design requirements of quantum dot spectrum acquisition system with the characteristics of short integration time, real-time and portability.

A new kind of universal smart home security safety monitoring system

NASA Astrophysics Data System (ADS)

Li, Biqing; Li, Zhao

2018-04-01

With the current level of social development, improved quality of life, existence and security issues of law and order has become an important issue. This graduation project adopts the form of wireless transmission, to STC89C52 microcontroller as the host control human infrared induction anti-theft monitoring system. The system mainly consists of main control circuit, power supply circuit, activities of the human body detection module, sound and light alarm circuit, record and display circuit. The main function is to achieve exploration activities on the human body, then the information is transmitted to the control panel, according to the system microcontroller program control sound and light alarm circuit, while recording the alarm location and time, and always check the record as required, and ultimately achieve the purpose of monitoring. The advantage of using pyroelectric infrared sensor can be installed in a hidden place, not easy to find, and low cost, good detection results, and has broad prospects for development.

Breathing and Vocal Control: The Respiratory System as both a Driver and Target of Telencephalic Vocal Motor Circuits in Songbirds

PubMed Central

Schmidt, Marc F.; McLean, Judith; Goller, Franz

2011-01-01

The production of vocalizations is intimately linked to the respiratory system. Despite our understanding of neural circuits that generate normal respiratory patterns, very little is understood regarding how these ponto-medullary circuits become engaged during vocal production. Songbirds offer a potentially powerful model system for addressing this relationship. Songs dramatically alter the respiratory pattern in ways that are often highly predictable and songbirds have a specialized telencephalic vocal motor circuit that provides massive innervation to a brainstem respiratory network that shares many similarities with its mammalian counterpart. In this review, we highlight interactions between the song motor circuit and the respiratory system, describing how both systems likely interact to produce the complex respiratory patterns that are observed during vocalization. We also discuss how the respiratory system, through its bilateral bottom-up projections to thalamus, might play a key role in sending precisely timed signals that synchronize premotor activity in both hemispheres. PMID:21984733

Printed Graphene Derivative Circuits as Passive Electrical Filters

PubMed Central

Sinar, Dogan

2018-01-01

The objective of this study is to inkjet print resistor-capacitor (RC) low pass electrical filters, using a novel water-based cellulose graphene ink, and compare the voltage-frequency and transient behavior to equivalent circuits constructed from discrete passive components. The synthesized non-toxic graphene-carboxymethyl cellulose (G-CMC) ink is deposited on mechanically flexible polyimide substrates using a customized printer that dispenses functionalized aqueous solutions. The design of the printed first-order and second-order low-pass RC filters incorporate resistive traces and interdigitated capacitors. Low pass filter characteristics, such as time constant, cut-off frequency and roll-off rate, are determined for comparative analysis. Experiments demonstrate that for low frequency applications (<100 kHz) the printed graphene derivative circuits performed as well as the circuits constructed from discrete resistors and capacitors for both low pass filter and RC integrator applications. The impact of mechanical stress due to bending on the electrical performance of the flexible printed circuits is also investigated. PMID:29473890

A programmable CCD driver circuit for multiphase CCD operation

NASA Technical Reports Server (NTRS)

Ewin, Audrey J.; Reed, Kenneth V.

1989-01-01

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Extended behavioural device modelling and circuit simulation with Qucs-S

NASA Astrophysics Data System (ADS)

Brinson, M. E.; Kuznetsov, V.

2018-03-01

Current trends in circuit simulation suggest a growing interest in open source software that allows access to more than one simulation engine while simultaneously supporting schematic drawing tools, behavioural Verilog-A and XSPICE component modelling, and output data post-processing. This article introduces a number of new features recently implemented in the 'Quite universal circuit simulator - SPICE variant' (Qucs-S), including structure and fundamental schematic capture algorithms, at the same time highlighting their use in behavioural semiconductor device modelling. Particular importance is placed on the interaction between Qucs-S schematics, equation-defined devices, SPICE B behavioural sources and hardware description language (HDL) scripts. The multi-simulator version of Qucs is a freely available tool that offers extended modelling and simulation features compared to those provided by legacy circuit simulators. The performance of a number of Qucs-S modelling extensions are demonstrated with a GaN HEMT compact device model and data obtained from tests using the Qucs-S/Ngspice/Xyce ©/SPICE OPUS multi-engine circuit simulator.

Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

NASA Technical Reports Server (NTRS)

Seefeldt, James (Inventor); Feng, Xiaoxin (Inventor); Roper, Weston (Inventor)

2013-01-01

A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Fast modeling of flux trapping cascaded explosively driven magnetic flux compression generators.

PubMed

Wang, Yuwei; Zhang, Jiande; Chen, Dongqun; Cao, Shengguang; Li, Da; Liu, Chebo

2013-01-01

To predict the performance of flux trapping cascaded flux compression generators, a calculation model based on an equivalent circuit is investigated. The system circuit is analyzed according to its operation characteristics in different steps. Flux conservation coefficients are added to the driving terms of circuit differential equations to account for intrinsic flux losses. To calculate the currents in the circuit by solving the circuit equations, a simple zero-dimensional model is used to calculate the time-varying inductance and dc resistance of the generator. Then a fast computer code is programmed based on this calculation model. As an example, a two-staged flux trapping generator is simulated by using this computer code. Good agreements are achieved by comparing the simulation results with the measurements. Furthermore, it is obvious that this fast calculation model can be easily applied to predict performances of other flux trapping cascaded flux compression generators with complex structures such as conical stator or conical armature sections and so on for design purpose.

Optical analog data link with simple self-test feature

DOEpatents

Witkover, Richard L.

1986-01-01

A communications circuit for optically transmitting analog data signals free of excessive ripple, while having rapid response time. The invention is further characterized by being adapted to provide an immediate indication of the failure of the optical transmission link of the circuit. Commercially available voltage to frequency converter chips are used in conjunction with suitable wiring arrays and in combination with readily available indicator means for constructing the communication circuit of the invention. A V/F converter in the communications circuit is coupled to an offset adjustment means to cause the converter to continuously produce a string of output voltage pulses having a frequency of about 1 Khz responsive to the input analog signal to the converter being zero. The continuous presence of the 1 Khz frequency on the optical transmission link is monitored at the receiving end of the communication circuit and the indicator means is connected to immediately provide an easily detected indication of a failure of the optical transmission link to transmit the 1 Khz frequency pulses.

Neural learning circuits utilizing nano-crystalline silicon transistors and memristors.

PubMed

Cantley, Kurtis D; Subramaniam, Anand; Stiegler, Harvey J; Chapman, Richard A; Vogel, Eric M

2012-04-01

Properties of neural circuits are demonstrated via SPICE simulations and their applications are discussed. The neuron and synapse subcircuits include ambipolar nano-crystalline silicon transistor and memristor device models based on measured data. Neuron circuit characteristics and the Hebbian synaptic learning rule are shown to be similar to biology. Changes in the average firing rate learning rule depending on various circuit parameters are also presented. The subcircuits are then connected into larger neural networks that demonstrate fundamental properties including associative learning and pulse coincidence detection. Learned extraction of a fundamental frequency component from noisy inputs is demonstrated. It is then shown that if the fundamental sinusoid of one neuron input is out of phase with the rest, its synaptic connection changes differently than the others. Such behavior indicates that the system can learn to detect which signals are important in the general population, and that there is a spike-timing-dependent component of the learning mechanism. Finally, future circuit design and considerations are discussed, including requirements for the memristive device.

Two-dimensional lattice gauge theories with superconducting quantum circuits

PubMed Central

Marcos, D.; Widmer, P.; Rico, E.; Hafezi, M.; Rabl, P.; Wiese, U.-J.; Zoller, P.

2014-01-01

A quantum simulator of U(1) lattice gauge theories can be implemented with superconducting circuits. This allows the investigation of confined and deconfined phases in quantum link models, and of valence bond solid and spin liquid phases in quantum dimer models. Fractionalized confining strings and the real-time dynamics of quantum phase transitions are accessible as well. Here we show how state-of-the-art superconducting technology allows us to simulate these phenomena in relatively small circuit lattices. By exploiting the strong non-linear couplings between quantized excitations emerging when superconducting qubits are coupled, we show how to engineer gauge invariant Hamiltonians, including ring-exchange and four-body Ising interactions. We demonstrate that, despite decoherence and disorder effects, minimal circuit instances allow us to investigate properties such as the dynamics of electric flux strings, signaling confinement in gauge invariant field theories. The experimental realization of these models in larger superconducting circuits could address open questions beyond current computational capability. PMID:25512676

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

PubMed

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

The Relationship between the Current Waveform just before the Current Zero and the Interruption Ability in the High-speed VCB

NASA Astrophysics Data System (ADS)

Niwa, Yoshimitsu; Matsuzaki, Jun; Yokokura, Kunio

The high-speed vacuum circuit breaker, which forced the fault current to zero was investigated. The test circuit breaker consisted of a vacuum interrupter and a high frequency current source. The vacuum interrupter, which had the axial magnetic field electrode and the disk shape electrode, was tested. The arcing period of the high-speed vacuum circuit breaker is much shorter than that of conventional circuit breaker. The arc behavior of the test electrodes immediately after the contact separation was observed by a high-speed video camcorder. The relation between the current waveform just before the current zero and the interruption ability by varying the high frequency current source was investigated experimentally. The results demonstrate the interruption ability and the arc behavior of the high-speed vacuum circuit breaker. The high current interruption was made possible by the low current period just before the current zero, although the arcing time is short and the arc is concentrated.

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Sayyah, Rana; Ho, Fat D.

2009-01-01

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

Optical analog data link with simple self-test feature

DOEpatents

Witkover, R.L.

1984-02-01

A communications circuit for optically transmitting analog data signals free of excessive ripple, while having rapid response time. The invention is further characterized by being adapted to provide an immediate indication of the failure of the optical transmission link of the circuit. Commerically available voltage to frequency converter chips are used in conjunction with suitable wiring arrays and in combination with readily available indicator means for constructing the communication circuit of the invention. A V/F converter in the communications circuit is coupled to an offset adjustment means to cause the converter to continuously produce a string of output voltage pulses having a frequency of about 1Khz responsive to the input analog signal to the converter being zero. The continuous presence of the 1Khz frequency on the optical transmission link is monitored at the receiving end of the communication circuit and the indicator means is connected to immediately provide an easily detected indication of a failure of the optical transmission link to transmit the 1Khz frequency pulses.

Printed Graphene Derivative Circuits as Passive Electrical Filters.

PubMed

Sinar, Dogan; Knopf, George K

2018-02-23

The objective of this study is to inkjet print resistor-capacitor ( RC ) low pass electrical filters, using a novel water-based cellulose graphene ink, and compare the voltage-frequency and transient behavior to equivalent circuits constructed from discrete passive components. The synthesized non-toxic graphene-carboxymethyl cellulose (G-CMC) ink is deposited on mechanically flexible polyimide substrates using a customized printer that dispenses functionalized aqueous solutions. The design of the printed first-order and second-order low-pass RC filters incorporate resistive traces and interdigitated capacitors. Low pass filter characteristics, such as time constant, cut-off frequency and roll-off rate, are determined for comparative analysis. Experiments demonstrate that for low frequency applications (<100 kHz) the printed graphene derivative circuits performed as well as the circuits constructed from discrete resistors and capacitors for both low pass filter and RC integrator applications. The impact of mechanical stress due to bending on the electrical performance of the flexible printed circuits is also investigated.

Time-space modal logic for verification of bit-slice circuits

NASA Astrophysics Data System (ADS)

Hiraishi, Hiromi

1996-03-01

The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

Development of ball surface acoustic wave trace moisture analyzer using burst waveform undersampling circuit

NASA Astrophysics Data System (ADS)

Tsuji, Toshihiro; Oizumi, Toru; Fukushi, Hideyuki; Takeda, Nobuo; Akao, Shingo; Tsukahara, Yusuke; Yamanaka, Kazushi

2018-05-01

The measurement and control of trace moisture, where the water concentration is lower than 1 ppmv [-76.2 °C for the frost point (°CFP)], are essential for improving the yield rate of semiconductor devices and for ensuring their reliability. A ball surface acoustic wave (SAW) sensor with a sol-gel silica coating exhibited useful characteristics for a trace moisture analyzer (TMA) when the temperature drift of the delay time output was precisely compensated using two-frequency measurement (TFM), where the temperature-compensated relative delay time change (RDTC) was obtained by subtracting the RDTC at the fundamental frequency from that at the third harmonic frequency on an identical propagation path. However, the cost of the measurement circuit was a problem. In this study, a burst waveform undersampling (BUS) circuit based on the theory of undersampling measurement was developed as a practical means. The BUS circuit was useful for precise temperature compensation of the RDTC, and the ball SAW TMA was prototyped by calibrating the RDTC using a TMA based on cavity ring-down spectroscopy (CRDS), which is the most reliable method for trace moisture measurement. The ball SAW TMA outputted a similar concentration to that obtained by the CRDS TMA, and its response time at a set concentration in N2 with a flow rate of 1 l/min was about half that of the CRDS TMA, suggesting that moisture of -80 °CFP was measured within only 1 min. The detection limit at a signal-to-noise ratio of 3 was estimated to be 0.05 ppbv, comparable with that of the CRDS TMA. From these results, it was demonstrated that a practical ball SAW TMA can be realized using the developed BUS circuit.

Circuit-Detour Design and Implementation - Enhancing the Southern California's Seismic Network Reliability through Redundant Network Paths

NASA Astrophysics Data System (ADS)

Watkins, M.; Busby, R.; Rico, H.; Johnson, M.; Hauksson, E.

2003-12-01

We provide enhanced network robustness by apportioning redundant data communications paths for seismic stations in the field. By providing for more than one telemetry route, either physical or logical, network operators can improve availability of seismic data while experiencing occasional network outages, and also during the loss of key gateway interfaces such as a router or central processor. This is especially important for seismic stations in sparsely populated regions where a loss of a single site may result in a significant gap in the network's monitoring capability. A number of challenges arise in the application of a circuit-detour mechanism. One requirement is that it fits well within the existing framework of our real-time system processing. It is also necessary to craft a system that is not needlessly complex to maintain or implement, particularly during a crisis. The method that we use for circuit-detours does not require the reconfiguration of dataloggers or communications equipment in the field. Remote network configurations remain static, changes are only required at the central site. We have implemented standardized procedures to detour circuits on similar transport mediums, such as virtual circuits on the same leased line; as well as physically different communications pathways, such as a microwave link backed up by a leased line. The lessons learned from these improvements in reliability, and optimization efforts could be applied to other real-time seismic networks. A fundamental tenant of most seismic networks is that they are reliable and have a high percentage of real-time data availability. A reasonable way to achieve these expectations is to provide alternate means of delivering data to the central processing sites, with a simple method for utilizing these alternate paths.

A closed-loop compressive-sensing-based neural recording system.

PubMed

Zhang, Jie; Mitra, Srinjoy; Suo, Yuanming; Cheng, Andrew; Xiong, Tao; Michon, Frederic; Welkenhuysen, Marleen; Kloosterman, Fabian; Chin, Peter S; Hsiao, Steven; Tran, Trac D; Yazicioglu, Firat; Etienne-Cummings, Ralph

2015-06-01

This paper describes a low power closed-loop compressive sensing (CS) based neural recording system. This system provides an efficient method to reduce data transmission bandwidth for implantable neural recording devices. By doing so, this technique reduces a majority of system power consumption which is dissipated at data readout interface. The design of the system is scalable and is a viable option for large scale integration of electrodes or recording sites onto a single device. The entire system consists of an application-specific integrated circuit (ASIC) with 4 recording readout channels with CS circuits, a real time off-chip CS recovery block and a recovery quality evaluation block that provides a closed feedback to adaptively adjust compression rate. Since CS performance is strongly signal dependent, the ASIC has been tested in vivo and with standard public neural databases. Implemented using efficient digital circuit, this system is able to achieve >10 times data compression on the entire neural spike band (500-6KHz) while consuming only 0.83uW (0.53 V voltage supply) additional digital power per electrode. When only the spikes are desired, the system is able to further compress the detected spikes by around 16 times. Unlike other similar systems, the characteristic spikes and inter-spike data can both be recovered which guarantes a >95% spike classification success rate. The compression circuit occupied 0.11mm(2)/electrode in a 180nm CMOS process. The complete signal processing circuit consumes <16uW/electrode. Power and area efficiency demonstrated by the system make it an ideal candidate for integration into large recording arrays containing thousands of electrode. Closed-loop recording and reconstruction performance evaluation further improves the robustness of the compression method, thus making the system more practical for long term recording.

Full-Circle Resolver-to-Linear-Analog Converter

NASA Technical Reports Server (NTRS)

Alhorn, Dean C.; Smith, Dennis A.; Howard, David E.

2005-01-01

A circuit generates sinusoidal excitation signals for a shaft-angle resolver and, like the arctangent circuit described in the preceding article, generates an analog voltage proportional to the shaft angle. The disadvantages of the circuit described in the preceding article arise from the fact that it must be made from precise analog subcircuits, including a functional block capable of implementing some trigonometric identities; this circuitry tends to be expensive, sensitive to noise, and susceptible to errors caused by temperature-induced drifts and imprecise matching of gains and phases. These disadvantages are overcome by the design of the present circuit. The present circuit (see figure) includes an excitation circuit, which generates signals Ksin(Omega(t)) and Kcos(Omega(t)) [where K is an amplitude, Omega denotes 2(pi)x a carrier frequency (the design value of which is 10 kHz), and t denotes time]. These signals are applied to the excitation terminals of a shaft-angle resolver, causing the resolver to put out signals C sin(Omega(t)-Theta) and C cos(Omega(t)-Theta). The cosine excitation signal and the cosine resolver output signal are processed through inverting comparator circuits, which are configured to function as inverting squarers, to obtain logic-level or square-wave signals .-LL[cos(Omega(t)] and -LL[cos(Omega(t)-Theta)], respectively. These signals are fed as inputs to a block containing digital logic circuits that effectively measure the phase difference (which equals Theta between the two logic-level signals). The output of this block is a pulse-width-modulated signal, PWM(Theta), the time-averaged value of which ranges from 0 to 5 VDC as Theta ranges from .180 to +180deg. PWM(Theta) is fed to a block of amplifying and level-shifting circuitry, which converts the input PWM waveform to an output waveform that switches between precise reference voltage levels of +10 and -10 V. This waveform is processed by a two-pole, low-pass filter, which removes the carrier-frequency component. The final output signal is a DC potential, proportional to Theta that ranges continuously from -10 V at Theta = -180deg to +10 V at Theta = +180deg..

A plausible neural circuit for decision making and its formation based on reinforcement learning.

PubMed

Wei, Hui; Dai, Dawei; Bu, Yijie

2017-06-01

A human's, or lower insects', behavior is dominated by its nervous system. Each stable behavior has its own inner steps and control rules, and is regulated by a neural circuit. Understanding how the brain influences perception, thought, and behavior is a central mandate of neuroscience. The phototactic flight of insects is a widely observed deterministic behavior. Since its movement is not stochastic, the behavior should be dominated by a neural circuit. Based on the basic firing characteristics of biological neurons and the neural circuit's constitution, we designed a plausible neural circuit for this phototactic behavior from logic perspective. The circuit's output layer, which generates a stable spike firing rate to encode flight commands, controls the insect's angular velocity when flying. The firing pattern and connection type of excitatory and inhibitory neurons are considered in this computational model. We simulated the circuit's information processing using a distributed PC array, and used the real-time average firing rate of output neuron clusters to drive a flying behavior simulation. In this paper, we also explored how a correct neural decision circuit is generated from network flow view through a bee's behavior experiment based on the reward and punishment feedback mechanism. The significance of this study: firstly, we designed a neural circuit to achieve the behavioral logic rules by strictly following the electrophysiological characteristics of biological neurons and anatomical facts. Secondly, our circuit's generality permits the design and implementation of behavioral logic rules based on the most general information processing and activity mode of biological neurons. Thirdly, through computer simulation, we achieved new understanding about the cooperative condition upon which multi-neurons achieve some behavioral control. Fourthly, this study aims in understanding the information encoding mechanism and how neural circuits achieve behavior control. Finally, this study also helps establish a transitional bridge between the microscopic activity of the nervous system and macroscopic animal behavior.

Macro- and micronutrient disposition in an ex vivo model of extracorporeal membrane oxygenation.

PubMed

Estensen, Kristine; Shekar, Kiran; Robins, Elissa; McDonald, Charles; Barnett, Adrian G; Fraser, John F

2014-12-01

Extracorporeal membrane oxygenation (ECMO) circuits have been shown to sequester circulating blood compounds such as drugs based on their physicochemical properties. This study aimed to describe the disposition of macro- and micronutrients in simulated ECMO circuits. Following baseline sampling, known quantities of macro- and micronutrients were injected post oxygenator into ex vivo ECMO circuits primed with the fresh human whole blood and maintained under standard physiologic conditions. Serial blood samples were then obtained at 1, 30 and 60 min and at 6, 12 and 24 h after the addition of nutrients, to measure the concentrations of study compounds using validated assays. Twenty-one samples were tested for thirty-one nutrient compounds. There were significant reductions (p < 0.05) in circuit concentrations of some amino acids [alanine (10%), arginine (95%), cysteine (14%), glutamine (25%) and isoleucine (7%)], vitamins [A (42%) and E (6%)] and glucose (42%) over 24 h. Significant increases in circuit concentrations (p < 0.05) were observed over time for many amino acids, zinc and vitamin C. There were no significant reductions in total proteins, triglycerides, total cholesterol, selenium, copper, manganese and vitamin D concentrations within the ECMO circuit over a 24-h period. No clear correlation could be established between physicochemical properties and circuit behaviour of tested nutrients. Significant alterations in macro- and micronutrient concentrations were observed in this single-dose ex vivo circuit study. Most significantly, there is potential for circuit loss of essential amino acid isoleucine and lipid soluble vitamins (A and E) in the ECMO circuit, and the mechanisms for this need further exploration. While the reductions in glucose concentrations and an increase in other macro- and micronutrient concentrations probably reflect cellular metabolism and breakdown, the decrement in arginine and glutamine concentrations may be attributed to their enzymatic conversion to ornithine and glutamate, respectively. While the results are generally reassuring from a macronutrient perspective, prospective studies in clinical subjects are indicated to further evaluate the influence of ECMO circuit on micronutrient concentrations and clinical outcomes.

Tantalum capacitor behavior under fast transient overvoltages. [circuit protection against lightning

NASA Technical Reports Server (NTRS)

Zill, J. A.; Castle, K. D.

1974-01-01

Tantalum capacitors were tested to determine failure time when subjected to short-duration, high-voltage surges caused by lightning strikes. Lightning is of concern to NASA because of possible damage to critical spacecraft circuits. The test was designed to determine the minimum time for tantalum capacitor failure and the amount of overvoltage a capacitor could survive, without permanent damage, in 100 microseconds. All tested exhibited good recovery from the transient one-shot pulses with no failure at any voltage, forward or reverse, in less than 25 microseconds.

Contour Detector and Data Acquisition System for the Left Ventricular Outline

NASA Technical Reports Server (NTRS)

Reiber, J. H. C. (Inventor)

1978-01-01

A real-time contour detector and data acquisition system is described for an angiographic apparatus having a video scanner for converting an X-ray image of a structure characterized by a change in brightness level compared with its surrounding into video format and displaying the X-ray image in recurring video fields. The real-time contour detector and data acqusition system includes track and hold circuits; a reference level analog computer circuit; an analog compartor; a digital processor; a field memory; and a computer interface.

Mixed Signal Learning by Spike Correlation Propagation in Feedback Inhibitory Circuits

PubMed Central

Hiratani, Naoki; Fukai, Tomoki

2015-01-01

The brain can learn and detect mixed input signals masked by various types of noise, and spike-timing-dependent plasticity (STDP) is the candidate synaptic level mechanism. Because sensory inputs typically have spike correlation, and local circuits have dense feedback connections, input spikes cause the propagation of spike correlation in lateral circuits; however, it is largely unknown how this secondary correlation generated by lateral circuits influences learning processes through STDP, or whether it is beneficial to achieve efficient spike-based learning from uncertain stimuli. To explore the answers to these questions, we construct models of feedforward networks with lateral inhibitory circuits and study how propagated correlation influences STDP learning, and what kind of learning algorithm such circuits achieve. We derive analytical conditions at which neurons detect minor signals with STDP, and show that depending on the origin of the noise, different correlation timescales are useful for learning. In particular, we show that non-precise spike correlation is beneficial for learning in the presence of cross-talk noise. We also show that by considering excitatory and inhibitory STDP at lateral connections, the circuit can acquire a lateral structure optimal for signal detection. In addition, we demonstrate that the model performs blind source separation in a manner similar to the sequential sampling approximation of the Bayesian independent component analysis algorithm. Our results provide a basic understanding of STDP learning in feedback circuits by integrating analyses from both dynamical systems and information theory. PMID:25910189

Micro EEG/ECG signal’s chopper-stabilization amplifying chip for novel dry-contact electrode

NASA Astrophysics Data System (ADS)

Sun, Jianhui; Wang, Chunxing; Wang, Gongtang; Wang, Jinhui; Hua, Qing; Cheng, Chuanfu; Cai, Xinxia; Yin, Tao; Yu, Yang; Yang, Haigang; Li, Dengwang

2017-02-01

Facing the body’s EEG (electroencephalograph, 0.5–100 Hz, 5–100 μV) and ECG’s (electrocardiogram, < 100 {Hz}, 0.01–5 mV) micro signal detection requirement, this paper develops a pervasive application micro signal detection ASIC chip with the chopping modulation/demodulation method. The chopper-stabilization circuit with the RRL (ripple reduction loop) circuit is to suppress the ripple voltage, which locates at the single-stage amplifier’s outputting terminal. The single-stage chopping core’s noise has been suppressed too, and it is beneficial for suppressing noises of post-circuit. The chopping core circuit uses the PFB (positive feedback loop) to increase the inputting resistance, and the NFB (negative feedback loop) to stabilize the 40 dB intermediate frequency gain. The cascaded switch-capacitor sample/hold circuit has been used for deleting spike noises caused by non-ideal MOS switches, and the VGA/BPF (voltage gain amplifier/band pass filter) circuit is used to tune the chopper system’s gain/bandwidth digitally. Assisted with the designed novel dry-electrode, the real test result of the chopping amplifying circuit gives some critical parameters: 8.1 μW/channel, 0.8 μVrms (@band-width = 100 Hz), 4216–11220 times digitally tuning gain range, etc. The data capture system uses the NI CO’s data capturing DAQmx interface, and the captured micro EEG/ECG’s waves are real-time displayed with the PC-Labview. The proposed chopper system is a unified EEG/ECG signal’s detection instrument and has a critical real application value. Project supported by the National Natural Science Foundation of China (Nos. 61527815, 31500800, 61501426, 61471342), the National Key Basic Research Plan (No. 2014CB744600), the Beijing Science and Technology Plan (No. Z141100000214002), and the Chinese Academy of Sciences’ Key Project (No. KJZD-EW-L11-2).

Comparative analysis of single-walled and multi-walled carbon nanotubes for electrochemical sensing of glucose on gold printed circuit boards.

PubMed

Alhans, Ruby; Singh, Anukriti; Singhal, Chaitali; Narang, Jagriti; Wadhwa, Shikha; Mathur, Ashish

2018-09-01

In the present work, a comparative study was performed between single-walled carbon nanotubes and multi-walled carbon nanotubes coated gold printed circuit board electrodes for glucose detection. Various characterization techniques were demonstrated in order to compare the modified electrodes viz. cyclic voltammetry, electrochemical impedance spectroscopy and chrono-amperometry. Results revealed that single-walled carbon nanotubes outperformed multi-walled carbon nanotubes and proved to be a better sensing interface for glucose detection. The single-walled carbon nanotubes coated gold printed circuit board electrodes showed a wide linear sensing range (1 mM to 100 mM) with detection limit of 0.1 mM with response time of 5 s while multi-walled carbon nanotubes coated printed circuit board gold electrodes showed linear sensing range (1 mM to 100 mM) with detection limit of 0.1 mM with response time of 5 s. This work provided low cost sensors with enhanced sensitivity, fast response time and reliable results for glucose detection which increased the affordability of such tests in remote areas. In addition, the comparative results confirmed that single-walled carbon nanotubes modified electrodes can be exploited for better amplification signal as compared to multi-walled carbon nanotubes. Copyright © 2018. Published by Elsevier B.V.

Robust wireless power transfer using a nonlinear parity-time-symmetric circuit.

PubMed

Assawaworrarit, Sid; Yu, Xiaofang; Fan, Shanhui

2017-06-14

Considerable progress in wireless power transfer has been made in the realm of non-radiative transfer, which employs magnetic-field coupling in the near field. A combination of circuit resonance and impedance transformation is often used to help to achieve efficient transfer of power over a predetermined distance of about the size of the resonators. The development of non-radiative wireless power transfer has paved the way towards real-world applications such as wireless powering of implantable medical devices and wireless charging of stationary electric vehicles. However, it remains a fundamental challenge to create a wireless power transfer system in which the transfer efficiency is robust against the variation of operating conditions. Here we propose theoretically and demonstrate experimentally that a parity-time-symmetric circuit incorporating a nonlinear gain saturation element provides robust wireless power transfer. Our results show that the transfer efficiency remains near unity over a distance variation of approximately one metre, without the need for any tuning. This is in contrast with conventional methods where high transfer efficiency can only be maintained by constantly tuning the frequency or the internal coupling parameters as the transfer distance or the relative orientation of the source and receiver units is varied. The use of a nonlinear parity-time-symmetric circuit should enable robust wireless power transfer to moving devices or vehicles.

Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II.

PubMed

Keivanian, Farshid; Mehrshad, Nasser; Bijari, Abolfazl

2016-01-01

D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

Robust wireless power transfer using a nonlinear parity-time-symmetric circuit

NASA Astrophysics Data System (ADS)

Assawaworrarit, Sid; Yu, Xiaofang; Fan, Shanhui

2017-06-01

Considerable progress in wireless power transfer has been made in the realm of non-radiative transfer, which employs magnetic-field coupling in the near field. A combination of circuit resonance and impedance transformation is often used to help to achieve efficient transfer of power over a predetermined distance of about the size of the resonators. The development of non-radiative wireless power transfer has paved the way towards real-world applications such as wireless powering of implantable medical devices and wireless charging of stationary electric vehicles. However, it remains a fundamental challenge to create a wireless power transfer system in which the transfer efficiency is robust against the variation of operating conditions. Here we propose theoretically and demonstrate experimentally that a parity-time-symmetric circuit incorporating a nonlinear gain saturation element provides robust wireless power transfer. Our results show that the transfer efficiency remains near unity over a distance variation of approximately one metre, without the need for any tuning. This is in contrast with conventional methods where high transfer efficiency can only be maintained by constantly tuning the frequency or the internal coupling parameters as the transfer distance or the relative orientation of the source and receiver units is varied. The use of a nonlinear parity-time-symmetric circuit should enable robust wireless power transfer to moving devices or vehicles.

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Matching tutors and students: effective strategies for information transfer between circuits

NASA Astrophysics Data System (ADS)

Tesileanu, Tiberiu; Balasubramanian, Vijay; Olveczky, Bence

Many neural circuits transfer learned information to downstream circuits: hippocampal-dependent memories are consolidated into long-term memories elsewhere; motor cortex is essential for skill learning but dispensable for execution; anterior forebrain pathway (AFP) in songbirds drives short-term improvements in song that are later consolidated in pre-motor area RA. We show how to match instructive signals from tutor circuits to synaptic plasticity rules in student circuits to achieve effective two-stage learning. We focus on learning sequential patterns where a timebase is transformed into motor commands by connectivity with a `student' area. If the sign of the synaptic change is given by the magnitude of tutor input, a good teaching strategy uses a strong (weak) tutor signal if student output is below (above) its target. If instead timing of tutor input relative to the timebase determines the sign of synaptic modifications, a good instructive signal accumulates the errors in student output as the motor program progresses. We demonstrate song learning in a biologically-plausible model of the songbird circuit given diverse plasticity rules interpolating between those described above. The model also reproduces qualitative firing statistics of RA neurons in juveniles and adults. Also affiliated to CUNY - Graduate Center.

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis

PubMed Central

Papadimitriou, Konstantinos I.; Liu, Shih-Chii; Indiveri, Giacomo; Drakakis, Emmanuel M.

2014-01-01

The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting from the Bernoulli Cell Formalism (BCF), originally formulated for the modular synthesis and analysis of externally linear, time-invariant logarithmic filters, and by means of the identification of new types of Bernoulli Cell (BC) operators presented here, a generalized formalism (GBCF) is established. The expanded formalism covers two new possible and practical combinations of a MOS transistor (MOST) and a linear capacitor. The corresponding mathematical relations codifying each case are presented and discussed through the tutorial treatment of three well-known transistor-level examples of log-domain neuromorphic silicon synapses. The proposed mathematical tool unifies past analysis approaches of the same circuits under a common theoretical framework. The speed advantage of the proposed mathematical framework as an analysis tool is also demonstrated by a compelling comparative circuit analysis example of high order, where the GBCF and another well-known log-domain circuit analysis method are used for the determination of the input-output transfer function of the high (4th) order topology. PMID:25653579

Artificial immune system algorithm in VLSI circuit configuration

NASA Astrophysics Data System (ADS)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

Verification of the predictive capabilities of the 4C code cryogenic circuit model

NASA Astrophysics Data System (ADS)

Zanino, R.; Bonifetto, R.; Hoa, C.; Richard, L. Savoldi

2014-01-01

The 4C code was developed to model thermal-hydraulics in superconducting magnet systems and related cryogenic circuits. It consists of three coupled modules: a quasi-3D thermal-hydraulic model of the winding; a quasi-3D model of heat conduction in the magnet structures; an object-oriented a-causal model of the cryogenic circuit. In the last couple of years the code and its different modules have undergone a series of validation exercises against experimental data, including also data coming from the supercritical He loop HELIOS at CEA Grenoble. However, all this analysis work was done each time after the experiments had been performed. In this paper a first demonstration is given of the predictive capabilities of the 4C code cryogenic circuit module. To do that, a set of ad-hoc experimental scenarios have been designed, including different heating and control strategies. Simulations with the cryogenic circuit module of 4C have then been performed before the experiment. The comparison presented here between the code predictions and the results of the HELIOS measurements gives the first proof of the excellent predictive capability of the 4C code cryogenic circuit module.

Neuromorphic log-domain silicon synapse circuits obey bernoulli dynamics: a unifying tutorial analysis.

PubMed

Papadimitriou, Konstantinos I; Liu, Shih-Chii; Indiveri, Giacomo; Drakakis, Emmanuel M

2014-01-01

The field of neuromorphic silicon synapse circuits is revisited and a parsimonious mathematical framework able to describe the dynamics of this class of log-domain circuits in the aggregate and in a systematic manner is proposed. Starting from the Bernoulli Cell Formalism (BCF), originally formulated for the modular synthesis and analysis of externally linear, time-invariant logarithmic filters, and by means of the identification of new types of Bernoulli Cell (BC) operators presented here, a generalized formalism (GBCF) is established. The expanded formalism covers two new possible and practical combinations of a MOS transistor (MOST) and a linear capacitor. The corresponding mathematical relations codifying each case are presented and discussed through the tutorial treatment of three well-known transistor-level examples of log-domain neuromorphic silicon synapses. The proposed mathematical tool unifies past analysis approaches of the same circuits under a common theoretical framework. The speed advantage of the proposed mathematical framework as an analysis tool is also demonstrated by a compelling comparative circuit analysis example of high order, where the GBCF and another well-known log-domain circuit analysis method are used for the determination of the input-output transfer function of the high (4(th)) order topology.

Compensation for Lithography Induced Process Variations during Physical Design

NASA Astrophysics Data System (ADS)

Chin, Eric Yiow-Bing

This dissertation addresses the challenge of designing robust integrated circuits in the deep sub micron regime in the presence of lithography process variability. By extending and combining existing process and circuit analysis techniques, flexible software frameworks are developed to provide detailed studies of circuit performance in the presence of lithography variations such as focus and exposure. Applications of these software frameworks to select circuits demonstrate the electrical impact of these variations and provide insight into variability aware compact models that capture the process dependent circuit behavior. These variability aware timing models abstract lithography variability from the process level to the circuit level and are used to estimate path level circuit performance with high accuracy with very little overhead in runtime. The Interconnect Variability Characterization (IVC) framework maps lithography induced geometrical variations at the interconnect level to electrical delay variations. This framework is applied to one dimensional repeater circuits patterned with both 90nm single patterning and 32nm double patterning technologies, under the presence of focus, exposure, and overlay variability. Studies indicate that single and double patterning layouts generally exhibit small variations in delay (between 1--3%) due to self compensating RC effects associated with dense layouts and overlay errors for layouts without self-compensating RC effects. The delay response of each double patterned interconnect structure is fit with a second order polynomial model with focus, exposure, and misalignment parameters with 12 coefficients and residuals of less than 0.1ps. The IVC framework is also applied to a repeater circuit with cascaded interconnect structures to emulate more complex layout scenarios, and it is observed that the variations on each segment average out to reduce the overall delay variation. The Standard Cell Variability Characterization (SCVC) framework advances existing layout-level lithography aware circuit analysis by extending it to cell-level applications utilizing a physically accurate approach that integrates process simulation, compact transistor models, and circuit simulation to characterize electrical cell behavior. This framework is applied to combinational and sequential cells in the Nangate 45nm Open Cell Library, and the timing response of these cells to lithography focus and exposure variations demonstrate Bossung like behavior. This behavior permits the process parameter dependent response to be captured in a nine term variability aware compact model based on Bossung fitting equations. For a two input NAND gate, the variability aware compact model captures the simulated response to an accuracy of 0.3%. The SCVC framework is also applied to investigate advanced process effects including misalignment and layout proximity. The abstraction of process variability from the layout level to the cell level opens up an entire new realm of circuit analysis and optimization and provides a foundation for path level variability analysis without the computationally expensive costs associated with joint process and circuit simulation. The SCVC framework is used with slight modification to illustrate the speedup and accuracy tradeoffs of using compact models. With variability aware compact models, the process dependent performance of a three stage logic circuit can be estimated to an accuracy of 0.7% with a speedup of over 50,000. Path level variability analysis also provides an accurate estimate (within 1%) of ring oscillator period in well under a second. Another significant advantage of variability aware compact models is that they can be easily incorporated into existing design methodologies for design optimization. This is demonstrated by applying cell swapping on a logic circuit to reduce the overall delay variability along a circuit path. By including these variability aware compact models in cell characterization libraries, design metrics such as circuit timing, power, area, and delay variability can be quickly assessed to optimize for the correct balance of all design metrics, including delay variability. Deterministic lithography variations can be easily captured using the variability aware compact models described in this dissertation. However, another prominent source of variability is random dopant fluctuations, which affect transistor threshold voltage and in turn circuit performance. The SCVC framework is utilized to investigate the interactions between deterministic lithography variations and random dopant fluctuations. Monte Carlo studies show that the output delay distribution in the presence of random dopant fluctuations is dependent on lithography focus and exposure conditions, with a 3.6 ps change in standard deviation across the focus exposure process window. This indicates that the electrical impact of random variations is dependent on systematic lithography variations, and this dependency should be included for precise analysis.

An on-chip coupled resonator optical waveguide single-photon buffer

PubMed Central

Takesue, Hiroki; Matsuda, Nobuyuki; Kuramochi, Eiichi; Munro, William J.; Notomi, Masaya

2013-01-01

Integrated quantum optical circuits are now seen as one of the most promising approaches with which to realize single-photon quantum information processing. Many of the core elements for such circuits have been realized, including sources, gates and detectors. However, a significant missing function necessary for photonic quantum information processing on-chip is a buffer, where single photons are stored for a short period of time to facilitate circuit synchronization. Here we report an on-chip single-photon buffer based on coupled resonator optical waveguides (CROW) consisting of 400 high-Q photonic crystal line-defect nanocavities. By using the CROW, a pulsed single photon is successfully buffered for 150 ps with 50-ps tunability while maintaining its non-classical properties. Furthermore, we show that our buffer preserves entanglement by storing and retrieving one photon from a time-bin entangled state. This is a significant step towards an all-optical integrated quantum information processor. PMID:24217422

Efficient Power Network Analysis with Modeling of Inductive Effects

NASA Astrophysics Data System (ADS)

Zeng, Shan; Yu, Wenjian; Hong, Xianlong; Cheng, Chung-Kuan

In this paper, an efficient method is proposed to accurately analyze large-scale power/ground (P/G) networks, where inductive parasitics are modeled with the partial reluctance. The method is based on frequency-domain circuit analysis and the technique of vector fitting [14], and obtains the time-domain voltage response at given P/G nodes. The frequency-domain circuit equation including partial reluctances is derived, and then solved with the GMRES algorithm with rescaling, preconditioning and recycling techniques. With the merit of sparsified reluctance matrix and iterative solving techniques for the frequency-domain circuit equations, the proposed method is able to handle large-scale P/G networks with complete inductive modeling. Numerical results show that the proposed method is orders of magnitude faster than HSPICE, several times faster than INDUCTWISE [4], and capable of handling the inductive P/G structures with more than 100, 000 wire segments.

Auxiliary quasi-resonant dc tank electrical power converter

DOEpatents

Peng, Fang Z.

2006-10-24

An auxiliary quasi-resonant dc tank (AQRDCT) power converter with fast current charging, voltage balancing (or charging), and voltage clamping circuits is provided for achieving soft-switched power conversion. The present invention is an improvement of the invention taught in U.S. Pat. No. 6,111,770, herein incorporated by reference. The present invention provides faster current charging to the resonant inductor, thus minimizing delay time of the pulse width modulation (PWM) due to the soft-switching process. The new AQRDCT converter includes three tank capacitors or power supplies to achieve the faster current charging and minimize the soft-switching time delay. The new AQRDCT converter further includes a voltage balancing circuit to charge and discharge the three tank capacitors so that additional isolated power supplies from the utility line are not needed. A voltage clamping circuit is also included for clamping voltage surge due to the reverse recovery of diodes.

Extracellular space preservation aids the connectomic analysis of neural circuits.

PubMed

Pallotto, Marta; Watkins, Paul V; Fubara, Boma; Singer, Joshua H; Briggman, Kevin L

2015-12-09

Dense connectomic mapping of neuronal circuits is limited by the time and effort required to analyze 3D electron microscopy (EM) datasets. Algorithms designed to automate image segmentation suffer from substantial error rates and require significant manual error correction. Any improvement in segmentation error rates would therefore directly reduce the time required to analyze 3D EM data. We explored preserving extracellular space (ECS) during chemical tissue fixation to improve the ability to segment neurites and to identify synaptic contacts. ECS preserved tissue is easier to segment using machine learning algorithms, leading to significantly reduced error rates. In addition, we observed that electrical synapses are readily identified in ECS preserved tissue. Finally, we determined that antibodies penetrate deep into ECS preserved tissue with only minimal permeabilization, thereby enabling correlated light microscopy (LM) and EM studies. We conclude that preservation of ECS benefits multiple aspects of the connectomic analysis of neural circuits.

Mini Photobioreactors for in Vivo Real-Time Characterization and Evolutionary Tuning of Bacterial Optogenetic Circuit.

PubMed

Wang, Hsinkai; Yang, Ya-Tang

2017-09-15

The current standard protocols for characterizing the optogenetic circuit of bacterial cells using flow cytometry in light tubes and light exposure of culture plates are tedious, labor-intensive, and cumbersome. In this work, we engineer a bioreactor with working volume of ∼10 mL for in vivo real-time optogenetic characterization of E. coli with a CcaS-CcaR light-sensing system. In the bioreactor, optical density measurements, reporter protein fluorescence detection, and light input stimuli are provided by four light-emitting diode sources and two photodetectors. Once calibrated, the device can cultivate microbial cells and record their growth and gene expression without human intervention. We measure gene expression during cell growth with different organic substrates (glucose, succinate, acetate, pyruvate) as carbon sources in minimal medium and demonstrate evolutionary tuning of the optogenetic circuit by serial dilution passages.

Design and testing of a low impedance transceiver circuit for nitrogen-14 nuclear quadrupole resonance.

PubMed

Sato-Akaba, Hideo

2014-01-01

A low impedance transceiver circuit consisting of a transmit-receive switch circuit, a class-D amplifier and a transimpedance amplifier (TIA) was newly designed and tested for a nitrogen-14 NQR. An NQR signal at 1.37MHz from imidazole was successfully observed with the dead time of ~85µs under the high Q transmission (Q~120) and reception (Q~140). The noise performance of the low impedance TIA with an NQR probe was comparable with a commercial low noise 50Ω amplifier (voltage input noise: 0.25 nV/Hz) which was also connected to the probe. The protection voltage for the pre-amplifier using the low impedance transceiver was ~10 times smaller than that for the pre-amplifier using a 50Ω conventional transceiver, which is suitable for NQR remote sensing applications. Copyright © 2014 Elsevier Inc. All rights reserved.