A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

NASA Astrophysics Data System (ADS)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

2018-01-01

In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

MOSFET analog memory circuit achieves long duration signal storage

NASA Technical Reports Server (NTRS)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Organic transistor memory with a charge storage molecular double-floating-gate monolayer.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2015-05-13

A flexible, low-voltage, and nonvolatile memory device was fabricated by implanting a functional monolayer on an aluminum oxide dielectric surface in a pentacene-based organic transistor. The monolayer-forming molecule contains a phosphonic acid group as the anchoring moiety and a charge-trapping core group flanked between two alkyl chain spacers as the charge trapping site. The memory characteristics strongly depend on the monolayer used due to the localized charge-trapping capability for different core groups, including the diacetylenic (DA) unit as the hole carrier trap, the naphthalenetetracarboxyldiimide (ND) unit as the electron carrier trap, and the one with both DA and ND units present, respectively. The device with the monolayer carrying both DA and ND groups has a larger memory window than that for the one containing DA only and a longer retention time than that for the one containing DA or ND only, giving a memory window of 1.4 V and a retention time around 10(9) s. This device with hybrid organic monolayer/inorganic dielectrics also exhibited rather stable device characteristics upon bending of the polymeric substrate.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

Multibit data storage states formed in plasma-treated MoS₂ transistors.

PubMed

Chen, Mikai; Nam, Hongsuk; Wi, Sungjin; Priessnitz, Greg; Gunawan, Ivan Manuel; Liang, Xiaogan

2014-04-22

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

NASA Astrophysics Data System (ADS)

Shin, Sunhae; Rok Kim, Kyung

2015-06-01

In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

The strain and thermal induced tunable charging phenomenon in low power flexible memory arrays with a gold nanoparticle monolayer.

PubMed

Zhou, Ye; Han, Su-Ting; Xu, Zong-Xiang; Roy, V A L

2013-03-07

The strain and temperature dependent memory effect of organic memory transistors on plastic substrates has been investigated under ambient conditions. The gold (Au) nanoparticle monolayer was prepared and embedded in an atomic layer deposited aluminum oxide (Al(2)O(3)) as the charge trapping layer. The devices exhibited low operation voltage, reliable memory characteristics and long data retention time. Experimental analysis of the programming and erasing behavior at various bending states showed the relationship between strain and charging capacity. Thermal-induced effects on these memory devices have also been analyzed. The mobility shows ~200% rise and the memory window increases from 1.48 V to 1.8 V when the temperature rises from 20 °C to 80 °C due to thermally activated transport. The retention capability of the devices decreases with the increased working temperature. Our findings provide a better understanding of flexible organic memory transistors under various operating temperatures and validate their applications in various areas such as temperature sensors, temperature memory or advanced electronic circuits. Furthermore, the low temperature processing procedures of the key elements (Au nanoparticle monolayer and Al(2)O(3) dielectric layer) could be potentially integrated with large area flexible electronics.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Organic-Inorganic Hybrid Halide Perovskites for Memories, Transistors, and Artificial Synapses.

PubMed

Choi, Jaeho; Han, Ji Su; Hong, Kootak; Kim, Soo Young; Jang, Ho Won

2018-05-30

Fascinating characteristics of halide perovskites (HPs), which cannot be seen in conventional semiconductors and metal oxides, have boosted the application of HPs in electronic devices beyond optoelectronics such as solar cells, photodetectors, and light-emitting diodes. Here, recent advances in HP-based memory and logic devices such as resistive-switching memories (i.e., resistive random access memory (RRAM) or memristors), transistors, and artificial synapses are reviewed, focusing on inherently exotic properties of HPs: i) tunable bandgap, ii) facile majority carrier control, iii) fast ion migration, and iv) superflexibility. Various fabrication techniques of HP thin films from solution-based methods to vacuum processes are introduced. Up-to-date work in the field, emphasizing the compositional flexibility of HPs, suggest that HPs are promising candidates for next-generation electronic devices. Taking advantages of their unique electrical properties, low-cost and low-temperature synthesis, and compositional and mechanical flexibility, HPs have enormous potential to provide a new platform for future electronic devices and explosively intensive studies will pave the way in finding new HP materials beyond conventional silicon-based semiconductors to keep up with "More-than-Moore" times. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Characteristics of Reduced Graphene Oxide Quantum Dots for a Flexible Memory Thin Film Transistor.

PubMed

Kim, Yo-Han; Lee, Eun Yeol; Lee, Hyun Ho; Seo, Tae Seok

2017-05-17

Reduced graphene oxide quantum dot (rGOQD) devices in formats of capacitor and thin film transistor (TFT) were demonstrated and examined as the first trial to achieve nonambipolar channel property. In addition, through a gold nanoparticle (Au NP) layer embedded between the rGOQD active channel and dielectric layer, memory capacitor and TFT performances were realized by capacitance-voltage (C-V) hysteresis and gate program, erase, and reprogram biases. First, capacitor structure of the rGOQD memory device was constructed to examine memory charging effect featured in hysteretic C-V behavior with a 30 nm dielectric layer of cross-linked poly(vinyl alcohol). For the intervening Au NP charging layer, self-assembled monolayer (SAM) formation of the Au NP was executed to utilize electrostatic interaction by a dip-coating process under ambient environments with a conformal fabrication uniformity. Second, the rGOQD memory TFT device was also constructed in the same format of the Au NPs SAMs on a flexible substrate. Characteristics of the rGOQD TFT output showed novel saturation curves unlike typical graphene-based TFTs. However, The rGOQD TFT device reveals relatively low on/off ratio of 10 1 and mobility of 5.005 cm 2 /V·s. For the memory capacitor, the flat-band voltage shift (ΔV FB ) was measured as 3.74 V for ±10 V sweep, and for the memory TFT, the threshold voltage shift (ΔV th ) by the Au NP charging was detected as 7.84 V. In summary, it was concluded that the rGOQD memory device could accomplish an ideal graphene-based memory performance, which could have provided a wide memory window and saturated output characteristics.

Copper atomic-scale transistors.

PubMed

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

High Density Memory Based on Quantum Device Technology

NASA Technical Reports Server (NTRS)

vanderWagt, Paul; Frazier, Gary; Tang, Hao

1995-01-01

We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Fabrication of one-transistor-capacitor structure of nonvolatile TFT ferroelectric RAM devices using Ba(Zr0.1Ti0.9)O3 gated oxide film.

PubMed

Yang, Cheng-Fu; Chen, Kai-Huang; Chen, Ying-Chung; Chang, Ting-Chang

2007-09-01

In this study, the Ba(Zr0.1Ti0.9)O3 (BZ1T9) thin films have been well deposited on the Pt/Ti/SiO2/Si substrate. The optimum radio frequency (RF) deposition parameters are developed, and the BZ1T9 thin films deposition at the optimum parameters have the maximum capacitance and dielectric constant of 4.4 nF and 190. As the applied voltage is increased to 8 V, the remnant polarization and coercive field of BZ1T9 thin films are about 4.5 microC/cm2 and 80 kV/cm. The counterclockwise current hysteresis and memory window of n-channel thin-film transistor property are observed, and that can be used to indicate the switching of ferroelectric polarization of BZ1T9 thin films. One-transistor-capacitor (1TC) structure of BZ1T9 ferroelectric random access memory device using bottom-gate amorphous silicon thin-film transistor was desirable because of the smaller size and better sensitivity. The BZ1T9 ferroelectric RAM devices with channel width = 40 microm and channel length = 8 microm has been successfully fabricated and the ID-VG transfer characteristics also are investigated in this study.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Quantum Optical Transistor and Other Devices Based on Nanostructures

NASA Astrophysics Data System (ADS)

Li, Jin-Jin; Zhu, Ka-Di

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to nanostructures. This provides an important clue toward the realization of quantum optical devices, such as quantum optical transistor, slow light device, fast light device, or light storage device. In contrast to conventional electronic transistor, a quantum optical transistor uses photons as signal carriers rather than electrons, which has a faster and more powerful transfer efficiency. Under the radiation of a strong pump laser, a signal laser can be amplified or attenuated via passing through a single quantum dot coupled to a photonic crystal (PC) nanocavity system. Such a switching and amplifying behavior can really implement the quantum optical transistor. By simply turning on or off the input pump laser, the amplified or attenuated signal laser can be obtained immediately. Based on this transistor, we further propose a method to measure the vacuum Rabi splitting of exciton in all-optical domain. Besides, we study the light propagation in a coupled QD and nanomechanical resonator (NR) system. We demonstrate that it is possible to achieve the slow light, fast light, and quantum memory for light on demand, which is based on the mechanically induced coherent population oscillation (MICPO) and exciton polaritons. These QD devices offer a route toward the use of all-optical technique to investigate the coupled QD systems and will make contributions to quantum internets and quantum computers.

CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

NASA Astrophysics Data System (ADS)

Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

2008-05-01

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

1T1R Nonvolatile Memory with Al/TiO₂/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor.

PubMed

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-12-09

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 5 cm²/Vs, low threshold voltage of -1.1 V, and low leakage current of 10 -12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO₂-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations

NASA Astrophysics Data System (ADS)

Choi, Shinhyun; Tan, Scott H.; Li, Zefan; Kim, Yunjo; Choi, Chanyeol; Chen, Pai-Yu; Yeon, Hanwool; Yu, Shimeng; Kim, Jeehwan

2018-01-01

Although several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on—formation of filaments in an amorphous medium—is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Synaptic plasticity functions in an organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Schaefer, Nathan; Strakosas, Xenofon; Fairfield, Jessamyn A.; Malliaras, George G.

2015-12-01

Synaptic plasticity functions play a crucial role in the transmission of neural signals in the brain. Short-term plasticity is required for the transmission, encoding, and filtering of the neural signal, whereas long-term plasticity establishes more permanent changes in neural microcircuitry and thus underlies memory and learning. The realization of bioinspired circuits that can actually mimic signal processing in the brain demands the reproduction of both short- and long-term aspects of synaptic plasticity in a single device. Here, we demonstrate the implementation of neuromorphic functions similar to biological memory, such as short- to long-term memory transition, in non-volatile organic electrochemical transistors (OECTs). Depending on the training of the OECT, the device displays either short- or long-term plasticity, therefore, exhibiting non von Neumann characteristics with merged processing and storing functionalities. These results are a first step towards the implementation of organic-based neuromorphic circuits.

Copper atomic-scale transistors

PubMed Central

Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors. PMID:28382242

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

NASA Astrophysics Data System (ADS)

Ascenso Simões, Bruno

Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values. The CNT transistors with field tunable band gaps would facilitate field programmable circuits based on the self-organized CNTs, and might also lead to novel analog memory, neuromorphic, and photonic devices.

Organic Ferroelectric-Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half-Selection Problem.

PubMed

Zhao, Qiang; Wang, Hanlin; Ni, Zhenjie; Liu, Jie; Zhen, Yonggang; Zhang, Xiaotao; Jiang, Lang; Li, Rongjin; Dong, Huanli; Hu, Wenping

2017-09-01

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF-TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low-cost and easy-fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half-selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm 2 V -1 s -1 (average) for 2,6-diphenylanthracene (DPA) and electron mobility of 0.124 cm 2 V -1 s -1 (average) for N,N'-1H,1H-perfluorobutyl dicyanoperylenecarboxydiimide (PDI-FCN 2 ) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric-based pixelated memory module fabrication. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

2016-05-01

The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00505e

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

1T1R Nonvolatile Memory with Al/TiO2/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor

PubMed Central

Lee, Ke-Jing; Chang, Yu-Chi; Lee, Cheng-Jung; Wang, Li-Wen; Wang, Yeong-Her

2017-01-01

A one-transistor and one-resistor (1T1R) architecture with a resistive random access memory (RRAM) cell connected to an organic thin-film transistor (OTFT) device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN) as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 2.5 cm2/Vs, low threshold voltage of −2.8 V, and low leakage current of 10−12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO2-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA) and reliable data retention (over ten years). This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II) acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications. PMID:29232828

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

FinFET memory cell improvements for higher immunity against single event upsets

NASA Astrophysics Data System (ADS)

Sajit, Ahmed Sattar

The 21st century is witnessing a tremendous demand for transistors. Life amenities have incorporated the transistor in every aspect of daily life, ranging from toys to rocket science. Day by day, scaling down the transistor is becoming an imperious necessity. However, it is not a straightforward process; instead, it faces overwhelming challenges. Due to these scaling changes, new technologies, such as FinFETs for example, have emerged as alternatives to the conventional bulk-CMOS technology. FinFET has more control over the channel, therefore, leakage current is reduced. FinFET could bridge the gap between silicon devices and non-silicon devices. The semiconductor industry is now incorporating FinFETs in systems and subsystems. For example, Intel has been using them in their newest processors, delivering potential saving powers and increased speeds to memory circuits. Memory sub-systems are considered a vital component in the digital era. In memory, few rows are read or written at a time, while the most rows are static; hence, reducing leakage current increases the performance. However, as a transistor shrinks, it becomes more vulnerable to the effects from radioactive particle strikes. If a particle hits a node in a memory cell, the content might flip; consequently, leading to corrupting stored data. Critical fields, such as medical and aerospace, where there are no second chances and cannot even afford to operate at 99.99% accuracy, has induced me to find a rigid circuit in a radiated working environment. This research focuses on a wide spectrum of memories such as 6T SRAM, 8T SRAM, and DICE memory cells using FinFET technology and finding the best platform in terms of Read and Write delay, susceptibility level of SNM, RSNM, leakage current, energy consumption, and Single Event Upsets (SEUs). This research has shown that the SEU tolerance that 6T and 8T FinFET SRAMs provide may not be acceptable in medical and aerospace applications where there is a very high likelihood of SEUs. Consequently, FinFET DICE memory can be a good candidate due to its high ability to tolerate SEUs of different amplitudes and long periods for both read and hold operations.

Li-ion synaptic transistor for low power analog computing

DOE PAGES

Fuller, Elliot J.; Gabaly, Farid El; Leonard, Francois; ...

2016-11-22

Nonvolatile redox transistors (NVRTs) based upon Li-ion battery materials are demonstrated as memory elements for neuromorphic computer architectures with multi-level analog states, “write” linearity, low-voltage switching, and low power dissipation. Simulations of back propagation using the device properties reach ideal classification accuracy. Finally, physics-based simulations predict energy costs per “write” operation of <10 aJ when scaled to 200 nm × 200 nm.

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Evaluation of 1.5-T Cell Flash Memory Total Ionizing Dose Response

NASA Astrophysics Data System (ADS)

Clark, Lawrence T.; Holbert, Keith E.; Adams, James W.; Navale, Harshad; Anderson, Blake C.

2015-12-01

Flash memory is an essential part of systems used in harsh environments, experienced by both terrestrial and aerospace TID applications. This paper presents studies of COTS flash memory TID hardness. While there is substantial literature on flash memory TID response, this work focuses for the first time on 1.5 transistor per cell flash memory. The experimental results show hardness varying from about 100 krad(Si) to over 250 krad(Si) depending on the usage model. We explore the circuit and device aspects of the results, based on the extensive reliability literature for this flash memory type. Failure modes indicate both device damage and circuit marginalities. Sector erase failure limits, but read only operation allows TID exceeding 200 krad(Si). The failures are analyzed by type.

End-group-directed self-assembly of organic compounds useful for photovoltaic applications

DOEpatents

Beaujuge, Pierre M.; Lee, Olivia P.; Yiu, Alan T.; Frechet, Jean M.J.

2016-05-31

The present invention provides for an organic compound comprising electron deficient unit covalently linked to two or more electron rich units. The present invention also provides for a device comprising the organic compound, such as a light-emitting diode, thin-film transistor, chemical biosensor, non-emissive electrochromic, memory device, photovoltaic cells, or the like.

Novel nano materials for high performance logic and memory devices

NASA Astrophysics Data System (ADS)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect mobility with the layer thickness. The non-monotonic trend suggests that in order to harvest the maximum potential of MoS2 for high performance device applications, a layer thickness in the range of 6-12 nm would be ideal. Finally using scandium contacts on 10nm thick exfoliated MoS2 flakes that are covered by a 15nm ALD grown Al2O3 film, record high mobility of 700cm2/Vs is achieved at room-temperature which is extremely encouraging for the design of high performance logic devices. The destructive nature of the readout process in Ferroelectric Random Access Memories (FeRAMs) is one of the major limiting factors for their wide scale commercialization. Utilizing Ferroelectric Field-Effect Transistor RAM (FeTRAM) instead solves the destructive read out problem, but at the expense of introducing crystalline ferroelectrics that are hard to integrate into CMOS. In order to address these challenges a novel, fully functional, CMOS compatible, One-Transistor-One-Transistor (1T1T) memory cell architecture using an organic ferroelectric -- PVDF-TrFE -- as the memory storage unit (gate oxide) and a silicon nanowire as the memory read out unit (channel material) is proposed and experimentally demonstrated. While evaluating the scaling potential of the above mentioned organic FeTRAM, it is found that the switching time and switching voltage of this organic copolymer PVDF-TrFE exhibits an unexpected scaling behavior as a function of the lateral device dimensions. The phenomenological theory, that explains this abnormal scaling trend, involves in-plane interchain and intrachain interaction of the copolymer - resulting in a power-law dependence of the switching field on the device area (ESW alpha ACH0.1) that is ultimately responsible for the decrease in the switching time and switching voltage. These findings are encouraging since they indicate that scaling the switching voltage and switching time without aggressively scaling the copolymer thickness occurs naturally while scaling the device area -- in this way ultimately improving the packing density and leading towards high performance memory devices.

Synaptic organic transistors with a vacuum-deposited charge-trapping nanosheet

NASA Astrophysics Data System (ADS)

Kim, Chang-Hyun; Sung, Sujin; Yoon, Myung-Han

2016-09-01

Organic neuromorphic devices hold great promise for unconventional signal processing and efficient human-machine interfaces. Herein, we propose novel synaptic organic transistors devised to overcome the traditional trade-off between channel conductance and memory performance. A vacuum-processed, nanoscale metallic interlayer provides an ultra-flat surface for a high-mobility molecular film as well as a desirable degree of charge trapping, allowing for low-temperature fabrication of uniform device arrays on plastic. The device architecture is implemented by widely available electronic materials in combination with conventional deposition methods. Therefore, our results are expected to generate broader interests in incorporation of organic electronics into large-area neuromorphic systems, with potential in gate-addressable complex logic circuits and transparent multifunctional interfaces receiving direct optical and cellular stimulation.

Organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Epitaxial Growth of Thin Ferroelectric Polymer Films on Graphene Layer for Fully Transparent and Flexible Nonvolatile Memory.

PubMed

Kim, Kang Lib; Lee, Wonho; Hwang, Sun Kak; Joo, Se Hun; Cho, Suk Man; Song, Giyoung; Cho, Sung Hwan; Jeong, Beomjin; Hwang, Ihn; Ahn, Jong-Hyun; Yu, Young-Jun; Shin, Tae Joo; Kwak, Sang Kyu; Kang, Seok Ju; Park, Cheolmin

2016-01-13

Enhancing the device performance of organic memory devices while providing high optical transparency and mechanical flexibility requires an optimized combination of functional materials and smart device architecture design. However, it remains a great challenge to realize fully functional transparent and mechanically durable nonvolatile memory because of the limitations of conventional rigid, opaque metal electrodes. Here, we demonstrate ferroelectric nonvolatile memory devices that use graphene electrodes as the epitaxial growth substrate for crystalline poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) polymer. The strong crystallographic interaction between PVDF-TrFE and graphene results in the orientation of the crystals with distinct symmetry, which is favorable for polarization switching upon the electric field. The epitaxial growth of PVDF-TrFE on a graphene layer thus provides excellent ferroelectric performance with high remnant polarization in metal/ferroelectric polymer/metal devices. Furthermore, a fully transparent and flexible array of ferroelectric field effect transistors was successfully realized by adopting transparent poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] semiconducting polymer.

High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

PubMed

Jung, Ji Hyung; Kim, Sunghwan; Kim, Hyeonjung; Park, Jongnam; Oh, Joon Hak

2015-10-07

Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Sketched oxide single-electron transistor

NASA Astrophysics Data System (ADS)

Cheng, Guanglei; Siles, Pablo F.; Bi, Feng; Cen, Cheng; Bogorin, Daniela F.; Bark, Chung Wung; Folkman, Chad M.; Park, Jae-Wan; Eom, Chang-Beom; Medeiros-Ribeiro, Gilberto; Levy, Jeremy

2011-06-01

Devices that confine and process single electrons represent an important scaling limit of electronics. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties. Here, we use an atomic force microscope tip to reversibly `sketch' single-electron transistors by controlling a metal-insulator transition at the interface of two oxides. In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ~1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.

Thermal annealing and temperature dependences of memory effect in organic memory transistor

NASA Astrophysics Data System (ADS)

Ren, X. C.; Wang, S. M.; Leung, C. W.; Yan, F.; Chan, P. K. L.

2011-07-01

We investigate the annealing and thermal effects of organic non-volatile memory with floating silver nanoparticles by real-time transfer curve measurements. During annealing, the memory window shows shrinkage of 23% due to structural variation of the nanoparticles. However, by increasing the device operating temperature from 20 to 90 °C after annealing, the memory window demonstrates an enlargement up to 100%. The differences in the thermal responses are explained and confirmed by the co-existence of electron and hole traps. Our findings provide a better understanding of organic memory performances under various operating temperatures and validate their applications for temperature sensing or thermal memories.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Synaptic organic transistors with a vacuum-deposited charge-trapping nanosheet

PubMed Central

Kim, Chang-Hyun; Sung, Sujin; Yoon, Myung-Han

2016-01-01

Organic neuromorphic devices hold great promise for unconventional signal processing and efficient human-machine interfaces. Herein, we propose novel synaptic organic transistors devised to overcome the traditional trade-off between channel conductance and memory performance. A vacuum-processed, nanoscale metallic interlayer provides an ultra-flat surface for a high-mobility molecular film as well as a desirable degree of charge trapping, allowing for low-temperature fabrication of uniform device arrays on plastic. The device architecture is implemented by widely available electronic materials in combination with conventional deposition methods. Therefore, our results are expected to generate broader interests in incorporation of organic electronics into large-area neuromorphic systems, with potential in gate-addressable complex logic circuits and transparent multifunctional interfaces receiving direct optical and cellular stimulation. PMID:27645425

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

PubMed Central

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-01-01

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

NASA Astrophysics Data System (ADS)

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-06-01

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

Long-term reliable physically unclonable function based on oxide tunnel barrier breakdown on two-transistors two-magnetic-tunnel-junctions cell-based embedded spin transfer torque magnetoresistive random access memory

NASA Astrophysics Data System (ADS)

Takaya, Satoshi; Tanamoto, Tetsufumi; Noguchi, Hiroki; Ikegami, Kazutaka; Abe, Keiko; Fujita, Shinobu

2017-04-01

Among the diverse applications of spintronics, security for internet-of-things (IoT) devices is one of the most important. A physically unclonable function (PUF) with a spin device (spin transfer torque magnetoresistive random access memory, STT-MRAM) is presented. Oxide tunnel barrier breakdown is used to realize long-term stability for PUFs. A secure PUF has been confirmed by evaluating the Hamming distance of a 32-bit STT-MRAM-PUF fabricated using 65 nm CMOS technology.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung

Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while themore » electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.« less

Sketched Oxide Single-Electron Transistor

NASA Astrophysics Data System (ADS)

Cheng, Guanglei

2012-02-01

Devices that confine and process single electrons represent an important scaling limit of electronics. Such devices have been realized in a variety of materials and exhibit remarkable electronic, optical and spintronic properties. Here, we use an atomic force microscope tip to reversibly ``sketch'' single-electron transistors by controlling a metal-insulator transition at the interface of two oxides.ootnotetextCheng et al., Nature Nanotechnology 6, 343 (2011). In these devices, single electrons tunnel resonantly between source and drain electrodes through a conducting oxide island with a diameter of ˜1.5 nm. We demonstrate control over the number of electrons on the island using bottom- and side-gate electrodes, and observe hysteresis in electron occupation that is attributed to ferroelectricity within the oxide heterostructure. These single-electron devices may find use as ultradense non-volatile memories, nanoscale hybrid piezoelectric and charge sensors, as well as building blocks in quantum information processing and simulation platforms.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Synaptic plasticity and oscillation at zinc tin oxide/silver oxide interfaces

NASA Astrophysics Data System (ADS)

Murdoch, Billy J.; McCulloch, Dougal G.; Partridge, James G.

2017-02-01

Short-term plasticity, long-term potentiation, and pulse interval dependent plasticity learning/memory functions have been observed in junctions between amorphous zinc-tin-oxide and silver-oxide. The same junctions exhibited current-controlled negative differential resistance and when connected in an appropriate circuit, they behaved as relaxation oscillators. These oscillators produced voltage pulses suitable for device programming. Transmission electron microscopy, energy dispersive X-ray spectroscopy, and electrical measurements suggest that the characteristics of these junctions arise from Ag+/O- electromigration across a highly resistive interface layer. With memory/learning functions and programming spikes provided in a single device structure, arrays of similar devices could be used to form transistor-free neuromorphic circuits.

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Oxide-based thin film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

He, Yongli; Wang, Xiangyu; Gao, Ya; Hou, Yahui; Wan, Qing

2018-01-01

The continuous progress in thin film materials and devices has greatly promoted the development in the field of flexible electronics. As one of the most common thin film devices, thin film transistors (TFTs) are significant building blocks for flexible platforms. Flexible oxide-based TFTs are well compatible with flexible electronic systems due to low process temperature, high carrier mobility, and good uniformity. The present article is a review of the recent progress and major trends in the field of flexible oxide-based thin film transistors. First, an introduction of flexible electronics and flexible oxide-based thin film transistors is given. Next, we introduce oxide semiconductor materials and various flexible oxide-based TFTs classified by substrate materials including polymer plastics, paper sheets, metal foils, and flexible thin glass. Afterwards, applications of flexible oxide-based TFTs including bendable sensors, memories, circuits, and displays are presented. Finally, we give conclusions and a prospect for possible development trends. Project supported in part by the National Science Foundation for Distinguished Young Scholars of China (No. 61425020), in part by the National Natural Science Foundation of China (No. 11674162).

High-temperature performance of MoS2 thin-film transistors: Direct current and pulse current-voltage characteristics

NASA Astrophysics Data System (ADS)

Jiang, C.; Rumyantsev, S. L.; Samnakay, R.; Shur, M. S.; Balandin, A. A.

2015-02-01

We report on fabrication of MoS2 thin-film transistors (TFTs) and experimental investigations of their high-temperature current-voltage characteristics. The measurements show that MoS2 devices remain functional to temperatures of at least as high as 500 K. The temperature increase results in decreased threshold voltage and mobility. The comparison of the direct current (DC) and pulse measurements shows that the direct current sub-linear and super-linear output characteristics of MoS2 thin-films devices result from the Joule heating and the interplay of the threshold voltage and mobility temperature dependences. At temperatures above 450 K, a kink in the drain current occurs at zero gate voltage irrespective of the threshold voltage value. This intriguing phenomenon, referred to as a "memory step," was attributed to the slow relaxation processes in thin films similar to those in graphene and electron glasses. The fabricated MoS2 thin-film transistors demonstrated stable operation after two months of aging. The obtained results suggest new applications for MoS2 thin-film transistors in extreme-temperature electronics and sensors.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

NASA Astrophysics Data System (ADS)

Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

2011-08-01

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Photonic band gap materials: towards an all-optical transistor

NASA Astrophysics Data System (ADS)

Florescu, Marian

2002-05-01

The transmission of information as optical signals encoded on light waves traveling through optical fibers and optical networks is increasingly moving to shorter and shorter distance scales. In the near future, optical networking is poised to supersede conventional transmission over electric wires and electronic networks for computer-to-computer communications, chip-to-chip communications, and even on-chip communications. The ever-increasing demand for faster and more reliable devices to process the optical signals offers new opportunities in developing all-optical signal processing systems (systems in which one optical signal controls another, thereby adding "intelligence" to the optical networks). All-optical switches, two-state and many-state all-optical memories, all-optical limiters, all-optical discriminators and all-optical transistors are only a few of the many devices proposed during the last two decades. The "all-optical" label is commonly used to distinguish the devices that do not involve dissipative electronic transport and require essentially no electrical communication of information. The all-optical transistor action was first observed in the context of optical bistability [1] and consists in a strong differential gain regime, in which, for small variations in the input intensity, the output intensity has a very strong variation. This analog operation is for all-optical input what transistor action is for electrical inputs.

Low-power integrated-circuit driver for ferrite-memory word lines

NASA Technical Reports Server (NTRS)

Katz, S.

1970-01-01

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Particle sensor array

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor); Lieneweg, Udo (Inventor)

1994-01-01

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Hysteresis in the transfer characteristics of MoS2 transistors

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Genovese, Luca; Giubileo, Filippo; Iemmo, Laura; Luongo, Giuseppe; Foller, Tobias; Schleberger, Marika

2018-01-01

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

Materials and methods for the preparation of nanocomposites

DOEpatents

Talapin, Dmitri V.; Kovalenko, Maksym V.; Lee, Jong-Soo; Jiang, Chengyang

2016-05-24

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a solution of the same, a method for making the same from a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, imaging devices, phase change layers, and sensor devices.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Sayyah, Rana; Ho, Fat D.

2009-01-01

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

Development and characterization of a ferroelectric non-volatile memory for flexible electronics

NASA Astrophysics Data System (ADS)

Mao, Duo

Flexible electronics have received significant attention recently because of the potential applications in displays, sensors, radio frequency identification (RFID) tags and other integrated circuits. Electrically addressable non-volatile memory is a key component for these applications. The major challenges are to fabricate the memory at a low temperature compatible with plastic substrates while maintaining good device reliability, by being compatible with process as needed to integrate with other electronic components for system-on-chip applications. In this work, ferroelectric capacitors fabricated at low temperature were developed. Based on that, a ferroelectric random access memory (FRAM) for flexible electronics was developed and characterized. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer was used as a ferroelectric material and a photolithographic process was developed to fabricate ferroelectric capacitors. Different characterization methods including atomic force microscopy, x-ray diffraction and Fourier-transform infrared reflection-absorption spectroscopy were used to study the material properties of the P(VDF-TrFE) film. The material properties were correlated with the electrical characteristics of the ferroelectric capacitors. To understand the polarization switching behavior of the P(VDF-TrFE) ferroelectric capacitors, a Nucleation-Limited-Switching (NLS) model was used to study the switching kinetics. The switching kinetics were characterized over the temperature range from -60 °C to 100 °C. Fatigue characteristics were studied at different electrical stress voltages and frequencies to evaluate the reliability of the ferroelectric capacitor. The degradation mechanism is attributed to the increase of the activation field and the suppression of the switchable polarization. To develop a FRAM circuit for flexible electronics, an n-channel thin film transistor (TFT) based on CdS as the semiconductor was integrated with a P(VDF-TrFE) ferroelectric capacitor for a one-transistor-one-capacitor (1T1C) memory cell. The 1T1C devices were fabricated at low temperature and demonstrated a memory window (DeltaVBL) of 2.3 V and 3.5 V, depending on the device dimensions. Next, FRAM arrays (4-bit, 16-bit and 64-bit) based on the two-transistor-two-capacitor (2T2C) memory cell architecture were designed and fabricated using a photolithographic process with 9 masks. The fabricated FRAM arrays were packaged in 28-pin ceramic packages. The read/write schemes were developed and the FRAM arrays show successful program and erase with a memory window of approximately 1 V at the output of the sense amplifier.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories

NASA Astrophysics Data System (ADS)

Akkala, Arun Goud

Leakage currents in CMOS transistors have risen dramatically with technology scaling leading to significant increase in standby power consumption. Among the various transistor candidates, the excellent short channel immunity of Silicon double gate FinFETs have made them the best contender for successful scaling to sub-10nm nodes. For sub-10nm FinFETs, new quantum mechanical leakage mechanisms such as direct source to drain tunneling (DSDT) of charge carriers through channel potential energy barrier arising due to proximity of source/drain regions coupled with the high transport direction electric field is expected to dominate overall leakage. To counter the effects of DSDT and worsening short channel effects and to maintain Ion/ Ioff, performance and power consumption at reasonable values, device optimization techniques are necessary for deeply scaled transistors. In this work, source/drain underlapping of FinFETs has been explored using quantum mechanical device simulations as a potentially promising method to lower DSDT while maintaining the Ion/ Ioff ratio at acceptable levels. By adopting a device/circuit/system level co-design approach, it is shown that asymmetric underlapping, where the drain side underlap is longer than the source side underlap, results in optimal energy efficiency for logic circuits in near-threshold as well as standard, super-threshold operating regimes. In addition, read/write conflict in 6T SRAMs and the degradation in cell noise margins due to the low supply voltage can be mitigated by using optimized asymmetric underlapped n-FinFETs for the access transistor, thereby leading to robust cache memories. When gate-workfunction tuning is possible, using asymmetric underlapped n-FinFETs for both access and pull-down devices in an SRAM bit cell can lead to high-speed and low-leakage caches. Further, it is shown that threshold voltage degradation in the presence of Hot Carrier Injection (HCI) is less severe in asymmetric underlap n-FinFETs. A lifetime projection is carried out assuming that HCI is the major degradation mechanism and it is shown that a 3.4x improvement in device lifetime is possible over symmetric underlapped n-FinFET.

Materials and methods for the preparation of nanocomposites

DOEpatents

Nag, Angshuman; Talapin, Dmitri V.

2018-01-30

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics

PubMed Central

Bae, Yoon Cheol; Lee, Ah Rahm; Baek, Gwang Ho; Chung, Je Bock; Kim, Tae Yoon; Park, Jea Gun; Hong, Jin Pyo

2015-01-01

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes. PMID:26289565

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

Total ionizing dose effect in an input/output device for flash memory

NASA Astrophysics Data System (ADS)

Liu, Zhang-Li; Hu, Zhi-Yuan; Zhang, Zheng-Xuan; Shao, Hua; Chen, Ming; Bi, Da-Wei; Ning, Bing-Xu; Zou, Shi-Chang

2011-12-01

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.

Artificial Synaptic Devices Based on Natural Chicken Albumen Coupled Electric-Double-Layer Transistors

NASA Astrophysics Data System (ADS)

Wu, Guodong; Feng, Ping; Wan, Xiang; Zhu, Liqiang; Shi, Yi; Wan, Qing

2016-03-01

Recent progress in using biomaterials to fabricate functional electronics has got growing attention for the new generation of environmentally friendly and biocompatible electronic devices. As a kind of biological material with rich source, proteins are essential natural component of all organisms. At the same time, artificial synaptic devices are of great significance for neuromorphic systems because they can emulate the signal process and memory behaviors of biological synapses. In this report, natural chicken albumen with high proton conductivity was used as the coupling electrolyte film for organic/inorganic hybrid synaptic devices fabrication. Some important synaptic functions including paired-pulse facilitation, dynamic filtering, short-term to long-term memory transition and spatial summation and shunting inhibition were successfully mimicked. Our results are very interesting for biological friendly artificial neuron networks and neuromorphic systems.

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

Accurate electrical prediction of memory array through SEM-based edge-contour extraction using SPICE simulation

NASA Astrophysics Data System (ADS)

Shauly, Eitan; Rotstein, Israel; Peltinov, Ram; Latinski, Sergei; Adan, Ofer; Levi, Shimon; Menadeva, Ovadya

2009-03-01

The continues transistors scaling efforts, for smaller devices, similar (or larger) drive current/um and faster devices, increase the challenge to predict and to control the transistor off-state current. Typically, electrical simulators like SPICE, are using the design intent (as-drawn GDS data). At more sophisticated cases, the simulators are fed with the pattern after lithography and etch process simulations. As the importance of electrical simulation accuracy is increasing and leakage is becoming more dominant, there is a need to feed these simulators, with more accurate information extracted from physical on-silicon transistors. Our methodology to predict changes in device performances due to systematic lithography and etch effects was used in this paper. In general, the methodology consists on using the OPCCmaxTM for systematic Edge-Contour-Extraction (ECE) from transistors, taking along the manufacturing and includes any image distortions like line-end shortening, corner rounding and line-edge roughness. These measurements are used for SPICE modeling. Possible application of this new metrology is to provide a-head of time, physical and electrical statistical data improving time to market. In this work, we applied our methodology to analyze a small and large array's of 2.14um2 6T-SRAM, manufactured using Tower Standard Logic for General Purposes Platform. 4 out of the 6 transistors used "U-Shape AA", known to have higher variability. The predicted electrical performances of the transistors drive current and leakage current, in terms of nominal values and variability are presented. We also used the methodology to analyze an entire SRAM Block array. Study of an isolation leakage and variability are presented.

Ionic current devices-Recent progress in the merging of electronic, microfluidic, and biomimetic structures.

PubMed

Koo, Hyung-Jun; Velev, Orlin D

2013-05-09

We review the recent progress in the emerging area of devices and circuits operating on the basis of ionic currents. These devices operate at the intersection of electrochemistry, electronics, and microfluidics, and their potential applications are inspired by essential biological processes such as neural transmission. Ionic current rectification has been demonstrated in diode-like devices containing electrolyte solutions, hydrogel, or hydrated nanofilms. More complex functions have been realized in ionic current based transistors, solar cells, and switching memory devices. Microfluidic channels and networks-an intrinsic component of the ionic devices-could play the role of wires and circuits in conventional electronics.

Rapid synthesis and decoration of reduced graphene oxide with gold nanoparticles by thermostable peptides for memory device and photothermal applications.

PubMed

Otari, Sachin V; Kumar, Manoj; Anwar, Muhammad Zahid; Thorat, Nanasaheb D; Patel, Sanjay K S; Lee, Dongjin; Lee, Jai Hyo; Lee, Jung-Kul; Kang, Yun Chan; Zhang, Liaoyuan

2017-09-08

This article presents novel, rapid, and environmentally benign synthesis method for one-step reduction and decoration of graphene oxide with gold nanoparticles (NAuNPs) by using thermostable antimicrobial nisin peptides to form a gold-nanoparticles-reduced graphene oxide (NAu-rGO) nanocomposite. The formed composite material was characterized by UV/Vis spectroscopy, X-ray diffraction, Raman spectroscopy, X-ray photoelectron spectroscopy, field emission scanning electron microscopy, and high-resolution transmission electron microscopy (HR-TEM). HR-TEM analysis revealed the formation of spherical AuNPs of 5-30 nm in size on reduced graphene oxide (rGO) nanosheets. A non-volatile-memory device was prepared based on a solution-processed ZnO thin-film transistor fabricated by inserting the NAu-rGO nanocomposite in the gate dielectric stack as a charge trapping medium. The transfer characteristic of the ZnO thin-film transistor memory device showed large clockwise hysteresis behaviour because of charge carrier trapping in the NAu-rGO nanocomposite. Under positive and negative bias conditions, clear positive and negative threshold voltage shifts occurred, which were attributed to charge carrier trapping and de-trapping in the ZnO/NAu-rGO/SiO 2 structure. Also, the photothermal effect of the NAu-rGO nanocomposites on MCF7 breast cancer cells caused inhibition of ~80% cells after irradiation with infrared light (0.5 W cm -2 ) for 5 min.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

NASA Technical Reports Server (NTRS)

Eldin, A. G.

1991-01-01

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Acoustic charge transport technology investigation for advanced development transponder

NASA Technical Reports Server (NTRS)

Kayalar, S.

1993-01-01

Acoustic charge transport (ACT) technology has provided a basis for a new family of analog signal processors, including a programmable transversal filter (PTF). Through monolithic integration of ACT delay lines with GaAs metal semiconductor field effect transistor (MESFET) digital memory and controllers, these devices significantly extend the performance of PTF's. This article introduces the basic operation of these devices and summarizes their present and future specifications. The production and testing of these devices indicate that this new technology is a promising one for future space applications.

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

NASA Technical Reports Server (NTRS)

Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

1991-01-01

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Effect of Pulse and dc Formation on the Performance of One-Transistor and One-Resistor Resistance Random Access Memory Devices

NASA Astrophysics Data System (ADS)

Liu, Hong-Tao; Yang, Bao-He; Lv, Hang-Bing; Xu, Xiao-Xin; Luo, Qing; Wang, Guo-Ming; Zhang, Mei-Yun; Long, Shi-Bing; Liu, Qi; Liu, Ming

2015-02-01

We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor (1T1R) resistance random access memory (RRAM) device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state (HRS) under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament (CF) formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state (LRS) can be easily changed by removing a few trapping states from the conducting path. Hence, a higher HRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Compact Method for Modeling and Simulation of Memristor Devices

DTIC Science & Technology

2011-08-01

single-valued equations. 15. SUBJECT TERMS Memristor, Neuromorphic , Cognitive, Computing, Memory, Emerging Technology, Computational Intelligence 16...resistance state depends on its previous state and present electrical biasing conditions, and when combined with transistors in a hybrid chip ...computers, reconfigurable electronics and neuromorphic computing [3,4]. According to Chua [4], the memristor behaves like a linear resistor with

High density submicron magnetoresistive random access memory (invited)

NASA Astrophysics Data System (ADS)

Tehrani, S.; Chen, E.; Durlam, M.; DeHerrera, M.; Slaughter, J. M.; Shi, J.; Kerszykowski, G.

1999-04-01

Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal-oxide-semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Boost Up Carrier Mobility for Ferroelectric Organic Transistor Memory via Buffering Interfacial Polarization Fluctuation

PubMed Central

Sun, Huabin; Wang, Qijing; Li, Yun; Lin, Yen-Fu; Wang, Yu; Yin, Yao; Xu, Yong; Liu, Chuan; Tsukagoshi, Kazuhito; Pan, Lijia; Wang, Xizhang; Hu, Zheng; Shi, Yi

2014-01-01

Ferroelectric organic field-effect transistors (Fe-OFETs) have been attractive for a variety of non-volatile memory device applications. One of the critical issues of Fe-OFETs is the improvement of carrier mobility in semiconducting channels. In this article, we propose a novel interfacial buffering method that inserts an ultrathin poly(methyl methacrylate) (PMMA) between ferroelectric polymer and organic semiconductor layers. A high field-effect mobility (μFET) up to 4.6 cm2 V−1 s−1 is obtained. Subsequently, the programming process in our Fe-OFETs is mainly dominated by the switching between two ferroelectric polarizations rather than by the mobility-determined charge accumulation at the channel. Thus, the “reading” and “programming” speeds are significantly improved. Investigations show that the polarization fluctuation at semiconductor/insulator interfaces, which affect the charge transport in conducting channels, can be suppressed effectively using our method. PMID:25428665

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Resistive switching characteristics and mechanisms in silicon oxide memory devices

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

2016-05-01

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

Multifunctional tunneling devices based on graphene/h-BN/MoSe2 van der Waals heterostructures

NASA Astrophysics Data System (ADS)

Cheng, Ruiqing; Wang, Feng; Yin, Lei; Xu, Kai; Ahmed Shifa, Tofik; Wen, Yao; Zhan, Xueying; Li, Jie; Jiang, Chao; Wang, Zhenxing; He, Jun

2017-04-01

The vertically stacked devices based on van der Waals heterostructures (vdWHs) of two-dimensional layered materials (2DLMs) have attracted considerable attention due to their superb properties. As a typical structure, graphene/hexagonal boron nitride (h-BN)/graphene vdWH has been proved possible to make tunneling devices. Compared with graphene, transition metal dichalcogenides possess intrinsic bandgap, leading to high performance of electronic devices. Here, tunneling devices based on graphene/h-BN/MoSe2 vdWHs are designed for multiple functions. On the one hand, the device shows a typical tunneling field-effect transistor behavior. A high on/off ratio of tunneling current (5 × 103) and an ultrahigh current rectification ratio (7 × 105) are achieved, which are attributed to relatively small electronic affinity of MoSe2 and optimized thickness of h-BN. On the other hand, the same structure also realizes 2D non-volatile memory with a high program/erase current ratio (>105), large memory window (˜150 V from ±90 V), and good retention characteristic. These results could enhance the fundamental understanding of tunneling behavior in vdWHs and contribute to the design of ultrathin rectifiers and memory based on 2DLMs.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

NASA Astrophysics Data System (ADS)

Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

Highly uniform and reliable resistive switching characteristics of a Ni/WOx/p+-Si memory device

NASA Astrophysics Data System (ADS)

Kim, Tae-Hyeon; Kim, Sungjun; Kim, Hyungjin; Kim, Min-Hwi; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

2018-02-01

In this paper, we investigate the resistive switching behavior of a bipolar resistive random-access memory (RRAM) in a Ni/WOx/p+-Si RRAM with CMOS compatibility. Highly unifrom and reliable bipolar resistive switching characteristics are observed by a DC voltage sweeping and its switching mechanism can be explained by SCLC model. As a result, the possibility of metal-insulator-silicon (MIS) structural WOx-based RRAM's application to Si-based 1D (diode)-1R (RRAM) or 1T (transistor)-1R (RRAM) structure is demonstrated.

Electric bistability induced by incorporating self-assembled monolayers/aggregated clusters of azobenzene derivatives in pentacene-based thin-film transistors.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2012-10-24

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.

Effect of substrate and temperature on the electronic properties of monolayer molybdenum disulfide field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Qizhi; Fang, Jiajia; Zhang, Guangru; Wang, Quan

2018-03-01

The use of two-dimensional nanostructured molybdenum disulfide (MoS2) films in field-effect transistors (FETs) in place of graphene was investigated. Monolayer MoS2 films were fabricated by chemical vapor deposition. The output and transfer curves of supported and suspended MoS2 FETs were measured. The mobility of the suspended device reached 364.2 cm2 V-1 s-1 at 150 °C. The hysteresis of the supported device in transfer curves was much larger than that of the suspended device, and it increased at higher temperatures. These results indicate that the device mobility was limited by Coulomb scattering at ambient temperature, and surface/interface phonon scattering at 150 °C, and the injection of electrons, via quantum tunneling through the Schottky barrier at the contact, was enhanced at higher temperatures and led to the increase of the hysteresis. The suspended MoS2 films show potential for application as a channel material in electronic devices, and further understanding the causes of hysteresis in a material is important for its use in technologies, such as memory devices and sensing cells.

Room temperature operation of electro-optical bistability in the edge-emitting tunneling-collector transistor laser

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Wang, C. Y.

2017-09-01

Optical bistable devices are fundamental to digital photonics as building blocks of switches, logic gates, and memories in future computer systems. Here, we demonstrate both optical and electrical bistability and capability for switching in a single transistor operated at room temperature. The electro-optical hysteresis is explained by the interaction of electron-hole (e-h) generation and recombination dynamics with the cavity photon modulation in different switching paths. The switch-UP and switch-DOWN threshold voltages are determined by the rate difference of photon generation at the base quantum-well and the photon absorption via intra-cavity photon-assisted tunneling controlled by the collector voltage. Thus, the transistor laser electro-optical bistable switching is programmable with base current and collector voltage, and the basis for high speed optical logic processors.

Photo-assisted hysteresis of electronic transport for ZnO nanowire transistors

NASA Astrophysics Data System (ADS)

Du, Qianqian; Ye, Jiandong; Xu, Zhonghua; Zhu, Shunming; Tang, Kun; Gu, Shulin; Zheng, Youdou

2018-03-01

Recently, ZnO nanowire field effect transistors (FETs) have received renewed interest due to their extraordinary low dimensionality and high sensitivity to external chemical environments and illumination conditions. These prominent properties have promising potential in nanoscale chemical and photo-sensors. In this article, we have fabricated ZnO nanowire FETs and have found hysteresis behavior in their transfer characteristics. The mechanism and dynamics of the hysteresis phenomena have been investigated in detail by varying the sweeping rate and range of the gate bias with and without light irradiation. Significantly, light irradiation is of great importance on charge trapping by regulating adsorption and desorption of oxygen at the interface of ZnO/SiO2. Carriers excited by light irradiation can dramatically promote trapping/detrapping processes. With the assistance of light illumination, we have demonstrated a photon-assisted nonvolatile memory which employs the ZnO nanowire FET. The device exhibits reliable programming/erasing operations and a large on/off ratio. The proposed proto-type memory has thus provided a possible novel path for creating a memory functionality to other low-dimensional material systems.

Soluble porphyrin polymers

DOEpatents

Gust, Jr., John Devens; Liddell, Paul Anthony

2015-07-07

Porphyrin polymers of Structure 1, where n is an integer (e.g., 1, 2, 3, 4, 5, or greater) ##STR00001## are synthesized by the method shown in FIGS. 2A and 2B. The porphyrin polymers of Structure 1 are soluble in organic solvents such as 2-MeTHF and the like, and can be synthesized in bulk (i.e., in processes other than electropolymerization). These porphyrin polymers have long excited state lifetimes, making the material suitable as an organic semiconductor for organic electronic devices including transistors and memories, as well as solar cells, sensors, light-emitting devices, and other opto-electronic devices.

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

NASA Astrophysics Data System (ADS)

Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Interface engineering of semiconductor/dielectric heterojunctions toward functional organic thin-film transistors.

PubMed

Zhang, Hongtao; Guo, Xuefeng; Hui, Jingshu; Hu, Shuxin; Xu, Wei; Zhu, Daoben

2011-11-09

Interface modification is an effective and promising route for developing functional organic field-effect transistors (OFETs). In this context, however, researchers have not created a reliable method of functionalizing the interfaces existing in OFETs, although this has been crucial for the technological development of high-performance CMOS circuits. Here, we demonstrate a novel approach that enables us to reversibly photocontrol the carrier density at the interface by using photochromic spiropyran (SP) self-assembled monolayers (SAMs) sandwiched between active semiconductors and gate insulators. Reversible changes in dipole moment of SPs in SAMs triggered by lights with different wavelengths produce two distinct built-in electric fields on the OFET that can modulate the channel conductance and consequently threshold voltage values, thus leading to a low-cost noninvasive memory device. This concept of interface functionalization offers attractive new prospects for the development of organic electronic devices with tailored electronic and other properties.

Transistor-based interface circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2007-02-13

Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

A hybrid ferroelectric-flash memory cells

NASA Astrophysics Data System (ADS)

Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

2014-09-01

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

Construction and Operation of Three-Dimensional Memory and Logic Molecular Devices and Circuits

DTIC Science & Technology

2013-07-01

higher currents and less leakage. We also constructed a ferrocene -based self-assembling monolayer attached to gold nanoparticles, exhibiting a...charging transistor utilizing Ferrocene -based SAM attached to gold nano-particle. Our experiments are, to our knowledge, the first to exhibit an...The molecular layer includes a ferrocene SAM attached to Au Distribution A: Approved for public release; distribution is unlimited

A light-stimulated synaptic transistor with synaptic plasticity and memory functions based on InGaZnO{sub x}–Al{sub 2}O{sub 3} thin film structure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, H. K.; Chen, T. P., E-mail: echentp@ntu.edu.sg; Liu, P.

In this work, a synaptic transistor based on the indium gallium zinc oxide (IGZO)–aluminum oxide (Al{sub 2}O{sub 3}) thin film structure, which uses ultraviolet (UV) light pulses as the pre-synaptic stimulus, has been demonstrated. The synaptic transistor exhibits the behavior of synaptic plasticity like the paired-pulse facilitation. In addition, it also shows the brain's memory behaviors including the transition from short-term memory to long-term memory and the Ebbinghaus forgetting curve. The synapse-like behavior and memory behaviors of the transistor are due to the trapping and detrapping processes of the holes, which are generated by the UV pulses, at the IGZO/Al{submore » 2}O{sub 3} interface and/or in the Al{sub 2}O{sub 3} layer.« less

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Ferroelectric polarization induces electronic nonlinearity in ion-doped conducting polymers

PubMed Central

Fabiano, Simone; Sani, Negar; Kawahara, Jun; Kergoat, Loïg; Nissa, Josefin; Engquist, Isak; Crispin, Xavier; Berggren, Magnus

2017-01-01

Poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) is an organic mixed ion-electron conducting polymer. The PEDOT phase transports holes and is redox-active, whereas the PSS phase transports ions. When PEDOT is redox-switched between its semiconducting and conducting state, the electronic and optical properties of its bulk are controlled. Therefore, it is appealing to use this transition in electrochemical devices and to integrate those into large-scale circuits, such as display or memory matrices. Addressability and memory functionality of individual devices, within these matrices, are typically achieved by nonlinear current-voltage characteristics and bistability—functions that can potentially be offered by the semiconductor-conductor transition of redox polymers. However, low conductivity of the semiconducting state and poor bistability, due to self-discharge, make fast operation and memory retention impossible. We report that a ferroelectric polymer layer, coated along the counter electrode, can control the redox state of PEDOT. The polarization switching characteristics of the ferroelectric polymer, which take place as the coercive field is overcome, introduce desired nonlinearity and bistability in devices that maintain PEDOT in its highly conducting and fast-operating regime. Memory functionality and addressability are demonstrated in ferro-electrochromic display pixels and ferro-electrochemical transistors. PMID:28695197

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Shape‐Controlled, Self‐Wrapped Carbon Nanotube 3D Electronics

PubMed Central

Wang, Huiliang; Wang, Yanming; Tee, Benjamin C.‐K.; Kim, Kwanpyo; Lopez, Jeffrey; Cai, Wei

2015-01-01

The mechanical flexibility and structural softness of ultrathin devices based on organic thin films and low‐dimensional nanomaterials have enabled a wide range of applications including flexible display, artificial skin, and health monitoring devices. However, both living systems and inanimate systems that are encountered in daily lives are all 3D. It is therefore desirable to either create freestanding electronics in a 3D form or to incorporate electronics onto 3D objects. Here, a technique is reported to utilize shape‐memory polymers together with carbon nanotube flexible electronics to achieve this goal. Temperature‐assisted shape control of these freestanding electronics in a programmable manner is demonstrated, with theoretical analysis for understanding the shape evolution. The shape control process can be executed with prepatterned heaters, desirable for 3D shape formation in an enclosed environment. The incorporation of carbon nanotube transistors, gas sensors, temperature sensors, and memory devices that are capable of self‐wrapping onto any irregular shaped‐objects without degradations in device performance is demonstrated. PMID:27980972

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

NASA Astrophysics Data System (ADS)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

Novel organic semiconductors and a high capacitance gate dielectric for organic thin film transistors

NASA Astrophysics Data System (ADS)

Cai, Xiuyu

2007-12-01

Organic semiconductors are attracting more and more interest as a promising set of materials in the field of electronics research. This thesis focused on several new organic semiconductors and a novel high-kappa dielectric thin film (SrTiO3), which are two essential parts in Organic Thin Film Transistors (OTFTs). Structure and morphology of thin films of tricyanovinyl capped oligothiophenes were studied using atomic force microscopy and x-ray diffraction. Thin film transistors of one compound exhibited a reasonable electron mobility of 0.02 cm2/Vs. Temperature dependent measurements on the thin film transistor based on this compound revealed shallow trap states that were interpreted in terms of a multiple trap and release model. Moreover, inversion of the majority charge carrier type from electrons to holes was observed when the number of oligothiophene rings increased to six and ambipolar transport behavior was observed for tricyanovinyl sexithiophene. Another interesting organic semiconductor compound is the fluoalkylquarterthiophene, which showed ambipolar transport and large hysteresis in the transfer curve. Due to the bistable state at floating gate, the thin film transistor was exploited to study non-volatile floating gate memory effects. The temperature dependence of the retention time for this memory device revealed that the electron trapping was an activated process. Following the earlier work on hybrid acene-thiophene organic semiconductors, new compounds with similar structure were studied to reveal the mechanism of the air-stability exhibited by some compounds. They all formed highly crystalline thin films and showed reasonable device performances which are well correlated with the molecular structures, thin film microstructures, and solid state packing. The most air-stable compound had no observable degradation with exposure to air for 15 months. SrTiO3 was developed to be employed in OTFTs. Optimization of thin film growth was performed using reactive sputtering growth. Excellent SrTiO3 epitaixal thin film growth was revealed on conductive SrTiO 3:Nb substrates. A maximum charge carrier density of 1014 cm-2 was obtained based on pentacene and perylene diimide thin film transistors. Some new physical phenomena, such as step-like transfer characteristic curve and negative transconductance, were observed at such high field effect induced charge carrier density.

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

2018-02-01

Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could enable complex neuromorphic learning and the study of the physics of defect kinetics in two-dimensional materials.

Industry Study, Electronics Industry, Spring 2009

DTIC Science & Technology

2009-01-01

Toshiba, Samsung , and NEC.7 The microprocessor is a central processing unit containing hundreds of millions of transistors and logic to perform...business with an 11.7% market share followed closely by Samsung with a 10.3% market share.40 Intel is the leader in the production of microprocessors...while Samsung is the leading memory chip producer. Other US chip manufacturers include Texas Instruments (TI), Advanced Micro Devices (AMD), Micron

Overview of emerging nonvolatile memory technologies

PubMed Central

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices. PMID:25278820

Overview of emerging nonvolatile memory technologies.

PubMed

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

NASA Astrophysics Data System (ADS)

Zand, Ramtin; DeMara, Ronald F.

2017-12-01

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat D.

2008-01-01

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy.

PubMed

Jaiswal, Akhilesh; Agrawal, Amogh; Roy, Kaushik

2018-04-10

Recently, the exponential increase in compute requirements demanded by emerging applications like artificial intelligence, Internet of things, etc. have rendered the state-of-art von-Neumann machines inefficient in terms of energy and throughput owing to the well-known von-Neumann bottleneck. A promising approach to mitigate the bottleneck is to do computations as close to the memory units as possible. One extreme possibility is to do in-situ Boolean logic computations by using stateful devices. Stateful devices are those that can act both as a compute engine and storage device, simultaneously. We propose such stateful, vector, in-memory operations using voltage controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions (MTJ). Our proposal is based on the well known manufacturable 1-transistor - 1-MTJ bit-cell and does not require any modifications in the bit-cell circuit or the magnetic device. Instead, we leverage the very physics of the VCMA effect to enable stateful computations. Specifically, we exploit the voltage asymmetry of the VCMA effect to construct stateful IMP (implication) gate and use the precessional switching dynamics of the VCMA devices to propose a massively parallel NOT operation. Further, we show that other gates like AND, OR, NAND, NOR, NIMP (complement of implication) can be implemented using multi-cycle operations.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Ferroelectricity in Covalently functionalized Two-dimensional Materials: Integration of High-mobility Semiconductors and Nonvolatile Memory.

PubMed

Wu, Menghao; Dong, Shuai; Yao, Kailun; Liu, Junming; Zeng, Xiao Cheng

2016-11-09

Realization of ferroelectric semiconductors by conjoining ferroelectricity with semiconductors remains a challenging task because most present-day ferroelectric materials are unsuitable for such a combination due to their wide bandgaps. Herein, we show first-principles evidence toward the realization of a new class of two-dimensional (2D) ferroelectric semiconductors through covalent functionalization of many prevailing 2D materials. Members in this new class of 2D ferroelectric semiconductors include covalently functionalized germanene, and stanene (Nat. Commun. 2014, 5, 3389), as well as MoS 2 monolayer (Nat. Chem. 2015, 7, 45), covalent functionalization of the surface of bulk semiconductors such as silicon (111) (J. Phys. Chem. B 2006, 110 , 23898), and the substrates of oxides such as silica with self-assembly monolayers (Nano Lett. 2014, 14, 1354). The newly predicted 2D ferroelectric semiconductors possess high mobility, modest bandgaps, and distinct ferroelectricity that can be exploited for developing various heterostructural devices with desired functionalities. For example, we propose applications of the 2D materials as 2D ferroelectric field-effect transistors with ultrahigh on/off ratio, topological transistors with Dirac Fermions switchable between holes and electrons, ferroelectric junctions with ultrahigh electro-resistance, and multiferroic junctions for controlling spin by electric fields. All these heterostructural devices take advantage of the combination of high-mobility semiconductors with fast writing and nondestructive reading capability of nonvolatile memory, thereby holding great potential for the development of future multifunctional devices.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

Photo-reactive charge trapping memory based on lanthanide complex.

PubMed

Zhuang, Jiaqing; Lo, Wai-Sum; Zhou, Li; Sun, Qi-Jun; Chan, Chi-Fai; Zhou, Ye; Han, Su-Ting; Yan, Yan; Wong, Wing-Tak; Wong, Ka-Leung; Roy, V A L

2015-10-09

Traditional utilization of photo-induced excitons is popularly but restricted in the fields of photovoltaic devices as well as photodetectors, and efforts on broadening its function have always been attempted. However, rare reports are available on organic field effect transistor (OFET) memory employing photo-induced charges. Here, we demonstrate an OFET memory containing a novel organic lanthanide complex Eu(tta)3ppta (Eu(tta)3 = Europium(III) thenoyltrifluoroacetonate, ppta = 2-phenyl-4,6-bis(pyrazol-1-yl)-1,3,5-triazine), in which the photo-induced charges can be successfully trapped and detrapped. The luminescent complex emits intense red emission upon ultraviolet (UV) light excitation and serves as a trapping element of holes injected from the pentacene semiconductor layer. Memory window can be significantly enlarged by light-assisted programming and erasing procedures, during which the photo-induced excitons in the semiconductor layer are separated by voltage bias. The enhancement of memory window is attributed to the increasing number of photo-induced excitons by the UV light. The charges are stored in this luminescent complex for at least 10(4) s after withdrawing voltage bias. The present study on photo-assisted novel memory may motivate the research on a new type of light tunable charge trapping photo-reactive memory devices.

Photo-reactive charge trapping memory based on lanthanide complex

NASA Astrophysics Data System (ADS)

Zhuang, Jiaqing; Lo, Wai-Sum; Zhou, Li; Sun, Qi-Jun; Chan, Chi-Fai; Zhou, Ye; Han, Su-Ting; Yan, Yan; Wong, Wing-Tak; Wong, Ka-Leung; Roy, V. A. L.

2015-10-01

Traditional utilization of photo-induced excitons is popularly but restricted in the fields of photovoltaic devices as well as photodetectors, and efforts on broadening its function have always been attempted. However, rare reports are available on organic field effect transistor (OFET) memory employing photo-induced charges. Here, we demonstrate an OFET memory containing a novel organic lanthanide complex Eu(tta)3ppta (Eu(tta)3 = Europium(III) thenoyltrifluoroacetonate, ppta = 2-phenyl-4,6-bis(pyrazol-1-yl)-1,3,5-triazine), in which the photo-induced charges can be successfully trapped and detrapped. The luminescent complex emits intense red emission upon ultraviolet (UV) light excitation and serves as a trapping element of holes injected from the pentacene semiconductor layer. Memory window can be significantly enlarged by light-assisted programming and erasing procedures, during which the photo-induced excitons in the semiconductor layer are separated by voltage bias. The enhancement of memory window is attributed to the increasing number of photo-induced excitons by the UV light. The charges are stored in this luminescent complex for at least 104 s after withdrawing voltage bias. The present study on photo-assisted novel memory may motivate the research on a new type of light tunable charge trapping photo-reactive memory devices.

Recent progress in tungsten oxides based memristors and their neuromorphological applications

NASA Astrophysics Data System (ADS)

Qu, Bo; Younis, Adnan; Chu, Dewei

2016-09-01

The advance in conventional silicon based semiconductor industry is now becoming indeterminacy as it still along the road of Moore's Law and concomitant problems associated with it are the emergence of a number of practical issues such as short channel effect. In terms of memory applications, it is generally believed that transistors based memory devices will approach to their scaling limits up to 2018. Therefore, one of the most prominent challenges today in semiconductor industry is the need of a new memory technology which is able to combine the best characterises of current devices. The resistive switching memories which are regarded as "memristors" thus gain great attentions thanks to their specific nonlinear electrical properties. More importantly, their behaviour resembles with the transmission characteristic of synapse in biology. Therefore, the research of synapses biomimetic devices based on memristor will certainly bring a great research prospect in studying synapse emulation as well as building artificial neural networks. Tungsten oxides (WO x ) exhibits many essential characteristics as a great candidate for memristive devices including: accredited endurance (over 105 cycles), stoichiometric flexibility, complimentary metal-oxide-semiconductor (CMOS) process compatibility and configurable properties including non-volatile rectification, memorization and learning functions. Herein, recent progress on Tungsten oxide based materials and its associating memory devices had been reviewed. The possible implementation of this material as a bio-inspired artificial synapse is also highlighted. The penultimate section summaries the current research progress for tungsten oxide based biological synapses and end up with several proposals that have been suggested for possible future developments.

Low-voltage-operated organic one-time programmable memory using printed organic thin-film transistors and antifuse capacitors.

PubMed

Jung, Soon-Won; Na, Bock Soon; Park, Chan Woo; Koo, Jae Bon

2014-11-01

We demonstrate an organic one-time programmable memory cell formed entirely at plastic-compatible temperatures. All the processes are performed at below 130 degrees C. Our memory cell consists of a printed organic transistor and an organic capacitor. Inkjet-printed organic transistors are fabricated by using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) for low-voltage operation. P(NDI2OD-T2) transistors have a high field-effect mobility of 0.2 cm2/Vs and a low operation gate voltage of less than 10 V. The operation voltage effectively decreases owing to the high permittivity of the P(VDF-TrFE):PMMA blended film. The data in the memory cell are programmed by electrically breaking the organic capacitor. The organic capacitor acts like an antifuse capacitor, because it is initially open, and it becomes permanently short-circuited by applying a high voltage. The organic memory cells are programmed with 4 V, and they are read out with 2 V. The memory data are read out by sensing the current in the memory cell. The printed organic one-time programmable memory is suitable for applications storing small amount of data, such as low-cost radio-frequency identification (RFID) tag.

Current control circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2005-03-15

Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gatemore » bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.« less

Extraction of sub-gap density of states via capacitance-voltage measurement for the erasing process in a TFT charge-trapping memory

NASA Astrophysics Data System (ADS)

Chiang, Yen-Chang; Hsiao, Yang-Hsuan; Li, Jeng-Ting; Chen, Jen-Sue

2018-02-01

Charge-trapping memories (CTMs) based on zinc tin oxide (ZTO) semiconductor thin-film transistors (TFTs) can be programmed by a positive gate voltage and erased by a negative gate voltage in conjunction with light illumination. To understand the mechanism involved, the sub-gap density of states associated with ionized oxygen vacancies in the ZTO active layer is extracted from optical response capacitance-voltage (C-V) measurements. The corresponding energy states of ionized oxygen vacancies are observed below the conduction band minimum at approximately 0.5-1.0 eV. From a comparison of the fitted oxygen vacancy concentration in the CTM-TFT after the light-bias erasing operation, it is found that the pristine-erased device contains more oxygen vacancies than the program-erased device because the trapped electrons in the programmed device are pulled into the active layer and neutralized by the oxygen vacancies that are present there.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

High-Fidelity Microwave Control of Single-Atom Spin Qubits in Silicon

DTIC Science & Technology

2014-07-08

reality. Every electronic device found in our homes, offices, cars, pockets contains a brain made up of silicon transistors. Naturally, the trillion-dollar...to 6 GHz) and digital IQ modulation. AlazarTech ATS9440 This digitiser samples signals and stores them in memory for analysis, and has a graphical...nanostructures. Spin resonance experiments on donors in enriched 28Si have raised the suspicion that the proximity to a Si/SiO2 interface deteriorates

Microcircuit Reliability Bibliography. Volume 4. 1976 Annual Reference Supplement. (Document Numbers 11045-11745)

DTIC Science & Technology

1976-04-01

State Electron- Res. Lab., Eindhoven, Neth.) icw 16, no. 12, 1315-20, Dec. 1973 ATMOS-AN ELECTRICALLY REPROGRAMMABLE READ-ONLY MEMORY DEVICE. IEEE Trans...transistor is described that can be used nular and array geometry contacts by as an electrically reprogrammable read- the pr~nciple of superposition. It is...digital tuning techniques for FM and typical automobile systems can be readily television, and pocket pagers. Tn. implemented by COS1440S monolithic

Built-in self-repair of VLSI memories employing neural nets

NASA Astrophysics Data System (ADS)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

Oscillatory threshold logic.

PubMed

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory.

Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

NASA Astrophysics Data System (ADS)

Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

2017-10-01

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator

NASA Astrophysics Data System (ADS)

Nishikata, Daisuke; Ali, Mohammad Alimudin Bin Mohd; Hosoda, Kento; Matsumoto, Hiroshi; Nakamura, Kazuyuki

2018-04-01

A 36-bit × 32-entry fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18 µm CMOS process. The minimum operating voltage of 0.25 V of the developed RL-TCAM, which is less than half of that of the conventional TCAM, was measured via the conventional CMOS push–pull output buffers with the level-shifting and flipping technique using optimized pull-up voltage and resistors.

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile memory characteristics of organic thin film transistors using poly(2-hydroxyethyl methacrylate)-based polymer multilayer dielectric

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Su, Yan-Kuin; Yu, Hsin-Chieh; Huang, Chun-Yuan; Huang, Tsung-Syun

2011-10-01

A wide hysteresis width characteristic (memory window) was observed in the organic thin film transistors (OTFTs) using poly(2-hydroxyethyl methacrylate) (PHEMA)-based polymer multilayers. In this study, a strong memory effect was also found in the pentacene-based OTFTs and the electric characteristics were improved by introducing PHEMA/poly(methyl methacrylate) (PMMA)/PHEMA trilayer to replace the conventional PHEMA monolayer or PMMA/PHEMA and PHEMA/PMMA bilayer as the dielectric layers of OTFTs. The memory effect was originated from the electron trapping and slow polarization of the dielectrics. The hydroxyl (-OH) groups inside the polymer dielectric were the main charge storage sites of the electrons. This charge-storage phenomenon could lead to a wide flat-band voltage shift (memory window, △VFB = 22 V) which is essential for the OTFTs' memory-related applications. Moreover, the fabricated transistors also exhibited significant switchable channel current due to the charge-storage and slow charge relaxation.

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

EDITORIAL: Synaptic electronics Synaptic electronics

NASA Astrophysics Data System (ADS)

Demming, Anna; Gimzewski, James K.; Vuillaume, Dominique

2013-09-01

Conventional computers excel in logic and accurate scientific calculations but make hard work of open ended problems that human brains handle easily. Even von Neumann—the mathematician and polymath who first developed the programming architecture that forms the basis of today's computers—was already looking to the brain for future developments before his death in 1957 [1]. Neuromorphic computing uses approaches that better mimic the working of the human brain. Recent developments in nanotechnology are now providing structures with very accommodating properties for neuromorphic approaches. This special issue, with guest editors James K Gimzewski and Dominique Vuillaume, is devoted to research at the serendipitous interface between the two disciplines. 'Synaptic electronics', looks at artificial devices with connections that demonstrate behaviour similar to synapses in the nervous system allowing a new and more powerful approach to computing. Synapses and connecting neurons respond differently to incident signals depending on the history of signals previously experienced, ultimately leading to short term and long term memory behaviour. The basic characteristics of a synapse can be replicated with around ten simple transistors. However with the human brain having around 1011 neurons and 1015 synapses, artificial neurons and synapses from basic transistors are unlikely to accommodate the scalability required. The discovery of nanoscale elements that function as 'memristors' has provided a key tool for the implementation of synaptic connections [2]. Leon Chua first developed the concept of the 'The memristor—the missing circuit element' in 1971 [3]. In this special issue he presents a tutorial describing how memristor research has fed into our understanding of synaptic behaviour and how they can be applied in information processing [4]. He also describes, 'The new principle of local activity, which uncovers a minuscule life-enabling "Goldilocks zone", dubbed the edge of chaos, where complex phenomena, including creativity and intelligence, may emerge'. Also in this issue R Stanley Williams and colleagues report results from simulations that demonstrate the potential for using Mott transistors as building blocks for scalable neuristor-based integrated circuits without transistors [5]. The scalability of neural chip designs is also tackled in the design reported by Narayan Srinivasa and colleagues in the US [6]. Meanwhile Carsten Timm and Massimiliano Di Ventra describe simulations of a molecular transistor in which electrons strongly coupled to a vibrational mode lead to a Franck-Condon (FC) blockade that mimics the spiking action potentials in synaptic memory behaviour [7]. The 'atomic switches' used to demonstrate synaptic behaviour by a collaboration of researchers in California and Japan also come under further scrutiny in this issue. James K Gimzewski and colleagues consider the difference between the behaviour of an atomic switch in isolation and in a network [8]. As the authors point out, 'The work presented represents steps in a unified approach of experimentation and theory of complex systems to make atomic switch networks a uniquely scalable platform for neuromorphic computing'. Researchers in Germany [9] and Sweden [10] also report on theoretical approaches to modelling networks of memristive elements and complementary resistive switches for synaptic devices. As Vincent Derycke and colleagues in France point out, 'Actual experimental demonstrations of neural network type circuits based on non-conventional/non-CMOS memory devices and displaying function learning capabilities remain very scarce'. They describe how their work using carbon nanotubes provides a rare demonstration of actual function learning with synapses based on nanoscale building blocks [11]. However, this is far from the only experimental work reported in this issue, others include: short-term memory of TiO2-based electrochemical capacitors [12]; a neuromorphic circuit composed of a nanoscale 1-kbit resistive random-access memory (RRAM) cross-point array of synapses and complementary metal-oxide-semiconductor (CMOS) neuron circuits [13]; a WO3-x-based nanoionics device from Masakazu Aono's group with a wide scale of reprogrammable memorization functions [14]; a new spike-timing dependent plasticity scheme based on a MOS transistor as a selector and a RRAM as a variable resistance device [15]; a new hybrid memristor-CMOS neuromorphic circuit [16]; and a photo-assisted atomic switch [17]. Synaptic electronics evidently has many emerging facets, and Duygu Kuzum, Shimeng Yu, and H-S Philip Wong in the US provide a review of the field, including the materials, devices and applications [18]. In embracing the expertise acquired over thousands of years of evolution, biomimetics and bio-inspired design is a common, smart approach to technological innovation. Yet in successfully mimicking the physiological mechanisms of the human mind synaptic electronics research has a potential impact that is arguably unprecedented. That the quirks and eccentricities recently unearthed in the behaviour of nanomaterials should lend themselves so accommodatingly to emulating synaptic functions promises some very exciting developments in the field, as the articles in this special issue emphasize. References [1] von Neumann J (ed) 2012 The Computer and the Brain 3rd edn (Yale: Yale University Press) [2] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 The missing memristor found Nature 453 80-3 [3] Chua L O 1971 Memristor—the missing circuit element IEEE Trans. Circuit Theory 18 507-19 [4] Chua L O 2013 Memristor, Hodgkin-Huxley, and Edge of Chaos Nanotechnology 24 383001 [5] Pickett M D and Williams R S 2013 Phase transitions enable computational universality in neuristor-based cellular automata Nanotechnology 24 384002 [6] Cruz-Albrecht J M, Derosier T and Srinivasa N 2013 Scalable neural chip with synaptic electronics using CMOS integrated memristors Nanotechnology 24 384011 [7] Timm C and Di Ventra M 2013 Molecular neuron based on the Franck-Condon blockade Nanotechnology 24 384001 [8] Sillin H O, Aguilera R, Shieh H-H, Avizienis A V, Aono M, Stieg A Z and Gimzewski J K 2013 A theoretical and experimental study of neuromorphic atomic switch networks for reservoir computing Nanotechnology 24 384004 [9] Linn E, Menzel S, Ferch S and Waser R 2013 Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications Nanotechnology 24 384008 [10] Konkoli Z and Wendin G 2013 A generic simulator for large networks of memristive elements Nanotechnology 24 384007 [11] Gacem K, Retrouvey J-M, Chabi D, Filoramo A, Zhao W, Klein J-O and Derycke V 2013 Neuromorphic function learning with carbon nanotube-based synapses Nanotechnology 24 384013 [12] Lim H, Kim I, Kim J-S, Hwang C S and Jeong D S 2013 Short-term memory of TiO2-based electrochemical capacitors: empirical analysis with adoption of a sliding threshold Nanotechnology 24 384005 [13] Park S, Noh J, Choo M-L, Sheri A M, Chang M, Kim Y-B, Kim C J, Jeon M, Lee B-G, Lee B H and Hwang H 2013 Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device Nanotechnology 24 384009 [14] Yang R, Terabe K, Yao Y, Tsuruoka T, Hasegawa T, Gimzewski J K and Aono M 2013 Synaptic plasticity and memory functions achieved in WO3-x-based nanoionics device by using principle of atomic switch operation Nanotechnology 24 384002 [15] Ambrogio S, Balatti S, Nardi F, Facchinetti S and Ielmini D 2013 Spike-timing dependent plasticity in a transistor-selected resistive switching memory Nanotechnology 24 384012 [16] Indiveria G, Linares-Barranco B, Legenstein R, Deligeorgis G and Prodromakise T 2013 Integration of nanoscale memristor synapses in neuromorphic computing architectures Nanotechnology 24 384010 [17] Hino T, Hasegawa T, Tanaka H, Tsuruoka T, Terabe K, Ogawa T and Aono M 2013 Volatile and nonvolatile selective switching of a photo-assited initialized atomic switch Nanotechnology 24 384006 [18] Kuzum D, Yu S and Wong H-S P 2013 Synaptic electronics: materials, devices and applications Nanotechnology 24 382001

Demonstration and properties of a planar heterojunction bipolar transistor with lateral current flow

NASA Astrophysics Data System (ADS)

Thornton, Robert L.; Mosby, William J.; Chung, Harlan F.

1989-10-01

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 micron. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-micron stripe.

Fabrication and characterization of the organic rectifying junctions by electrolysis

NASA Astrophysics Data System (ADS)

Karimov, Khasan; Ahmad, Zubair; Ali, Rashid; Noor, Adnan; Akmal, M.; Najeeb, M. A.; Shakoor, R. A.

2017-08-01

Unlike the conventional solution processable deposition techniques, in this study, we propose a novel and economical method for the fabrication of organic rectifying junctions. The solutions of the orange dye, copper phthalocyanine and NaCl were deposited on the surface-type interdigitated silver electrodes using electrolysis technique. Using the current-voltage (I-V) characteristics, the presence of rectifying behavior in the samples has been confirmed. This phenomenon, in principle, can be used for fabrication of the diodes, transistors and memory devices.

Recent developments and directions in printed nanomaterials

NASA Astrophysics Data System (ADS)

Choi, Hyung Woo; Zhou, Tianlei; Singh, Madhusudan; Jabbour, Ghassan E.

2015-02-01

In this review, we survey several recent developments in printing of nanomaterials for contacts, transistors, sensors of various kinds, light-emitting diodes, solar cells, memory devices, and bone and organ implants. The commonly used nanomaterials are classified according to whether they are conductive, semiconducting/insulating or biological in nature. While many printing processes are covered, special attention is paid to inkjet printing and roll-to-roll printing in light of their complexity and popularity. In conclusion, we present our view of the future development of this field.

High-speed low-power photonic transistor devices based on optically-controlled gain or absorption to affect optical interference.

PubMed

Huang, Yingyan; Ho, Seng-Tiong

2008-10-13

We show that a photonic transistor device can be realized via the manipulation of optical interference by optically controlled gain or absorption in novel ways, resulting in efficient transistor signal gain and switching action. Exemplary devices illustrate two complementary device types with high operating speed, microm size, microW switching power, and switching gain. They can act in tandem to provide a wide variety of operations including wavelength conversion, pulse regeneration, and logical operations. These devices could have a Transistor Figure-of-Merits >10(5) times higher than current chi((3)) approaches and are highly attractive.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

NASA Astrophysics Data System (ADS)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

A random access memory immune to single event upset using a T-Resistor

DOEpatents

Ochoa, A. Jr.

1987-10-28

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Random access memory immune to single event upset using a T-resistor

DOEpatents

Ochoa, Jr., Agustin

1989-01-01

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

Oscillatory Threshold Logic

PubMed Central

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

Flexible Organic Tribotronic Transistor Memory for a Visible and Wearable Touch Monitoring System.

PubMed

Li, Jing; Zhang, Chi; Duan, Lian; Zhang, Li Min; Wang, Li Duo; Dong, Gui Fang; Wang, Zhong Lin

2016-01-06

A new type of flexible organic tribotronic transistor memory is proposed, which can be written and erased by externally applied touch actions as an active memory. By further coupling with an organic light-emitting diode (OLED), a visible and wearable touch monitoring system is achieved, in which touch triggering can be memorized and shown as the emission from the OLED. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th}more » was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.« less

Novel Organic Phototransistor-Based Nonvolatile Memory Integrated with UV-Sensing/Green-Emissive Aggregation Enhanced Emission (AEE)-Active Aromatic Polyamide Electret Layer.

PubMed

Cheng, Shun-Wen; Han, Ting; Huang, Teng-Yung; Chang Chien, Yu-Hsin; Liu, Cheng-Liang; Tang, Ben Zhong; Liou, Guey-Sheng

2018-05-30

A novel aggregation enhanced emission (AEE)-active polyamide TPA-CN-TPE with a high photoluminesence characteristic was successfully synthesized by the direct polymerization of 4-cyanotriphenyl diamine (TPA-CN) and tetraphenylethene (TPE)-containing dicarboxylic acid. The obtained luminescent polyamide plays a significant role as the polymer electret layer in organic field-effect transistors (OFETs)-type memory. The strong green emission of TPA-CN-TPE under ultraviolet (UV) irradiation can be directly absorbed by the pentacene channel, displaying a light-induced programming and voltage-driven erasing organic phototransistor-based nonvolatile memory. Memory window can be effectively manipulated between the programming and erasing states by applying UV light illumination and electrical field, respectively. The photoinduced memory behavior can be maintained for over 10 4 s between these two states with an on/off ratio of 10 4 , and the memory switching can be steadily operated for many cycles. With high photoresponsivity ( R) and photosensitivity ( S), this organic phototransistor integrated with AEE-active polyamide electret layer could serve as an excellent candidate for UV photodetectors in optical applications. For comparison, an AEE-inactive aromatic polyimide TPA-PIS electret with much weaker solid-state emission was also applied in the same OFETs device architecture, but this device did not show any UV-sensitive and UV-induced memory characteristics, which further confirmed the significance of the light-emitting capability of the electret layer.

75 FR 30794 - Notice of Intent To Grant Exclusive Patent License; AmberWave Systems Corporation

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-02

..., power transistor devices, and power devices in the United States, the Government-owned inventions... amplifiers, radio frequency power transistor devices, and power devices and their use for the fabrication of...

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Single-transistor-clocked flip-flop

DOEpatents

Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

2005-08-30

The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Specifics of Pulsed Arc Welding Power Supply Performance Based On A Transistor Switch

NASA Astrophysics Data System (ADS)

Krampit, N. Yu; Kust, T. S.; Krampit, M. A.

2016-08-01

Specifics of designing a pulsed arc welding power supply device are presented in the paper. Electronic components for managing large current was analyzed. Strengths and shortcomings of power supply circuits based on thyristor, bipolar transistor and MOSFET are outlined. As a base unit for pulsed arc welding was chosen MOSFET transistor, which is easy to manage. Measures to protect a transistor are given. As for the transistor control device is a microcontroller Arduino which has a low cost and adequate performance of the work. Bead transfer principle is to change the voltage on the arc in the formation of beads on the wire end. Microcontroller controls transistor when the arc voltage reaches the threshold voltage. Thus there is a separation and transfer of beads without splashing. Control strategies tested on a real device and presented. The error in the operation of the device is less than 25 us, it can be used controlling drop transfer at high frequencies (up to 1300 Hz).

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Deviation from the law of energy equipartition in a small dynamic-random-access memory

NASA Astrophysics Data System (ADS)

Carles, Pierre-Alix; Nishiguchi, Katsuhiko; Fujiwara, Akira

2015-06-01

A small dynamic-random-access memory (DRAM) coupled with a high charge sensitivity electrometer based on a silicon field-effect transistor is used to study the law of equipartition of energy. By statistically analyzing the movement of single electrons in the DRAM at various temperature and voltage conditions in thermal equilibrium, we are able to observe a behavior that differs from what is predicted by the law of equipartition energy: when the charging energy of the capacitor of the DRAM is comparable to or smaller than the thermal energy kBT/2, random electron motion is ruled perfectly by thermal energy; on the other hand, when the charging energy becomes higher in relation to the thermal energy kBT/2, random electron motion is suppressed which indicates a deviation from the law of equipartition of energy. Since the law of equipartition is analyzed using the DRAM, one of the most familiar devices, we believe that our results are perfectly universal among all electronic devices.

Tunable organic transistors that use microfluidic source and drain electrodes

NASA Astrophysics Data System (ADS)

Maltezos, George; Nortrup, Robert; Jeon, Seokwoo; Zaumseil, Jana; Rogers, John A.

2003-09-01

This letter describes a type of transistor that uses conducting fluidic source and drain electrodes of mercury which flow on top of a thin film of the organic semiconductor pentacene. Pumping the mercury through suitably designed microchannels changes the width of the transistor channel and, therefore, the electrical characteristics of the device. Measurements on transistors with a range of channel lengths reveal low contact resistances between mercury and pentacene. Data collected before, during, and after pumping the mercury through the microchannels demonstrate reversible and systematic tuning of the devices. This unusual type of organic transistor has the potential to be useful in plastic microfluidic devices that require active elements for pumps, sensors, or other components. It also represents a noninvasive way to build transistor test structures that incorporate certain classes of chemically and mechanically fragile organic semiconductors.

Nanoelectronics: Opportunities for future space applications

NASA Technical Reports Server (NTRS)

Frazier, Gary

1995-01-01

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun

2014-09-22

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered moleculemore » orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.« less

Carbon nanotube chemistry and assembly for electronic devices

NASA Astrophysics Data System (ADS)

Derycke, Vincent; Auvray, Stéphane; Borghetti, Julien; Chung, Chia-Ling; Lefèvre, Roland; Lopez-Bezanilla, Alejandro; Nguyen, Khoa; Robert, Gaël; Schmidt, Gregory; Anghel, Costin; Chimot, Nicolas; Lyonnais, Sébastien; Streiff, Stéphane; Campidelli, Stéphane; Chenevier, Pascale; Filoramo, Arianna; Goffman, Marcelo F.; Goux-Capes, Laurence; Latil, Sylvain; Blase, Xavier; Triozon, François; Roche, Stephan; Bourgoin, Jean-Philippe

2009-05-01

Carbon nanotubes (CNTs) have exceptional physical properties that make them one of the most promising building blocks for future nanotechnologies. They may in particular play an important role in the development of innovative electronic devices in the fields of flexible electronics, ultra-high sensitivity sensors, high frequency electronics, opto-electronics, energy sources and nano-electromechanical systems (NEMS). Proofs of concept of several high performance devices already exist, usually at the single device level, but there remain many serious scientific issues to be solved before the viability of such routes can be evaluated. In particular, the main concern regards the controlled synthesis and positioning of nanotubes. In our opinion, truly innovative use of these nano-objects will come from: (i) the combination of some of their complementary physical properties, such as combining their electrical and mechanical properties; (ii) the combination of their properties with additional benefits coming from other molecules grafted on the nanotubes (this route being particularly relevant for gas- and bio-sensors, opto-electronic devices and energy sources); and (iii) the use of chemically- or bio-directed self-assembly processes to allow the efficient combination of several devices into functional arrays or circuits. In this article, we review our recent results concerning nanotube chemistry and assembly and their use to develop electronic devices. In particular, we present carbon nanotube field effect transistors and their chemical optimization, high frequency nanotube transistors, nanotube-based opto-electronic devices with memory capabilities and nanotube-based nano-electromechanical systems (NEMS). The impact of chemical functionalization on the electronic properties of CNTs is analyzed on the basis of theoretical calculations. To cite this article: V. Derycke et al., C. R. Physique 10 (2009).

Liquid crystals for organic transistors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Hanna, Jun-ichi; Iino, Hiroaki

2016-09-01

Liquid crystals are a new type of organic semiconductors exhibiting molecular orientation in self-organizing manner, and have high potential for device applications. In fact, various device applications have been proposed so far, including photosensors, solar cells, light emitting diodes, field effect transistors, and so on.. However, device performance in those fabricated with liquid crystals is less than those of devices fabricated with conventional materials in spite of unique features of liquid crystals. Here we discuss how we can utilize the liquid crystallinity in organic transistors and how we can overcome conventional non-liquid crystalline organic transistor materials. Then, we demonstrate high performance organic transistors fabricated with a smectic E liquid crystal of Ph-BTBT-10, which show high mobility of over 10cm2/Vs and high thermal durability of over 200oC in OFETs fabricated with its spin-coated polycrystalline thin films.

Metal nanoparticle film-based room temperature Coulomb transistor.

PubMed

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Memristive behavior in a junctionless flash memory cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orak, Ikram; Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl; Ürel, Mustafa

2015-06-08

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits themore » pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.« less

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Spin-based single-photon transistor, dynamic random access memory, diodes, and routers in semiconductors

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2016-12-01

The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect: giant circular birefringence induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet: a mixture of all-optical Internet with quantum Internet.

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2011 CFR

2011-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2012 CFR

2012-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2013 CFR

2013-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2014 CFR

2014-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

Energy-Filtered Tunnel Transistor: A New Device Concept Toward Extremely-Low Energy Consumption Electronics

DTIC Science & Technology

2015-12-17

temperature . New device architecture that utilizes cold-electron transport for ultra-low energy consumption electronics has been designed in a configuration...the oxygen has also been found important for the SiC>2 sputter deposition. The sputter was carried out at room temperature . Our optimized process...have been pursued for two electronic devices, 1) room- temperature single-electron transistors, and 2) ultralow energy consumption transistors. For

Conjugated polymers and their use in optoelectronic devices

DOEpatents

Marks, Tobin J.; Guo, Xugang; Zhou, Nanjia; Chang, Robert P. H.; Drees, Martin; Facchetti, Antonio

2016-10-18

The present invention relates to certain polymeric compounds and their use as organic semiconductors in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The present compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The present compounds can have good solubility in common solvents enabling device fabrication via solution processes.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Fully inkjet-printed two-dimensional material field-effect heterojunctions for wearable and textile electronics.

PubMed

Carey, Tian; Cacovich, Stefania; Divitini, Giorgio; Ren, Jiesheng; Mansouri, Aida; Kim, Jong M; Wang, Chaoxia; Ducati, Caterina; Sordan, Roman; Torrisi, Felice

2017-10-31

Fully printed wearable electronics based on two-dimensional (2D) material heterojunction structures also known as heterostructures, such as field-effect transistors, require robust and reproducible printed multi-layer stacks consisting of active channel, dielectric and conductive contact layers. Solution processing of graphite and other layered materials provides low-cost inks enabling printed electronic devices, for example by inkjet printing. However, the limited quality of the 2D-material inks, the complexity of the layered arrangement, and the lack of a dielectric 2D-material ink able to operate at room temperature, under strain and after several washing cycles has impeded the fabrication of electronic devices on textile with fully printed 2D heterostructures. Here we demonstrate fully inkjet-printed 2D-material active heterostructures with graphene and hexagonal-boron nitride (h-BN) inks, and use them to fabricate all inkjet-printed flexible and washable field-effect transistors on textile, reaching a field-effect mobility of ~91 cm 2  V -1  s -1 , at low voltage (<5 V). This enables fully inkjet-printed electronic circuits, such as reprogrammable volatile memory cells, complementary inverters and OR logic gates.

Development and fabrication of improved power transistor switches

NASA Technical Reports Server (NTRS)

Hower, P. L.; Chu, C. K.

1979-01-01

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

Metal nanoparticle film–based room temperature Coulomb transistor

PubMed Central

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

Micro-power dissipation device described

NASA Astrophysics Data System (ADS)

Mao, X.; Zhou, L.; Zhou, J.

1985-11-01

The common-emitter current gain beta of a common two-pole transistor is generally below 250. They are referred to as high-beta or high gain transistors when the beta of such transistors exceeds 300. When the beta of a transistor is higher than 1,000, it is called a super-beta transistor (SBT) or supergain transistor. The micropower dissipation type has the widest applications among the high-beta. Micropower dissipation high-beta means that there is a high gain or a superhigh gain under a microcurrent. The device is widely used in small signal-detection systems and stereo audio equipment because of their characteristics of high gain, low frequency and low noise under small signals.

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

PubMed

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

Theoretical Investigation of Device Aspects of Semiconductor Superlattices.

DTIC Science & Technology

1983-09-01

n-i-p-i devices include bulk field effect transistors, ultrasensitive or ultrafast IR photodetectors , tunable light-emitting devices, and ultrafast...transistor4 ultrasensitive or ultrafast IR photodetectors , tunable light-emitt tg devices, and ultrafast optical modulators. Particularlylppealing...differential conductivity ( NDC ) ......................... 19 3.2.2. Spontaneous and stimulated FIR emission from interlayer transitions

Development and fabrication of an augmented power transistor

NASA Technical Reports Server (NTRS)

Geisler, M. J.; Hill, F. E.; Ostop, J. A.

1983-01-01

The development of device design and processing techniques for the fabrication of an augmented power transistor capable of fast switching and high voltage power conversion is discussed. The major device goals sustaining voltages in the range of 800 to 1000 V at 80 A and 50 A, respectively, at a gain of 14. The transistor switching rise and fall times were both to have been less than 0.5 microseconds. The development of a passivating glass technique to shield the device high voltage junction from moisture and ionic contaminants is discussed as well as the development of an isolated package that separates the thermal and electrical interfaces. A new method was found to alloy the transistors to the molybdenum disc at a relatively low temperature. The measured electrical performance compares well with the predicted optimum design specified in the original proposed design. A 40 mm diameter transistor was fabricated with seven times the emitter area of the earlier 23 mm diameter device.

Molecular controlled of quantum nano systems

NASA Astrophysics Data System (ADS)

Paltiel, Yossi

2014-03-01

A century ago quantum mechanics created a conceptual revolution whose fruits are now seen in almost any aspect of our day-to-day life. Lasers, transistors and other solid state and optical devices represent the core technology of current computers, memory devices and communication systems. However, all these examples do not exploit fully the quantum revolution as they do not take advantage of the coherent wave-like properties of the quantum wave function. Controlled coherent system and devices at ambient temperatures are challenging to realize. We are developing a novel nano tool box with control coupling between the quantum states and the environment. This tool box that combines nano particles with organic molecules enables the integration of quantum properties with classical existing devices at ambient temperatures. The nano particles generate the quantum states while the organic molecules control the coupling and therefore the energy, charge, spin, or quasi particle transfer between the layers. Coherent effects at ambient temperatures can be measured in the strong coupling regime. In the talk I will present our nano tool box and show studies of charge transfer, spin transfer and energy transfer in the hybrid layers as well as collective transfer phenomena. These enable the realization of room temperature operating quantum electro optical devices. For example I will present in details, our recent development of a new type of chiral molecules based magnetless universal memory exploiting selective spin transfer.

Fused thiophene-based conjugated polymers and their use in optoelectronic devices

DOEpatents

Facchetti, Antonio; Marks, Tobin J; Takai, Atsuro; Seger, Mark; Chen, Zhihua

2015-11-03

The present teachings relate to certain polymeric compounds and their use as organic semiconductors in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The disclosed compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The disclosed compounds can have good solubility in common solvents enabling device fabrication via solution processes.

Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor

PubMed Central

Park, Jae Hyo; Kim, Hyung Yoon; Jang, Gil Su; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Kiaee, Zohreh; Joo, Seung Ki

2016-01-01

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films. PMID:27005886

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

PubMed

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Oxide-based materials by atomic layer deposition

NASA Astrophysics Data System (ADS)

Godlewski, Marek; Pietruszka, Rafał; Kaszewski, Jarosław; Witkowski, Bartłomiej S.; Gierałtowska, Sylwia; Wachnicki, Łukasz; Godlewski, Michał M.; Slonska, Anna; Gajewski, Zdzisław

2017-02-01

Thin films of wide band-gap oxides grown by Atomic Layer Deposition (ALD) are suitable for a range of applications. Some of these applications will be presented. First of all, ALD-grown high-k HfO2 is used as a gate oxide in the electronic devices. Moreover, ALD-grown oxides can be used in memory devices, in transparent transistors, or as elements of solar cells. Regarding photovoltaics (PV), ALD-grown thin films of Al2O3 are already used as anti-reflection layers. In addition, thin films of ZnO are tested as replacement of ITO in PV devices. New applications in organic photovoltaics, electronics and optoelectronics are also demonstrated Considering new applications, the same layers, as used in electronics, can also find applications in biology, medicine and in a food industry. This is because layers of high-k oxides show antibacterial activity, as discussed in this work.

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

2016-10-01

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

A kilobyte rewritable atomic memory

NASA Astrophysics Data System (ADS)

Kalff, F. E.; Rebergen, M. P.; Fahrenfort, E.; Girovsky, J.; Toskovic, R.; Lado, J. L.; Fernández-Rossier, J.; Otte, A. F.

2016-11-01

The advent of devices based on single dopants, such as the single-atom transistor, the single-spin magnetometer and the single-atom memory, has motivated the quest for strategies that permit the control of matter with atomic precision. Manipulation of individual atoms by low-temperature scanning tunnelling microscopy provides ways to store data in atoms, encoded either into their charge state, magnetization state or lattice position. A clear challenge now is the controlled integration of these individual functional atoms into extended, scalable atomic circuits. Here, we present a robust digital atomic-scale memory of up to 1 kilobyte (8,000 bits) using an array of individual surface vacancies in a chlorine-terminated Cu(100) surface. The memory can be read and rewritten automatically by means of atomic-scale markers and offers an areal density of 502 terabits per square inch, outperforming state-of-the-art hard disk drives by three orders of magnitude. Furthermore, the chlorine vacancies are found to be stable at temperatures up to 77 K, offering the potential for expanding large-scale atomic assembly towards ambient conditions.

High transconductance organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

Vertical organic transistors.

PubMed

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

High transconductance organic electrochemical transistors

PubMed Central

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

NASA Astrophysics Data System (ADS)

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Multiferroic nanomagnetic logic: Hybrid spintronics-straintronic paradigm for ultra-low energy computing

NASA Astrophysics Data System (ADS)

Salehi Fashami, Mohammad

Excessive energy dissipation in CMOS devices during switching is the primary threat to continued downscaling of computing devices in accordance with Moore's law. In the quest for alternatives to traditional transistor based electronics, nanomagnet-based computing [1, 2] is emerging as an attractive alternative since: (i) nanomagnets are intrinsically more energy-efficient than transistors due to the correlated switching of spins [3], and (ii) unlike transistors, magnets have no leakage and hence have no standby power dissipation. However, large energy dissipation in the clocking circuit appears to be a barrier to the realization of ultra low power logic devices with such nanomagnets. To alleviate this issue, we propose the use of a hybrid spintronics-straintronics or straintronic nanomagnetic logic (SML) paradigm. This uses a piezoelectric layer elastically coupled to an elliptically shaped magnetostrictive nanomagnetic layer for both logic [4-6] and memory [7-8] and other information processing [9-10] applications that could potentially be 2-3 orders of magnitude more energy efficient than current CMOS based devices. This dissertation focuses on studying the feasibility, performance and reliability of such nanomagnetic logic circuits by simulating the nanoscale magnetization dynamics of dipole coupled nanomagnets clocked by stress. Specifically, the topics addressed are: 1. Theoretical study of multiferroic nanomagnetic arrays laid out in specific geometric patterns to implement a "logic wire" for unidirectional information propagation and a universal logic gate [4-6]. 2. Monte Carlo simulations of the magnetization trajectories in a simple system of dipole coupled nanomagnets and NAND gate described by the Landau-Lifshitz-Gilbert (LLG) equations simulated in the presence of random thermal noise to understand the dynamics switching error [11, 12] in such devices. 3. Arriving at a lower bound for energy dissipation as a function of switching error [13] for a practical nanomagnetic logic scheme. 4. Clocking of nanomagnetic logic with surface acoustic waves (SAW) to drastically decrease the lithographic burden needed to contact each multiferroic nanomagnet while maintaining pipelined information processing. 5. Nanomagnets with four (or higher states) implemented with shape engineering. Two types of magnet that encode four states: (i) diamond, and (ii) concave nanomagnets are studied for coherence of the switching process.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Hot-Electron-Induced Device Degradation during Gate-Induced Drain Leakage Stress

NASA Astrophysics Data System (ADS)

Kim, Kwang-Soo; Han, Chang-Hoon; Lee, Jun-Ki; Kim, Dong-Soo; Kim, Hyong-Joon; Shin, Joong-Shik; Lee, Hea-Beoum; Choi, Byoung-Deog

2012-11-01

We studied the interface state generation and electron trapping by hot electrons under gate-induced drain leakage (GIDL) stress in p-type metal oxide semiconductor field-effect transistors (P-MOSFETs), which are used as the high-voltage core circuit of flash memory devices. When negative voltage was applied to a drain in the off-state, a GIDL current was generated, but when high voltage was applied to the drain, electrons had a high energy. The hot electrons produced the interface state and electron trapping. As a result, the threshold voltage shifted and the off-state leakage current (trap-assisted drain junction leakage current) increased. On the other hand, electron trapping mitigated the energy band bending near the drain and thus suppressed the GIDL current generation.

Charge transport and trapping in organic field effect transistors exposed to polar analytes

NASA Astrophysics Data System (ADS)

Duarte, Davianne; Sharma, Deepak; Cobb, Brian; Dodabalapur, Ananth

2011-03-01

Pentacene based organic thin-film transistors were used to study the effects of polar analytes on charge transport and trapping behavior during vapor sensing. Three sets of devices with differing morphology and mobility (0.001-0.5 cm2/V s) were employed. All devices show enhanced trapping upon exposure to analyte molecules. The organic field effect transistors with different mobilities also provide evidence for morphology dependent partition coefficients. This study helps provide a physical basis for many reports on organic transistor based sensor response.

Total Dose Effects in Conventional Bipolar Transistors

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swift, G. W.; Rax, B. G.

1994-01-01

This paper examines various factors in bipolar device construction and design, and discusses their impact on radiation hardness. The intent of the paper is to improve understanding of the underlying mechanisms for practical devices without special test structures, and to provide (1) guidance in ways to select transistor designs that are more resistant to radiation damage, and (2) methods to estimate the maximum amount of damage that might be expected from a basic transistor design. The latter factor is extremely important in assessing the risk that future lots of devices will be substantially below design limits, which are usually based on test data for older devices.

Ordered polymer nanofibers enhance output brightness in bilayer light-emitting field-effect transistors.

PubMed

Hsu, Ben B Y; Seifter, Jason; Takacs, Christopher J; Zhong, Chengmei; Tseng, Hsin-Rong; Samuel, Ifor D W; Namdas, Ebinazar B; Bazan, Guillermo C; Huang, Fei; Cao, Yong; Heeger, Alan J

2013-03-26

Polymer light emitting field effect transistors are a class of light emitting devices that reveal interesting device physics. Device performance can be directly correlated to the most fundamental polymer science. Control over surface properties of the transistor dielectric can dramatically change the polymer morphology, introducing ordered phase. Electronic properties such as carrier mobility and injection efficiency on the interface can be promoted by ordered nanofibers in the polymer. Moreover, by controlling space charge in the polymer interface, the recombination zone can be spatially extended and thereby enhance the optical output.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Spatial profile of charge storage in organic field-effect transistor nonvolatile memory using polymer electret

NASA Astrophysics Data System (ADS)

She, Xiao-Jian; Liu, Jie; Zhang, Jing-Yu; Gao, Xu; Wang, Sui-Dong

2013-09-01

Spatial profile of the charge storage in the pentacene-based field-effect transistor nonvolatile memories using poly(2-vinyl naphthalene) electret is probed. The electron trapping into the electret after programming can be space dependent with more electron storage in the region closer to the contacts, and reducing the channel length is an effective approach to improve the memory performance. The deficient electron supply in pentacene is proposed to be responsible for the inhomogeneous electron storage in the electret. The hole trapping into the electret after erasing is spatially homogeneous, arising from the sufficient hole accumulation in the pentacene channel.

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

NASA Astrophysics Data System (ADS)

Sakamoto, Toshitsugu; Tada, Munehiro; Tsuji, Yukihide; Makiyama, Hideki; Hasegawa, Takumi; Yamamoto, Yoshiki; Okanishi, Shinobu; Banno, Naoki; Miyamura, Makoto; Okamoto, Koichiro; Iguchi, Noriyuki; Ogasahara, Yasuhiro; Oda, Hidekazu; Kamohara, Shiro; Yamagata, Yasushi; Sugii, Nobuyuki; Hada, Hiromitsu

2015-04-01

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34-1.2 V operating voltage and 12 µA/MHz active current (or 4.5 µW/MHz active power). Furthermore, the sleep current is as low as 0.4 µA when a body bias voltage is applied to the SOTB.

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

NASA Technical Reports Server (NTRS)

MacLeod, Todd, C.; Ho, Fat Duen

2006-01-01

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

Large scale electromechanical transistor with application in mass sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Leisheng; Li, Lijie, E-mail: L.Li@swansea.ac.uk

Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to bemore » used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.« less

Nitrogen-doped partially reduced graphene oxide rewritable nonvolatile memory.

PubMed

Seo, Sohyeon; Yoon, Yeoheung; Lee, Junghyun; Park, Younghun; Lee, Hyoyoung

2013-04-23

As memory materials, two-dimensional (2D) carbon materials such as graphene oxide (GO)-based materials have attracted attention due to a variety of advantageous attributes, including their solution-processability and their potential for highly scalable device fabrication for transistor-based memory and cross-bar memory arrays. In spite of this, the use of GO-based materials has been limited, primarily due to uncontrollable oxygen functional groups. To induce the stable memory effect by ionic charges of a negatively charged carboxylic acid group of partially reduced graphene oxide (PrGO), a positively charged pyridinium N that served as a counterion to the negatively charged carboxylic acid was carefully introduced on the PrGO framework. Partially reduced N-doped graphene oxide (PrGODMF) in dimethylformamide (DMF) behaved as a semiconducting nonvolatile memory material. Its optical energy band gap was 1.7-2.1 eV and contained a sp2 C═C framework with 45-50% oxygen-functionalized carbon density and 3% doped nitrogen atoms. In particular, rewritable nonvolatile memory characteristics were dependent on the proportion of pyridinum N, and as the proportion of pyridinium N atom decreased, the PrGODMF film lost memory behavior. Polarization of charged PrGODMF containing pyridinium N and carboxylic acid under an electric field produced N-doped PrGODMF memory effects that followed voltage-driven rewrite-read-erase-read processes.

A microwave field-driven transistor-like skyrmionic device with the microwave current-assisted skyrmion creation

NASA Astrophysics Data System (ADS)

Xia, Jing; Huang, Yangqi; Zhang, Xichao; Kang, Wang; Zheng, Chentian; Liu, Xiaoxi; Zhao, Weisheng; Zhou, Yan

2017-10-01

Magnetic skyrmion is a topologically protected domain-wall structure at nanoscale, which could serve as a basic building block for advanced spintronic devices. Here, we propose a microwave field-driven skyrmionic device with the transistor-like function, where the motion of a skyrmion in a voltage-gated ferromagnetic nanotrack is studied by micromagnetic simulations. It is demonstrated that the microwave field can drive the motion of a skyrmion by exciting the propagating spin waves, and the skyrmion motion can be governed by a gate voltage. We also investigate the microwave current-assisted creation of a skyrmion to facilitate the operation of the transistor-like skyrmionic device on the source terminal. It is found that the microwave current with an appropriate frequency can reduce the threshold current density required for the creation of a skyrmion from the ferromagnetic background. The proposed transistor-like skyrmionic device operated with the microwave field and current could be useful for building future skyrmion-based circuits.

Total Ionizing Dose Influence on the Single-Event Upset Sensitivity of 130-nm PD SOI SRAMs

NASA Astrophysics Data System (ADS)

Zheng, Qiwen; Cui, Jiangwei; Liu, Mengxin; Zhou, Hang; Liu, Mohan; Wei, Ying; Su, Dandan; Ma, Teng; Lu, Wu; Yu, Xuefeng; Guo, Qi; He, Chengfa

2017-07-01

Effect of total ionizing dose (TID) on single-event upset (SEU) hardness of 130 nm partially depleted (PD) silicon-on-insulator (SOI) static random access memories (SRAMs) is investigated in this paper. The measurable synergistic effect of TID on SEU sensitivity of 130-nm PD SOI SRAM was observed in our experiment, even though that is far less than micrometer and submicrometer devices. Moreover, SEU cross section after TID irradiation has no dependence on the data pattern that was applied during TID exposure: SEU cross sections are characterized by TID data pattern and its complement data pattern are decreased consistently rather than a preferred state and a nonpreferred state as micrometer and sub-micrometer SRAMs. The memory cell test structure allowing direct measurement of static noise margin (SNM) under standby operation was designed using identical memory cell layout of SRAM. Direct measurement of the memory cell SNM shows that both data sides' SNM is decreased by TID, indicating that SEU cross section of 130-nm PD SOI SRAM will be increased by TID. And, the decreased SNM is caused by threshold shift in memory cell transistors induced by “radiation-induced narrow channel effect”.

A transistor based on 2D material and silicon junction

NASA Astrophysics Data System (ADS)

Kim, Sanghoek; Lee, Seunghyun

2017-07-01

A new type of graphene-silicon junction transistor based on bipolar charge-carrier injection was designed and investigated. In contrast to many recent studies on graphene field-effect transistor (FET), this device is a new type of bipolar junction transistor (BJT). The transistor fully utilizes the Fermi level tunability of graphene under bias to increase the minority-carrier injection efficiency of the base-emitter junction in the BJT. Single-layer graphene was used to form the emitter and the collector, and a p-type silicon was used as the base. The output of this transistor was compared with a metal-silicon junction transistor ( i.e. surface-barrier transistor) to understand the difference between a graphene-silicon junction and metal-silicon Schottky junction. A significantly higher current gain was observed in the graphene-silicon junction transistor as the base current was increased. The graphene-semiconductor heterojunction transistor offers several unique advantages, such as an extremely thin device profile, a low-temperature (< 110 °C) fabrication process, low cost (no furnace process), and high-temperature tolerance due to graphene's stability. A transistor current gain ( β) of 33.7 and a common-emitter amplifier voltage gain of 24.9 were achieved.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Solving the integration problem of one transistor one memristor architecture with a Bi-layer IGZO film through synchronous process

NASA Astrophysics Data System (ADS)

Chang, Che-Chia; Liu, Po-Tsun; Chien, Chen-Yu; Fan, Yang-Shun

2018-04-01

This study demonstrates the integration of a thin film transistor (TFT) and resistive random-access memory (RRAM) to form a one-transistor-one-resistor (1T1R) configuration. With the concept of the current conducting direction in RRAM and TFT, a triple-layer stack design of Pt/InGaZnO/Al2O3 is proposed for both the switching layer of RRAM and the channel layer of TFT. This proposal decreases the complexity of fabrication and the numbers of photomasks required. Also, the robust endurance and stable retention characteristics are exhibited by the 1T1R architecture for promising applications in memory-embedded flat panel displays.

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

PubMed Central

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-01-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing. PMID:26349444

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

NASA Astrophysics Data System (ADS)

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-09-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

High-performance a MoS2 nanosheet-based nonvolatile memory transistor with a ferroelectric polymer and graphene source-drain electrode

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Im, Seongil

2015-11-01

Two-dimensional (2D) van der Waals (vdWs) materials are a class of new materials due to their unique physical properties. Of the many 2D vdWs materials, molybdenum disulfide (MoS2) is a representative n-type transition-metal dichalcogenide (TMD) semiconductor. Here, we report on a high-performance MoS2 nanosheet-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. In order to enhance the ohmic contact property, we use graphene flakes as source/drain electrodes prepared by using the direct imprinting method with an elastomer stamp. The MoS2 ferroelectric field-effect transistor (FeFET) shows the highest linear electron mobility value of 175 cm2/Vs with a high on/off current ratio of more than 107, and a very clear memory window of more than 15 V. The program and erase dynamics and the static retention properties are also well demonstrated.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Fabrication of eco-friendly PNP transistor using RF magnetron sputtering

NASA Astrophysics Data System (ADS)

Kumar, B. Santhosh; Harinee, N.; Purvaja, K.; Shanker, N. Praveen; Manikandan, M.; Aparnadevi, N.; Mukilraj, T.; Venkateswaran, C.

2018-05-01

An effort has been made to fabricate a thin film transistor using eco-friendly oxide semiconductor materials. Oxide semiconductor materials are cost - effective, thermally and chemically stable with high electron/hole mobility. Copper (II) oxide is a p-type semiconductor and zinc oxide is an n-type semiconductor. A pnp thin film transistor was fabricated using RF magnetron sputtering. The films deposited have been subjected to structural characterization using AFM. I-V characterization of the fabricated device, Ag/CuO/ZnO/CuO/Ag, confirms transistor behaviour. The mechanism of electron/hole transport of the device is discussed below.

Application of Transistors in Textiles: Monitoring Water Transportation Behaviour in Fibrous Assemblies

NASA Astrophysics Data System (ADS)

Chatterjee, Arobindo; Singh, Pratibha; Ghosh, Subrata

2017-06-01

Simple semiconductor device has been used for amplifying the analog signals, obtained with the change in electrical resistance in fibrous assembly and converting these amplified copies of signals to digital signals. This paper deals with the application of transistors as amplifier, as well as switch. Different circuit configurations using transistors have been tried for sensing and reciprocating the real time data on suitable display device. It is found that transistors configured as common-emitter amplifiers can precisely sense the liquid at the surface of fibrous assembly at different levels with respect to time.

‘Symbiotic’ semiconductors: unusual and counter-intuitive Ge/Si/O interactions

NASA Astrophysics Data System (ADS)

George, T.; Li, P. W.; Chen, K. H.; Peng, K. P.; Lai, W. T.

2017-03-01

Since the inception of the first transistors in the 1940s, the immense body of work on the Group IV semiconductors, Si and Ge, has spearheaded spectacular advances in modern integrated-circuit (IC) technology that has enabled a vast landscape of device applications in logic, memory, and computing. Although initially Si supplanted Ge as the material of choice for metal-oxide-semiconductor field-effect transistors, Ge-based devices are now breaking new ground. Widespread and innovative Ge-based applications exist in optoelectronics, communications, microelectro-mechanical systems, and energy harvesting/savings. On the fundamental, materials science front, while it is well known that Ge and Si are fully miscible in each other, the nature and extent of their attraction for each other has largely been unexplored. In this paper, we report a rather curious interplay between Ge and Si that occurs at high temperature (~900 °C) and that can be best described as ‘symbiotic’. Each element appears to facilitate reactions in the other which would otherwise not be possible. Oxygen intersititials also appear to play a major role in these reactions. Our experimental work has allowed us to classify four distinct regimes where these reactions occur. We describe these conditions and provide the necessary theoretical explanations for these results.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

PubMed

Dey, Anil W; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik

2013-01-01

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

Healing of voids in the aluminum metallization of integrated circuit chips

NASA Technical Reports Server (NTRS)

Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas R.

1990-01-01

The thermal stability of GaAs modulation-doped field effect transistors (MODFETs) is evaluated in order to identify failure mechanisms and validate the reliability of these devices. The transistors were exposed to thermal step-stress and characterized at ambient temperatures to indicate device reliability, especially that of the transistor ohmic contacts with and without molybdenum diffusion barriers. The devices without molybdenum exhibited important transconductance deterioration. MODFETs with molybdenum diffusion barriers were tolerant to temperatures above 300 C. This tolerance indicates that thermally activated failure mechanisms are slow at operational temperatures. Therefore, high-reliability MODFET-based circuits are possible.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Photoresponse and photo-induced memory effect in the organic field-effect transistor based on AlOX nanoparticles at the interface of semiconductor/dielectric

NASA Astrophysics Data System (ADS)

Cheng, Yunfei; Wang, Wu

2017-10-01

In this work, the photoresponse and photo-induced memory effect were demonstrated in an organic field-effect transistor (OFET) with semiconductor pentacene and SiO2 as the active and gate dielectric layers, respectively. By inserting AlOX nanoparticles (NPs) at the interface of pentacene/SiO2, obvious enhancing photoresponse was obtained in the OFET with the maximum responsivity and photosensitivity of about 15 A/W and 100, respectively. Moreover, the stable photoinduced memory effect was achieved in the OFET, attributing to the photogenerated electrons captured by the interface traps of the AlOX NPs/SiO2.

Analysis of a Memory Device Failure

NASA Technical Reports Server (NTRS)

Nicolas, David P.; Devaney, John; Gores, Mark; Dicken, Howard

1998-01-01

The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Resistive Random Access Memory from Materials Development fnd Engineering to Novel Encryption and Neuromorphic Applications

NASA Astrophysics Data System (ADS)

Beckmann, Karsten

Resistive random access memory (ReRAM or RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance state of ReRAM devices can be precisely tuned by modulating switching voltages, by limiting peak current, and by adjusting the switching pulse properties. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. I have developed two processes based on 100 and 300mm wafer platforms to demonstrate functional HfO2 based ReRAM devices. The first process is designed for a rapid materials engineering and device characterization, while the second is an advanced hybrid ReRAM/CMOS combination based on the IBM 65nm 10LPe process technology. The 100mm wafer efforts were used to show impacts of etch processes on ReRAM switching performance and the need for a rigorous structural evaluation of ReRAM devices before starting materials development. After an etch development, a bottom electrode comparison between the inert materials Pt, Ru and W was performed where Ru showed superior results with respect to yield and resilience against environmental impacts such as humidity over a 2-month period. A comparison of amorphous and crystalline devices showed no statistical difference in the performance with respect to random telegraph noise. This demonstrates, that the forming process fundamentally alters the crystallographic structure within and around the filament. The 300mm wafer development efforts were aimed towards implementing ReRAM in the FEOL, combined with CMOS, to yield a seamless process flow of 1 transistor 1 ReRAM structures (1T1R). This technology was customized with custom-developed tungsten metal 1 (M1) and dual tungsten/copper via 1 (V1) structures, within which the ReRAM stack is embedded. The ReRAM itself consists of an inert W bottom electrode, HfO2 based active switching layer, a Ti oxygen scavenger layer, and an inert TiN top electrode. Linear sweep and controlled pulse (down to 5 ns) based electrical characterization of 1 transistor 1 ReRAM (1T1R) elements was performed to determine key properties including endurance, reliability, and threshold voltages. We demonstrated endurance values above 1010 cycles with an average on/off ratio of 10, and pulse voltages for set/reset operation of +/-1.5V. The on-chip 1T1R structures show an excellent controllability with respect to the low and high resistive states by manipulating the peak current from 75 up to 350 mu?A resulting in 10 distinct low resistance states (LRS). Our results demonstrate that the set operation (which shifts the ReRAM device from the high to the low resistance state) is only dependent on the voltage of the switching pulse and the peak current limit. The reset operation, however, occurs in an analog fashion and appears to be dependent on the total energy of the applied switching pulse. Pulse energy was modulated by varying the peak voltage resulting in a larger relative change of the ReRAM device resistance. The incremental resistance changes are ideally suited to emulate synaptic weights for future implementation into neuromorphic architectures. Switching results from these devices were also used to develop a model time-delay physical unclonable function (PUF) circuit, which showed excellent performance when compared to a pure CMOS implementation with significant improvements in uniqueness, size and accuracy.

Spiers memorial lecture. Organic electronics: an organic materials perspective.

PubMed

Wudl, Fred

2014-01-01

This Introductory Lecture is intended to provide a background to Faraday Discussion 174: "Organic Photonics and Electronics" and will consist of a chronological, subjective review of organic electronics. Starting with "ancient history" (1888) and history (1950-present), the article will take us to the present. The principal developments involved the processes of charge carrier generation and charge transport in molecular solids, starting with insulators (photoconductors) and moving to metals, to semiconductors and ending with the most popular semiconductor devices, such as organic light-emitting diodes (OLEDs), organic field effect transistors (OFETs) and organic photovoltaics (OPVs). The presentation will be from an organic chemistry/materials point of view.

Nondestructive Memory Elements Based on Polymeric Langmuir-Blodgett Thin Films

NASA Astrophysics Data System (ADS)

Reece, T. J.; Ducharme, S.

2007-03-01

Ferroelectric field effect transistors (FeFETs) have attracted much attention recently because of their low power consumption and fast nondestructive readout. Among the ferroelectric thin films used in FET devices; the ferroelectric copolymer of polyvinylidene fluoride, PVDF (C2H2F2), with trifluoroethylene, TrFE (C2HF3), has distinct advantages, including low dielectric constant, low processing temperature, low cost and compatibility with organic semiconductors. By employing the Langmuir-Blodgett technique, we are able to deposit films as thin as 1.8 nm. We discuss the characterization, modeling and fabrication of metal-ferroelectric-insulator-semiconductor (MFIS) structures incorporating these films.

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

PubMed

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 2

NASA Technical Reports Server (NTRS)

Lee, F. C.; Chen, D. Y.; Jovanic, M.; Hopkins, D. C.

1985-01-01

Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.

Combinatorial study of zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

2008-01-01

Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

Triggering Mechanism for Neutron Induced Single-Event Burnout in Power Devices

NASA Astrophysics Data System (ADS)

Shoji, Tomoyuki; Nishida, Shuichi; Hamada, Kimimori

2013-04-01

Cosmic ray neutrons can trigger catastrophic failures in power devices. It has been reported that parasitic transistor action causes single-event burnout (SEB) in power metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). However, power diodes do not have an inherent parasitic transistor. In this paper, we describe the mechanism triggering SEB in power diodes for the first time using transient device simulation. Initially, generated electron-hole pairs created by incident recoil ions generate transient current, which increases the electron density in the vicinity of the n-/n+ boundary. The space charge effect of the carriers leads to an increase in the strength of the electric field at the n-/n+ boundary. Finally, the onset of impact ionization at the n-/n+ boundary can trigger SEB. Furthermore, this failure is closely related to diode secondary breakdown. It was clarified that the impact ionization at the n-/n+ boundary is a key point of the mechanism triggering SEB in power devices.

Charge collection and SEU mechanisms

NASA Astrophysics Data System (ADS)

Musseau, O.

1994-01-01

In the interaction of cosmic ions with microelectronic devices a dense electron-hole plasma is created along the ion track. Carriers are separated and transported by the electric field and under the action of the concentration gradient. The subsequent collection of these carriers induces a transient current at some electrical node of the device. This "ionocurrent" (single ion induced current) acts as any electrical perturbation in the device, propagating in the circuit and inducing failures. In bistable systems (registers, memories) the stored data can be upset. In clocked devices (microprocessors) the parasitic perturbation may propagate through the device to the outputs. This type of failure only effects the information, and do not degrade the functionally of the device. The purpose of this paper is to review the mechanisms of single event upset in microelectronic devices. Experimental and theoretical results are presented, and actual questions and problems are discussed. A brief introduction recalls the creation of the dense plasma of electron-hole pairs. The basic processes for charge collection in a simple np junction (drift and diffusion) are presented. The funneling-field effect is discussed and experimental results are compared to numerical simulations and semi-empirical models. Charge collection in actual microelectronic structures is then presented. Due to the parasitic elements, coupling effects are observed. Geometrical effects, in densely packed structures, results in multiple errors. Electronic couplings are due to the carriers in excess, acting as minority carriers, that trigger parasitic bipolar transistors. Single event upset of memory cells is discussed, based on numerical and experimental data. The main parameters for device characterization are presented. From the physical interpretation of charge collection mechanisms, the intrinsic sensitivity of various microelectronic technologies is determined and compared to experimental data. Scaling laws and future trends are finally discussed.

Acoustic transistor: Amplification and switch of sound by sound

NASA Astrophysics Data System (ADS)

Liang, Bin; Kan, Wei-wei; Zou, Xin-ye; Yin, Lei-lei; Cheng, Jian-chun

2014-08-01

We designed an acoustic transistor to manipulate sound in a manner similar to the manipulation of electric current by its electrical counterpart. The acoustic transistor is a three-terminal device with the essential ability to use a small monochromatic acoustic signal to control a much larger output signal within a broad frequency range. The output and controlling signals have the same frequency, suggesting the possibility of cascading the structure to amplify an acoustic signal. Capable of amplifying and switching sound by sound, acoustic transistors have various potential applications and may open the way to the design of conceptual devices such as acoustic logic gates.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

A magnetic phase-transition graphene transistor with tunable spin polarization

NASA Astrophysics Data System (ADS)

Vancsó, Péter; Hagymási, Imre; Tapasztó, Levente

2017-06-01

Graphene nanoribbons (GNRs) have been proposed as potential building blocks for field effect transistor (FET) devices due to their quantum confinement bandgap. Here, we propose a novel GNR device concept, enabling the control of both charge and spin signals, integrated within the simplest three-terminal device configuration. In a conventional FET device, a gate electrode is employed to tune the Fermi level of the system in and out of a static bandgap. By contrast, in the switching mechanism proposed here, the applied gate voltage can dynamically open and close an interaction gap, with only a minor shift of the Fermi level. Furthermore, the strong interplay of the band structure and edge spin configuration in zigzag ribbons enables such transistors to carry spin polarized current without employing an external magnetic field or ferromagnetic contacts. Using an experimentally validated theoretical model, we show that such transistors can switch at low voltages and high speed, and the spin polarization of the current can be tuned from 0% to 50% by using the same back gate electrode. Furthermore, such devices are expected to be robust against edge irregularities and can operate at room temperature. Controlling both charge and spin signal within the simplest FET device configuration could open up new routes in data processing with graphene based devices.

Circuit-level simulation of transistor lasers and its application to modelling of microwave photonic links

NASA Astrophysics Data System (ADS)

Iezekiel, Stavros; Christou, Andreas

2015-03-01

Equivalent circuit models of a transistor laser are used to investigate the suitability of this relatively new device for analog microwave photonic links. The three-terminal nature of the device enables transistor-based circuit design techniques to be applied to optoelectronic transmitter design. To this end, we investigate the application of balanced microwave amplifier topologies in order to enable low-noise links to be realized with reduced intermodulation distortion and improved RF impedance matching compared to conventional microwave photonic links.

EDITORIAL: Flexible OLEDs and organic electronics Flexible OLEDs and organic electronics

NASA Astrophysics Data System (ADS)

Kim, Jang-Joo; Han, Min-Koo; Noh, Yong-Young

2011-03-01

Following the great discovery of the electrically conducting polymer, doped polyacetylene, which was honorably recognized in 2000 with the Nobel Prize in chemistry, conjugated molecules, i.e. organic semiconductors, have become an attractive class of active elements for various electronic or opto-electronic applications. Significant effort has been made in both academia and industry to investigate π-conjugated molecules for their unique electrical or opto-electrical properties over the last three decades. The discovery of electroluminescence in conjugated small molecules in 1982 and in polymers in 1989 was a major breakthrough, bringing those molecules to commercial applications within reach for the first time in (opto-)electronic devices, such as organic light-emitting diodes (OLEDs), photovoltaic cells (OPVs), and field-effect transistors (OFETs). Nowadays, we use OLED displays in everyday life in mobile devices. The potential of these devices, which have been fabricated with conjugated molecules, lies in the possibility to combine the advantages of solution processability, chemical tunability and material strength of polymers with the typical properties of plastics, to realize low-cost, large-area electronic devices on flexible substrates by solution deposition and direct-write graphic art printing techniques. The articles in the flexible OLEDs and organic electronics special issue in Semiconductor Science and Technology deal with a diversity of topics and effectively reflect the current status of research from all over the world on various organic electronic devices, including OLEDs, OPVs, and OFETs. Firstly, S Park et al describe the recent progress in thin-film encapsulation techniques for flexible AM-OLED and large-area OLED lightings, and their applications are discussed by J-W Park et al. Flexible active-matrix OLEDs on plastics require stable and flexible thin-film transistors processed at low temperature. Metal oxide thin-film transistors are proposed as one of the best candidates for the purpose, and J K Jeong discusses their status and perspectives. Next, several excellent research articles on OFETs follow. In particular, Y-Y Noh et al introduce an interesting method to control charge injection in top-gated OFETs by insertion of various self-assembled monolayers in their paper entitled 'Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering'. We would like to thank all the authors for their contributions, which combine new results and profound overviews of the state of the art in flexible OLEDs and organic electronics areas; it is this combination that most often adds to the value of topical issues. Special thanks also go to the staff of IOP Publishing, particularly Ms Alice Malhador, for contributing to the success of this effort. In this special issue, many wonderful reviews and research articles provide a detailed overview of recent progress in OLEDs, OPVs and OFETs as well as a scientific understanding of the device physics with these materials. We sincerely believe this special issue is a timely publication and will give productive information to a broad range of readers. Flexible OLEDs and organic electronics Contents Thin film encapsulation for flexible AM-OLED: a review Jin-Seong Park, Heeyeop Chae, Ho Kyoon Chung and Sang In Lee Large-area OLED lightings and their applications J W Park, D C Shin and S H Park Controlling contact resistance in top-gate polythiophene-based field-effect transistors by molecular engineering Yong-Young Noh, Xiaoyang Cheng, Marta Tello, Mi-Jung Lee and Henning Sirringhaus Branched polythiophene as a new amorphous semiconducting polymer for an organic field-effect transistor Makoto Karakawa, Yutaka Ie and Yoshio Aso Influence of mechanical strain on the electrical properties of flexible organic thin-film transistors Fang-Chung Chen, Tzung-Da Chen, Bing-Ruei Zeng and Ya-Wei Chung Frequency operation of low-voltage, solution-processed organic field-effect transistors M Caironi, Y-Y Noh and H Sirringhaus Nonvolatile memory thin-film transistors using an organic ferroelectric gate insulator and an oxide semiconducting channel Sung-Min Yoon, Shinhyuk Yang, Chun-Won Byun, Soon-Won Jung, Min-Ki Ryu, Sang-Hee Ko Park, ByeongHoon Kim, Himchan Oh, Chi-Sun Hwang and Byoung-Gon Yu The status and perspectives of metal oxide thin-film transistors for active matrix flexible displays Jae Kyeong Jeong Vertical phase segregation of hybrid poly(3-hexylthiophene) and fullerene derivative composites controlled via velocity of solvent drying Tao Song, Zhongwei Wu, Yingfen Tu, Yizheng Jin and Baoquan Sun Variations of cell performance in ITO-free organic solar cells with increasing cell areas Jun-Seok Yeo, Jin-Mun Yun, Seok-Soon Kim, Dong-Yu Kim, Junkyung Kim and Seok-In Na

Modeling and Design of GaN High Electron Mobility Transistors and Hot Electron Transistors through Monte Carlo Particle-based Device Simulations

NASA Astrophysics Data System (ADS)

Soligo, Riccardo

In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and Hot Electron Transistors. Chapter 1 is dedicated to the description of the simulation tool used to obtain the results shown in this work. Moreover, a separate section is dedicated the set up of a procedure to validate to the tunneling algorithm recently implemented in the simulator. Chapter 2 introduces High Electron Mobility Transistors (HEMTs), state-of-art devices characterized by highly non linear transport phenomena that require the use of advanced simulation methods. The techniques for device modeling are described applied to a recent GaN-HEMT, and they are validated with experimental measurements. The main techniques characterization techniques are also described, including the original contribution provided by this work. Chapter 3 focuses on a popular technique to enhance HEMTs performance: the down-scaling of the device dimensions. In particular, this chapter is dedicated to lateral scaling and the calculation of a limiting cutoff frequency for a device of vanishing length. Finally, Chapter 4 and Chapter 5 describe the modeling of Hot Electron Transistors (HETs). The simulation approach is validated by matching the current characteristics with the experimental one before variations of the layouts are proposed to increase the current gain to values suitable for amplification. The frequency response of these layouts is calculated, and modeled by a small signal circuit. For this purpose, a method to directly calculate the capacitance is developed which provides a graphical picture of the capacitative phenomena that limit the frequency response in devices. In Chapter 5 the properties of the hot electrons are investigated for different injection energies, which are obtained by changing the layout of the emitter barrier. Moreover, the large signal characterization of the HET is shown for different layouts, where the collector barrier was scaled.

Total-dose radiation effects data for semiconductor devices, volume 1. [radiation resistance of components for the Galileo Project

NASA Technical Reports Server (NTRS)

Price, W. E.; Martin, K. E.; Nichols, D. K.; Gauthier, M. K.; Brown, S. F.

1981-01-01

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. Data are presented by JPL for various NASA space programs on diodes, bipolar transistors, field effect transistors, silicon-controlled rectifiers, and optical devices. A vendor identification code list is included along with semiconductor device electrical parameter symbols and abbreviations.

Development of high temperature, high radiation resistant silicon semiconductors

NASA Technical Reports Server (NTRS)

Whorl, C. A.; Evans, A. W.

1972-01-01

The development of a hardened silicon power transistor for operation in severe nuclear radiation environments at high temperature was studied. Device hardness and diffusion techniques are discussed along with the geometries of hardened power transistor chips. Engineering drawings of 100 amp and 5 amp silicon devices are included.

Optical bistability for optical signal processing and computing

NASA Astrophysics Data System (ADS)

Peyghambarian, N.; Gibbs, H. M.

1985-02-01

Optical bistability (OB) is a phenomenon in which a nonlinear medium responds to an optical input beam by changing its transmission abruptly from one value to another. A 'nonlinear medium' is a medium in which the index of refraction depends on the incident light intensity. A device is said to be optically bistable if two stable output states exist for the same value of the input. Optically bistable devices can perform a number of logic functions related to optical memory, optical transistor, optical discriminator, optical limiter, optical oscillator, and optical gate. They also have the potential for subpicosecond switching, greatly exceeding the capability of electronics. This potential is one of several advantages of optical data processing over electronic processing. Other advantages are greater immunity to electromagnetic interference and crosstalk, and highly parallel processing capability. The present investigation is mainly concerned with all-optical etalon devices. The considered materials, include GaAs, ZnS and ZnSe, CuCl, InSb, InAs, and CdS.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Variable temperature performance of a fully screen printed transistor switch

NASA Astrophysics Data System (ADS)

Zambou, Serges; Magunje, Batsirai; Rhyme, Setshedi; Walton, Stanley D.; Idowu, M. Florence; Unuigbe, David; Britton, David T.; Härting, Margit

2016-12-01

This article reports on the variable temperature performance of a flexible printed transistor which works as a current driven switch. In this work, electronic ink is formulated from nanostructured silicon produced by milling polycrystalline silicon. The study of the silicon active layer shows that its conductivity is based on thermal activation of carriers, and could be used as active layers in active devices. We further report on the transistors switching operation and their electrical performance under variable temperature. The reliability of the transistors at constant current bias was also investigated. Analysis of the electrical transfer characteristics from 340 to 10 K showed that the printed devices' current ON/OFF ratio increases as temperature decreases making it a better switch at lower temperatures. A constant current bias on a terminal for up to six hours shows extraordinary stability in electrical performance of the device.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Graphene - ferroelectric and MoS2 - ferroelectric heterostructures for memory applications

NASA Astrophysics Data System (ADS)

Lipatov, Alexey; Sharma, Pankaj; Gruverman, Alexei; Sinitskii, Alexander

In recent years there has been an unprecedented interest in two-dimensional (2D) materials with unique physical and chemical properties that cannot be found in their three-dimensional (3D) counterparts. One of the important advantages of 2D materials is that they can be easily integrated with other 2D materials and functional films, resulting in multilayered structures with new properties. We fabricated and tested electronic and memory properties of field-effect transistors (FETs) based on a single-layer graphene combined with lead zirconium titanate (PZT) substrate. Previously studied graphene-PZT devices exhibited an unusual electronic behavior such as clockwise hysteresis of electronic transport, in contradiction with counterclockwise polarization dependence of PZT. We investigated how the interplay of polarization and interfacial phenomena affects the electronic behavior and memory characteristics of graphene-PZT FETs, explain the origin of unusual clockwise hysteresis and experimentally demonstrate a reversed polarization-dependent hysteresis of electronic transport. In addition we fabricated and tested properties of MoS2-PZT FETs which exhibit a large hysteresis of electronic transport with high ON/OFF ratios. We demonstrate that MoS2-PZT memories have a number of advantages over commercial FeRAMs, such as nondestructive data readout, low operation voltage, wide memory window and the possibility to write and erase them both electrically and optically.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

NASA Technical Reports Server (NTRS)

Kolasinski, W. A.; Koga, R.; Blake, J. B.; Brucker, G.; Pandya, P.; Petersen, E.; Price, W.

1982-01-01

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Light sensitivity of a one transistor-one capacitor memory cell when used as a micromirror actuator in projector applications

NASA Astrophysics Data System (ADS)

Huffman, James Douglas

2001-11-01

The most important issue facing the future business success of the Digital Micromirror Device or DMD™ produced by Texas Instruments is the cost of the actual device. As the business and consumer markets call for higher resolution displays, the array size will have to be increased to incorporate more pixels. The manufacturing costs associated with building these higher resolution displays follow an exponential relation with the number of pixels due to yield loss and reduced number of chips per silicon wafer. Each pixel is actuated by electrostatics that are provided by a memory cell that is built in the underlying silicon substrate. One way to decrease cost of the wafer is to change the memory cell architecture from a static random access configuration or SRAM to a dynamic random access configuration or DRAM. This change has the benefits of having fewer components per area and a lower metal density. This reduction in the component count and metal density has a dramatic effect on the yield of the memory array by reducing the particle sensitivity of the underlying cell. The main drawback to using a DRAM configuration in a display application is the light sensitivity of a charge storage device built in the silicon substrate. As the photons pass through the mechanical micromirrors and illuminate the DRAM cell, the effective electrostatic potential of the memory element used for the mirror actuation is reduced. This dissertation outlines the issues associated with the light sensitivity of a DRAM memory cell as the actuation element for a micromirror. The concept of charge depletion on a silicon capacitor due to recombination of photogenerated carriers is explored and experimentally verified. The effects of the reduced potential on the capacitor on the micromirror are also explored. Optical modeling is used to determine the incoming photon flux to determine the benefits of adding a charge recombination region as part of the DRAM memory cell. Several options are explored to reduce the effect of the incoming photons on the potential of the memory cell. The results will show that a 1T1C memory cell with N-type recombination regions and maximum light shielding is sufficient for a projector application.

DFM flow by using combination between design based metrology system and model based verification at sub-50nm memory device

NASA Astrophysics Data System (ADS)

Kim, Cheol-kyun; Kim, Jungchan; Choi, Jaeseung; Yang, Hyunjo; Yim, Donggyu; Kim, Jinwoong

2007-03-01

As the minimum transistor length is getting smaller, the variation and uniformity of transistor length seriously effect device performance. So, the importance of optical proximity effects correction (OPC) and resolution enhancement technology (RET) cannot be overemphasized. However, OPC process is regarded by some as a necessary evil in device performance. In fact, every group which includes process and design, are interested in whole chip CD variation trend and CD uniformity, which represent real wafer. Recently, design based metrology systems are capable of detecting difference between data base to wafer SEM image. Design based metrology systems are able to extract information of whole chip CD variation. According to the results, OPC abnormality was identified and design feedback items are also disclosed. The other approaches are accomplished on EDA companies, like model based OPC verifications. Model based verification will be done for full chip area by using well-calibrated model. The object of model based verification is the prediction of potential weak point on wafer and fast feed back to OPC and design before reticle fabrication. In order to achieve robust design and sufficient device margin, appropriate combination between design based metrology system and model based verification tools is very important. Therefore, we evaluated design based metrology system and matched model based verification system for optimum combination between two systems. In our study, huge amount of data from wafer results are classified and analyzed by statistical method and classified by OPC feedback and design feedback items. Additionally, novel DFM flow would be proposed by using combination of design based metrology and model based verification tools.

Simulation study of ballistic spin-MOSFET devices with ferromagnetic channels based on some Heusler and oxide compounds

NASA Astrophysics Data System (ADS)

Graziosi, Patrizio; Neophytou, Neophytos

2018-02-01

Newly emerged materials from the family of Heuslers and complex oxides exhibit finite bandgaps and ferromagnetic behavior with Curie temperatures much higher than even room temperature. In this work, using the semiclassical top-of-the-barrier FET model, we explore the operation of a spin-MOSFET that utilizes such ferromagnetic semiconductors as channel materials, in addition to ferromagnetic source/drain contacts. Such a device could retain the spin polarization of injected electrons in the channel, the loss of which limits the operation of traditional spin transistors with non-ferromagnetic channels. We examine the operation of four material systems that are currently considered some of the most prominent known ferromagnetic semiconductors: three Heusler-type alloys (Mn2CoAl, CrVZrAl, and CoVZrAl) and one from the oxide family (NiFe2O4). We describe their band structures by using data from DFT (Density Functional Theory) calculations. We investigate under which conditions high spin polarization and significant ION/IOFF ratio, two essential requirements for the spin-MOSFET operation, are both achieved. We show that these particular Heusler channels, in their bulk form, do not have adequate bandgap to provide high ION/IOFF ratios and have small magnetoconductance compared to state-of-the-art devices. However, with confinement into ultra-narrow sizes down to a few nanometers, and by engineering their spin dependent contact resistances, they could prove promising channel materials for the realization of spin-MOSFET transistor devices that offer combined logic and memory functionalities. Although the main compounds of interest in this paper are Mn2CoAl, CrVZrAl, CoVZrAl, and NiFe2O4 alone, we expect that the insight we provide is relevant to other classes of such materials as well.

Impact of strain on electronic and transport properties of 6 nm hydrogenated germanane nano-ribbon channel double gate field effect transistor

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Sundararaj, Anuraj; Gopalakrishnan, Chandrasekaran; Kasmir Raja, S. V.; Chokhra, Saurabh

2017-11-01

In this work, chair like fully hydrogenated germanane (CGeH) nano-ribbon 6 nm short channel double gate field effect transistor (DG-FET) has been modeled and the impact of strain on the I-V characteristics of CGeH channel has been examined. The bond lengths, binding and formation energies of various hydrogenated geometries of buckled germanane channel were calculated using local density approximation (LDA) with Perdew-Zunger (PZ) and generalized gradient approximation (GGA) with Perdew Burke Ernzerhof (PBE) parameterization. From four various geometries, chair like structure is found to be more stable compared to boat like obtuse, stiruup structure and table like structure. The bandgap versus width, bandgap versus strain characteristics and I-V characteristics had been analyzed at room temperature using density functional theory (DFT). Using self consistent calculation it was observed that the electronic properties of nano-ribbon is independent of length and band structure, but dependent on edge type, strain [Uni-axial (ɛ xx ), bi-axial (ɛ xx   =  ɛ yy )] and width of the ribbon. The strain engineered hydrogenated germanane (GeH) showed wide direct bandgap (2.3 eV) which could help to build low noise electronic devices that operates at high frequencies. The observed bi-axial compression has high impact on the device transport characteristics with peak to valley ratio (PVR) of 2.14 and 380% increase in peak current compared to pristine CGeH device. The observed strain in CGeH DG-FET could facilitate in designing novel multiple-logic memory devices due to multiple negative differential resistance (NDR) regions.

Multimode Silicon Nanowire Transistors

PubMed Central

2014-01-01

The combined capabilities of both a nonplanar design and nonconventional carrier injection mechanisms are subject to recent scientific investigations to overcome the limitations of silicon metal oxide semiconductor field effect transistors. In this Letter, we present a multimode field effect transistors device using silicon nanowires that feature an axial n-type/intrinsic doping junction. A heterostructural device design is achieved by employing a self-aligned nickel-silicide source contact. The polymorph operation of the dual-gate device enabling the configuration of one p- and two n-type transistor modes is demonstrated. Not only the type but also the carrier injection mode can be altered by appropriate biasing of the two gate terminals or by inverting the drain bias. With a combined band-to-band and Schottky tunneling mechanism, in p-type mode a subthreshold swing as low as 143 mV/dec and an ON/OFF ratio of up to 104 is found. As the device operates in forward bias, a nonconventional tunneling transistor is realized, enabling an effective suppression of ambipolarity. Depending on the drain bias, two different n-type modes are distinguishable. The carrier injection is dominated by thermionic emission in forward bias with a maximum ON/OFF ratio of up to 107 whereas in reverse bias a Schottky tunneling mechanism dominates the carrier transport. PMID:25303290

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Orientation selectivity in a multi-gated organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

2016-06-01

Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

Gallium Arsenide Pilot Line for High Performance Components

DTIC Science & Technology

1992-05-28

two transistors’ characteristics were a close enough match to use as pull -up, high resistance loads in the cell. FET Data Unfortunately, data obtained...length transistors in 4K SRAM II, we can predict the performance of the memory chip. Since there is essentially no active pull up capability in the c a...Second, the 2/2 Am DFET’s threshold and "ON" current could be adjusted. Or third, a different size DFET pull -up transistor could be used which more

Enhanced Performance of Field-Effect Transistors Based on Black Phosphorus Channels Reduced by Galvanic Corrosion of Al Overlayers.

PubMed

Lee, Sangik; Yoon, Chansoo; Lee, Ji Hye; Kim, Yeon Soo; Lee, Mi Jung; Kim, Wondong; Baik, Jaeyoon; Jia, Quanxi; Park, Bae Ho

2018-06-06

Two-dimensional (2D)-layered semiconducting materials with considerable band gaps are emerging as a new class of materials applicable to next-generation devices. Particularly, black phosphorus (BP) is considered to be very promising for next-generation 2D electrical and optical devices because of its high carrier mobility of 200-1000 cm 2 V -1 s -1 and large on/off ratio of 10 4 to 10 5 in field-effect transistors (FETs). However, its environmental instability in air requires fabrication processes in a glovebox filled with nitrogen or argon gas followed by encapsulation, passivation, and chemical functionalization of BP. Here, we report a new method for reduction of BP-channel devices fabricated without the use of a glovebox by galvanic corrosion of an Al overlayer. The reduction of BP induced by an anodic oxidation of Al overlayer is demonstrated through surface characterization of BP using atomic force microscopy, Raman spectroscopy, and X-ray photoemission spectroscopy along with electrical measurement of a BP-channel FET. After the deposition of an Al overlayer, the FET device shows a significantly enhanced performance, including restoration of ambipolar transport, high carrier mobility of 220 cm 2 V -1 s -1 , low subthreshold swing of 0.73 V/decade, and low interface trap density of 7.8 × 10 11 cm -2 eV -1 . These improvements are attributed to both the reduction of the BP channel and the formation of an Al 2 O 3 interfacial layer resulting in a high- k screening effect. Moreover, ambipolar behavior of our BP-channel FET device combined with charge-trap behavior can be utilized for implementing reconfigurable memory and neuromorphic computing applications. Our study offers a simple device fabrication process for BP-channel FETs with high performance using galvanic oxidation of Al overlayers.

Properties and Applications of Varistor-Transistor Hybrid Devices

NASA Astrophysics Data System (ADS)

Pandey, R. K.; Stapleton, William A.; Sutanto, Ivan; Scantlin, Amanda A.; Lin, Sidney

2014-05-01

The nonlinear current-voltage characteristics of a varistor device are modified with the help of external agents, resulting in tuned varistor-transistor hybrid devices with multiple applications. The substrate used to produce these hybrid devices belongs to the modified iron titanate family with chemical formula 0.55FeTiO3·0.45Fe2O3 (IHC45), which is a prominent member of the ilmenite-hematite solid-solution series. It is a wide-bandgap magnetic oxide semiconductor. Electrical resistivity and Seebeck coefficient measurements from room temperature to about 700°C confirm that it retains its p-type nature for the entire temperature range. The direct-current (DC) and alternating-current (AC) properties of these hybrid devices are discussed and their applications identified. It is shown here that such varistor embedded ceramic transistors with many interesting properties and applications can be mass produced using incredibly simple structures. The tuned varistors by themselves can be used for current amplification and band-pass filters. The transistors on the other hand could be used to produce sensors, voltage-controlled current sources, current-controlled voltage sources, signal amplifiers, and low-band-pass filters. We believe that these devices could be suitable for a number of applications in consumer and defense electronics, high-temperature and space electronics, bioelectronics, and possibly also for electronics specific to handheld devices.

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

A microprocessor based on a two-dimensional semiconductor.

PubMed

Wachter, Stefan; Polyushkin, Dmitry K; Bethge, Ole; Mueller, Thomas

2017-04-11

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor-molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

A microprocessor based on a two-dimensional semiconductor

NASA Astrophysics Data System (ADS)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

Analytic model for low-frequency noise in nanorod devices.

PubMed

Lee, Jungil; Yu, Byung Yong; Han, Ilki; Choi, Kyoung Jin; Ghibaudo, Gerard

2008-10-01

In this work analytic model for generation of excess low-frequency noise in nanorod devices such as field-effect transistors are developed. In back-gate field-effect transistors where most of the surface area of the nanorod is exposed to the ambient, the surface states could be the major noise source via random walk of electrons for the low-frequency or 1/f noise. In dual gate transistors, the interface states and oxide traps can compete with each other as the main noise source via random walk and tunneling, respectively.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Johnson, R. Wayne; Askew, Ray; Bromstead, James; Weir, Bennett

1991-01-01

The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter.

Large scale integration of graphene transistors for potential applications in the back end of the line

NASA Astrophysics Data System (ADS)

Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

2015-06-01

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

PubMed Central

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

Pass-transistor very large scale integration

NASA Technical Reports Server (NTRS)

Maki, Gary K. (Inventor); Bhatia, Prakash R. (Inventor)

2004-01-01

Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements.

ZrO2 Layer Thickness Dependent Electrical and Dielectric Properties of BST/ZrO2/BST Multilayer Thin Films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sahoo, S. K.; Misra, D.; Agrawal, D. C.

2011-01-01

Recently, high K materials play an important role in microelectronic devices such as capacitors, memory devices, and microwave devices. Now a days ferroelectric barium strontium titanate [Ba{sub x}Sr{sub 1-x}TiO{sub 3}, (BST)] thin film is being actively investigated for applications in dynamic random access memories (DRAM), field effect transistor (FET), and tunable devices because of its properties such as high dielectric constant, low leakage current, low dielectric loss, and high dielectric breakdown strength. Several approaches have been used to optimize the dielectric and electrical properties of BST thin films such as doping, graded compositions, and multilayer structures. We have found thatmore » inserting a ZrO{sub 2} layer in between two BST layers results in a significant reduction in dielectric constant, loss tangent, and leakage current in the multilayer thin films. Also it is shown that the properties of multilayer structure are found to depend strongly on the sublayer thicknesses. In this work the effect of ZrO{sub 2} layer thickness on the dielectric, ferroelectric as well as electrical properties of BST/ZrO{sub 2}/BST multilayer structure is studied. The multilayer Ba{sub 0.8}Sr{sub 0.2}TiO{sub 3}/ZrO{sub 2}/Ba{sub 0.8}Sr{sub 0.2}TiO{sub 3} film is deposited by a sol-gel process on the platinized Si substrate. The thickness of the middle ZrO{sub 2} layer is varied while keeping the top and bottom BST layer thickness as fixed. It is observed that the dielectric constant, dielectric loss tangent, and leakage current of the multilayer films reduce with the increase of ZrO{sub 2} layer thickness and hence suitable for memory device applications. The ferroelectric properties of the multilayer film also decrease with the ZrO{sub 2} layer thickness.« less

Assessment of Phospohrene Field Effect Transistors

DTIC Science & Technology

2018-01-28

electronics industry. To this end, transistor test structures would initially be fabricated on phosphorene exfoliated from black phosphorus and, later, on...34Phosphorene FETs-Promising Transistors Based on a few Layers of Phosphorus Atoms," Nanjing Electronic Devices Institute, Nanjing, China, Jul. 2015...OH, Nov. 2015. J.C. M. Hwang, "Phosphorene Transistors-Transient or Lasting Electronics ?" Workshop Frontier Electronics , San Juan, PR, Dec. 2015

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

PRESSURE TRANSDUCER

DOEpatents

Sander, H.H.

1959-10-01

A pressure or mechanical force transducer particularly adaptable to miniature telemetering systems is described. Basically the device consists of a transistor located within a magnetic field adapted to change in response to mechanical force. The conduction characteristics of the transistor in turn vary proportionally with changes in the magnetic flux across the transistor such that the output (either frequency of amplitude) of the transistor circuit is proportional to mechanical force or pressure.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

Splash, pop, sizzle: Information processing with phononic computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sklan, Sophia R.

2015-05-15

Phonons, the quanta of mechanical vibration, are important to the transport of heat and sound in solid materials. Recent advances in the fundamental control of phonons (phononics) have brought into prominence the potential role of phonons in information processing. In this review, the many directions of realizing phononic computing and information processing are examined. Given the relative similarity of vibrational transport at different length scales, the related fields of acoustic, phononic, and thermal information processing are all included, as are quantum and classical computer implementations. Connections are made between the fundamental questions in phonon transport and phononic control and themore » device level approach to diodes, transistors, memory, and logic. .« less

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

NASA Technical Reports Server (NTRS)

White, Mark; Huang, Bing; Qin, Jin; Gur, Zvi; Talmor, Michael; Chen, Yuan; Heidecker, Jason; Nguyen, Duc; Bernstein, Joseph

2005-01-01

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

Double quantum dot memristor

NASA Astrophysics Data System (ADS)

Li, Ying; Holloway, Gregory W.; Benjamin, Simon C.; Briggs, G. Andrew D.; Baugh, Jonathan; Mol, Jan A.

2017-08-01

Memristive systems are generalizations of memristors, which are resistors with memory. In this paper, we present a quantum description of quantum dot memristive systems. Using this model we propose and experimentally demonstrate a simple and practical scheme for realizing memristive systems with quantum dots. The approach harnesses a phenomenon that is commonly seen as a bane of nanoelectronics, i.e., switching of a trapped charge in the vicinity of the device. We show that quantum dot memristive systems have hysteresis current-voltage characteristics and quantum jump-induced stochastic behavior. While our experiment requires low temperatures, the same setup could, in principle, be realized with a suitable single-molecule transistor and operated at or near room temperature.

Quantum Devices and Structures Using Si-Based Molecular Beam Epitaxy

DTIC Science & Technology

1991-05-15

the MBE growth studies of Sii_..,Ge./Si superlattices and the fabrication of resonant tunneling devices. 1 In the following we highlight the...relaxation was obtained.[7] A new approach in growth of strained layers on a patterned substrate was implemented. Permeable transistors and tunneling ...Fig. 5(b) shows a hot hole transistor using a superlattice base and resonant tunneling injector. In order to facilitate the design of such devices

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

Dramatic switching behavior in suspended MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Chen, Huawei; Li, Jingyu; Chen, Xiaozhang; Zhang, David; Zhou, Peng

2018-02-01

When integrating MoS2 flakes into scaling-down transistors, the short-channel effect, which is severe in silicon technology below 5-nanometer, can be avoided effectively. MoS2 transistors not only exhibit a high on/off ratio but also demonstrate a rapid switching speed. According to the theoretical calculation, the thermionic limit subthreshold slope (SS) of the ideal device could reach 60 mV/dec. However, due to the confinement of defects from substrates or contamination during the process, the SS deteriorates to more than 300 mV/dec, causing serious power consumption. In this work, we optimize the SS through structure design of MoS2 transistors. The suspended transistors exhibit a high on/off ratio of 107 and a minimum SS of 63 mV/dec with an ultralow standby power at room temperature. This study demonstrates the promising potential of structure design for electronic devices with ultralow-power switching behaviors.

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

PubMed

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Polymer-based doping control for performance enhancement of wet-processed short-channel CNTFETs

NASA Astrophysics Data System (ADS)

Hartmann, Martin; Schubel, René; Claus, Martin; Jordan, Rainer; Schulz, Stefan E.; Hermann, Sascha

2018-01-01

The electrical transport properties of short-channel transistors based on single-walled carbon nanotubes (CNT) are significantly affected by bundling along with solution processing. We report that especially high off currents of CNT transistors are not only related to the incorporation of metallic CNTs but also to the incorporation of CNT bundles. By applying device passivation with poly(4-vinylpyridine), the impact of CNT bundling on the device performance can be strongly reduced due to increased gate efficiency as well as reduced oxygen and water-induced p-type doping, boosting essential field-effect transistor performance parameters by several orders of magnitude. Moreover, this passivation approach allows the hysteresis and threshold voltage of CNT transistors to be tuned.

Electrochemical doping for lowering contact barriers in organic field effect transistors

PubMed Central

Schaur, Stefan; Stadler, Philipp; Meana-Esteban, Beatriz; Neugebauer, Helmut; Serdar Sariciftci, N.

2012-01-01

By electrochemically p-doping pentacene in the vicinity of the source-drain electrodes in organic field effect transistors the injection barrier for holes is decreased. The focus of this work is put on the influence of the p-doping process on the transistor performance. Cyclic voltammetry performed on a pentacene based transistor exhibits a reversible p-doping response. This doped state is evoked at the transistor injection electrodes. An improvement is observed when comparing transistor characteristics before and after the doping process apparent by an improved transistor on-current. This effect is reflected in the analysis of the contact resistances of the devices. PMID:23483101

Fully-printed high-performance organic thin-film transistors and circuitry on one-micron-thick polymer films

NASA Astrophysics Data System (ADS)

Fukuda, Kenjiro; Takeda, Yasunori; Yoshimura, Yudai; Shiwaku, Rei; Tran, Lam Truc; Sekine, Tomohito; Mizukami, Makoto; Kumaki, Daisuke; Tokito, Shizuo

2014-06-01

Thin, ultra-flexible devices that can be manufactured in a process that covers a large area will be essential to realizing low-cost, wearable electronic applications including foldable displays and medical sensors. The printing technology will be instrumental in fabricating these novel electronic devices and circuits; however, attaining fully printed devices on ultra-flexible films in large areas has typically been a challenge. Here we report on fully printed organic thin-film transistor devices and circuits fabricated on 1-μm-thick parylene-C films with high field-effect mobility (1.0 cm2 V-1 s-1) and fast operating speeds (about 1 ms) at low operating voltages. The devices were extremely light (2 g m-2) and exhibited excellent mechanical stability. The devices remained operational even under 50% compressive strain without significant changes in their performance. These results represent significant progress in the fabrication of fully printed organic thin-film transistor devices and circuits for use in unobtrusive electronic applications such as wearable sensors.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

PubMed Central

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Thermal Simulation of a Silicon Carbide (SiC) Insulated-Gate Bipolar Transistor (IGBT) in Continuous Switching Mode

DTIC Science & Technology

operation in a DC-DC power converter switching at a frequency of up to 15 kHz. Calculations also estimated the effect of solder layers on temperature in the device....Thermal simulations were used to calculate temperatures in a silicon carbide (SiC) Insulated -Gate Bipolar Transistor (IGBT),simulating device

Front and backside processed thin film electronic devices

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Recent progress in high-mobility thin-film transistors based on multilayer 2D materials

NASA Astrophysics Data System (ADS)

Hong, Young Ki; Liu, Na; Yin, Demin; Hong, Seongin; Kim, Dong Hak; Kim, Sunkook; Choi, Woong; Yoon, Youngki

2017-04-01

Two-dimensional (2D) layered semiconductors are emerging as promising candidates for next-generation thin-film electronics because of their high mobility, relatively large bandgap, low-power switching, and the availability of large-area growth methods. Thin-film transistors (TFTs) based on multilayer transition metal dichalcogenides or black phosphorus offer unique opportunities for next-generation electronic and optoelectronic devices. Here, we review recent progress in high-mobility transistors based on multilayer 2D semiconductors. We describe the theoretical background on characterizing methods of TFT performance and material properties, followed by their applications in flexible, transparent, and optoelectronic devices. Finally, we highlight some of the methods used in metal-semiconductor contacts, hybrid structures, heterostructures, and chemical doping to improve device performance.

Photon-triggered nanowire transistors

NASA Astrophysics Data System (ADS)

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J.; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 106. A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Material Synthesis and Device Aspects of Monolayer Tungsten Diselenide.

PubMed

Yao, Zihan; Liu, Jialun; Xu, Kai; Chow, Edmond K C; Zhu, Wenjuan

2018-03-27

In this paper, we investigate the synthesis of WSe 2 by chemical vapor deposition and study the current transport and device scaling of monolayer WSe 2 . We found that the device characteristics of the back-gated WSe 2 transistors with thick oxides are very sensitive to the applied drain bias, especially for transistors in the sub-micrometer regime. The threshold voltage, subthreshold swing, and extracted field-effect mobility vary with the applied drain bias. The output characteristics in the long-channel transistors show ohmic-like behavior, while that in the short-channel transistors show Schottky-like behavior. Our investigation reveals that these phenomena are caused by the drain-induced barrier lowering (short-channel effect). For back-gated WSe 2 transistors with 280 nm oxide, the short-channel effect appears when the channel length is shorter than 0.4 µm. This extremely long electrostatic scaling length is due to the thick back-gate oxides. In addition, we also found that the hydrogen flow rate and the amount of WO 3 precursor play an important role in the morphology of the WSe 2 . The hole mobility of the monolayer WSe 2 is limited by Columbic scattering below 250 K, while it is limited by phonon scattering above 250 K. These findings are very important for the synthesis of WSe 2 and accurate characterization of the electronic devices based on 2D materials.

Photon-triggered nanowire transistors.

PubMed

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 10 6 . A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Device Engineered Organic Transistors for Flexible Sensing Applications.

PubMed

Zang, Yaping; Huang, Dazhen; Di, Chong-An; Zhu, Daoben

2016-06-01

Organic thin-film transistors (OFETs) represent a promising candidate for next-generation sensing applications because of the intrinsic advantages of organic semiconductors. The development of flexible sensing devices has received particular interest in the past few years. The recent efforts of developing OFETs for sensitive and specific flexible sensors are summarized from the standpoint of device engineering. The tuning of signal transduction and signal amplification are highlighted based on an overview of active-layer thickness modulation, functional receptor implantation and device geometry optimization. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A pattern recognition approach to transistor array parameter variance

NASA Astrophysics Data System (ADS)

da F. Costa, Luciano; Silva, Filipi N.; Comin, Cesar H.

2018-06-01

The properties of semiconductor devices, including bipolar junction transistors (BJTs), are known to vary substantially in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters. All in all, this work yielded interesting results from both semiconductor engineering and pattern recognition perspectives.

A Novel SPM Probe with MOS Transistor and Nano Tip for Surface Electric Properties

NASA Astrophysics Data System (ADS)

Lee, Sang H.; Lim, Geunbae; Moon, Wonkyu

2007-03-01

In this paper, the novel SPM (Scanning Probe Microscope) probe with the planar MOS (Metal-Oxide-Semiconductor) transistor and the FIB (Focused Ion Beam) nano tip is fabricated for the surface electric properties. Since the MOS transistor has high working frequency, the device can overcome the speed limitation of EFM (Electrostatic Force Microscope) system. The sensitivity is also high, and no bulky device such as lock-in-amplifier is required. Moreover, the nano tip with nanometer scale tip radius is fabricated with FIB system, and the resolution can be improved. Therefore, the probe can rapidly detect small localized electric properties with high sensitivity and high resolution. The MOS transistor is fabricated with the common semiconductor process, and the nano tip is grown by the FIB system. The planar structure of the MOS transistor makes the fabrication process easier, which is the advantage on the commercial production. Various electric signals are applied using the function generator, and the measured data represent the well-established electric properties of the device. It shows the promising aspect of the local surface electric property detection with high sensitivity and high resolution.

Photosensitive graphene transistors.

PubMed

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

p-Type Transparent Electronics

DTIC Science & Technology

2003-09-25

thin - film transistors (TTFTs) reported to date in the literature are summarized. 2.2.1 Thin - Film Transistor Structure and Fabrication A TFT ...is incapable of controlling the TFT regardless of gate voltage, as described in Sec. 2.2.3.1. 2.2.4 Transparent Thin - Film Transistors (TTFTs...Transparent thin - film transistors (TTFTs) described in the literature to date are all n-channel devices. Several n-channel TTFTs (n-TTFTs) based on

Theory and Device Modeling for Nano-Structured Transistor Channels

DTIC Science & Technology

2011-06-01

zinc oxide ( ZnO ) thin film transistors ( TFTs ) that contain nanocrystalline grains on the order of ~20nm. The authors of ref. 1 present results...problem in order to determine the threshold voltage. 15. SUBJECT TERMS nano-structured transistor , mesoscopic, zinc oxide , ZnO , field-effect...and R. Neidhard, “Microwave ZnO Thin - Film Transistors ”, IEEE Electron Dev. Lett. 29, 1024 (2008); doi: 10.1109/LED.2008.2001635.

Current crowding mediated large contact noise in graphene field-effect transistors

PubMed Central

Karnatak, Paritosh; Sai, T. Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

2016-01-01

The impact of the intrinsic time-dependent fluctuations in the electrical resistance at the graphene–metal interface or the contact noise, on the performance of graphene field-effect transistors, can be as adverse as the contact resistance itself, but remains largely unexplored. Here we have investigated the contact noise in graphene field-effect transistors of varying device geometry and contact configuration, with carrier mobility ranging from 5,000 to 80,000 cm2 V−1 s−1. Our phenomenological model for contact noise because of current crowding in purely two-dimensional conductors confirms that the contacts dominate the measured resistance noise in all graphene field-effect transistors in the two-probe or invasive four-probe configurations, and surprisingly, also in nearly noninvasive four-probe (Hall bar) configuration in the high-mobility devices. The microscopic origin of contact noise is directly linked to the fluctuating electrostatic environment of the metal–channel interface, which could be generic to two-dimensional material-based electronic devices. PMID:27929087

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Mobility overestimation due to gated contacts in organic field-effect transistors

PubMed Central

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Current crowding mediated large contact noise in graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Karnatak, Paritosh; Sai, T. Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

2016-12-01

The impact of the intrinsic time-dependent fluctuations in the electrical resistance at the graphene-metal interface or the contact noise, on the performance of graphene field-effect transistors, can be as adverse as the contact resistance itself, but remains largely unexplored. Here we have investigated the contact noise in graphene field-effect transistors of varying device geometry and contact configuration, with carrier mobility ranging from 5,000 to 80,000 cm2 V-1 s-1. Our phenomenological model for contact noise because of current crowding in purely two-dimensional conductors confirms that the contacts dominate the measured resistance noise in all graphene field-effect transistors in the two-probe or invasive four-probe configurations, and surprisingly, also in nearly noninvasive four-probe (Hall bar) configuration in the high-mobility devices. The microscopic origin of contact noise is directly linked to the fluctuating electrostatic environment of the metal-channel interface, which could be generic to two-dimensional material-based electronic devices.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array.

PubMed

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B-H; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable-like human skin-would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a general platform for incorporating other intrinsically stretchable polymer materials, enabling the fabrication of next-generation stretchable skin electronic devices.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array

NASA Astrophysics Data System (ADS)

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R.; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M.; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B.-H.; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable—like human skin—would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a general platform for incorporating other intrinsically stretchable polymer materials, enabling the fabrication of next-generation stretchable skin electronic devices.

Modified Reference SPS with Solid State Transmitting Antenna

NASA Technical Reports Server (NTRS)

Woodcock, G. R.; Sperber, B. R.

1980-01-01

The development of solid state microwave power amplifiers for a solar power satellite transmitting antenna is discussed. State-of-the-art power-added efficiency, gain, and single device power of various microwave solid state devices are compared. The GaAs field effect transistors and the Si-bipolar transistors appear potentially feasible for solar power satellite use. The integration of solid state devices into antenna array elements is examined and issues concerning antenna integration and consequent satellite configurations are examined.

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

PubMed

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

PubMed

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

Transcap: A new integrated hybrid supercapacitor and electrolyte-gated transistor device (Presentation Recording)

NASA Astrophysics Data System (ADS)

Santato, Clara

2015-10-01

The boom in multifunctional, flexible, and portable electronics and the increasing need of low-energy cost and autonomy for applications ranging from wireless sensor networks for smart environments to biomedical applications are triggering research efforts towards the development of self-powered sustainable electronic devices. Within this context, the coupling of electronic devices (e.g. sensors, transistors) with small size energy storage systems (e.g. micro-batteries or micro-supercapacitors) is actively pursued. Micro-electrochemical supercapacitors are attracting much attention in electronics for their capability of delivering short power pulses with high stability over repeated charge/discharge cycling. For their high specific pseudocapacitance, electronically conducting polymers are well known as positive materials for hybrid supercapacitors featuring high surface carbon negative electrodes. The processability of both polymer and carbon is of great relevance for the development of flexible miniaturised devices. Electronically conducting polymers are even well known to feature an electronic conductivity that depends on their oxidation (p-doped state) and that it is modulated by the polymer potential. This property and the related pseudocapacitive response make polymer very attracting channel materials for electrolyte-gated (EG) transistors. Here, we propose a novel concept of "Trans-capacitor", an integrated device that exhibits the storage properties of a polymer/carbon hybrid supercapacitor and the low-voltage operation of an electrolyte-gated transistor.

Final report for CCS cross-layer reliability visioning study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Dehon, Andre; Carter, Nicj

The geometric rate of improvement of transistor size and integrated circuit performance known as Moore's Law has been an engine of growth for our economy, enabling new products and services, creating new value and wealth, increasing safety, and removing menial tasks from our daily lives. Affordable, highly integrated components have enabled both life-saving technologies and rich entertainment applications. Anti-lock brakes, insulin monitors, and GPS-enabled emergency response systems save lives. Cell phones, internet appliances, virtual worlds, realistic video games, and mp3 players enrich our lives and connect us together. Over the past 40 years of silicon scaling, the increasing capabilities ofmore » inexpensive computation have transformed our society through automation and ubiquitous communications. Looking forward, increasing unpredictability threatens our ability to continue scaling integrated circuits at Moore's Law rates. As the transistors and wires that make up integrated circuits become smaller, they display both greater differences in behavior among devices designed to be identical and greater vulnerability to transient and permanent faults. Conventional design techniques expend energy to tolerate this unpredictability by adding safety margins to a circuit's operating voltage, clock frequency or charge stored per bit. However, the rising energy costs needed to compensate for increasing unpredictability are rapidly becoming unacceptable in today's environment where power consumption is often the limiting factor on integrated circuit performance and energy efficiency is a national concern. Reliability and energy consumption are both reaching key inflection points that, together, threaten to reduce or end the benefits of feature size reduction. To continue beneficial scaling, we must use a cross-layer, Jull-system-design approach to reliability. Unlike current systems, which charge every device a substantial energy tax in order to guarantee correct operation in spite of rare events, such as one high-threshold transistor in a billion or one erroneous gate evaluation in an hour of computation, cross-layer reliability schemes make reliability management a cooperative effort across the system stack, sharing information across layers so that they only expend energy on reliability when an error actually occurs. Figure 1 illustrates an example of such a system that uses a combination of information from the application and cheap architecture-level techniques to detect errors. When an error occurs, mechanisms at higher levels in the stack correct the error, efficiently delivering correct operation to the user in spite of errors at the device or circuit levels. In the realms of memory and communication, engineers have a long history of success in tolerating unpredictable effects such as fabrication variability, transient upsets, and lifetime wear using information sharing, limited redundancy, and cross-layer approaches that anticipate, accommodate, and suppress errors. Networks use a combination of hardware and software to guarantee end-toend correctness. Error-detection and correction codes use additional information to correct the most common errors, single-bit transmission errors. When errors occur that cannot be corrected by these codes, the network protocol requests re-transmission of one or more packets until the correct data is received. Similarly, computer memory systems exploit a cross-layer division of labor to achieve high performance with modest hardware. Rather than demanding that hardware alone provide the virtual memory abstraction, software page-fault and TLB-miss handlers allow a modest piece of hardware, the TLB, to handle the common-case operations on a cyc1e-by-cycle basis while infrequent misses are handled in system software. Unfortunately, mitigating logic errors is not as simple or as well researched as memory or communication systems. This lack of understanding has led to very expensive solutions. For example, triple-modular redundancy masks errors by triplicating computations in either time or area. This mitigation methods imposes a 200% increase in energy consumption for every operation, not just the uncommon failure cases. At a time when computation is rapidly becoming part of our critical civilian and military infrastructure and decreasing costsfor computation are fueling our economy and our well being, we cannot afford increasingly unreliable electronics or a stagnation in capabilities per dollar, watt, or cubic meter. If researchers are able to develop techniques that tolerate the growing unpredictability of silicon devices, Moore's Law scaling should continue until at least 2022. During this 12-year time period, transistors, which are the building blocks of electronic devices, will scale their dimensions (feature sizes) from 45nm to 4.5nm.« less

Material Engineering for Phase Change Memory

NASA Astrophysics Data System (ADS)

Cabrera, David M.

As semiconductor devices continue to scale downward, and portable consumer electronics become more prevalent there is a need to develop memory technology that will scale with devices and use less energy, while maintaining performance. One of the leading prototypical memories that is being investigated is phase change memory. Phase change memory (PCM) is a non-volatile memory composed of 1 transistor and 1 resistor. The resistive structure includes a memory material alloy which can change between amorphous and crystalline states repeatedly using current/voltage pulses of different lengths and magnitudes. The most widely studied PCM materials are chalcogenides - Germanium-Antimony-Tellerium (GST) with Ge2Sb2Te3 and Germanium-Tellerium (GeTe) being some of the most popular stochiometries. As these cells are scaled downward, the current/voltage needed to switch these materials becomes comparable to the voltage needed to sense the cell's state. The International Roadmap for Semiconductors aims to raise the threshold field of these devices from 66.6 V/mum to be at least 375 V/mum for the year 2024. These cells are also prone to resistance drift between states, leading to bit corruption and memory loss. Phase change material properties are known to influence PCM device performance such as crystallization temperature having an effect on data retention and litetime, while resistivity values in the amorphous and crystalline phases have an effect on the current/voltage needed to write/erase the cell. Addition of dopants is also known to modify the phase change material parameters. The materials G2S2T5, GeTe, with dopants - nitrogen, silicon, titanium, and aluminum oxide and undoped Gallium-Antimonide (GaSb) are studied for these desired characteristics. Thin films of these compositions are deposited via physical vapor deposition at IBM Watson Research Center. Crystallization temperatures are investigated using time resolved x-ray diffraction at Brookhaven National Laboratory. Subsequently, these are incorporated into PCM cells with structure designed as shown in Fig.1. A photolithographic lift-off process is developed to realize these devices. Electrical parameters such as the voltage needed to switch the device between memory states, the difference in resistance between these memory states, and the amount of time to switch are studied using HP4145 equipped with a pulsed generator. The results show that incorporating aluminum oxide dopant into G2S2T 5 raises its threshold field from 60 V/mum to 96 V/mum, while for GeTe, nitrogen doping raises its threshold field from 143 V/mum to 248 V/mum. It is found that GaSb at comparable volume devices has a threshold field of 130 V/mum. It was also observed that nitrogen and silicon doping made G 2S2T5 more resistant to drift, raising time to drift from 2 to 16.6 minutes while titanium and aluminum oxide doping made GeTe drift time rise from 3 to 20 minutes. It was also found that shrinking the cell area in GaSb from 1 mum2 to 0.5 mum2 lengthened drift time from 45s to over 24 hours. The PCM process developed in this study is extended to GeTe/Sb2 Te3 multilayers called the superlattice (SL) structure that opens opportunities for future work. Recent studies have shown that the superlattice structure exhibits low switching energies, therefore has potential for low power operation.

Effects of Various Passivation Layers on Electrical Properties of Multilayer MoS₂ Transistors.

PubMed

Ma, Jiyeon; Yoo, Geonwook

2018-09-01

So far many of research on transition metal dichalcogenides (TMDCs) are based on a bottomgate device structure due to difficulty with depositing a dielectric film on top of TMDs channel layer. In this work, we study different effects of various passivation layers on electrical properties of multilayer MoS2 transistors: spin-coated CYTOP, SU-8, and thermal evaporated MoOX. The SU-8 passivation layer alters device performance least significantly, and MoOX induces positive threshold voltage shift of ~8.0 V due to charge depletion at the interface, and the device with CYTOP layer exhibits decreased field-effect mobility by ~50% due to electric dipole field effect of C-F bonds in the end groups. Our results imply that electrical properties of the multilayer MoS2 transistors can be modulated using a passivation layer, and therefore a proper passivation layer should be considered for MoS2 device structures.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

PubMed

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

Recent progress on fabrication of memristor and transistor-based neuromorphic devices for high signal processing speed with low power consumption

NASA Astrophysics Data System (ADS)

Hadiyawarman; Budiman, Faisal; Goldianto Octensi Hernowo, Detiza; Pandey, Reetu Raj; Tanaka, Hirofumi

2018-03-01

The advanced progress of electronic-based devices for artificial neural networks and recent trends in neuromorphic engineering are discussed in this review. Recent studies indicate that the memristor and transistor are two types of devices that can be implemented as neuromorphic devices. The electrical switching characteristics and physical mechanism of neuromorphic devices based on metal oxide, metal sulfide, silicon, and carbon materials are broadly covered in this review. Moreover, the switching performance comparison of several materials mentioned above are well highlighted, which would be useful for the further development of memristive devices. Recent progress in synaptic devices and the application of a switching device in the learning process is also discussed in this paper.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

NASA Astrophysics Data System (ADS)

Lee, Sungsik; Nathan, Arokia

2016-10-01

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

Chemical free device fabrication of two dimensional van der Waals materials based transistors by using one-off stamping

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Young Tack, E-mail: 023273@kist.re.kr, E-mail: stunalren@gmail.com; Choi, Won Kook; Materials and Life Science Research Division, Korea Institute of Science and Technology

We report on a chemical free one-off imprinting method to fabricate two dimensional (2D) van der Waals (vdWs) materials based transistors. Such one-off imprinting technique is the simplest and effective way to prevent unintentional chemical reaction or damage of 2D vdWs active channel during device fabrication process. 2D MoS{sub 2} nanosheets based transistors with a hexagonal-boron-nitride (h-BN) passivation layer, prepared by one-off imprinting, show negligible variations of transfer characteristics after chemical vapor deposition process. In addition, this method enables the fabrication of all 2D MoS{sub 2} transistors consisting of h-BN gate insulator, and graphene source/drain and gate electrodes without anymore » chemical damage.« less

Thermal-noise suppression in nano-scale Si field-effect transistors by feedback control based on single-electron detection

NASA Astrophysics Data System (ADS)

Chida, Kensaku; Nishiguchi, Katsuhiko; Yamahata, Gento; Tanaka, Hirotaka; Fujiwara, Akira

2015-08-01

We perform feedback (FB) control for suppressing thermal fluctuation in the number of electrons in a silicon single-electron (SE) device composed of a small transistor and capacitor. SEs enter and leave the capacitor via the transistor randomly at thermal equilibrium, which is monitored in real time using a high-charge-sensitivity detector. In order to suppress such random motion or thermal fluctuation of the electrons, SEs are injected and removed using the transistor according to the monitored change in the number of electrons in the capacitor, which is exactly the FB control. As a result, thermal fluctuation in the number of electrons in a SE device is suppressed by 60%, which corresponds to the so-called FB cooling from 300 to 110 K. Moreover, a thermodynamics analysis of this FB cooling reveals that entropy in the capacitor is reduced and the device is at non-equilibrium; i.e., the free energy of the device increases. Since this entropy reduction originates from information about the electrons' motion monitored by the detector, our results by the FB control represent one type of information-to-energy conversion.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

NASA Astrophysics Data System (ADS)

Shauly, Eitan N.; Levi, Shimon; Schwarzband, Ishai; Adan, Ofer; Latinsky, Sergey

2015-04-01

A fully automated silicon-based methodology for systematic analysis of electrical features is shown. The system was developed for process monitoring and electrical variability reduction. A mapping step was created by dedicated structures such as static-random-access-memory (SRAM) array or standard cell library, or by using a simple design rule checking run-set. The resulting database was then used as an input for choosing locations for critical dimension scanning electron microscope images and for specific layout parameter extraction then was input to SPICE compact modeling simulation. Based on the experimental data, we identified two items that must be checked and monitored using the method described here: transistor's sensitivity to the distance between the poly end cap and edge of active area (AA) due to AA rounding, and SRAM leakage due to a too close N-well to P-well. Based on this example, for process monitoring and variability analyses, we extensively used this method to analyze transistor gates having different shapes. In addition, analysis for a large area of high density standard cell library was done. Another set of monitoring focused on a high density SRAM array is also presented. These examples provided information on the poly and AA layers, using transistor parameters such as leakage current and drive current. We successfully define "robust" and "less-robust" transistor configurations included in the library and identified unsymmetrical transistors in the SRAM bit-cells. These data were compared to data extracted from the same devices at the end of the line. Another set of analyses was done to samples after Cu M1 etch. Process monitoring information on M1 enclosed contact was extracted based on contact resistance as a feedback. Guidelines for the optimal M1 space for different layout configurations were also extracted. All these data showed the successful in-field implementation of our methodology as a useful process monitoring method.

GaN transistors on Si for switching and high-frequency applications

NASA Astrophysics Data System (ADS)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Quantum Device Applications of Mesoscopic Superconductivity

NASA Astrophysics Data System (ADS)

Hakonen, P. J.

2006-08-01

A brief account is given on the possibilities of mesoscopic superconductivity in low-noise amplifier and detector applications. In particular, three devices will be described: 1) Bloch oscillating transistor (BOT), 2) Inductively-read superconducting Cooper pair transistor (L-SET), and 3) Quantum capacitive phase detector (C-SET). The BOT is a low-noise current amplifier while the L-SET and C-SET act as ultra-sensitive charge and phase detectors, respectively. The basic operating principles and the main characteristics of these devices will be reviewed and discussed.

Flexible thin-film transistors on plastic substrate at room temperature.

PubMed

Han, Dedong; Wang, Wei; Cai, Jian; Wang, Liangliang; Ren, Yicheng; Wang, Yi; Zhang, Shengdong

2013-07-01

We have fabricated flexible thin-film transistors (TFTs) on plastic substrates using Aluminum-doped ZnO (AZO) as an active channel layer at room temperature. The AZO-TFTs showed n-channel device characteristics and operated in enhancement mode. The device shows a threshold voltage of 1.3 V, an on/off ratio of 2.7 x 10(7), a field effect mobility of 21.3 cm2/V x s, a subthreshold swing of 0.23 V/decade, and the off current of less than 10(-12) A at room temperature. Recently, the flexible displays have become a very hot topic. Flexible thin film transistors are key devices for realizing flexible displays. We have investigated AZO-TFT on flexible plastic substrate, and high performance flexible TFTs have been obtained.

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Hu, Zhaoying; Tulevski, George S.; Hannon, James B.; Afzali, Ali; Liehr, Michael; Park, Hongsik

2015-06-01

Carbon nanotubes (CNTs) have been widely studied as a channel material of scaled transistors for high-speed and low-power logic applications. In order to have sufficient drive current, it is widely assumed that CNT-based logic devices will have multiple CNTs in each channel. Understanding the effects of the number of CNTs on device performance can aid in the design of CNT field-effect transistors (CNTFETs). We have fabricated multi-CNT-channel CNTFETs with an 80-nm channel length using precise self-assembly methods. We describe compact statistical models and Monte Carlo simulations to analyze failure probability and the variability of the on-state current and threshold voltage. The results show that multichannel CNTFETs are more resilient to process variation and random environmental fluctuations than single-CNT devices.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

In vivo recordings of brain activity using organic transistors

PubMed Central

Khodagholy, Dion; Doublet, Thomas; Quilichini, Pascale; Gurfinkel, Moshe; Leleux, Pierre; Ghestem, Antoine; Ismailova, Esma; Hervé, Thierry; Sanaur, Sébastien; Bernard, Christophe; Malliaras, George G.

2013-01-01

In vivo electrophysiological recordings of neuronal circuits are necessary for diagnostic purposes and for brain-machine interfaces. Organic electronic devices constitute a promising candidate because of their mechanical flexibility and biocompatibility. Here we demonstrate the engineering of an organic electrochemical transistor embedded in an ultrathin organic film designed to record electrophysiological signals on the surface of the brain. The device, tested in vivo on epileptiform discharges, displayed superior signal-to-noise ratio due to local amplification compared with surface electrodes. The organic transistor was able to record on the surface low-amplitude brain activities, which were poorly resolved with surface electrodes. This study introduces a new class of biocompatible, highly flexible devices for recording brain activity with superior signal-to-noise ratio that hold great promise for medical applications. PMID:23481383

In vivo recordings of brain activity using organic transistors.

PubMed

Khodagholy, Dion; Doublet, Thomas; Quilichini, Pascale; Gurfinkel, Moshe; Leleux, Pierre; Ghestem, Antoine; Ismailova, Esma; Hervé, Thierry; Sanaur, Sébastien; Bernard, Christophe; Malliaras, George G

2013-01-01

In vivo electrophysiological recordings of neuronal circuits are necessary for diagnostic purposes and for brain-machine interfaces. Organic electronic devices constitute a promising candidate because of their mechanical flexibility and biocompatibility. Here we demonstrate the engineering of an organic electrochemical transistor embedded in an ultrathin organic film designed to record electrophysiological signals on the surface of the brain. The device, tested in vivo on epileptiform discharges, displayed superior signal-to-noise ratio due to local amplification compared with surface electrodes. The organic transistor was able to record on the surface low-amplitude brain activities, which were poorly resolved with surface electrodes. This study introduces a new class of biocompatible, highly flexible devices for recording brain activity with superior signal-to-noise ratio that hold great promise for medical applications.

Fabrication and characterization of active nanostructures

NASA Astrophysics Data System (ADS)

Opondo, Noah F.

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface. A micro-vacuum electron device based on silicon field emitters for cold cathode emission is also presented. The presented work utilizes vertical Si nanowires fabricated by means of self-assembly, standard lithography and etching techniques as field emitters in this dissertation. To obtain a high nanowire density, hence a high current density, a simple and inexpensive Langmuir Blodgett technique to deposit silica nanoparticles as a mask to etch Si is adopted. Fabrication and characterization of a metal-gated microtriode with a high current density and low operating voltage are presented.

Fabricating photoswitches and field-effect transistors from self-assembled tetra(2-isopropyl-5-methyphenoxy) copper phthalocyanines nanowires.

PubMed

Cheng, Chuanwei; Gao, Junshan; Xu, Guoyue; Zhang, Haiqian; Li, Yingying; Luo, Yan

2009-05-01

Tetra(2-isopropyl-5-methyphenoxy) copper phthalocyanine (CuPc) nanowires synthesized by a facile, low temperature self-assembled route, were incorporated into nano-devices: photoswitch and organic field-effect transistor. The devices were capable of switching on/off reversibly and fast by turning the 808 nm infrared light on/off. And the carrier mobility micro of CuPc nanowires incorporated in the devices was -0.02 cm2/V x s. The prelimenary results in this study show the potential application of metal phthalocyanine nanowires in low-cost fabrication of nano photo-electric devices.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Intrinsically stretchable and transparent thin-film transistors based on printable silver nanowires, carbon nanotubes and an elastomeric dielectric

PubMed Central

Liang, Jiajie; Li, Lu; Chen, Dustin; Hajagos, Tibor; Ren, Zhi; Chou, Shu-Yu; Hu, Wei; Pei, Qibing

2015-01-01

Thin-film field-effect transistor is a fundamental component behind various mordern electronics. The development of stretchable electronics poses fundamental challenges in developing new electronic materials for stretchable thin-film transistors that are mechanically compliant and solution processable. Here we report the fabrication of transparent thin-film transistors that behave like an elastomer film. The entire fabrication is carried out by solution-based techniques, and the resulting devices exhibit a mobility of ∼30 cm2 V−1 s−1, on/off ratio of 103–104, switching current >100 μA, transconductance >50 μS and relative low operating voltages. The devices can be stretched by up to 50% strain and subjected to 500 cycles of repeated stretching to 20% strain without significant loss in electrical property. The thin-film transistors are also used to drive organic light-emitting diodes. The approach and results represent an important progress toward the development of stretchable active-matrix displays. PMID:26173436

Transport spectroscopy of coupled donors in silicon nano-transistors

PubMed Central

Moraru, Daniel; Samanta, Arup; Anh, Le The; Mizuno, Takeshi; Mizuta, Hiroshi; Tabe, Michiharu

2014-01-01

The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed: dopant-atom-based transistors. So far, most studies report transport through dopants randomly located in the channel. However, for practical applications, it is critical to control the location of the donors with simple techniques. Here, we fabricate silicon transistors with selectively nanoscale-doped channels using nano-lithography and thermal-diffusion doping processes. Coupled phosphorus donors form a quantum dot with the ground state split into a number of levels practically equal to the number of coupled donors, when the number of donors is small. Tunneling-transport spectroscopy reveals fine features which can be correlated with the different numbers of donors inside the quantum dot, as also suggested by first-principles simulation results. PMID:25164032

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

PULSE COUNTER

DOEpatents

Trumbo, D.E.

1959-02-10

A transistorized pulse-counting circuit adapted for use with nuclear radiation detecting detecting devices to provide a small, light weight portable counter is reported. The small size and low power requirements of the transistor are of particular value in this instance. The circuit provides an adjustable count scale with a single transistor which is triggered by the accumulated charge on a storage capacitor.

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Nanoscale structural and chemical analysis of F-implanted enhancement-mode InAlN/GaN heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Tang, Fengzai; Lee, Kean B.; Guiney, Ivor; Frentrup, Martin; Barnard, Jonathan S.; Divitini, Giorgio; Zaidi, Zaffar H.; Martin, Tomas L.; Bagot, Paul A.; Moody, Michael P.; Humphreys, Colin J.; Houston, Peter A.; Oliver, Rachel A.; Wallis, David J.

2018-01-01

We investigate the impact of a fluorine plasma treatment used to obtain enhancement-mode operation on the structure and chemistry at the nanometer and atomic scales of an InAlN/GaN field effect transistor. The fluorine plasma treatment is successful in that enhancement mode operation is achieved with a +2.8 V threshold voltage. However, the InAlN barrier layers are observed to have been damaged by the fluorine treatment with their thickness being reduced by up to 50%. The treatment also led to oxygen incorporation within the InAlN barrier layers. Furthermore, even in the as-grown structure, Ga was unintentionally incorporated during the growth of the InAlN barrier. The impact of both the reduced barrier thickness and the incorporated Ga within the barrier on the transistor properties has been evaluated theoretically and compared to the experimentally determined two-dimensional electron gas density and threshold voltage of the transistor. For devices without fluorine treatment, the two-dimensional electron gas density is better predicted if the quaternary nature of the barrier is taken into account. For the fluorine treated device, not only the changes to the barrier layer thickness and composition, but also the fluorine doping needs to be considered to predict device performance. These studies reveal the factors influencing the performance of these specific transistor structures and highlight the strengths of the applied nanoscale characterisation techniques in revealing information relevant to device performance.

Near-Infrared to Visible Organic Upconversion Devices Based on Organic Light-Emitting Field Effect Transistors.

PubMed

Li, Dongwei; Hu, Yongsheng; Zhang, Nan; Lv, Ying; Lin, Jie; Guo, Xiaoyang; Fan, Yi; Luo, Jinsong; Liu, Xingyuan

2017-10-18

The near-infrared (NIR) to visible upconversion devices have attracted great attention because of their potential applications in the fields of night vision, medical imaging, and military security. Herein, a novel all-organic upconversion device architecture has been first proposed and developed by incorporating a NIR absorption layer between the carrier transport layer and the emission layer in heterostructured organic light-emitting field effect transistors (OLEFETs). The as-prepared devices show a typical photon-to-photon upconversion efficiency as high as 7% (maximum of 28.7% under low incident NIR power intensity) and millisecond-scale response time, which are the highest upconversion efficiency and one of the fastest response time among organic upconversion devices as referred to the previous reports up to now. The high upconversion performance mainly originates from the gain mechanism of field-effect transistor structures and the unique advantage of OLEFETs to balance between the photodetection and light emission. Meanwhile, the strategy of OLEFETs also offers the advantage of high integration so that no extra OLED is needed in the organic upconversion devices. The results would pave way for low-cost, flexible and portable organic upconversion devices with high efficiency and simplified processing.

Analysis of Time Dependent Electric Field Degradation in AlGaN/GaN HEMTs (POSTPRINT)

DTIC Science & Technology

2014-10-01

identifying and understanding the failure mechanisms that limit the safe operating area of GaN HEMTs. 15. SUBJECT TERMS aluminum gallium nitride... gallium nitride, HEMTs, semiconductor device reliability, transistors 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT SAR 18. NUMBER...area of GaN HEMTs. Index Terms— Aluminum gallium nitride, gallium nitride, HEMTs, semiconductor device reliability, transistors. I. INTRODUCTION A

Layer-dependent electrical and optoelectronic responses of ReSe2 nanosheet transistors.

PubMed

Yang, Shengxue; Tongay, Sefaattin; Li, Yan; Yue, Qu; Xia, Jian-Bai; Li, Shun-Shen; Li, Jingbo; Wei, Su-Huai

2014-07-07

The ability to control the appropriate layer thickness of transition metal dichalcogenides (TMDs) affords the opportunity to engineer many properties for a variety of applications in possible technological fields. Here we demonstrate that band-gap and mobility of ReSe2 nanosheet, a new member of the TMDs, increase when the layer number decreases, thus influencing the performances of ReSe2 transistors with different layers. A single-layer ReSe2 transistor shows much higher device mobility of 9.78 cm(2) V(-1) s(-1) than few-layer transistors (0.10 cm(2) V(-1) s(-1)). Moreover, a single-layer device shows high sensitivity to red light (633 nm) and has a light-improved mobility of 14.1 cm(2) V(-1) s(-1). Molecular physisorption is used as "gating" to modulate the carrier density of our single-layer transistors, resulting in a high photoresponsivity (Rλ) of 95 A W(-1) and external quantum efficiency (EQE) of 18 645% in O2 environment. This work highlights the fact that the properties of ReSe2 can be tuned in terms of the number of layers and gas molecule gating, and single-layer ReSe2 with appropriate band-gap is a promising material for future functional device applications.

Polariton devices and quantum fluids

NASA Astrophysics Data System (ADS)

Ballarini, D.; De Giorgi, M.; Lerario, G.; Cannavale, A.; Cancellieri, E.; Bramati, A.; Gigli, G.; Laussy, F.; Sanvitto, D.

2014-02-01

Exciton-polaritons, composite particles resulting from the strong coupling between excitons and photons, have shown the capability to undergo condensation into a macroscopically coherent quantum state, demonstrating strong non-linearities and unique propagation properties. These strongly-coupled light-matter particles are promising candidates for the realization of semiconductor all-optical devices with fast time response and small energy consumption. Recently, quantum fluids of polaritons have been used to demonstrate the possibility to implement optical functionalities as spin switches, transistors or memories, but also to provide a channel for the transmission of information inside integrated circuits. In this context, the possibility to extend the range of light-matter interaction up to room temperature becomes of crucial importance. One of the most intriguing promises is to use organic Frenkel excitons, which, thanks to their huge oscillator strength, not only sustain the polariton picture at room temperature, but also bring the system into the unexplored regime of ultra-strong coupling. The combination of these materials with ad-hoc designed structures may allow the control of the propagation properties of polaritons, paving the way towards their implementation of the polariton functionalities in actual devices for opto-electronic applications.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

PubMed

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Solution-Processed Carbon Nanotube True Random Number Generator.

PubMed

Gaviria Rojas, William A; McMorrow, Julian J; Geier, Michael L; Tang, Qianying; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

2017-08-09

With the growing adoption of interconnected electronic devices in consumer and industrial applications, there is an increasing demand for robust security protocols when transmitting and receiving sensitive data. Toward this end, hardware true random number generators (TRNGs), commonly used to create encryption keys, offer significant advantages over software pseudorandom number generators. However, the vast network of devices and sensors envisioned for the "Internet of Things" will require small, low-cost, and mechanically flexible TRNGs with low computational complexity. These rigorous constraints position solution-processed semiconducting single-walled carbon nanotubes (SWCNTs) as leading candidates for next-generation security devices. Here, we demonstrate the first TRNG using static random access memory (SRAM) cells based on solution-processed SWCNTs that digitize thermal noise to generate random bits. This bit generation strategy can be readily implemented in hardware with minimal transistor and computational overhead, resulting in an output stream that passes standardized statistical tests for randomness. By using solution-processed semiconducting SWCNTs in a low-power, complementary architecture to achieve TRNG, we demonstrate a promising approach for improving the security of printable and flexible electronics.

Silicon Carbide Transistor For Detecting Hydrocarbon Gases

NASA Technical Reports Server (NTRS)

Shields, Virgil B.; Ryan, Margaret A.; Williams, Roger M.

1996-01-01

Proposed silicon carbide variable-potential insulated-gate field-effect transistor specially designed for use in measuring concentrations of hydrocarbon gases. Devices like this prove useful numerous automotive, industrial, aeronautical, and environmental monitoring applications.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Interaction of solid organic acids with carbon nanotube field effect transistors

NASA Astrophysics Data System (ADS)

Klinke, Christian; Afzali, Ali; Avouris, Phaedon

2006-10-01

A series of solid organic acids were used to p-dope carbon nanotubes. The extent of doping is shown to be dependent on the pKa value of the acids. Highly fluorinated carboxylic acids and sulfonic acids are very effective in shifting the threshold voltage and making carbon nanotube field effect transistors to be more p-type devices. Weaker acids like phosphonic or hydroxamic acids had less effect. The doping of the devices was accompanied by a reduction of the hysteresis in the transfer characteristics. In-solution doping survives standard fabrication processes and renders p-doped carbon nanotube field effect transistors with good transport characteristics.

An investigation into the feasibility of myoglobin-based single-electron transistors

PubMed Central

Li, Debin; Gannett, Peter M.; Lederman, David

2016-01-01

Myoglobin single-electron transistors were investigated using nanometer-gap platinum electrodes fabricated by electromigration at cryogenic temperatures. Apomyoglobin (myoglobin without heme group) was used as a reference. The results suggest single electron transport is mediated by resonant tunneling with the electronic and vibrational levels of the heme group in a single protein. They also represent a proof-of-principle that proteins with redox centers across nanometer-gap electrodes can be utilized to fabricate single-electron transistors. The protein orientation and conformation may significantly affect the conductance of these devices. Future improvements in device reproducibility and yield will require control of these factors. PMID:22972432

Going ballistic: Graphene hot electron transistors

NASA Astrophysics Data System (ADS)

Vaziri, S.; Smith, A. D.; Östling, M.; Lupina, G.; Dabrowski, J.; Lippert, G.; Mehr, W.; Driussi, F.; Venica, S.; Di Lecce, V.; Gnudi, A.; König, M.; Ruhl, G.; Belete, M.; Lemme, M. C.

2015-12-01

This paper reviews the experimental and theoretical state of the art in ballistic hot electron transistors that utilize two-dimensional base contacts made from graphene, i.e. graphene base transistors (GBTs). Early performance predictions that indicated potential for THz operation still hold true today, even with improved models that take non-idealities into account. Experimental results clearly demonstrate the basic functionality, with on/off current switching over several orders of magnitude, but further developments are required to exploit the full potential of the GBT device family. In particular, interfaces between graphene and semiconductors or dielectrics are far from perfect and thus limit experimental device integrity, reliability and performance.

Quantum engineering of transistors based on 2D materials heterostructures

NASA Astrophysics Data System (ADS)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Advanced technology component derating

NASA Astrophysics Data System (ADS)

Jennings, Timothy A.

1992-02-01

A technical study performed to determine the derating criteria of advanced technology components is summarized. The study covered existing criteria from AFSC Pamphlet 800-27 and the development of new criteria based on data, literature searches, and the use of advanced technology prediction methods developed in RADC-TR-90-72. The devices that were investigated were as follows: VHSIC, ASIC, MIMIC, Microprocessor, PROM, Power Transistors, RF Pulse Transistors, RF Multi-Transistor Packages, Photo Diodes, Photo Transistors, Opto-Electronic Couplers, Injection Laser Diodes, LED, Hybrid Deposited Film Resistors, Chip Resistors, and Capacitors and SAW devices. The results of the study are additional derating criteria that extend the range of AFSC Pamphlet 800-27. These data will be transitioned from the report to AFSC Pamphlet 800-27 for use by government and contractor personnel in derating electronics systems yielding increased safety margins and improved system reliability.

Quantum engineering of transistors based on 2D materials heterostructures.

PubMed

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain.

PubMed

Lee, Sungsik; Nathan, Arokia

2016-10-21

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation. Copyright © 2016, American Association for the Advancement of Science.

Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naquin, Clint; Lee, Mark; Edwards, Hal

2014-11-24

Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility ofmore » exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.« less

Hysteresis mechanism and control in pentacene organic field-effect transistors with polymer dielectric

NASA Astrophysics Data System (ADS)

Huang, Wei; Shi, Wei; Han, Shijiao; Yu, Junsheng

2013-05-01

Hysteresis mechanism of pentacene organic field-effect transistors (OFETs) with polyvinyl alcohol (PVA) and/or polymethyl methacrylate (PMMA) dielectrics is studied. Through analyzing the electrical characteristics of OFETs with various PVA/PMMA arrangements, it shows that charge, which is trapped in PVA bulk and at the interface of pentacene/PVA, is one of the origins of hysteresis. The results also show that memory window is proportional to both trap amount in PVA and charge density at the gate/PVA or PVA/pentacene interfaces. Hence, the controllable memory window of around 0 ˜ 10 V can be realized by controlling the thickness and combination of triple-layer polymer dielectrics.

Annealed Au-assisted epitaxial growth of si nanowires: control of alignment and density.

PubMed

Park, Yi-Seul; Jung, Da Hee; Kim, Hyun Ji; Lee, Jin Seok

2015-04-14

The epitaxial growth of 1D nanostructures is of particular interest for future nanoelectronic devices such as vertical field-effect transistors because it directly influences transistor densities and 3D logic or memory architectures. Silicon nanowires (SiNWs) are a particularly important 1D nanomaterial because they possess excellent electronic and optical properties. What is more, the scalable fabrication of vertically aligned SiNW arrays presents an opportunity for improved device applications if suitable properties can be achieved through controlling the alignment and density of SiNWs, yet this is something that has not been reported in the case of SiNWs synthesized from Au films. This work therefore explores the controllable synthesis of vertically aligned SiNWs through the introduction of an annealing process prior to growth via a Au-catalyzed vapor-liquid-solid mechanism. The epitaxial growth of SiNWs was demonstrated to be achievable using SiCl4 as the Si precursor in chemical vapor deposition, whereas the alignment and density of the SiNWs could be controlled by manipulating the annealing time during the formation of Au nanoparticles (AuNPs) from Au films. During the annealing process, gold silicide was observed to form on the interface of the liquid-phase AuNPs, depending on the size of the AuNPs and the annealing time. This work therefore makes a valuable contribution to improving nanowire-based engineering by controlling its alignment and density as well as providing greater insight into the epitaxial growth of 1D nanostructures.

Two dimensional simulation of patternable conducting polymer electrode based organic thin film transistor

NASA Astrophysics Data System (ADS)

Nair, Shiny; Kathiresan, M.; Mukundan, T.

2018-02-01

Device characteristics of organic thin film transistor (OTFT) fabricated with conducting polyaniline:polystyrene sulphonic acid (PANi-PSS) electrodes, patterned by the Parylene lift-off method are systematically analyzed by way of two dimensional numerical simulation. The device simulation was performed taking into account field-dependent mobility, low mobility layer at the electrode-semiconductor interface, trap distribution in pentacene film and trapped charge at the organic/insulator interface. The electrical characteristics of bottom contact thin film transistor with PANi-PSS electrodes and pentacene active material is superior to those with palladium electrodes due to a lower charge injection barrier. Contact resistance was extracted in both cases by the transfer line method (TLM). The extracted charge concentration and potential profile from the two dimensional numerical simulation was used to explain the observed electrical characteristics. The simulated device characteristics not only matched the experimental electrical characteristics, but also gave an insight on the charge injection, transport and trap properties of the OTFTs as a function of different electrode materials from the perspectives of transistor operation.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

High-performance transistors for bioelectronics through tuning of channel thickness

PubMed Central

Rivnay, Jonathan; Leleux, Pierre; Ferro, Marc; Sessolo, Michele; Williamson, Adam; Koutsouras, Dimitrios A.; Khodagholy, Dion; Ramuz, Marc; Strakosas, Xenofon; Owens, Roisin M.; Benar, Christian; Badier, Jean-Michel; Bernard, Christophe; Malliaras, George G.

2015-01-01

Despite recent interest in organic electrochemical transistors (OECTs), sparked by their straightforward fabrication and high performance, the fundamental mechanism behind their operation remains largely unexplored. OECTs use an electrolyte in direct contact with a polymer channel as part of their device structure. Hence, they offer facile integration with biological milieux and are currently used as amplifying transducers for bioelectronics. Ion exchange between electrolyte and channel is believed to take place in OECTs, although the extent of this process and its impact on device characteristics are still unknown. We show that the uptake of ions from an electrolyte into a film of poly(3,4-ethylenedioxythiophene) doped with polystyrene sulfonate (PEDOT:PSS) leads to a purely volumetric capacitance of 39 F/cm3. This results in a dependence of the transconductance on channel thickness, a new degree of freedom that we exploit to demonstrate high-quality recordings of human brain rhythms. Our results bring to the forefront a transistor class in which performance can be tuned independently of device footprint and provide guidelines for the design of materials that will lead to state-of-the-art transistor performance. PMID:26601178

Development of 3-Year Roadmap to Transform the Discipline of Systems Engineering

DTIC Science & Technology

2010-03-31

quickly humans could physically construct them. Indeed, magnetic core memory was entirely constructed by human hands until it was superseded by...For their mainframe computers, IBM develops the applications, operating system, computer hardware and microprocessors (off the shelf standard memory ...processor developers work on potential computational and memory pipelines to support the required performance capabilities and use the available transistors

Low-noise current amplifier based on mesoscopic Josephson junction.

PubMed

Delahaye, J; Hassel, J; Lindell, R; Sillanpää, M; Paalanen, M; Seppä, H; Hakonen, P

2003-02-14

We used the band structure of a mesoscopic Josephson junction to construct low-noise amplifiers. By taking advantage of the quantum dynamics of a Josephson junction, i.e., the interplay of interlevel transitions and the Coulomb blockade of Cooper pairs, we created transistor-like devices, Bloch oscillating transistors, with considerable current gain and high-input impedance. In these transistors, the correlated supercurrent of Cooper pairs is controlled by a small base current made up of single electrons. Our devices reached current and power gains on the order of 30 and 5, respectively. The noise temperature was estimated to be around 1 kelvin, but noise temperatures of less than 0.1 kelvin can be realistically achieved. These devices provide quantum-electronic building blocks that will be useful at low temperatures in low-noise circuit applications with an intermediate impedance level.

Teaching the Common Emitter Amplifier.

ERIC Educational Resources Information Center

Ellse, Mark D.

1984-01-01

Describes experiments in which a bipolar transistor is used to examine the behavior of a simple circuit. Also addresses problems in teaching the related concepts. (The experiments can be modified to incorporate devices other than bipolar transistors.) (JN)

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

Review of Heterojunctin Bipolar Transistor Structure, Applications, and Reliability

NASA Technical Reports Server (NTRS)

Lee, C.; Kayali, S.

1993-01-01

Heterojunction Bipolar Transistors (HBTs) are increasingly employed in high frequency, high linerity, and high efficiency applications. As the utilization of these devices becomes more widespread, their operation will be viewed with more scrutiny.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Evaluation of Enhanced Low Dose Rate Sensitivity in Discrete Bipolar Junction Transistors

NASA Technical Reports Server (NTRS)

Chen, Dakai; Ladbury Raymond; LaBel, Kenneth; Topper, Alyson; Ladbury, Raymond; Triggs, Brian; Kazmakites, Tony

2012-01-01

We evaluate the low dose rate sensitivity in several families of discrete bipolar transistors across device parameter, quality assurance level, and irradiation bias configuration. The 2N2222 showed the most significant low dose rate sensitivity, with low dose rate enhancement factor of 3.91 after 100 krad(Si). The 2N2907 also showed critical degradation levels. The devices irradiated at 10 mrad(Si)/s exceeded specifications after 40 and 50 krad(Si) for the 2N2222 and 2N2907 devices, respectively.

Negative differential resistance in GaN tunneling hot electron transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Zhichao; Nath, Digbijoy; Rajan, Siddharth

Room temperature negative differential resistance is demonstrated in a unipolar GaN-based tunneling hot electron transistor. Such a device employs tunnel-injected electrons to vary the electron energy and change the fraction of reflected electrons, and shows repeatable negative differential resistance with a peak to valley current ratio of 7.2. The device was stable when biased in the negative resistance regime and tunable by changing collector bias. Good repeatability and double-sweep characteristics at room temperature show the potential of such device for high frequency oscillators based on quasi-ballistic transport.

Superlattice structure modeling and simulation of High Electron Mobility Transistor for improved performance

NASA Astrophysics Data System (ADS)

Munusami, Ravindiran; Yakkala, Bhaskar Rao; Prabhakar, Shankar

2013-12-01

Magnetic tunnel junction were made by inserting the magnetic materials between the source, channel and the drain of the High Electron Mobility Transistor (HEMT) to enhance the performance. Material studio software package was used to design the superlattice layers. Different cases were analyzed to optimize the performance of the device by placing the magnetic material at different positions of the device. Simulation results based on conductivity reveals that the device has a very good electron transport due to the magnetic materials and will amplify very low frequency signals.

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2016-05-01

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions.

PubMed

Trommer, Jens; Heinzig, André; Mühle, Uwe; Löffler, Markus; Winzer, Annett; Jordan, Paul M; Beister, Jürgen; Baldauf, Tim; Geidel, Marion; Adolphi, Barbara; Zschech, Ehrenfried; Mikolajick, Thomas; Weber, Walter M

2017-02-28

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.

Wide Bandgap Semiconductor Nanowires for Electronic, Photonic and Sensing Devices

DTIC Science & Technology

2012-01-05

oxide -based thin film transistors ( TFTs ) have attracted much attention for applications like flexible electronic devices. The...crystals, and ~ 1.5 cm2.V-1.s-1 for pentacene thin films ). A number of groups have demonstrated TFTs based on α- oxide semiconductors such as zinc oxide ...show excellent long-term stability at room temperature. Results: High-performance amorphous (α-) InGaZnO-based thin film transistors ( TFTs )

Organic transistors for electrophysiology (Presentation Recording)

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan

2015-10-01

Efficient local transduction of biological signals is of critical importance for mapping brain activity and diagnosing pathological conditions. Traditional devices used to record electrophysiological signals are passive electrodes that require (pre)amplification with downstream electronics. Organic electrochemical transistors (OECTs) that utilize conducting polymer films as the channel have shown considerable promise as amplifying transducers due to their stability in aqueous conditions and high transconductance (>3 mS). The materials properties and physics of such transistors, however, remains largely unexplored thus limiting their potential. Here we show that the uptake of ionic charge from an electrolyte into a poly(3,4-ethylenedioxythiophene) doped with polystyrene sulfonate (PEDOT:PSS) OECT channel leads to a dependence of the effective capacitance on the entire volume of the film. Subsequently, device transconductance and time response vary with channel thickness, a defining characteristic that differentiates OECTs from field effect transistors, and provides a new degree of freedom for device engineering. Using this understanding we tailor OECTs for a variety of low (1-100 Hz) and high (1-10 kHz) frequency applications, including human electroencephalography, where high transconductance devices impart richer signal content without the need for additional amplification circuitry. We also show that the materials figure of merit OECTs is the product of hole mobility and volumetric capacitance of the channel, leading to design rules for novel high performance materials.

Bioinspired architecture approach for a one-billion transistor smart CMOS camera chip

NASA Astrophysics Data System (ADS)

Fey, Dietmar; Komann, Marcus

2007-05-01

In the paper we present a massively parallel VLSI architecture for future smart CMOS camera chips with up to one billion transistors. To exploit efficiently the potential offered by future micro- or nanoelectronic devices traditional on central structures oriented parallel architectures based on MIMD or SIMD approaches will fail. They require too long and too many global interconnects for the distribution of code or the access to common memory. On the other hand nature developed self-organising and emergent principles to manage successfully complex structures based on lots of interacting simple elements. Therefore we developed a new as Marching Pixels denoted emergent computing paradigm based on a mixture of bio-inspired computing models like cellular automaton and artificial ants. In the paper we present different Marching Pixels algorithms and the corresponding VLSI array architecture. A detailed synthesis result for a 0.18 μm CMOS process shows that a 256×256 pixel image is processed in less than 10 ms assuming a moderate 100 MHz clock rate for the processor array. Future higher integration densities and a 3D chip stacking technology will allow the integration and processing of Mega pixels within the same time since our architecture is fully scalable.

A thin-film microprocessor with inkjet print-programmable memory

NASA Astrophysics Data System (ADS)

Myny, Kris; Smout, Steve; Rockelé, Maarten; Bhoolokam, Ajay; Ke, Tung Huei; Steudel, Soeren; Cobb, Brian; Gulati, Aashini; Rodriguez, Francisco Gonzalez; Obata, Koji; Marinkovic, Marko; Pham, Duy-Vu; Hoppe, Arne; Gelinck, Gerwin H.; Genoe, Jan; Dehaene, Wim; Heremans, Paul

2014-12-01

The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration of relatively simple electronics, for example through `stick-on' electronics labels. We believe the future evolution of this technology will be governed by Wright's Law, which was first proposed in 1936 and states that the cost of a product decreases with cumulative production. This implies that a generic electronic device that can be tailored for application-specific requirements during downstream integration would be a cornerstone in the development of the Internet of Things. We present an 8-bit thin-film microprocessor with a write-once, read-many (WORM) instruction generator that can be programmed after manufacture via inkjet printing. The processor combines organic p-type and soluble oxide n-type thin-film transistors in a new flavor of the familiar complementary transistor technology with the potential to be manufactured on a very thin polyimide film, enabling low-cost flexible electronics. It operates at 6.5 V and reaches clock frequencies up to 2.1 kHz. An instruction set of 16 code lines, each line providing a 9 bit instruction, is defined by means of inkjet printing of conductive silver inks.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors.

PubMed

Giusi, G; Giordano, O; Scandurra, G; Rapisarda, M; Calvi, S; Ciofi, C

2016-04-01

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz(1/2), while DC performances are limited only by the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.

High sensitivity measurement system for the direct-current, capacitance-voltage, and gate-drain low frequency noise characterization of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Giusi, G.; Giordano, O.; Scandurra, G.

Measurements of current fluctuations originating in electron devices have been largely used to understand the electrical properties of materials and ultimate device performances. In this work, we propose a high-sensitivity measurement setup topology suitable for the automatic and programmable Direct-Current (DC), Capacitance-Voltage (CV), and gate-drain low frequency noise characterization of field effect transistors at wafer level. Automatic and programmable operation is particularly useful when the device characteristics relax or degrade with time due to optical, bias, or temperature stress. The noise sensitivity of the proposed topology is in the order of fA/Hz{sup 1/2}, while DC performances are limited only bymore » the source and measurement units used to bias the device under test. DC, CV, and NOISE measurements, down to 1 pA of DC gate and drain bias currents, in organic thin film transistors are reported to demonstrate system operation and performances.« less

Large contact noise in graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Karnatak, Paritosh; Sai, Phanindra; Goswami, Srijit; Ghatak, Subhamoy; Kaushal, Sanjeev; Ghosh, Arindam

Fluctuations in the electrical resistance at the interface of atomically thin materials and metals, or the contact noise, can adversely affect the device performance but remains largely unexplored. We have investigated contact noise in graphene field effect transistors of varying device geometry and contact configuration, with channel carrier mobility ranging from 5,000 to 80,000 cm2V-1s-1. A phenomenological model developed for contact noise due to current crowding for two dimensional conductors, shows a dominant contact contribution to the measured resistance noise in all graphene field effect transistors when measured in the two-probe or invasive four probe configurations, and surprisingly, also in nearly noninvasive four probe (Hall bar) configuration in the high mobility devices. We identify the fluctuating electrostatic environment of the metal-channel interface as the major source of contact noise, which could be generic to two dimensional material-based electronic devices. The work was financially supported by the Department of Science and Technology, India and Tokyo Electron Limited.

Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

NASA Astrophysics Data System (ADS)

Celik, Cihangir

Advances in microelectronics result in sub-micrometer electronic technologies as predicted by Moore's Law, 1965, which states the number of transistors in a given space would double every two years. The most available memory architectures today have submicrometer transistor dimensions. The International Technology Roadmap for Semiconductors (ITRS), a continuation of Moore's Law, predicts that Dynamic Random Access Memory (DRAM) will have an average half pitch size of 50 nm and Microprocessor Units (MPU) will have an average gate length of 30 nm over the period of 2008-2012. Decreases in the dimensions satisfy the producer and consumer requirements of low power consumption, more data storage for a given space, faster clock speed, and portability of integrated circuits (IC), particularly memories. On the other hand, these properties also lead to a higher susceptibility of IC designs to temperature, magnetic interference, power supply, and environmental noise, and radiation. Radiation can directly or indirectly affect device operation. When a single energetic particle strikes a sensitive node in the micro-electronic device, it can cause a permanent or transient malfunction in the device. This behavior is called a Single Event Effect (SEE). SEEs are mostly transient errors that generate an electric pulse which alters the state of a logic node in the memory device without having a permanent effect on the functionality of the device. This is called a Single Event Upset (SEU) or Soft Error . Contrary to SEU, Single Event Latchup (SEL), Single Event Gate Rapture (SEGR), or Single Event Burnout (SEB) they have permanent effects on the device operation and a system reset or recovery is needed to return to proper operations. The rate at which a device or system encounters soft errors is defined as Soft Error Rate (SER). The semiconductor industry has been struggling with SEEs and is taking necessary measures in order to continue to improve system designs in nano-scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement results show that soft errors in the memories increase proportionally with the neutron flux, whereas they decrease with increasing the supply voltages. NISC design considerations include the effects of device scaling, 10B content in the BPSG layer, incoming neutron energy, and critical charge of the node for this dissertation. NISCSAT simulations were performed with various memory node models to account these effects. Device scaling simulations showed that any further increase in the thickness of the BPSG layer beyond 2 mum causes self-shielding of the incoming neutrons due to the BPSG layer and results in lower detection efficiencies. Moreover, if the BPSG layer is located more than 4 mum apart from the depletion region in the node, there are no soft errors in the node due to the fact that both of the reaction products have lower ranges in the silicon or any possible node layers. Calculation results regarding the critical charge indicated that the mean charge deposition of the reaction products in the sensitive volume of the node is about 15 fC. It is evident that the NISC design should have a memory architecture with a critical charge of 15 fC or less to obtain higher detection efficiencies. Moreover, the sensitive volume should be placed in close proximity to the BPSG layers so that its location would be within the range of alpha and 7Li particles. Results showed that the distance between the BPSG layer and the sensitive volume should be less than 2 mum to increase the detection efficiency of the NISC. Incoming neutron energy was also investigated by simulations and the results obtained from these simulations showed that NISC neutron detection efficiency is related with the neutron cross-sections of 10B (n,alpha) 7Li reaction, e.g., ratio of the thermal (0.0253 eV) to fast (2 MeV) neutron detection efficiencies is approximately equal to 8000:1. Environmental conditions and their effects on the NISC performance were also studied in this research. Cosmic rays were modeled and simulated via NISCSAT to investigate detection reliability of the NISC. Simulation results show that cosmic rays account for less than 2 % of the soft errors for the thermal neutron detection. On the other hand, fast neutron detection by the NISC, which already has a poor efficiency due to the low neutron cross-sections, becomes almost impossible at higher altitudes where the cosmic ray fluxes and their energies are higher. NISCSAT simulations regarding soft error dependency of the NISC for temperature and electromagnetic fields show that there are no significant effects in the NISC detection efficiency. Furthermore, the detection efficiency of the NISC decreases with both air humidity and use of moderators since the incoming neutrons scatter away before reaching the memory surface.

Diffused Silicon Transistors and Switches (1954-55): The Beginning of Integrated Circuit Technology

NASA Astrophysics Data System (ADS)

Holonyak, N.

2003-09-01

Silicon (Si) transistor and integrated circuit (IC) technology has grown so big, and become so important, that it is now hard to recognize where, apart from the invention of the transistor itself (Bardeen and Brattain, Dec 16, 1947), it had its origin. In spite of obvious differences in Ge and Si, in 1950-55 it was not evident in many laboratories, concentrating only on Ge, what form of Ge transistor (grown, alloyed, jet-etched, etc.) might be expected to prevail, with Si not even being considered (or being dismissed outright). What was the need for Si and, at the time, such a seemingly intractable peculiar new technology? The requirement on switching devices of low leakage, and thus the need to leave Ge in favor of Si, led directly in 1954-55 (Bell Telephone Laboratories, BTL) to the exploration of impurity-diffusion and metallization technology to realize Si transistors and p-n-p-n switches. This technology, a more or less ideal thin-layer technology that can be referenced from a single surface (and which indeed has proven to be basically invariant and constantly growing), led further to the discovery (1955) of the protective Si oxide, oxide masking and patterning, and the fundamental basis of the integrated circuit (i.e., device-to-device interconnection by patterned metallization across the oxide). We recount some of the exploratory diffused-impurity Si device development of 1954-55 at BTL, particularly the work in and near Moll's group, that helped to establish the basis for today's electronics. The Si diffused-impurity devices of 1954-55 are described, including work and data not previously reported or broadly known—in fact, much work and data (a new technology) that was carried across the Country to a place that became known as Silicon Valley. For further perspective, an appendix is included of independent early suggestions of Bardeen (Urbana notebook, Feb 1952) to leave Ge in favor of diffused Si devices.

Proton irradiation effects on gallium nitride-based devices

NASA Astrophysics Data System (ADS)

Karmarkar, Aditya P.

Proton radiation effects on state-of-the-art gallium nitride-based devices were studied using Schottky diodes and high electron-mobility transistors. The device degradation was studied over a wide range of proton fluences. This study allowed for a correlation between proton irradiation effects between different types of devices and enhanced the understanding of the mechanisms responsible for radiation damage in GaN-based devices. Proton irradiation causes reduced carrier concentration and increased series resistance and ideality factor in Schottky diodes. 1.0-MeV protons cause greater degradation than 1.8-MeV protons because of their higher non-ionizing energy loss. The displacement damage in Schottky diodes recovers during annealing. High electron-mobility transistors exhibit extremely high radiation tolerance, continuing to perform up to a fluence of ˜1014 cm-2 of 1.8-MeV protons. Proton irradiation creates defect complexes in the thin-film structure. Decreased sheet carrier mobility due to increased carrier scattering and decreased sheet carrier density due to carrier removal by the defect centers are the primary damage mechanisms. Interface disorder at either the Schottky or the Ohmic contact plays a relatively unimportant part in overall device degradation in both Schottky diodes and high electron-mobility transistors.

Organic Light-Emitting Transistors: Materials, Device Configurations, and Operations.

PubMed

Zhang, Congcong; Chen, Penglei; Hu, Wenping

2016-03-09

Organic light-emitting transistors (OLETs) represent an emerging class of organic optoelectronic devices, wherein the electrical switching capability of organic field-effect transistors (OFETs) and the light-generation capability of organic light-emitting diodes (OLEDs) are inherently incorporated in a single device. In contrast to conventional OFETs and OLEDs, the planar device geometry and the versatile multifunctional nature of OLETs not only endow them with numerous technological opportunities in the frontier fields of highly integrated organic electronics, but also render them ideal scientific scaffolds to address the fundamental physical events of organic semiconductors and devices. This review article summarizes the recent advancements on OLETs in light of materials, device configurations, operation conditions, etc. Diverse state-of-the-art protocols, including bulk heterojunction, layered heterojunction and laterally arranged heterojunction structures, as well as asymmetric source-drain electrodes, and innovative dielectric layers, which have been developed for the construction of qualified OLETs and for shedding new and deep light on the working principles of OLETs, are highlighted by addressing representative paradigms. This review intends to provide readers with a deeper understanding of the design of future OLETs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

MOSFET's for Cryogenic Amplifiers

NASA Technical Reports Server (NTRS)

Dehaye, R.; Ventrice, C. A.

1987-01-01

Study seeks ways to build transistors that function effectively at liquid-helium temperatures. Report discusses physics of metaloxide/semiconductor field-effect transistors (MOSFET's) and performances of these devices at cryogenic temperatures. MOSFET's useful in highly sensitive cryogenic preamplifiers for infrared astronomy.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

PubMed

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Linear conduction in N-type organic field effect transistors with nanometric channel lengths and graphene as electrodes

NASA Astrophysics Data System (ADS)

Chianese, F.; Candini, A.; Affronte, M.; Mishra, N.; Coletti, C.; Cassinese, A.

2018-05-01

In this work, we test graphene electrodes in nanometric channel n-type Organic Field Effect Transistors (OFETs) based on thermally evaporated thin films of the perylene-3,4,9,10-tetracarboxylic acid diimide derivative. By a thorough comparison with short channel transistors made with reference gold electrodes, we found that the output characteristics of the graphene-based devices respond linearly to the applied bias, in contrast with the supralinear trend of gold-based transistors. Moreover, short channel effects are considerably suppressed in graphene electrode devices. More specifically, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for L down to ˜140 nm. These results are rationalized taking into account the morphological and electronic characteristics of graphene, showing that the use of graphene electrodes may help to overcome the problem of Space Charge Limited Current in short channel OFETs.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

PubMed Central

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

The fabrication and optical detection of a vertical structure organic thin film transistor

NASA Astrophysics Data System (ADS)

Zhang, H.; Wang, D.; Jia, P.

2014-03-01

Using vacuum evaporation and sputtering process, we prepared a photoelectric transistor with the vertical structure of Cu/copper phthalocyanine (CuPc)/Al/copper phthalocyanine (CuPc)/ITO. The material of CuPc semiconductor has good photosensitive properties. Excitons will be generated after the optical signal irradiation in semiconductor material, and then transformed into photocurrent under the built-in electric field formed by the Schottky contact, as the organic transistor drive current makes the output current enlarged. The results show that the I-V characteristics of transistor are unsaturated. When device was irradiated by full band (white) light, its working current significantly increased. In full band white light, when Vec = 3 V, the ratio of light and no light current was ranged for 2.9-6.4 times. Device in the absence of light current amplification coefficient is 16.5, and white light amplification coefficient is 98.65.

Disabling CNT Electronic Devices by Use of Electron Beams

NASA Technical Reports Server (NTRS)

Petkov, Mihail

2008-01-01

Bombardment with tightly focused electron beams has been suggested as a means of electrically disabling selected individual carbon-nanotubes (CNTs) in electronic devices. Evidence in support of the suggestion was obtained in an experiment in which a CNT field-effect transistor was disabled (see figure) by focusing a 1-keV electron beam on a CNT that served as the active channel of a field-effect transistor (FET). Such bombardment could be useful in the manufacture of nonvolatile-memory circuits containing CNT FETs. Ultimately, in order to obtain the best electronic performances in CNT FETs and other electronic devices, it will be necessary to fabricate the devices such that each one contains only a single CNT as an active element. At present, this is difficult because there is no way to grow a single CNT at a specific location and with a specific orientation. Instead, the common practice is to build CNTs into electronic devices by relying on spatial distribution to bridge contacts. This practice results in some devices containing no CNTs and some devices containing more than one CNT. Thus, CNT FETs have statistically distributed electronic characteristics (including switching voltages, gains, and mixtures of metallic and semiconducting CNTs). According to the suggestion, by using a 1-keV electron beam (e.g., a beam from a scanning electron microscope), a particular nanotube could be rendered electrically dysfunctional. This procedure could be repeated as many times as necessary on different CNTs in a device until all of the excess CNTs in the device had been disabled, leaving only one CNT as an active element (e.g., as FET channel). The physical mechanism through which a CNT becomes electrically disabled is not yet understood. On one hand, data in the literature show that electron kinetic energy >86 keV is needed to cause displacement damage in a CNT. On the other hand, inasmuch as a 1-keV beam focused on a small spot (typically a few tens of nanometers wide) deposits a significant amount of energy in a small volume, the energy density may suffice to thermally induce structural and/or electronic changes that disable the CNT. Research may be warranted to investigate this effect in detail.

Studies Of Single-Event-Upset Models

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.

1988-01-01

Report presents latest in series of investigations of "soft" bit errors known as single-event upsets (SEU). In this investigation, SEU response of low-power, Schottky-diode-clamped, transistor/transistor-logic (TTL) static random-access memory (RAM) observed during irradiation by Br and O ions in ranges of 100 to 240 and 20 to 100 MeV, respectively. Experimental data complete verification of computer model used to simulate SEU in this circuit.

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, W.L.; Vanheusden, K.; Fleetwood, D.M.

Recently, the authors have demonstrated that annealing Si/SiO{sub 2}/Si structures in a hydrogen containing ambient introduces mobile H{sup +} ions into the buried SiO{sub 2} layer. Changes in the H{sup +} spatial distribution within the SiO{sub 2} layer were electrically monitored by current-voltage (I-V) measurements. The ability to directly probe reversible protonic motion in Si/SiO{sub 2}/Si structures makes this an exemplar system to explore the physics and chemistry of hydrogen in the technologically relevant Si/SiO{sub 2} structure. In this work, they illustrate that this effect can be used as the basis for a programmable nonvolatile field effect transistor (NVFET) memorymore » that may compete with other Si-based memory devices. The power of this novel device is its simplicity; it is based upon standard Si/SiO{sub 2}/Si technology and forming gas annealing, a common treatment used in integrated circuit processing. They also briefly discuss the effects of radiation on its retention properties.« less

Semiconductor Characterization: from Growth to Manufacturing

NASA Astrophysics Data System (ADS)

Colombo, Luigi

The successful growth and/or deposition of materials for any application require basic understanding of the materials physics for a given device. At the beginning, the first and most obvious characterization tool is visual observation; this is particularly true for single crystal growth. The characterization tools are usually prioritized in order of ease of measurement, and have become especially sophisticated as we have moved from the characterization of macroscopic crystals and films to atomically thin materials and nanostructures. While a lot attention is devoted to characterization and understanding of materials physics at the nano level, the characterization of single crystals as substrates or active components is still critically important. In this presentation, I will review and discuss the basic materials characterization techniques used to get to the materials physics to bring crystals and thin films from research to manufacturing in the fields of infrared detection, non-volatile memories, and transistors. Finally I will present and discuss metrology techniques used to understand the physics and chemistry of atomically thin two-dimensional materials for future device applications.

Modelling of the hole-initiated impact ionization current in the framework of hydrodynamic equations

NASA Astrophysics Data System (ADS)

Lorenzini, Martino; Van Houdt, Jan

2002-02-01

Several research papers have shown the feasibility of the hydrodynamic transport model to investigate impact ionization in semiconductor devices by means of mean-energy-dependent generation rates. However, the analysis has been usually carried out for the case of the electron-initiated impact ionization process and less attention has been paid to the modelling of the generation rate due to impact ionization events initiated by holes. This paper therefore presents an original model for the hole-initiated impact ionization in silicon and validates it by comparing simulation results with substrate currents taken from p-channel transistors manufactured in a 0.35 μm CMOS technology having three different channel lengths. The experimental data are successfully reproduced over a wide range of applied voltages using only one fitting parameter. Since the impact ionization of holes triggers the mechanism responsible for the back-bias enhanced gate current in deep submicron nMOS devices, the model can be exploited in the development of non-volatile memories programmed by secondary electron injection.

A microprocessor based on a two-dimensional semiconductor

PubMed Central

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-01-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III–V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor—molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material. PMID:28398336

A trident dithienylethene-perylenemonoimide dyad with super fluorescence switching speed and ratio

NASA Astrophysics Data System (ADS)

Li, Chong; Yan, Hui; Zhao, Ling-Xi; Zhang, Guo-Feng; Hu, Zhe; Huang, Zhen-Li; Zhu, Ming-Qiang

2014-12-01

Photoswitchable fluorescent diarylethenes are promising in molecular optical memory and photonic devices. However, the performance of current diarylethenes is far from satisfactory because of the scarcity of high-speed switching capability and large fluorescence on-off ratio. Here we report a trident perylenemonoimide dyad modified by triple dithienylethenes whose photochromic fluorescence quenching ratio at the photostationary state exceeds 10,000 and the fluorescence quenching efficiency is close to 100% within seconds of ultraviolet irradiation. The highly sensitive fluorescence on/off switching of the trident dyad enables recyclable fluorescence patterning and all-optical transistors. The prototype optical device based on the trident dyad enables the optical switching of incident light and conversion from incident light wavelength to transmitted light wavelength, which is all-optically controlled, reversible and wavelength-convertible. In addition, the trident dyad-staining block copolymer vesicles are observed via optical nanoimaging with a sub-100 nm resolution, portending a potential prospect of the dithienylethene dyad in super-resolution imaging.

A trident dithienylethene-perylenemonoimide dyad with super fluorescence switching speed and ratio.

PubMed

Li, Chong; Yan, Hui; Zhao, Ling-Xi; Zhang, Guo-Feng; Hu, Zhe; Huang, Zhen-Li; Zhu, Ming-Qiang

2014-12-12

Photoswitchable fluorescent diarylethenes are promising in molecular optical memory and photonic devices. However, the performance of current diarylethenes is far from satisfactory because of the scarcity of high-speed switching capability and large fluorescence on-off ratio. Here we report a trident perylenemonoimide dyad modified by triple dithienylethenes whose photochromic fluorescence quenching ratio at the photostationary state exceeds 10,000 and the fluorescence quenching efficiency is close to 100% within seconds of ultraviolet irradiation. The highly sensitive fluorescence on/off switching of the trident dyad enables recyclable fluorescence patterning and all-optical transistors. The prototype optical device based on the trident dyad enables the optical switching of incident light and conversion from incident light wavelength to transmitted light wavelength, which is all-optically controlled, reversible and wavelength-convertible. In addition, the trident dyad-staining block copolymer vesicles are observed via optical nanoimaging with a sub-100 nm resolution, portending a potential prospect of the dithienylethene dyad in super-resolution imaging.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

Towards phase-coherent caloritronics in superconducting circuits

NASA Astrophysics Data System (ADS)

Fornieri, Antonio; Giazotto, Francesco

2017-10-01

The emerging field of phase-coherent caloritronics (from the Latin word calor, heat) is based on the possibility of controlling heat currents by using the phase difference of the superconducting order parameter. The goal is to design and implement thermal devices that can control energy transfer with a degree of accuracy approaching that reached for charge transport by contemporary electronic components. This can be done by making use of the macroscopic quantum coherence intrinsic to superconducting condensates, which manifests itself through the Josephson effect and the proximity effect. Here, we review recent experimental results obtained in the realization of heat interferometers and thermal rectifiers, and discuss a few proposals for exotic nonlinear phase-coherent caloritronic devices, such as thermal transistors, solid-state memories, phase-coherent heat splitters, microwave refrigerators, thermal engines and heat valves. Besides being attractive from the fundamental physics point of view, these systems are expected to have a vast impact on many cryogenic microcircuits requiring energy management, and possibly lay the first stone for the foundation of electronic thermal logic.

Towards phase-coherent caloritronics in superconducting circuits.

PubMed

Fornieri, Antonio; Giazotto, Francesco

2017-10-06

The emerging field of phase-coherent caloritronics (from the Latin word calor, heat) is based on the possibility of controlling heat currents by using the phase difference of the superconducting order parameter. The goal is to design and implement thermal devices that can control energy transfer with a degree of accuracy approaching that reached for charge transport by contemporary electronic components. This can be done by making use of the macroscopic quantum coherence intrinsic to superconducting condensates, which manifests itself through the Josephson effect and the proximity effect. Here, we review recent experimental results obtained in the realization of heat interferometers and thermal rectifiers, and discuss a few proposals for exotic nonlinear phase-coherent caloritronic devices, such as thermal transistors, solid-state memories, phase-coherent heat splitters, microwave refrigerators, thermal engines and heat valves. Besides being attractive from the fundamental physics point of view, these systems are expected to have a vast impact on many cryogenic microcircuits requiring energy management, and possibly lay the first stone for the foundation of electronic thermal logic.

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik

2015-02-14

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

Detection of saliva-range glucose concentrations using organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elkington, D.; Belcher, W. J.; Dastoor, P. C.

We describe the development of a glucose sensor through direct incorporation of an enzyme (glucose oxidase) into the gate of an organic thin film transistor (OTFT). We show that glucose diffusion is the key determinant of the device response time and present a mechanism of glucose sensing in these devices that involves protonic doping of the transistor channel via enzymatic oxidation of glucose. The integrated OTFT sensor is sensitive across 4 decades of glucose concentration; a range that encompasses both the blood and salivary glucose concentration levels. As such, this work acts as a proof-of-concept for low-cost printed biosensors formore » salivary glucose.« less

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and static induction transistors (SITs) are given. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Postirradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

EDITORIAL: Nanotechnology-based flexible electronics Nanotechnology-based flexible electronics

NASA Astrophysics Data System (ADS)

Subramanian, Vivek; Lee, Takhee

2012-08-01

Research on flexible electronics has grown exponentially over the last decade. Researchers around the globe are developing a wide range of flexible systems, including displays [1, 2], sensors [3-5], RFID tags [6, 7] and other similar devices [8]. Innovations in materials have been key to the increased research success in this field of research in recent years [9]. Transistors, interconnects, memory cells, passive components and other assorted devices all have challenging material demands for flexible electronics to become a reality. Nanomaterials of various kinds have been found to represent a tremendously powerful tool, with nanoparticles [10], nanotubes, nanowires [3, 11] and engineered organic molecules [12, 13] contributing to the realization of high-performance semiconductors, dielectrics and conductors for flexible electronics applications. Nanomaterials offer tunability in terms of performance, solution processability and processing temperature requirements, which makes them very attractive as building blocks for flexible electronic systems. Indeed, such systems represent some of the largest families of commercially produced nanomaterials today, and numerous commercial products based on nanoparticle formulations are widely available. This special issue focuses on the rapidly blossoming field of flexible electronics, with a particular focus on the use of nanotechnology to facilitate flexible electronic materials, processes, devices and systems. Contributions to the issue describe the development of nanomaterials—including nanoparticles, nanotubes, nanowires and carbon-based thin films—for use in conductors, transparent electrodes, semiconductors and dielectrics. The articles feature innovations in nanomanufacturing and novel materials, as well as the application of these technologies to advanced flexible devices and systems. As flexible electronics systems move rapidly towards successful commercial deployment, it is extremely likely that they will exploit nanomaterials as building blocks. Developments in the field will help to leverage the power of these materials to realize novel functionalities in flexible form factors. This special issue provides a view of the state of the art in these technologies, and gives a vision of the coming innovations that will make flexible electronics a reality. References [1] Gelinck G H et al 2004 Flexible active-matrix displays and shift registers based on solution-processed organic transistors Nature Mater. 3 106-10 [2] Zhou L, Wanga A, Wu S C, Sun J, Park S and Jackson T N 2006 All-organic active matrix flexible display Appl. Phys. Lett. 88 083502 [3] Fan Z, Ho J C, Jacobson Z A, Razavi H and Javey A 2008 Large-scale, heterogeneous integration of nanowire arrays for image sensor circuitry Proc. Natl Acad. Sci. 105 11066 [4] Sekitani T et al 2009 Organic nonvolatile memory transistors for flexible sensor arrays Science 326 1516-9 [5] Mannsfeld S C B et al 2010 Highly sensitive flexible pressure sensors with microstructured rubber dielectric layers Nature Mater. 9 859-64 [6]Subramanian V, Frechet J M J, Chang P C, Huang D C, Lee J B, Molesa S E, Murphy A R, Redinger D R and Volkman S K 2005 Progress toward development of all-printed RFID tags: materials, processes, and devices Proc. IEEE 93 1330-8 [7] Jung M et al 2010 All-printed and roll-to-roll-printable 13.56 MHz-operated 1 bit RF tag on plastic foils IEEE Trans. Electron. Devices 57 571-80 [8] Kim D-H et al 2011 Epidermal electronics Science 333 838-43 [9] Wagner S and Bauer S 2012 Materials for stretchable electronics MRS Bull. 37 207 [10] Grouchko M, Kamyshny A and Magdassi S 2009 Formation of air-stable copper-silver core-shell nanoparticles for inkjet printing J. Mater. Chem. 19 3057-62 [11] Takei K et al 2010 Nanowire active-matrix circuitry for low-voltage macroscale artificial skin Nature Mater. 9 821-6 [12] Sekitani T, Zschieschang U, Klauk H and Someya T 2010 Flexible organic transistors and circuits with extreme bending stability Nature Mater. 9 1015-22 [13] Park S, Wang G, Cho B, Kim Y, Song S, Ji Y, Yoon M and Lee T 2012 Flexible molecular-scale electronic devices Nature Nanotechnol. 7 438-42

Achieving high mobility, low-voltage operating organic field-effect transistor nonvolatile memory by an ultraviolet-ozone treating ferroelectric terpolymer

PubMed Central

Xiang, Lanyi; Wang, Wei; Xie, Wenfa

2016-01-01

Poly(vinylidene fluoride–trifluoroethylene) has been widely used as a dielectric of the ferroelectric organic field-effect transistor (FE-OFET) nonvolatile memory (NVM). Some critical issues, including low mobility and high operation voltage, existed in these FE-OFET NVMs, should be resolved before considering to their commercial application. In this paper, we demonstrated low-voltage operating FE-OFET NVMs based on a ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)] owed to its low coercive field. By applying an ultraviolet-ozone (UVO) treatment to modify the surface of P(VDF-TrFE-CTFE) films, the growth model of the pentacene film was changed, which improved the pentacene grain size and the interface morphology of the pentacene/P(VDF-TrFE-CTFE). Thus, the mobility of the FE-OFET was significantly improved. As a result, a high performance FE-OFET NVM, with a high mobility of 0.8 cm2 V−1 s−1, large memory window of 15.4~19.2, good memory on/off ratio of 103, the reliable memory endurance over 100 cycles and stable memory retention ability, was achieved at a low operation voltage of ±15 V. PMID:27824101

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

PubMed

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Comparison of effect of 5 MeV proton and Co-60 gamma irradiation on silicon NPN rf power transistors and N-channel depletion MOSFETs

NASA Astrophysics Data System (ADS)

Gnana Prakash, A. P.; Pradeep, T. M.; Hegde, Vinayakprasanna N.; Pushpa, N.; Bajpai, P. K.; Patel, S. P.; Trivedi, Tarkeshwar; Bhushan, K. G.

2017-12-01

NPN transistors and N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 5 MeV protons and 60Co gamma radiation in the dose ranging from 1 Mrad(Si) to 100 Mrad(Si). The different electrical characteristics of the NPN transistor such as Gummel characteristics, excess base current (ΔIB), dc current gain (hFE), transconductance (gm), displacement damage factor (K) and output characteristics were studied as a function of total dose. The different electrical characteristics of N-channel MOSFETs such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot), transconductance (gm), mobility (µ) and drain saturation current (IDSat) were studied systematically before and after irradiation in the same dose ranges. A considerable increase in the base current (IB) and decrease in the hFE, gm and collector saturation current (ICSat) were observed after irradiation in the case of the NPN transistor. In the N-channel MOSFETs, the ΔNit and ΔNot were found to increase and Vth, gm, µ and IDSat were found to decrease with increase in the radiation dose. The 5 MeV proton irradiation results of both the NPN transistor and N-channel MOSFETs were compared with 60Co gamma-irradiated devices in the same dose ranges. It was observed that the degradation in 5 MeV proton-irradiated devices is more when compared with the 60Co gamma-irradiated devices at higher total doses.

A NANO enhancement to Moore's law

NASA Astrophysics Data System (ADS)

Wu, Jerry; Shen, Yin-Lin; Reinhardt, Kitt; Szu, Harold

2012-06-01

In the past 46 years, Intel Moore observed an exponential doubling in the number of transistors in every 18 months through the size reduction of individual transistor components since 1965. In this paper, we are exploring the nanotechnology impact upon the Law. Since we cannot break down the atomic size barrier, the fact implies a fundamental size limit at the atomic or Nanotechnology scale. This means, no more simple 18 month doubling as in Moore's Law, but other forms of transistor doubling may happen at a different slope in new directions. We are particularly interested in the Nano enhancement area. (i) 3-D: If the progress in shrinking the in-plane dimensions (2D) is to slow down, vertical integration (3D) can help increasing the areal device transistor density and keep us on the modified Moore's Law curve including the 3rd dimension. As the devices continue to shrink further into the 20 to 30 nm range, the consideration of thermal properties and transport in such nanoscale devices becomes increasingly important. (ii) Carbon Computing: Instead of traditional Transistors, the other types of transistors material are rapidly developed in Laboratories Worldwide, e.g. IBM Spintronics bandgap material and Samsung Nano-storage material, HD display Nanotechnology, which are modifying the classical Moore's Law. We shall consider the overall limitation of phonon engineering, fundamental information unit 'Qubyte' in quantum computing, Nano/Micro Electrical Mechanical System (NEMS), Carbon NanoTubes (CNTs), single layer Graphemes, single strip Nano-Ribbons, etc., and their variable degree of fabrication maturities for the computing and information processing applications.

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Npn double heterostructure bipolar transistor with ingaasn base region

DOEpatents

Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.

2004-07-20

An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Center for High-Frequency Microelectronics

DTIC Science & Technology

1992-08-31

34 IEEE Transactions on Electron Devices, 38, No. 6, pp. 1324-1333, June 1991. 185. C. C. Chen, R. K. Mains and G. I. Haddad, " High - Power Generation in...Weiss, J. Hu and W.-P. Hong, "Electronic 0 Properties of Power High Electron Mobility Transistors," Conference on Ballistic Electrons for Transistors...method at higher frequencies than previously believed. - Calculations of high - power generation modes in Si IMPATT devices in the 100-200 GHz range have

IGZO thin film transistor biosensors functionalized with ZnO nanorods and antibodies.

PubMed

Shen, Yi-Chun; Yang, Chun-Hsu; Chen, Shu-Wen; Wu, Shou-Hao; Yang, Tsung-Lin; Huang, Jian-Jang

2014-04-15

We demonstrate a biosensor structure consisting of an IGZO (Indium-Gallium-Zinc-Oxide) TFT (thin film transistor) and an extended sensing pad. The TFT acts as the sensing and readout device, while the sensing pad ensures the isolation of biological solution from the transistor channel layer, and meanwhile increases the sensing area. The biosensor is functionalized by first applying ZnO nanorods to increase the surface area for attracting electrical charges of EGFR (epidermal growth factor receptor) antibodies. The device is able to selectively detect 36.2 fM of EGFR in the total protein solution of 0.1 ng/ml extracted from squamous cell carcinoma (SCC). Furthermore, the conjugation duration of the functionalized device with EGFR can be limited to 3 min, implying that the biosensor has the advantage for real-time detection. © 2013 Elsevier B.V. All rights reserved.

Energy dependence of proton displacement damage factors for bipolar transistors

NASA Astrophysics Data System (ADS)

Summers, Geoffrey P.; Xapsos, Michael A.; Dale, Cheryl J.; Wolicki, Eligius A.; Marshall, Paul

1986-12-01

Displacement damage factors, K(p), have been measured as a function of collector current for proton irradiations of 2N2222A (npn) and 2N2907A (pnp) switching transistors and 2N3055 (npn) power transistors over the energy range 5.0 to 60.3 MeV. The measurements of K(p) were made on specially selected lots of devices and were compared to values of the neutron damage factors, K(n), for 1-MeV displacement damage equivalent neutrons made on the same devices. The results show that, so far as device operation is concerned, the nature of the displacement damage produced by high energy protons and by fission neutrons is essentially the same. Over the energy range studied, protons were found to be more damaging than neutrons. For 5.0 MeV protons Kp/Kn was about 8.5 compared to about 1.8 for 60.3 MeV protons.

Vacuum-processed polyethylene as a dielectric for low operating voltage organic field effect transistors

PubMed Central

Kanbur, Yasin; Irimia-Vladu, Mihai; Głowacki, Eric D.; Voss, Gundula; Baumgartner, Melanie; Schwabegger, Günther; Leonat, Lucia; Ullah, Mujeeb; Sarica, Hizir; Erten-Ela, Sule; Schwödiauer, Reinhard; Sitter, Helmut; Küçükyavuz, Zuhal; Bauer, Siegfried; Sariciftci, Niyazi Serdar

2012-01-01

We report on the fabrication and performance of vacuum-processed organic field effect transistors utilizing evaporated low-density polyethylene (LD-PE) as a dielectric layer. With C60 as the organic semiconductor, we demonstrate low operating voltage transistors with field effect mobilities in excess of 4 cm2/Vs. Devices with pentacene showed a mobility of 0.16 cm2/Vs. Devices using tyrian Purple as semiconductor show low-voltage ambipolar operation with equal electron and hole mobilities of ∼0.3 cm2/Vs. These devices demonstrate low hysteresis and operational stability over at least several months. Grazing-angle infrared spectroscopy of evaporated thin films shows that the structure of the polyethylene is similar to solution-cast films. We report also on the morphological and dielectric properties of these films. Our experiments demonstrate that polyethylene is a stable dielectric supporting both hole and electron channels. PMID:23483783

Progress Towards High-Sensitivity Arrays of Detectors of Sub-mm Radiation Using Superconducting Tunnel Junctions with Integrated Radio Frequency Single-Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Prober, D. E.; Rhee, K. W.; Schoelkopf, R. J.; Stahle, C. M.; Teufel, J.; Wollack, E. J.

2004-01-01

For high resolution imaging and spectroscopy in the FIR and submillimeter, space observatories will demand sensitive, fast, compact, low-power detector arrays with 104 pixels and sensitivity less than 10(exp -20) W/Hz(sup 0.5). Antenna-coupled superconducting tunnel junctions with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique. The device consists of an antenna to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure current through junctions contacting the absorber. We describe optimization of device parameters, and results on fabrication techniques for producing devices with high yield for detector arrays. We also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.