Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lai, Hsin-Cheng; Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw; Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan

In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100 °C. The a-IGZO TFT exhibit a mobility of 5.13 cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4 mm (strain = 1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10 V for 1500 s. Thus, this technology ismore » suitable for use in flexible displays.« less

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics

DOE PAGES

Hong, Wen-Chiang; Ku, Chieh-Jen; Li, Rui; ...

2016-10-10

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. But, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. We designed devices with unique ring-type structures andmore » use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass.« less

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics.

PubMed

Hong, Wen-Chiang; Ku, Chieh-Jen; Li, Rui; Abbaslou, Siamak; Reyes, Pavel; Wang, Szu-Ying; Li, Guangyuan; Lu, Ming; Sheng, Kuang; Lu, Yicheng

2016-10-10

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. However, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. The devices are designed with unique ring-type structures and use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass.

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics

PubMed Central

Hong, Wen-Chiang; Ku, Chieh-Jen; Li, Rui; Abbaslou, Siamak; Reyes, Pavel; Wang, Szu-Ying; Li, Guangyuan; Lu, Ming; Sheng, Kuang; Lu, Yicheng

2016-01-01

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. However, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. The devices are designed with unique ring-type structures and use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass. PMID:27721484

Photo-Induced Room-Temperature Gas Sensing with a-IGZO Based Thin-Film Transistors Fabricated on Flexible Plastic Foil.

PubMed

Knobelspies, Stefan; Bierer, Benedikt; Daus, Alwin; Takabayashi, Alain; Salvatore, Giovanni Antonio; Cantarella, Giuseppe; Ortiz Perez, Alvaro; Wöllenstein, Jürgen; Palzer, Stefan; Tröster, Gerhard

2018-01-26

We present a gas sensitive thin-film transistor (TFT) based on an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) semiconductor as the sensing layer, which is fabricated on a free-standing flexible polyimide foil. The photo-induced sensor response to NO₂ gas at room temperature and the cross-sensitivity to humidity are investigated. We combine the advantages of a transistor based sensor with flexible electronics technology to demonstrate the first flexible a-IGZO based gas sensitive TFT. Since flexible plastic substrates prohibit the use of high operating temperatures, the charge generation is promoted with the help of UV-light absorption, which ultimately triggers the reversible chemical reaction with the trace gas. Furthermore, the device fabrication process flow can be directly implemented in standard TFT technology, allowing for the parallel integration of the sensor and analog or logical circuits.

Photo-Induced Room-Temperature Gas Sensing with a-IGZO Based Thin-Film Transistors Fabricated on Flexible Plastic Foil

PubMed Central

Bierer, Benedikt; Takabayashi, Alain; Ortiz Perez, Alvaro; Wöllenstein, Jürgen

2018-01-01

We present a gas sensitive thin-film transistor (TFT) based on an amorphous Indium–Gallium–Zinc–Oxide (a-IGZO) semiconductor as the sensing layer, which is fabricated on a free-standing flexible polyimide foil. The photo-induced sensor response to NO2 gas at room temperature and the cross-sensitivity to humidity are investigated. We combine the advantages of a transistor based sensor with flexible electronics technology to demonstrate the first flexible a-IGZO based gas sensitive TFT. Since flexible plastic substrates prohibit the use of high operating temperatures, the charge generation is promoted with the help of UV-light absorption, which ultimately triggers the reversible chemical reaction with the trace gas. Furthermore, the device fabrication process flow can be directly implemented in standard TFT technology, allowing for the parallel integration of the sensor and analog or logical circuits. PMID:29373524

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

PubMed

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Novel gallium nitride based microwave noise and power heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Chumbes, Eduardo Martin

With the pioneering efforts of Isamu Akasaki of Meiji University and Shuji Nakamura of Nichia Chemical Industries in the late 1980's and early 1990's, the first long-lived candela-class blue and ultraviolet light emitting devices have finally come to fruition. Their success in conquering this Holy Grail in opto-electronics is due to their development of a new technology based remarkably on a class of semiconductor materials that has been practically ignored and overlooked by almost everyone for the past twenty years---the nitrides of Al, Ga and In and their alloys. The breakthroughs made from this new technology in the last decade of the 20th century has revolutionized and revitalized worldwide research and development efforts to the point where it is feasible for other important technologies such as high-density information storage, high-resolution full-color displays and efficient white light lamps and UV sensors to come much closer to realization. Equally important is the potential that this new technology can bring toward the development of efficient ultra-high power and high-temperature electronics that will revolutionize the aerospace and high-speed communication industries. Specifically, the large bandgap and strong polar properties of the group III-nitrides has at present allowed for the realization of simple doped and remarkably undoped AlGaN/GaN transistor structures on sapphire and SiC substrates with two-dimensional electron gas sheet densities significantly greater than that of conventional transistor structures based on GaAs and InP. This dissertation will look specifically at extending undoped AlGaN/GaN heterostructure field-effect transistors or HFETs towards more advanced system applications involving the integration of these devices onto a more advanced Si technology and looking at the feasibility of this integration. It will also address important issues similar devices on semi-insulating SiC substrates have in robust microwave low noise and linear amplification. Finally, it will look at incorporating high-temperature silicon nitride passivation as a key ingredient to developing a unique class of devices: metal-insulator-semiconductor field effect transistors or MISFETs as a means for providing efficient high power amplification without compromising performance associated with surface- and process-related dispersion. This dissertation will finally close with a brief outlook on the future outlook of these technologies.

Solvent-Free Toner Printing of Organic Semiconductor Layer in Flexible Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Sakai, Masatoshi; Koh, Tokuyuki; Toyoshima, Kenji; Nakamori, Kouta; Okada, Yugo; Yamauchi, Hiroshi; Sadamitsu, Yuichi; Shinamura, Shoji; Kudo, Kazuhiro

2017-07-01

A solvent-free printing process for printed electronics is successfully developed using toner-type patterning of organic semiconductor toner particles and the subsequent thin-film formation. These processes use the same principle as that used for laser printing. The organic thin-film transistors are prepared by electrically distributing the charged toner onto a Au electrode on a substrate film, followed by thermal lamination. The thermal lamination is effective for obtaining an oriented and crystalline thin film. Toner printing is environmentally friendly compared with other printing technologies because it is solvent free, saves materials, and enables easy recycling. In addition, this technology simultaneously enables both wide-area and high-resolution printing.

Amorphous silicon thin film transistor active-matrix organic light-emitting diode displays fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Nichols, Jonathan A.

Organic light-emitting diode (OLED) displays are of immense interest because they have several advantages over liquid crystal displays, the current dominant flat panel display technology. OLED displays are emissive and therefore are brighter, have a larger viewing angle, and do not require backlights and filters, allowing thinner, lighter, and more power efficient displays. The goal of this work was to advance the state-of-the-art in active-matrix OLED display technology. First, hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) active-matrix OLED pixels and arrays were designed and fabricated on glass substrates. The devices operated at low voltages and demonstrated that lower performance TFTs could be utilized in active-matrix OLED displays, possibly allowing lower cost processing and the use of polymeric substrates. Attempts at designing more control into the display at the pixel level were also made. Bistable (one bit gray scale) active-matrix OLED pixels and arrays were designed and fabricated. Such pixels could be used in novel applications and eventually help reduce the bandwidth requirements in high-resolution and large-area displays. Finally, a-Si:H TFT active-matrix OLED pixels and arrays were fabricated on a polymeric substrate. Displays fabricated on a polymeric substrates would be lightweight; flexible, more rugged, and potentially less expensive to fabricate. Many of the difficulties associated with fabricating active-matrix backplanes on flexible substrates were studied and addressed.

Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers

NASA Astrophysics Data System (ADS)

Daugherty, Robin

This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10-100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.

An AlGaN/GaN high-electron-mobility transistor with an AlN sub-buffer layer

NASA Astrophysics Data System (ADS)

Shealy, J. R.; Kaper, V.; Tilak, V.; Prunty, T.; Smart, J. A.; Green, B.; Eastman, L. F.

2002-04-01

The AlGaN/GaN high-electron-mobility transistor requires a thermally conducting, semi-insulating substrate to achieve the best possible microwave performance. The semi-insulating SiC substrate is currently the best choice for this device technology; however, fringing fields which penetrate the GaN buffer layer at pinch-off introduce significant substrate conduction at modest drain bias if channel electrons are not well confined to the nitride structure. The addition of an insulating AlN sub-buffer on the semi-insulating SiC substrate suppresses this parasitic conduction, which results in dramatic improvements in the AlGaN/GaN transistor performance. A pronounced reduction in both the gate-lag and the gate-leakage current are observed for structures with the AlN sub-buffer layer. These structures operate up to 50 V drain bias under drive, corresponding to a peak voltage of 80 V, for a 0.30 µm gate length device. The devices have achieved high-efficiency operation at 10 GHz (>70% power-added efficiency in class AB mode at 15 V drain bias) and the highest output power density observed thus far (11.2 W mm-1). Large-periphery devices (1.5 mm gate width) deliver 10 W (continuous wave) of maximum saturated output power at 10 GHz. The growth, processing, and performance of these devices are briefly reviewed.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

FinFET and UTBB for RF SOI communication systems

NASA Astrophysics Data System (ADS)

Raskin, Jean-Pierre

2016-11-01

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Microwave flexible transistors on cellulose nanofibrillated fiber substrates

Treesearch

Jung-Hun Seo; Tzu-Hsuan Chang; Jaeseong Lee; Ronald Sabo; Weidong Zhou; Zhiyong Cai; Shaoqin Gong; Zhenqiang Ma

2015-01-01

In this paper, we demonstrate microwave flexible thin-film transistors (TFTs) on biodegradable substrates towards potential green portable devices. The combination of cellulose nanofibrillated fiber (CNF) substrate, which is a biobased and biodegradable platform, with transferrable single crystalline Si nanomembrane (Si NM), enables the realization of truly...

Transparent active matrix organic light-emitting diode displays driven by nanowire transistor circuitry.

PubMed

Ju, Sanghyun; Li, Jianfeng; Liu, Jun; Chen, Po-Chiang; Ha, Young-Geun; Ishikawa, Fumiaki; Chang, Hsiaokang; Zhou, Chongwu; Facchetti, Antonio; Janes, David B; Marks, Tobin J

2008-04-01

Optically transparent, mechanically flexible displays are attractive for next-generation visual technologies and portable electronics. In principle, organic light-emitting diodes (OLEDs) satisfy key requirements for this application-transparency, lightweight, flexibility, and low-temperature fabrication. However, to realize transparent, flexible active-matrix OLED (AMOLED) displays requires suitable thin-film transistor (TFT) drive electronics. Nanowire transistors (NWTs) are ideal candidates for this role due to their outstanding electrical characteristics, potential for compact size, fast switching, low-temperature fabrication, and transparency. Here we report the first demonstration of AMOLED displays driven exclusively by NW electronics and show that such displays can be optically transparent. The displays use pixel dimensions suitable for hand-held applications, exhibit 300 cd/m2 brightness, and are fabricated at temperatures suitable for integration on plastic substrates.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

1.55 Micrometer Sub-Micron Finger, Interdigitated MSM Photodetector Arrays with Low Dark Current

DTIC Science & Technology

2010-02-02

pf a- IGZO TFTs. IV. RF Characteristics of Room Temperature Deposited Indium Zinc Oxide Thin - Film Transistors Depletion-mode indium zinc...III. High Performance Indium Gallium Zinc Oxide Thin Film Transistors Fabricated On Polyethylene Terephthalate Substrates High-performance...amorphous (a-) InGaZnO-based thin film transistors (TFTs) were fabricated on flexible polyethylene terephthalate (PET) substrates coated with indium

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

2002-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

PubMed

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

DOEpatents

Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

2016-03-29

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

Inverter circuits on freestanding flexible substrate using ZnO nanoparticles for cost-efficient electronics

NASA Astrophysics Data System (ADS)

Vidor, Fábio F.; Meyers, Thorsten; Müller, Kathrin; Wirth, Gilson I.; Hilleringmann, Ulrich

2017-11-01

Driven by the Internet of Things (IoT), flexible and transparent smart systems have been intensively researched by the scientific community and by several companies. This technology is already available for consumers in a wide range of innovative products, e.g., flexible displays, radio-frequency identification tags and wearable electronic skins which, for instance, collect and analyze data for medical applications. For these systems, thin-film transistors (TFTs) are the key elements responsible for the driving currents. Solution-based materials such as nanoparticle dispersions avail the fabrication on large-area substrates with high throughput processes. In this study, we discuss the integration of ZnO nanoparticle thin-film transistors and inverter circuits on freestanding polymeric substrates enclosing the main issues concerning the transfer of the integration process from a rigid substrate to a flexible one. The TFTs depict VON between -0.2 and 1 V, ION/IOFF > 104 and field-effect mobility >0.5 cm2 V-1 s-1. Additionally, in order to enhance the transistors and inverters performance, an adaptation on the device configuration, from an inverted coplanar to an inverted staggered setup, was conducted and analyzed. By employing the inverted staggered setup a considerable increase in the contact quality between the semiconductor and the drain and source electrodes was observed. As the integrated devices depict electrical characteristics which enable the fabrication of electronic circuits for the low-cost sector, inverters were fabricated and characterized, evaluating the circuit's gain as function of the applied supply voltage and circuit's geometric ratio.

Maskless writing of a flexible nanoscale transistor with Au-contacted carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Dockendorf, Cedric P. R.; Poulikakos, Dimos; Hwang, Gilgueng; Nelson, Bradley J.; Grigoropoulos, Costas P.

2007-12-01

A flexible polymer field effect transistor with a nanoscale carbon nanotube channel is conceptualized and realized herein. Carbon nanotubes (CNTs) were dispersed on a polyimide substrate and marked in an scanning electron microscope with focused ion beam such that they could be contacted with gold nanoink. The CNTs were divided into two parts forming the source and drain of the transistor. A micropipette writing method was used to contact the carbon nanotube electrodes with gold nanoink and to deposit the poly(3-hexylthiophene) as an active layer. The mobility of the transistors is of the order of 10-5cm/Vs. After fabrication, the flexible transistors can be peeled off the substrate.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

Flexible graphene transistors for recording cell action potentials

NASA Astrophysics Data System (ADS)

Blaschke, Benno M.; Lottner, Martin; Drieschner, Simon; Bonaccini Calia, Andrea; Stoiber, Karolina; Rousseau, Lionel; Lissourges, Gaëlle; Garrido, Jose A.

2016-06-01

Graphene solution-gated field-effect transistors (SGFETs) are a promising platform for the recording of cell action potentials due to the intrinsic high signal amplification of graphene transistors. In addition, graphene technology fulfills important key requirements for in-vivo applications, such as biocompability, mechanical flexibility, as well as ease of high density integration. In this paper we demonstrate the fabrication of flexible arrays of graphene SGFETs on polyimide, a biocompatible polymeric substrate. We investigate the transistor’s transconductance and intrinsic electronic noise which are key parameters for the device sensitivity, confirming that the obtained values are comparable to those of rigid graphene SGFETs. Furthermore, we show that the devices do not degrade during repeated bending and the transconductance, governed by the electronic properties of graphene, is unaffected by bending. After cell culture, we demonstrate the recording of cell action potentials from cardiomyocyte-like cells with a high signal-to-noise ratio that is higher or comparable to competing state of the art technologies. Our results highlight the great capabilities of flexible graphene SGFETs in bioelectronics, providing a solid foundation for in-vivo experiments and, eventually, for graphene-based neuroprosthetics.

Biodegradable elastomers and silicon nanomembranes/nanoribbons for stretchable, transient electronics, and biosensors.

PubMed

Hwang, Suk-Won; Lee, Chi Hwan; Cheng, Huanyu; Jeong, Jae-Woong; Kang, Seung-Kyun; Kim, Jae-Hwan; Shin, Jiho; Yang, Jian; Liu, Zhuangjian; Ameer, Guillermo A; Huang, Yonggang; Rogers, John A

2015-05-13

Transient electronics represents an emerging class of technology that exploits materials and/or device constructs that are capable of physically disappearing or disintegrating in a controlled manner at programmed rates or times. Inorganic semiconductor nanomaterials such as silicon nanomembranes/nanoribbons provide attractive choices for active elements in transistors, diodes and other essential components of overall systems that dissolve completely by hydrolysis in biofluids or groundwater. We describe here materials, mechanics, and design layouts to achieve this type of technology in stretchable configurations with biodegradable elastomers for substrate/encapsulation layers. Experimental and theoretical results illuminate the mechanical properties under large strain deformation. Circuit characterization of complementary metal-oxide-semiconductor inverters and individual transistors under various levels of applied loads validates the design strategies. Examples of biosensors demonstrate possibilities for stretchable, transient devices in biomedical applications.

An Al2O3 Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials

PubMed Central

Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Zhang, Xueao

2017-01-01

We fabricated 70 nm Al2O3 gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al2O3/Si substrate is superior to that on a traditional 300 nm SiO2/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al2O3/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS2, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices. PMID:28937619

Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors

NASA Astrophysics Data System (ADS)

Sun, Xiao

As the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology. In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT). By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed. The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.

Radiation tolerant back biased CMOS VLSI

NASA Technical Reports Server (NTRS)

Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

2003-01-01

A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

Low-voltage self-assembled monolayer field-effect transistors on flexible substrates.

PubMed

Schmaltz, Thomas; Amin, Atefeh Y; Khassanov, Artoem; Meyer-Friedrichsen, Timo; Steinrück, Hans-Georg; Magerl, Andreas; Segura, Juan José; Voitchovsky, Kislon; Stellacci, Francesco; Halik, Marcus

2013-08-27

Self-assembled monolayer field-effect transistors (SAMFETs) of BTBT functionalized phosphonic acids are fabricated. The molecular design enables device operation with charge carrier mobilities up to 10(-2) cm(2) V(-1) s(-1) and for the first time SAMFETs which operate on rough, flexible PEN substrates even under mechanical substrate bending. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Mechanically adjustable single-molecule transistors and stencil mask nanofabrication of high-resolution scanning probes

NASA Astrophysics Data System (ADS)

Champagne, Alexandre

This dissertation presents the development of two original experimental techniques to probe nanoscale objects. The first one studies electronic transport in single organic molecule transistors in which the source-drain electrode spacing is mechanically adjustable. The second involves the fabrication of high-resolution scanning probe microscopy sensors using a stencil mask lithography technique. We describe the fabrication of transistors in which a single organic molecule can be incorporated. The source and drain leads of these transistors are freely suspended above a flexible substrate, and their spacing can be adjusted by bending the substrate. We detail the technology developed to carry out measurements on these samples. We study electronic transport in single C60 molecules at low temperature. We observe Coulomb blockaded transport and can resolve the discrete energy spectrum of the molecule. We are able to mechanically tune the spacing between the electrodes (over a range of 5 A) to modulate the lead-molecule coupling, and can electrostatically tune the energy levels on the molecule by up to 160 meV using a gate electrode. Initial progress in studying different transport regimes in other molecules is also discussed. We present a lithographic process that allows the deposition of metal nanostructures with a resolution down to 10 nm directly onto atomic force microscope (AFM) tips. We show that multiple layers of lithography can be deposited and aligned. We fabricate high-resolution magnetic force microscopy (MFM) probes using this method and discuss progress to fabricate other scanning probe microscopy (SPM) sensors.

Graphene Exfoliation at a Ferroelectric Domain Wall Induced by the Piezoelectric Effect: Impact on the Conductance of the Graphene Channel

NASA Astrophysics Data System (ADS)

Morozovska, Anna N.; Kurchak, Anatolii I.; Strikha, Maksym V.

2017-11-01

p -n junctions in graphene on ferroelectric substrates have been actively studied, but the impact of the piezoelectric effect in ferroelectric substrate with ferroelectric domain walls (FDWs) on graphene characteristics was not considered. Because of the piezoeffect, ferroelectric domain stripes with opposite spontaneous polarizations elongate or contract depending on the polarity of voltage applied to the substrate. We show that the alternating piezoelectric displacement of the ferroelectric domain surfaces can lead to the alternate stretching and separation of graphene areas at the steps between elongated and contracted domains. Graphene separation at FDWs induced by the piezoeffect can cause unusual effects. In particular, the conductance of the graphene channel in a field-effect transistor increases significantly because electrons in the stretched section scatter on acoustic phonons. At the same time, the graphene conductance is determined by ferroelectric spontaneous polarization and varies greatly in the presence of FDWs. The revealed piezomechanism of graphene conductance control is promising for next generations of graphene-based field-effect transistors, modulators, electrical transducers, and piezoresistive elements. Also, our results propose the method of suspended graphene fabrication based on the piezoeffect in a ferroelectric substrate that does not require any additional technological procedures.

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Silicon thin-film transistor backplanes on flexible substrates

NASA Astrophysics Data System (ADS)

Kattamis, Alexis Z.

Flexible large area electronics, especially for displays, is a rapidly growing field. Since hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have become the industry standard for liquid crystal displays, it makes sense that they be used in any transition from glass substrates to flexible substrates. The goal of this thesis work was to implement a-Si:H backplane technology on stainless steel and clear plastic substrates, with minimal recipe changes to ensure high device quality. When fabricating TFTs on flexible substrates many new issues arise, from thin-film fracture to overlay alignment errors. Our approach was to maintain elevated deposition temperatures (˜300°C) and engineer methods to minimize these problems, rather than reducing deposition temperatures. The resulting TFTs exhibit more stable operation than their low temperature counterparts and are therefore similar to the TFTs produced on glass. Two display projects using a-Si:H TFTs will be discussed in detail. They are an active-matrix organic light emitting display (AMOLED) on stainless steel and an active-matrix electrophoretic display (AMEPD) on clear plastic, with TFTs deposited at 250°C-280°C. Achieving quality a-Si:H TFTs on these substrates required addressing a host of technical challenges, including surface roughness and feature misalignment. Nanocrystalline silicon (nc-Si) was also implemented on a clear plastic substrate as a possible alternative to a-Si:H. nc-Si:H TFTs can be deposited using the same techniques as a-Si:H but yield carrier mobilities one order of magnitude greater. Their large mobilities could enable high resolution OLED displays and system-on-panel electronics.

Organic thin film transistor with a simplified planar structure

NASA Astrophysics Data System (ADS)

Zhang, Lei; Yu, Jungsheng; Zhong, Jian; Jiang, Yadong

2009-05-01

Organic thin film transistor (OTFT) with a simplified planar structure is described. The gate electrode and the source/drain electrodes of OTFT are processed in one planar structure. And these three electrodes are deposited on the glass substrate by DC sputtering technology using Cr/Ni target. Then the electrode layouts of different width length ratio are made by photolithography technology at the same time. Only one step of deposition and one step of photolithography is needed while conventional process takes at least two steps of deposition and two steps of photolithography. Metal is first prepared on the other side of glass substrate and electrode is formed by photolithography. Then source/drain electrode is prepared by deposition and photolithography on the side with the insulation layer. Compared to conventional process of OTFTs, the process in this work is simplified. After three electrodes prepared, the insulation layer is made by spin coating method. The organic material of polyimide is used as the insulation layer. A small molecular material of pentacene is evaporated on the insulation layer using vacuum deposition as the active layer. The process of OTFTs needs only three steps totally. A semi-auto probe stage is used to connect the three electrodes and the probe of the test instrument. A charge carrier mobility of 0.3 cm2 /V s, is obtained from OTFTs on glass substrates with and on/off current ratio of 105. The OTFTs with the planar structure using simplified process can simplify the device process and reduce the fabrication cost.

All diamond self-aligned thin film transistor

DOEpatents

Gerbi, Jennifer [Champaign, IL

2008-07-01

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

NASA Astrophysics Data System (ADS)

Chen, Jone F.; Tsai, Yen-Lin; Chen, Chun-Yen; Hsu, Hao-Tang; Kao, Chia-Yu; Hwang, Hann-Ping

2018-04-01

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

Stretchable metal oxide thin film transistors on engineered substrate for electronic skin applications.

PubMed

Romeo, Alessia; Lacour, Stphanie P

2015-08-01

Electronic skins aim at providing distributed sensing and computation in a large-area and elastic membrane. Control and addressing of high-density soft sensors will be achieved when thin film transistor matrices are also integrated in the soft carrier substrate. Here, we report on the design, manufacturing and characterization of metal oxide thin film transistors on these stretchable substrates. The TFTs are integrated onto an engineered silicone substrate with embedded strain relief to protect the devices from catastrophic cracking. The TFT stack is composed of an amorphous In-Ga-Zn-O active layer, a hybrid AlxOy/Parylene dielectric film, gold electrodes and interconnects. All layers are prepared and patterned with planar, low temperature and dry processing. We demonstrate the interconnected IGZO TFTs sustain applied tensile strain up to 20% without electrical degradation and mechanical fracture. Active devices are critical for distributed sensing. The compatibility of IGZO TFTs with soft and biocompatible substrates is an encouraging step towards wearable electronic skins.

Chemical-free n-type and p-type multilayer-graphene transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dissanayake, D. M. N. M., E-mail: nandithad@voxtel-inc.com; Eisaman, M. D.; Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, New York 11794

A single-step doping method to fabricate n- and p-type multilayer graphene (MG) top-gate field effect transistors (GFETs) is demonstrated. The transistors are fabricated on soda-lime glass substrates, with the n-type doping of MG caused by the sodium in the substrate without the addition of external chemicals. Placing a hydrogen silsesquioxane (HSQ) barrier layer between the MG and the substrate blocks the n-doping, resulting in p-type doping of the MG above regions patterned with HSQ. The HSQ is deposited in a single fabrication step using electron beam lithography, allowing the patterning of arbitrary sub-micron spatial patterns of n- and p-type doping.more » When a MG channel is deposited partially on the barrier and partially on the glass substrate, a p-type and n-type doping profile is created, which is used for fabricating complementary transistors pairs. Unlike chemically doped GFETs in which the external dopants are typically introduced from the top, these substrate doped GFETs allow for a top gate which gives a stronger electrostatic coupling to the channel, reducing the operating gate bias. Overall, this method enables scalable fabrication of n- and p-type complementary top-gated GFETs with high spatial resolution for graphene microelectronic applications.« less

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

PubMed

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

The analysis of ion-selective field-effect transistor operation in chemical sensors

NASA Astrophysics Data System (ADS)

Hotra, Zenon; Holyaka, Roman; Hladun, Michael; Humenuk, Iryna

2003-09-01

In this paper we present the research results of influence of substrate potential in ion-selective field-effect transistors (ISFET) on output signal of chemical sensors, e.g. PH-meters. It is shown that the instability of substrate-source p-n junction bias in well-known chemical sensors, which use grounded reference electrode - ISFET gate, affect on sensor characteristics in negative way. The analytical description and research results of 'substrate effect' on ISFET characteristics are considered.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

Fabrication and characterization on reduced graphene oxide field effect transistor (RGOFET) based biosensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rashid, A. Diyana; Ruslinda, A. Rahim, E-mail: ruslinda@unimap.edu.my; Fatin, M. F.

2016-07-06

The fabrication and characterization on reduced graphene oxide field effect transistor (RGO-FET) were demonstrated using a spray deposition method for biological sensing device purpose. A spray method is a fast, low-cost and simple technique to deposit graphene and the most promising technology due to ideal coating on variety of substrates and high production speed. The fabrication method was demonstrated for developing a label free aptamer reduced graphene oxide field effect transistor biosensor. Reduced graphene oxide (RGO) was obtained by heating on hot plate fixed at various temperatures of 100, 200 and 300°C, respectively. The surface morphology of RGO were examinedmore » via atomic force microscopy to observed the temperature effect of produced RGO. The electrical measurement verify the performance of electrical conducting RGO-FET at temperature 300°C is better as compared to other temperature due to the removal of oxygen groups in GO. Thus, reduced graphene oxide was a promising material for biosensor application.« less

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

NASA Astrophysics Data System (ADS)

Petti, Luisa; Pattanasattayavong, Pichaya; Lin, Yen-Hung; Münzenrieder, Niko; Cantarella, Giuseppe; Yaacobi-Gross, Nir; Yan, Feng; Tröster, Gerhard; Anthopoulos, Thomas D.

2017-03-01

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V-1 s-1 and 0.013 cm2 V-1 s-1, respectively, current on/off ratio in the range 102-104, and maximum operating voltages between -3.5 and -10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as -3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

A stable solution-processed polymer semiconductor with record high-mobility for printed transistors

PubMed Central

Li, Jun; Zhao, Yan; Tan, Huei Shuan; Guo, Yunlong; Di, Chong-An; Yu, Gui; Liu, Yunqi; Lin, Ming; Lim, Suo Hon; Zhou, Yuhua; Su, Haibin; Ong, Beng S.

2012-01-01

Microelectronic circuits/arrays produced via high-speed printing instead of traditional photolithographic processes offer an appealing approach to creating the long-sought after, low-cost, large-area flexible electronics. Foremost among critical enablers to propel this paradigm shift in manufacturing is a stable, solution-processable, high-performance semiconductor for printing functionally capable thin-film transistors — fundamental building blocks of microelectronics. We report herein the processing and optimisation of solution-processable polymer semiconductors for thin-film transistors, demonstrating very high field-effect mobility, high on/off ratio, and excellent shelf-life and operating stabilities under ambient conditions. Exceptionally high-gain inverters and functional ring oscillator devices on flexible substrates have been demonstrated. This optimised polymer semiconductor represents a significant progress in semiconductor development, dispelling prevalent skepticism surrounding practical usability of organic semiconductors for high-performance microelectronic devices, opening up application opportunities hitherto functionally or economically inaccessible with silicon technologies, and providing an excellent structural framework for fundamental studies of charge transport in organic systems. PMID:23082244

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Coaxial inverted geometry transistor having buried emitter

NASA Technical Reports Server (NTRS)

Hruby, R. J.; Cress, S. B.; Dunn, W. R. (Inventor)

1973-01-01

The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Flexible thin-film transistors on plastic substrate at room temperature.

PubMed

Han, Dedong; Wang, Wei; Cai, Jian; Wang, Liangliang; Ren, Yicheng; Wang, Yi; Zhang, Shengdong

2013-07-01

We have fabricated flexible thin-film transistors (TFTs) on plastic substrates using Aluminum-doped ZnO (AZO) as an active channel layer at room temperature. The AZO-TFTs showed n-channel device characteristics and operated in enhancement mode. The device shows a threshold voltage of 1.3 V, an on/off ratio of 2.7 x 10(7), a field effect mobility of 21.3 cm2/V x s, a subthreshold swing of 0.23 V/decade, and the off current of less than 10(-12) A at room temperature. Recently, the flexible displays have become a very hot topic. Flexible thin film transistors are key devices for realizing flexible displays. We have investigated AZO-TFT on flexible plastic substrate, and high performance flexible TFTs have been obtained.

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

High Resolution Adjustable Mirror Control for X-ray Astronomy

NASA Astrophysics Data System (ADS)

Trolier-McKinstry, Susan

We propose to build and test thin film transistor control circuitry for a new highresolution adjustable X-ray mirror technology. This control circuitry will greatly simplify the wiring scheme to address individual actuator cells. The result will be a transformative improvement for the X-ray Surveyor mission concept: mathematical models, which fit the experimental data quite well, indicate that 0.5 arcsecond imaging is feasible through this technique utilizing thin slumped glass substrates with uncorrected angular resolution of order 5-10 arcseconds. In order to correct for figures errors in a telescope with several square meters of collecting area, millions of actuator cells must be set and held at specific voltages. It is clearly not feasible to do this via millions of wires, each one connected to an actuator. Instead, we propose to develop and test thin-film technology that operates on the same principle as megapixel computer screens. We will develop the technologies needed to build thin film piezoelectric actuators, controlled by thin film ZnO transistors, on flexible polyimide films, and to connect those films to the back surfaces of X-ray mirrors on thin glass substrates without deforming the surface. These technologies represent a promising avenue of the development of mirrors for the X-Ray Surveyor mission concept. Such a telescope will make possible detailed studies of a wide variety of astrophysical sources. One example is the Warm-Hot Intergalactic Medium (WHIM), which is thought to account for a large fraction of the normal matter in the universe but which has not been detected unambiguously to date. Another is the growth of supermassive black holes in the early universe. This proposal supports NASA's goals of technical advancement of technologies suitable for future missions, and training of graduate students.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Advances in maskless and mask-based optical lithography on plastic flexible substrates

NASA Astrophysics Data System (ADS)

Barbu, Ionut; Ivan, Marius G.; Giesen, Peter; Van de Moosdijk, Michel; Meinders, Erwin R.

2009-12-01

Organic flexible electronics is an emerging technology with huge potential growth in the future which is likely to open up a complete new series of potential applications such as flexible OLED-based displays, urban commercial signage, and flexible electronic paper. The transistor is the fundamental building block of all these applications. A key challenge in patterning transistors on flexible plastic substrates stems from the in-plane nonlinear deformations as a consequence of foil expansion/shrinkage, moisture uptake, baking etc. during various processing steps. Optical maskless lithography is one of the potential candidates for compensating for these foil distortions by in-situ adjustment prior to exposure of the new layer image with respect to the already patterned layers. Maskless lithography also brings the added value of reducing the cost-of-ownership related to traditional mask-based tools by eliminating the need for expensive masks. For the purpose of this paper, single-layer maskless exposures at 355 nm were performed on gold-coated poly(ethylenenaphthalate) (PEN) flexible substrates temporarily attached to rigid carriers to ensure dimensional stability during processing. Two positive photoresists were employed for this study and the results on plastic foils were benchmarked against maskless as well as mask-based (ASML PAS 5500/100D stepper) exposures on silicon wafers.

Materials for Stretchable Electronics - Electronic Eyeballs, Brain Monitors and Other Applications

ScienceCinema

Rogers, John A. [University of Illinois, Urbana Champaign, Illinois, United States

2017-12-09

Electronic circuits that involve transistors and related components on thin plastic sheets or rubber slabs offer mechanical properties (e.g. bendability, stretchability) and other features (e.g. lightweight, rugged construction) which cannot be easily achieved with technologies that use rigid, fragile semiconductor wafer or glass substrates.  Device examples include personal or structural health monitors and electronic eye imagers, in which the electronics must conform to complex curvilinear shapes or flex/stretch during use.  Our recent work accomplishes these technology outcomes by use of single crystal inorganic nanomaterials in ‘wavy’ buckled configurations on elastomeric supports.  This talk will describe key fundamental materials and mechanics aspects of these approaches, as well as engineering features of their use in individual transistors, photodiodes and integrated circuits.  Cardiac and brain monitoring devices provide examples of application in biomedicine; hemispherical electronic eye cameras illustrate new capacities for bio-inspired device design.

Separated carbon nanotube macroelectronics for active matrix organic light-emitting diode displays.

PubMed

Zhang, Jialu; Fu, Yue; Wang, Chuan; Chen, Po-Chiang; Liu, Zhiwei; Wei, Wei; Wu, Chao; Thompson, Mark E; Zhou, Chongwu

2011-11-09

Active matrix organic light-emitting diode (AMOLED) display holds great potential for the next generation visual technologies due to its high light efficiency, flexibility, lightweight, and low-temperature processing. However, suitable thin-film transistors (TFTs) are required to realize the advantages of AMOLED. Preseparated, semiconducting enriched carbon nanotubes are excellent candidates for this purpose because of their excellent mobility, high percentage of semiconducting nanotubes, and room-temperature processing compatibility. Here we report, for the first time, the demonstration of AMOLED displays driven by separated nanotube thin-film transistors (SN-TFTs) including key technology components, such as large-scale high-yield fabrication of devices with superior performance, carbon nanotube film density optimization, bilayer gate dielectric for improved substrate adhesion to the deposited nanotube film, and the demonstration of monolithically integrated AMOLED display elements with 500 pixels driven by 1000 SN-TFTs. Our approach can serve as the critical foundation for future nanotube-based thin-film display electronics.

Separated Carbon Nanotube Macroelectronics for Active Matrix Organic Light-Emitting Diode Displays

NASA Astrophysics Data System (ADS)

Fu, Yue; Zhang, Jialu; Wang, Chuan; Chen, Pochiang; Zhou, Chongwu

2012-02-01

Active matrix organic light-emitting diode (AMOLED) display holds great potential for the next generation visual technologies due to its high light efficiency, flexibility, lightweight, and low-temperature processing. However, suitable thin-film transistors (TFTs) are required to realize the advantages of AMOLED. Pre-separated, semiconducting enriched carbon nanotubes are excellent candidates for this purpose because of their excellent mobility, high percentage of semiconducting nanotubes, and room-temperature processing compatibility. Here we report, for the first time, the demonstration of AMOLED displays driven by separated nanotube thin-film transistors (SN-TFTs) including key technology components such as large-scale high-yield fabrication of devices with superior performance, carbon nanotube film density optimization, bilayer gate dielectric for improved substrate adhesion to the deposited nanotube film, and the demonstration of monolithically integrated AMOLED display elements with 500 pixels driven by 1000 SN-TFTs. Our approach can serve as the critical foundation for future nanotube-based thin-film display electronics.

Producing smart sensing films by means of organic field effect transistors.

PubMed

Manunza, Ileana; Orgiu, Emanuele; Caboni, Alessandra; Barbaro, Massimo; Bonfiglio, Annalisa

2006-01-01

We have fabricated the first example of totally flexible field effect device for chemical detection based on an organic field effect transistor (OFET) made by pentacene films grown on flexible plastic structures. The ion sensitivity is achieved by employing a thin Mylar foil as gate dielectric. A sensitivity of the device to the pH of the electrolyte solution has been observed A similar structure can be used also for detecting mechanical deformations on flexible surfaces. Thanks to the flexibility of the substrate and the low cost of the employed technology, these devices open the way for the production of flexible chemical and strain gauge sensors that can be employed in a variety of innovative applications such as wearable electronics, e-textiles, new man-machine interfaces.

OP-AMPS on Flexible Substrates with Printable Materials

DTIC Science & Technology

2011-08-10

Zinc Tin Oxide Thin - Film - Transistor Enhancement...II196, 2010. [3] D. Geng, D. H. Kang, and J. Jang, "High-Performance Amorphous Indium-Gallium- Zinc - Oxide Thin - Film Transistor With a Self-Aligned...B., Dodabalapur, A., “Band transport and mobility edge in amorphous solution-processed zinc tin oxide thin - film transistors ”, Applied

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

PubMed

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

An ultra-lightweight design for imperceptible plastic electronics.

PubMed

Kaltenbrunner, Martin; Sekitani, Tsuyoshi; Reeder, Jonathan; Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Drack, Michael; Schwödiauer, Reinhard; Graz, Ingrid; Bauer-Gogonea, Simona; Bauer, Siegfried; Someya, Takao

2013-07-25

Electronic devices have advanced from their heavy, bulky origins to become smart, mobile appliances. Nevertheless, they remain rigid, which precludes their intimate integration into everyday life. Flexible, textile and stretchable electronics are emerging research areas and may yield mainstream technologies. Rollable and unbreakable backplanes with amorphous silicon field-effect transistors on steel substrates only 3 μm thick have been demonstrated. On polymer substrates, bending radii of 0.1 mm have been achieved in flexible electronic devices. Concurrently, the need for compliant electronics that can not only be flexed but also conform to three-dimensional shapes has emerged. Approaches include the transfer of ultrathin polyimide layers encapsulating silicon CMOS circuits onto pre-stretched elastomers, the use of conductive elastomers integrated with organic field-effect transistors (OFETs) on polyimide islands, and fabrication of OFETs and gold interconnects on elastic substrates to realize pressure, temperature and optical sensors. Here we present a platform that makes electronics both virtually unbreakable and imperceptible. Fabricated directly on ultrathin (1 μm) polymer foils, our electronic circuits are light (3 g m(-2)) and ultraflexible and conform to their ambient, dynamic environment. Organic transistors with an ultra-dense oxide gate dielectric a few nanometres thick formed at room temperature enable sophisticated large-area electronic foils with unprecedented mechanical and environmental stability: they withstand repeated bending to radii of 5 μm and less, can be crumpled like paper, accommodate stretching up to 230% on prestrained elastomers, and can be operated at high temperatures and in aqueous environments. Because manufacturing costs of organic electronics are potentially low, imperceptible electronic foils may be as common in the future as plastic wrap is today. Applications include matrix-addressed tactile sensor foils for health care and monitoring, thin-film heaters, temperature and infrared sensors, displays, and organic solar cells.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.

Metal Oxide Thin Film Transistors on Paper Substrate: Fabrication, Characterization, and Printing Process

NASA Astrophysics Data System (ADS)

Choi, Nack-Bong

Flexible electronics is an emerging next-generation technology that offers many advantages such as light weight, durability, comfort, and flexibility. These unique features enable many new applications such as flexible display, flexible sensors, conformable electronics, and so forth. For decades, a variety of flexible substrates have been demonstrated for the application of flexible electronics. Most of them are plastic films and metal foils so far. For the fundamental device of flexible circuits, thin film transistors (TFTs) using poly silicon, amorphous silicon, metal oxide and organic semiconductor have been successfully demonstrated. Depending on application, low-cost and disposable flexible electronics will be required for convenience. Therefore it is important to study inexpensive substrates and to explore simple processes such as printing technology. In this thesis, paper is introduced as a new possible substrate for flexible electronics due to its low-cost and renewable property, and amorphous indium gallium zinc oxide (a-IGZO) TFTs are realized as the promising device on the paper substrate. The fabrication process and characterization of a-IGZO TFT on the paper substrate are discussed. a-IGZO TFTs using a polymer gate dielectric on the paper substrate demonstrate excellent performances with field effect mobility of ˜20 cm2 V-1 s-1, on/off current ratio of ˜106, and low leakage current, which show the enormous potential for flexible electronics application. In order to complement the n-channel a-IGZO TFTs and then enable complementary metal-oxide semiconductor (CMOS) circuit architectures, cuprous oxide is studied as a candidate material of p-channel oxide TFTs. In this thesis, a printing process is investigated as an alternative method for the fabrication of low-cost and disposable electronics. Among several printing methods, a modified offset roll printing that prints high resolution patterns is presented. A new method to fabricate a high resolution printing plate is investigated and the most favorable condition to transfer ink from a blanket to a cliche is studied. Consequently, a high resolution cliche is demonstrated and the printed patterns of 10mum width and 6mum line spacing are presented. In addition, the top gate a-IGZO TFTs with channel width/length of 12/6mum is successfully demonstrated by printing etch-resists. This work validates the compatibility of a-IGZO TFT on paper substrate for the disposable microelectronics application and presents the potential of low-cost and high resolution printing technology.

Transferred substrate heterojunction bipolar transistors for submillimeter wave applications

NASA Technical Reports Server (NTRS)

Fung, A.; Samoska, L.; Siegel, P.; Rodwell, M.; Urteaga, M.; Paidi, V.

2003-01-01

We present ongoing work towards the development of submillimeter wave transistors with goals of realizing advanced high frequency amplifiers, voltage controlled oscillators, active multipliers, and traditional high-speed digital circuits.

Method of fabrication of display pixels driven by silicon thin film transistors

DOEpatents

Carey, Paul G.; Smith, Patrick M.

1999-01-01

Display pixels driven by silicon thin film transistors are fabricated on plastic substrates for use in active matrix displays, such as flat panel displays. The process for forming the pixels involves a prior method for forming individual silicon thin film transistors on low-temperature plastic substrates. Low-temperature substrates are generally considered as being incapable of withstanding sustained processing temperatures greater than about 200.degree. C. The pixel formation process results in a complete pixel and active matrix pixel array. A pixel (or picture element) in an active matrix display consists of a silicon thin film transistor (TFT) and a large electrode, which may control a liquid crystal light valve, an emissive material (such as a light emitting diode or LED), or some other light emitting or attenuating material. The pixels can be connected in arrays wherein rows of pixels contain common gate electrodes and columns of pixels contain common drain electrodes. The source electrode of each pixel TFT is connected to its pixel electrode, and is electrically isolated from every other circuit element in the pixel array.

Paper-like electronic displays: Large-area rubber-stamped plastic sheets of electronics and microencapsulated electrophoretic inks

PubMed Central

Rogers, John A.; Bao, Zhenan; Baldwin, Kirk; Dodabalapur, Ananth; Crone, Brian; Raju, V. R.; Kuck, Valerie; Katz, Howard; Amundson, Karl; Ewing, Jay; Drzaic, Paul

2001-01-01

Electronic systems that use rugged lightweight plastics potentially offer attractive characteristics (low-cost processing, mechanical flexibility, large area coverage, etc.) that are not easily achieved with established silicon technologies. This paper summarizes work that demonstrates many of these characteristics in a realistic system: organic active matrix backplane circuits (256 transistors) for large (≈5 × 5-inch) mechanically flexible sheets of electronic paper, an emerging type of display. The success of this effort relies on new or improved processing techniques and materials for plastic electronics, including methods for (i) rubber stamping (microcontact printing) high-resolution (≈1 μm) circuits with low levels of defects and good registration over large areas, (ii) achieving low leakage with thin dielectrics deposited onto surfaces with relief, (iii) constructing high-performance organic transistors with bottom contact geometries, (iv) encapsulating these transistors, (v) depositing, in a repeatable way, organic semiconductors with uniform electrical characteristics over large areas, and (vi) low-temperature (≈100°C) annealing to increase the on/off ratios of the transistors and to improve the uniformity of their characteristics. The sophistication and flexibility of the patterning procedures, high level of integration on plastic substrates, large area coverage, and good performance of the transistors are all important features of this work. We successfully integrate these circuits with microencapsulated electrophoretic “inks” to form sheets of electronic paper. PMID:11320233

Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube Networks for Digital, Analog, and Radio-Frequency Applications

DTIC Science & Technology

2012-02-07

circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The asobtained thin-film transistors ( TFTs ) exhibit... flexible substrates for digital, analog and radio frequency applications. The as- obtained thin-film transistors ( TFTs ) exhibit highly uniform device...LCD) and organic light- emitting diode ( OLED ) displays lack the transparency and flexibility and are thus unsuitable for flexible electronic

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Electrical and mechanical characteristics of fully transparent IZO thin-film transistors on stress-relieving bendable substrates

NASA Astrophysics Data System (ADS)

Park, Sukhyung; Cho, Kyoungah; Oh, Hyungon; Kim, Sangsig

2016-10-01

In this study, we report the electrical and mechanical characteristics of fully transparent indium zinc oxide (IZO) thin-film transistors (TFTs) fabricated on stress-relieving bendable substrates. An IZO TFT on a stress-relieving substrate can operate normally at a bending radius of 6 mm, while an IZO TFT on a normal plastic substrate fails to operate normally at a bending radius of 15 mm. A plastic island with high Young's modulus embedded on a soft elastomer layer with low Young's modulus plays the role of a stress-relieving substrate for the operation of the bent IZO TFT. The stress and strain distributions over the IZO TFT will be analyzed in detail in this paper.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Performance Evaluation of III-V Hetero/Homojunction Esaki Tunnel Diodes on Si and Lattice Matched Substrates

NASA Astrophysics Data System (ADS)

Thomas, Paul M.

Understanding of quantum tunneling phenomenon in semiconductor systems is increasingly important as CMOS replacement technologies are investigated. This work studies a variety of heterojunction materials and types to increase tunnel currents to CMOS competitive levels and to understand how integration onto Si substrates affects performance. Esaki tunnel diodes were grown by Molecular Beam Epitaxy (MBE) on Si substrates via a graded buffer and control Esaki tunnel diodes grown on lattice matched substrates for this work. Peak current density for each diode is extracted and benchmarked to build an empirical data set for predicting diode performance. Additionally, statistics are used as tool to show peak to valley ratio for the III-V on Si sample and the control perform similarly below a threshold area. This work has applications beyond logic, as multijunction solar cell, heterojunction bipolar transistor, and light emitting diode designs all benefit from better tunnel contact design.

Nanotechnology in paper electronics

NASA Astrophysics Data System (ADS)

Demming, Anna; Österbacka, Professor Ronald; Han, Jin-Woo, Dr

2014-03-01

The ability to put cutting edge technology on paper—not in words but in a working physical form—has been attracting an increasing number of researchers over the past decade. Paper has many advantages that make it attractive for flexible electronics: it is relatively environmentally benign; it is renewable; it can be recycled; it is light weight; production processes for paper are well advanced; and it is inexpensive. This special issue, with guest editors Ronald Österbacka from Åbo Akademi University in Finland and Jin-Woo Han from the NASA AMES Research Center, features some of the latest in paper electronics research, including developments towards applications in displays, sensing and alternative energy sources, as well as fundamental studies to further our understanding of how paper can be most effectively used in electronics. As Andrew Steckl and colleagues in the US point out, 'Cellulose-based paper substrates were implemented as an electronic substrate as early as 1969, with most advancement occurring in the past decade largely due to technology improvements in thin film deposition and organic materials' [1, 2]. They report a detailed comparison between paper, standard liquid crystal display rigid glass and flexible glass for hosting pentacene organic thin film transistors, and obtain promising results for future paper-based devices. As most meaningful electronic devices rely on transistors to function, transistors feature quite prominently in this special issue. Rodrigo Martins and colleagues in France and Portugal study the effect of fibre type, structure and dimension on paper-based transistors and reveal further insights into how paper properties affect device performance [3]. Qing Wan and colleagues in China bring the state of the art in transistor technology to paper substrates [4], fabricating indium-zinc-oxide (IZO)-based protonic/electronic hybrid thin film transistors on paper and showing that they can be used as artificial synapses. Like the connections in the nervous system, these synaptic transistors can mimic synaptic stimulation response and short-term synaptic plasticity. The idea of harnessing paper electronics for display applications seems a natural update on the familiar traditional uses of paper to host text and images. Jong-Man Kim and Bora Yoon at Hanyang University in Korea screen print a flexible paper-based display for representing the digits 0-9 [5]. The device exploits the electrochromothermic properties of five different polydiacetylenes to allow a range of activation temperatures and operational voltages for the display. A number of other applications also feature in the special issue, including two different supramolecular recognition architectures for DNA hybridization in sensing applications [6] and all-solid flexible micro-supercapacitors with excellent cycling stability [7]. The demonstrated potential in the alternative energy industry seems particularly fitting given the environmental recommendations of paper electronics. Despite the promising outlook demonstrated for fabricating on paper by screen or ink-jet printing, as Henrik A Andersson and colleagues point out, it may be some time before devices can be printed with the functionality of even the most inexpensive microcontroller or other integrated circuit [8]. In their report they consider different methods to mount and contact standard surface mount device components to ink-jet printed conductive tracks on paper substrates. 'If paper is used as a substrate for printed hybrid electronics, it opens the possibility of integrating low-cost electronic functions directly on packages, even possibly directly in the production line', they add. A blank sheet of paper can be considered useful for making notes, convenient for slipping in a purse or pocket and enormously inspiring for the infinity of ideas not yet written on it. As this special issue demonstrates [2-14] all three attributes are at least as valid when using paper for electronics devices. If 'writing is thinking on paper' [15], it seems researchers are finding yet more powerful means of putting their ideas on paper. References [1] Barquinha P, Martins R, Pereira L and Fortunato E 2012 Transparent Oxide Electronics: From Materials to Devices (Chichester: Wiley) [2] Zocco A T, You H, Hagen J A and Steckl A J 2014 Pentacene organic thin film transistors on flexible paper and glass substrates Nanotechnology 25 094005 [3] Pereira L, Gaspar D, Guerin D, Delattre A, Fortunato E and Martins R 2014 The influence of fibril composition and dimension on the performance of paper gated oxide transistors Nanotechnology 25 094007 [4] Wu G, Wan C, Zhou J, Zhu L and Wan Q 2014 Low-voltage protonic/electronic hybrid indium-zinc-oxide synaptic transistors on paper substrates Nanotechnology 25 094001 [5] Shin H, Yoon B, Park I S and Kim J-M 2014 An electrothermochromic paper display based on colorimetrically reversible polydiacetylenes Nanotechnology 25 094011 [6] Ihalainen P, Pettersson F, Pesonen M, Viitala T, Määttänen A, Österbacka R and Peltonen J 2014 An impedimetric study of DNA hybridization on paper supported inkjet-printed gold electrodes Nanotechnology 25 094009 [7] Wang Y, Shi Y, Zhao C X, Wong J I, Sun X W and Yang H Y 2014 Printed all-solid flexible microsupercapacitors: towards the general route for high energy storage device Nanotechnology 25 094010 [8] Andersson H A, Manuilskiy A, Haller S, Hummelgård M, Sidén J, Hummelgård C, Olin H and Nilsson H-E 2014 Assembling surface mounted components on ink-jet printed double sided paper circuit board Nanotechnology 25 094002 [9] Gaspar D, Fernandes S N, de Oliveira A G, Fernandes J G, Grey P, Pontes R V, Pereira L, Martins R, Godinho M H and Fortunato E 2014 Nanocrystalline cellulose applied simultaneously as gate dielectric and substrate on flexible field effect transistors Nanotechnology 25 094008 [10] Männl U, van den Berg C, Magunje B, Härting M, Britton D T, Jones S, Mvan Staden M J and Scriba M R 2014 Nanoparticle composites for printed electronics Nanotechnology 25 094004 [11] Costa M N, Veigas B, Jacob J M, Santos D S, Gomes J, Baptista P V, Martins R, Inácio J and Fortunato E 2014 Low cost, safe, disposable, rapid and self-sustainable paper based platform for diagnostic testing: lab-on-paper Nanotechnology 25 094006 [12] Bollström R, Pettersson F, Dolietis P, Preston J, Österbacka R and Toivakka M 2014 Impact of humidity on functionality of on-paper printed electronics Nanotechnology 25 094003 [13] Purandare S, Gomez E F and Steckl A J 2014 High brightness phosphorescent organic light emitting diodes on transparent and flexible cellulose films Nanotechnology 25 094012 [14] Kim J-H, Mun S, Ko H-U, Yun G-Y and Kim J 2014 Disposable chemical and biosensors made on cellulose paper Nanotechnology 25 092001 [15] Zinsser W 1976 Introduction On Writing Well 5th edn, p vii

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Flexible digital x-ray technology for far-forward remote diagnostic and conformal x-ray imaging applications

NASA Astrophysics Data System (ADS)

Smith, Joseph; Marrs, Michael; Strnad, Mark; Apte, Raj B.; Bert, Julie; Allee, David; Colaneri, Nicholas; Forsythe, Eric; Morton, David

2013-05-01

Today's flat panel digital x-ray image sensors, which have been in production since the mid-1990s, are produced exclusively on glass substrates. While acceptable for use in a hospital or doctor's office, conventional glass substrate digital x-ray sensors are too fragile for use outside these controlled environments without extensive reinforcement. Reinforcement, however, significantly increases weight, bulk, and cost, making them impractical for far-forward remote diagnostic applications, which demand rugged and lightweight x-ray detectors. Additionally, glass substrate x-ray detectors are inherently rigid. This limits their use in curved or bendable, conformal x-ray imaging applications such as the non-destructive testing (NDT) of oil pipelines. However, by extending low-temperature thin-film transistor (TFT) technology previously demonstrated on plastic substrate- based electrophoretic and organic light emitting diode (OLED) flexible displays, it is now possible to manufacture durable, lightweight, as well as flexible digital x-ray detectors. In this paper, we discuss the principal technical approaches used to apply flexible display technology to two new large-area flexible digital x-ray sensors for defense, security, and industrial applications and demonstrate their imaging capabilities. Our results include a 4.8″ diagonal, 353 x 463 resolution, flexible digital x-ray detector, fabricated on a 6″ polyethylene naphthalate (PEN) plastic substrate; and a larger, 7.9″ diagonal, 720 x 640 resolution, flexible digital x-ray detector also fabricated on PEN and manufactured on a gen 2 (370 x 470 mm) substrate.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Direct growth of single-crystalline III–V semiconductors on amorphous substrates

DOE PAGES

Chen, Kevin; Kapadia, Rehan; Harker, Audrey; ...

2016-01-27

The III–V compound semiconductors exhibit superb electronic and optoelectronic properties. Traditionally, closely lattice-matched epitaxial substrates have been required for the growth of high-quality single-crystal III–V thin films and patterned microstructures. To remove this materials constraint, here we introduce a growth mode that enables direct writing of single-crystalline III–V’s on amorphous substrates, thus further expanding their utility for various applications. The process utilizes templated liquid-phase crystal growth that results in user-tunable, patterned micro and nanostructures of single-crystalline III–V’s of up to tens of micrometres in lateral dimensions. InP is chosen as a model material system owing to its technological importance. Themore » patterned InP single crystals are configured as high-performance transistors and photodetectors directly on amorphous SiO 2 growth substrates, with performance matching state-of-the-art epitaxially grown devices. In conclusion, the work presents an important advance towards universal integration of III–V’s on application-specific substrates by direct growth.« less

Direct growth of single-crystalline III–V semiconductors on amorphous substrates

PubMed Central

Chen, Kevin; Kapadia, Rehan; Harker, Audrey; Desai, Sujay; Seuk Kang, Jeong; Chuang, Steven; Tosun, Mahmut; Sutter-Fella, Carolin M.; Tsang, Michael; Zeng, Yuping; Kiriya, Daisuke; Hazra, Jubin; Madhvapathy, Surabhi Rao; Hettick, Mark; Chen, Yu-Ze; Mastandrea, James; Amani, Matin; Cabrini, Stefano; Chueh, Yu-Lun; Ager III, Joel W.; Chrzan, Daryl C.; Javey, Ali

2016-01-01

The III–V compound semiconductors exhibit superb electronic and optoelectronic properties. Traditionally, closely lattice-matched epitaxial substrates have been required for the growth of high-quality single-crystal III–V thin films and patterned microstructures. To remove this materials constraint, here we introduce a growth mode that enables direct writing of single-crystalline III–V's on amorphous substrates, thus further expanding their utility for various applications. The process utilizes templated liquid-phase crystal growth that results in user-tunable, patterned micro and nanostructures of single-crystalline III–V's of up to tens of micrometres in lateral dimensions. InP is chosen as a model material system owing to its technological importance. The patterned InP single crystals are configured as high-performance transistors and photodetectors directly on amorphous SiO2 growth substrates, with performance matching state-of-the-art epitaxially grown devices. The work presents an important advance towards universal integration of III–V's on application-specific substrates by direct growth. PMID:26813257

The study of VOPc thin film transistors on modified substrates

NASA Astrophysics Data System (ADS)

Song, De; Xu, Qi; Cheng, Hongcang; Li, Bao-zeng; Shang, Yubin

2018-02-01

The vanadyl phthalocyanine (VOPc) organic thin film transistors (OTFTs) were fabricated on the various organosilane self-assembled monolayer (SAM) modified substrates. And the effect of the surface properties on the performance of these transistors was studied. The atomic force morphologies and X-ray diffraction (XRD) spectrums of vanadyl phthalocyanine films on different SAM-modified surfaces were studied. They reveal that the terminal functional groups of organosilane affect the growth of VOPc film and device performance. The VOPc film on octadecyltrichlorosilane (OTS) modified substrate has larger crystal size and effective crystal thickness than those on phenyltrichlorosilane (PTS), 1H,1H,2H,2H-Perfluorodec-yltrichlorosilane (FDTS) as well as non-modified substrate, which contributes the mobility of corresponding device several and several dozen times relative to other ones. The effective crystal thickness and crystal grain size of VOPc film on PTS is between that on OTS treated and that on non-modified substrate due to the stronger attractive force between VOPc and SiO2. The VOPc films' performance and effective crystal thickness on FDTS treated are worse than that on PTS due to the existents of attractive force between -CF3 and VOPc.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

PubMed Central

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

Flexible active-matrix displays and shift registers based on solution-processed organic transistors.

PubMed

Gelinck, Gerwin H; Huitema, H Edzer A; van Veenendaal, Erik; Cantatore, Eugenio; Schrijnemakers, Laurens; van der Putten, Jan B P H; Geuns, Tom C T; Beenhakkers, Monique; Giesbers, Jacobus B; Huisman, Bart-Hendrik; Meijer, Eduard J; Benito, Estrella Mena; Touwslager, Fred J; Marsman, Albert W; van Rens, Bas J E; de Leeuw, Dago M

2004-02-01

At present, flexible displays are an important focus of research. Further development of large, flexible displays requires a cost-effective manufacturing process for the active-matrix backplane, which contains one transistor per pixel. One way to further reduce costs is to integrate (part of) the display drive circuitry, such as row shift registers, directly on the display substrate. Here, we demonstrate flexible active-matrix monochrome electrophoretic displays based on solution-processed organic transistors on 25-microm-thick polyimide substrates. The displays can be bent to a radius of 1 cm without significant loss in performance. Using the same process flow we prepared row shift registers. With 1,888 transistors, these are the largest organic integrated circuits reported to date. More importantly, the operating frequency of 5 kHz is sufficiently high to allow integration with the display operating at video speed. This work therefore represents a major step towards 'system-on-plastic'.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

PubMed

Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

2014-10-29

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate.

PubMed

Lee, Jae-Kyu; Choi, Duck-Kyun

2012-07-01

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

Graphene-based flexible and stretchable thin film transistors.

PubMed

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

Stable organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

DOE PAGES

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; ...

2018-01-12

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

PubMed Central

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Park, Youngrak; Kippelen, Bernard

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies. PMID:29340301

Flexible Graphene Transistor Architecture for Optical Sensor Technology

NASA Astrophysics Data System (ADS)

Ordonez, Richard Christopher

The unique electrical and optoelectronic properties of graphene allow tunable conductivity and broadband electromagnetic absorption that spans the ultraviolet and infrared regimes. However, in the current state-of-art graphene sensor architectures, junction resistance and doping concentration are predominant factors that affect signal strength and sensitivity. Unfortunately, graphene produces high contact resistances with standard electrode materials ( few kilo-ohms), therefore, signal is weak and large carrier concentrations are required to probe sensitivity. Moreover, the atomic thickness of graphene enables the potential for flexible electronics, but there has not been a successful graphene sensor architecture that demonstrates stable operation on flexible substrates and with minimal fabrication cost. In this study, the author explores a novel 3-terminal transistor architecture that integrates twodimensional graphene, liquid metal, and electrolytic gate dielectrics (LM-GFETs: Liquid Metal and Graphene Field-Effect Transistors ). The goal is to deliver a sensitive, flexible, and lightweight transistor architecture that will improve sensor technology and maneuverability. The reported high thermal conductivity of graphene provides potential for room-temperature thermal management without the need of thermal-electric and gas cooling systems that are standard in sensor platforms. Liquid metals provide a unique opportunity for conformal electrodes that maximize surface area contact, therefore, enable flexibility, lower contact resistance, and reduce damage to the graphene materials involved. Lastly, electrolytic gate dielectrics provide conformability and high capacitances needed for high on/off rations and electrostatic gating. Results demonstrated that with minimal fabrication steps the proposed flexible graphene transistor architecture demonstrated ambipolar current-voltage transfer characteristics that are comparable to the current state-of-the-art. An additional investigation demonstrated PN junction operation and the successful integration of the proposed architecture into an optoelectronic application with the use of semiconductor quantum dots in contact with the graphene material that acted as optical absorbers to increase detector gain. Applications that can benefit from such technology advancement include Nano-satellites (Nanosat), Underwater autonomous vehicles (UAV), and airborne platforms in which flexibility and sensitivity are critical parameters that must be optimized to increase mission duration and range.

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets

NASA Technical Reports Server (NTRS)

Zoutendyk, John A. (Inventor)

1991-01-01

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Control of droplet morphology for inkjet-printed TIPS-pentacene transistors

USGS Publications Warehouse

Lee, Myung Won; Ryu, Gi Seong; Lee, Young Uk; Pearson, Christopher; Petty, Michael C.; Song, Chung Kun

2012-01-01

We report on methods to control the morphology of droplets of 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-PEN), which are then used in the fabrication of organic thin film transistors (OTFTs). The grain size and distribution of the TIPS-PEN were found to depend on the temperature of the droplets during drying. The performance of the OTFTs could be improved by heating the substrate and also by changing the relative positions of the inkjet-printed droplets. In our experiments, the optimum substrate temperature was 46 °C in air. Transistors with the TIPS-PEN grain boundaries parallel to the current flow between the source and drain electrodes exhibited charge carrier mobilities of 0.44 ± 0.08 cm2/V s.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

NASA Astrophysics Data System (ADS)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

High mobility n-type organic thin-film transistors deposited at room temperature by supersonic molecular beam deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiarella, F., E-mail: fabio.chiarella@spin.cnr.it; Barra, M.; Ciccullo, F.

In this paper, we report on the fabrication of N,N′-1H,1H-perfluorobutil dicyanoperylenediimide (PDIF-CN{sub 2}) organic thin-film transistors by Supersonic Molecular Beam Deposition. The devices exhibit mobility up to 0.2 cm{sup 2}/V s even if the substrate is kept at room temperature during the organic film growth, exceeding by three orders of magnitude the electrical performance of those grown at the same temperature by conventional Organic Molecular Beam Deposition. The possibility to get high-mobility n-type transistors avoiding thermal treatments during or after the deposition could significantly extend the number of substrates suitable to the fabrication of flexible high-performance complementary circuits by using this compound.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

PubMed

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Carbon Based Transistors and Nanoelectronic Devices

NASA Astrophysics Data System (ADS)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the effect of nanotube network density was explained in detail. On the other hand, graphene transfer technology was explored here as well. Annealing techniques were utilized to deposit clean graphene on arbitrary substrates. Raman spectroscopy and Raman data analysis was used to confirm the clean process. Furthermore, suspended graphene membrane was fabricated using single and multi-layer graphene films. This can make a major impact on graphene based transistors and bio-nano sensors technology.

Gallium nitride vertical power devices on foreign substrates: a review and outlook

NASA Astrophysics Data System (ADS)

Zhang, Yuhao; Dadgar, Armin; Palacios, Tomás

2018-07-01

Vertical gallium nitride (GaN) power devices have attracted increased attention due to their superior high-voltage and high-current capacity as well as easier thermal management than lateral GaN high electron mobility transistors. Vertical GaN devices are promising candidates for next-generation power electronics in electric vehicles, data centers, smart grids and renewable energy process. The use of low-cost foreign substrates such as silicon (Si) substrates, instead of the expensive free-standing GaN substrates, could greatly trim material cost and enable large-diameter wafer processing while maintaining high device performance. This review illustrates recent progress in material epitaxy, device design, device physics and processing technologies for the development of vertical GaN power devices on low-cost foreign substrates. Although the device technologies are still at the early stage of development, state-of-the-art vertical GaN-on-Si power diodes have already shown superior Baliga’s figure of merit than commercial SiC and Si power devices at the voltage classes beyond 600 V. Furthermore, we unveil the design space of vertical GaN power devices on native and different foreign substrates, from the analysis of the impact of dislocation and defects on device performance. We conclude by identifying the application space, current challenges and exciting research opportunities in this very dynamic research field.

Npn double heterostructure bipolar transistor with ingaasn base region

DOEpatents

Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.

2004-07-20

An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors

PubMed Central

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-01-01

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Flexible organic transistors and circuits with extreme bending stability

NASA Astrophysics Data System (ADS)

Sekitani, Tsuyoshi; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2010-12-01

Flexible electronic circuits are an essential prerequisite for the development of rollable displays, conformable sensors, biodegradable electronics and other applications with unconventional form factors. The smallest radius into which a circuit can be bent is typically several millimetres, limited by strain-induced damage to the active circuit elements. Bending-induced damage can be avoided by placing the circuit elements on rigid islands connected by stretchable wires, but the presence of rigid areas within the substrate plane limits the bending radius. Here we demonstrate organic transistors and complementary circuits that continue to operate without degradation while being folded into a radius of 100μm. This enormous flexibility and bending stability is enabled by a very thin plastic substrate (12.5μm), an atomically smooth planarization coating and a hybrid encapsulation stack that places the transistors in the neutral strain position. We demonstrate a potential application as a catheter with a sheet of transistors and sensors wrapped around it that enables the spatially resolved measurement of physical or chemical properties inside long, narrow tubes.

Heterojunction bipolar transistor technology for data acquisition and communication

NASA Technical Reports Server (NTRS)

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Gallium Arsenide Monolithic Optoelectronic Circuits

NASA Astrophysics Data System (ADS)

Bar-Chaim, N.; Katz, J.; Margalit, S.; Ury, I.; Wilt, D.; Yariv, A.

1981-07-01

The optical properties of GaAs make it a very useful material for the fabrication of optical emitters and detectors. GaAs also possesses electronic properties which allow the fabrication of high speed electronic devices which are superior to conventional silicon devices. Monolithic optoelectronic circuits are formed by the integration of optical and electronic devices on a single GaAs substrate. Integration of many devices is most easily accomplished on a semi-insulating (SI) sub-strate. Several laser structures have been fabricated on SI GaAs substrates. Some of these lasers have been integrated with Gunn diodes and with metal semiconductor field effect transistors (MESFETs). An integrated optical repeater has been demonstrated in which MESFETs are used for optical detection and electronic amplification, and a laser is used to regenerate the optical signal. Monolithic optoelectronic circuits have also been constructed on conducting substrates. A heterojunction bipolar transistor driver has been integrated with a laser on an n-type GaAs substrate.

Current-Induced Transistor Sensorics with Electrogenic Cells

PubMed Central

Fromherz, Peter

2016-01-01

The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned. PMID:27120627

Analysis of e-beam impact on the resist stack in e-beam lithography process

NASA Astrophysics Data System (ADS)

Indykeiwicz, K.; Paszkiewicz, B.

2013-07-01

Paper presents research on the sub-micron gate, AlGaN /GaN HEMT type transistors, fabrication by e-beam lithography and lift-off technique. The impact of the electron beam on the resists layer and the substrate was analyzed by MC method in Casino v3.2 software. The influence of technological process parameters on the metal structures resolution and quality for paths 100 nm, 300 nm and 500 nm wide and 20 μm long was studied. Qualitative simulation correspondences to the conducted experiments were obtained.

Self Assembly of Nano Metric Metallic Particles for Realization of Photonic and Electronic Nano Transistors

PubMed Central

Shahmoon, Asaf; Limon, Ofer; Girshevitz, Olga; Zalevsky, Zeev

2010-01-01

In this paper, we present the self assembly procedure as well as experimental results of a novel method for constructing well defined arrangements of self assembly metallic nano particles into sophisticated nano structures. The self assembly concept is based on focused ion beam (FIB) technology, where metallic nano particles are self assembled due to implantation of positive gallium ions into the insulating material (e.g., silica as in silicon on insulator wafers) that acts as intermediary layer between the substrate and the negatively charge metallic nanoparticles. PMID:20559513

Permanent and Transient Radiation Effects on Thin-Oxide (200-A) MOS Transistors

DTIC Science & Technology

1976-06-01

n-channel technology using a SiO, gate-oxide thickness ol ’ 200 A and a %hallow phiosphorus diffusion of 0.5 pin on a 0.7-ohm)-cmn 8-doped > Si...substrate. The thickness of the sell-aligned it polysilicon gate was kept at 3500 A. The oxide was grown in dry 0, at a temperature ot 1000C, followed...semiconductor work function difference (equal to 0 V for the polysilicon gates’ studied here). The effect of the ionizing radiation is to introduce

Self assembly of nano metric metallic particles for realization of photonic and electronic nano transistors.

PubMed

Shahmoon, Asaf; Limon, Ofer; Girshevitz, Olga; Zalevsky, Zeev

2010-05-25

In this paper, we present the self assembly procedure as well as experimental results of a novel method for constructing well defined arrangements of self assembly metallic nano particles into sophisticated nano structures. The self assembly concept is based on focused ion beam (FIB) technology, where metallic nano particles are self assembled due to implantation of positive gallium ions into the insulating material (e.g., silica as in silicon on insulator wafers) that acts as intermediary layer between the substrate and the negatively charge metallic nanoparticles.

Si1-yGey or Ge1-zSnz Source/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

NASA Astrophysics Data System (ADS)

Eneman, Geert; De Keersgieter, An; Witters, Liesbeth; Mitard, Jerome; Vincent, Benjamin; Hikavyy, Andriy; Loo, Roger; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron

2013-04-01

The interaction between two stress techniques, strain-relaxed buffers (SRBs) and epitaxial source/drain stressors, is studied on short, Si1-xGex- and Ge-channel planar transistors. This work focuses on the longitudinal channel stress generated by these two techniques. Unlike for unstrained silicon-channel transistors, for strained channels on top of a strain-relaxed buffer a source/drain stressor without recess generates similar longitudinal channel stress than source/drain stressors with a deep recess. The least efficient stress transfer is obtained for source/drain stressors with a small recess that removes only the strained channel, not the substrate underneath. These trends are explained by a trade-off between elastic relaxation of the strained-channel during source/drain recess and the increased stress generation of thicker source/drain stressors. For Ge-channel pFETs, GeSn source/drains and Si1-xGex strain-relaxed buffers are efficient stressors for mobility enhancement. The former is more efficient for gate-last schemes than for gate-first, while the stress generated by the SRB is found to be independent of the gate-scheme.

Transfer of Graphene Layers Grown on SiC Wafers to Other Substrates and Their Integration into Field Effect Transistors

NASA Astrophysics Data System (ADS)

Unarunotai, Sakulsuk; Murata, Yuya; Chialvo, Cesar; Kim, Hoon-Sik; MacLaren, Scott; Mason, Nadya; Petrov, Ivan; Rogers, John

2010-03-01

An approach to produce graphene films by epitaxial growth on silicon carbide substrate is promising, but its current implementation requires the use of SiC as the device substrate. We present a simple method for transferring epitaxial sheets of graphene on SiC to other substrates. The graphene was grown on the (0001) face of 6H-SiC by thermal annealing in a hydrogen atmosphere. Transfer was accomplished using a peeling process with a bilayer film of Gold/polyimide, to yield graphene with square millimeters of coverage on the target substrate. Back gated field-effect transistors fabricated on oxidized silicon substrates with Cr/Au as source-drain electrodes exhibited ambipolar characteristics with hole mobilities of ˜100 cm^2/V-s, and negligible influence of resistance at the contacts. This work was supported by the U.S. DOE, under Award No. DE-FG02-07ER46471, through the Frederick Seitz Materials Research Laboratory at the University of Illinois at Urbana-Champaign.

Design of Low-Noise Output Amplifiers for P-channel Charge-Coupled Devices Fabricated on High-Resistivity Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haque, S; Frost, F Dion R.; Groulx, R

2011-12-22

We describe the design and optimization of low-noise, single-stage output amplifiers for p-channel charge-coupled devices (CCDs) used for scientific applications in astronomy and other fields. The CCDs are fabricated on high-resistivity, 4000–5000 -cm, n-type silicon substrates. Single-stage amplifiers with different output structure designs and technologies have been characterized. The standard output amplifier is designed with an n{sup +} polysilicon gate that has a metal connection to the sense node. In an effort to lower the output amplifier readout noise by minimizing the capacitance seen at the sense node, buried-contact technology has been investigated. In this case, the output transistor hasmore » a p{sup +} polysilicon gate that connects directly to the p{sup +} sense node. Output structures with buried-contact areas as small as 2 μm × 2 μm are characterized. In addition, the geometry of the source-follower transistor was varied, and we report test results on the conversion gain and noise of the various amplifier structures. By use of buried-contact technology, better amplifier geometry, optimization of the amplifier biases and improvements in the test electronics design, we obtain a 45% reduction in noise, corresponding to 1.7 e{sup -} rms at 70 kpixels/sec.« less

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

PubMed

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Current progress and technical challenges of flexible liquid crystal displays

NASA Astrophysics Data System (ADS)

Fujikake, Hideo; Sato, Hiroto

2009-02-01

We focused on several technical approaches to flexible liquid crystal (LC) display in this report. We have been developing flexible displays using plastic film substrates based on polymer-dispersed LC technology with molecular alignment control. In our representative devices, molecular-aligned polymer walls keep plastic-substrate gap constant without LC alignment disorder, and aligned polymer networks create monostable switching of fast-response ferroelectric LC (FLC) for grayscale capability. In the fabrication process, a high-viscosity FLC/monomer solution was printed, sandwiched and pressed between plastic substrates. Then the polymer walls and networks were sequentially formed based on photo-polymerization-induced phase separation in the nematic phase by two exposure processes of patterned and uniform ultraviolet light. The two flexible backlight films of direct illumination and light-guide methods using small three-primary-color light-emitting diodes were fabricated to obtain high-visibility display images. The fabricated flexible FLC panels were driven by external transistor arrays, internal organic thin film transistor (TFT) arrays, and poly-Si TFT arrays. We achieved full-color moving-image displays using the flexible FLC panel and the flexible backlight film based on field-sequential-color driving technique. Otherwise, for backlight-free flexible LC displays, flexible reflective devices of twisted guest-host nematic LC and cholesteric LC were discussed with molecular-aligned polymer walls. Singlesubstrate device structure and fabrication method using self-standing polymer-stabilized nematic LC film and polymer ceiling layer were also proposed for obtaining LC devices with excellent flexibility.

Challenges and the state of the technology for printed sensor arrays for structural monitoring

NASA Astrophysics Data System (ADS)

Joshi, Shiv; Bland, Scott; DeMott, Robert; Anderson, Nickolas; Jursich, Gregory

2017-04-01

Printed sensor arrays are attractive for reliable, low-cost, and large-area mapping of structural systems. These sensor arrays can be printed on flexible substrates or directly on monitored structural parts. This technology is sought for continuous or on-demand real-time diagnosis and prognosis of complex structural components. In the past decade, many innovative technologies and functional materials have been explored to develop printed electronics and sensors. For example, an all-printed strain sensor array is a recent example of a low-cost, flexible and light-weight system that provides a reliable method for monitoring the state of aircraft structural parts. Among all-printing techniques, screen and inkjet printing methods are well suited for smaller-scale prototyping and have drawn much interest due to maturity of printing procedures and availability of compatible inks and substrates. Screen printing relies on a mask (screen) to transfer a pattern onto a substrate. Screen printing is widely used because of the high printing speed, large selection of ink/substrate materials, and capability of making complex multilayer devices. The complexity of collecting signals from a large number of sensors over a large area necessitates signal multiplexing electronics that need to be printed on flexible substrate or structure. As a result, these components are subjected to same deformation, temperature and other parameters for which sensor arrays are designed. The characteristics of these electronic components, such as transistors, are affected by deformation and other environmental parameters which can lead to erroneous sensed parameters. The manufacturing and functional challenges of the technology of printed sensor array systems for structural state monitoring are the focus of this presentation. Specific examples of strain sensor arrays will be presented to highlight the technical challenges.

Conceptual techniques for reducing parasitic current gain of lateral pnp transistors

NASA Technical Reports Server (NTRS)

Gallagher, R. C.; Scott, J. M.

1969-01-01

Two techniques have been conceptually proposed as possible means of reducing parasitic beta in lateral p-n-p transistors. One method uses a degenerate substrate and high concentration P /plus/ guard-ring diffusion, another places the base contact at the center of an annular ring structure.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Solution-Processed Organic and Halide Perovskite Transistors on Hydrophobic Surfaces.

PubMed

Ward, Jeremy W; Smith, Hannah L; Zeidell, Andrew; Diemer, Peter J; Baker, Stephen R; Lee, Hyunsu; Payne, Marcia M; Anthony, John E; Guthold, Martin; Jurchescu, Oana D

2017-05-31

Solution-processable electronic devices are highly desirable due to their low cost and compatibility with flexible substrates. However, they are often challenging to fabricate due to the hydrophobic nature of the surfaces of the constituent layers. Here, we use a protein solution to modify the surface properties and to improve the wettability of the fluoropolymer dielectric Cytop. The engineered hydrophilic surface is successfully incorporated in bottom-gate solution-deposited organic field-effect transistors (OFETs) and hybrid organic-inorganic trihalide perovskite field-effect transistors (HTP-FETs) fabricated on flexible substrates. Our analysis of the density of trapping states at the semiconductor-dielectric interface suggests that the increase in the trap density as a result of the chemical treatment is minimal. As a result, the devices exhibit good charge carrier mobilities, near-zero threshold voltages, and low electrical hysteresis.

Ubiquitous Graphene Electronics on Scotch Tape

PubMed Central

Chung, Yoonyoung; Ho Kim, Hyun; Lee, Sangryun; Lee, Eunho; Won Kim, Seong; Ryu, Seunghwa; Cho, Kilwon

2015-01-01

We report a novel concept of graphene transistors on Scotch tape for use in ubiquitous electronic systems. Unlike common plastic substrates such as polyimide and polyethylene terephthalate, the Scotch tape substrate is easily attached onto various objects such as banknotes, curved surfaces, and human skin, which implies potential applications wherein electronics can be placed in any desired position. Furthermore, the soft Scotch tape serves as an attractive substrate for flexible/foldable electronics that can be significantly bent, or even crumpled. We found that the adhesive layer of the tape with a relatively low shear modulus relaxes the strain when subjected to bending. The capacitance of the gate dielectric made of oxidized aluminum oxide was 1.5 μF cm−2, so that a supply voltage of only 2.5 V was sufficient to operate the devices. As-fabricated graphene transistors on Scotch tape exhibited high electron mobility of 1326 (±155) cm2 V−1 s−1; the transistors still showed high mobility of 1254 (±478) cm2 V−1 s−1 even after they were crumpled. PMID:26220874

S-MMICs: Sub-mm-Wave Transistors and Integrated Circuits

DTIC Science & Technology

2008-09-01

Research Lab BAA DAAD19-03-R-0017 Research area 2.35: RF devices—Dr. Alfred Hung Submitted by: Mark Rodwell, Department of Electrical and Computer ...MOTIVATION / APPLICATION 3 TECHNOLOGY STATUS 4 TRANSISTOR SCALING LAWS 5 256 NM GENERATION 6 HBT POWER AMPLIFIER DEVELOPMENT 7 DRY-ETCHED EMITTER...TECHNOLOGY: 256 NM GENERATION 9 SCALED EPITAXY 11 CONCLUSIONS 12 20081103013 Executive Summary Transistor and power amplifier IC technology was

High mobility La-doped BaSnO3 on non-perovskite MgO substrate

NASA Astrophysics Data System (ADS)

Kim, Youjung; Shin, Juyeon; Kim, Young Mo; Char, Kookrin

(Ba,La)SnO3 is a transparent perovskite oxide with high electron mobility and excellent oxygen stability. Field effect device with (Ba,La)SnO3 channel was reported to show good output characteristics on STO substrate. Here, we fabricated (Ba,La)SnO3\\ films and field effect devices with (Ba,La)SnO3 channel on non-perovskite MgO substrates, which are available in large size wafers. X-ray diffraction and transmission electron microscope (TEM) images of (Ba,La)SnO3\\ films on MgO substrates show that the films are epitaxial with many threading dislocations. (Ba,La)SnO3 exhibits the high mobility with 97.2 cm2/Vs at 2 % La doping on top of 150 nm thick BaSnO3 buffer layer. Excellent carrier modulation was observed in field effect devices. FET performances on MgO substrates are slightly better than those on SrTiO3 substrates in spite of the higher dislocation density on MgO than on SrTiO3 substrates. These high mobility BaSnO3 thin films and transistors on MgO substrates will accelerate development for applications in high temperature and high power electronics. Samsung Science and Technology Foundation.

Vertical GaN Devices for Power Electronics in Extreme Environments

DTIC Science & Technology

2016-03-31

electronics applications. In this paper vertical p-n diodes and transistors fabricated on pseudo bulk low defect density (104 to 106 cm-2) GaN substrates are...holes in p-GaN has deleterious effect on p-n junction behavior (Fig. 2), p-GaN contacts, and channel control in junction field-effect transistors at...and transistors ) utilizing p-n junctions are suitable for most practical applications including automotive (210K < T < 423K) but may have limitations

High performance tunnel field-effect transistor by gate and source engineering.

PubMed

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

High Reliability of 0.1 μm InGaAs/InAlAs/InP High Electron Mobility Transistors Microwave Monolithic Integrated Circuit on 3-inch InP Substrates

NASA Astrophysics Data System (ADS)

Chou, Yeong-Chang; Leung, Denise; Lai, Richard; Grundbacher, Ron; Scarpulla, John; Barsky, Mike; Nishimoto, Matt; Eng, David; Liu, Po-Hsin; Oki, Aaron; Streit, Dwight

2002-02-01

The high-reliability performance of K-band microwave monolithic integrated circuit (MMIC) amplifiers fabricated with 0.1 μm gate length InGaAs/InAlAs/InP high electron mobility transistors (HEMTs) on 3-inch wafers using a high volume production process technology is reported. Operating at an accelerated life test condition of Vds=1.5 V and Ids=150 mA/mm, two-stage balanced amplifiers were lifetested at two-temperatures (T1=230°C, and T2=250°C) in nitrogen ambient. The activation energy (Ea) is as high as 1.5 eV, achieving a projected median-time-to-failure (MTTF) >1× 106 h at a 125°C of junction temperature. MTTF was determined by 2-temperature constant current stress using |Δ S21|>1.0 dB as the failure criteria. This is the first report of high reliability 0.1 μm InGaAs/InAlAs/InP HEMT MMICs based on small-signal microwave characteristics. This result demonstrates a reliable InGaAs/InAlAs/InP HEMT production technology.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Treesearch

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Doped Organic Transistors.

PubMed

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Flexible amorphous oxide thin-film transistors on polyimide substrate for AMOLED

NASA Astrophysics Data System (ADS)

Xu, Zhiping; Li, Min; Xu, Miao; Zou, Jianhua; Gao, Zhuo; Pang, Jiawei; Guo, Ying; Zhou, Lei; Wang, Chunfu; Fu, Dong; Peng, Junbiao; Wang, Lei; Cao, Yong

2014-10-01

We report a flexible amorphous Lanthanide doped In-Zn-O (IZO) thin-film transistor (TFT) backplane on polyimide (PI) substrate. In order to de-bond the PI film from the glass carrier easily after the flexible AMOLED process, a special inorganic film is deposited on the glass before the PI film is coated. The TFT exhibited a field-effect mobility of 6.97 cm2V-1 s-1, a subthreshold swing of 0.248 V dec-1, and an Ion/Ioff ratio of 5.19×107, which is sufficient to drive the OLEDs.

Self-aligned photolithography for the fabrication of fully transparent high-voltage devices

NASA Astrophysics Data System (ADS)

Zhang, Yonghui; Mei, Zengxia; Huo, Wenxing; Wang, Tao; Liang, Huili; Du, Xiaolong

2018-05-01

High-voltage devices, working in the range of hundreds of volts, are indispensable elements in the driving or readout circuits for various kinds of displays, integrated microelectromechanical systems and x-ray imaging sensors. However, the device performances are found hardly uniform or repeatable due to the misalignment issue, which are extremely common for offset drain high-voltage devices. To resolve this issue, this article reports a set of self-aligned photolithography technology for the fabrication of high-voltage devices. High-performance fully-transparent high-voltage thin film transistors, diodes and logic inverters are successfully fabricated with this technology. Unlike other self-aligned routes, opaque masks are introduced on the backside of the transparent substrate to facilitate proximity exposure method. The photolithography process is simulated and analyzed with technology computer aided design simulation to explain the working principle of the proximity exposure method. The substrate thickness is found to be vital for the implementation of this technology based on both simulation and experimental results. The electrical performance of high-voltage devices is dependent on the offset length, which can be delicately modulated by changing the exposure dose. The presented self-aligned photolithography technology is proved to be feasible in high-voltage circuits, demonstrating its huge potential in practical industrial applications.

Fabricating metal-oxide-semiconductor field-effect transistors on a polyethylene terephthalate substrate by applying low-temperature layer transfer of a single-crystalline silicon layer by meniscus force

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sakaike, Kohei; Akazawa, Muneki; Nakamura, Shogo

2013-12-02

A low-temperature local-layer technique for transferring a single-crystalline silicon (c-Si) film by using a meniscus force was proposed, and an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) was fabricated on polyethylene terephthalate (PET) substrate. It was demonstrated that it is possible to transfer and form c-Si films in the required shape at the required position on PET substrates at extremely low temperatures by utilizing a meniscus force. The proposed technique for layer transfer was applied for fabricating high-performance c-Si MOSFETs on a PET substrate. The fabricated MOSFET showed a high on/off ratio of more than 10{sup 8} and a high field-effect mobilitymore » of 609 cm{sup 2} V{sup −1} s{sup −1}.« less

AlGaN/GaN high electron mobility transistor grown on GaN template substrate by molecule beam epitaxy system

NASA Astrophysics Data System (ADS)

Tsai, Jenn-Kai; Chen, Y. L.; Gau, M. H.; Pang, W. Y.; Hsu, Y. C.; Lo, Ikai; Hsieh, C. H.

2008-03-01

In this study, AlGaN/GaN high electron mobility transistor (HEMT) structure was grow on GaN template substrate radio frequency plasma assisted molecular beam epitaxy (MBE) equipped with an EPI UNI-Bulb nitrogen plasma source. The undoped GaN template substrate was grown on c-sapphire substrate by metal organic vapor phase epitaxy system (MOPVD). After growth of MOVPE and MBE, the samples are characterized by double crystal X-ray diffraction (XRD), transmission electron microscopy (TEM), field emission scanning electron microscopy (SEM), atomic force microscopy (AFM), and Hall effect measurements. We found that the RMS roughness of template substrate play the major role in got the high value of mobility on AlGaN/GaN HEMT. When the roughness was lower than 0.77 nm in a 25 μm x 25 μm area, the mobility of HEMT at the temperature of 77 K was over 10000 cm^2/Vs.

Doped organic transistors operating in the inversion and depletion regime

PubMed Central

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

A graphene Zener-Klein transistor cooled by a hyperbolic substrate

NASA Astrophysics Data System (ADS)

Yang, Wei; Berthou, Simon; Lu, Xiaobo; Wilmart, Quentin; Denis, Anne; Rosticher, Michael; Taniguchi, Takashi; Watanabe, Kenji; Fève, Gwendal; Berroir, Jean-Marc; Zhang, Guangyu; Voisin, Christophe; Baudin, Emmanuel; Plaçais, Bernard

2018-01-01

The engineering of cooling mechanisms is a bottleneck in nanoelectronics. Thermal exchanges in diffusive graphene are mostly driven by defect-assisted acoustic phonon scattering, but the case of high-mobility graphene on hexagonal boron nitride (hBN) is radically different, with a prominent contribution of remote phonons from the substrate. Bilayer graphene on a hBN transistor with a local gate is driven in a regime where almost perfect current saturation is achieved by compensation of the decrease in the carrier density and Zener-Klein tunnelling (ZKT) at high bias. Using noise thermometry, we show that the ZKT triggers a new cooling pathway due to the emission of hyperbolic phonon polaritons in hBN by out-of-equilibrium electron-hole pairs beyond the super-Planckian regime. The combination of ZKT transport and hyperbolic phonon polariton cooling renders graphene on BN transistors a valuable nanotechnology for power devices and RF electronics.

Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

PubMed

Putranto, Dedy Septono Catur; Priambodo, Purnomo Sidi; Hartanto, Djoko; Du, Wei; Satoh, Hiroaki; Ono, Atsushi; Inokawa, Hiroshi

2014-09-08

Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation.

A Substrate Bias Effect on Recovery of the Threshold Voltage Shift of Amorphous Silicon Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Han, Chang-Wook; Han, Min-Koo; Choi, Nack-Bong; Kim, Chang-Dong; Kim, Ki-Yong; Chung, In-Jae

2007-07-01

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were fabricated on a flexible stainless-steel (SS) substrate. The stability of the a-Si:H TFT is a key issue for active matrix organic light-emitting diodes (AMOLEDs). The drain current decreases because of the threshold voltage shift (Δ VTH) during OLED driving. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and the gate electrode without additional circuits. The negative voltage biased at the SS substrate can recover Δ VTH and reduced drain current of the driving TFT. The VTH of the TFT increased by 2.3 V under a gate bias of +15 V and a drain bias of +15 V at 65 °C applied for 3,500 s. The VTH decreased by -2.3 V and the drain current recovered 97% of its initial value under a substrate bias of -23 V at 65 °C applied for 3,500 s.

High-Performance Vertical Organic Electrochemical Transistors.

PubMed

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

PubMed

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

Deposition of tetracene thin films on SiO2/Si substrates by rapid expansion of supercritical solutions using carbon dioxide

NASA Astrophysics Data System (ADS)

Fujii, Tatsuya; Takahashi, Yuta; Uchida, Hirohisa

2015-03-01

We report on a novel deposition technique of tetracene (naphthacene) thin films on SiO2/Si substrates by rapid expansion of supercritical solutions (RESS) using CO2. Optical microscopy and scanning electron microscopy show that the thin films consist of a high density of submicron-sized grains. The growth mode of the grains followed the Volmer-Weber mode. X-ray diffraction shows that the thin films have regularly arranged structures in both the horizontal and vertical directions of the substrate. A fabricated top-contacted organic thin-film transistor with the tetracene active layer showed p-type transistor characteristics with a field-effect mobility of 5.1 × 10-4 cm2 V-1 s-1.

Fabrication of InGaN thin-film transistors using pulsed sputtering deposition.

PubMed

Itoh, Takeki; Kobayashi, Atsushi; Ueno, Kohei; Ohta, Jitsuo; Fujioka, Hiroshi

2016-07-07

We report the first demonstration of operational InGaN-based thin-film transistors (TFTs) on glass substrates. The key to our success was coating the glass substrate with a thin amorphous layer of HfO2, which enabled a highly c-axis-oriented growth of InGaN films using pulsed sputtering deposition. The electrical characteristics of the thin films were controlled easily by varying their In content. The optimized InGaN-TFTs exhibited a high on/off ratio of ~10(8), a field-effect mobility of ~22 cm(2) V(-1) s(-1), and a maximum current density of ~30 mA/mm. These results lay the foundation for developing high-performance electronic devices on glass substrates using group III nitride semiconductors.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE PAGES

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja; ...

2014-11-26

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Noh, Joo Hyon; Joshi, Pooran C.; Kuruganti, Teja

Pulse thermal processing (PTP) has been explored for low thermal budget integration of indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The IGZO TFTs are exposed to a broadband (0.2-1.4 m) arc lamp radiation spectrum with 100 pulses of 1 msec pulse width. The impact of radiant exposure power on the TFT performance was analyzed in terms of the switching characteristics and bias stress reliability characteristics, respectively. The PTP treated IGZO TFTs with power density of 3.95 kW/cm 2 and 0.1 sec total irradiation time showed comparable switching properties, at significantly lower thermal budget, to furnace annealed IGZO TFT.more » The typical field effect mobility FE, threshold voltage VT, and sub-threshold gate swing S.S were calculated to be 7.8 cm 2/ V s, 8.1 V, and 0.22 V/ decade, respectively. The observed performance shows promise for low thermal budget TFT integration on flexible substrates exploiting the large-area, scalable PTP technology.« less

Scaling and Graphical Transport-Map Analysis of Ambipolar Schottky-Barrier Thin-Film Transistors Based on a Parallel Array of Si Nanowires.

PubMed

Jeon, Dae-Young; Pregl, Sebastian; Park, So Jeong; Baraban, Larysa; Cuniberti, Gianaurelio; Mikolajick, Thomas; Weber, Walter M

2015-07-08

Si nanowire (Si-NW) based thin-film transistors (TFTs) have been considered as a promising candidate for next-generation flexible and wearable electronics as well as sensor applications with high performance. Here, we have fabricated ambipolar Schottky-barrier (SB) TFTs consisting of a parallel array of Si-NWs and performed an in-depth study related to their electrical performance and operation mechanism through several electrical parameters extracted from the channel length scaling based method. Especially, the newly suggested current-voltage (I-V) contour map clearly elucidates the unique operation mechanism of the ambipolar SB-TFTs, governed by Schottky-junction between NiSi2 and Si-NW. Further, it reveals for the first-time in SB based FETs the important internal electrostatic coupling between the channel and externally applied voltages. This work provides helpful information for the realization of practical circuits with ambipolar SB-TFTs that can be transferred to different substrate technologies and applications.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis.

PubMed

Sowade, Enrico; Ramon, Eloi; Mitra, Kalyan Yoti; Martínez-Domingo, Carme; Pedró, Marta; Pallarès, Jofre; Loffredo, Fausta; Villani, Fulvia; Gomes, Henrique L; Terés, Lluís; Baumann, Reinhard R

2016-09-21

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

NASA Technical Reports Server (NTRS)

Mueller, Carl; Alterovitz, Samuel; Croke, Edward; Ponchak, George

2004-01-01

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

NASA Astrophysics Data System (ADS)

Tajima, Takuro; Kosugi, Toshihiko; Song, Ho-Jin; Hamada, Hiroshi; El Moutaouakil, Amine; Sugiyama, Hiroki; Matsuzaki, Hideaki; Yaita, Makoto; Kagami, Osamu

2016-12-01

Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm3. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.

Room temperature bonding and debonding of polyimide film and glass substrate based on surface activate bonding method

NASA Astrophysics Data System (ADS)

Takeuchi, Kai; Fujino, Masahisa; Matsumoto, Yoshiie; Suga, Tadatomo

2018-02-01

The temporary bonding of polyimide (PI) films and glass substrates is a key technology for realizing flexible devices with thin-film transistors (TFTs). In this paper, we report the surface activated bonding (SAB) method using Si intermediate layers and its bonding and debonding mechanisms after heating. The bonding interface composed of Si and Fe shows a higher bond strength than the interface of only Si, while the bond strengths of both interfaces decrease with post bonding heating. It is also clarified by composition analysis on the debonded surfaces and cross-sectional observation of the bonding interface that the bond strength depends on the toughness of the intermediated layers and PI. The SAB method using Si intermediate layers is found to be applicable to the bonding and debonding of PI and glass.

Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits

NASA Astrophysics Data System (ADS)

Sutton, Akil K.

Hydrocarbon exploration, global navigation satellite systems, computed tomography, and aircraft avionics are just a few examples of applications that require system operation at an ambient temperature, pressure, or radiation level outside the range covered by military specifications. The electronics employed in these applications are known as "extreme environment electronics." On account of the increased cost resulting from both process modifications and the use of exotic substrate materials, only a handful of semiconductor foundries have specialized in the production of extreme environment electronics. Protection of these electronic systems in an extreme environment may be attained by encapsulating sensitive circuits in a controlled environment, which provides isolation from the hostile ambient, often at a significant cost and performance penalty. In a significant departure from this traditional approach, system designers have begun to use commercial off-the-shelf technology platforms with built in mitigation techniques for extreme environment applications. Such an approach simultaneously leverages the state of the art in technology performance with significant savings in project cost. Silicon-germanium is one such commercial technology platform that demonstrates potential for deployment into extreme environment applications as a result of its excellent performance at cryogenic temperatures, remarkable tolerance to radiation-induced degradation, and monolithic integration with silicon-based manufacturing. In this dissertation the radiation response of silicon-germanium technology is investigated, and novel transistor-level layout-based techniques are implemented to improve the radiation tolerance of HBT digital logic.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Three-Dimensional Printed Poly(vinyl alcohol) Substrate with Controlled On-Demand Degradation for Transient Electronics.

PubMed

Yoon, Jinsu; Han, Jungmin; Choi, Bongsik; Lee, Yongwoo; Kim, Yeamin; Park, Jinhee; Lim, Meehyun; Kang, Min-Ho; Kim, Dae Hwan; Kim, Dong Myong; Kim, Sungho; Choi, Sung-Jin

2018-05-25

Electronics that degrade after stable operation for a desired operating time, called transient electronics, are of great interest in many fields, including biomedical implants, secure memory devices, and environmental sensors. Thus, the development of transient materials is critical for the advancement of transient electronics and their applications. However, previous reports have mostly relied on achieving transience in aqueous solutions, where the transience time is largely predetermined based on the materials initially selected at the beginning of the fabrication. Therefore, accurate control of the transience time is difficult, thereby limiting their application. In this work, we demonstrate transient electronics based on a water-soluble poly(vinyl alcohol) (PVA) substrate on which carbon nanotube (CNT)-based field-effect transistors were fabricated. We regulated the structural parameters of the PVA substrate using a three-dimensional (3D) printer to accurately control and program the transience time of the PVA substrate in water. The 3D printing technology can produce complex objects directly, thus enabling the efficient fabrication of a transient substrate with a prescribed and controlled transience time. In addition, the 3D printer was used to develop a facile method for the selective and partial destruction of electronics.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Silicone substrate with in situ strain relief for stretchable thin-film transistors

NASA Astrophysics Data System (ADS)

Graz, Ingrid M.; Cotton, Darryl P. J.; Robinson, Adam; Lacour, Stéphanie P.

2011-03-01

We have manufactured stretchable thin-film transistors and interconnects directly onto an engineered silicone matrix with localized and graded mechanical compliance. The fabrication only involves planar and standard processing. Brittle active device materials are patterned on non deformable elastomer regions (strain <1% at all times) while interconnects run smoothly from "stiff" to "soft" elastomer. Pentacene thin-film transistors sustain applied strain up to 13% without electrical degradation and mechanical fracture. This integrated approach opens promising options for the manufacture of physically adaptable and transformable circuitry.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Charge movement in a GaN-based hetero-structure field effect transistor structure with carbon doped buffer under applied substrate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pooth, Alexander, E-mail: a.pooth@bristol.ac.uk; IQE; Uren, Michael J.

2015-12-07

Charge trapping and transport in the carbon doped GaN buffer of a GaN-based hetero-structure field effect transistor (HFET) has been investigated under both positive and negative substrate bias. Clear evidence of redistribution of charges in the carbon doped region by thermally generated holes is seen, with electron injection and capture observed during positive bias. Excellent agreement is found with simulations. It is shown that these effects are intrinsic to the carbon doped GaN and need to be controlled to provide reliable and efficient GaN-based power HFETs.

Interband Lateral Resonant Tunneling Transistor.

DTIC Science & Technology

1994-11-14

INTERBAND LATERAL RESONANT TUNNELING TRANSISTOR 10 BACKGROUND OF THE INVENTION Field of the Invention This invention pertains to a tunneling transistor...and in 15 particular to an interband lateral resonant tunneling transistor. Description of Related Art Conventional semiconductor technologies are... interband lateral resonant tunneling transistor along the cross-section B-B of Figure 2c. Figure 4 is another preferred embodiment cross-sectional 20

Fabrication of air-stable n-type carbon nanotube thin-film transistors on flexible substrates using bilayer dielectrics.

PubMed

Li, Guanhong; Li, Qunqing; Jin, Yuanhao; Zhao, Yudan; Xiao, Xiaoyang; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2015-11-14

Single-walled carbon nanotube (SWNT) thin-film transistors hold great potential for flexible electronics. However, fabrication of air-stable n-type devices by methods compatible with standard photolithography on flexible substrates is challenging. Here, we demonstrated that by using a bilayer dielectric structure of MgO and atomic layer deposited (ALD) Al2O3 or HfO2, air-stable n-type devices can be obtained. The mechanism for conduction type conversion was elucidated and attributed to the hole depletion in SWNT, the decrease of the trap state density by MgO assimilating adsorbed water molecules in the vicinity of SWNT, and the energy band bending because of the positive fixed charges in the ALD layer. The key advantage of the method is the relatively low temperature (120 or 90 °C) required here for the ALD process because we need not employ this step to totally remove the absorbates on the SWNTs. This advantage facilitates the integration of both p-type and n-type transistors through a simple lift off process and compact CMOS inverters were demonstrated. We also demonstrated that the doping of SWNTs in the channel plays a more important role than the Schottky barriers at the metal contacts in carbon nanotube thin-film transistors, unlike the situation in individual SWNT-based transistors.

Strained InGaAs/InAlAs Quantum Wells for Complementary III-V Transistors

DTIC Science & Technology

2014-01-01

GaAs substrates for low power and high frequency applications, J. Appl. Phys. 109 (2011) 033706. [28] A. Ali, H. Madan , A. Agrawal, I. Ramirez, R...Growth of InAsSb-channel high electron mobility transistor structures, J. Vac. Sci. Technol. B 23 (2005) 1441–1444. [30] A. Ali, H. Madan , M.J

High-mobility field-effect transistor based on crystalline ZnSnO3 thin films

NASA Astrophysics Data System (ADS)

Minato, Hiroya; Fujiwara, Kohei; Tsukazaki, Atsushi

2018-05-01

We propose crystalline ZnSnO3 as a new channel material for field-effect transistors. By molecular-beam epitaxy on LiNbO3(0001) substrates, we synthesized films of ZnSnO3, which crystallizes in the LiNbO3-type polar structure. Field-effect transistors on ZnSnO3 exhibit n-type operation with field-effect mobility of as high as 45 cm2V-1s-1 at room temperature. Systematic examination of the transistor operation for channels with different Zn/Sn compositional ratios revealed that the observed high-mobility reflects the nature of stoichiometric ZnSnO3 phase. Moreover, we found an indication of coupling of transistor characteristics with intrinsic spontaneous polarization in ZnSnO3, potentially leading to a distinct type of polarization-induced conduction.

Quantum engineering of transistors based on 2D materials heterostructures

NASA Astrophysics Data System (ADS)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Quantum engineering of transistors based on 2D materials heterostructures.

PubMed

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Si and Mg pair-doped interlayers for improving performance of AlGaN/GaN heterostructure field effect transistors grown on Si substrate

NASA Astrophysics Data System (ADS)

Ni, Yi-Qiang; He, Zhi-Yuan; Yao, Yao; Yang, Fan; Zhou, De-Qiu; Zhou, Gui-Lin; Shen, Zhen; Zhong, Jian; Zheng, Yue; Zhang, Bai-Jun; Liu, Yang

2015-05-01

We report a novel structure of AlGaN/GaN heterostructure field effect transistors (HFETs) with a Si and Mg pair-doped interlayer grown on Si substrate. By optimizing the doping concentrations of the pair-doped interlayers, the mobility of 2DEG increases by twice for the conventional structure under 5 K due to the improved crystalline quality of the conduction channel. The proposed HFET shows a four orders lower off-state leakage current, resulting in a much higher on/off ratio (˜ 109). Further temperature-dependent performance of Schottky diodes revealed that the inhibition of shallow surface traps in proposed HFETs should be the main reason for the suppression of leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 51177175 and 61274039), the National Basic Research Project of China (Grant Nos. 2010CB923200 and 2011CB301903), the Ph.D. Program Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Sci. & Tech. Collaboration Program of China (Grant No. 2012DFG52260), the National High-tech R&D Program of China (Grant No. 2014AA032606), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics (Grant No. IOSKL2014KF17).

Low thermal budget annealing technique for high performance amorphous In-Ga-ZnO thin film transistors

NASA Astrophysics Data System (ADS)

Shin, Joong-Won; Cho, Won-Ju

2017-07-01

In this paper, we investigate a low thermal budget post-deposition-annealing (PDA) process for amorphous In-Ga-ZnO (a-IGZO) oxide semiconductor thin-film-transistors (TFTs). To evaluate the electrical characteristics and reliability of the TFTs after the PDA process, microwave annealing (MWA) and rapid thermal annealing (RTA) methods were applied, and the results were compared with those of the conventional annealing (CTA) method. The a-IGZO TFTs fabricated with as-deposited films exhibited poor electrical characteristics; however, their characteristics were improved by the proposed PDA process. The CTA-treated TFTs had excellent electrical properties and stability, but the CTA method required high temperatures and long processing times. In contrast, the fabricated RTA-treated TFTs benefited from the lower thermal budget due to the short process time; however, they exhibited poor stability. The MWA method uses a low temperature (100 °C) and short annealing time (2 min) because microwaves transfer energy directly to the substrate, and this method effectively removed the defects in the a-IGZO TFTs. Consequently, they had a higher mobility, higher on-off current ratio, lower hysteresis voltage, lower subthreshold swing, and higher interface trap density than TFTs treated with CTA or RTA, and exhibited excellent stability. Based on these results, low thermal budget MWA is a promising technology for use on various substrates in next generation displays.

Sensing properties of separative paper-based extended-gate ion-sensitive field-effect transistor for cost effective pH sensor applications

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Lim, Cheol-Min

2018-02-01

In this study, we developed a cost-effective ion-sensing field-effect transistor (FET) with an extended gate (EG) fabricated on a separative paper substrate. The pH sensing characteristics of the paper EG was compared with those of other EGs fabricated on silicon, glass, or polyimide substrates. The fabricated paper-based EGFET exhibited excellent sensitivity close to the Nernst response limit as well as to that of the other substrate-based EGFETs. In addition, we found that all EGFETs, regardless of the substrate, have similar non-ideal behavior, i.e., drift phenomenon and hysteresis width. To investigate the degradation and durability of the paper EG after prolonged use, aging-effect tests were carried out in terms of the hysteresis width and sensitivity over a course of 30 days. As a result, the paper EG maintained stable pH sensing characteristics after 30 days. Therefore, we expect that paper EGFETs can provide a cost-effective sensor platform.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs).

PubMed

Kumar, Annie; Lee, Shuh-Ying; Yadav, Sachin; Tan, Kian Hua; Loke, Wan Khai; Dong, Yuan; Lee, Kwang Hong; Wicaksono, Satrio; Liang, Gengchiau; Yoon, Soon-Fatt; Antoniadis, Dimitri; Yeo, Yee-Chia; Gong, Xiao

2017-12-11

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an I ON /I OFF ratio of more than 10 6 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

ISFET Based Microsensors for Environmental Monitoring

PubMed Central

Jimenez-Jorquera, Cecilia; Orozco, Jahir; Baldi, Antoni

2010-01-01

The use of microsensors for in-field monitoring of environmental parameters is gaining interest due to their advantages over conventional sensors. Among them microsensors based on semiconductor technology offer additional advantages such as small size, robustness, low output impedance and rapid response. Besides, the technology used allows integration of circuitry and multiple sensors in the same substrate and accordingly they can be implemented in compact probes for particular applications e.g., in situ monitoring and/or on-line measurements. In the field of microsensors for environmental applications, Ion Selective Field Effect Transistors (ISFETs) have a special interest. They are particularly helpful for measuring pH and other ions in small volumes and they can be integrated in compact flow cells for continuous measurements. In this paper the technologies used to fabricate ISFETs and a review of the role of ISFETs in the environmental field are presented. PMID:22315527

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

PubMed

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

PubMed

Moon, Kyeong-Ju; Lee, Tae-Il; Lee, Sang-Hoon; Han, Young-Uk; Ham, Moon-Ho; Myoung, Jae-Min

2012-07-25

A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

Direct measurement of density of states in pentacene thin film transistors

NASA Astrophysics Data System (ADS)

Yogev, S.; Halpern, E.; Matsubara, R.; Nakamura, M.; Rosenwaks, Y.

2011-10-01

We report on direct high lateral resolution measurements of density of states in pentacene thin film transistors using Kelvin probe force microscopy. The measurements were conducted on passivated (hexamethyldisilazane) and unpassivated field effect transistors with 10- and 30-nm-thick pentacene polycrystalline layers. The analysis takes into account both the band bending in the organic film and the trapped charge at the SiO2-pentacene interface. We found that the density of states for the highest occupied molecular orbital band of pentacene film on the treated substrate is Gaussian with a width (variance) of σ=0.07±0.01eV and an exponential tail. The concentration of the density of states in the gap for pentacene on bare SiO2 substrate was larger by one order of magnitude, had a different energy distribution, and induced Fermi level pinning. The results are discussed in view of their effect on pentacene thin film transistors’ performance.

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.; Ponchak, George E.

2004-01-01

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony concentration was approximately 4 x 10(exp 19) per cubic centimeter. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per square centimeter, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V (sub DS)) range, with V (sub DS) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer

PubMed Central

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-01-01

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm2/Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 105. Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles. PMID:27876893

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer.

PubMed

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; Kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-11-23

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O 2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm 2 /Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 10 5 . Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles.

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Indirect X-ray Detectors Based on Inkjet-Printed Photodetectors with a Screen-Printed Scintillator Layer.

PubMed

Oliveira, Juliana; Correia, Vitor; Sowade, Enrico; Etxebarria, Ikerne; Rodriguez, Raul D; Mitra, Kalyan Y; Baumann, Reinhard R; Lanceros-Mendez, Senentxu

2018-04-18

Organic photodetectors (PDs) based on printing technologies will allow to expand the current field of PD applications toward large-area and flexible applications in areas such as medical imaging, security, and quality control, among others. Inkjet printing is a powerful digital tool for the deposition of smart and functional materials on various substrates, allowing the development of electronic devices such as PDs on various substrates. In this work, inkjet-printed PD arrays, based on the organic thin-film transistor architecture, have been developed and applied for the indirect detection of X-ray radiation using a scintillator ink as an X-ray absorber. The >90% increase of the photocurrent of the PDs under X-ray radiation, from about 53 nA without the scintillator film to about 102 nA with the scintillator located on top of the PD, proves the suitability of the developed printed device for X-ray detection applications.

Planar resonator and integrated oscillator using magnetostatic waves.

PubMed

Kinoshita, Y; Kubota, S; Takeda, S; Nakagoshi, A

1990-01-01

A simple planar resonator using a magnetostatic wave (MSW) excited by aluminum finger electrodes with two bonding pads was realized on YIG/GGG (yttrium-iron-garnet film on a gadolinium-gallium-garnet crystal) substrate with two reflection edges. The tunable MSW resonator chip (2 mmx5 mm) exhibited a sharp notch filter response, as deep as 20-35 dB, and a high loaded Q up to 2000, which was tunable over the microwave frequency range from 2 to 4 GHz. A small tunable oscillator (8 cm(3)) was experimentally demonstrated using the MSW planar resonator and a silicon bipolar transistor integrated on a ceramic microwave circuit substrate. Microwave oscillation with spectral purity, at the same level as that of YIG sphere technology, was observed at 3 GHz. The experimental results indicate the technical areas where improvement must be made to realize a practical oscillator configuration.

C-band superconductor/semiconductor hybrid field-effect transistor amplifier on a LaAlO3 substrate

NASA Technical Reports Server (NTRS)

Nahra, J. J.; Bhasin, K. B.; Toncich, S. S.; Subramanyam, G.; Kapoor, V. J.

1992-01-01

A single-stage C-band superconductor/semiconductor hybrid field-effect transistor amplifier was designed, fabricated, and tested at 77 K. The large area (1 inch x 0.5 inches) high temperature superconducting Tl-Ba-Ca-Cu-O (TBCCO) thin film was rf magnetron sputtered onto a LaAlO3 substrate. The film had a transition temperature of about 92 K after it was patterned and etched. The amplifier showed a gain of 6 dB and a 3 dB bandwidth of 100 MHz centered at 7.9 GHz. An identical gold amplifier circuit was tested at 77 K, and these results are compared with those from the hybrid amplifier.

Study of InGaAs-based modulation doped field effect transistor structures using variable-angle spectroscopic ellipsometry

NASA Technical Reports Server (NTRS)

Alterovitz, S. A.; Sieg, R. M.; Yao, H. D.; Snyder, P. G.; Woollam, J. A.; Pamulapati, J.; Bhattacharya, P. K.; Sekula-Moise, P. A.

1991-01-01

Variable-angle spectroscopic ellipsometry was used to estimate the thicknesses of all layers within the optical penetration depth of InGaAs-based modulation doped field effect transistor structures. Strained and unstrained InGaAs channels were made by molecular beam epitaxy (MBE) on InP substrates and by metal-organic chemical vapor deposition on GaAs substrates. In most cases, ellipsometrically determined thicknesses were within 10% of the growth-calibration results. The MBE-made InGaAs strained layers showed large strain effects, indicating a probable shift in the critical points of their dielectric function toward the InP lattice-matched concentration.

Nanoparticle Selective Laser Processing for a Flexible Display Fabrication

NASA Astrophysics Data System (ADS)

Seung Hwan Ko,; Heng Pan,; Daeho Lee,; Costas P. Grigoropoulos,; Hee K. Park,

2010-05-01

To demonstrate a first step for a novel fabrication method of a flexible display, nanomaterial based laser processing schemes to demonstrate organic light emitting diode (OLED) pixel transfer and organic field effect transistor (OFET) fabrication on a polymer substrate without using any conventional vacuum or photolithography processes were developed. The unique properties of nanomaterials allow laser induced forward transfer of organic light emitting material at low laser energy while maintaining good fluorescence and also allow high resolution transistor electrode patterning at plastic compatible low temperature. These novel processes enable an environmentally friendly and cost effective process as well as a low temperature manufacturing sequence to realize inexpensive, large area, flexible electronics on polymer substrates.

SOI MESFETs on high-resistivity, trap-rich substrates

NASA Astrophysics Data System (ADS)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

High performance organic transistor active-matrix driver developed on paper substrate

NASA Astrophysics Data System (ADS)

Peng, Boyu; Ren, Xiaochen; Wang, Zongrong; Wang, Xinyu; Roberts, Robert C.; Chan, Paddy K. L.

2014-09-01

The fabrication of electronic circuits on unconventional substrates largely broadens their application areas. For example, green electronics achieved through utilization of biodegradable or recyclable substrates, can mitigate the solid waste problems that arise at the end of their lifespan. Here, we combine screen-printing, high precision laser drilling and thermal evaporation, to fabricate organic field effect transistor (OFET) active-matrix (AM) arrays onto standard printer paper. The devices show a mobility and on/off ratio as high as 0.56 cm2V-1s-1 and 109 respectively. Small electrode overlap gives rise to a cut-off frequency of 39 kHz, which supports that our AM array is suitable for novel practical applications. We demonstrate an 8 × 8 AM light emitting diode (LED) driver with programmable scanning and information display functions. The AM array structure has excellent potential for scaling up.

A pH sensor based on electric properties of nanotubes on a glass substrate

PubMed Central

Nakamura, Motonori; Ishii, Atsushi; Subagyo, Agus; Hosoi, Hirotaka; Sueoka, Kazuhisa; Mukasa, Koichi

2007-01-01

We fabricated a pH-sensitive device on a glass substrate based on properties of carbon nanotubes. Nanotubes were immobilized specifically on chemically modified areas on a substrate followed by deposition of metallic source and drain electrodes on the area. Some nanotubes connected the source and drain electrodes. A top gate electrode was fabricated on an insulating layer of silane coupling agent on the nanotube. The device showed properties of ann-type field effect transistor when a potential was applied to the nanotube from the top gate electrode. Before fabrication of the insulating layer, the device showed that thep-type field effect transistor and the current through the source and drain electrodes depend on the buffer pH. The current increases with decreasing pH of the CNT solution. This device, which can detect pH, is applicable for use as a biosensor through modification of the CNT surface. PMID:21806848

Fabrication and Characterization of Fully Transparent ZnO Thin-Film Transistors and Self-Switching Nano-Diodes

NASA Astrophysics Data System (ADS)

Sun, Y.; Ashida, K.; Sasaki, S.; Koyama, M.; Maemoto, T.; Sasa, S.; Kasai, S.; Iñiguez-de-la-Torre, I.; González, T.

2015-10-01

Fully transparent zinc oxide (ZnO) based thin-film transistors (TFTs) and a new type of rectifiers calls self-switching nano-diodes (SSDs) were fabricated on glass substrates at room temperature by using low resistivity and transparent conducting Al- doped ZnO (AZO) thin-films. The deposition conditions of AZO thin-films were optimized with pulsed laser deposition (PLD). AZO thin-films on glass substrates were characterized and the transparency of 80% and resistivity with 1.6*10-3 Ωcm were obtained of 50 nm thickness. Transparent ZnO-TFTs were fabricated on glass substrates by using AZO thin-films as electrodes. A ZnO-TFT with 2 μm long gate device exhibits a transconductance of 400 μS/mm and an ON/OFF ratio of 2.8*107. Transparent ZnO-SSDs were also fabricated by using ZnO based materials and clear diode-like characteristics were observed.

Titanyl phthalocyanine ambipolar thin film transistors making use of carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Coppedè, Nicola; Valitova, Irina; Mahvash, Farzaneh; Tarabella, Giuseppe; Ranzieri, Paolo; Iannotta, Salvatore; Santato, Clara; Martel, Richard; Cicoira, Fabio

2014-12-01

The capability of efficiently injecting charge carriers into organic films and finely tuning their morphology and structure is crucial to improve the performance of organic thin film transistors (OTFTs). In this work, we investigate OTFTs employing carbon nanotubes (CNTs) as the source-drain electrodes and, as the organic semiconductor, thin films of titanyl phthalocyanine (TiOPc) grown by supersonic molecular beam deposition (SuMBD). While CNT electrodes have shown an unprecedented ability to improve charge injection in OTFTs, SuMBD is an effective technique to tune film morphology and structure. Varying the substrate temperature during deposition, we were able to grow both amorphous (low substrate temperature) and polycrystalline (high substrate temperature) films of TiOPc. Regardless of the film morphology and structure, CNT electrodes led to superior charge injection and transport performance with respect to benchmark Au electrodes. Vacuum annealing of polycrystalline TiOPc films with CNT electrodes yielded ambipolar OTFTs.

High performance organic transistor active-matrix driver developed on paper substrate

PubMed Central

Peng, Boyu; Ren, Xiaochen; Wang, Zongrong; Wang, Xinyu; Roberts, Robert C.; Chan, Paddy K. L.

2014-01-01

The fabrication of electronic circuits on unconventional substrates largely broadens their application areas. For example, green electronics achieved through utilization of biodegradable or recyclable substrates, can mitigate the solid waste problems that arise at the end of their lifespan. Here, we combine screen-printing, high precision laser drilling and thermal evaporation, to fabricate organic field effect transistor (OFET) active-matrix (AM) arrays onto standard printer paper. The devices show a mobility and on/off ratio as high as 0.56 cm2V−1s−1 and 109 respectively. Small electrode overlap gives rise to a cut-off frequency of 39 kHz, which supports that our AM array is suitable for novel practical applications. We demonstrate an 8 × 8 AM light emitting diode (LED) driver with programmable scanning and information display functions. The AM array structure has excellent potential for scaling up. PMID:25234244

Optical and Interface-Based Methods of Defect Engineering in Silicon

ERIC Educational Resources Information Center

Kondratenko, Yevgeniy Vladimirovich

2009-01-01

Ion implantation is widely used in the microelectronics industry for fabrication of source and drain transistor regions. Unfortunately, implantation causes considerable damage to the substrate lattice rendering most of the implanted dopant electrically inactive. Rapid thermal annealing (RTA) heals the damage by rapidly heating the substrate with a…

Ultrasensitive label-free detection of DNA hybridization by sapphire-based graphene field-effect transistor biosensor

NASA Astrophysics Data System (ADS)

Xu, Shicai; Jiang, Shouzhen; Zhang, Chao; Yue, Weiwei; Zou, Yan; Wang, Guiying; Liu, Huilan; Zhang, Xiumei; Li, Mingzhen; Zhu, Zhanshou; Wang, Jihua

2018-01-01

Graphene has attracted much attention in biosensing applications for its unique properties. Because of one-atom layer structure, every atom of graphene is exposed to the environment, making the electronic properties of graphene are very sensitive to charged analytes. Therefore, graphene is an ideal material for transistors in high-performance sensors. Chemical vapor deposition (CVD) method has been demonstrated the most successful method for fabricating large area graphene. However, the conventional CVD methods can only grow graphene on metallic substrate and the graphene has to be transferred to the insulating substrate for further device fabrication. The transfer process creates wrinkles, cracks, or tears on the graphene, which severely degrade electrical properties of graphene. These factors severely degrade the sensing performance of graphene. Here, we directly fabricated graphene on sapphire substrate by high temperature CVD without the use of metal catalysts. The sapphire-based graphene was patterned and make into a DNA biosensor in the configuration of field-effect transistor. The sensors show high performance and achieve the DNA detection sensitivity as low as 100 fM (10-13 M), which is at least 10 times lower than prior transferred CVD G-FET DNA sensors. The use of the sapphire-based G-FETs suggests a promising future for biosensing applications.

Modeling of short channel MOS transistors

NASA Technical Reports Server (NTRS)

Lin, H. C.; Kokalis, D. P.; Bandy, W. R.

1976-01-01

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Organic Field Effect Transistors for Large Format Electronics

DTIC Science & Technology

2003-06-19

calculated output characteristics for a p-channel substrate insulator Organic layer Source Drain Gate 6 pentacene OFET with 2µm source to drain spacing...conventional transistors. Figure 3. Calculated output characteristics of a pentacene OFET with image charge induced contact barrier...Cross section view of a part of an OFET in the vicinity of a source or drain contact. local ordering due to surface energy effects. The development of

Transport Mechanisms in Organic Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fung, A. W. P.

1996-03-01

Recent success in fabricating field-effect transistors with polycrystalline α-sexithiophene (α-6T) has allowed us to study charge transport in this organic semiconductor. The appealing structural property that the oligomer chains are seated almost perpendicular to the substrate provides a model π-conjugated system which we find exhibits band transport at low temperatures. We observe a behavioral transition around 50K which is consistent with the metal-insulator transition in Holstein's small-polaron theory. The fact that we can observe intrinsic behavior means that the ambient-temperature mobility obtained in these transistors is optimal for α-6T. Agreement with the Holstein theory provides us with a prescription for rational design of materials for organic transistor applications. Work done in collaboration with L. Torsi, A. Dodabalapur, L. J. Rothberg and H. E. Katz.

The 2018 GaN power electronics roadmap

NASA Astrophysics Data System (ADS)

Amano, H.; Baines, Y.; Beam, E.; Borga, Matteo; Bouchet, T.; Chalker, Paul R.; Charles, M.; Chen, Kevin J.; Chowdhury, Nadim; Chu, Rongming; De Santi, Carlo; Merlyne De Souza, Maria; Decoutere, Stefaan; Di Cioccio, L.; Eckardt, Bernd; Egawa, Takashi; Fay, P.; Freedsman, Joseph J.; Guido, L.; Häberlen, Oliver; Haynes, Geoff; Heckel, Thomas; Hemakumara, Dilini; Houston, Peter; Hu, Jie; Hua, Mengyuan; Huang, Qingyun; Huang, Alex; Jiang, Sheng; Kawai, H.; Kinzer, Dan; Kuball, Martin; Kumar, Ashwani; Boon Lee, Kean; Li, Xu; Marcon, Denis; März, Martin; McCarthy, R.; Meneghesso, Gaudenzio; Meneghini, Matteo; Morvan, E.; Nakajima, A.; Narayanan, E. M. S.; Oliver, Stephen; Palacios, Tomás; Piedra, Daniel; Plissonnier, M.; Reddy, R.; Sun, Min; Thayne, Iain; Torres, A.; Trivellin, Nicola; Unni, V.; Uren, Michael J.; Van Hove, Marleen; Wallis, David J.; Wang, J.; Xie, J.; Yagi, S.; Yang, Shu; Youtsey, C.; Yu, Ruiyang; Zanoni, Enrico; Zeltner, Stefan; Zhang, Yuhao

2018-04-01

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Very low temperature materials and self-alignment technology for amorphous hydrated silicon thin film transistors fabricated on transparent large area plastic substrates

NASA Astrophysics Data System (ADS)

Yang, Chien-Sheng

The purpose of this research has been to (1) explore materials prepared using plasma enhanced chemical vapor deposition (PECVD) at 110sp°C for amorphous silicon thin film transistors (TFT's) fabricated on low temperature compatible, large area flexible polyethylene terephthalate (PET) substrates, and (2) develop full self-alignment technology using selective area n+ PECVD for source/drain contacts of amorphous silicon TFT's. For item (1), silicon nitride films, as gate dielectrics of TFT's, were deposited using SiHsb4+NHsb3, SiHsb4+NHsb3+Nsb2, SiHsb4+NHsb3+He, or SiHsb4+NHsb3+Hsb2 gases. Good quality silicon nitride films can be deposited using a SiHsb4+NHsb3 gas with high NHsb3/SiHsb4 ratios, or using a SiHsb4+NHsb3+Nsb2 gas with moderate NHsb3/SiHsb4 ratios. A chemical model was proposed to explain the Nsb2 dilution effect. This model includes calculations of (a) the electron energy distribution function in a plasma, (b) rate constants of electron impact dissociation, and (3) the (NHsbx) / (SiHsby) ratio in a plasma. The Nsb2 dilution was shown to have a effect of shifting the electron energy distribution into high energy, thus enhancing the (NHsbx) / (SiHsbyrbrack ratio in a plasma and promoting the deposition of N-rich silicon nitride films, which leads to decreased trap state density and a shift in trap state density to deeper in the gap. Amorphous silicon were formed successfully at 110sp°C on large area glass and plastic(PET) substrates. Linear mobilities are 0.33 and 0.12 cmsp2/Vs for TFT's on glass and plastic substrates, respectively. ON/OFF current ratios exceed 10sp7 for TFT's on glass and 10sp6 for TFT's on PET. For item (2), a novel full self-alignment process was developed for amorphous silicon TFT's. This process includes (1) back-exposure using the bottom gate metal as the mask, and (2) selective area n+ micro-crystalline silicon PECVD for source/drain contacts of amorphous silicon TFT's. TFT's fabricated using the full self-alignment process showed linear mobilities ranging from 0.5 to 1.0 cmsp2/Vs.

Highly Robust Neutral Plane Oxide TFTs Withstanding 0.25 mm Bending Radius for Stretchable Electronics

PubMed Central

Kim, Yong-Hwan; Lee, Eunji; Um, Jae Gwang; Mativenga, Mallory; Jang, Jin

2016-01-01

Advancements in thin-film transistor (TFT) technology have extended to electronics that can withstand extreme bending or even folding. Although the use of ultrathin plastic substrates has achieved considerable advancement towards this end, free-standing ultrathin plastics inevitably suffer from mechanical instability and are very difficult to handle during TFT fabrication. Here, in addition to the use of a 1.5 μm-thick polyimide (PI) substrate, a 1.5 μm-thick PI film is also deposited on top of the TFT devices to ensure that the devices are located at the neutral plane of the two PI films for high folding stability. For mechanical support during TFT fabrication up to the deposition of the top PI film, the PI substrate is spin coated on top of a carrier glass that is coated with a mixture of carbon nanotubes (CNTs) and graphene oxide (GO). The mixture of CNT and GO facilitates mechanical detachment of the neutral plane (NP) TFTs from the carrier glass before they are transferred to a polydimethylsiloxane (PDMS) substrate as islands. Being located in the neutral bending plane, the NP TFT can be transferred to the PDMS without performance degradation and exhibit excellent mechanical stability after stretching the PDMS substrate up to a 25% elastic elongation. PMID:27165715

Advanced technology component derating

NASA Astrophysics Data System (ADS)

Jennings, Timothy A.

1992-02-01

A technical study performed to determine the derating criteria of advanced technology components is summarized. The study covered existing criteria from AFSC Pamphlet 800-27 and the development of new criteria based on data, literature searches, and the use of advanced technology prediction methods developed in RADC-TR-90-72. The devices that were investigated were as follows: VHSIC, ASIC, MIMIC, Microprocessor, PROM, Power Transistors, RF Pulse Transistors, RF Multi-Transistor Packages, Photo Diodes, Photo Transistors, Opto-Electronic Couplers, Injection Laser Diodes, LED, Hybrid Deposited Film Resistors, Chip Resistors, and Capacitors and SAW devices. The results of the study are additional derating criteria that extend the range of AFSC Pamphlet 800-27. These data will be transitioned from the report to AFSC Pamphlet 800-27 for use by government and contractor personnel in derating electronics systems yielding increased safety margins and improved system reliability.

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application.

PubMed

Liang, Xuelei; Xia, Jiye; Dong, Guodong; Tian, Boyuan; Peng, Lianmao

2016-12-01

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

Structure and properties of small molecule-polymer blend semiconductors for organic thin film transistors.

PubMed

Kang, Jihoon; Shin, Nayool; Jang, Do Young; Prabhu, Vivek M; Yoon, Do Y

2008-09-17

A comprehensive structural and electrical characterization of solution-processed blend films of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) semiconductor and poly(alpha-methylstyrene) (PalphaMS) insulator was performed to understand and optimize the blend semiconductor films, which are very attractive as the active layer in solution-processed organic thin-film transistors (OTFTs). Our study, based on careful measurements of specular neutron reflectivity and grazing-incidence X-ray diffraction, showed that the blends with a low molecular-mass PalphaMS exhibited a strong segregation of TIPS-pentacene only at the air interface, but surprisingly the blends with a high molecular-mass PalphaMS showed a strong segregation of TIPS-pentacene at both air and bottom substrate interfaces with high crystallinity and desired orientation. This finding led to the preparation of a TIPS-pentacene/PalphaMS blend active layer with superior performance characteristics (field-effect mobility, on/off ratio, and threshold voltage) over those of neat TIPS-pentacene, as well as the solution-processability of technologically attractive bottom-gate/bottom-contact OTFT devices.

Direct Inkjet Printing of Silver Source/Drain Electrodes on an Amorphous InGaZnO Layer for Thin-Film Transistors

PubMed Central

Ning, Honglong; Chen, Jianqiu; Fang, Zhiqiang; Tao, Ruiqiang; Cai, Wei; Yao, Rihui; Hu, Shiben; Zhu, Zhennan; Zhou, Yicong; Yang, Caigui; Peng, Junbiao

2017-01-01

Printing technologies for thin-film transistors (TFTs) have recently attracted much interest owing to their eco-friendliness, direct patterning, low cost, and roll-to-roll manufacturing processes. Lower production costs could result if electrodes fabricated by vacuum processes could be replaced by inkjet printing. However, poor interfacial contacts and/or serious diffusion between the active layer and the silver electrodes are still problematic for achieving amorphous indium–gallium–zinc–oxide (a-IGZO) TFTs with good electrical performance. In this paper, silver (Ag) source/drain electrodes were directly inkjet-printed on an amorphous a-IGZO layer to fabricate TFTs that exhibited a mobility of 0.29 cm2·V−1·s−1 and an on/off current ratio of over 105. To the best of our knowledge, this is a major improvement for bottom-gate top-contact a-IGZO TFTs with directly printed silver electrodes on a substrate with no pretreatment. This study presents a promising alternative method of fabricating electrodes of a-IGZO TFTs with desirable device performance. PMID:28772410

Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

PubMed

Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

2013-01-01

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

Direct Inkjet Printing of Silver Source/Drain Electrodes on an Amorphous InGaZnO Layer for Thin-Film Transistors.

PubMed

Ning, Honglong; Chen, Jianqiu; Fang, Zhiqiang; Tao, Ruiqiang; Cai, Wei; Yao, Rihui; Hu, Shiben; Zhu, Zhennan; Zhou, Yicong; Yang, Caigui; Peng, Junbiao

2017-01-10

Printing technologies for thin-film transistors (TFTs) have recently attracted much interest owing to their eco-friendliness, direct patterning, low cost, and roll-to-roll manufacturing processes. Lower production costs could result if electrodes fabricated by vacuum processes could be replaced by inkjet printing. However, poor interfacial contacts and/or serious diffusion between the active layer and the silver electrodes are still problematic for achieving amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs with good electrical performance. In this paper, silver (Ag) source/drain electrodes were directly inkjet-printed on an amorphous a-IGZO layer to fabricate TFTs that exhibited a mobility of 0.29 cm²·V -1 ·s -1 and an on/off current ratio of over 10⁵. To the best of our knowledge, this is a major improvement for bottom-gate top-contact a-IGZO TFTs with directly printed silver electrodes on a substrate with no pretreatment. This study presents a promising alternative method of fabricating electrodes of a-IGZO TFTs with desirable device performance.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis

PubMed Central

Sowade, Enrico; Ramon, Eloi; Mitra, Kalyan Yoti; Martínez-Domingo, Carme; Pedró, Marta; Pallarès, Jofre; Loffredo, Fausta; Villani, Fulvia; Gomes, Henrique L.; Terés, Lluís; Baumann, Reinhard R.

2016-01-01

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement. PMID:27649784

Vertical field effect tunneling transistor based on graphene-ultrathin Si nanomembrane heterostructures

NASA Astrophysics Data System (ADS)

Das, Tanmoy; Jang, Houk; Bok Lee, Jae; Chu, Hyunwoo; Kim, Seong Dae; Ahn, Jong-Hyun

2015-12-01

Graphene-based heterostructured vertical transistors have attracted a great deal of research interest. Herein we propose a Si-based technology platform for creating graphene/ultrathin semiconductor/metal (GSM) junctions, which can be applied to large-scale and low-power electronics compatible with a variety of substrates. We fabricated graphene/Si nanomembrane (NM)/metal vertical heterostructures by using a dry transfer technique to transfer Si NMs onto chemical vapor deposition-grown graphene layers. The resulting van der Waals interfaces between graphene and p-Si NMs exhibited nearly ideal Schottky barrier behavior. Due to the low density of states of graphene, the graphene/Si NM Schottky barrier height can be modulated by modulating the band profile in the channel region, yielding well-defined current modulation. We obtained a maximum current on/off ratio (Ion/Ioff) of up to ˜103, with a current density of 102 A cm-2. We also observed significant dependence of Schottky barrier height Δφb on the thickness of the Si NMs. We confirmed that the transport in these devices is dominated by the effects of the graphene/Si NM Schottky barrier.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Graphene Field Effect Transistor for Radiation Detection

NASA Technical Reports Server (NTRS)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

NASA Astrophysics Data System (ADS)

Konwar, K.; Baishya, B.

2010-12-01

Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La2O3, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07×10-3 cm2V-1s-1 for the devices annealed in vacuum at 90° C for 5 hours.

Enhanced stability against bias-stress of metal-oxide thin film transistors deposited at elevated temperatures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakhri, M.; Goerrn, P.; Riedl, T.

2011-09-19

Transparent zinc-tin-oxide (ZTO) thin film transistors (TFTs) have been prepared by DC magnetron sputtering. Compared to reference devices with a channel deposited at room temperature and subsequently annealing at 400 deg. C, a substantially enhanced stability against bias stress is evidenced for devices with in-situ substrate heating during deposition (400 deg. C). A reduced density of sub-gap defect states in TFT channels prepared with in-situ substrate heating is found. Concomitantly, a reduced sensitivity to the adsorption of ambient gases is evidenced for the in-situ heated devices. This finding is of particular importance for an application as driver electronics for organicmore » light emitting diode displays.« less

High Mobility SiGe/Si n-Type Structures and Field Effect Transistors on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Ponchak, George E.; Mueller, Carl H.; Croke, Edward T.

2004-01-01

SiGe/Si n-type modulation doped field effect transistors (MODFETs) fabricated on sapphire substrates have been characterized at microwave frequencies for the first time. The highest measured room temperature electron mobility is 1380 sq cm/V-sec at a carrier density of 1.8 x 10(exp 12)/sq cm for a MODFET structure, and 900 sq cm/V-sec at a carrier density of 1.3 x 10/sq cm for a phosphorus ion implanted sample. A two finger, 2 x 200 micron gate n-MODFET has a peak transconductance of 37 mS/mm at a drain to source voltage of 2.5 V and a transducer gain of 6.4 dB at 1 GHz.

Application of the Johnson criteria to graphene transistors

NASA Astrophysics Data System (ADS)

Kelly, M. J.

2013-12-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications.

Oxide Based Transistor for Flexible Displays

DTIC Science & Technology

2014-09-15

thin film transistors (TFTs) for next generation display technologies. A detailed and comprehensive study was carried out to ascertain the process...Box 12211 Research Triangle Park, NC 27709-2211 Thin film transistors , flexible electronics, RF sputtering, Transparent amorphous oxide semiconductors...NC A&T and RTI, International investigated In free GaSnZnO (GSZO) material system, as the active channel in thin film transistors (TFTs) for next

Quantum Devices and Structures Using Si-Based Molecular Beam Epitaxy

DTIC Science & Technology

1991-05-15

the MBE growth studies of Sii_..,Ge./Si superlattices and the fabrication of resonant tunneling devices. 1 In the following we highlight the...relaxation was obtained.[7] A new approach in growth of strained layers on a patterned substrate was implemented. Permeable transistors and tunneling ...Fig. 5(b) shows a hot hole transistor using a superlattice base and resonant tunneling injector. In order to facilitate the design of such devices

Bistability in Doped Organic Thin Film Transistors (Preprint)

DTIC Science & Technology

2007-03-01

small molecules (e.g. pentacene ). As such, they do not necessarily compete with these more typical organic transistors, but rather have pertinence...involves dipping a substrate between two dilute polyelectrolyte solutions of opposite charge to build up a thin film via the electrostatic interactions...recovery is due to trapped O2(g) remaining in the film, which causes the reverse of reaction (1) to occur and the concomitant increase in the level of

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Fabrication of metal nanopatterns for organic field effect transistor electrodes by cracking and transfer printing

NASA Astrophysics Data System (ADS)

Wang, Xiaonan; Fu, Tingting; Wang, Zhe

2018-04-01

In this paper, we demonstrate a novel method for fabricating metal nanopatterns using cracking to address the limitations of traditional techniques. Parallel crack arrays were created in a polydimethylsiloxane (PDMS) mold using a combination of surface modification and control of strain fields. The elastic PDMS containing the crack arrays was subsequently used as a stamp to prepare nanoscale metal patterns on a substrate by transfer printing. To illustrate the functionality of this technique, we employed the metal patterns as the source and drain contacts of an organic field effect transistor. Using this approach, we fabricated transistors with channel lengths ranging from 70-600 nm. The performance of these devices when the channel length was reduced was studied. The drive current density increases as expected, indicating the creation of operational transistors with recognizable properties.

Influence of pre-annealing of printed silver electrodes on ultrafast laser ablation of short thin-film transistor channels on flexible substrates

NASA Astrophysics Data System (ADS)

Wiig, M. S.; You, C. C.; Brox-Nilsen, C.; Foss, S. E.

2018-02-01

The cutoff frequency and current from an organic thin-film transistor (OTFT) are strongly dependent on the length and to some extent on the uniformity of the transistor channel. Reducing the channel length can improve the OTFT performance with the increase in the current and frequency. Picosecond laser ablation of the printed Ag electrodes, compatible with roll-to-roll fabrication, has been investigated. The ablation threshold was found to be similar for the laser wavelengths tested: 515 nm and 1030 nm. Short transistor channels could be opened both after light annealing at 70 °C and after annealing at 140 °C. The channels in the lightly cured films had a significantly less scale formation, which is critical for avoiding shunts in the device. By moving from bottom electrodes fully defined by printing to the bottom electrodes where the transistor channel is opened by the laser, the channel length could be reduced from 40 μm to less than 5 μm.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

Strain-effect transistors: Theoretical study on the effects of external strain on III-nitride high-electron-mobility transistors on flexible substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shervin, Shahab; Asadirad, Mojtaba; Materials Science and Engineering Program, University of Houston, Houston, Texas 77204

This paper presents strain-effect transistors (SETs) based on flexible III-nitride high-electron-mobility transistors (HEMTs) through theoretical calculations. We show that the electronic band structures of InAlGaN/GaN thin-film heterostructures on flexible substrates can be modified by external bending with a high degree of freedom using polarization properties of the polar semiconductor materials. Transfer characteristics of the HEMT devices, including threshold voltage and transconductance, are controlled by varied external strain. Equilibrium 2-dimensional electron gas (2DEG) is enhanced with applied tensile strain by bending the flexible structure with the concave-side down (bend-down condition). 2DEG density is reduced and eventually depleted with increasing compressive strainmore » in bend-up conditions. The operation mode of different HEMT structures changes from depletion- to enchantment-mode or vice versa depending on the type and magnitude of external strain. The results suggest that the operation modes and transfer characteristics of HEMTs can be engineered with an optimum external bending strain applied in the device structure, which is expected to be beneficial for both radio frequency and switching applications. In addition, we show that drain currents of transistors based on flexible InAlGaN/GaN can be modulated only by external strain without applying electric field in the gate. The channel conductivity modulation that is obtained by only external strain proposes an extended functional device, gate-free SETs, which can be used in electro-mechanical applications.« less

Functional Na+ Channels in Cell Adhesion probed by Transistor Recording

PubMed Central

Schmidtner, Markus; Fromherz, Peter

2006-01-01

Cell membranes in a tissue are in close contact to each other, embedded in the extracellular matrix. Standard electrophysiological methods are not able to characterize ion channels under these conditions. Here we consider the area of cell adhesion on a solid substrate as a model system. We used HEK 293 cells cultured on fibronectin and studied the activation of NaV1.4 sodium channels in the adherent membrane with field-effect transistors in a silicon substrate. Under voltage clamp, we compared the transistor response with the whole-cell current. We observed that the extracellular voltage in the cell-chip contact was proportional to the total membrane current. The relation was calibrated by alternating-current stimulation. We found that Na+ channels are present in the area of cell adhesion on fibronectin with a functionality and a density that is indistinguishable from the free membrane. The experiment provides a basis for studying selective accumulation and depletion of ion channels in cell adhesion and also for a development of cell-based biosensoric devices and neuroelectronic systems. PMID:16227504

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

NASA Astrophysics Data System (ADS)

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-01

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min-1), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 105, a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm2 V-1 s-1. The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing.

PubMed

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-13

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min(-1)), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 10(5), a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm(2) V(-1) s(-1). The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

Organic-inorganic field effect transistor with SnI-based perovskite channel layer using vapor phase deposition technique

NASA Astrophysics Data System (ADS)

Matsushima, Toshinori; Yasuda, Takeshi; Fujita, Katsuhiko; Tsutsui, Tetsuo

2003-11-01

High field-effect hole mobility of (formula available in paper)and threshold voltage is -3.2 V) in organic-inorganic layered perovskite film (formula available in paper)prepared by a vapor phase deposition technique have been demonstrated through the octadecyltrichlorosilane treatment of substrate. Previously, the (formula available in paper)films prepared on the octadecyltrichlorosilane-covered substrates using a vapor evaporation showed not only intense exciton absorption and photoluminescence in the optical spectroscopy but also excellent crystallinity and large grain structure in X-ray and atomic force microscopic studies. Especially, the (formula available in paper)structure in the region below few nm closed to the surface of octadecyltrichlorosilane monolayer was drastically improved in comparison with that on the non-covered substrate. Though our initial (formula available in paper)films via a same sequence of preparation of (formula available in paper)and octadecyltrichlorosilane monolayer did not show the field-effect properties because of a lack of spectral, structural, and morphological features. The unformation of favorable (formula available in paper)structure in the very thin region, that is very important for the field-effect transistors to transport electrons or holes, closed to the surface of non-covered (formula available in paper)dielectric layer was also one of the problems for no observation of them. By adding further optimization and development, such as deposition rate of perovskite, substrate heating during deposition, and tuning device architecture, with hydrophobic treatment, the vacuum-deposited (formula available in paper)have achieved above-described high performance in organic-inorganic hybrid transistors.

On-Chip Chemical Self-Assembly of Semiconducting Single-Walled Carbon Nanotubes (SWNTs): Toward Robust and Scale Invariant SWNTs Transistors.

PubMed

Derenskyi, Vladimir; Gomulya, Widianta; Talsma, Wytse; Salazar-Rios, Jorge Mario; Fritsch, Martin; Nirmalraj, Peter; Riel, Heike; Allard, Sybille; Scherf, Ullrich; Loi, Maria A

2017-06-01

In this paper, the fabrication of carbon nanotubes field effect transistors by chemical self-assembly of semiconducting single walled carbon nanotubes (s-SWNTs) on prepatterned substrates is demonstrated. Polyfluorenes derivatives have been demonstrated to be effective in selecting s-SWNTs from raw mixtures. In this work the authors functionalized the polymer with side chains containing thiols, to obtain chemical self-assembly of the selected s-SWNTs on substrates with prepatterned gold electrodes. The authors show that the full side functionalization of the conjugated polymer with thiol groups partially disrupts the s-SWNTs selection, with the presence of metallic tubes in the dispersion. However, the authors determine that the selectivity can be recovered either by tuning the number of thiol groups in the polymer, or by modulating the polymer/SWNTs proportions. As demonstrated by optical and electrical measurements, the polymer containing 2.5% of thiol groups gives the best s-SWNT purity. Field-effect transistors with various channel lengths, using networks of SWNTs and individual tubes, are fabricated by direct chemical self-assembly of the SWNTs/thiolated-polyfluorenes on substrates with lithographically defined electrodes. The network devices show superior performance (mobility up to 24 cm 2 V -1 s -1 ), while SWNTs devices based on individual tubes show an unprecedented (100%) yield for working devices. Importantly, the SWNTs assembled by mean of the thiol groups are stably anchored to the substrate and are resistant to external perturbation as sonication in organic solvents. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Vertical organic transistors.

PubMed

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology

NASA Astrophysics Data System (ADS)

Ou-Peng, Li; Yong, Zhang; Rui-Min, Xu; Wei, Cheng; Yuan, Wang; Bing, Niu; Hai-Yan, Lu

2016-05-01

Design and characterization of a G-band (140-220 GHz) terahertz monolithic integrated circuit (TMIC) amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm InGaAs/InP double heterojunction bipolar transistor (DHBT). An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the InP substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140-190 GHz respectively. The saturation output powers are -2.688 dBm at 210 GHz and -2.88 dBm at 220 GHz, respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications. Project supported by the National Natural Science Foundation of China (Grant No. 61501091) and the Fundamental Research Funds for the Central Universities of Ministry of Education of China (Grant Nos. ZYGX2014J003 and ZYGX2013J020).

Substrate noise coupling: a pain for mixed-signal systems (Keynote Address)

NASA Astrophysics Data System (ADS)

Wambacq, Piet; Van der Plas, Geert; Donnay, Stephane; Badaroglu, Mustafa; Soens, Charlotte

2005-06-01

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. From the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

The interface between ferroelectric and 2D material for a Ferroelectric Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Park, Nahee; Kang, Haeyong; Lee, Sang-Goo; Lee, Young Hee; Suh, Dongseok

We have studied electrical property of ferroelectric field-effect transistor which consists of graphene on hexagonal Boron-Nitride (h-BN) gated by a ferroelectric, PMN-PT (i.e. (1-x)Pb(Mg1/3Nb2/3) O3-xPbTiO3) single-crystal substrate. The PMN-PT was expected to have an effect on polarization field into the graphene channel and to induce a giant amount of surface charge. The hexagonal Boron-Nitride (h-BN) flake was directly exfoliated on the PMN-PT substrate for preventing graphene from directly contacting on the PMN-PT substrate. It can make us to observe the effect of the interface between ferroelectric and 2D material on the device operation. Monolayer graphene as 2D channel material, which was confirmed by Raman spectroscopy, was transferred on top of the hexagonal Boron-Nitride (h-BN) by using the conventional dry-transfer method. Here, we can demonstrate that the structure of graphene/hexagonal-BN/ferroelectric field-effect transistor makes us to clearly understand the device operation as well as the interface between ferroelectric and 2D materials by inserting h-BN between them. The phenomena such as anti-hysteresis, current saturation behavior, and hump-like increase of channel current, will be discussed by in terms of ferroelectric switching, polarization-assisted charge trapping.

GaN-on-Silicon - Present capabilities and future directions

NASA Astrophysics Data System (ADS)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Monolithic 20W 2GHz Transistor and Monolithic 5W 4GHz Transistor.

DTIC Science & Technology

1979-02-01

epitaxial material of better quality than has been obtained from outside vendors . Ini tial tests indicate that the intrinsic material grown in our...system exceeds 800~ —cm , which is at least twice the value required . Also , the correct substrate material will be used and the N buried layer will...be the correct resistivity and thickness. The N layer will also be deposited somewhat thinner than the exist- ing material to reduce the collector

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Realizing Large-Scale, Electronic-Grade Two-Dimensional Semiconductors.

PubMed

Lin, Yu-Chuan; Jariwala, Bhakti; Bersch, Brian M; Xu, Ke; Nie, Yifan; Wang, Baoming; Eichfeld, Sarah M; Zhang, Xiaotian; Choudhury, Tanushree H; Pan, Yi; Addou, Rafik; Smyth, Christopher M; Li, Jun; Zhang, Kehao; Haque, M Aman; Fölsch, Stefan; Feenstra, Randall M; Wallace, Robert M; Cho, Kyeongjae; Fullerton-Shirey, Susan K; Redwing, Joan M; Robinson, Joshua A

2018-02-27

Atomically thin transition metal dichalcogenides (TMDs) are of interest for next-generation electronics and optoelectronics. Here, we demonstrate device-ready synthetic tungsten diselenide (WSe 2 ) via metal-organic chemical vapor deposition and provide key insights into the phenomena that control the properties of large-area, epitaxial TMDs. When epitaxy is achieved, the sapphire surface reconstructs, leading to strong 2D/3D (i.e., TMD/substrate) interactions that impact carrier transport. Furthermore, we demonstrate that substrate step edges are a major source of carrier doping and scattering. Even with 2D/3D coupling, transistors utilizing transfer-free epitaxial WSe 2 /sapphire exhibit ambipolar behavior with excellent on/off ratios (∼10 7 ), high current density (1-10 μA·μm -1 ), and good field-effect transistor mobility (∼30 cm 2 ·V -1 ·s -1 ) at room temperature. This work establishes that realization of electronic-grade epitaxial TMDs must consider the impact of the TMD precursors, substrate, and the 2D/3D interface as leading factors in electronic performance.

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

High Mobility SiGe/Si Transistor Structures on Sapphire Substrates Using Ion Implantation

NASA Technical Reports Server (NTRS)

Alterovitz, S. A.; Mueller, C. H.; Croke, E. T.

2003-01-01

High mobility n-type SiGe/Si transistor structures have been fabricated on sapphire substrates by ion implanting phosphorus ions into strained 100 Angstrom thick silicon channels for the first time. The strained Si channels were sandwiched between Si(sub 0.7)Ge(sub 0.3) layers, which, in turn, were deposited on Si(sub 0.7)Ge(sub 0.3) virtual substrates and graded SiGe buffer layers. After the molecular beam epitaxy (MBE) film growth process was completed, ion thick silicon channels implantation and post-annealing were used to introduce donors. The phosphorous ions were preferentially located in the Si channel at a peak concentration of approximately 1x10(exp 18)/cu cm. Room temperature electron mobilities exceeding 750 sq cm/V-sec at carrier densities of 1x10(exp 12)/sq cm were measured. Electron concentration appears to be the key factor that determines mobility, with the highest mobility observed for electron densities in the 1 - 2x10(exp 12)/sq cm range.

Synthesis of ZnO nanowires for thin film network transistors

NASA Astrophysics Data System (ADS)

Dalal, S. H.; Unalan, H. E.; Zhang, Y.; Hiralal, Pritesh; Gangloff, L.; Flewitt, Andrew J.; Amaratunga, Gehan A. J.; Milne, William I.

2008-08-01

Zinc oxide nanowire networks are attractive as alternatives to organic and amorphous semiconductors due to their wide bandgap, flexibility and transparency. We demonstrate the fabrication of thin film transistors (TFT)s which utilize ZnO nanowires as the semiconducting channel. These thin film transistors can be transparent and flexible and processed at low temperatures on to a variety of substrates. The nanowire networks are created using a simple contact transfer method that is easily scalable. Apparent nanowire network mobility values can be as high as 3.8 cm2/Vs (effective thin film mobility: 0.03 cm2/Vs) in devices with 20μm channel lengths and ON/OFF ratios of up to 104.

Catalytic activity of enzymes immobilized on AlGaN /GaN solution gate field-effect transistors

NASA Astrophysics Data System (ADS)

Baur, B.; Howgate, J.; von Ribbeck, H.-G.; Gawlina, Y.; Bandalo, V.; Steinhoff, G.; Stutzmann, M.; Eickhoff, M.

2006-10-01

Enzyme-modified field-effect transistors (EnFETs) were prepared by immobilization of penicillinase on AlGaN /GaN solution gate field-effect transistors. The influence of the immobilization process on enzyme functionality was analyzed by comparing covalent immobilization and physisorption. Covalent immobilization by Schiff base formation on GaN surfaces modified with an aminopropyltriethoxysilane monolayer exhibits high reproducibility with respect to the enzyme/substrate affinity. Reductive amination of the Schiff base bonds to secondary amines significantly increases the stability of the enzyme layer. Electronic characterization of the EnFET response to penicillin G indicates that covalent immobilization leads to the formation of an enzyme (sub)monolayer.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

PubMed

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Fully Printed Stretchable Thin-Film Transistors and Integrated Logic Circuits.

PubMed

Cai, Le; Zhang, Suoming; Miao, Jinshui; Yu, Zhibin; Wang, Chuan

2016-12-27

This paper reports intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits directly printed on elastomeric polydimethylsiloxane (PDMS) substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO 3 ) nanoparticles. The BaTiO 3 /PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. This work may offer an entry into more sophisticated stretchable electronic systems with monolithically integrated sensors, actuators, and displays, fabricated by scalable and low-cost methods for real life applications.

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Design-Oriented Introduction of Nanotechnology into the Electrical and Computer Engineering Curriculum

ERIC Educational Resources Information Center

Kim, Donghwi; Kamoua, Ridha; Pacelli, Andrea

2006-01-01

Nanoelectronics has the potential, and is indeed expected, to revolutionize information technology by the use of the impressive characteristics of nano-devices such as carbon nanotube transistors, molecular diodes and transistors, etc. A great effort is being put into creating an introductory course in nano-technology. However, practically all…

Tattoo-Paper Transfer as a Versatile Platform for All-Printed Organic Edible Electronics.

PubMed

Bonacchini, Giorgio E; Bossio, Caterina; Greco, Francesco; Mattoli, Virgilio; Kim, Yun-Hi; Lanzani, Guglielmo; Caironi, Mario

2018-04-01

The use of natural or bioinspired materials to develop edible electronic devices is a potentially disruptive technology that can boost point-of-care testing. The technology exploits devices that can be safely ingested, along with pills or even food, and operated from within the gastrointestinal tract. Ingestible electronics can potentially target a significant number of biomedical applications, both as therapeutic and diagnostic tool, and this technology may also impact the food industry, by providing ingestible or food-compatible electronic tags that can "smart" track goods and monitor their quality along the distribution chain. Temporary tattoo-paper is hereby proposed as a simple and versatile platform for the integration of electronics onto food and pharmaceutical capsules. In particular, the fabrication of all-printed organic field-effect transistors on untreated commercial tattoo-paper, and their subsequent transfer and operation on edible substrates with a complex nonplanar geometry is demonstrated. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fully Printed Flexible and Stretchable Electronics

NASA Astrophysics Data System (ADS)

Zhang, Suoming

Through this thesis proposal, the author has demonstrated series of flexible or stretchable sensors including strain gauge, pressure sensors, display arrays, thin film transistors and photodetectors fabricated by a direct printing process. By adopting the novel serpentine configuration with conventional non-stretchable materials silver nanoparticles, the fully printed stretchable devices are successfully fabricated on elastomeric substrate with the demonstration of stretchable conductors that can maintain the electrical properties under strain and the strain gauge, which could be used to measure the strain in desired locations and also to monitor individual person's finger motion. And by investigating the intrinsic stretchable materials silver nanowires (AgNWs) with the conventional configuration, the fully printed stretchable conductors are achieved on various substrates including Si, glass, Polyimide, Polydimethylsiloxane (PDMS) and Very High Bond (VHB) tape with the illustration of the capacitive pressure sensor and stretchable electroluminescent displays. In addition, intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits are directly printed on elastomeric PDMS substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO3) nanoparticles. The BaTiO3/PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. Finally, by applying the SWNTs as the channel layer of the thin film transistor, we successfully fabricate the fully printed flexible photodetector which exhibits good electrical characteristics and the transistors exhibit good reliability under bending conditions owing to the ultrathin polyimide substrate as well as the superior mechanical flexibility of the gate dielectric and carbon nanotube network. Furthermore, we have demonstrated that by using two types of SWCNT samples with different optical absorption characteristics, the photoresponse exhibits unique wavelength selectivity, as manifested by the good correlation between the responsive wavelengths of the devices with the absorption peaks of the corresponding carbon nanotubes. All the proposed materials above together with the unique direct printing process may offer an entry into more sophisticated flexible or stretchable electronic systems with monolithically integrated sensors, actuators, and displays for real life applications.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

PubMed

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, C.; Li, J.; Song, X. B.

2016-01-04

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density I{sub ds} of 4.2 A/mm, and a peak transconductance g{sub m} of 2880 mS/mm. Intrinsic current-gain cutoff frequency f{sub T} of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standingmore » bilayer epitaxial graphene transistor show the great application potential of this material system.« less

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

PubMed Central

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Technological Innovation of Thin-Film Transistors: Technology Development, History, and Future

NASA Astrophysics Data System (ADS)

Yamamoto, Yoshitaka

2012-06-01

The scale of the liquid crystal display industry has expanded rapidly, driven by technological innovations for thin-film transistors (TFTs). The TFT technology, which started from amorphous silicon (a-Si), has produced large TVs, and low-temperature polycrystalline silicon (poly-Si) has become a core technology for small displays, such as mobile phones. Recently, various TFT technological seeds have been realized, indicating that new information appliances that match new lifestyles and information infrastructures will be available in the near future. In this article, I review the history of TFT technology and discuss the future of TFT technological development from the technological innovation viewpoint.

Lithographically defined few-electron silicon quantum dots based on a silicon-on-insulator substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horibe, Kosuke; Oda, Shunri; Kodera, Tetsuo, E-mail: kodera.t.ac@m.titech.ac.jp

2015-02-23

Silicon quantum dot (QD) devices with a proximal single-electron transistor (SET) charge sensor have been fabricated in a metal-oxide-semiconductor structure based on a silicon-on-insulator substrate. The charge state of the QDs was clearly read out using the charge sensor via the SET current. The lithographically defined small QDs enabled clear observation of the few-electron regime of a single QD and a double QD by charge sensing. Tunnel coupling on tunnel barriers of the QDs can be controlled by tuning the top-gate voltages, which can be used for manipulation of the spin quantum bit via exchange interaction between tunnel-coupled QDs. Themore » lithographically defined silicon QD device reported here is technologically simple and does not require electrical gates to create QD confinement potentials, which is advantageous for the integration of complicated constructs such as multiple QD structures with SET charge sensors for the purpose of spin-based quantum computing.« less

Polymer substrate temperature sensor array for brain interfaces.

PubMed

Kim, Insoo; Fok, Ho Him R; Li, Yuanyuan; Jackson, Thomas N; Gluckman, Bruce J

2011-01-01

We developed an implantable thin film transistor temperature sensor (TFT-TS) to measure temperature changes in the brain. These changes are assumed to be associated with cerebral metabolism and neuronal activity. Two prototype TFT-TSs were designed and tested in-vitro: one with 8 diode-connected single-ended sensors, and the other with 4 pairs of differential-ended sensors in an array configuration. The sensor elements are 25 ~ 100 pm in width and 5 μm in length. The TFT-TSs were fabricated based on high-speed ZnO TFT process technology on flexible polyimide substrates (50 μm thick, 500 μm width, 20 mm length). In order to interface external signal electronics, they were directly bonded to a prototype printed circuit board using anisotropic conductive films The prototypes were characterized between 23 ~ 38 °C using a commercial temperature sensor and custom-designed temperature controlled oven. The maximum sensitivity of 40 mV/°C was obtained from the TFT-TS.

Zinc nitride thin films: basic properties and applications

NASA Astrophysics Data System (ADS)

Redondo-Cubero, A.; Gómez-Castaño, M.; García Núñez, C.; Domínguez, M.; Vázquez, L.; Pau, J. L.

2017-02-01

Zinc nitride films can be deposited by radio frequency magnetron sputtering using a Zn target at substrate temperatures lower than 250°C. This low deposition temperature makes the material compatible with flexible substrates. The asgrown layers present a black color, polycrystalline structures, large conductivities, and large visible light absorption. Different studies have reported about the severe oxidation of the layers in ambient conditions. Different compositional, structural and optical characterization techniques have shown that the films turn into ZnO polycrystalline layers, showing visible transparency and semi-insulating properties after total transformation. The oxidation rate is fairly constant as a function of time and depends on environmental parameters such as relative humidity or temperature. Taking advantage of those properties, potential applications of zinc nitride films in environmental sensing have been studied in the recent years. This work reviews the state-of-the-art of the zinc nitride technology and the development of several devices such as humidity indicators, thin film (photo)transistors and sweat monitoring sensors.

Polymer Substrate Temperature Sensor Array for Brain Interfaces

PubMed Central

Kim, Insoo; Fok, Ho Him R.; Li, Yuanyuan; Jackson, Thomas N.; Gluckman, Bruce J.

2012-01-01

We developed an implantable thin film transistor temperature sensor (TFT-TS) to measure temperature changes in the brain. These changes are assumed to be associated with cerebral metabolism and neuronal activity. Two prototype TFT-TSs were designed and tested in-vitro: one with 8 diode-connected single-ended sensors, and the other with 4 pairs of differential-ended sensors in an array configuration. The sensor elements are 25~100 μm in width and 5 μm in length. The TFT-TSs were fabricated based on high-speed ZnO TFT process technology on flexible polyimide substrates (50 μm thick, 500 μm width, 20 mm length). In order to interface external signal electronics, they were directly bonded to a prototype printed circuit board using anisotropic conductive films The prototypes were characterized between 20~40 °C using a surface mounted thermocouple and custom-designed temperature controlled oven. The maximum sensitivity of 40 mV/°C was obtained from the TFT-TS. PMID:22255041

Direct Growth of Graphene Film on Germanium Substrate

PubMed Central

Wang, Gang; Zhang, Miao; Zhu, Yun; Ding, Guqiao; Jiang, Da; Guo, Qinglei; Liu, Su; Xie, Xiaoming; Chu, Paul K.; Di, Zengfeng; Wang, Xi

2013-01-01

Graphene has been predicted to play a role in post-silicon electronics due to the extraordinary carrier mobility. Chemical vapor deposition of graphene on transition metals has been considered as a major step towards commercial realization of graphene. However, fabrication based on transition metals involves an inevitable transfer step which can be as complicated as the deposition of graphene itself. By ambient-pressure chemical vapor deposition, we demonstrate large-scale and uniform depositon of high-quality graphene directly on a Ge substrate which is wafer scale and has been considered to replace conventional Si for the next generation of high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The immiscible Ge-C system under equilibrium conditions dictates graphene depositon on Ge via a self-limiting and surface-mediated process rather than a precipitation process as observed from other metals with high carbon solubility. Our technique is compatible with modern microelectronics technology thus allowing integration with high-volume production of complementary metal-oxide-semiconductors (CMOS). PMID:23955352

Transistor-like behavior of single metalloprotein junctions.

PubMed

Artés, Juan M; Díez-Pérez, Ismael; Gorostiza, Pau

2012-06-13

Single protein junctions consisting of azurin bridged between a gold substrate and the probe of an electrochemical tunneling microscope (ECSTM) have been obtained by two independent methods that allowed statistical analysis over a large number of measured junctions. Conductance measurements yield (7.3 ± 1.5) × 10(-6)G(0) in agreement with reported estimates using other techniques. Redox gating of the protein with an on/off ratio of 20 was demonstrated and constitutes a proof-of-principle of a single redox protein field-effect transistor.

Fabrication and characterization of low temperature polycrystalline silicon thin film transistors

NASA Astrophysics Data System (ADS)

Krishnan, Anand Thiruvengadathan

2000-10-01

The proliferation of devices with built-in displays, such as personal digital assistants and cellular phones has created a demand for rugged light-weight displays. Polymeric substrates could be suited for these applications, and they offer the possibility of flexible displays also. However, driver circuitry needs to be integrated in the display if the cost is to be reduced. Low temperature (<350°C) polycrystalline silicon (poly-Si) thin film transistors, if developed, offer driver circuitry integration during pixel transistor fabrication on top of flexible substrates. This thesis addresses several issues related to the fabrication of thin film transistors at low temperatures on glass substrates. A high-density plasma (electron cyclotron resonance (ECR)) based approach was adopted for deposition of thin films. A process for deposition of n-type doped silicon (n-type doped Si) at T < 350°C and having resistivity <1 ohm/cm has been developed. Intrinsic poly-Si was deposited under different conditions of microwave power, RF bias and deposition times. The properties of n-type doped Si and intrinsic poly-Si were correlated with the structure and the deposition conditions. A novel TFT structure has been proposed and implemented in this work. This top gate TFT structure uses n-type doped Si and utilizes only two masks and one alignment step. There are no critical etch steps and good interface quality could be obtained even without post-processing hydrogenation as the poly-Si surface was not exposed to air before deposition of the gate dielectric. TFTs using this top gate structure were fabricated with no process step exceeding 340°C electrode temperature (surface temperature <300°C). These TFTs show ON/OFF ratios in excess of 105. Their sub-threshold swing is ˜0.5 V/decade and mobility is 1--10 cm2/V-s. Several TFTs were also fabricated using alternative dielectrics such as oxide deposited from tetramethyl silane in an RFPECVD chamber and silicon nitride deposited in the ECR and these TFTs also show reasonable device characteristics. TFTs processed using this high-density plasma based approach show great potential for use in applications such as driver circuitry integration on low temperature substrates.

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

High-mobility pyrene-based semiconductor for organic thin-film transistors.

PubMed

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

Bandgap-Engineered Zinc-Tin-Oxide Thin Films for Ultraviolet Sensors.

PubMed

Cheng, Tien-Hung; Chang, Sheng-Po; Chang, Shoou-Jinn

2018-07-01

Zinc-tin-oxide thin-film transistors were prepared by radio frequency magnetron co-sputtering, while an identical zinc-tin-oxide thin film was deposited simultaneously on a clear glass substrate to facilitate measurements of the optical properties. When we adjusted the deposition power of ZnO and SnO2, the bandgap of the amorphous thin film was dominated by the deposition power of SnO2. Since the thin-film transistor has obvious absorption in the ultraviolet region owing to the wide bandgap, the drain current increases with the generation of electron-hole pairs. As part of these investigations, a zinc-tin-oxide thin-film transistor has been fabricated that appears to be very promising for ultraviolet applications.

Integration of Indium Phosphide Based Devices with Flexible Substrates

NASA Astrophysics Data System (ADS)

Chen, Wayne Huai

2011-12-01

Flexible substrates have many advantages in applications where bendability, space, or weight play important roles or where rigid circuits are undesirable. However, conventional flexible thin film transistors are typically characterized as having low carrier mobility as compared to devices used in the electronics industry. This is in part due to the limited temperature tolerance of plastic flexible substrates, which commonly reduces the highest processing temperature to below 200°C. Common approaches of implementation include low temperature deposition of organic, amorphous, or polycrystalline semiconductors, all of which result in carrier mobility well below 100 cm2V -1s-1. High quality, single crystalline III-V semiconductors such as indium phosphide (InP), on the other hand, have carrier mobility well over 1000 cm 2V-1s-1 at room temperature, depending on carrier concentration. Recently, the ion-cut process has been used in conjunction with wafer bonding to integrate thin layers of III-V material onto silicon for optoelectronic applications. This approach has the advantage of high scalability, reusability of the initial III-V substrate, and the ability to tailor the location (depth) of the layer splitting. However, the transferred substrate usually suffers from hydrogen implantation damage. This dissertation demonstrates a new approach to enable integration of InP with various substrates, called the double-flip transfer process. The process combines ion-cutting with adhesive bonding. The problem of hydrogen implantation was overcome by patterned ion-cut transfer. In this type of transfer, areas of interest are shielded from implantation but still transferred by surrounding implanted regions. We found that patterned ion-cut transfer is strongly dependent upon crystal orientation and that using cleavage-plane oriented donors can be beneficial in transferring large areas of high quality semiconductor material. InP-based devices were fabricated to demonstrate the transfer process and test functionality following transfer. Passive devices (photodetectors) as well as active transistors were transferred and fabricated on various substrates. The transferred device layers were either implanted through with a blanket implant or protected with an ion-mask during implantation. Results demonstrate the viability of the double-flip ion-cut process in achieving very high electron mobility (˜2800 cm2V-1s-1) transistors on plastic flexible substrates.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Effect of substrate and temperature on the electronic properties of monolayer molybdenum disulfide field-effect transistors

NASA Astrophysics Data System (ADS)

Yang, Qizhi; Fang, Jiajia; Zhang, Guangru; Wang, Quan

2018-03-01

The use of two-dimensional nanostructured molybdenum disulfide (MoS2) films in field-effect transistors (FETs) in place of graphene was investigated. Monolayer MoS2 films were fabricated by chemical vapor deposition. The output and transfer curves of supported and suspended MoS2 FETs were measured. The mobility of the suspended device reached 364.2 cm2 V-1 s-1 at 150 °C. The hysteresis of the supported device in transfer curves was much larger than that of the suspended device, and it increased at higher temperatures. These results indicate that the device mobility was limited by Coulomb scattering at ambient temperature, and surface/interface phonon scattering at 150 °C, and the injection of electrons, via quantum tunneling through the Schottky barrier at the contact, was enhanced at higher temperatures and led to the increase of the hysteresis. The suspended MoS2 films show potential for application as a channel material in electronic devices, and further understanding the causes of hysteresis in a material is important for its use in technologies, such as memory devices and sensing cells.

Improved performance of inkjet-printed Ag source/drain electrodes for organic thin-film transistors by overcoming the coffee ring effects

NASA Astrophysics Data System (ADS)

Liu, Cheng-Fang; Lin, Yan; Lai, Wen-Yong; Huang, Wei

2017-11-01

Inkjet printing is a promising technology for the scalable fabrication of organic electronics because of the material conservation and facile patterning as compared with other solution processing techniques. In this study, we have systematically investigated the cross-sectional profile control of silver (Ag) electrode via inkjet printing. A facile methodology for achieving inkjet-printed Ag source/drain with improved profiles is developed. It is demonstrated that the printing conditions such as substrate temperature, drop spacing and printing layers affect the magnitude of the droplet deposition and the rate of evaporation, which can be optimized to greatly reduce the coffee ring effects for improving the inkjet-printed electrode profiles. Ag source/drain electrodes with uniform profiles were successfully inkjet-printed and incorporated into organic thin-film transistors (OTFTs). The resulting devices showed superior electrical performance than those without special treatments. It is noted to mention that the strategy for modulating the inkjet-printed Ag electrodes in this work does not demand the ink formulation or complicated steps, which is beneficial for scaling up the printing techniques for potential large-area/mass manufacturing.

All-Printed, Self-Aligned Carbon Nanotube Thin-Film Transistors on Imprinted Plastic Substrates.

PubMed

Song, Donghoon; Zare Bidoky, Fazel; Hyun, Woo Jin; Walker, S Brett; Lewis, Jennifer A; Frisbie, C Daniel

2018-05-09

We present a self-aligned process for printing thin-film transistors (TFTs) on plastic with single-walled carbon nanotube (SWCNT) networks as the channel material. The SCALE (self-aligned capillarity-assisted lithography for electronics) process combines imprint lithography with inkjet printing. Specifically, inks are jetted into imprinted reservoirs, where they then flow into narrow device cavities due to capillarity. Here, we incorporate a composite high- k gate dielectric and an aligned conducting polymer gate electrode in the SCALE process to enable a smaller areal footprint than prior designs that yields low-voltage SWCNT TFTs with average p-type carrier mobilities of 4 cm 2 /V·s and ON/OFF current ratios of 10 4 . Our work demonstrates the promising potential of the SCALE process to fabricate SWCNT-based TFTs with favorable I- V characteristics on plastic substrates.

Biosensors based on enzyme field-effect transistors for determination of some substrates and inhibitors.

PubMed

Dzyadevych, Sergei V; Soldatkin, Alexey P; Korpan, Yaroslav I; Arkhypova, Valentyna N; El'skaya, Anna V; Chovelon, Jean-Marc; Martelet, Claude; Jaffrezic-Renault, Nicole

2003-10-01

This paper is a review of the authors' publications concerning the development of biosensors based on enzyme field-effect transistors (ENFETs) for direct substrates or inhibitors analysis. Such biosensors were designed by using immobilised enzymes and ion-selective field-effect transistors (ISFETs). Highly specific, sensitive, simple, fast and cheap determination of different substances renders them as promising tools in medicine, biotechnology, environmental control, agriculture and the food industry. The biosensors based on ENFETs and direct enzyme analysis for determination of concentrations of different substrates (glucose, urea, penicillin, formaldehyde, creatinine, etc.) have been developed and their laboratory prototypes were fabricated. Improvement of the analytical characteristics of such biosensors may be achieved by using a differential mode of measurement, working solutions with different buffer concentrations and specific agents, negatively or positively charged additional membranes, or genetically modified enzymes. These approaches allow one to decrease the effect of the buffer capacity influence on the sensor response in an aim to increase the sensitivity of the biosensors and to extend their dynamic ranges. Biosensors for the determination of concentrations of different toxic substances (organophosphorous pesticides, heavy metal ions, hypochlorite, glycoalkaloids, etc.) were designed on the basis of reversible and/or irreversible enzyme inhibition effect(s). The conception of an enzymatic multibiosensor for the determination of different toxic substances based on the enzyme inhibition effect is also described. We will discuss the respective advantages and disadvantages of biosensors based on the ENFETs developed and also demonstrate their practical application.

Impact of humidity on functionality of on-paper printed electronics.

PubMed

Bollström, Roger; Pettersson, Fredrik; Dolietis, Peter; Preston, Janet; Osterbacka, Ronald; Toivakka, Martti

2014-03-07

A multilayer coated paper substrate, combining barrier and printability properties was manufactured utilizing a pilot-scale slide curtain coating technique. The coating structure consists of a thin mineral pigment layer coated on top of a barrier layer. The surface properties, i.e. smoothness and surface porosity, were adjusted by the choice of calendering parameters. The influence of surface properties on the fine line printability and conductivity of inkjet-printed silver lines was studied. Surface roughness played a significant role when printing narrow lines, increasing the risk of defects and discontinuities, whereas for wider lines the influence of surface roughness was less critical. A smooth, calendered surface resulted in finer line definition, i.e. less edge raggedness. Dimensional stability and its influence on substrate surface properties as well as on the functionality of conductive tracks and transistors were studied by exposure to high/low humidity cycles. The barrier layer of the multilayer coated paper reduced the dimensional changes and surface roughness increase caused by humidity and helped maintain the conductivity of the printed tracks. Functionality of a printed transistor during a short, one hour humidity cycle was maintained, but a longer exposure to humidity destroyed the non-encapsulated transistor.

Inkjet printed graphene-based field-effect transistors on flexible substrate

NASA Astrophysics Data System (ADS)

Monne, Mahmuda Akter; Enuka, Evarestus; Wang, Zhuo; Chen, Maggie Yihong

2017-08-01

This paper presents the design and fabrication of inkjet printed graphene field-effect transistors (GFETs). The inkjet printed GFET is fabricated on a DuPont Kapton FPC Polyimide film with a thickness of 5 mill and dielectric constant of 3.9 by using a Fujifilm Dimatix DMP-2831 materials deposition system. A layer by layer 3D printing technique is deployed with an initial printing of source and drain by silver nanoparticle ink. Then graphene active layer doped with molybdenum disulfide (MoS2) monolayer/multilayer dispersion, is printed onto the surface of substrate covering the source and drain electrodes. High capacitance ion gel is adopted as the dielectric material due to the high dielectric constant. Then the dielectric layer is then covered with silver nanoparticle gate electrode. Characterization of GFET has been done at room temperature (25°C) using HP-4145B semiconductor parameter analyzer (Hewlett-Packard). The characterization result shows for a voltage sweep from -2 volts to 2 volts, the drain current changes from 949 nA to 32.3 μA and the GFET achieved an on/off ratio of 38:1, which is a milestone for inkjet printed flexible graphene transistor.

High Electron Mobility SiGe/Si Transistor Structures on Sapphire Substrates

NASA Technical Reports Server (NTRS)

Alterovitz, Samuel A.; Mueller, Carl H.; Croke, Edward T.; Ponchak, George E.

2003-01-01

SiGe/Si n-type modulation doped field effect structures and transistors (n-MODFETs) have been fabricated on r-plane sapphire substrates. The structures were deposited using molecular beam epitaxy, and antimony dopants were incorporated via a delta doping process. Secondary ion mass spectroscopy (SIMS) indicates that the peak antimony, concentration was approximately 4 x 10(exp19) per cubic cm. The electron mobility was over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively. At these two temperatures, the electron carrier densities were 1.6 and 1.33 x 10(exp 12) per sq cm, thus demonstrating that carrier confinement was excellent. Shubnikov-de Haas oscillations were observed at 0.25 K, thus confirming the two-dimensional nature of the carriers. Transistors, with gate lengths varying from 1 micron to 5 microns, were fabricated using these structures and dc characterization was performed at room temperature. The saturated drain current region extended over a wide source-to-drain voltage (V(sub DS)) range, with (V(sub DS)) knee voltages of approximately 0.5 V and increased leakage starting at voltages slightly higher than 4 V.

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes.

PubMed

Cao, Xuan; Chen, Haitian; Gu, Xiaofei; Liu, Bilu; Wang, Wenli; Cao, Yu; Wu, Fanqi; Zhou, Chongwu

2014-12-23

Semiconducting single-wall carbon nanotubes are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible electronics. Nonetheless, developing scalable and low-cost approaches for manufacturing fully printed high-performance single-wall carbon nanotube thin-film transistors remains a major challenge. Here we report that screen printing, which is a simple, scalable, and cost-effective technique, can be used to produce both rigid and flexible thin-film transistors using separated single-wall carbon nanotubes. Our fully printed top-gated nanotube thin-film transistors on rigid and flexible substrates exhibit decent performance, with mobility up to 7.67 cm2 V(-1) s(-1), on/off ratio of 10(4)∼10(5), minimal hysteresis, and low operation voltage (<10 V). In addition, outstanding mechanical flexibility of printed nanotube thin-film transistors (bent with radius of curvature down to 3 mm) and driving capability for organic light-emitting diode have been demonstrated. Given the high performance of the fully screen-printed single-wall carbon nanotube thin-film transistors, we believe screen printing stands as a low-cost, scalable, and reliable approach to manufacture high-performance nanotube thin-film transistors for application in display electronics. Moreover, this technique may be used to fabricate thin-film transistors based on other materials for large-area flexible macroelectronics, and low-cost display electronics.

Black Phosphorus Flexible Thin Film Transistors at Gighertz Frequencies.

PubMed

Zhu, Weinan; Park, Saungeun; Yogeesh, Maruthi N; McNicholas, Kyle M; Bank, Seth R; Akinwande, Deji

2016-04-13

Black phosphorus (BP) has attracted rapidly growing attention for high speed and low power nanoelectronics owing to its compelling combination of tunable bandgap (0.3 to 2 eV) and high carrier mobility (up to ∼1000 cm(2)/V·s) at room temperature. In this work, we report the first radio frequency (RF) flexible top-gated (TG) BP thin-film transistors on highly bendable polyimide substrate for GHz nanoelectronic applications. Enhanced p-type charge transport with low-field mobility ∼233 cm(2)/V·s and current density of ∼100 μA/μm at VDS = -2 V were obtained from flexible BP transistor at a channel length L = 0.5 μm. Importantly, with optimized dielectric coating for air-stability during microfabrication, flexible BP RF transistors afforded intrinsic maximum oscillation frequency fMAX ∼ 14.5 GHz and unity current gain cutoff frequency fT ∼ 17.5 GHz at a channel length of 0.5 μm. Notably, the experimental fT achieved here is at least 45% higher than prior results on rigid substrate, which is attributed to the improved air-stability of fabricated BP devices. In addition, the high-frequency performance was investigated through mechanical bending test up to ∼1.5% tensile strain, which is ultimately limited by the inorganic dielectric film rather than the 2D material. Comparison of BP RF devices to other 2D semiconductors clearly indicates that BP offers the highest saturation velocity, an important metric for high-speed and RF flexible nanosystems.

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

PubMed

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Thin glass substrates for mobile applications

NASA Astrophysics Data System (ADS)

Mauch, Reiner H.; Wegener, Holger; Kruse, Anke; Hildebrand, Norbert

2000-10-01

Flat panel displays play an important role as the visual interface for today's electronic devices (Notebook computers, PDA's, pagers, mobile phones, etc.). Liquid Crystal Display's are dominating the market. While for higher resolution displays active matrix displays like Thin Film Transistor LCD's are used, portable devices are mainly using Super Twisted Nematic (STN) displays. Based on the application, STN displays for mobile applications require thinner glass substrates with improved surface quality at a lower cost. The requirements and trends for STN glass substrates are identified and discussed. Different glass manufacturing processes are used today for the manufacture of these substrates. Advantages and disadvantages of the different glass substrate types are presented and discussed.

In vitro cyto-biocompatibility study of thin-film transistors substrates using an organotypic culture method.

PubMed

Leclerc, Eric; Duval, Jean-Luc; Egles, Christophe; Ihida, Satoshi; Toshiyoshi, Hiroshi; Tixier-Mita, Agnès

2017-01-01

Thin-Film-Transistors Liquid-Crystal Display has become a standard in the field of displays. However, the structure of these devices presents interest not only in that field, but also for biomedical applications. One of the key components, called here TFT substrate, is a glass substrate with a dense and large array of thousands of transparent micro-electrodes that can be considered as a large scale multi-electrode array(s). Multi-electrode array(s) are widely used for in vitro electrical investigations on neurons and brain, allowing excitation, registration, and recording of their activity. However, the range of application of conventional multi-electrode array(s) is usually limited to some tens of cells in a homogeneous cell culture, because of a small area, small number and a low density of the micro-electrodes. TFT substrates do not have these limitations and the authors are currently studying the possibility to use TFT substrates as new tools for in vitro electrical investigation on tissues and organoids. In this respect, experiments to determine the cyto-biocompatibility of TFT substrates with tissues were conducted and are presented in this study. The investigation was performed using an organotypic culture method with explants of brain and liver tissues of chick embryos. The results in term of morphology, cell migration, cell density and adhesion were compared with the results from Thermanox ® , a conventional plastic for cell culture, and with polydimethylsiloxane, a hydrophobic silicone. The results with TFT substrates showed similar results as for the Thermanox ® , despite the TFT hydrophobicity. TFT substrates have a weak cell adhesion and promote cell migration similarly to Thermanox ® . It could be concluded that the TFT substrates are cyto-biocompatible with the two studied organs.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Low-Dimensional Nanomaterials and Molecular Dielectrics for Radiation-Hard Electronics

NASA Astrophysics Data System (ADS)

McMorrow, Julian

The electronic materials research driving Moore's law has provided several decades of increasingly powerful yet simultaneously miniaturized computer technologies. As we approach the physical and practical limits of what can be accomplished with silicon electronics, we look to new materials to drive innovation in future electronic applications. New materials paradigms require the development of understanding from first principles to the demonstration of applications that comes with mature technologies. Semiconducting single-walled carbon nanotubes (SWCNTs), single- and few-layer molybdenum disulfide (MoS2) and self-assembled nanodielectric (SAND) gate materials have all made significant impacts in the research field of unconventional electronic materials. The materials selection, interfaces between materials, processing steps to assemble them, and their interaction with their environment all have significant bearing on the operation of the overall device. Operating in harsh radiation environments, like those of satellites orbiting the Earth, present unique challenges to the functionality and reliability of electronic devices. Because the future of space-bound electronics is often informed by the technology of terrestrial devices, a proactive approach is adopted to identify and understand the radiation response of new materials systems as they emerge and develop. The work discussed here drives the innovation and development of multiple nanomaterial based electronic technologies while simultaneously exploring their relevant radiation response mechanisms. First, collaborative efforts result in the demonstration of a SWCNT-based circuit technology that is solution processed, large-area, and compatible with flexible substrates. The statistical characterization of SWCNT transistors enables the development of robust doping and encapsulation schemes, which make the SWCNT circuits stable, scalable, and low-power. These SWCNTs are then integrated into static random access memory (SRAM) cells, an accomplishment that illustrates the technological relevance of this work by implementing a highly utilized component of modern day computing. Next, these SRAM devices demonstrate functionality as true random number generators (TRNGs), which are critical components in cryptography and encryption. The randomness of these SWCNT TRNGs is verified by a suite of statistical tests. This achievement has implications for securing data and communication in future solution-processed, large-area, flexible electronics. The unprecedented integration achieved by the underlying SWCNT doping and encapsulation motivates the study of this technology in a radiation environment. Doing so results in an understanding of the fundamental charge trapping mechanisms responsible for the radiation response in this system. The integrated nature of these devices enables, for the first time, the observation of system-level effects in a SWCNT integrated circuit technology. This technology is found to be total ionizing dose-hard, a promising result for the adoption of SWCNTs in future space-bound applications. Compared to SWCNTs, the field of MoS2 electronics is relatively nascent. As a result, studies of radiation effects in MoS2 devices focus on the fundamental mechanisms at play in the materials system. Here, we reveal the critical role of atmospheric adsorbates in the radiation effects of MoS2 transistors by measuring their response to vacuum ultraviolet radiation. These results highlight the importance of controlling the atmosphere of MoS2 devices during irradiation. Furthermore, we make recommendations for radiation-hard MoS2-based devices in the future as the technology continues to mature. One such recommendation is the incorporation of specialized dielectrics with proven radiation hardness. To this end, we address the materials integration challenge of incorporating SAND gate dielectrics on arbitrary substrates. We explore a novel approach for preparing metal substrates for SAND deposition, supporting the SAND superlattice structure and its superlative electronic properties on a metal surface. This result is critical for conducting fundamental transport studies when integrating SAND with novel semiconductor materials, as well as enabling complex circuit integration and SAND on flexible substrates. Altogether, these works drive the integration of novel nanoelectronic materials for future electronics while providing an understanding of their varying radiation response mechanisms to enable their adoption in future space-bound applications.

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NASA Astrophysics Data System (ADS)

Houin, G.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-09-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance with hysteresis-free characteristics. A number of approaches were applied to simplify the process, improve device performance and decrease the operating voltage: they include an oxide interfacial layer to decrease contact resistance; a polymer passivation layer to optimize semiconductor/dielectric interface and an anodized high-k oxide as dielectric layer for low voltage operation. The devices fabricated on plastic substrate yielded excellent electrical characteristics, showing mobility of 1.6 cm2/Vs, lack of hysteresis, operation below 5 V and on/off current ratio above 105. An OFET model based on variable ranging hopping theory was used to extract the relevant parameters from the transfer and output characteristics, which enabled us to simulate our devices achieving reasonable agreement with the measurements

Improving performance of armchair graphene nanoribbon field effect transistors via boron nitride doping

NASA Astrophysics Data System (ADS)

Goharrizi, A. Yazdanpanah; Sanaeepur, M.; Sharifi, M. J.

2015-09-01

Device performance of 10 nm length armchair graphene nanoribbon field effect transistors with 1.5 nm and 4 nm width (13 and 33 atoms in width respectively) are compared in terms of Ion /Ioff , trans-conductance, and sub-threshold swing. While narrow devices suffer from edge roughness wider devices are subject to more substrate surface roughness and reduced bandgap. Boron Nitride doping is employed to compensate reduced bandgap in wider devices. Simultaneous effects of edge and substrate surface roughness are considered. Results show that in the presence of both the edge and substrate surface roughness the 4 nm wide device with boron nitride doping shows improved performance with respect to the 1.5 nm one (both of which incorporate the same bandgap AGNR as channel material). Electronic simulations are performed via NEGF method along with tight-binding Hamiltonian. Edge and surface roughness are created by means of one and two dimensional auto correlation functions respectively. Electronic characteristics are averaged over a large number of devices due to statistic nature of both the edge and surface roughness.

AlGaAs/InGaAs/AlGaAs double pulse doped pseudomorphic high electron mobility transistor structures on InGaAs substrates

NASA Astrophysics Data System (ADS)

Hoke, W. E.; Lyman, P. S.; Mosca, J. J.; McTaggart, R. A.; Lemonias, P. J.; Beaudoin, R. M.; Torabi, A.; Bonner, W. A.; Lent, B.; Chou, L.-J.; Hsieh, K. C.

1997-10-01

Double pulse doped AlGaAs/InGaAs/AlGaAs pseudomorphic high electron mobility transistor (PHEMT) structures have been grown on InxGa1-xAs (x=0.025-0.07) substrates using molecular beam epitaxy. A strain compensated, AlGaInAs/GaAs superlattice was used for improved resistivity and breakdown. Excellent electrical and optical properties were obtained for 110-Å-thick InGaAs channel layers with indium concentrations up to 31%. A room temperature mobility of 6860 cm2/V s with 77 K sheet density of 4.0×1012cm-2 was achieved. The InGaAs channel photoluminescence intensity was equivalent to an analogous structure on a GaAs substrate. To reduce strain PHEMT structures with a composite InGaP/AlGaAs Schottky layer were also grown. The structures also exhibited excellent electrical and optical properties. Transmission electron micrographs showed planar channel interfaces for highly strained In0.30Ga0.70As channel layers.

Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

NASA Astrophysics Data System (ADS)

Marrs, Michael

A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs between low temperature and low stress (less than -70 MPa compressive) and device performance. Devices with a dark current of less than 1.0 pA/mm2 and a quantum efficiency of 68% have been demonstrated. Alternative processing techniques, such as pixelating the PIN diode and using organic photodiodes have also been explored for applications where extreme flexibility is desired.

A comparative study of graphene and graphite-based field effect transistor on flexible substrate

NASA Astrophysics Data System (ADS)

Bhatt, Kapil; Rani, Cheenu; Vaid, Monika; Kapoor, Ankit; Kumar, Pramod; Kumar, Sandeep; Shriwastawa, Shilpi; Sharma, Sandeep; Singh, Randhir; Tripathi, C. C.

2018-06-01

In the present era, there has been a great demand of cost-effective, biodegradable, flexible and wearable electronics which may open the gate to many applications like flexible displays, RFID tags, health monitoring devices, etc. Due to the versatile nature of plastic substrates, they have been extensively used in packaging, printing, etc. However, the fabrication of electronic devices requires specially prepared substrates with high quality surfaces, chemical compositions and solutions to the related fabrication issues along with its non-biodegradable nature. Therefore, in this report, a cost-effective, biodegradable cellulose paper as an alternative dielectric substrate material for the fabrication of flexible field effect transistor (FET) is presented. The graphite and liquid phase exfoliated graphene have been used as the material for the realisation of source, drain and channel on cellulose paper substrate for its comparative analysis. The mobility of fabricated FETs was calculated to be 83 cm2/V s (holes) and 33 cm2/V s (electrons) for graphite FET and 100 cm2/V s (holes) and 52 cm2/V s (electrons) for graphene FET, respectively. The output characteristic of the device demonstrates the linear behaviour and a comprehensive increase in conductance as a function of gate voltages. The fabricated FETs may be used for strain sensing, health care monitoring devices, human motion detection, etc.

Thermal Gradient During Vacuum-Deposition Dramatically Enhances Charge Transport in Organic Semiconductors: Toward High-Performance N-Type Organic Field-Effect Transistors.

PubMed

Kim, Joo-Hyun; Han, Singu; Jeong, Heejeong; Jang, Hayeong; Baek, Seolhee; Hu, Junbeom; Lee, Myungkyun; Choi, Byungwoo; Lee, Hwa Sung

2017-03-22

A thermal gradient distribution was applied to a substrate during the growth of a vacuum-deposited n-type organic semiconductor (OSC) film prepared from N,N'-bis(2-ethylhexyl)-1,7-dicyanoperylene-3,4:9,10-bis(dicarboxyimide) (PDI-CN2), and the electrical performances of the films deployed in organic field-effect transistors (OFETs) were characterized. The temperature gradient at the surface was controlled by tilting the substrate, which varied the temperature one-dimensionally between the heated bottom substrate and the cooled upper substrate. The vacuum-deposited OSC molecules diffused and rearranged on the surface according to the substrate temperature gradient, producing directional crystalline and grain structures in the PDI-CN2 film. The morphological and crystalline structures of the PDI-CN2 thin films grown under a vertical temperature gradient were dramatically enhanced, comparing with the structures obtained from either uniformly heated films or films prepared under a horizontally applied temperature gradient. The field effect mobilities of the PDI-CN2-FETs prepared using the vertically applied temperature gradient were as high as 0.59 cm 2 V -1 s -1 , more than a factor of 2 higher than the mobility of 0.25 cm 2 V -1 s -1 submitted to conventional thermal annealing and the mobility of 0.29 cm 2 V -1 s -1 from the horizontally applied temperature gradient.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Polycrystalline silicon thin-film transistors on quartz fiber

NASA Astrophysics Data System (ADS)

Sugawara, Yuta; Uraoka, Yukiharu; Yano, Hiroshi; Hatayama, Tomoaki; Fuyuki, Takashi; Nakamura, Toshihiro; Toda, Sadayuki; Koaizawa, Hisashi; Mimura, Akio; Suzuki, Kenkichi

2007-11-01

We demonstrate the fabrication of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) on a thin quartz fiber for the first time. The poly-Si used in the active layer of the TFTs was prepared by excimer laser annealing of an amorphous Si thin film deposited on the fiber. Top-gated TFTs were fabricated on the fiber, and a field effect mobility of 10cm2/Vs was obtained. The proposed TFTs on a thin quartz fiber, named fiber TFTs, have potential application in microelectronic devices using TFTs fabricated on one-dimensional substrates.

Morphology and electronic transport of polycrystalline pentacene thin-film transistors

NASA Astrophysics Data System (ADS)

Knipp, D.; Street, R. A.; Völkel, A. R.

2003-06-01

Temperature-dependent measurements of thin-film transistors were performed to gain insight in the electronic transport of polycrystalline pentacene. Devices were fabricated with plasma-enhanced chemical vapor deposited silicon nitride gate dielectrics. The influence of the dielectric roughness and the deposition temperature of the thermally evaporated pentacene films were studied. Although films on rougher gate dielectrics and films prepared at low deposition temperatures exhibit similar grain size, the electronic properties are different. Increasing the dielectric roughness reduces the free carrier mobility, while low substrate temperature leads to more and deeper hole traps.

A crystalline germanium flexible thin-film transistor

NASA Astrophysics Data System (ADS)

Higashi, H.; Nakano, M.; Kudo, K.; Fujita, Y.; Yamada, S.; Kanashima, T.; Tsunoda, I.; Nakashima, H.; Hamaya, K.

2017-11-01

We experimentally demonstrate a flexible thin-film transistor (TFT) with (111)-oriented crystalline germanium (Ge) layers grown by a gold-induced crystallization method. Accumulation-mode metal source/drain p-channel Ge TFTs are fabricated on a polyimide film at ≤ 400 ° C . A field-effect mobility (μFE) of 10.7 cm2/Vs is obtained, meaning the highest μFE in the p-TFTs fabricated at ≤ 400 ° C on flexible plastic substrates. This study will lead to high-performance flexible electronics based on an inorganic-semiconductor channel.

Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques

NASA Technical Reports Server (NTRS)

Policastro, Steven G. (Inventor); Woo, Dae-Shik (Inventor)

1983-01-01

A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

Flexible diodes for radio frequency (RF) electronics: a materials perspective

NASA Astrophysics Data System (ADS)

Semple, James; Georgiadou, Dimitra G.; Wyatt-Moon, Gwenhivir; Gelinck, Gerwin; Anthopoulos, Thomas D.

2017-12-01

Over the last decade, there has been increasing interest in transferring the research advances in radiofrequency (RF) rectifiers, the quintessential element of the chip in the RF identification (RFID) tags, obtained on rigid substrates onto plastic (flexible) substrates. The growing demand for flexible RFID tags, wireless communications applications and wireless energy harvesting systems that can be produced at a low-cost is a key driver for this technology push. In this topical review, we summarise recent progress and status of flexible RF diodes and rectifying circuits, with specific focus on materials and device processing aspects. To this end, different families of materials (e.g. flexible silicon, metal oxides, organic and carbon nanomaterials), manufacturing processes (e.g. vacuum and solution processing) and device architectures (diodes and transistors) are compared. Although emphasis is placed on performance, functionality, mechanical flexibility and operating stability, the various bottlenecks associated with each technology are also addressed. Finally, we present our outlook on the commercialisation potential and on the positioning of each material class in the RF electronics landscape based on the findings summarised herein. It is beyond doubt that the field of flexible high and ultra-high frequency rectifiers and electronics as a whole will continue to be an active area of research over the coming years.

Diffused Silicon Transistors and Switches (1954-55): The Beginning of Integrated Circuit Technology

NASA Astrophysics Data System (ADS)

Holonyak, N.

2003-09-01

Silicon (Si) transistor and integrated circuit (IC) technology has grown so big, and become so important, that it is now hard to recognize where, apart from the invention of the transistor itself (Bardeen and Brattain, Dec 16, 1947), it had its origin. In spite of obvious differences in Ge and Si, in 1950-55 it was not evident in many laboratories, concentrating only on Ge, what form of Ge transistor (grown, alloyed, jet-etched, etc.) might be expected to prevail, with Si not even being considered (or being dismissed outright). What was the need for Si and, at the time, such a seemingly intractable peculiar new technology? The requirement on switching devices of low leakage, and thus the need to leave Ge in favor of Si, led directly in 1954-55 (Bell Telephone Laboratories, BTL) to the exploration of impurity-diffusion and metallization technology to realize Si transistors and p-n-p-n switches. This technology, a more or less ideal thin-layer technology that can be referenced from a single surface (and which indeed has proven to be basically invariant and constantly growing), led further to the discovery (1955) of the protective Si oxide, oxide masking and patterning, and the fundamental basis of the integrated circuit (i.e., device-to-device interconnection by patterned metallization across the oxide). We recount some of the exploratory diffused-impurity Si device development of 1954-55 at BTL, particularly the work in and near Moll's group, that helped to establish the basis for today's electronics. The Si diffused-impurity devices of 1954-55 are described, including work and data not previously reported or broadly known—in fact, much work and data (a new technology) that was carried across the Country to a place that became known as Silicon Valley. For further perspective, an appendix is included of independent early suggestions of Bardeen (Urbana notebook, Feb 1952) to leave Ge in favor of diffused Si devices.

AlN/GaN heterostructures for normally-off transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Highly stable amorphous silicon thin film transistors and integration approaches for reliable organic light emitting diode displays on clear plastic

NASA Astrophysics Data System (ADS)

Hekmatshoar, Bahman

Hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are currently in widespread production for integration with liquid crystals as driver devices. Liquid crystal displays are driven in AC with very low duty cycles and therefore fairly insensitive to the TFT threshold voltage rise which is well-known in a-Si:H devices. Organic light-emitting diodes (OLEDs) are a future technology choice for flexible displays with several advantages over liquid crystals. In contrast to liquid crystal displays, however, OLEDs are driven in DC and thus far more demanding in terms of the TFT stability requirements. Therefore the conventional thinking has been that a-Si:H TFTs are too unstable for driving OLEDs and the more expensive poly-Si or alternative TFT technologies are required. This thesis defies the conventional thinking by demonstrating that the knowledge of the degradation mechanisms in a-Si:H TFTs may be used to enhance the drive current half-life of a-Si:H TFTs from lower than a month to over 1000 years by modifying the growth conditions of the channel and the gate dielectric. Such high lifetimes suggest that the improved a-Si:H TFTs may qualify for driving OLEDs in commercial products. Taking advantage of industry-standard growth techniques, the improved a-Si:H TFTs offer a low barrier for industry insertion, in stark contrast with alternative technologies which require new infrastructure development. Further support for the practical advantages of a-Si:H TFTs for driving OLEDs is provided by a universal lifetime comparison framework proposed in this work, showing that the lifetime of the improved a-Si:H TFTs is well above those of other TFT technologies reported in the literature. Manufacturing of electronic devices on flexible plastic substrates is highly desirable for reducing the weight of the finished products as well as increasing their ruggedness. In addition, the flexibility of the substrate allows manufacturing bendable, foldable or rollable electronic systems which is not possible with conventional rigid substrates. The most reliable TFTs require a temperature higher than that possible with existing clear flexible plastic substrates. Successful integration of a-Si:H TFTs with OLEDs on new high temperature flexible clear plastic substrates, capable of being processed at 300°C, is presented in this thesis. Controlling the mechanical stress and adhesion of the layers is found to be critical at high process temperatures to avoid cracking and delamination on clear plastic, and TFTs with a lifetime of 100 years on clear plastic have been achieved. In addition, a new "inverted" integration technique is demonstrated both on glass and clear plastic to allow the programming of standard bottom-emission OLEDs with a-Si:H TFTs independent of the OLED characteristics which may change over time and vary from device to device in manufacturing. This technique also enhances the pixel drive current by nearly an order of magnitude for the same programming voltage. Finally, an approach for the design of reliable pixels is presented. Based on the individual TFT and OLED device stability, a guideline to the overall circuit configuration that will provide the most stable light emission is provided.

Highly Sensitive Flexible Pressure Sensors Based on Printed Organic Transistors with Centro-Apically Self-Organized Organic Semiconductor Microstructures.

PubMed

Yeo, So Young; Park, Sangsik; Yi, Yeon Jin; Kim, Do Hwan; Lim, Jung Ah

2017-12-13

A highly sensitive pressure sensor based on printed organic transistors with three-dimensionally self-organized organic semiconductor microstructures (3D OSCs) was demonstrated. A unique organic transistor with semiconductor channels positioned at the highest summit of printed cylindrical microstructures was achieved simply by printing an organic semiconductor and polymer blend on the plastic substrate without the use of additional etching or replication processes. A combination of the printed organic semiconductor microstructure and an elastomeric top-gate dielectric resulted in a highly sensitive organic field-effect transistor (FET) pressure sensor with a high pressure sensitivity of 1.07 kPa -1 and a rapid response time of <20 ms with a high reliability over 1000 cycles. The flexibility and high performance of the 3D OSC FET pressure sensor were exploited in the successful application of our sensors to real-time monitoring of the radial artery pulse, which is useful for healthcare monitoring, and to touch sensing in the e-skin of a realistic prosthetic hand.

Organic Field Effect Transistor Using Amorphous Fluoropolymer as Gate Insulating Film

NASA Astrophysics Data System (ADS)

Kitajima, Yosuke; Kojima, Kenzo; Mizutani, Teruyoshi; Ochiai, Shizuyasu

Organic field effect transistors are fabricated by the active layer of Regioregular poly (3-hexylthiophene-2,5-diy)(P3HT) thin film. CYTOP thin film made from Amorphous Fluoropolymer and fabricated by spin-coating is adopted to a gate dielectric layer on Polyethylenenaphthalate (PEN) thin film that is the substrate of an organic field effect transistor. The surface morphology and molecular orientation of P3HT thin films is observed by atomic force microscope (AFM) and X-Ray diffractometer (XRD). Grains are observed on the CYTOP thin film via an AFM image and the P3HT molecule is oriented perpendicularly on the CYTOP thin film. Based on the performance of the organic field effect transistor, the carrier mobility is 0.092 cm2/Vs, the ON/OFF ratio is 7, and the threshold voltage is -12 V. The ON/OFF ratio is relatively low and to improve On/Off ratio, the CYTOP/Polyimide double gate insulating layer is adopted to OFET.

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

NASA Astrophysics Data System (ADS)

Gutiérrez-Heredia, G.; González, L. A.; Alshareef, H. N.; Gnade, B. E.; Quevedo-López, M.

2010-11-01

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 µA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 µA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented.

Improving yield and performance in ZnO thin-film transistors made using selective area deposition.

PubMed

Nelson, Shelby F; Ellinger, Carolyn R; Levy, David H

2015-02-04

We describe improvements in both yield and performance for thin-film transistors (TFTs) fabricated by spatial atomic layer deposition (SALD). These improvements are shown to be critical in forming high-quality devices using selective area deposition (SAD) as the patterning method. Selective area deposition occurs when the precursors for the deposition are prevented from reacting with some areas of the substrate surface. Controlling individual layer quality and the interfaces between layers is essential for obtaining good-quality thin-film transistors and capacitors. The integrity of the gate insulator layer is particularly critical, and we describe a method for forming a multilayer dielectric using an oxygen plasma treatment between layers that improves crossover yield. We also describe a method to achieve improved mobility at the important interface between the semiconductor and the gate insulator by, conversely, avoiding oxygen plasma treatment. Integration of the best designs results in wide design flexibility, transistors with mobility above 15 cm(2)/(V s), and good yield of circuits.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-12-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Characterization and Modeling of Nano-organic Thin Film Phototransistors Based on 6,13(Triisopropylsilylethynyl)-Pentacene: Photovoltaic Effect

NASA Astrophysics Data System (ADS)

Jouili, A.; Mansouri, S.; Al-Ghamdi, Ahmed A.; El Mir, L.; Farooq, W. A.; Yakuphanoglu, F.

2017-04-01

Organic thin film transistors based on 6,13(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) with various channel widths and thicknesses of the active layer (300 nm and 135 nm) were photo-characterized. The photoresponse behavior and the gate field dependence of the charge transport were analyzed in detail. The surface properties of TIPS-pentacene deposited on silicon dioxide substrate were investigated using an atomic force microscope. We confirm that the threshold voltage values of the TIPS-pentacene transistor depend on the intensity of white light illumination. With the multiple trapping and release model, we have developed an analytical model that was applied to reproduce the experimental output characteristics of organic thin film transistors based on TIPS-pentacene under dark and under light illumination.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

PubMed Central

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-01-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption. PMID:26656113

Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

2016-09-01

In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

Fabrication of Stretchable Organic-Inorganic Hybrid Thin-Film Transistors on Polyimide Stiff-Island Structures.

PubMed

Jung, Soon-Won; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lee, Sang Seok

2015-10-01

In this study, stretchable organic-inorganic hybrid thin-film transistors (TFTs) are fabricated on a polyimide (PI) stiff-island/elastomer substrate using blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) and oxide semiconductor In-Ga-Zn-O as the gate dielectric and semiconducting layer, respectively. Carrier mobility, Ion/Ioff ratio, and subthreshold swing (SS) values of 6.1 cm2 V(-1) s(-1), 10(7), and 0.2 V/decade, respectively, were achieved. For the hybrid TFTs, the endurable maximum strain without degradation of electrical properties was approximately 49%. These results correspond to those obtained in the first study on fabrication of stretchable hybrid-type TFTs on elastomer substrate using an organic gate insulator and oxide semiconducting active channel structure, thus indicating the feasibility of a promising device for stretchable electronic systems.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

A new detector concept for silicon photomultipliers

NASA Astrophysics Data System (ADS)

Sadigov, A.; Ahmadov, F.; Ahmadov, G.; Ariffin, A.; Khorev, S.; Sadygov, Z.; Suleymanov, S.; Zerrouk, F.; Madatov, R.

2016-07-01

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

Fluorine and oxygen plasma influence on nanoparticle formation and aggregation in metal oxide thin film transistors

NASA Astrophysics Data System (ADS)

MÄ dzik, Mateusz; Elamurugu, Elangovan; Viegas, Jaime

2017-03-01

Despite recent advances in metal oxide thin-film transistor technology, there are no foundry processes available yet for large-scale deployment of metal oxide electronics and photonics, in a similar way as found for silicon based electronics and photonics. One of the biggest challenges of the metal oxide platform is the stability of the fabricated devices. Also, there is wide dispersion on the measured specifications of fabricated TFT, from lot-to-lot and from different research groups. This can be partially explained by the importance of the deposition method and its parameters, which determine thin film microstructure and thus its electrical properties. Furthermore, substrate pretreatment is an important factor, as it may act as a template for material growth. Not so often mentioned, plasma processes can also affect the morphology of deposited films on further deposition steps, such as inducing nanoparticle formation, which strongly impact the conduction mechanism in the channel layer of the TFT. In this study, molybdenum doped indium oxide is sputtered onto ALD deposited HfO2 with or without pattering, and etched by RIE chlorine based processing. Nanoparticle formation is observed when photoresist is removed by oxygen plasma ashing. HfO2 etching in CF4/Ar plasma prior to resist stripping in oxygen plasma promotes the aggregation of nanoparticles into nanosized branched structures. Such nanostructuring is absent when oxygen plasma steps are replaced by chemical wet processing with acetone. Finally, in order to understand the electronic transport effect of the nanoparticles on metal oxide thin film transistors, TFT have been fabricated and electrically characterized.

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

Direct Fabrication of a-Si:H Thin Film Transistor Arrays on Plastic and Metal Foils for Flexible Displays

DTIC Science & Technology

2008-12-01

TFTs ) arrays for high information content active matrix flexible displays for Army applications. For all flexible substrates a manufacturable...impermeable flexible substrate systems “display-ready” materials and handling protocols, (ii) high performance TFT devices and circuits fabricated...processes for integration with the flexible TFT arrays. Approaches and solution to address each of these major challenges are described in the

Investigations on Substrate Temperature-Induced Growth Modes of Organic Semiconductors at Dielectric/semiconductor Interface and Their Correlation with Threshold Voltage Stability in Organic Field-Effect Transistors.

PubMed

Padma, Narayanan; Maheshwari, Priya; Bhattacharya, Debarati; Tokas, Raj B; Sen, Shashwati; Honda, Yoshihide; Basu, Saibal; Pujari, Pradeep Kumar; Rao, T V Chandrasekhar

2016-02-10

Influence of substrate temperature on growth modes of copper phthalocyanine (CuPc) thin films at the dielectric/semiconductor interface in organic field effect transistors (OFETs) is investigated. Atomic force microscopy (AFM) imaging at the interface reveals a change from 'layer+island' to "island" growth mode with increasing substrate temperatures, further confirmed by probing the buried interfaces using X-ray reflectivity (XRR) and positron annihilation spectroscopic (PAS) techniques. PAS depth profiling provides insight into the details of molecular ordering while positron lifetime measurements reveal the difference in packing modes of CuPc molecules at the interface. XRR measurements show systematic increase in interface width and electron density correlating well with the change from layer + island to coalesced huge 3D islands at higher substrate temperatures. Study demonstrates the usefulness of XRR and PAS techniques to study growth modes at buried interfaces and reveals the influence of growth modes of semiconductor at the interface on hole and electron trap concentrations individually, thereby affecting hysteresis and threshold voltage stability. Minimum hole trapping is correlated to near layer by layer formation close to the interface at 100 °C and maximum to the island formation with large voids between the grains at 225 °C.

Nanoribbon field-effect transistors as direct and label-free sensors of enzyme-substrate interactions

NASA Astrophysics Data System (ADS)

Mu, Luye; Droujinine, Ilia; Rajan, Nitin; Sawtelle, Sonya; Reed, Mark

2015-03-01

The ability to measure enzyme-substrate interactions is essential in areas such as diagnostics, treatment, and biochemical screens. Many enzymatic reactions alter the pH of its environment, suggesting of a simple and direct method for detection. We show the ability of Al2O3-coated Si nanoribbon field-effect transistor biosensors to sensitively measure various aspects of enzyme-substrate interactions through measuring the pH. Urea in phosphate buffered saline (PBS) and penicillinase in PBS and urine were measured to limits of <200 μM and 0.02 units/mL, respectively. We also show the ability to extract accurate kinetics from the interaction of acetylcholine and its esterase. Prior work on FET sensors has been limited by the use of surface functionalization, which not only alters enzyme-substrate affinity, but also makes enzyme activity quantification difficult. Our method involves direct detection of reactions in solution without requiring alteration to the reactants, allowing us to obtain repeatable results and sensitive limits of detection. This method is a simple, inexpensive, and effective platform for detection of enzymatic reactions, and can be readily generalized to many unrelated classes of reactants. This work was supported in part by U.S. Army Research Office and Air Force Research Laboratory.

Indium antimonide quantum well structures for electronic device applications

NASA Astrophysics Data System (ADS)

Edirisooriya, Madhavie

The electron effective mass is smaller in InSb than in any other III-V semiconductor. Since the electron mobility depends inversely on the effective mass, InSb-based devices are attractive for field effect transistors, magnetic field sensors, ballistic transport devices, and other applications where the performance depends on a high mobility or a long mean free path. In addition, electrons in InSb have a large g-factor and strong spin orbit coupling, which makes them well suited for certain spin transport devices. The first n-channel InSb high electron mobility transistor (HEMT) was produced in 2005 with a power-delay product superior to HEMTs with a channel made from any other III-V semiconductor. The high electron mobility in the InSb quantum-well channel increases the switching speed and lowers the required supply voltage. This dissertation focuses on several materials challenges that can further increase the appeal of InSb quantum wells for transistors and other electronic device applications. First, the electron mobility in InSb quantum wells, which is the highest for any semiconductor quantum well, can be further increased by reducing scattering by crystal defects. InSb-based heteroepitaxy is usually performed on semi-insulating GaAs (001) substrates due to the lack of a lattice matched semi-insulating substrate. The 14.6% mismatch between the lattice parameters of GaAs and InSb results in the formation of structural defects such as threading dislocations and microtwins which degrade the electrical and optical properties of InSb-based devices. Chapter 1 reviews the methods and procedures for growing InSb-based heterostructures by molecular beam epitaxy. Chapters 2 and 3 introduce techniques for minimizing the crystalline defects in InSb-based structures grown on GaAs substrates. Chapter 2 discusses a method of reducing threading dislocations by incorporating AlyIn1-ySb interlayers in an AlxIn1-xSb buffer layer and the reduction of microtwin defects by growth on GaAs substrates that are oriented 2° away from the [011] direction. Chapter 3 discusses designing InSb QW layer structures that are strain balanced. By applying these defect-reducing techniques, the electron mobility in InSb quantum wells at room temperature was significantly increased. For complementary logic technology, p-channel transistors with high mobility are equally as important as n-channel transistors. However, achieving a high hole mobility in III-V semiconductors is challenging. A controlled introduction of strain in the quantum-well material is an effective technique for enhancing the hole mobility beyond its value in bulk material. The strain reduces the hole effective mass by splitting the heavy hole and light hole valence bands. Chapter 4 discusses a successful attempt to realize p-type InSb quantum well structures. The biaxial strain applied via a relaxed metamorphic buffer resulted in a significantly higher room-temperature hole mobility and a record high low-temperature hole mobility. To demonstrate the usefulness of high mobility in a device structure, magnetoresistive devices were fabricated from remotely doped InSb QWs. Such devices have numerous practical applications such as position and speed sensors and as read heads in magnetic storage systems. In a magnetoresistive device composed of a series of shorted Hall bars, the magnetoresistance is proportional to the electron mobility squared for small magnetic fields. Hence, the high electron mobility in InSb QWs makes them highly preferable for geometrical magnetoresistors. Chapter 5 reports the fabrication and characterization of InSb quantum-well magnetoresistors. The excellent transport properties of the InSb QWs resulted in high room-temperature sensitivity to applied magnetic fields. Finally, Chapter 6 provides the conclusions obtained during this research effort, and makes suggestions for future work.

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

PubMed Central

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

NASA Astrophysics Data System (ADS)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

2015-10-01

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

Real-time photoelectron spectroscopy study of the oxidation reaction kinetics on p-type and n-type Si (001) surfaces

NASA Astrophysics Data System (ADS)

Yu, Zhou

Silicon oxides thermally grown on Si surface are the core gate materials of metal-oxide-semiconductor field effect transistor (MOSFET). This thin oxide layer insulates the gate terminals and the transistors substrate which make MOSFET has certain advantages over those conventional junctions, such as field-effect transistor (FET) and junction field effect transistor (JFET). With an oxide insulating layer, MOSFET is able to sustain higher input impedance and the corresponding gate leakage current can be minimized. Today, though the oxidation process on Si substrate is popular in industry, there are still some uncertainties about its oxidation kinetics. On a path to clarify and modeling the oxidation kinetics, a study of initial oxidation kinetics on Si (001) surface has attracted attentions due to having a relatively low surface electron density and few adsorption channels compared with other Si surface direction. Based on previous studies, there are two oxidation models of Si (001) that extensively accepted, which are dual oxide species mode and autocatalytic reaction model. These models suggest the oxidation kinetics on Si (001) mainly relies on the metastable oxygen atom on the surface and the kinetic is temperature dependent. Professor Yuji Takakuwa's group, Surface Physics laboratory, Institute of Multidisciplinary Research for Advanced Materials, Tohoku University, observed surface strain existed during the oxidation kinetics on Si (001) and this is the first time that strain was discovered during Si oxidation. Therefore, it is necessary to explain where the strain comes from since none of previous model research included the surface strain (defects generation) into considerations. Moreover, recent developing of complementary metal-oxide-semiconductor (CMOS) requires a simultaneous oxidation process on p- and n-type Si substrate. However, none of those previous models included the dopant factor into the oxidation kinetic modeling. All of these points that further work is necessary to update and modify the traditional Si (001) oxidation models that had been accepted for several decades. To update and complement the Si (001) oxidation kinetics, an understanding of the temperature and dopant factor during initial oxidation kinetics on Si (001) is our first step. In this study, real-time photoelectron spectroscopy is applied to characterize the oxidized (001) surface and surface information was collected by ultraviolet photoelectron spectroscopy technique. By analyzing parameters such as O 2p spectra uptake, change of work function and the surface state in respect of p- and n- type Si (001) substrate under different temperature, the oxygen adsorption structure and the dopant factor can be determined. In this study, experiments with temperature gradients on p-type Si (001) were conducted and this aims to clarify the temperature dependent characteristic of Si (001) surface oxidation. A comparison of the O 2p uptake, change of work function and surface state between p-and n-type Si (001) is made under a normal temperature and these provides with the data to explain how the dopant factor impacts the oxygen adsorption structure on the surface. In the future, the study of the oxygen adsorption structure will lead to an explanation of the surface strain that discovered; therefore, fundamental of the initial oxidation on Si (001) would be updated and complemented, which would contribute to the future gate technology in MOSFET and CMOS.

From Bell Labs to Silicon Valley: A Saga of Technology Transfer, 1954-1961

NASA Astrophysics Data System (ADS)

Riordan, Michael

2009-03-01

Although Bell Telephone Laboratories invented the transistor and developed most of the associated semiconductor technology, the integrated circuit or microchip emerged elsewhere--at Texas Instruments and Fairchild Semiconductor Company. I recount how the silicon technology required to make microchips possible was first developed at Bell Labs in the mid-1950s. Much of it reached the San Francisco Bay Area when transistor pioneer William Shockley left Bell Labs in 1955 to establish the Shockley Semiconductor Laboratory in Mountain View, hiring a team of engineers and scientists to develop and manufacture transistors and related semiconductor devices. But eight of them--including Gordon Moore and Robert Noyce, eventually the co-founders of Intel--resigned en masse in September 1957 to start Fairchild, bringing with them the scientific and technological expertise they had acquired and further developed at Shockley's firm. This event marked the birth of Silicon Valley, both technologically and culturally. By March 1961 the company was marketing its Micrologic integrated circuits, the first commercial silicon microchips, based on the planar processing technique developed at Fairchild by Jean Hoerni.

Graphene-Nanodiamond Heterostructures and their application to High Current Devices

PubMed Central

Zhao, Fang; Vrajitoarea, Andrei; Jiang, Qi; Han, Xiaoyu; Chaudhary, Aysha; Welch, Joseph O.; Jackman, Richard B.

2015-01-01

Graphene on hydrogen terminated monolayer nanodiamond heterostructures provides a new way to improve carrier transport characteristics of the graphene, offering up to 60% improvement when compared with similar graphene on SiO2/Si substrates. These heterostructures offers excellent current-carrying abilities whilst offering the prospect of a fast, low cost and easy methodology for device applications. The use of ND monolayers is also a compatible technology for the support of large area graphene films. The nature of the C-H bonds between graphene and H-terminated NDs strongly influences the electronic character of the heterostructure, creating effective charge redistribution within the system. Field effect transistors (FETs) have been fabricated based on this novel herterostructure to demonstrate device characteristics and the potential of this approach. PMID:26350107

Ultrahigh-mobility graphene devices from chemical vapor deposition on reusable copper

PubMed Central

Banszerus, Luca; Schmitz, Michael; Engels, Stephan; Dauber, Jan; Oellers, Martin; Haupt, Federica; Watanabe, Kenji; Taniguchi, Takashi; Beschoten, Bernd; Stampfer, Christoph

2015-01-01

Graphene research has prospered impressively in the past few years, and promising applications such as high-frequency transistors, magnetic field sensors, and flexible optoelectronics are just waiting for a scalable and cost-efficient fabrication technology to produce high-mobility graphene. Although significant progress has been made in chemical vapor deposition (CVD) and epitaxial growth of graphene, the carrier mobility obtained with these techniques is still significantly lower than what is achieved using exfoliated graphene. We show that the quality of CVD-grown graphene depends critically on the used transfer process, and we report on an advanced transfer technique that allows both reusing the copper substrate of the CVD growth and making devices with mobilities as high as 350,000 cm2 V–1 s–1, thus rivaling exfoliated graphene. PMID:26601221

Away from silicon era: the paper electronics

NASA Astrophysics Data System (ADS)

Martins, R.; Brás, B.; Ferreira, I.; Pereira, L.; Barquinha, P.; Correia, N.; Costa, R.; Busani, T.; Gonçalves, A.; Pimentel, A.; Fortunato, E.

2011-02-01

Today there is a strong interest in the scientific and industrial community concerning the use of biopolymers for electronic applications, mainly driven by low-cost and disposable applications. Adding to this interest, we must recognize the importance of the wireless auto sustained and low energy consumption electronics dream. This dream can be fulfilled by cellulose paper, the lightest and the cheapest known substrate material, as well as the Earth's major biopolymer and of tremendous global economic importance. The recent developments of oxide thin film transistors and in particular the production of paper transistors at room temperature had contributed, as a first step, for the development of disposable, low cost and flexible electronic devices. To fulfil the wireless demand, it is necessary to prove the concept of self powered devices. In the case of paper electronics, this implies demonstrating the idea of self regenerated thin film paper batteries and its integration with other electronic components. Here we demonstrate this possibility by actuating the gate of paper transistors by paper batteries. We found that when a sheet of cellulose paper is covered in both faces with thin layers of opposite electrochemical potential materials, a voltage appears between both electrodes -paper battery, which is also self-regenerated. The value of the potential depends upon the materials used for anode and cathode. An open circuit voltage of 0.5V and a short-circuit current density of 1μA/cm2 were obtained in the simplest structure produced (Cu/paper/Al). For actuating the gate of the paper transistor, seven paper batteries were integrated in the same substrate in series, supplying a voltage of 3.4V. This allows proper ON/OFF control of the paper transistor. Apart from that transparent conductive oxides can be also used as cathode/anode materials allowing so the production of thin film batteries with transparent electrodes compatible with flexible, invisible, self powered and wireless electronics.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

NASA Technical Reports Server (NTRS)

Choi, Sang; King, Glen; Park, Yeonjoon

2009-01-01

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Solid-state X-band Combiner Study

NASA Technical Reports Server (NTRS)

Pitzalis, O., Jr.; Russell, K. J.

1979-01-01

The feasibility of developing solid-state amplifiers at 4 and 10 GHz for application in spacecraft altimeters was studied. Bipolar-transistor, field-effect-transistor, and Impatt-diode amplifier designs based on 1980 solid-state technology are investigated. Several output power levels of the pulsed, low-duty-factor amplifiers are considered at each frequency. Proposed transistor and diode amplifier designs are illustrated in block diagrams. Projections of size, weight, and primary power requirements are given for each design.

InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

NASA Technical Reports Server (NTRS)

Radisic, Vesna; Sawdai, Donald; Scott, Dennis; Deal, William; Dang, Linh; Li, Danny; Cavus, Abdullah; To, Richard; Lai, Richard

2009-01-01

Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

2016-11-01

Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Modelling and analysis of the wetting characteristics of ink for display applications with the surface evolution technique

NASA Astrophysics Data System (ADS)

Shin, Dong-Youn; Brakke, Kenneth A.

2009-06-01

Piezo drop-on-demand inkjet printing technology has attracted the attention of display industries for the production of colour filters for thin film transistor liquid crystal displays (TFT LCD) because of the opportunity of reducing manufacturing cost. Colourant ink droplets ejected from inkjet nozzles selectively fill subpixels surrounded with black matrix (BM). Surface energy differences between the glass substrate and the BM generally guide this ink filling process. This colourant ink filling process, however, results from the complex hydrodynamic interaction of ink with the substrate and the BM. Neither computationally expensive numerical methods nor time and cost expensive experiments are suitable for the derivation of optimum surface conditions at the early development stage. In this study, a more concise surface evolution technique is proposed and ways to find the optimum surface conditions for the fabrication of TFT LCD colour filters and polymer light emitting devices are discussed, which might be useful for chemists and developers of ink and BM material, as well as for process engineers in display industries.

Comparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS2 flake based field effect transistors on SiO2 and hBN substrates.

PubMed

Lee, Changhee; Rathi, Servin; Khan, Muhammad Atif; Lim, Dongsuk; Kim, Yunseob; Yun, Sun Jin; Youn, Doo-Hyeb; Watanabe, Kenji; Taniguchi, Takashi; Kim, Gil-Ho

2018-08-17

Molybdenum disulfide (MoS 2 ) based field effect transistors (FETs) are of considerable interest in electronic and opto-electronic applications but often have large hysteresis and threshold voltage instabilities. In this study, by using advanced transfer techniques, hexagonal boron nitride (hBN) encapsulated FETs based on a single, homogeneous and atomic-thin MoS 2 flake are fabricated on hBN and SiO 2 substrates. This allows for a better and a precise comparison between the charge traps at the semiconductor-dielectric interfaces at MoS 2 -SiO 2 and hBN interfaces. The impact of ambient environment and entities on hysteresis is minimized by encapsulating the active MoS 2 layer with a single hBN on both the devices. The device to device variations induced by different MoS 2 layer is also eliminated by employing a single MoS 2 layer for fabricating both devices. After eliminating these additional factors which induce variation in the device characteristics, it is found from the measurements that the trapped charge density is reduced to 1.9 × 10 11 cm -2 on hBN substrate as compared to 1.1 × 10 12 cm -2 on SiO 2 substrate. Further, reduced hysteresis and stable threshold voltage are observed on hBN substrate and their dependence on gate sweep rate, sweep range, and gate stress is also studied. This precise comparison between encapsulated devices on SiO 2 and hBN substrates further demonstrate the requirement of hBN substrate and encapsulation for improved and stable performance of MoS 2 FETs.

Printed organo-functionalized graphene for biosensing applications.

PubMed

Wisitsoraat, A; Mensing, J Ph; Karuwan, C; Sriprachuabwong, C; Jaruwongrungsee, K; Phokharatkul, D; Daniels, T M; Liewhiran, C; Tuantranont, A

2017-01-15

Graphene is a highly promising material for biosensors due to its excellent physical and chemical properties which facilitate electron transfer between the active locales of enzymes or other biomaterials and a transducer surface. Printing technology has recently emerged as a low-cost and practical method for fabrication of flexible and disposable electronics devices. The combination of these technologies is promising for the production and commercialization of low cost sensors. In this review, recent developments in organo-functionalized graphene and printed biosensor technologies are comprehensively covered. Firstly, various methods for printing graphene-based fluids on different substrates are discussed. Secondly, different graphene-based ink materials and preparation methods are described. Lastly, biosensing performances of printed or printable graphene-based electrochemical and field effect transistor sensors for some important analytes are elaborated. The reported printed graphene based sensors exhibit promising properties with good reliability suitable for commercial applications. Among most reports, only a few printed graphene-based biosensors including screen-printed oxidase-functionalized graphene biosensor have been demonstrated. The technology is still at early stage but rapidly growing and will earn great attention in the near future due to increasing demand of low-cost and disposable biosensors. Copyright © 2016 Elsevier B.V. All rights reserved.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

NASA Astrophysics Data System (ADS)

Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

2016-02-01

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

NASA Astrophysics Data System (ADS)

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

High-mobility low-temperature ZnO transistors with low-voltage operation

NASA Astrophysics Data System (ADS)

Bong, Hyojin; Lee, Wi Hyoung; Lee, Dong Yun; Kim, Beom Joon; Cho, Jeong Ho; Cho, Kilwon

2010-05-01

Low voltage high mobility n-type thin film transistors (TFTs) based on sol-gel processed zinc oxide (ZnO) were fabricated using a high capacitance ion gel gate dielectric. The ion gel gated solution-processed ZnO TFTs were found to exhibit excellent electrical properties. TFT carrier mobilities were 13 cm2/V s, ON/OFF current ratios were 105, regardless of the sintering temperature used for the preparation of the ZnO thin films. Ion gel gated ZnO TFTs are successfully demonstrated on plastic substrates for the large area flexible electronics.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

InN thin-film transistors fabricated on polymer sheets using pulsed sputtering deposition at room temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lye, Khe Shin; Kobayashi, Atsushi; Ueno, Kohei

Indium nitride (InN) is potentially suitable for the fabrication of high performance thin-film transistors (TFTs) because of its high electron mobility and peak electron velocity. However, InN is usually grown using a high temperature growth process, which is incompatible with large-area and lightweight TFT substrates. In this study, we report on the room temperature growth of InN films on flexible polyimide sheets using pulsed sputtering deposition. In addition, we report on the fabrication of InN-based TFTs on flexible polyimide sheets and the operation of these devices.

Technology Directions for the 21st Century, volume 1

NASA Technical Reports Server (NTRS)

Crimi, Giles F.; Verheggen, Henry; McIntosh, William; Botta, Robert

1996-01-01

For several decades, semiconductor device density and performance have been doubling about every 18 months (Moore's Law). With present photolithography techniques, this rate can continue for only about another 10 years. Continued improvement will need to rely on newer technologies. Transition from the current micron range for transistor size to the nanometer range will permit Moore's Law to operate well beyond 10 years. The technologies that will enable this extension include: single-electron transistors; quantum well devices; spin transistors; and nanotechnology and molecular engineering. Continuation of Moore's Law will rely on huge capital investments for manufacture as well as on new technologies. Much will depend on the fortunes of Intel, the premier chip manufacturer, which, in turn, depend on the development of mass-market applications and volume sales for chips of higher and higher density. The technology drivers are seen by different forecasters to include video/multimedia applications, digital signal processing, and business automation. Moore's Law will affect NASA in the areas of communications and space technology by reducing size and power requirements for data processing and data fusion functions to be performed onboard spacecraft. In addition, NASA will have the opportunity to be a pioneering contributor to nanotechnology research without incurring huge expenses.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Variability-aware compact modeling and statistical circuit validation on SRAM test array

NASA Astrophysics Data System (ADS)

Qiao, Ying; Spanos, Costas J.

2016-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose a variability-aware compact model characterization methodology based on stepwise parameter selection. Transistor I-V measurements are obtained from bit transistor accessible SRAM test array fabricated using a collaborating foundry's 28nm FDSOI technology. Our in-house customized Monte Carlo simulation bench can incorporate these statistical compact models; and simulation results on SRAM writability performance are very close to measurements in distribution estimation. Our proposed statistical compact model parameter extraction methodology also has the potential of predicting non-Gaussian behavior in statistical circuit performances through mixtures of Gaussian distributions.

Growth-substrate induced performance degradation in chemically synthesized monolayer MoS{sub 2} field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Amani, Matin; Chin, Matthew L.; Mazzoni, Alexander L.

2014-05-19

We report on the electronic transport properties of single-layer thick chemical vapor deposition (CVD) grown molybdenum disulfide (MoS{sub 2}) field-effect transistors (FETs) on Si/SiO{sub 2} substrates. MoS{sub 2} has been extensively investigated for the past two years as a potential semiconductor analogue to graphene. To date, MoS{sub 2} samples prepared via mechanical exfoliation have demonstrated field-effect mobility values which are significantly higher than that of CVD-grown MoS{sub 2}. In this study, we will show that the intrinsic electronic performance of CVD-grown MoS{sub 2} is equal or superior to that of exfoliated material and has been possibly masked by a combinationmore » of interfacial contamination on the growth substrate and residual tensile strain resulting from the high-temperature growth process. We are able to quantify this strain in the as-grown material using pre- and post-transfer metrology and microscopy of the same crystals. Moreover, temperature-dependent electrical measurements made on as-grown and transferred MoS{sub 2} devices following an identical fabrication process demonstrate the improvement in field-effect mobility.« less

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate.

PubMed

Han, Dedong; Zhang, Yi; Cong, Yingying; Yu, Wen; Zhang, Xing; Wang, Yi

2016-12-12

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O 2 /Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O 2 /Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (I off ) of 3 pA, a high on/off current ratio of 2 × 10 7 , a high saturation mobility (μ sat ) of 66.7 cm 2 /V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (V th ) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate

NASA Astrophysics Data System (ADS)

Han, Dedong; Zhang, Yi; Cong, Yingying; Yu, Wen; Zhang, Xing; Wang, Yi

2016-12-01

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O2/Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O2/Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (Ioff) of 3 pA, a high on/off current ratio of 2 × 107, a high saturation mobility (μsat) of 66.7 cm2/V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (Vth) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Transfer printing of thermoreversible ion gels for flexible electronics.

PubMed

Lee, Keun Hyung; Zhang, Sipei; Gu, Yuanyan; Lodge, Timothy P; Frisbie, C Daniel

2013-10-09

Thermally assisted transfer printing was employed to pattern thin films of high capacitance ion gels on polyimide, poly(ethylene terephthalate), and SiO2 substrates. The ion gels consisted of 20 wt % block copolymer poly(styrene-b-ethylene oxide-b-styrene and 80 wt % ionic liquid 1-ethyl-3-methylimidazolium bis(trifluoromethyl sulfonyl)amide. Patterning resolution was on the order of 10 μm. Importantly, ion gels containing the block polymer with short PS end blocks (3.4 kg/mol) could be transfer-printed because of thermoreversible gelation that enabled intimate gel-substrate contact at 100 °C, while gels with long PS blocks (11 kg/mol) were not printable at the same temperature due to poor wetting contact between the gel and substrates. By using printed ion gels as high-capacitance gate insulators, electrolyte-gated thin-film transistors were fabricated that operated at low voltages (<1 V) with high on/off current ratios (∼10(5)). Statistical analysis of carrier mobility, turn-on voltage, and on/off ratio for an array of printed transistors demonstrated the excellent reproducibility of the printing technique. The results show that transfer printing is an attractive route to pattern high-capacitance ion gels for flexible thin-film devices.

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

Low Voltage, Low Power Organic Light Emitting Transistors for AMOLED Displays

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCarthy, M. A.; Liu, B.; Donoghue, E. P.

2011-01-01

Low voltage, low power dissipation, high aperture ratio organic light emitting transistors are demonstrated. The high level of performance is enabled by a carbon nanotube source electrode that permits integration of the drive transistor and the organic light emitting diode into an efficient single stacked device. Given the demonstrated performance, this technology could break the technical logjam holding back widespread deployment of active matrix organic light emitting displays at flat panel screen sizes.

Radiation evaluation study of LSI RAM technologies

NASA Astrophysics Data System (ADS)

Dinger, G. L.; Knoll, M. G.

1980-01-01

Five commercial LSI static random access memory technologies having a 1 kilobit capacity were radiation characterized. Arrays from the transistor-transistor-logic (TTL), Schottky TTL, n-channel metal oxide semiconductor, complementary metal oxide semiconductor (CMOS), and CMOS/silicon on sapphire families were evaluated. Radiation failure thresholds for gamma doserate logic upset, total gamma dose survivability, and neutron fluence survivability were determined. A brief analysis of the radiation failure mechanism for each of the logic families tested is included.

Hybrid thin-film amplifier

NASA Technical Reports Server (NTRS)

Cleveland, G.

1977-01-01

Miniature amplifier for bioelectronic instrumentation consumes only about 100 mW and has frequency response flat to within 0.5 dB from 0.14 to 450 Hz. Device consists of five thin film substrates, which contain eight operational amplifiers and seven field-effect transistor dice.

Fabrication of nanowire electronics on nonconventional substrates by water-assisted transfer printing method

NASA Astrophysics Data System (ADS)

Lee, Chi Hwan; Kim, Dong Rip; Zheng, Xiaolin

2015-06-01

We report a simple, versatile, and wafer-scale water-assisted transfer printing method (WTP) that enables the transfer of nanowire devices onto diverse nonconventional substrates that were not easily accessible before, such as paper, plastics, tapes, glass, polydimethylsiloxane (PDMS), aluminum foil, and ultrathin polymer substrates. The WTP method relies on the phenomenon of water penetrating into the interface between Ni and SiO2. The transfer yield is nearly 100%, and the transferred devices, including NW resistors, diodes, and field effect transistors, maintain their original geometries and electronic properties with high fidelity.

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

NASA Astrophysics Data System (ADS)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

GaN transistors on Si for switching and high-frequency applications

NASA Astrophysics Data System (ADS)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Graphene and carbon nanotubes: synthesis, characterization and applications for beyond silicon electronics

NASA Astrophysics Data System (ADS)

Gomez de Arco, Lewis Mortimer

Graphene and carbon nanotubes have outstanding electrical and thermal conductivity. These characteristics make them exciting materials with high potential to replace silicon and surpass its performance in the next generation of semiconductors devices, such devices ought to be considerably smaller and faster than the ones used in present technology. Despite of the excellent electrical and thermal conduction properties of graphene and carbon nanotubes, the advance of nanoelectronics based on them has been hampered due to fundamental limitations of the current synthesis and integration technologies of these carbon nanomaterials. Therefore, there is a strong need to do research at fundamental and applicative levels to help find the roadmap that these materials need to follow, in order to become a real alternative for silicon in future technologies. This dissertation present our approach to overcome some of the most critical problems that hinder the implementation of graphene and carbon nanotubes as important components in real-life macro and nanoelectronic devices. Towards this end, we systematically studied synthesis methods for scalable, high quality graphene and evaluated our large-scale synthesized graphene as transparent electrodes in functional energy conversion devices. In addition, we explored scalable methods to obtain carbon nanotube field-effect transistors with only semiconductor nanotube channels and studied the substrate influence on the structure and metal to semiconductor ratio of aligned nanotubes. Although we have successfully tackled some of the most important challenges of the above-mentioned one- and two-dimensional carbon nanostructures, more remains to be done to integrate them as functional components in electronic devices to reach the goal of transferring them from the laboratory to the manufacturing industry, and ultimately to the society. In chapter 1, a general introduction to carbon nanomaterials is presented, followed by a more focused discussion on the structure and properties of graphene and carbon nanotubes. Chapter 2, presents the development of a chemical vapor deposition method for scalable graphene synthesis and the evaluation of its electrical properties as the active channel in field effect transistor and as a transparent conductor. Chapter 3 presents further work on graphene synthesis on single crystal nickel and the influence of the substrate atomic arrangement on the synthesized graphene. Chapter 4 presents the implementation of the highly scalable graphene synthesized by CVD as the transparent electrode in flexible organic photovoltaic cells. Chapter 5 evaluates the influence of substrate/nanotube interactions during align nanotube growth on the Raman signature of the resulting aligned nanotubes, nanotube structure and metal to semiconductor ratio. Chapter 6 presents our findings on a scalable method that can be used at wafer scale to achieve metal to semiconductor conversion of carbon nanotubes by light irradiation and its application to achieve semiconducting CNTFETs. Finally, in chapter 7, future research directions in related areas of science and technology are proposed.

Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer

NASA Astrophysics Data System (ADS)

Jiménez Tejada, Juan A.; Lopez-Varo, Pilar; Chaure, Nandu B.; Chambrier, Isabelle; Cammidge, Andrew N.; Cook, Michael J.; Jafari-Fini, Ali; Ray, Asim K.

2018-03-01

70 nm thick solution-processed films of a palladium phthalocyanine (PdPc6) derivative bearing eight hexyl (-C6H13) chains at non-peripheral positions have been employed as active layers in the fabrication of bottom-gate bottom-contact organic thin film transistors (OTFTs) deposited on highly doped p-type Si (110) substrates with SiO2 gate dielectric. The dependence of the transistor electrical performance upon the mesophase behavior of the PdPc6 films has been investigated by measuring the output and transfer characteristics of the OTFT having its active layer ex situ vacuum annealed at temperatures between 500 °C and 200 °C. A clear correlation between the annealing temperature and the threshold voltage and carrier mobility of the transistors, and the transition temperatures extracted from the differential scanning calorimetric curves for bulk materials has been established. This direct relation has been obtained by means of a compact electrical model in which the contact effects are taken into account. The precise determination of the contact-voltage drain-current curves allows for obtaining such a relation.

Oxide-based thin film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

He, Yongli; Wang, Xiangyu; Gao, Ya; Hou, Yahui; Wan, Qing

2018-01-01

The continuous progress in thin film materials and devices has greatly promoted the development in the field of flexible electronics. As one of the most common thin film devices, thin film transistors (TFTs) are significant building blocks for flexible platforms. Flexible oxide-based TFTs are well compatible with flexible electronic systems due to low process temperature, high carrier mobility, and good uniformity. The present article is a review of the recent progress and major trends in the field of flexible oxide-based thin film transistors. First, an introduction of flexible electronics and flexible oxide-based thin film transistors is given. Next, we introduce oxide semiconductor materials and various flexible oxide-based TFTs classified by substrate materials including polymer plastics, paper sheets, metal foils, and flexible thin glass. Afterwards, applications of flexible oxide-based TFTs including bendable sensors, memories, circuits, and displays are presented. Finally, we give conclusions and a prospect for possible development trends. Project supported in part by the National Science Foundation for Distinguished Young Scholars of China (No. 61425020), in part by the National Natural Science Foundation of China (No. 11674162).

High-power flexible AlGaN/GaN heterostructure field-effect transistors with suppression of negative differential conductance

NASA Astrophysics Data System (ADS)

Oh, Seung Kyu; Cho, Moon Uk; Dallas, James; Jang, Taehoon; Lee, Dong Gyu; Pouladi, Sara; Chen, Jie; Wang, Weijie; Shervin, Shahab; Kim, Hyunsoo; Shin, Seungha; Choi, Sukwon; Kwak, Joon Seop; Ryou, Jae-Hyun

2017-09-01

We investigate thermo-electronic behaviors of flexible AlGaN/GaN heterostructure field-effect transistors (HFETs) for high-power operation of the devices using Raman thermometry, infrared imaging, and current-voltage characteristics. A large negative differential conductance observed in HFETs on polymeric flexible substrates is confirmed to originate from the decreasing mobility of the two-dimensional electron gas channel caused by the self-heating effect. We develop high-power transistors by suppressing the negative differential conductance in the flexible HFETs using chemical lift-off and modified Ti/Au/In metal bonding processes with copper (Cu) tapes for high thermal conductivity and low thermal interfacial resistance in the flexible hybrid structures. Among different flexible HFETs, the ID of the HFETs on Cu with Ni/Au/In structures decreases only by 11.3% with increasing drain bias from the peak current to the current at VDS = 20 V, which is close to that of the HFETs on Si (9.6%), solving the problem of previous flexible AlGaN/GaN transistors.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays.

PubMed

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon; Hussain, Muhammad Mustafa

2018-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Parallel Nanoshaping of Brittle Semiconductor Nanowires for Strained Electronics.

PubMed

Hu, Yaowu; Li, Ji; Tian, Jifa; Xuan, Yi; Deng, Biwei; McNear, Kelly L; Lim, Daw Gen; Chen, Yong; Yang, Chen; Cheng, Gary J

2016-12-14

Semiconductor nanowires (SCNWs) provide a unique tunability of electro-optical property than their bulk counterparts (e.g., polycrystalline thin films) due to size effects. Nanoscale straining of SCNWs is desirable to enable new ways to tune the properties of SCNWs, such as electronic transport, band structure, and quantum properties. However, there are two bottlenecks to prevent the real applications of straining engineering of SCNWs: strainability and scalability. Unlike metallic nanowires which are highly flexible and mechanically robust for parallel shaping, SCNWs are brittle in nature and could easily break at strains slightly higher than their elastic limits. In addition, the ability to generate nanoshaping in large scale is limited with the current technologies, such as the straining of nanowires with sophisticated manipulators, nanocombing NWs with U-shaped trenches, or buckling NWs with prestretched elastic substrates, which are incompatible with semiconductor technology. Here we present a top-down fabrication methodology to achieve large scale nanoshaping of SCNWs in parallel with tunable elastic strains. This method utilizes nanosecond pulsed laser to generate shock pressure and conformably deform the SCNWs onto 3D-nanostructured silicon substrates in a scalable and ultrafast manner. A polymer dielectric nanolayer is integrated in the process for cushioning the high strain-rate deformation, suppressing the generation of dislocations or cracks, and providing self-preserving mechanism for elastic strain storage in SCNWs. The elastic strain limits have been studied as functions of laser intensity, dimensions of nanowires, and the geometry of nanomolds. As a result of 3D straining, the inhomogeneous elastic strains in GeNWs result in notable Raman peak shifts and broadening, which bring more tunability of the electrical-optical property in SCNWs than traditional strain engineering. We have achieved the first 3D nanostraining enhanced germanium field-effect transistors from GeNWs. Due to laser shock induced straining effect, a more than 2-fold hole mobility enhancement and a 120% transconductance enhancement are obtained from the fabricated back-gated field effect transistors. The presented nanoshaping of SCNWs provide new ways to manipulate nanomaterials with tunable electrical-optical properties and open up many opportunities for nanoelectronics, the nanoelectrical-mechanical system, and quantum devices.

Controlling charge current through a DNA based molecular transistor

NASA Astrophysics Data System (ADS)

Behnia, S.; Fathizadeh, S.; Ziaei, J.

2017-01-01

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I-V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive.

Fabrication and transfer of flexible few-layers MoS2 thin film transistors to any arbitrary substrate.

PubMed

Salvatore, Giovanni A; Münzenrieder, Niko; Barraud, Clément; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Ensslin, Klaus; Tröster, Gerhard

2013-10-22

Recently, transition metal dichalcogenides (TMDCs) have attracted interest thanks to their large field effective mobility (>100 cm(2)/V · s), sizable band gap (around 1-2 eV), and mechanical properties, which make them suitable for high performance and flexible electronics. In this paper, we present a process scheme enabling the fabrication and transfer of few-layers MoS2 thin film transistors from a silicon template to any arbitrary organic or inorganic and flexible or rigid substrate or support. The two-dimensional semiconductor is mechanically exfoliated from a bulk crystal on a silicon/polyvinyl alcohol (PVA)/polymethyl methacrylane (PMMA) stack optimized to ensure high contrast for the identification of subnanometer thick flakes. Thin film transistors (TFTs) with structured source/drain and gate electrodes are fabricated following a designed procedure including steps of UV lithography, wet etching, and atomic layer deposited (ALD) dielectric. Successively, after the dissolution of the PVA sacrificial layer in water, the PMMA film, with the devices on top, can be transferred to another substrate of choice. Here, we transferred the devices on a polyimide plastic foil and studied the performance when tensile strain is applied parallel to the TFT channel. We measured an electron field effective mobility of 19 cm(2)/(V s), an I(on)/I(off)ratio greater than 10(6), a gate leakage current as low as 0.3 pA/μm, and a subthreshold swing of about 250 mV/dec. The devices continue to work when bent to a radius of 5 mm and after 10 consecutive bending cycles. The proposed fabrication strategy can be extended to any kind of 2D materials and enable the realization of electronic circuits and optical devices easily transferrable to any other support.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

NASA Astrophysics Data System (ADS)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Highly Conductive Graphene/Ag Hybrid Fibers for Flexible Fiber-Type Transistors.

PubMed

Yoon, Sang Su; Lee, Kang Eun; Cha, Hwa-Jin; Seong, Dong Gi; Um, Moon-Kwang; Byun, Joon-Hyung; Oh, Youngseok; Oh, Joon Hak; Lee, Wonoh; Lee, Jea Uk

2015-11-09

Mechanically robust, flexible, and electrically conductive textiles are highly suitable for use in wearable electronic applications. In this study, highly conductive and flexible graphene/Ag hybrid fibers were prepared and used as electrodes for planar and fiber-type transistors. The graphene/Ag hybrid fibers were fabricated by the wet-spinning/drawing of giant graphene oxide and subsequent functionalization with Ag nanoparticles. The graphene/Ag hybrid fibers exhibited record-high electrical conductivity of up to 15,800 S cm(-1). As the graphene/Ag hybrid fibers can be easily cut and placed onto flexible substrates by simply gluing or stitching, ion gel-gated planar transistors were fabricated by using the hybrid fibers as source, drain, and gate electrodes. Finally, fiber-type transistors were constructed by embedding the graphene/Ag hybrid fiber electrodes onto conventional polyurethane monofilaments, which exhibited excellent flexibility (highly bendable and rollable properties), high electrical performance (μh = 15.6 cm(2) V(-1) s(-1), Ion/Ioff > 10(4)), and outstanding device performance stability (stable after 1,000 cycles of bending tests and being exposed for 30 days to ambient conditions). We believe that our simple methods for the fabrication of graphene/Ag hybrid fiber electrodes for use in fiber-type transistors can potentially be applied to the development all-organic wearable devices.

Transistors and tunnel diodes enabled by large-scale MoS2 nanosheets grown on GaN

NASA Astrophysics Data System (ADS)

San Yip, Pak; Zou, Xinbo; Cho, Wai Ching; Wu, Kam Lam; Lau, Kei May

2017-07-01

We report growth, fabrication, and device results of MoS2-based transistors and diodes implemented on a single 2D/3D material platform. The 2D/3D platform consists of a large-area MoS2 thin film grown on SiO2/p-GaN substrates. Atomic force microscopy, scanning electron microscopy, and Raman spectroscopy were used to characterize the thickness and quality of the as-grown MoS2 film, showing that the large-area MoS2 nanosheet has a smooth surface morphology constituted by small grains. Starting from the same material, both top-gated MoS2 field effect transistors and MoS2/SiO2/p-GaN heterojunction diodes were fabricated. The transistors exhibited a high on/off ratio of 105, a subthreshold swing of 74 mV dec-1, field effect mobility of 0.17 cm2 V-1 s-1, and distinctive current saturation characteristics. For the heterojunction diodes, current-rectifying characteristics were demonstrated with on-state current density of 29 A cm-2 and a current blocking property up to -25 V without breakdown. The reported transistors and diodes enabled by the same 2D/3D material stack present promising building blocks for constructing future nanoscale electronics.

Highly Conductive Graphene/Ag Hybrid Fibers for Flexible Fiber-Type Transistors

PubMed Central

Yoon, Sang Su; Lee, Kang Eun; Cha, Hwa-Jin; Seong, Dong Gi; Um, Moon-Kwang; Byun, Joon-Hyung; Oh, Youngseok; Oh, Joon Hak; Lee, Wonoh; Lee, Jea Uk

2015-01-01

Mechanically robust, flexible, and electrically conductive textiles are highly suitable for use in wearable electronic applications. In this study, highly conductive and flexible graphene/Ag hybrid fibers were prepared and used as electrodes for planar and fiber-type transistors. The graphene/Ag hybrid fibers were fabricated by the wet-spinning/drawing of giant graphene oxide and subsequent functionalization with Ag nanoparticles. The graphene/Ag hybrid fibers exhibited record-high electrical conductivity of up to 15,800 S cm−1. As the graphene/Ag hybrid fibers can be easily cut and placed onto flexible substrates by simply gluing or stitching, ion gel-gated planar transistors were fabricated by using the hybrid fibers as source, drain, and gate electrodes. Finally, fiber-type transistors were constructed by embedding the graphene/Ag hybrid fiber electrodes onto conventional polyurethane monofilaments, which exhibited excellent flexibility (highly bendable and rollable properties), high electrical performance (μh = 15.6 cm2 V−1 s−1, Ion/Ioff > 104), and outstanding device performance stability (stable after 1,000 cycles of bending tests and being exposed for 30 days to ambient conditions). We believe that our simple methods for the fabrication of graphene/Ag hybrid fiber electrodes for use in fiber-type transistors can potentially be applied to the development all-organic wearable devices. PMID:26549711

Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

PubMed Central

Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

2016-01-01

Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

The Warm, Rich Sound of Valve Guitar Amplifiers

ERIC Educational Resources Information Center

Keeports, David

2017-01-01

Practical solid state diodes and transistors have made glass valve technology nearly obsolete. Nevertheless, valves survive largely because electric guitar players much prefer the sound of valve amplifiers to the sound of transistor amplifiers. This paper discusses the introductory-level physics behind that preference. Overdriving an amplifier…

Top-down nanofabrication of silicon nanoribbon field effect transistor (Si-NR FET) for carcinoembryonic antigen detection.

PubMed

Bao, Zengtao; Sun, Jialin; Zhao, Xiaoqian; Li, Zengyao; Cui, Songkui; Meng, Qingyang; Zhang, Ye; Wang, Tong; Jiang, Yanfeng

2017-01-01

Sensitive and quantitative detection of tumor markers is highly required in the clinic for cancer diagnosis and consequent treatment. A field-effect transistor-based (FET-based) nanobiosensor emerges with characteristics of being label-free, real-time, having high sensitivity, and providing direct electrical readout for detection of biomarkers. In this paper, a top-down approach is proposed and implemented to fulfill a novel silicon nano-ribbon FET, which acts as biomarker sensor for future clinical application. Compared with the bottom-up approach, a top-down fabrication approach can confine width and length of the silicon FET precisely to control its electrical properties. The silicon nanoribbon (Si-NR) transistor is fabricated on a Silicon-on-Insulator (SOI) substrate by a top-down approach with complementary metal oxide semiconductor (CMOS)-compatible technology. After the preparation, the surface of Si-NR is functionalized with 3-aminopropyltriethoxysilane (APTES). Glutaraldehyde is utilized to bind the amino terminals of APTES and antibody on the surface. Finally, a microfluidic channel is integrated on the top of the device, acting as a flowing channel for the carcinoembryonic antigen (CEA) solution. The Si-NR FET is 120 nm in width and 25 nm in height, with ambipolar electrical characteristics. A logarithmic relationship between the changing ratio of the current and the CEA concentration is measured in the range of 0.1-100 ng/mL. The sensitivity of detection is measured as 10 pg/mL. The top-down fabricated biochip shows feasibility in direct detecting of CEA with the benefits of real-time, low cost, and high sensitivity as a promising biosensor for tumor early diagnosis.

A hybrid nanomemristor/transistor logic circuit capable of self-programming

PubMed Central

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A. A.; Wu, Wei; Stewart, Duncan R.; Williams, R. Stanley

2009-01-01

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

PubMed

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

New Flexible Channels for Room Temperature Tunneling Field Effect Transistors.

PubMed

Hao, Boyi; Asthana, Anjana; Hazaveh, Paniz Khanmohammadi; Bergstrom, Paul L; Banyai, Douglas; Savaikar, Madhusudan A; Jaszczak, John A; Yap, Yoke Khin

2016-02-05

Tunneling field effect transistors (TFETs) have been proposed to overcome the fundamental issues of Si based transistors, such as short channel effect, finite leakage current, and high contact resistance. Unfortunately, most if not all TFETs are operational only at cryogenic temperatures. Here we report that iron (Fe) quantum dots functionalized boron nitride nanotubes (QDs-BNNTs) can be used as the flexible tunneling channels of TFETs at room temperatures. The electrical insulating BNNTs are used as the one-dimensional (1D) substrates to confine the uniform formation of Fe QDs on their surface as the flexible tunneling channel. Consistent semiconductor-like transport behaviors under various bending conditions are detected by scanning tunneling spectroscopy in a transmission electron microscopy system (in-situ STM-TEM). As suggested by computer simulation, the uniform distribution of Fe QDs enable an averaging effect on the possible electron tunneling pathways, which is responsible for the consistent transport properties that are not sensitive to bending.

Reducing flicker noise in chemical vapor deposition graphene field-effect transistors

NASA Astrophysics Data System (ADS)

Arnold, Heather N.; Sangwan, Vinod K.; Schmucker, Scott W.; Cress, Cory D.; Luck, Kyle A.; Friedman, Adam L.; Robinson, Jeremy T.; Marks, Tobin J.; Hersam, Mark C.

2016-02-01

Single-layer graphene derived from chemical vapor deposition (CVD) holds promise for scalable radio frequency (RF) electronic applications. However, prevalent low-frequency flicker noise (1/f noise) in CVD graphene field-effect transistors is often up-converted to higher frequencies, thus limiting RF device performance. Here, we achieve an order of magnitude reduction in 1/f noise in field-effect transistors based on CVD graphene transferred onto silicon oxide substrates by utilizing a processing protocol that avoids aqueous chemistry after graphene transfer. Correspondingly, the normalized noise spectral density (10-7-10-8 μm2 Hz-1) and noise amplitude (4 × 10-8-10-7) in these devices are comparable to those of exfoliated and suspended graphene. We attribute the reduction in 1/f noise to a decrease in the contribution of fluctuations in the scattering cross-sections of carriers arising from dynamic redistribution of interfacial disorder.

All 2D, high mobility, flexible, transparent thin film transistor

DOEpatents

Das, Saptarshi; Sumant, Anirudha V.; Roelofs, Andreas

2017-01-17

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

PubMed

Egard, M; Johansson, S; Johansson, A-C; Persson, K-M; Dey, A W; Borg, B M; Thelander, C; Wernersson, L-E; Lind, E

2010-03-10

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

Effect of nickel silicide gettering on metal-induced crystallized polycrystalline-silicon thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Lee, Yong Hee; Joo, Seung Ki

2017-06-01

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. He received the B.S. degree in School of Advanced Materials Engineering from Kookmin University, Seoul, South Korea in 2012, and the M.S. degree in Department of Materials Science and Engineering from Seoul National University, Seoul, South Korea in 2014. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and top-gate polycrystalline-silicon thin-film transistors. He received the M.S. degree in innovation technology from Ecol Polytechnique, Palaiseau, France in 2013. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and copper-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He is currently pursuing the integrated M.S and Ph.D course with the Department of Materials Science and Engineering, Seoul National University, Seoul. He is involved in semiconductor device fabrication technology and bottom-gate polycrystalline-silicon thin-film transistors. He received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, South Korea, in 1974, and the M.S. and Ph.D. degrees in material science and engineering from Stanford University, Stanford, CA, USA, in 1980 and 1983, respectively. He is currently a Professor with the Department of Materials Science and Engineering, Seoul National University, Seoul.

Orthogonal Chip Based Electronic Sensors for Chemical Agents

DTIC Science & Technology

2012-04-06

operation with ultralow power requirements. This work has been carried out with the aid of substrate wafers provided by Qualcomm . The initial...produced by Qualcomm as a less expensive OTFT platform for sensors. 8. New Discoveries Air-stable organic thin-film transistor (OTFT) sensors

Plasma-Assisted Atomic Layer Deposition of High-Density Ni Nanoparticles for Amorphous In-Ga-Zn-O Thin Film Transistor Memory

NASA Astrophysics Data System (ADS)

Qian, Shi-Bing; Wang, Yong-Ping; Shao, Yan; Liu, Wen-Jun; Ding, Shi-Jin

2017-02-01

For the first time, the growth of Ni nanoparticles (NPs) was explored by plasma-assisted atomic layer deposition (ALD) technique using NiCp2 and NH3 precursors. Influences of substrate temperature and deposition cycles on ALD Ni NPs were studied by field emission scanning electron microscope and X-ray photoelectron spectroscopy. By optimizing the process parameters, high-density and uniform Ni NPs were achieved in the case of 280 °C substrate temperature and 50 deposition cycles, exhibiting a density of 1.5 × 1012 cm-2 and a small size of 3 4 nm. Further, the above Ni NPs were used as charge storage medium of amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistor (TFT) memory, demonstrating a high storage capacity for electrons. In particular, the nonvolatile memory exhibited an excellent programming characteristic, e.g., a large threshold voltage shift of 8.03 V was obtained after being programmed at 17 V for 5 ms.

Surface morphology of Al0.3Ga0.7N/Al2O3-high electron mobility transistor structure.

PubMed

Cörekçi, S; Usanmaz, D; Tekeli, Z; Cakmak, M; Ozçelik, S; Ozbay, E

2008-02-01

We present surface properties of buffer films (AIN and GaN) and Al0.3Gao.zN/Al2O3-High Electron Mobility Transistor (HEMT) structures with/without AIN interlayer grown on High Temperature (HT)-AIN buffer/Al2O3 substrate and Al2O3 substrate. We have found that the GaN surface morphology is step-flow in character and the density of dislocations was about 10(8)-10(9) cm(-2). The AFM measurements also exhibited that the presence of atomic steps with large lateral step dimension and the surface of samples was smooth. The lateral step sizes are in the range of 100-250 nm. The typical rms values of HEMT structures were found as 0.27, 0.30, and 0.70 nm. HT-AIN buffer layer can have a significant impact on the surface morphology of Al0.3Ga0.7N/Al2O3-HEMT structures.

Effect of Pentacene-dielectric Affinity on Pentacene Thin Film Growth Morphology in Organic Field-effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

S Kim; M Jang; H Yang

2011-12-31

Organic field-effect transistors (OFETs) are fabricated by depositing a thin film of semiconductor on the functionalized surface of a SiO{sub 2} dielectric. The chemical and morphological structures of the interface between the semiconductor and the functionalized dielectric are critical for OFET performance. We have characterized the effect of the affinity between semiconductor and functionalized dielectric on the properties of the semiconductor-dielectric interface. The crystalline microstructure/nanostructure of the pentacene semiconductor layers, grown on a dielectric substrate that had been functionalized with either poly(4-vinyl pyridine) or polystyrene (to control hydrophobicity), and grown under a series of substrate temperatures and deposition rates, weremore » characterized by X-ray diffraction, photoemission spectroscopy, and atomic force microscopy. By comparing the morphological features of the semiconductor thin films with the device characteristics (field-effect mobility, threshold voltage, and hysteresis) of the OFET devices, the effect of affinity-driven properties on charge modulation, charge trapping, and charge carrier transport could be described.« less

Mobility-dependent low-frequency noise in graphene field-effect transistors.

PubMed

Zhang, Yan; Mendez, Emilio E; Du, Xu

2011-10-25

We have investigated the low-frequency 1/f noise of both suspended and on-substrate graphene field-effect transistors and its dependence on gate voltage, in the temperature range between 300 and 30 K. We have found that the noise amplitude away from the Dirac point can be described by a generalized Hooge's relation in which the Hooge parameter α(H) is not constant but decreases monotonically with the device's mobility, with a universal dependence that is sample and temperature independent. The value of α(H) is also affected by the dynamics of disorder, which is not reflected in the DC transport characteristics and varies with sample and temperature. We attribute the diverse behavior of gate voltage dependence of the noise amplitude to the relative contributions from various scattering mechanisms, and to potential fluctuations near the Dirac point caused by charge carrier inhomogeneity. The higher carrier mobility of suspended graphene devices accounts for values of 1/f noise significantly lower than those observed in on-substrate graphene devices and most traditional electronic materials.

Solution processed flexible organic thin film back-gated transistors based on polyimide dielectric films

NASA Astrophysics Data System (ADS)

Park, Janghoon; Min, Yoonki; Lee, Dongjin

2018-04-01

An organic thin film back-gated transistor (OBGT) was fabricated and characterized. The gate electrode was printed on the back side of substrate, and the dielectric layer was omitted by substituting the dielectric layer with the polyimide (PI) film substrate. Roll-to-roll (R2R) gravure printing, doctor blading, and drop casting methods were used to fabricate the OBGT. The printed OBGT device shows better performance compared with an OTFT device based on dielectric layer of BaTiO3. Additionally, a calendering process enhanced the performance by a factor of 3 to 7 (mobility: 0.016 cm2/V.s, on/off ratio: 9.17×103). A bending test was conducted to confirm the flexibility and durability of the OBGT device. The results show the fabricated device endures 20000-cyclic motions. The realized OBGT device was successfully fabricated and working, which is meaningful for production engineering from the viewpoint of process development.

Effects of various oxygen partial pressures on Ti-doped ZnO thin film transistors fabricated on flexible plastic substrate

NASA Astrophysics Data System (ADS)

Cui, Guodong; Han, Dedong; Yu, Wen; Shi, Pan; Zhang, Yi; Huang, Lingling; Cong, Yingying; Zhou, Xiaoliang; Zhang, Xiaomi; Zhang, Shengdong; Zhang, Xing; Wang, Yi

2016-04-01

By applying a novel active layer of titanium zinc oxide (TiZO), we have successfully fabricated fully transparent thin-film transistors (TFTs) with a bottom gate structure fabricated on a flexible plastic substrate at low temperatures. The effects of various oxygen partial pressures during channel deposition were studied to improve the device performance. We found that the oxygen partial pressure during channel deposition has a significant impact on the performance of TiZO TFTs, and that the TFT developed under 10% oxygen partial pressure exhibits superior performance with a low threshold voltage (V th) of 2.37 V, a high saturation mobility (μsat) of 125.4 cm2 V-1 s-1, a steep subthreshold swing (SS) of 195 mV/decade and a high I on/I off ratio of 3.05 × 108. These results suggest that TiZO thin films are promising for high-performance fully transparent flexible TFTs and displays.

Remarkably High Mobility Thin-Film Transistor on Flexible Substrate by Novel Passivation Material.

PubMed

Shih, Cheng Wei; Chin, Albert

2017-04-25

High mobility thin-film transistor (TFT) is crucial for future high resolution and fast response flexible display. Remarkably high performance TFT, made at room temperature on flexible substrate, is achieved with record high field-effect mobility (μ FE ) of 345 cm 2 /Vs, small sub-threshold slope (SS) of 103 mV/dec, high on-current/off-current (I ON /I OFF ) of 7 × 10 6 , and a low drain-voltage (V D ) of 2 V for low power operation. The achieved mobility is the best reported data among flexible electronic devices, which is reached by novel HfLaO passivation material on nano-crystalline zinc-oxide (ZnO) TFT to improve both I ON and I OFF . From X-ray photoelectron spectroscopy (XPS) analysis, the non-passivated device has high OH-bonding intensity in nano-crystalline ZnO, which damage the crystallinity, create charged scattering centers, and form potential barriers to degrade mobility.

320-nm Flexible Solution-Processed 2,7-dioctyl[1] benzothieno[3,2-b]benzothiophene Transistors.

PubMed

Ren, Hang; Tang, Qingxin; Tong, Yanhong; Liu, Yichun

2017-08-09

Flexible organic thin-film transistors (OTFTs) have received extensive attention due to their outstanding advantages such as light weight, low cost, flexibility, large-area fabrication, and compatibility with solution-processed techniques. However, compared with a rigid substrate, it still remains a challenge to obtain good device performance by directly depositing solution-processed organic semiconductors onto an ultrathin plastic substrate. In this work, ultrathin flexible OTFTs are successfully fabricated based on spin-coated 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene (C8-BTBT) films. The resulting device thickness is only ~320 nm, so the device has the ability to adhere well to a three-dimension curved surface. The ultrathin C8-BTBT OTFTs exhibit a mobility as high as 4.36 cm² V -1 s -1 and an on/off current ratio of over 10⁶. These results indicate the substantial promise of our ultrathin flexible C8-BTBT OTFTs for next-generation flexible and conformal electronic devices.

320-nm Flexible Solution-Processed 2,7-dioctyl[1] benzothieno[3,2-b]benzothiophene Transistors

PubMed Central

Ren, Hang; Tang, Qingxin; Tong, Yanhong; Liu, Yichun

2017-01-01

Flexible organic thin-film transistors (OTFTs) have received extensive attention due to their outstanding advantages such as light weight, low cost, flexibility, large-area fabrication, and compatibility with solution-processed techniques. However, compared with a rigid substrate, it still remains a challenge to obtain good device performance by directly depositing solution-processed organic semiconductors onto an ultrathin plastic substrate. In this work, ultrathin flexible OTFTs are successfully fabricated based on spin-coated 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene (C8-BTBT) films. The resulting device thickness is only ~320 nm, so the device has the ability to adhere well to a three-dimension curved surface. The ultrathin C8-BTBT OTFTs exhibit a mobility as high as 4.36 cm2 V−1 s−1 and an on/off current ratio of over 106. These results indicate the substantial promise of our ultrathin flexible C8-BTBT OTFTs for next-generation flexible and conformal electronic devices. PMID:28792438

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Passivation and Depassivation of Defects in Graphene-based field-effect transistors

NASA Astrophysics Data System (ADS)

O'Hara, Andrew; Wang, Pan; Perini, Chris J.; Fleetwood, Daniel M.; Vogel, Eric M.; Pantelides, Sokrates T.

Field effect transistors based on graphene on amorphous SiO2 substrates were fabricated, both with and without a top oxide passivation layer of Al2O3. Initial I-V characteristics of these devices show that the Fermi energy occurs below the Dirac point in graphene (i.e. p-type behavior). Introduction of environmental stresses, e.g. baking the devices, causes a shift in the Fermi energy relative to the Dirac point. 1/f noise measurements indicate the presence of charge trapping defects. In order to find the origins of this behavior, we construct atomistic models of the substrate/graphene interface and the graphene/oxide passivation layer interface. Using density functional theory, we investigate the role that the introduction and removal of hydrogen and hydroxide passivants has on the electronic structure of the graphene layer as well as the relative energetics for these processes to occur in order to gain insights into the experimental results. Supported by DTRA: 1-16-0032 and NSF: ECCS-1508898.

Application of pentacene thin-film transistors with controlled threshold voltages to enhancement/depletion inverters

NASA Astrophysics Data System (ADS)

Takahashi, Hajime; Hanafusa, Yuki; Kimura, Yoshinari; Kitamura, Masatoshi

2018-03-01

Oxygen plasma treatment has been carried out to control the threshold voltage in organic thin-film transistors (TFTs) having a SiO2 gate dielectric prepared by rf sputtering. The threshold voltage linearly changed in the range of -3.7 to 3.1 V with the increase in plasma treatment time. Although the amount of change is smaller than that for organic TFTs having thermally grown SiO2, the tendency of the change was similar to that for thermally grown SiO2. To realize different plasma treatment times on the same substrate, a certain region on the SiO2 surface was selected using a shadow mask, and was treated with oxygen plasma. Using the process, organic TFTs with negative threshold voltages and those with positive threshold voltages were fabricated on the same substrate. As a result, enhancement/depletion inverters consisting of the organic TFTs operated at supply voltages of 5 to 15 V.

Radiation sensitivity of graphene field effect transistors and other thin film architectures

NASA Astrophysics Data System (ADS)

Cazalas, Edward

An important contemporary motivation for advancing radiation detection science and technology is the need for interdiction of nuclear and radiological materials, which may be used to fabricate weapons of mass destruction. The detection of such materials by nuclear techniques relies on achieving high sensitivity and selectivity to X-rays, gamma-rays, and neutrons. To be attractive in field deployable instruments, it is desirable for detectors to be lightweight, inexpensive, operate at low voltage, and consume low power. To address the relatively low particle flux in most passive measurements for nuclear security applications, detectors scalable to large areas that can meet the high absolute detection efficiency requirements are needed. Graphene-based and thin-film-based radiation detectors represent attractive technologies that could meet the need for inexpensive, low-power, size-scalable detection architectures, which are sensitive to X-rays, gamma-rays, and neutrons. The utilization of graphene to detect ionizing radiation relies on the modulation of graphene charge carrier density by changes in local electric field, i.e. the field effect in graphene. Built on the principle of a conventional field effect transistor, the graphene-based field effect transistor (GFET) utilizes graphene as a channel and a semiconducting substrate as an absorber medium with which the ionizing radiation interacts. A radiation interaction event that deposits energy within the substrate creates electron-hole pairs, which modify the electric field and modulate graphene charge carrier density. A detection event in a GFET is therefore measured as a change in graphene resistance or current. Thin (micron-scale) films can also be utilized for radiation detection of thermal neutrons provided nuclides with high neutron absorption cross section are present with appreciable density. Detection in thin-film detectors could be realized through the collection of charge carriers generated within the film by slowing-down of neutron capture reaction products. The objective of this dissertation is to develop, characterize, and optimize novel graphene-based and thin-film radiation detectors. The dissertation includes a review of relevant physics, comprehensive descriptions and discussions of the experimental campaigns that were conducted, computational simulations, and detailed analysis of certain processes occurring in graphene-based and thin-film radiation detectors that significantly affect their response characteristics. Experiments have been conducted to characterize the electrical properties of GFETs and their responsivity to radiation of different types, such as visible, ultraviolet, X-ray, and gamma-ray photons, and alpha particles. The nature of graphene hysteretic effects under operational conditions has been studied. Spatially dependent sensitivity of GFETs to irradiation has been experimentally investigated using both a focused laser beam and focused X-ray microbeam. A model has been developed that deterministically simulates the mechanisms of charge transport within the GFET substrate and explains the experimental finding that the effective area of the GFET significantly exceeds the size of graphene. Monte Carlo simulations were also carried out to examine the efficacy of thin-film radiation detectors based on 10B-enriched boron nitride and Gd2O3 for neutron detection.

Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrappedmore » around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal–oxide–semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.« less

GaAs-based optoelectronic neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H. (Inventor); Kim, Jae H. (Inventor); Psaltis, Demetri (Inventor)

1993-01-01

An integrated, optoelectronic, variable thresholding neuron implemented monolithically in GaAs integrated circuit and exhibiting high differential optical gain and low power consumption is presented. Two alternative embodiments each comprise an LED monolithically integrated with a detector and two transistors. One of the transistors is responsive to a bias voltage applied to its gate for varying the threshold of the neuron. One embodiment is implemented as an LED monolithically integrated with a double heterojunction bipolar phototransistor (detector) and two metal semiconductor field effect transistors (MESFET's) on a single GaAs substrate and another embodiment is implemented as an LED monolithically integrated with three MESFET's (one of which is an optical FET detector) on a single GaAs substrate. The first noted embodiment exhibits a differential optical gain of 6 and an optical switching energy of 10 pJ. The second embodiment has a differential optical gain of 80 and an optical switching energy of 38 pJ. Power consumption is 2.4 and 1.8 mW, respectively. Input 'light' power needed to turn on the LED is 2 micro-W and 54 nW, respectively. In both embodiments the detector is in series with a biasing MESFET and saturates the other MESFET upon detecting light above a threshold level. The saturated MESFET turns on the LED. Voltage applied to the biasing MESFET gate controls the threshold.

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Charge transfer at organic-organic heterojunctions, and remote doping of a pentacene transistor

NASA Astrophysics Data System (ADS)

Zhao, Wei

Organic-organic heterojunctions (OOHs) are the fundamental building blocks of organic devices, such as organic light-emitting diodes, organic photovoltaic cells, and photo detectors. Transport of free electrons and holes, exciton formation, recombination or dissociation, and various other physical processes all take place in OOHs. Understanding the electronic structures of OOH is critical for studying device physics and further improving the performance of organic devices. This work focuses on the electronic structure, i.e., the energy level alignment, at OOHs, investigated by ultraviolet and inverse photoemission spectroscopy (UPS and IPES). The weak interaction that generally prevails at OOH interfaces leads to small interface dipoles of 0˜0.5eV. The experimental observations on the majority of OOHs studied can be semi-quantitatively predicted by the model derived from the induced density of interface states and charge neutrality level (IDIS/CNL). However, we also find that the electronic structure of interfaces between two small-band-gap semiconductors, e.g., using copper phthalocyanine (CuPc) as the donor and a tris(thieno)-hexaazatriphenylene derivative (THAP) as the acceptor, is strongly influenced by changes in the substrate work function. In these cases, the charge transfer that takes place at the interface is governed by thermodynamic equilibrium, dominating any subtle interaction due to IDIS/CNL. The impact of doping on the energy level alignment of OOHs is also studied. The charges donated by the dopant molecules transfer from the parent doped layer to the adjacent undoped layer, taking advantage of the molecular level offset, and are then spatially separated from the dopant molecules. Remote doping, based on this charge transfer mechanism, is demonstrated with the heterojunction formed between pentacene and N,N'-diphenyl-N,N'-bis(1-naphthyl)-1,1'bisphenyl-4,4'diazine (alpha-NPD) p-doped with tris[1,2-bis(trifluoromethyl) ethane-1,2-dithiolene] (Mo(tfd)3). A remotely doped pentacene transistor, based on this type of hetero-structure, exhibits increased conductivity, decreased activation energy for carrier hopping, and enhanced mobility, compared to an undoped transistor. Another featured improvement of the remotely doped transistor is that it can be reasonably switched off by placing an undoped interlayer in the structure. Our preliminary results show chemical doping technology can potentially benefit the organic thin film transistors.

Wafer scale BN on sapphire substrates for improved graphene transport.

PubMed

Vangala, Shivashankar; Siegel, Gene; Prusnick, Timothy; Snure, Michael

2018-06-11

Wafer scale (2") BN grown by metal organic chemical vapor deposition (MOCVD) on sapphire was examined as a weakly interacting dielectric substrate for graphene, demonstrating improved transport properties over conventional sapphire and SiO 2 /Si substrates. Chemical vapor deposition grown graphene was transferred to BN/sapphire substrates for evaluation of more than 30 samples using Raman and Hall effects measurements. A more than 2x increase in Hall mobility and 10x reduction in sheet carrier density was measured for graphene on BN/sapphire compared to sapphire substrates. Through control of the MOCVD process, BN films with roughness ranging from <0.1 nm to >1 nm were grown and used to study the effects of substrate roughness on graphene transport. Arrays of graphene field effect transistors were fabricated on 2" BN/sapphire substrates demonstrating scalability and device performance enhancement.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Ultrathin and lightweight organic solar cells with high flexibility

PubMed Central

Kaltenbrunner, Martin; White, Matthew S.; Głowacki, Eric D.; Sekitani, Tsuyoshi; Someya, Takao; Sariciftci, Niyazi Serdar; Bauer, Siegfried

2012-01-01

Application-specific requirements for future lighting, displays and photovoltaics will include large-area, low-weight and mechanical resilience for dual-purpose uses such as electronic skin, textiles and surface conforming foils. Here we demonstrate polymer-based photovoltaic devices on plastic foil substrates less than 2 μm thick, with equal power conversion efficiency to their glass-based counterparts. They can reversibly withstand extreme mechanical deformation and have unprecedented solar cell-specific weight. Instead of a single bend, we form a random network of folds within the device area. The processing methods are standard, so the same weight and flexibility should be achievable in light emitting diodes, capacitors and transistors to fully realize ultrathin organic electronics. These ultrathin organic solar cells are over ten times thinner, lighter and more flexible than any other solar cell of any technology to date. PMID:22473014

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hasanah, Lilik, E-mail: lilikhasanah@upi.edu; Suhendi, Endi; Tayubi, Yuyu Rahmat

In this work we discuss the surface roughness of Si interface impact to the tunneling current of the Si/Si{sub 1-x}Ge{sub x}/Si heterojunction bipolar transistor. The Si interface surface roughness can be analyzed from electrical characteristics through the transversal electron velocity obtained as fitting parameter factor. The results showed that surface roughness increase as Ge content of virtual substrate increase This model can be used to investigate the effect of Ge content of the virtual substrate to the interface surface condition through current-voltage characteristic.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Electrical Performance of Monolayer MoS2 Field-Effect Transistors Prepared by Chemical Vapor Deposition

DTIC Science & Technology

2013-05-16

Furthermore, MoS2 also shows promise for use in logic circuits and optoelectronic devices, and it is a promising material for use on flexible and...onto an auxiliary silicon substrate and placed inside a tube furnace with the growth substrates surrounding it. Sulfur powder, placed upstream near the...opening of the furnace at an approximate temperature of 600 C, was subli- mated for use as the sulfur vapor source. The furnace was heated to a peak

Enhanced Hole Mobility and Density in GaSb Quantum Wells

DTIC Science & Technology

2013-01-01

Keywords: Molecular beam epitaxy Quantum wells Semiconducting III–V materials Field-effect transistors GaSb a b s t r a c t Modulation-doped quantum wells...QWs) of GaSb clad by AlAsSb were grown by molecular beam epitaxy on InP substrates. By virtue of quantum confinement and compressive strain of the...heterostructures studied here are grown by molecular beam epitaxy (MBE) on semi-insulating (001) InP substrates using a Riber Compact 21T MBE system. A cross

Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang H. (Inventor); King, Glen C. (Inventor)

2011-01-01

Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulle; Robinson, Daryl C.; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel translators and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. Furthermore, the ability to form devices on flexible substrates expands the range of applications where electronic circuitry can be introduced. For NASA, nonotechndogy offers opportunities for increased onboard data processing and thus autonomous decision-making ability, ad novel sensors that detect and respond to external stimuli with few oversight requirements. The goat of this work is to demonstrate transistor behavior in polyaniline/ polyethylene oxide nanofibers, thus creating a foundation for future logic devices.

Maskless selective laser patterning of PEDOT:PSS on barrier/foil for organic electronics applications

NASA Astrophysics Data System (ADS)

Karnakis, Dimitris; Stephens, Tim; Chabrol, Gregoire

2013-03-01

Rapid developments in organic electronics promise low cost devices for applications such as OLED, organic transistors and organic photovoltaics on large-area glass or flexible substrates in the near future. The technology is very attractive as most device layers can be solution printed. But when directly patterned deposition is impossible, a post-patterning step is required and laser processing is gradually emerging as a key-enabling tool. DPSS lasers offer several advantages including maskless, non-contact, dry patterning, but also scalable large area processing, well suited to roll-to-roll manufacturing at μm resolutions. However, very few reports discuss in detail the merits of DPSS laser patterning technology, especially on flexible substrates. This paper describes the potential of ultrafast DPSS laser technology for OLED fabrication on foil and, specifically, picosecond laser ablation of PEDOT:PSS on multilayered barrier/foil or metal grids aimed as a synthetic alternative to inorganic transparent conductive electrodes. Key requirements include: (a) the complete removal of PEDOT layers without residue, (b) the complete absence of surface contamination from redeposited laser debris to avoid short circuiting and (c) no loss in performance of from laser exposure. We will demonstrate that with careful optimisation and appropriate choice of ultrafast laser, the above criteria can be fulfilled. A suitable process window exists resulting in clean laser structuring without damage to the underlying heat sensitive barrier layers whilst also containing laser debris. A low temperature ablation most likely proceeds via a stress-assisted (film fracture and ejection) process as opposed to vaporisation or other phase change commonly encountered with longer pulse lasers.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Nanoelectronics and Plasma Processing---The Next 15 Years and Beyond

NASA Astrophysics Data System (ADS)

Lieberman, Michael A.

2006-10-01

The number of transistors per chip has doubled every 2 years since 1959, and this doubling will continue over the next 15 years as transistor sizes shrink. There has been a 25 million-fold decrease in cost for the same performance, and in 15 years a desktop computer will be hundreds of times more powerful than one today. Transistors now have 37 nm (120 atoms) gate lengths and 1.5 nm (5 atoms) gate oxide thicknesses. The smallest working transistor has a 5 nm (17 atoms) gate length, close to the limiting gate length, from simulations, of about 4 nm. Plasma discharges are used to fabricate hundreds of billions of these nano-size transistors on a silicon wafer. These discharges have evolved from a first generation of ``low density'' reactors capacitively driven by a single source, to a second generation of ``high density'' reactors (inductive and electron cyclotron resonance) having two rf power sources, in order to control independently the ion flux and ion bombarding energy to the substrate. A third generation of ``moderate density'' reactors, driven capacitively by one high and one low frequency rf source, is now widely used. Recently, triple frequency and combined dc/dual frequency discharges have been investigated, to further control processing characteristics, such as ion energy distributions, uniformity, and plasma etch selectivities. There are many interesting physics issues associated with these discharges, including stochastic heating of discharge electrons by dual frequency sheaths, nonlinear frequency interactions, powers supplied by the multi-frequency sources, and electromagnetic effects such as standing waves and skin effects. Beyond the 4 nm transistor limit lies a decade of further performance improvements for conventional nanoelectronics, and beyond that, a dimly-seen future of spintronics, single-electron transistors, cross-bar latches, and molecular electronics.

Zinc oxide films chemically grown onto rigid and flexible substrates for TFT applications

NASA Astrophysics Data System (ADS)

Suchea, M.; Kornilios, N.; Koudoumas, E.

2010-10-01

This contribution presents some preliminary results regarding the use of a chemical route for the growth of good quality ZnO thin films that can be used for the fabrication of thin film transistors (TFTs). The films were grown at rather low temperature (60 °C) on glass and PET substrates using non-aqueous (zinc acetate dihydrate in methanol) precursor solution and their surface morphology, crystalline structure, optical transmittance and electrical characteristics were studied. The study indicated that good quality films with desirable ZnO structure onto rigid and flexible substrates can be obtained, using a simple, cheap, low temperature chemical growth method.

Carbon nanotube transistors scaled to a 40-nanometer footprint.

PubMed

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution.

PubMed

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A; Anthopoulos, Thomas D

2017-03-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In 2 O 3 /ZnO heterojunction. We find that In 2 O 3 /ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In 2 O 3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In 2 O 3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution

PubMed Central

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A.; Anthopoulos, Thomas D.

2017-01-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In2O3/ZnO heterojunction. We find that In2O3/ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In2O3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In2O3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications. PMID:28435867

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Optically switched graphene/4H-SiC junction bipolar transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chandrashekhar, MVS; Sudarshan, Tangali S.; Omar, Sabih U.

A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on amore » first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.« less

High frequency characteristic of a monolithic 500 °C OpAmp-RC integrator in SiC bipolar IC technology

NASA Astrophysics Data System (ADS)

Tian, Ye; Zetterling, Carl-Mikael

2017-09-01

This paper presents a comprehensive investigation of the frequency response of a monolithic OpAmp-RC integrator implemented in a 4H-SiC bipolar IC technology. The circuits and devices have been measured and characterized from 27 to 500 °C. The devices have been modelled to identify that the substrate capacitance is a dominant factor affecting the OpAmp's high-frequency response. Large Miller compensation capacitors of more than 540 pF are required to ensure stability of the internal OpAmp. The measured unit-gain-bandwidth product of the OpAmp is ∼1.1 MHz at 27 °C, and decreases to ∼0.5 MHz at 500 °C mainly due to the reduction of the transistor's current gain. On the other hand, it is not necessary to compensate the integrator in a relatively wide bandwidth ∼0.7 MHz over the investigated temperature range. At higher frequencies, the integrator's frequency response has been identified to be significantly affected by that of the OpAmp and load impedance. This work demonstrates the potential of this technology for high temperature applications requiring bandwidths of several megahertz.

10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

NASA Astrophysics Data System (ADS)

Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

1985-02-01

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

High-power microwave LDMOS transistors for wireless data transmission technologies (Review)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kuznetsov, E. V., E-mail: E.Kouzntsov@tcen.ru; Shemyakin, A. V.

The fields of the application, structure, fabrication, and packaging technology of high-power microwave LDMOS transistors and the main advantages of these devices were analyzed. Basic physical parameters and some technology factors were matched for optimum device operation. Solid-state microwave electronics has been actively developed for the last 10-15 years. Simultaneously with improvement of old devices, new devices and structures are actively being adopted and developed and new semiconductor materials are being commercialized. Microwave LDMOS technology is in demand in such fields as avionics, civil and military radars, repeaters, base stations of cellular communication systems, television and broadcasting transmitters, and transceiversmore » for high-speed wireless computer networks (promising Wi-Fi and Wi-Max standards).« less

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Packaging Technologies for High Temperature Electronics and Sensors

NASA Technical Reports Server (NTRS)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Effect of excimer laser annealing on a-InGaZnO thin-film transistors passivated by solution-processed hybrid passivation layers

NASA Astrophysics Data System (ADS)

Bermundo, Juan Paolo; Ishikawa, Yasuaki; Fujii, Mami N.; Nonaka, Toshiaki; Ishihara, Ryoichi; Ikenoue, Hiroshi; Uraoka, Yukiharu

2016-01-01

We demonstrate the use of excimer laser annealing (ELA) as a low temperature annealing alternative to anneal amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) passivated by a solution-processed hybrid passivation layer. Usually, a-IGZO is annealed using thermal annealing at high temperatures of up to 400 °C. As an alternative to high temperature thermal annealing, two types of ELA, XeCl (308 nm) and KrF (248 nm) ELA, are introduced. Both ELA types enhanced the electrical characteristics of a-IGZO TFTs leading to a mobility improvement of ~13 cm2 V-1 s-1 and small threshold voltage which varied from ~0-3 V. Furthermore, two-dimensional heat simulation using COMSOL Multiphysics was used to identify possible degradation sites, analyse laser heat localization, and confirm that the substrate temperature is below 50 °C. The two-dimensional heat simulation showed that the substrate temperature remained at very low temperatures, less than 30 °C, during ELA. This implies that any flexible material can be used as the substrate. These results demonstrate the large potential of ELA as a low temperature annealing alternative for already-passivated a-IGZO TFTs.

A room temperature strategy towards enhanced performance and bias stability of oxide thin film transistor with a sandwich structure channel layer

NASA Astrophysics Data System (ADS)

Zeng, Yong; Ning, Honglong; Zheng, Zeke; Zhang, Hongke; Fang, Zhiqiang; Yao, Rihui; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao; Lu, Xubing

2017-04-01

Thermal annealing is a conventional and effective way to improve the bias stress stability of oxide thin film transistors (TFT) on solid substrates. However, it is still a challenge for enhancing the bias stress stability of oxide TFTs on flexible substrates by high-temperature post-treatment due to the thermal sensitivity of flexible substrates. Here, a room temperature strategy is presented towards enhanced performance and bias stability of oxide TFTs by intentionally engineering a sandwich structure channel layer consisting of a superlattice with aluminum doped zinc oxide (AZO) and Al2O3 thin films. The Al2O3/AZO/Al2O3-TFTs not only exhibit a saturation mobility of 9.27 cm2 V-1 s-1 and a linear mobility of 11.38 cm2 V-1 s-1 but also demonstrate a better bias stress stability than AZO/Al2O3-TFT. Moreover, the underlying mechanism of this enhanced electrical performance of TFTs with a sandwich structure channel layer is that the bottom Al2O3 thin films can obviously improve the crystalline phase of AZO films while decreasing electrical trapping centers and adsorption sites for undesirable molecules such as water and oxygen.

Organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Nanocrystal-based complementary inverters constructed on flexible plastic substrates.

PubMed

Jang, Jaewon; Cho, Kyoungah; Yun, Junggwon; Kim, Sangsig

2013-05-01

We demonstrate a nanocrystal (NC)-based complementary inverter constructed on a flexible plastic substrate. The NC-based complementary inverter consists of n-type HgSe NC- and p-type HgTe NC-based thin-film transistors (TFTs). Solid films on a plastic substrate obtained from HgSe and HgTe nanocrystals by thermal transformation are utilized as the n- and p-channel layers in these TFTs, respectively. The electrical properties of these component TFTs on unstrained and strained substrates are characterized and the performance of the inverter on the flexible substrate is investigated. The inverter on the unstrained substrate exhibits a logic gain of about 8, a logic swing of 90%, and a noise margin of 2.0 V. The characteristics of the inverter are changed under tensile and compressive strains, but not very significantly. Moreover, a comparison of the electrical characteristics of the n- and p-channel TFTs and the inverter is made in this paper.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

NASA Technical Reports Server (NTRS)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

High-Throughput Characterization of Vapor-Deposited Organic Glasses

NASA Astrophysics Data System (ADS)

Dalal, Shakeel S.

Glasses are non-equilibrium materials which on short timescales behave like solids, and on long timescales betray their liquid-like structure. The most common way of preparing a glass is to cool the liquid faster than it can structurally rearrange. Until recently, most preparation schemes for a glass were considered to result in materials with undifferentiable structure and properties. This thesis utilizes a particular preparation method, physical vapor deposition, in order to prepare glasses of organic molecules with properties otherwise considered to be unobtainable. The glasses are characterized using spectroscopic ellipsometry, both as a dilatometric technique and as a reporter of molecular packing. The results reported here develop ellipsometry as a dilatometric technique on a pair of model glass formers, alpha,alpha,beta-trisnaphthylbenzene and indomethacin. It is found that the molecular orientation, as measured by birefringence, can be tuned by changing the substrate temperature during the deposition. In order to efficiently characterize the properties of vapor-deposited indomethacin as a function of substrate temperature, a high-throughput method is developed to capture the entire interesting range of substrate temperatures in just a few experiments. This high-throughput method is then leveraged to describe molecular mobility in vapor-deposited indomethacin. It is also used to demonstrate that the behavior of organic semiconducting molecules agrees with indomethacin quantitatively, and this agreement has implications for emerging technologies such as light-emitting diodes, photovoltaics and thin-film transistors made from organic molecules.

Gold Nanoparticles on Functionalized Silicon Substrate under Coulomb Blockade Regime: An Experimental and Theoretical Investigation.

PubMed

Pluchery, Olivier; Caillard, Louis; Dollfus, Philippe; Chabal, Yves J

2018-01-18

Single charge electronics offer a way for disruptive technology in nanoelectronics. Coulomb blockade is a realistic way for controlling the electric current through a device with the accuracy of one electron. In such devices the current exhibits a step-like increase upon bias which reflects the discrete nature of the fundamental charge. We have assembled a double tunnel junction on an oxide-free silicon substrate that exhibits Coulomb staircase characteristics using gold nanoparticles (AuNPs) as Coulomb islands. The first tunnel junction is an insulating layer made of a grafted organic monolayer (GOM) developed for this purpose. The GOM also serves for attaching AuNPs covalently. The second tunnel junction is made by the tip of an STM. We show that this device exhibits reproducible Coulomb blockade I-V curves at 40 K in vacuum. We also show that depending on the doping of the silicon substrate, the whole Coulomb staircase can be adjusted. We have developed a simulation approach based on the orthodox theory that was completed by calculating the bias dependent tunnel barriers and by including an accurate calculation of the band bending. This model accounts for the experimental data and the doping dependence of Coulomb oscillations. This study opens new perspectives toward designing new kind of single electron transistors (SET) based on this dependence of the Coulomb staircase with the charge carrier concentration.

Hydrothermally Processed Photosensitive Field-Effect Transistor Based on ZnO Nanorod Networks

NASA Astrophysics Data System (ADS)

Kumar, Ashish; Bhargava, Kshitij; Dixit, Tejendra; Palani, I. A.; Singh, Vipul

2016-11-01

Formation of a stable, reproducible zinc oxide (ZnO) nanorod-network-based photosensitive field-effect transistor using a hydrothermal process at low temperature has been demonstrated. K2Cr2O7 additive was used to improve adhesion and facilitate growth of the ZnO nanorod network over the SiO2/Si substrate. Transistor characteristics obtained in the dark resemble those of the n-channel-mode field-effect transistor (FET). The devices showed I on/ I off ratio above 8 × 102 under dark condition, field-effect mobility of 4.49 cm2 V-1 s-1, and threshold voltage of -12 V. Further, under ultraviolet (UV) illumination, the FET exhibited sensitivity of 2.7 × 102 in off-state (-10 V) versus 1.4 in on-state (+9.7 V) of operation. FETs based on such nanorod networks showed good photoresponse, which is attributed to the large surface area of the nanorod network. The growth temperature for ZnO nanorod networks was kept at 110°C, enabling a low-temperature, cost-effective, simple approach for high-performance ZnO-based FETs for large-scale production. The role of network interfaces in the FET performance is also discussed.

Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

PubMed

Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki

2016-07-20

We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

NASA Astrophysics Data System (ADS)

Shen, Yanfei; Cui, Jie; Mohammadi, Saeed

2017-05-01

A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45 nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40 GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26 GHz. The developed model is simple and easy to extract, yet very accurate.

Stable and High-Performance Flexible ZnO Thin-Film Transistors by Atomic Layer Deposition.

PubMed

Lin, Yuan-Yu; Hsu, Che-Chen; Tseng, Ming-Hung; Shyue, Jing-Jong; Tsai, Feng-Yu

2015-10-14

Passivation is a challenging issue for the oxide thin-film transistor (TFT) technologies because it requires prolonged high-temperature annealing treatments to remedy defects produced in the process, which greatly limits its manufacturability as well as its compatibility with temperature-sensitive materials such as flexible plastic substrates. This study investigates the defect-formation mechanisms incurred by atomic layer deposition (ALD) passivation processes on ZnO TFTs, based on which we demonstrate for the first time degradation-free passivation of ZnO TFTs by a TiO2/Al2O3 nanolaminated (TAO) film deposited by a low-temperature (110 °C) ALD process. By combining the TAO passivation film with ALD dielectric and channel layers into an integrated low-temperature ALD process, we successfully fabricate flexible ZnO TFTs on plastics. Thanks to the exceptional gas-barrier property of the TAO film (water vapor transmission rate (WVTR)<10(-6) g m(-2) day(-1)) as well as the defect-free nature of the ALD dielectric and ZnO channel layers, the TFTs exhibit excellent device performance with high stability and flexibility: field-effect mobility>20 cm2 V(-1) s(-1), subthreshold swing<0.4 V decade(-1) after extended bias-stressing (>10,000 s), air-storage (>1200 h), and bending (1.3 cm radius for 1000 times).

Fin field effect transistor directionality impacts printing of implantation shapes

NASA Astrophysics Data System (ADS)

Wang, Xiren; Granik, Yuri

2018-01-01

In modern integrated circuit (IC) fabrication processes, the photoresist receives considerable illumination energy that is reflected by underlying topography during optical lithography of implantation layers. Bottom antireflective coating (BARC) is helpful to mitigate the reflection. Often, however, BARC is not used, because its removal is technically challenging, in addition to its relatively high economic cost. Furthermore, the advanced technology nodes, such as 14/10-nm nodes, have introduced fin field effect transistor (FinFET), which makes reflection from nonuniform silicon substrates exceptionally complicated. Therefore, modeling reflection from topography becomes obligatory to accurately predict printing of implantation shapes. Typically, FinFET is always fixed in one direction in realistic designs. However, the same implantation rectangle may be oriented in either horizontal or vertical direction. Then, there are two types of relations between the critical dimension (CD) and FinFET, namely a parallel-to and a perpendicular-to relation. We examine the fin directionality impact on CD. We found that this impact may be considerable in some cases. We use our in-house rigorous optical topography simulator to reveal underlining physical reasons. One of the major causes of the CD differences is that in the parallel orientation, the solid sidewalls of the fins conduct considerable light reflections unlike for the perpendicular orientation. This finding can aid the compact modeling in optical proximity correction of implantation masks.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors: II—Numerical modeling of dc characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

A numerical procedure to calculate the drain-current (ID) vs. gate-voltage (VG) characteristics from numerical solutions of the Poisson equation for organic Thin-Film Transistors (TFTs) is presented. Polaron transport is modeled as two-dimensional charge transport in a semiconductor having free-carrier density of states proportional to the density of molecules and traps with energy equal to the polaron-hopping barrier. The simulated ID-VG curves are proportional to the product of the density of free carriers, calculated as a function of VG, and the intrinsic mobility, assumed to be a constant independent of temperature. The presence of traps in the oxide was also taken into account in the model, which was applied to a TFT made with six monolayers of pentacene grown on an oxide substrate. The polaron-hopping barrier determines the temperature dependence of the simulated ID-VG curves, trapping in the oxide is responsible for current reduction at high bias and the slope of the characteristics near threshold is related to the metal-semiconductor work-function difference. The values of the model parameters yielding the best match between calculations and experiments are consistent with previous experimental results and theoretical predictions. Therefore, this model enables to extract both physical and technological properties of thin-film devices from the temperature-dependent dc characteristics.

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

NASA Technical Reports Server (NTRS)

Bar-Cohen, Avram; Robinson, Franklin L.; Deisenroth, David C.

2018-01-01

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

NASA Astrophysics Data System (ADS)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

PubMed

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

A flexible future for paper-based electronics

NASA Astrophysics Data System (ADS)

Liang, Tongfen; Zou, Xiyue; Mazzeo, Aaron D.

2016-05-01

This paper will review the origins and state of the art in paper-based electronics, suggesting the stage is set for future promising applications. Current interest in paper-based electronics can trace its roots to recent developments in paper-based microfluidics. With a need to improve the reliability and sensitivity of paperbased microfluidics for certain tasks, there were natural efforts to begin embedding sensing electrodes into microfluidic devices. Recognizing the general benefits of paper as an advanced material (e.g., its environmental friendliness, bendable nature, and low cost), efforts in paper-based electronics also began to take a life of their own with demonstrations of transistors, batteries and devices for energy storage, energy harvesting, sensors to improve situational awareness, acoustics, and displays. The state-of-the-art paper-based electronic devices have benefited and will continue to profit from technologies for printing and transferring electronic functionality onto the surfaces of paper-based substrates. Nonetheless, the authors suggest that many future promising applications will go beyond using paper as a carrier/substrate for electronic components to explore tuning of the electrical, mechanical, and chemical properties of the paper itself. With these technical advances, paper-based electronics will move closer to economically viable killer applications.

Technology development of high-quality semiconductor devices using solution-processed crystallization of pentacene

NASA Astrophysics Data System (ADS)

Liu, Hung-Wei

Organic electronic materials and processing techniques have attracted considerable attention for developing organic thin-film transistors (OTFTs), since they may be patterned on flexible substrates which may be bent into a variety of shapes for applications such as displays, smart cards, solar devices and sensors Various fabrication methods for building pentacene-based OTFTs have been demonstrated. Traditional vacuum deposition and vapor deposition methods have been studied for deposition on plastic and paper, but these are unlikely to scale well to large area printing. Researchers have developed methods for processing OTFTs from solution because of the potential for low-cost and large area device manufacturing, such as through inkjet or offset printing. Most methods require the use of precursors which are used to make pentacene soluble, and these methods have typically produced much lower carrier mobility than the best vacuum deposited devices. We have investigated devices built from solution-processed pentacene that is locally crystallized at room temperature on the polymer substrates. Pentacene crystals grown in this manner are highly localized at pre-determined sites, have good crystallinity and show good carrier mobility, making this an attractive method for large area manufacturing of semiconductor devices.

Electronic Disorder in Organic Semiconducting Films Observed with Kelvin Probe Force Microscopy

NASA Astrophysics Data System (ADS)

Hoffman, Benjamin Carl

This work is a study into electronic disorder within organic semiconducting (OSC) films from a scan-probe perspective. Organic electronics are an exciting technology poised for use in next generation devices with unique applications such as transparent displays and ultrathin flexible solar cells. Understanding and mapping electronic disorder in OSC has a high degree of relevance towards recognizing the properties of charge trapping that hinders transport and diminishes device performance. Evidence of surface potential inhomogeneity is identified by using Kelvin probe force microscopy (KPFM) to measure the contact potential difference (CPD) between probe and sample. OSC films are grown via organic molecular beam deposition (OMBD) to create well-ordered crystals with precise control of nominal thickness. Further research methods involve the study of diffraction peaks from grazing-incidence wide-angle x-ray scattering (GIWAXS) for crystallographic analysis as well as use of a probe station for transfer characteristics of fabricated thin film transistors. Initial research into this subject involved thin films of the novel organic molecule 2,8- diflouro-5,11-bis(triethylsilylethynyl)-anthradithiophene (diF-TES-ADT) that were grown on silicon substrates with a native oxide layer and analyzed with GIWAXS and KPFM. The crystallography of the films is that of a uniform (001) orientation. Variations in surface potential in diF-TES-ADT crystallites are observed to be unique from variations in the substrate. Nevertheless, surface potential variations in thick films are influenced by chemical passivation of the substrate and so the source of CPD variations are assigned to be intrinsic defects. Chemical treatment and processing methods control the growth kinetics which are linked to charge traps locally distorting the surface potential in OSC films. To continue the research into identifying charge trapping in ultra-thin films, 1.5 monolayer thick films of alpha-sexithiophene (6T) were grown on silicon substrates with a thick oxide layer to compare the surface potential of the first monolayer with that of the bilayer. The temperature of the substrate during film growth was varied and found to influence the interlayer surface potential contrast. Higher temperature samples have a bilayer with CPD above that of the monolayer, while lower temperature samples have a bilayer with CPD below that of the monolayer. GIWAXS data collected shows that the lower temperature sample has no observed out-of-plane order which we identify as the source of interlayer trapping formed between the first and second monolayers of the 6T films. The final project into the specifics of disorder involves using ultrathin films of 6T in an operational transistor with grounded source-drain electrodes to study the influence of gate bias on surface potential. Using the mean and standard deviation of CPD for a series of gate biases, the trap density of states (DOS) is calculated directly while allowing for the quantification of spatial variations. CPD histograms from the series of images illustrate the screening of deep traps as the transistor is turned on. While in the 'off' regime the images are electrostatic, after transitioning to the 'on' state the images show instability after threshold voltage. This dynamic 'on' state offers a unique view of shallow trap states being filled and then thermally released.

Integration of active devices on smart polymers for neural interfaces

NASA Astrophysics Data System (ADS)

Avendano-Bolivar, Adrian Emmanuel

The increasing ability to ever more precisely identify and measure neural interactions and other phenomena in the central and peripheral nervous systems is revolutionizing our understanding of the human body and brain. To facilitate further understanding, more sophisticated neural devices, perhaps using microelectronics processing, must be fabricated. Materials often used in these neural interfaces, while compatible with these fabrication processes, are not optimized for long-term use in the body and are often orders of magnitude stiffer than the tissue with which they interact. Using the smart polymer substrates described in this work, suitability for processing as well as chronic implantation is demonstrated. We explore how to integrate reliable circuitry onto these flexible, biocompatible substrates that can withstand the aggressive environment of the body. To increase the capabilities of these devices beyond individual channel sensing and stimulation, active electronics must also be included onto our systems. In order to add this functionality to these substrates and explore the limits of these devices, we developed a process to fabricate single organic thin film transistors with mobilities up to 0.4 cm2/Vs and threshold voltages close to 0V. A process for fabricating organic light emitting diodes on flexible substrates is also addressed. We have set a foundation and demonstrated initial feasibility for integrating multiple transistors onto thin-film flexible devices to create new applications, such as matrix addressable functionalized electrodes and organic light emitting diodes. A brief description on how to integrate waveguides for their use in optogenetics is addressed. We have built understanding about device constraints on mechanical, electrical and in vivo reliability and how various conditions affect the electronics' lifetime. We use a bi-layer gate dielectric using an inorganic material such as HfO 2 combined with organic Parylene-c. A study of reliability of widely used Parylene-c encapsulation for in vivo conditions for thin film transistors is presented. These various inquiries, taken in their entirety, facilitate understanding of fundamental problems for biocompatible, chronic electronic device implants in the body, leading to a new set of tools and devices that will help understand complex problems in neuroscience and materials research.

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

PubMed

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Weakly doped InP layers prepared by liquid phase epitaxy using a modulated cooling rate

NASA Astrophysics Data System (ADS)

Krukovskyi, R.; Mykhashchuk, Y.; Kost, Y.; Krukovskyi, S.; Saldan, I.

2017-04-01

Epitaxial structures based on InP are widely used to manufacture a number of devices such as microwave transistors, light-emitting diodes, lasers and Gunn diodes. However, their temporary instability caused by heterogeneity of resistivity along the layer thickness and the influence of various external or internal factors prompts the need for the development of a new reliable technology for their preparation. Weak doping by Yb, Al and Sn together with modulation of the cooling rate applied to prepare InP epitaxial layers is suggested to be adopted within the liquid phase epitaxy (LPE) method. The experimental results confirm the optimized conditions created to get a uniform electron concentration in the active n-InP layer. A sharp profile of electron concentration in the n+-InP(substrate)/n-InP/n+-InP epitaxial structure was observed experimentally at the proposed modulated cooling rate of 0.3 °С-1.5 °С min-1. The proposed technological method can be used to control the electrical and physical properties of InP epitaxial layers to be used in Gunn diodes.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Pulsed direct flame deposition and thermal annealing of transparent amorphous indium zinc oxide films as active layers in field effect transistors.

PubMed

Kilian, Daniel; Polster, Sebastian; Vogeler, Isabell; Jank, Michael P M; Frey, Lothar; Peukert, Wolfgang

2014-08-13

Indium-zinc oxide (IZO) films were deposited via flame spray pyrolysis (FSP) by pulsewise shooting a Si/SiO2 substrate directly into the combustion area of the flame. Based on UV-vis measurements of thin-films deposited on glass substrates, the optimal deposition parameters with respect to low haze values and film thicknesses of around 100 nm were determined. Thermal annealing of the deposited films at temperatures between 300 and 700 °C was carried out and staggered bottom gate thin-film transistors (TFT) were fabricated. The thin films were investigated by scanning electron microscopy, atomic force microscopy, X-ray diffraction, Fourier transformed infrared spectroscopy, and room-temperature photoluminescence measurements. The outcome of these investigations lead to two major requirements in order to implement a working TFT: (i) organic residues from the deposition process need to be removed and (ii) the net free charge carrier concentration has to be minimized by controlling the trap states in the semiconductor. The optimal annealing temperature was 300 °C as both requirements are fulfilled best in this case. This leads to field effect transistors with a low hysteresis, a saturation mobility of μSat = 0.1 cm(2)/(V s), a threshold voltage of Vth = -18.9 V, and an Ion/Ioff ratio on the order of 10(7). Depending on thermal treatment, the defect density changes significantly strongly influencing the transfer characteristics of the device.

Single ZnO nanowire-PZT optothermal field effect transistors.

PubMed

Hsieh, Chun-Yi; Lu, Meng-Lin; Chen, Ju-Ying; Chen, Yung-Ting; Chen, Yang-Fang; Shih, Wan Y; Shih, Wei-Heng

2012-09-07

A new type of pyroelectric field effect transistor based on a composite consisting of single zinc oxide nanowire and lead zirconate titanate (ZnO NW-PZT) has been developed. Under infrared (IR) laser illumination, the transconductance of the ZnO NW can be modulated by optothermal gating. The drain current can be increased or decreased by IR illumination depending on the polarization orientation of the Pb(Zr(0.3)Ti(0.7))O(3) (PZT) substrate. Furthermore, by combining the photocurrent behavior in the UV range and the optothermal gating effect in the IR range, the wide spectrum of response of current by light offers a variety of opportunities for nanoscale optoelectronic devices.

Effect of Zinc Oxide Film Deposition Position on the Characteristics of Zinc Oxide Thin Film Transistors Fabricated by Low-Temperature Magnetron Sputtering

NASA Astrophysics Data System (ADS)

Takechi, Kazushige; Nakata, Mitsuru; Eguchi, Toshimasa; Otsuki, Shigeyoshi; Yamaguchi, Hirotaka; Kaneko, Setsuo

2008-09-01

We report on the effect of zinc oxide (ZnO) film deposition position on the characteristics of ZnO thin-film transistors (TFTs) fabricated by magnetron sputtering with no intentional heating of the substrate. We evaluate the properties of ZnO (channel semiconductor) films deposited at various positions with respect to the target position. We show that the film deposition at a position off-centered from the target results in good TFT characteristics. This might be due to the fact that the off-centered deposition position is effective for suppressing the effect of energetic negative ions in the plasma.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Dual-Input AND Gate From Single-Channel Thin-Film FET

NASA Technical Reports Server (NTRS)

Miranda, F. A.; Pinto, N. J.; Perez, R.; Mueller, C. H.

2008-01-01

A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Polycrystalline silicon ion sensitive field effect transistors

NASA Astrophysics Data System (ADS)

Yan, F.; Estrela, P.; Mo, Y.; Migliorato, P.; Maeda, H.; Inoue, S.; Shimoda, T.

2005-01-01

We report the operation of polycrystalline silicon ion sensitive field effect transistors. These devices can be fabricated on inexpensive disposable substrates such as glass or plastics and are, therefore, promising candidates for low cost single-use intelligent multisensors. In this work we have developed an extended gate structure with a Si3N4 sensing layer. Nearly ideal pH sensitivity (54mV /pH) and stable operation have been achieved. Temperature effects have been characterized. A penicillin sensor has been fabricated by functionalizing the sensing area with penicillinase. The sensitivity to penicillin G is about 10mV/mM, in solutions with concentration lower than the saturation value, which is about 7 mM.

Methodological comparison on OLED and OLET fabrication

NASA Astrophysics Data System (ADS)

Suppiah, Sarveshvaran; Hambali, Nor Azura Malini Ahmad; Wahid, Mohamad Halim Abd; Retnasamy, Vithyacharan; Shahimin, Mukhzeer Mohamad

2018-02-01

The potential of organic semiconductor devices for light generation is demonstrated by the commercialization of display technologies based on organic light emitting diode (OLED). In OLED, organic materials play the role of light emission once the current is passed through. However, OLED do have major drawbacks whereby it suffers from photon loss and exciton quenching. Organic light emitting transistor (OLET) emerged as the new technology to compensate the efficiency and brightness loss encountered in OLED. The structure has combinational capability to switch the electronic signal such as the field effect transistor (FET) as well as light generation. The aim of this study is to methodologically compare and contrast fabrication process and evaluate feasibility of both organic light emitting diode (OLED) and organic light emitting transistor (OLET). The proposed light emitting layer in this study is poly [2-methoxy-5- (2'-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV).