Recent progress in photoactive organic field-effect transistors.

PubMed

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Controlled n-Type Doping of Carbon Nanotube Transistors by an Organorhodium Dimer.

PubMed

Geier, Michael L; Moudgil, Karttikay; Barlow, Stephen; Marder, Seth R; Hersam, Mark C

2016-07-13

Single-walled carbon nanotube (SWCNT) transistors are among the most developed nanoelectronic devices for high-performance computing applications. While p-type SWCNT transistors are easily achieved through adventitious adsorption of atmospheric oxygen, n-type SWCNT transistors require extrinsic doping schemes. Existing n-type doping strategies for SWCNT transistors suffer from one or more issues including environmental instability, limited carrier concentration modulation, undesirable threshold voltage control, and/or poor morphology. In particular, commonly employed benzyl viologen n-type doping layers possess large thicknesses, which preclude top-gate transistor designs that underlie high-density integrated circuit layouts. To overcome these limitations, we report here the controlled n-type doping of SWCNT thin-film transistors with a solution-processed pentamethylrhodocene dimer. The charge transport properties of organorhodium-treated SWCNT thin films show consistent n-type behavior when characterized in both Hall effect and thin-film transistor geometries. Due to the molecular-scale thickness of the organorhodium adlayer, large-area arrays of top-gated, n-type SWCNT transistors are fabricated with high yield. This work will thus facilitate ongoing efforts to realize high-density SWCNT integrated circuits.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries.

PubMed

Lee, Yi-Ying; Hsu, Chih-Yuan; Lin, Ling-Jiun; Chang, Chih-Chun; Cheng, Hsiao-Chun; Yeh, Tsung-Hsien; Hu, Rei-Hsing; Lin, Che; Xie, Zhen; Chen, Bor-Sen

2013-10-27

Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components.According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching.

Systematic design methodology for robust genetic transistors based on I/O specifications via promoter-RBS libraries

PubMed Central

2013-01-01

Background Synthetic genetic transistors are vital for signal amplification and switching in genetic circuits. However, it is still problematic to efficiently select the adequate promoters, Ribosome Binding Sides (RBSs) and inducer concentrations to construct a genetic transistor with the desired linear amplification or switching in the Input/Output (I/O) characteristics for practical applications. Results Three kinds of promoter-RBS libraries, i.e., a constitutive promoter-RBS library, a repressor-regulated promoter-RBS library and an activator-regulated promoter-RBS library, are constructed for systematic genetic circuit design using the identified kinetic strengths of their promoter-RBS components. According to the dynamic model of genetic transistors, a design methodology for genetic transistors via a Genetic Algorithm (GA)-based searching algorithm is developed to search for a set of promoter-RBS components and adequate concentrations of inducers to achieve the prescribed I/O characteristics of a genetic transistor. Furthermore, according to design specifications for different types of genetic transistors, a look-up table is built for genetic transistor design, from which we could easily select an adequate set of promoter-RBS components and adequate concentrations of external inducers for a specific genetic transistor. Conclusion This systematic design method will reduce the time spent using trial-and-error methods in the experimental procedure for a genetic transistor with a desired I/O characteristic. We demonstrate the applicability of our design methodology to genetic transistors that have desirable linear amplification or switching by employing promoter-RBS library searching. PMID:24160305

Stretchable transistors with buckled carbon nanotube films as conducting channels

DOEpatents

Arnold, Michael S; Xu, Feng

2015-03-24

Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.

Electrophoretic and field-effect graphene for all-electrical DNA array technology.

PubMed

Xu, Guangyu; Abbott, Jeffrey; Qin, Ling; Yeung, Kitty Y M; Song, Yi; Yoon, Hosang; Kong, Jing; Ham, Donhee

2014-09-05

Field-effect transistor biomolecular sensors based on low-dimensional nanomaterials boast sensitivity, label-free operation and chip-scale construction. Chemical vapour deposition graphene is especially well suited for multiplexed electronic DNA array applications, since its large two-dimensional morphology readily lends itself to top-down fabrication of transistor arrays. Nonetheless, graphene field-effect transistor DNA sensors have been studied mainly at single-device level. Here we create, from chemical vapour deposition graphene, field-effect transistor arrays with two features representing steps towards multiplexed DNA arrays. First, a robust array yield--seven out of eight transistors--is achieved with a 100-fM sensitivity, on par with optical DNA microarrays and at least 10 times higher than prior chemical vapour deposition graphene transistor DNA sensors. Second, each graphene acts as an electrophoretic electrode for site-specific probe DNA immobilization, and performs subsequent site-specific detection of target DNA as a field-effect transistor. The use of graphene as both electrode and transistor suggests a path towards all-electrical multiplexed graphene DNA arrays.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance vertical organic transistors.

PubMed

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

PubMed Central

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-01-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing. PMID:26349444

Analogy of transistor function with modulating photonic band gap in electromagnetically induced grating

NASA Astrophysics Data System (ADS)

Wang, Zhiguo; Ullah, Zakir; Gao, Mengqin; Zhang, Dan; Zhang, Yiqi; Gao, Hong; Zhang, Yanpeng

2015-09-01

Optical transistor is a device used to amplify and switch optical signals. Many researchers focus on replacing current computer components with optical equivalents, resulting in an optical digital computer system processing binary data. Electronic transistor is the fundamental building block of modern electronic devices. To replace electronic components with optical ones, an equivalent optical transistor is required. Here we compare the behavior of an optical transistor with the reflection from a photonic band gap structure in an electromagnetically induced transparency medium. A control signal is used to modulate the photonic band gap structure. Power variation of the control signal is used to provide an analogy between the reflection behavior caused by modulating the photonic band gap structure and the shifting of Q-point (Operation point) as well as amplification function of optical transistor. By means of the control signal, the switching function of optical transistor has also been realized. Such experimental schemes could have potential applications in making optical diode and optical transistor used in quantum information processing.

Current control circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2005-03-15

Among the embodiments of the present invention is an apparatus that includes a transistor (30), a servo device (40), and a current source (50). The servo device (40) is operable to provide a common base mode of operation of the transistor (30) by maintaining an approximately constant voltage level at the transistor base (32b). The current source (150) is operable to provide a bias current to the transistor (30). A first device (24) provides an input signal to an electrical node (70) positioned between the emitter (32e) of the transistor (30) and the current source (50). A second device (26) receives an output signal from the collector (32c) of the transistor (30).

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dib, E., E-mail: elias.dib@for.unipi.it; Carrillo-Nuñez, H.; Cavassilas, N.

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Triple-mode single-transistor graphene amplifier and its applications.

PubMed

Yang, Xuebei; Liu, Guanxiong; Balandin, Alexander A; Mohanram, Kartik

2010-10-26

We propose and experimentally demonstrate a triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor. The ambipolar nature of electronic transport in graphene transistors leads to increased amplifier functionality as compared to amplifiers built with unipolar semiconductor devices. The ambipolar graphene transistors can be configured as n-type, p-type, or hybrid-type by changing the gate bias. As a result, the single-transistor graphene amplifier can operate in the common-source, common-drain, or frequency multiplication mode, respectively. This in-field controllability of the single-transistor graphene amplifier can be used to realize the modulation necessary for phase shift keying and frequency shift keying, which are widely used in wireless applications. It also offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

PubMed

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Self-protecting transistor oscillator for treating animal tissues

DOEpatents

Doss, James D.

1980-01-01

A transistor oscillator circuit wherein the load current applied to animal tissue treatment electrodes is fed back to the transistor. Removal of load is sensed to automatically remove feedback and stop oscillations. A thermistor on one treatment electrode senses temperature, and by means of a control circuit controls oscillator transistor current.

Development and Experimental Evaluation of an Automated Multi-Media Course on Transistors.

ERIC Educational Resources Information Center

Whitted, J.H., Jr.; And Others

A completely automated multi-media self-study program for teaching a portion of electronic solid-state fundamentals was developed. The subject matter areas included were fundamental theory of transistors, transistor amplifier fundamentals, and simple mathematical analysis of transistors including equivalent circuits, parameters, and characteristic…

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

NASA Astrophysics Data System (ADS)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor behaviour in devices fabricated from chemically reduced graphene oxide. The work provided an important step forward for graphene electronics, which has been hampered by difficulties in scaling up the mechanical exfoliation techniques required to produce the high-quality graphene often needed for functioning devices [8]. In Sweden, researchers have developed a transistor design that they fabricate using standard III-V parallel processing, which also has great promise for scaling up production. Their transistor is based on a vertical array of InAs nanowires, which provide high electron mobility and the possibility of high-speed and low-power operation [9]. Different fabrication techniques and design parameters can influence the properties of transistors. Researchers in Belgium used a new method based on high-vacuum scanning spreading resistance microscopy to study the effect of diameter on carrier profile in nanowire transistors [10]. They then used experimental data and simulations to gain a better understanding of how this influenced the transistor performance. In Japan, Y Ohno and colleagues at Nagoya University have reported how atomic layer deposition of an insulating layer of HfO2 on carbon nanotube field effect transistors can change the carrier from p-type to n-type [11]. Carrier type switching—'ambipolar behaviour'—and hysteresis of carbon nanotube network transistors can make achieving reliable device performance challenging. However studies have also suggested that the hysteretic properties may be exploited in non-volatile memory applications. A collaboration of researchers in Italy and the US demonstrated transistor and memory cell behaviour in a system based on a carbon nanotube network [13]. Their device had relatively fast programming, good endurance and the charge retention was successfully enhanced by limiting exposure to air. Progress in understanding transistor behaviour has inspired other innovations in device applications. Nanowires are notoriously sensitive to gases such as CO, opening opportunities for applications in sensing using one-dimensional nanostructure transistors [12]. The pyroelectric transistor reported in this issue represents an intriguing development for device applications of this versatile and ubiquitous electronics component [3]. As the researchers point out, 'By combining the photocurrent feature and optothermal gating effect, the wide range of response to light covering ultraviolet and infrared radiation can lead to new nanoscale optoelectronic devices that are suitable for remote or wireless applications.' In nanotechnology research and development, often the race is on to achieve reliable device behaviour in the smallest possible systems. But sometimes it is the innovations in the approach used that revolutionize technology in industry. The pyroelectric transistor reported in this issue is a neat example of the ingenious innovations in this field of research. While in research the race is never really over, as this work demonstrates the journey itself remains an inspiration. References [1] Bardeen J and Brattain W H 1948 The transistor, a semi-conductor triode Phys. Rev 74 230-1 [2] Shockley W B, Bardeen J and Brattain W H 1956 The nobel prize in physics www.nobelprize.org/nobel_prizes/physics/laureates/1956/# [3] Hsieh C-Y, Lu M-L, Chen J-Y, Chen Y-T, Chen Y-F, Shih W Y and Shih W-H 2012 Single ZnO nanowire-PZT optothermal field effect transistors Nanotechnology 23 355201 [4] Tans S J, Verschueren A R M and Dekker C 1998 Room-temperature transistor based on a single carbon nanotube Nature 393 49-52 [5] Cui Y, Zhong Z, Wang D, Wang W U and Lieber C M 2003 High performance silicon nanowire field effect transistors Nano Lett. 3 149-52 [6]Stafford C A, Cardamone D M and Mazumdar S 2007 The quantum interference effect transistor Nanotechnology 18 424014 [7] Garnier F, Hajlaoui R, Yassar A and Srivastava P 1994 All-polymer field-effect transistor realized by printing techniques Science 265 1684-6 [8] Joung D, Chunder A, Zhai L and Khondaker S I 2010 High yield fabrication of chemically reduced graphene oxide field effect transistors by dielectrophoresis Nanotechnology 21 165202 [9] Bryllert T, Wernersson L-E, L¨owgren T and Samuelson L 2006 Vertical wrap-gated nanowire transistors Nanotechnology 17 S227-30 [10] Schulze A et al 2011 Observation of diameter dependent carrier distribution in nanowire-based transistors Nanotechnology 22 185701 [11] Moriyama N, Ohno Y, Kitamura T, Kishimoto S and Mizutani T 2010 Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges Nanotechnology 21 165201 [12] Bartolomeo A D, Rinzan M, Boyd A K, Yang Y, Guadagno L, Giubileo F and Barbara P 2010 Electrical properties and memory effects of field-effect transistors from networks of single-and double-walled carbon nanotubes Nanotechnology 21 115204 [13] Liao L et al 2009 Multifunctional CuO nanowire devices: P-type field effect transistors and CO gas sensors Nanotechnology 20 085203

Method and Circuit for Injecting a Precise Amount of Charge onto a Circuit Node

NASA Technical Reports Server (NTRS)

Hancock, Bruce R. (Inventor)

2016-01-01

A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.

A PWM transistor inverter for an ac electric vehicle drive

NASA Technical Reports Server (NTRS)

Slicker, J. M.

1981-01-01

A prototype system consisting of closely integrated motor, inverter, and transaxle has been built in order to demonstrate the feasibility of a three-phase ac transistorized inverter for electric vehicle applications. The microprocessor-controlled inverter employs monolithic power transistors to drive an oil-cooled, three-phase induction traction motor at a peak output power of 30 kW from a 144 V battery pack. Transistor safe switching requirements are discussed, and a circuit is presented for recovering trapped snubber inductor energy at transistor turn-off.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

Graphene-based flexible and stretchable thin film transistors.

PubMed

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

Micro-power dissipation device described

NASA Astrophysics Data System (ADS)

Mao, X.; Zhou, L.; Zhou, J.

1985-11-01

The common-emitter current gain beta of a common two-pole transistor is generally below 250. They are referred to as high-beta or high gain transistors when the beta of such transistors exceeds 300. When the beta of a transistor is higher than 1,000, it is called a super-beta transistor (SBT) or supergain transistor. The micropower dissipation type has the widest applications among the high-beta. Micropower dissipation high-beta means that there is a high gain or a superhigh gain under a microcurrent. The device is widely used in small signal-detection systems and stereo audio equipment because of their characteristics of high gain, low frequency and low noise under small signals.

High-frequency noise characterization of graphene field effect transistors on SiC substrates

NASA Astrophysics Data System (ADS)

Yu, C.; He, Z. Z.; Song, X. B.; Liu, Q. B.; Dun, S. B.; Han, T. T.; Wang, J. J.; Zhou, C. J.; Guo, J. C.; Lv, Y. J.; Cai, S. J.; Feng, Z. H.

2017-07-01

Considering its high carrier mobility and high saturation velocity, a low-noise amplifier is thought of as being the most attractive analogue application of graphene field-effect transistors. The noise performance of graphene field-effect transistors at frequencies in the K-band remains unknown. In this work, the noise parameters of a graphene transistor are measured from 10 to 26 GHz and noise models are built with the data. The extrinsic minimum noise figure for a graphene transistor reached 1.5 dB, and the intrinsic minimum noise figure was as low as 0.8 dB at a frequency of 10 GHz, which were comparable with the results from tests on Si CMOS and started to approach those for GaAs and InP transistors. Considering the short development time, the current results are a significant step forward for graphene transistors and show their application potential in high-frequency electronics.

Electrical coupling of single cardiac rat myocytes to field-effect and bipolar transistors.

PubMed

Kind, Thomas; Issing, Matthias; Arnold, Rüdiger; Müller, Bernt

2002-12-01

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Ultra-high gain diffusion-driven organic transistor.

PubMed

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Ultra-high gain diffusion-driven organic transistor

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-02-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal-semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics.

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

DTIC Science & Technology

2014-06-19

PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Evan R. Kemp, Ctr...United States. AFIT-ENP-T-14-J-39 PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS THESIS Presented to...PROTON DAMAGE EFFECTS ON CARBON NANOTUBE FIELD-EFFECT TRANSISTORS Evan R. Kemp, BS Ctr, USAF Approved: // Signed

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 2

NASA Technical Reports Server (NTRS)

Lee, F. C.; Chen, D. Y.; Jovanic, M.; Hopkins, D. C.

1985-01-01

Test data of switching times characterization of bipolar transistors, of field effect transistor's switching times on-resistance and characterization, comparative data of field effect transistors, and test data of field effect transistor's parallel operation characterization are given. Data is given in the form of graphs.

A steep-slope transistor based on abrupt electronic phase transition

NASA Astrophysics Data System (ADS)

Shukla, Nikhil; Thathachary, Arun V.; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G.; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-01

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (`sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

A steep-slope transistor based on abrupt electronic phase transition.

PubMed

Shukla, Nikhil; Thathachary, Arun V; Agrawal, Ashish; Paik, Hanjong; Aziz, Ahmedullah; Schlom, Darrell G; Gupta, Sumeet Kumar; Engel-Herbert, Roman; Datta, Suman

2015-08-07

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep ('sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Radiation effects in LDD MOS devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woodruff, R.L.; Adams, J.R.

1987-12-01

The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined thatmore » the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10/sup 6/ rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10/sup 6/ rads(Si), and shows promise for achieving 1.0 x 10/sup 7/ rad(Si) total-dose capability.« less

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording

PubMed Central

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-01-01

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development. PMID:28350370

Feasibility Study of Extended-Gate-Type Silicon Nanowire Field-Effect Transistors for Neural Recording.

PubMed

Kang, Hongki; Kim, Jee-Yeon; Choi, Yang-Kyu; Nam, Yoonkey

2017-03-28

In this research, a high performance silicon nanowire field-effect transistor (transconductance as high as 34 µS and sensitivity as 84 nS/mV) is extensively studied and directly compared with planar passive microelectrode arrays for neural recording application. Electrical and electrochemical characteristics are carefully characterized in a very well-controlled manner. We especially focused on the signal amplification capability and intrinsic noise of the transistors. A neural recording system using both silicon nanowire field-effect transistor-based active-type microelectrode array and platinum black microelectrode-based passive-type microelectrode array are implemented and compared. An artificial neural spike signal is supplied as input to both arrays through a buffer solution and recorded simultaneously. Recorded signal intensity by the silicon nanowire transistor was precisely determined by an electrical characteristic of the transistor, transconductance. Signal-to-noise ratio was found to be strongly dependent upon the intrinsic 1/f noise of the silicon nanowire transistor. We found how signal strength is determined and how intrinsic noise of the transistor determines signal-to-noise ratio of the recorded neural signals. This study provides in-depth understanding of the overall neural recording mechanism using silicon nanowire transistors and solid design guideline for further improvement and development.

Copper atomic-scale transistors.

PubMed

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

PubMed

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizingmore » controllable high-performance stable transistors.« less

Copper atomic-scale transistors

PubMed Central

Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors. PMID:28382242

A III-V nanowire channel on silicon for high-performance vertical transistors.

PubMed

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

High voltage power transistor development

NASA Technical Reports Server (NTRS)

Hower, P. L.

1981-01-01

Design considerations, fabrication procedures, and methods of evaluation for high-voltage power-transistor development are discussed. Technique improvements such as controlling the electric field at the surface and perserving lifetimes in the collector region which have advanced the state of the art in high-voltage transistors are discussed. These improvements can be applied directly to the development of 1200 volt, 200 ampere transistors.

Metal Oxide Silicon /MOS/ transistors protected from destructive damage by wire

NASA Technical Reports Server (NTRS)

Deboo, G. J.; Devine, E. J.

1966-01-01

Loop of flexible, small diameter, nickel wire protects metal oxide silicon /MOS/ transistors from a damaging electrostatic potential. The wire is attached to a music-wire spring, slipped over the MOS transistor case, and released so the spring tensions the wire loop around all the transistor leads, shorting them together. This allows handling without danger of damage.

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2011 CFR

2011-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2012 CFR

2012-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2014 CFR

2014-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2013 CFR

2013-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

19 CFR 10.13 - Statutory provision: Subheading 9802.00.80, Harmonized Tariff Schedule of the United States (19 U...

Code of Federal Regulations, 2010 CFR

2010-04-01

... the exemption bears to the full value of the assembled article. Example 1. A transistor radio is assembled abroad from foreign-made components and American-made transistors. Upon importation, the transistor radio is subject to the ad valorem rate of duty applicable to transistor radios upon the value of...

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

DOEpatents

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Enhanced Amplification and Fan-Out Operation in an All-Magnetic Transistor

PubMed Central

Barman, Saswati; Saha, Susmita; Mondal, Sucheta; Kumar, Dheeraj; Barman, Anjan

2016-01-01

Development of all-magnetic transistor with favorable properties is an important step towards a new paradigm of all-magnetic computation. Recently, we showed such possibility in a Magnetic Vortex Transistor (MVT). Here, we demonstrate enhanced amplification in MVT achieved by introducing geometrical asymmetry in a three vortex sequence. The resulting asymmetry in core to core distance in the three vortex sequence led to enhanced amplification of the MVT output. A cascade of antivortices travelling in different trajectories including a nearly elliptical trajectory through the dynamic stray field is found to be responsible for this amplification. This asymmetric vortex transistor is further used for a successful fan-out operation, which gives large and nearly equal gains in two output branches. This large amplification in magnetic vortex gyration in magnetic vortex transistor is proposed to be maintained for a network of vortex transistor. The above observations promote the magnetic vortex transistors to be used in complex circuits and logic operations. PMID:27624662

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

PubMed

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Ultra-high gain diffusion-driven organic transistor

PubMed Central

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

PubMed

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Universal power transistor base drive control unit

DOEpatents

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Universal power transistor base drive control unit

DOEpatents

Gale, A.R.; Gritter, D.J.

1988-06-07

A saturation condition regulator system for a power transistor is disclosed which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition. 2 figs.

Transistor-based filter for inhibiting load noise from entering a power supply

DOEpatents

Taubman, Matthew S

2013-07-02

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

Transistor-based filter for inhibiting load noise from entering a power supply

DOEpatents

Taubman, Matthew S

2015-02-24

A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

Transistor circuit increases range of logarithmic current amplifier

NASA Technical Reports Server (NTRS)

Gilmour, G.

1966-01-01

Circuit increases the range of a logarithmic current amplifier by combining a commercially available amplifier with a silicon epitaxial transistor. A temperature compensating network is provided for the transistor.

Application of the Johnson criteria to graphene transistors

NASA Astrophysics Data System (ADS)

Kelly, M. J.

2013-12-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications.

Assessment of Phospohrene Field Effect Transistors

DTIC Science & Technology

2018-01-28

electronics industry. To this end, transistor test structures would initially be fabricated on phosphorene exfoliated from black phosphorus and, later, on...34Phosphorene FETs-Promising Transistors Based on a few Layers of Phosphorus Atoms," Nanjing Electronic Devices Institute, Nanjing, China, Jul. 2015...OH, Nov. 2015. J.C. M. Hwang, "Phosphorene Transistors-Transient or Lasting Electronics ?" Workshop Frontier Electronics , San Juan, PR, Dec. 2015

Subtractive Plasma-Assisted-Etch Process for Developing High Performance Nanocrystalline Zinc-Oxide Thin-Film-Transistors

DTIC Science & Technology

2015-03-26

THIN - FILM - TRANSISTORS THESIS Thomas M. Donigan, First Lieutenant, USAF AFIT-ENG-MS-15-M-027 DEPARTMENT OF THE AIR FORCE AIR UNIVERSITY AIR...DEVELOPING HIGH PERFORMANCE NANOCRYSTALLINE ZINC-OXIDE THIN - FILM - TRANSISTORS THESIS Presented to the Faculty Department of Electrical and...15-M-027 SUBTRACTIVE PLASMA-ASSISTED-ETCH PROCESS FOR DEVELOPING HIGH PERFORMANCE NANOCRYSTALLINE ZINC-OXIDE THIN - FILM - TRANSISTORS

Oxide Based Transistor for Flexible Displays

DTIC Science & Technology

2014-09-15

thin film transistors (TFTs) for next generation display technologies. A detailed and comprehensive study was carried out to ascertain the process...Box 12211 Research Triangle Park, NC 27709-2211 Thin film transistors , flexible electronics, RF sputtering, Transparent amorphous oxide semiconductors...NC A&T and RTI, International investigated In free GaSnZnO (GSZO) material system, as the active channel in thin film transistors (TFTs) for next

Coaxial inverted geometry transistor having buried emitter

NASA Technical Reports Server (NTRS)

Hruby, R. J.; Cress, S. B.; Dunn, W. R. (Inventor)

1973-01-01

The invention relates to an inverted geometry transistor wherein the emitter is buried within the substrate. The transistor can be fabricated as a part of a monolithic integrated circuit and is particularly suited for use in applications where it is desired to employ low actuating voltages. The transistor may employ the same doping levels in the collector and emitter, so these connections can be reversed.

Transistor Laser Optical NOR Gate for High Speed Optical Logic Processors

DTIC Science & Technology

2017-03-20

proposes an optical bistable latch can be built with two universal photonic NOR gate circuits, which are implemented by the three-port tunneling ... Tunneling Junction Transistor Laser (TJ-TL); Optical NOR Gate. Introduction To fulfill the future national security and intelligence needs in this...two-terminal diode lasers. Three-Port Transistor Laser – an Integration of Quantum-Wells into Heterojunction Bipolar Transistor Different than

Field-effect transistors (2nd revised and enlarged edition)

NASA Astrophysics Data System (ADS)

Bocharov, L. N.

The design, principle of operation, and principal technical characteristics of field-effect transistors produced in the USSR are described. Problems related to the use of field-effect transistors in various radioelectronic devices are examined, and tables of parameters and mean statistical characteristics are presented for the main types of field-effect transistors. Methods for calculating various circuit components are discussed and illustrated by numerical examples.

PRESSURE TRANSDUCER

DOEpatents

Sander, H.H.

1959-10-01

A pressure or mechanical force transducer particularly adaptable to miniature telemetering systems is described. Basically the device consists of a transistor located within a magnetic field adapted to change in response to mechanical force. The conduction characteristics of the transistor in turn vary proportionally with changes in the magnetic flux across the transistor such that the output (either frequency of amplitude) of the transistor circuit is proportional to mechanical force or pressure.

Single-transistor-clocked flip-flop

DOEpatents

Zhao, Peiyi; Darwish, Tarek; Bayoumi, Magdy

2005-08-30

The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Boron nitride housing cools transistors

NASA Technical Reports Server (NTRS)

1965-01-01

Boron nitride ceramic heat sink cools transistors in r-f transmitter and receiver circuits. Heat dissipated by the transistor is conducted by the boron nitride housing to the metal chassis on which it is mounted.

Current sensing circuit

NASA Technical Reports Server (NTRS)

Franke, Ralph J. (Inventor)

1996-01-01

A current sensing circuit is described in which a pair of bipolar transistors are arranged with a pair of field effect transistors such that the field effect transistors absorb most of the supply voltage associated with a load.

Three dimensional-stacked complementary thin-film transistors using n-type Al:ZnO and p-type NiO thin-film transistors.

PubMed

Lee, Ching-Ting; Chen, Chia-Chi; Lee, Hsin-Ying

2018-03-05

The three dimensional inverters were fabricated using novel complementary structure of stacked bottom n-type aluminum-doped zinc oxide (Al:ZnO) thin-film transistor and top p-type nickel oxide (NiO) thin-film transistor. When the inverter operated at the direct voltage (V DD ) of 10 V and the input voltage from 0 V to 10 V, the obtained high performances included the output swing of 9.9 V, the high noise margin of 2.7 V, and the low noise margin of 2.2 V. Furthermore, the high performances of unskenwed inverter were demonstrated by using the novel complementary structure of the stacked n-type Al:ZnO thin-film transistor and p-type nickel oxide (NiO) thin-film transistor.

Tunable organic transistors that use microfluidic source and drain electrodes

NASA Astrophysics Data System (ADS)

Maltezos, George; Nortrup, Robert; Jeon, Seokwoo; Zaumseil, Jana; Rogers, John A.

2003-09-01

This letter describes a type of transistor that uses conducting fluidic source and drain electrodes of mercury which flow on top of a thin film of the organic semiconductor pentacene. Pumping the mercury through suitably designed microchannels changes the width of the transistor channel and, therefore, the electrical characteristics of the device. Measurements on transistors with a range of channel lengths reveal low contact resistances between mercury and pentacene. Data collected before, during, and after pumping the mercury through the microchannels demonstrate reversible and systematic tuning of the devices. This unusual type of organic transistor has the potential to be useful in plastic microfluidic devices that require active elements for pumps, sensors, or other components. It also represents a noninvasive way to build transistor test structures that incorporate certain classes of chemically and mechanically fragile organic semiconductors.

Apparatus and method for recharging a string a avalanche transistors within a pulse generator

DOEpatents

Fulkerson, E. Stephen

2000-01-01

An apparatus and method for recharging a string of avalanche transistors within a pulse generator is disclosed. A plurality of amplification stages are connected in series. Each stage includes an avalanche transistor and a capacitor. A trigger signal, causes the apparatus to generate a very high voltage pulse of a very brief duration which discharges the capacitors. Charge resistors inject current into the string of avalanche transistors at various points, recharging the capacitors. The method of the present invention includes the steps of supplying current to charge resistors from a power supply; using the charge resistors to charge capacitors connected to a set of serially connected avalanche transistors; triggering the avalanche transistors; generating a high-voltage pulse from the charge stored in the capacitors; and recharging the capacitors through the charge resistors.

Smallest Nanoelectronic with Atomic Devices with Precise Structures

NASA Technical Reports Server (NTRS)

Yamada, Toshishige

2000-01-01

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Study on the Hydrogenated ZnO-Based Thin Film Transistors. Part 1

DTIC Science & Technology

2011-04-30

IGZO film on the performance of thin film transistors 5 Chapter 2. Hydrogenation of a- IGZO channel layer in the thin film transistors 12...effect of substrate temperature during the deposition of a- IGZO film on the performance of thin film transistors Introduction The effect of substrate...temperature during depositing IGZO channel layer on the performance of amorphous indium-gallium-zinc oxide (a- IGZO

p-Type Transparent Electronics

DTIC Science & Technology

2003-09-25

thin - film transistors (TTFTs) reported to date in the literature are summarized. 2.2.1 Thin - Film Transistor Structure and Fabrication A TFT ...is incapable of controlling the TFT regardless of gate voltage, as described in Sec. 2.2.3.1. 2.2.4 Transparent Thin - Film Transistors (TTFTs...Transparent thin - film transistors (TTFTs) described in the literature to date are all n-channel devices. Several n-channel TTFTs (n-TTFTs) based on

Theory and Device Modeling for Nano-Structured Transistor Channels

DTIC Science & Technology

2011-06-01

zinc oxide ( ZnO ) thin film transistors ( TFTs ) that contain nanocrystalline grains on the order of ~20nm. The authors of ref. 1 present results...problem in order to determine the threshold voltage. 15. SUBJECT TERMS nano-structured transistor , mesoscopic, zinc oxide , ZnO , field-effect...and R. Neidhard, “Microwave ZnO Thin - Film Transistors ”, IEEE Electron Dev. Lett. 29, 1024 (2008); doi: 10.1109/LED.2008.2001635.

High-Speed, high-power, switching transistor

NASA Technical Reports Server (NTRS)

Carnahan, D.; Ohu, C. K.; Hower, P. L.

1979-01-01

Silicon transistor rate for 200 angstroms at 400 to 600 volts combines switching speed of transistors with ruggedness, power capacity of thyristor. Transistor introduces unique combination of increased power-handling capability, unusally low saturation and switching losses, and submicrosecond switching speeds. Potential applications include high power switching regulators, linear amplifiers, chopper controls for high frequency electrical vehicle drives, VLF transmitters, RF induction heaters, kitchen cooking ranges, and electronic scalpels for medical surgery.

AlGaSb Buffer Layers for Sb-Based Transistors

DTIC Science & Technology

2010-01-01

transistor ( HEMT ), molecular beam epitaxy (MBE), field-effect transistor (FET), buffer layer INTRODUCTION High-electron-mobility transistors ( HEMTs ) with InAs...monolayers/s. The use of thinner buffer layers reduces molecular beam epitaxial growth time and source consumption. The buffer layers also exhibit...source. In addition, some of the flux from an Sb cell in a molecular beam epitaxy (MBE) system will deposit near the mouth of the cell, eventually

Photonic transistor and router using a single quantum-dot-confined spin in a single-sided optical microcavity

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2017-03-01

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic transistor that forms the basis of modern electronics. In sharp contrast to previous all-optical tran-sistors which are all based on optical nonlinearities, here I introduce a novel design for a high-gain and high-speed (up to terahertz) photonic transistor and its counterpart in the quantum limit, i.e., single-photon transistor based on a linear optical effect: giant Faraday rotation induced by a single electronic spin in a single-sided optical microcavity. A single-photon or classical optical pulse as the gate sets the spin state via projective measurement and controls the polarization of a strong light to open/block the photonic channel. Due to the duality as quantum gate for quantum information processing and transistor for optical information processing, this versatile spin-cavity quantum transistor provides a solid-state platform ideal for all-optical networks and quantum networks.

Photonic transistor and router using a single quantum-dot-confined spin in a single-sided optical microcavity

PubMed Central

Hu, C. Y.

2017-01-01

The future Internet is very likely the mixture of all-optical Internet with low power consumption and quantum Internet with absolute security guaranteed by the laws of quantum mechanics. Photons would be used for processing, routing and com-munication of data, and photonic transistor using a weak light to control a strong light is the core component as an optical analogue to the electronic transistor that forms the basis of modern electronics. In sharp contrast to previous all-optical tran-sistors which are all based on optical nonlinearities, here I introduce a novel design for a high-gain and high-speed (up to terahertz) photonic transistor and its counterpart in the quantum limit, i.e., single-photon transistor based on a linear optical effect: giant Faraday rotation induced by a single electronic spin in a single-sided optical microcavity. A single-photon or classical optical pulse as the gate sets the spin state via projective measurement and controls the polarization of a strong light to open/block the photonic channel. Due to the duality as quantum gate for quantum information processing and transistor for optical information processing, this versatile spin-cavity quantum transistor provides a solid-state platform ideal for all-optical networks and quantum networks. PMID:28349960

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, Albert G.; Drummond, Timothy J.; Robertson, Perry J.; Zipperian, Thomas E.

1995-01-01

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.

Complementary junction heterostructure field-effect transistor

DOEpatents

Baca, A.G.; Drummond, T.J.; Robertson, P.J.; Zipperian, T.E.

1995-12-26

A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits. 10 figs.

High-performance carbon nanotube thin-film transistors on flexible paper substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Na; Yun, Ki Nam; Yu, Hyun-Yong

Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.

Npn double heterostructure bipolar transistor with ingaasn base region

DOEpatents

Chang, Ping-Chih; Baca, Albert G.; Li, Nein-Yi; Hou, Hong Q.; Ashby, Carol I. H.

2004-07-20

An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

PubMed

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

TRANSISTOR HIGH VOLTAGE POWER SUPPLY

DOEpatents

Driver, G.E.

1958-07-15

High voltage, direct current power supplies are described for use with battery powered nuclear detection equipment. The particular advantages of the power supply described, are increased efficiency and reduced size and welght brought about by the use of transistors in the circuit. An important feature resides tn the employment of a pair of transistors in an alternatefiring oscillator circuit having a coupling transformer and other circuit components which are used for interconnecting the various electrodes of the transistors.

Base drive circuit

DOEpatents

Lange, A.C.

1995-04-04

An improved base drive circuit having a level shifter for providing bistable input signals to a pair of non-linear delays. The non-linear delays provide gate control to a corresponding pair of field effect transistors through a corresponding pair of buffer components. The non-linear delays provide delayed turn-on for each of the field effect transistors while an associated pair of transistors shunt the non-linear delays during turn-off of the associated field effect transistor. 2 figures.

Organic transistors manufactured using inkjet technology with subfemtoliter accuracy

PubMed Central

Sekitani, Tsuyoshi; Noguchi, Yoshiaki; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2008-01-01

A major obstacle to the development of organic transistors for large-area sensor, display, and circuit applications is the fundamental compromise between manufacturing efficiency, transistor performance, and power consumption. In the past, improving the manufacturing efficiency through the use of printing techniques has inevitably resulted in significantly lower performance and increased power consumption, while attempts to improve performance or reduce power have led to higher process temperatures and increased manufacturing cost. Here, we lift this fundamental limitation by demonstrating subfemtoliter inkjet printing to define metal contacts with single-micrometer resolution on the surface of high-mobility organic semiconductors to create high-performance p-channel and n-channel transistors and low-power complementary circuits. The transistors employ an ultrathin low-temperature gate dielectric based on a self-assembled monolayer that allows transistors and circuits on rigid and flexible substrates to operate with very low voltages. PMID:18362348

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Back bias induced dynamic and steep subthreshold swing in junctionless transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Parihar, Mukta Singh; Kranti, Abhinav, E-mail: akranti@iiti.ac.in

In this work, we analyze back bias induced steep and dynamic subthreshold swing in junctionless double gate transistors operated in the asymmetric mode. This impact ionization induced dynamic subthreshold swing is explained in terms of the ratio between minimum hole concentration and peak electron concentration, and the dynamic change in the location of the conduction channel with applied front gate voltage. The reason for the occurrence of impact ionization at sub-bandgap drain voltages in silicon junctionless transistors is also accounted for. The optimum junctionless transistor operating at a back gate bias of −0.9 V, achieves over 5 orders of change inmore » drain current at a gate overdrive of 200 mV and drain bias of 1 V. These results for junctionless transistors are significantly better than those exhibited by silicon tunnel field effect transistors operating at the same drain bias.« less

I-V Characteristics of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

High-Performance Vertical Organic Electrochemical Transistors.

PubMed

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Failure rates for accelerated acceptance testing of silicon transistors

NASA Technical Reports Server (NTRS)

Toye, C. R.

1968-01-01

Extrapolation tables for the control of silicon transistor product reliability have been compiled. The tables are based on a version of the Arrhenius statistical relation and are intended to be used for low- and medium-power silicon transistors.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Current Source Logic Gate

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor); Prokop, Norman F. (Inventor)

2017-01-01

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Mixed protonic and electronic conductors hybrid oxide synaptic transistors

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Zhu, Li Qiang; Wen, Juan; Xiao, Hui; Liu, Rui

2017-05-01

Mixed ionic and electronic conductor hybrid devices have attracted widespread attention in the field of brain-inspired neuromorphic systems. Here, mixed protonic and electronic conductor (MPEC) hybrid indium-tungsten-oxide (IWO) synaptic transistors gated by nanogranular phosphorosilicate glass (PSG) based electrolytes were obtained. Unique field-configurable proton self-modulation behaviors were observed on the MPEC hybrid transistor with extremely strong interfacial electric-double-layer effects. Temporally coupled synaptic plasticities were demonstrated on the MPEC hybrid IWO synaptic transistor, including depolarization/hyperpolarization, synaptic facilitation and depression, facilitation-stead/depression-stead behaviors, spiking rate dependent plasticity, and high-pass/low-pass synaptic filtering behaviors. MPEC hybrid synaptic transistors may find potential applications in neuron-inspired platforms.

Maskless writing of a flexible nanoscale transistor with Au-contacted carbon nanotube electrodes

NASA Astrophysics Data System (ADS)

Dockendorf, Cedric P. R.; Poulikakos, Dimos; Hwang, Gilgueng; Nelson, Bradley J.; Grigoropoulos, Costas P.

2007-12-01

A flexible polymer field effect transistor with a nanoscale carbon nanotube channel is conceptualized and realized herein. Carbon nanotubes (CNTs) were dispersed on a polyimide substrate and marked in an scanning electron microscope with focused ion beam such that they could be contacted with gold nanoink. The CNTs were divided into two parts forming the source and drain of the transistor. A micropipette writing method was used to contact the carbon nanotube electrodes with gold nanoink and to deposit the poly(3-hexylthiophene) as an active layer. The mobility of the transistors is of the order of 10-5cm/Vs. After fabrication, the flexible transistors can be peeled off the substrate.

High performance n-channel thin-film transistors with an amorphous phase C60 film on plastic substrate

NASA Astrophysics Data System (ADS)

Na, Jong H.; Kitamura, M.; Arakawa, Y.

2007-11-01

We fabricated high mobility, low voltage n-channel transistors on plastic substrates by combining an amorphous phase C60 film and a high dielectric constant gate insulator titanium silicon oxide (TiSiO2). The transistors exhibited high performance with a threshold voltage of 1.13V, an inverse subthreshold swing of 252mV/decade, and a field-effect mobility up to 1cm2/Vs at an operating voltage as low as 5V. The amorphous phase C60 films can be formed at room temperature, implying that this transistor is suitable for corresponding n-channel transistors in flexible organic logic devices.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

Ripple gate drive circuit for fast operation of series connected IGBTs

DOEpatents

Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

2005-09-20

A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

Pentacene Organic Thin-Film Transistors on Flexible Paper and Glass Substrates

DTIC Science & Technology

2014-02-12

FEB 2014 2. REPORT TYPE 3. DATES COVERED 00-00-2014 to 00-00-2014 4. TITLE AND SUBTITLE Pentacene organic thin - film transistors on flexible...Nanotechnology 25 (2014) 094005 (7pp) doi:10.1088/0957-4484/25/9/094005 Pentacene organic thin - film transistors on flexible paper and glass substrates Adam T...organic thin - film transistors (OTFTs) were fabricated on several types of flexible substrate: commercial photo paper, ultra-smooth specialty paper and

Organic field effect transistor with ultra high amplification

NASA Astrophysics Data System (ADS)

Torricelli, Fabrizio

2016-09-01

High-gain transistors are essential for the large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show organic transistors fabricated on plastic foils enabling unipolar amplifiers with ultra-gain. The proposed approach is general and opens up new opportunities for ultra-large signal amplification in organic circuits and sensors.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Large scale electromechanical transistor with application in mass sensing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Leisheng; Li, Lijie, E-mail: L.Li@swansea.ac.uk

Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to bemore » used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.« less

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Dual-mode operation of 2D material-base hot electron transistors

PubMed Central

Lan, Yann-Wen; Torres, Jr., Carlos M.; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R.; Lerner, Mitchell B.; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L.

2016-01-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications. PMID:27581550

Dual-mode operation of 2D material-base hot electron transistors.

PubMed

Lan, Yann-Wen; Torres, Carlos M; Zhu, Xiaodan; Qasem, Hussam; Adleman, James R; Lerner, Mitchell B; Tsai, Shin-Hung; Shi, Yumeng; Li, Lain-Jong; Yeh, Wen-Kuan; Wang, Kang L

2016-09-01

Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive collector-base potential (VCB > 0) as is necessary for the typical unipolar hot-electron transistor behavior. Here we demonstrate a novel functionality, specifically a dual-mode operation, in our 2D material-base hot electron transistors (e.g. with either graphene or MoS2 in the base region) with the application of a negative collector-base potential (VCB < 0). That is, our 2D material-base hot electron transistors can operate in either a hot-electron or a reverse-current dominating mode depending upon the particular polarity of VCB. Furthermore, these devices operate at room temperature and their current gains can be dynamically tuned by varying VCB. We anticipate our multi-functional dual-mode transistors will pave the way towards the realization of novel flexible 2D material-based high-density and low-energy hot-carrier electronic applications.

Unified planar process for fabricating heterojunction bipolar transistors and buried-heterostructure lasers utilizing impurity-induced disordering

NASA Astrophysics Data System (ADS)

Thornton, R. L.; Mosby, W. J.; Chung, H. F.

1988-12-01

We describe results on a novel geometry of heterojunction bipolar transistor that has been realized by impurity-induced disordering. This structure is fabricated by a method that is compatible with techniques for the fabrication of low threshold current buried-heterostructure lasers. We have demonstrated this compatibility by fabricating a hybrid laser/transistor structure that operates as a laser with a threshold current of 6 mA at room temperature, and as a transistor with a current gain of 5.

The total switch time of silicon bipolar transistors with base doping gradients or with germanium gradients in the base

NASA Astrophysics Data System (ADS)

Karlsteen, M.; Willander, M.

1993-11-01

In this paper the total switch time for a transistor in a Direct Coupled Transistor Logic (DCTL) circuit is simulated by using Laplace transformations of the Ebers-Moll equations. The influence of doping gradients and germanium gradients in the base is investigated and their relative importance and their limitations are established. In a well designed bipolar transistor only a minor enhancement of the total switch time is obtained with the use of a doping gradient in the base. However, for bipolar transistors with base thickness over 500 Å, an improperly selected doping profile could be devastating for the total switch time. For a bipolar transistor the improvement of the total switch time due to a linear germanium gradient in the base could be up to about 30% compared with an ordinary silicon bipolar transistor. Still, a too high germanium gradient forces the normal transistor current gain (α N) to grow and the total switch time is thereby increased. Further enhancement could be achieved by the use of a second degree polynomial germanium profile in the base. Also in this case, care must be taken not to enlarge the germanium gradient too much as the total switch time then starts to increase. In all cases the betterment of the base transit time that is introduced by the electric field will not be directly used to reduce the base transit time. Instead the improvement is mostly used to lower the emitter transition charging time. However, the most important parameter to control is the normal transistor current gain (α N) that has to be kept within a narrow range to keep the total switch time low.

Metal nanoparticle film-based room temperature Coulomb transistor.

PubMed

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-07-01

Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity.

PubMed

Li, Jin-Jin; Zhu, Ka-Di

2011-02-04

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

N-Heterocyclic-Carbene-Treated Gold Surfaces in Pentacene Organic Field-Effect Transistors: Improved Stability and Contact at the Interface.

PubMed

Lv, Aifeng; Freitag, Matthias; Chepiga, Kathryn M; Schäfer, Andreas H; Glorius, Frank; Chi, Lifeng

2018-04-16

N-Heterocyclic carbenes (NHCs), which react with the surface of Au electrodes, have been successfully applied in pentacene transistors. With the application of NHCs, the charge-carrier mobility of pentacene transistors increased by five times, while the contact resistance at the pentacene-Au interface was reduced by 85 %. Even after annealing the NHC-Au electrodes at 200 °C for 2 h before pentacene deposition, the charge-carrier mobility of the pentacene transistors did not decrease. The distinguished performance makes NHCs as excellent alternatives to thiols as metal modifiers for the application in organic field-effect transistors (OFETs). © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Voltage controlled spintronic devices for logic applications

DOEpatents

You, Chun-Yeol; Bader, Samuel D.

2001-01-01

A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

Module failure isolation circuit for paralleled inverters. [preventing system failure during power conditioning for spacecraft applications

NASA Technical Reports Server (NTRS)

Nagano, S. (Inventor)

1979-01-01

A module failure isolation circuit is described which senses and averages the collector current of each paralled inverter power transistor and compares the collector current of each power transistor the average collector current of all power transistors to determine when the sensed collector current of a power transistor in any one inverter falls below a predetermined ratio of the average collector current. The module associated with any transistor that fails to maintain a current level above the predetermined radio of the average collector current is then shut off. A separate circuit detects when there is no load, or a light load, to inhibit operation of the isolation circuit during no load or light load conditions.

Specifics of Pulsed Arc Welding Power Supply Performance Based On A Transistor Switch

NASA Astrophysics Data System (ADS)

Krampit, N. Yu; Kust, T. S.; Krampit, M. A.

2016-08-01

Specifics of designing a pulsed arc welding power supply device are presented in the paper. Electronic components for managing large current was analyzed. Strengths and shortcomings of power supply circuits based on thyristor, bipolar transistor and MOSFET are outlined. As a base unit for pulsed arc welding was chosen MOSFET transistor, which is easy to manage. Measures to protect a transistor are given. As for the transistor control device is a microcontroller Arduino which has a low cost and adequate performance of the work. Bead transfer principle is to change the voltage on the arc in the formation of beads on the wire end. Microcontroller controls transistor when the arc voltage reaches the threshold voltage. Thus there is a separation and transfer of beads without splashing. Control strategies tested on a real device and presented. The error in the operation of the device is less than 25 us, it can be used controlling drop transfer at high frequencies (up to 1300 Hz).

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

PubMed

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes.

PubMed

Cao, Xuan; Chen, Haitian; Gu, Xiaofei; Liu, Bilu; Wang, Wenli; Cao, Yu; Wu, Fanqi; Zhou, Chongwu

2014-12-23

Semiconducting single-wall carbon nanotubes are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible electronics. Nonetheless, developing scalable and low-cost approaches for manufacturing fully printed high-performance single-wall carbon nanotube thin-film transistors remains a major challenge. Here we report that screen printing, which is a simple, scalable, and cost-effective technique, can be used to produce both rigid and flexible thin-film transistors using separated single-wall carbon nanotubes. Our fully printed top-gated nanotube thin-film transistors on rigid and flexible substrates exhibit decent performance, with mobility up to 7.67 cm2 V(-1) s(-1), on/off ratio of 10(4)∼10(5), minimal hysteresis, and low operation voltage (<10 V). In addition, outstanding mechanical flexibility of printed nanotube thin-film transistors (bent with radius of curvature down to 3 mm) and driving capability for organic light-emitting diode have been demonstrated. Given the high performance of the fully screen-printed single-wall carbon nanotube thin-film transistors, we believe screen printing stands as a low-cost, scalable, and reliable approach to manufacture high-performance nanotube thin-film transistors for application in display electronics. Moreover, this technique may be used to fabricate thin-film transistors based on other materials for large-area flexible macroelectronics, and low-cost display electronics.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Field effect transistors improve buffer amplifier

NASA Technical Reports Server (NTRS)

1967-01-01

Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.

Silicon switching transistor with high power and low saturation voltage

NASA Technical Reports Server (NTRS)

Stonebraker, E.; Stoneburner, D.; Ferree, H.

1973-01-01

Assembly of two individually encapsulated silicon-chip transistors produces silicon power-transistor that has low electrical resistance and low thermal impedance. Electrical resistance and thermal impedance are low because of short lead lengths, and external contact surfaces are plated to reduce resistance at interfaces.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

PubMed

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Fabrication and high temperature characteristics of ion-implanted GaAs bipolar transistors and ring-oscillators

NASA Technical Reports Server (NTRS)

Doerbeck, F. H.; Yuan, H. T.; Mclevige, W. V.

1981-01-01

Ion implantation techniques that permit the reproducible fabrication of bipolar GaAs integrated circuits are studied. A 15 stage ring oscillator and discrete transistor were characterized between 25 and 400 C. The current gain of the transistor was found to increase slightly with temperature. The diode leakage currents increase with an activation energy of approximately 1 eV and dominate the transistor leakage current 1 sub CEO above 200 C. Present devices fail catastrophically at about 400 C because of Au-metallization.

Charge transport and trapping in organic field effect transistors exposed to polar analytes

NASA Astrophysics Data System (ADS)

Duarte, Davianne; Sharma, Deepak; Cobb, Brian; Dodabalapur, Ananth

2011-03-01

Pentacene based organic thin-film transistors were used to study the effects of polar analytes on charge transport and trapping behavior during vapor sensing. Three sets of devices with differing morphology and mobility (0.001-0.5 cm2/V s) were employed. All devices show enhanced trapping upon exposure to analyte molecules. The organic field effect transistors with different mobilities also provide evidence for morphology dependent partition coefficients. This study helps provide a physical basis for many reports on organic transistor based sensor response.

AlN/GaN heterostructures for normally-off transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Base drive circuit

DOEpatents

Lange, Arnold C.

1995-01-01

An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Development and fabrication of improved power transistor switches

NASA Technical Reports Server (NTRS)

Hower, P. L.; Chu, C. K.

1979-01-01

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

Metal nanoparticle film–based room temperature Coulomb transistor

PubMed Central

Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

2017-01-01

Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

PubMed

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Experimental and numerical investigation of contact-area-limited doping for top-contact pentacene thin-film transistors with Schottky contact.

PubMed

Noda, Kei; Wada, Yasuo; Toyabe, Toru

2015-10-28

Effects of contact-area-limited doping for pentacene thin-film transistors with a bottom-gate, top-contact configuration were investigated. The increase in the drain current and the effective field-effect mobility was achieved by preparing hole-doped layers underneath the gold contact electrodes by coevaporation of pentacene and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ), confirmed by using a thin-film organic transistor advanced simulator (TOTAS) incorporating Schottky contact with a thermionic field emission (TFE) model. Although the simulated electrical characteristics fit the experimental results well only in the linear regime of the transistor operation, the barrier height for hole injection and the gate-voltage-dependent hole mobility in the pentacene transistors were evaluated with the aid of the device simulation. This experimental data analysis with the simulation indicates that the highly-doped semiconducting layers prepared in the contact regions can enhance the charge carrier injection into the active semiconductor layer and concurrent trap filling in the transistor channel, caused by the mitigation of a Schottky energy barrier. This study suggests that both the contact-area-limited doping and the device simulation dealing with Schottky contact are indispensable in designing and developing high-performance organic thin-film transistors.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

OP-AMPS on Flexible Substrates with Printable Materials

DTIC Science & Technology

2011-08-10

Zinc Tin Oxide Thin - Film - Transistor Enhancement...II196, 2010. [3] D. Geng, D. H. Kang, and J. Jang, "High-Performance Amorphous Indium-Gallium- Zinc - Oxide Thin - Film Transistor With a Self-Aligned...B., Dodabalapur, A., “Band transport and mobility edge in amorphous solution-processed zinc tin oxide thin - film transistors ”, Applied

E-Learning System for Design and Construction of Amplifier Using Transistors

ERIC Educational Resources Information Center

Takemura, Atsushi

2014-01-01

This paper proposes a novel e-Learning system for the comprehensive understanding of electronic circuits with transistors. The proposed e-Learning system allows users to learn a wide range of topics, encompassing circuit theories, design, construction, and measurement. Given the fact that the amplifiers with transistors are an integral part of…

Analysis of long-channel nanotube field-effect-transistors (NT FETs)

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Kwak, Dochan (Technical Monitor)

2001-01-01

This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).

Spin-based single-photon transistor, dynamic random access memory, diodes, and routers in semiconductors

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2016-12-01

The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect: giant circular birefringence induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet: a mixture of all-optical Internet with quantum Internet.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

High Accuracy Transistor Compact Model Calibrations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirementsmore » require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.« less

Hafnium transistor design for neural interfacing.

PubMed

Parent, David W; Basham, Eric J

2008-01-01

A design methodology is presented that uses the EKV model and the g(m)/I(D) biasing technique to design hafnium oxide field effect transistors that are suitable for neural recording circuitry. The DC gain of a common source amplifier is correlated to the structural properties of a Field Effect Transistor (FET) and a Metal Insulator Semiconductor (MIS) capacitor. This approach allows a transistor designer to use a design flow that starts with simple and intuitive 1-D equations for gain that can be verified in 1-D MIS capacitor TCAD simulations, before final TCAD process verification of transistor properties. The DC gain of a common source amplifier is optimized by using fast 1-D simulations and using slower, complex 2-D simulations only for verification. The 1-D equations are used to show that the increased dielectric constant of hafnium oxide allows a higher DC gain for a given oxide thickness. An additional benefit is that the MIS capacitor can be employed to test additional performance parameters important to an open gate transistor such as dielectric stability and ionic penetration.

Imperceptible and Ultraflexible p-Type Transistors and Macroelectronics Based on Carbon Nanotubes.

PubMed

Cao, Xuan; Cao, Yu; Zhou, Chongwu

2016-01-26

Flexible thin-film transistors based on semiconducting single-wall carbon nanotubes are promising for flexible digital circuits, artificial skins, radio frequency devices, active-matrix-based displays, and sensors due to the outstanding electrical properties and intrinsic mechanical strength of carbon nanotubes. Nevertheless, previous research effort only led to nanotube thin-film transistors with the smallest bending radius down to 1 mm. In this paper, we have realized the full potential of carbon nanotubes by making ultraflexible and imperceptible p-type transistors and circuits with a bending radius down to 40 μm. In addition, the resulted transistors show mobility up to 12.04 cm(2) V(-1) S(-1), high on-off ratio (∼10(6)), ultralight weight (<3 g/m(2)), and good mechanical robustness (accommodating severe crumpling and 67% compressive strain). Furthermore, the nanotube circuits can operate properly with 33% compressive strain. On the basis of the aforementioned features, our ultraflexible p-type nanotube transistors and circuits have great potential to work as indispensable components for ultraflexible complementary electronics.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Top-Contact Self-Aligned Printing for High-Performance Carbon Nanotube Thin-Film Transistors with Sub-Micron Channel Length.

PubMed

Cao, Xuan; Wu, Fanqi; Lau, Christian; Liu, Yihang; Liu, Qingzhou; Zhou, Chongwu

2017-02-28

Semiconducting single-wall carbon nanotubes are ideal semiconductors for printed thin-film transistors due to their excellent electrical performance and intrinsic printability with solution-based deposition. However, limited by resolution and registration accuracy of current printing techniques, previously reported fully printed nanotube transistors had rather long channel lengths (>20 μm) and consequently low current-drive capabilities (<0.2 μA/μm). Here we report fully inkjet printed nanotube transistors with dramatically enhanced on-state current density of ∼4.5 μA/μm by downscaling the devices to a sub-micron channel length with top-contact self-aligned printing and employing high-capacitance ion gel as the gate dielectric. Also, the printed transistors exhibited a high on/off ratio of ∼10 5 , low-voltage operation, and good mobility of ∼15.03 cm 2 V -1 s -1 . These advantageous features of our printed transistors are very promising for future high-definition printed displays and sensing systems, low-power consumer electronics, and large-scale integration of printed electronics.

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

NASA Technical Reports Server (NTRS)

Mclyman, W. T. (Inventor)

1981-01-01

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

High-mobility field-effect transistor based on crystalline ZnSnO3 thin films

NASA Astrophysics Data System (ADS)

Minato, Hiroya; Fujiwara, Kohei; Tsukazaki, Atsushi

2018-05-01

We propose crystalline ZnSnO3 as a new channel material for field-effect transistors. By molecular-beam epitaxy on LiNbO3(0001) substrates, we synthesized films of ZnSnO3, which crystallizes in the LiNbO3-type polar structure. Field-effect transistors on ZnSnO3 exhibit n-type operation with field-effect mobility of as high as 45 cm2V-1s-1 at room temperature. Systematic examination of the transistor operation for channels with different Zn/Sn compositional ratios revealed that the observed high-mobility reflects the nature of stoichiometric ZnSnO3 phase. Moreover, we found an indication of coupling of transistor characteristics with intrinsic spontaneous polarization in ZnSnO3, potentially leading to a distinct type of polarization-induced conduction.

High-frequency output characteristics of AlGaAs/GaAs heterojunction bipolar transistors for large-signal applications

NASA Astrophysics Data System (ADS)

Chen, J.; Gao, G. B.; Ünlü, M. S.; Morkoç, H.

1991-11-01

High-frequency ic- vce output characteristics of bipolar transistors, derived from calculated device cutoff frequencies, are reported. The generation of high-frequency output characteristics from device design specifications represents a novel bridge between microwave circuit design and device design: the microwave performance of simulated device structures can be analyzed, or tailored transistor device structures can be designed to fit specific circuit applications. The details of our compact transistor model are presented, highlighting the high-current base-widening (Kirk) effect. The derivation of the output characteristics from the modeled cutoff frequencies are then presented, and the computed characteristics of an AlGaAs/GaAs heterojunction bipolar transistor operating at 10 GHz are analyzed. Applying the derived output characteristics to microwave circuit design, we examine large-signal class A and class B amplification.

Fabrication of eco-friendly PNP transistor using RF magnetron sputtering

NASA Astrophysics Data System (ADS)

Kumar, B. Santhosh; Harinee, N.; Purvaja, K.; Shanker, N. Praveen; Manikandan, M.; Aparnadevi, N.; Mukilraj, T.; Venkateswaran, C.

2018-05-01

An effort has been made to fabricate a thin film transistor using eco-friendly oxide semiconductor materials. Oxide semiconductor materials are cost - effective, thermally and chemically stable with high electron/hole mobility. Copper (II) oxide is a p-type semiconductor and zinc oxide is an n-type semiconductor. A pnp thin film transistor was fabricated using RF magnetron sputtering. The films deposited have been subjected to structural characterization using AFM. I-V characterization of the fabricated device, Ag/CuO/ZnO/CuO/Ag, confirms transistor behaviour. The mechanism of electron/hole transport of the device is discussed below.

Design and Analysis of Reconfigurable Analog System

DTIC Science & Technology

2011-02-01

the number of the bits of the sub-ADC, the range of V is smaller than the full-scale input range by a factor of -L. If it is desired that Vin and Vst ...Transistor M1, M9, and M8 are off. Transistor M3 turns on which turns on transistor M7. As a result Vst is connected to V2. Since V2 was charged to Vdd when...Vutb), it disconnects the other output voltage ( Vst ) from the lower transistors (M2). A regenerative action helps both V0st and Vtb to reach their final

Application of Transistors in Textiles: Monitoring Water Transportation Behaviour in Fibrous Assemblies

NASA Astrophysics Data System (ADS)

Chatterjee, Arobindo; Singh, Pratibha; Ghosh, Subrata

2017-06-01

Simple semiconductor device has been used for amplifying the analog signals, obtained with the change in electrical resistance in fibrous assembly and converting these amplified copies of signals to digital signals. This paper deals with the application of transistors as amplifier, as well as switch. Different circuit configurations using transistors have been tried for sensing and reciprocating the real time data on suitable display device. It is found that transistors configured as common-emitter amplifiers can precisely sense the liquid at the surface of fibrous assembly at different levels with respect to time.

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

PubMed

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Influence of polymer dielectrics on C60-based field-effect transistors

NASA Astrophysics Data System (ADS)

Zhou, Jianlin; Zhang, Fujia; Lan, Lifeng; Wen, Shangsheng; Peng, Junbiao

2007-12-01

Fullerene C60 organic field-effect transistors (OFETs) have been fabricated based on two different polymer dielectric materials, poly(methylmethacrylate) (PMMA) and cross-linkable poly(4-vinylphenol). The large grain size of C60 film and small number of traps at the interface of PMMA /C60 were obtained with high electron mobility of 0.66cm2/Vs in the PMMA transistor. The result suggests that the C60 semiconductor cooperating with polymer dielectric is a promising application in the fabrication of n-type organic transistors because of low threshold voltage and high electron mobility.

N Channel JFET Based Digital Logic Gate Structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J (Inventor)

2013-01-01

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

DTIC Science & Technology

2016-03-01

Fabrication with 0.09-µm High-Electron-Mobility Transistors (HEMTs) Using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC) by John E Penn...for Fabrication with 0.09-µm High-Electron-Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide by John E Penn...µm High-Electron-Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c

A 10kW series resonant converter design, transistor characterization, and base-drive optimization

NASA Technical Reports Server (NTRS)

Robson, R.; Hancock, D.

1981-01-01

Transistors are characterized for use as switches in resonant circuit applications. A base drive circuit to provide the optimal base drive to these transistors under resonant circuit conditions is developed and then used in the design, fabrication and testing of a breadboard, spaceborne type 10 kW series resonant converter.

PULSE COUNTER

DOEpatents

Trumbo, D.E.

1959-02-10

A transistorized pulse-counting circuit adapted for use with nuclear radiation detecting detecting devices to provide a small, light weight portable counter is reported. The small size and low power requirements of the transistor are of particular value in this instance. The circuit provides an adjustable count scale with a single transistor which is triggered by the accumulated charge on a storage capacitor.

Multi-Resolution Imaging of Electron Dynamics in Nanostructure Interfaces

DTIC Science & Technology

2010-07-27

metallic carbon nanotubes from semiconducting ones. In pentacene transistors, we used scanning photocurrent microscopy to study spatially resolved...photoelectric response of pentacene thin films, which showed that point contacts formed near the hole injection points limit the overall performance of the...photothermal current microscopy, carbon nanotube transistor, pentacene transistor, contact resistance, hole injection 16. SECURITY CLASSIFICATION OF

Method for double-sided processing of thin film transistors

DOEpatents

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

65nm OPC and design optimization by using simple electrical transistor simulation

NASA Astrophysics Data System (ADS)

Trouiller, Yorick; Devoivre, Thierry; Belledent, Jerome; Foussadier, Franck; Borjon, Amandine; Patterson, Kyle; Lucas, Kevin; Couderc, Christophe; Sundermann, Frank; Urbani, Jean-Christophe; Baron, Stanislas; Rody, Yves; Chapon, Jean-Damien; Arnaud, Franck; Entradas, Jorge

2005-05-01

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples: -design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. -Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

Design of a Multi-Level/Analog Ferroelectric Memory Device

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2006-01-01

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Direct observation of single-charge-detection capability of nanowire field-effect transistors.

PubMed

Salfi, J; Savelyev, I G; Blumin, M; Nair, S V; Ruda, H E

2010-10-01

A single localized charge can quench the luminescence of a semiconductor nanowire, but relatively little is known about the effect of single charges on the conductance of the nanowire. In one-dimensional nanostructures embedded in a material with a low dielectric permittivity, the Coulomb interaction and excitonic binding energy are much larger than the corresponding values when embedded in a material with the same dielectric permittivity. The stronger Coulomb interaction is also predicted to limit the carrier mobility in nanowires. Here, we experimentally isolate and study the effect of individual localized electrons on carrier transport in InAs nanowire field-effect transistors, and extract the equivalent charge sensitivity. In the low carrier density regime, the electrostatic potential produced by one electron can create an insulating weak link in an otherwise conducting nanowire field-effect transistor, modulating its conductance by as much as 4,200% at 31 K. The equivalent charge sensitivity, 4 × 10(-5) e Hz(-1/2) at 25 K and 6 × 10(-5) e Hz(-1/2) at 198 K, is orders of magnitude better than conventional field-effect transistors and nanoelectromechanical systems, and is just a factor of 20-30 away from the record sensitivity for state-of-the-art single-electron transistors operating below 4 K (ref. 8). This work demonstrates the feasibility of nanowire-based single-electron memories and illustrates a physical process of potential relevance for high performance chemical sensors. The charge-state-detection capability we demonstrate also makes the nanowire field-effect transistor a promising host system for impurities (which may be introduced intentionally or unintentionally) with potentially long spin lifetimes, because such transistors offer more sensitive spin-to-charge conversion readout than schemes based on conventional field-effect transistors.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Erofeev, E. V., E-mail: erofeev@micran.ru; Fedin, I. V.; Kutkov, I. V.

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping levelmore » makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.« less

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer

PubMed Central

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-01-01

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm2/Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 105. Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles. PMID:27876893

Highly Bendable In-Ga-ZnO Thin Film Transistors by Using a Thermally Stable Organic Dielectric Layer.

PubMed

Kumaresan, Yogeenth; Pak, Yusin; Lim, Namsoo; Kim, Yonghun; Park, Min-Ji; Yoon, Sung-Min; Youn, Hyoc-Min; Lee, Heon; Lee, Byoung Hun; Jung, Gun Young

2016-11-23

Flexible In-Ga-ZnO (IGZO) thin film transistor (TFT) on a polyimide substrate is produced by employing a thermally stable SA7 organic material as the multi-functional barrier and dielectric layers. The IGZO channel layer was sputtered at Ar:O 2 gas flow rate of 100:1 sccm and the fabricated TFT exhibited excellent transistor performances with a mobility of 15.67 cm 2 /Vs, a threshold voltage of 6.4 V and an on/off current ratio of 4.5 × 10 5 . Further, high mechanical stability was achieved by the use of organic/inorganic stacking of dielectric and channel layers. Thus, the IGZO transistor endured unprecedented bending strain up to 3.33% at a bending radius of 1.5 mm with no significant degradation in transistor performances along with a superior reliability up to 1000 cycles.

Low voltage to high voltage level shifter and related methods

NASA Technical Reports Server (NTRS)

Mentze, Erik J. (Inventor); Buck, Kevin M. (Inventor); Hess, Herbert L. (Inventor); Cox, David F. (Inventor)

2006-01-01

A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

High transconductance organic electrochemical transistors

NASA Astrophysics Data System (ADS)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

Tunneling modulation of a quantum-well transistor laser

NASA Astrophysics Data System (ADS)

Feng, M.; Qiu, J.; Wang, C. Y.; Holonyak, N.

2016-11-01

Different than the Bardeen and Brattain transistor (1947) with the current gain depending on the ratio of the base carrier spontaneous recombination lifetime to the emitter-collector transit time, the Feng and Holonyak transistor laser current gain depends upon the base electron-hole (e-h) stimulated recombination, the base dielectric relaxation transport, and the collector stimulated tunneling. For the n-p-n transistor laser tunneling operation, the electron-hole pairs are generated at the collector junction under the influence of intra-cavity photon-assisted tunneling, with electrons drifting to the collector and holes drifting to the base. The excess charge in the base lowers the emitter junction energy barrier, allowing emitter electron injection into the base and satisfying charge neutrality via base dielectric relaxation transport (˜femtoseconds). The excess electrons near the collector junction undergo stimulated recombination at the base quantum-well or transport to the collector, thus supporting tunneling current amplification and optical modulation of the transistor laser.

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

Modeling of high composition AlGaN channel high electron mobility transistors with large threshold voltage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bajaj, Sanyam, E-mail: bajaj.10@osu.edu; Hung, Ting-Hsiang; Akyol, Fatih

2014-12-29

We report on the potential of high electron mobility transistors (HEMTs) consisting of high composition AlGaN channel and barrier layers for power switching applications. Detailed two-dimensional (2D) simulations show that threshold voltages in excess of 3 V can be achieved through the use of AlGaN channel layers. We also calculate the 2D electron gas mobility in AlGaN channel HEMTs and evaluate their power figures of merit as a function of device operating temperature and Al mole fraction in the channel. Our models show that power switching transistors with AlGaN channels would have comparable on-resistance to GaN-channel based transistors for the samemore » operation voltage. The modeling in this paper shows the potential of high composition AlGaN as a channel material for future high threshold enhancement mode transistors.« less

Increasing the dynamic range of CMOS photodiode imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor)

2007-01-01

A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

High-performance radio frequency transistors based on diameter-separated semiconducting carbon nanotubes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Yu; Che, Yuchi; Zhou, Chongwu, E-mail: chongwuz@usc.edu

In this paper, we report the high-performance radio-frequency transistors based on the single-walled semiconducting carbon nanotubes with a refined average diameter of ∼1.6 nm. These diameter-separated carbon nanotube transistors show excellent transconductance of 55 μS/μm and desirable drain current saturation with an output resistance of ∼100 KΩ μm. An exceptional radio-frequency performance is also achieved with current gain and power gain cut-off frequencies of 23 GHz and 20 GHz (extrinsic) and 65 GHz and 35 GHz (intrinsic), respectively. These radio-frequency metrics are among the highest reported for the carbon nanotube thin-film transistors. This study provides demonstration of radio frequency transistors based on carbon nanotubes with tailoredmore » diameter distributions, which will guide the future application of carbon nanotubes in radio-frequency electronics.« less

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

Vertical organic transistors.

PubMed

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

Liquid crystals for organic transistors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Hanna, Jun-ichi; Iino, Hiroaki

2016-09-01

Liquid crystals are a new type of organic semiconductors exhibiting molecular orientation in self-organizing manner, and have high potential for device applications. In fact, various device applications have been proposed so far, including photosensors, solar cells, light emitting diodes, field effect transistors, and so on.. However, device performance in those fabricated with liquid crystals is less than those of devices fabricated with conventional materials in spite of unique features of liquid crystals. Here we discuss how we can utilize the liquid crystallinity in organic transistors and how we can overcome conventional non-liquid crystalline organic transistor materials. Then, we demonstrate high performance organic transistors fabricated with a smectic E liquid crystal of Ph-BTBT-10, which show high mobility of over 10cm2/Vs and high thermal durability of over 200oC in OFETs fabricated with its spin-coated polycrystalline thin films.

Aqueous gating of van der Waals materials on bilayer nanopaper.

PubMed

Bao, Wenzhong; Fang, Zhiqiang; Wan, Jiayu; Dai, Jiaqi; Zhu, Hongli; Han, Xiaogang; Yang, Xiaofeng; Preston, Colin; Hu, Liangbing

2014-10-28

In this work, we report transistors made of van der Waals materials on a mesoporous paper with a smooth nanoscale surface. The aqueous transistor has a novel planar structure with source, drain, and gate electrodes on the same surface of the paper, while the mesoporous paper is used as an electrolyte reservoir. These transistors are enabled by an all-cellulose paper with nanofibrillated cellulose (NFC) on the top surface that leads to an excellent surface smoothness, while the rest of the microsized cellulose fibers can absorb electrolyte effectively. Based on two-dimensional van der Waals materials, including MoS2 and graphene, we demonstrate high-performance transistors with a large on-off ratio and low subthreshold swing. Such planar transistors with absorbed electrolyte gating can be used as sensors integrated with other components to form paper microfluidic systems. This study is significant for future paper-based electronics and biosensors.

Light programmable organic transistor memory device based on hybrid dielectric

NASA Astrophysics Data System (ADS)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Dramatic switching behavior in suspended MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Chen, Huawei; Li, Jingyu; Chen, Xiaozhang; Zhang, David; Zhou, Peng

2018-02-01

When integrating MoS2 flakes into scaling-down transistors, the short-channel effect, which is severe in silicon technology below 5-nanometer, can be avoided effectively. MoS2 transistors not only exhibit a high on/off ratio but also demonstrate a rapid switching speed. According to the theoretical calculation, the thermionic limit subthreshold slope (SS) of the ideal device could reach 60 mV/dec. However, due to the confinement of defects from substrates or contamination during the process, the SS deteriorates to more than 300 mV/dec, causing serious power consumption. In this work, we optimize the SS through structure design of MoS2 transistors. The suspended transistors exhibit a high on/off ratio of 107 and a minimum SS of 63 mV/dec with an ultralow standby power at room temperature. This study demonstrates the promising potential of structure design for electronic devices with ultralow-power switching behaviors.

Carrier mobility in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Xu, Yong; Benwadih, Mohamed; Gwoziecki, Romain; Coppard, Romain; Minari, Takeo; Liu, Chuan; Tsukagoshi, Kazuhito; Chroboczek, Jan; Balestra, Francis; Ghibaudo, Gerard

2011-11-01

A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors.

Thermal transistor utilizing gas-liquid transition.

PubMed

Komatsu, Teruhisa S; Ito, Nobuyasu

2011-01-01

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

NASA Astrophysics Data System (ADS)

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J.; Janes, David B.

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including `see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In2O3 and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with ~82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics.

PubMed

Ju, Sanghyun; Facchetti, Antonio; Xuan, Yi; Liu, Jun; Ishikawa, Fumiaki; Ye, Peide; Zhou, Chongwu; Marks, Tobin J; Janes, David B

2007-06-01

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.

High transconductance organic electrochemical transistors

PubMed Central

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

High-frequency self-aligned graphene transistors with transferred gate stacks.

PubMed

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-07-17

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra-high-frequency circuits.

1 μm-thickness ultra-flexible and high electrode-density surface electromyogram measurement sheet with 2 V organic transistors for prosthetic hand control.

PubMed

Fuketa, Hiroshi; Yoshioka, Kazuaki; Shinozuka, Yasuhiro; Ishida, Koichi; Yokota, Tomoyuki; Matsuhisa, Naoji; Inoue, Yusuke; Sekino, Masaki; Sekitani, Tsuyoshi; Takamiya, Makoto; Someya, Takao; Sakurai, Takayasu

2014-12-01

A 64-channel surface electromyogram (EMG) measurement sheet (SEMS) with 2 V organic transistors on a 1 μm-thick ultra-flexible polyethylene naphthalate (PEN) film is developed for prosthetic hand control. The surface EMG electrodes must satisfy the following three requirements; high mechanical flexibility, high electrode density and high signal integrity. To achieve high electrode density and high signal integrity, a distributed and shared amplifier (DSA) architecture is proposed, which enables an in-situ amplification of the myoelectric signal with a fourfold increase in EMG electrode density. In addition, a post-fabrication select-and-connect (SAC) method is proposed to cope with the large mismatch of organic transistors. The proposed SAC method reduces the area and the power overhead by 96% and 98.2%, respectively, compared with the use of conventional parallel transistors to reduce the transistor mismatch by a factor of 10.

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

PubMed

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Controlling charge current through a DNA based molecular transistor

NASA Astrophysics Data System (ADS)

Behnia, S.; Fathizadeh, S.; Ziaei, J.

2017-01-01

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I-V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive.

Modeling of short channel MOS transistors

NASA Technical Reports Server (NTRS)

Lin, H. C.; Kokalis, D. P.; Bandy, W. R.

1976-01-01

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Correlation and squeezing for optical transistor and intensity for router applications in Pr3+:YSO.

PubMed

Khan, Ghulam Abbas; Li, Changbiao; Raza, Faizan; Ahmed, Noor; Mahesar, Abdul Rasheed; Ahmed, Irfan; Zhang, Yanpeng

2017-06-14

We realized an optical transistor and router utilizing multi-order fluorescence and spontaneous parametric four-wave mixing. Specifically, the optical routing action was derived from the results of splitting in the intensity signal due to a dressing effect, whereas the transistor as a switch and amplifier was realized by a switching correlation and squeezing via a nonlinear phase. A substantial enhancement of the optical contrast was observed for switching applications using correlation and squeezing contrary to the intensity signal. Moreover, the controlling parameters were also configured to devise a control mechanism for the optical transistor and router.

High-speed low-power photonic transistor devices based on optically-controlled gain or absorption to affect optical interference.

PubMed

Huang, Yingyan; Ho, Seng-Tiong

2008-10-13

We show that a photonic transistor device can be realized via the manipulation of optical interference by optically controlled gain or absorption in novel ways, resulting in efficient transistor signal gain and switching action. Exemplary devices illustrate two complementary device types with high operating speed, microm size, microW switching power, and switching gain. They can act in tandem to provide a wide variety of operations including wavelength conversion, pulse regeneration, and logical operations. These devices could have a Transistor Figure-of-Merits >10(5) times higher than current chi((3)) approaches and are highly attractive.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

A gallium phosphide high-temperature bipolar junction transistor

NASA Technical Reports Server (NTRS)

Zipperian, T. E.; Dawson, L. R.; Chaffin, R. J.

1981-01-01

Preliminary results are reported on the development of a high temperature (350 C) gallium phosphide bipolar junction transistor (BJT) for geothermal and other energy applications. This four-layer p(+)n(-)pp(+) structure was formed by liquid phase epitaxy using a supercooling technique to insure uniform nucleation of the thin layers. Magnesium was used as the p-type dopant to avoid excessive out-diffusion into the lightly doped base. By appropriate choice of electrodes, the device may also be driven as an n-channel junction field-effect transistor. The initial design suffers from a series resistance problem which limits the transistor's usefulness at high temperatures.

VOLTAGE REGULATOR

DOEpatents

Von Eschen, R.L.; Scheele, P.F.

1962-04-24

A transistorized voltage regulator which provides very close voitage regulation up to about 180 deg F is described. A diode in the positive line provides a constant voltage drop from the input to a regulating transistor emitter. An amplifier is coupled to the positive line through a resistor and is connected between a difference circuit and the regulating transistor base which is negative due to the difference in voltage drop across thc diode and the resistor so that a change in the regulator output causes the amplifier to increase or decrease the base voltage and current and incrcase or decrease the transistor impedance to return the regulator output to normal. (AEC)

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2014-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Three-terminal graphene single-electron transistor fabricated using feedback-controlled electroburning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Puczkarski, Paweł; Gehring, Pascal, E-mail: pascal.gehring@materials.ox.ac.uk; Lau, Chit S.

2015-09-28

We report room-temperature Coulomb blockade in a single layer graphene three-terminal single-electron transistor fabricated using feedback-controlled electroburning. The small separation between the side gate electrode and the graphene quantum dot results in a gate coupling up to 3 times larger compared to the value found for the back gate electrode. This allows for an effective tuning between the conductive and Coulomb blocked state using a small side gate voltage of about 1 V. The technique can potentially be used in the future to fabricate all-graphene based room temperature single-electron transistors or three terminal single molecule transistors with enhanced gate coupling.

Measuring bi-directional current through a field-effect transistor by virtue of drain-to-source voltage measurement

DOEpatents

Turner, Steven Richard

2006-12-26

A method and apparatus for measuring current, and particularly bi-directional current, in a field-effect transistor (FET) using drain-to-source voltage measurements. The drain-to-source voltage of the FET is measured and amplified. This signal is then compensated for variations in the temperature of the FET, which affects the impedance of the FET when it is switched on. The output is a signal representative of the direction of the flow of current through the field-effect transistor and the level of the current through the field-effect transistor. Preferably, the measurement only occurs when the FET is switched on.

Pass-transistor very large scale integration

NASA Technical Reports Server (NTRS)

Maki, Gary K. (Inventor); Bhatia, Prakash R. (Inventor)

2004-01-01

Logic elements are provided that permit reductions in layout size and avoidance of hazards. Such logic elements may be included in libraries of logic cells. A logical function to be implemented by the logic element is decomposed about logical variables to identify factors corresponding to combinations of the logical variables and their complements. A pass transistor network is provided for implementing the pass network function in accordance with this decomposition. The pass transistor network includes ordered arrangements of pass transistors that correspond to the combinations of variables and complements resulting from the logical decomposition. The logic elements may act as selection circuits and be integrated with memory and buffer elements.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

The resonant body transistor.

PubMed

Weinstein, Dana; Bhave, Sunil A

2010-04-14

This paper introduces the resonant body transistor (RBT), a silicon-based dielectrically transduced nanoelectromechanical (NEM) resonator embedding a sense transistor directly into the resonator body. Combining the benefits of FET sensing with the frequency scaling capabilities and high quality factors (Q) of internal dielectrically transduced bar resonators, the resonant body transistor achieves >10 GHz frequencies and can be integrated into a standard CMOS process for on-chip clock generation, high-Q microwave circuits, fundamental quantum-state preparation and observation, and high-sensitivity measurements. An 11.7 GHz bulk-mode RBT is demonstrated with a quality factor Q of 1830, marking the highest frequency acoustic resonance measured to date on a silicon wafer.

Method for Providing Semiconductors Having Self-Aligned Ion Implant

NASA Technical Reports Server (NTRS)

Neudeck, Philip G. (Inventor)

2011-01-01

A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.

Acoustic transistor: Amplification and switch of sound by sound

NASA Astrophysics Data System (ADS)

Liang, Bin; Kan, Wei-wei; Zou, Xin-ye; Yin, Lei-lei; Cheng, Jian-chun

2014-08-01

We designed an acoustic transistor to manipulate sound in a manner similar to the manipulation of electric current by its electrical counterpart. The acoustic transistor is a three-terminal device with the essential ability to use a small monochromatic acoustic signal to control a much larger output signal within a broad frequency range. The output and controlling signals have the same frequency, suggesting the possibility of cascading the structure to amplify an acoustic signal. Capable of amplifying and switching sound by sound, acoustic transistors have various potential applications and may open the way to the design of conceptual devices such as acoustic logic gates.

Demonstration and properties of a planar heterojunction bipolar transistor with lateral current flow

NASA Astrophysics Data System (ADS)

Thornton, Robert L.; Mosby, William J.; Chung, Harlan F.

1989-10-01

The authors present fabrication techniques and device performance for a novel transistor structure, the lateral heterojunction bipolar transistor. The lateral heterojunctions are formed by impurity-induced disordering of a GaAs base layer sandwiched between two AlGaAs layers. These transistor structures exhibit current gains of 14 for base widths of 0.74 micron. Transistor action in this device occurs parallel to the surface of the device structure. The active base region of the structure is completely submerged, resulting in a reduction of surface recombination as a mechanism for gain reduction in the device. Impurity-induced disordering is used to widen the bandgap of the alloy in the emitter and collector, resulting in an improvement of the emitter injection efficiency. Since the device is based entirely on a surface diffusion process, the device is completely planar and has no steps involving etching of the III-V alloy material. These advantages lead this device to be considered as a candidate for optoelectronic integration applications. The transistor device functions as a buried heterostructure laser, with a threshold current as low as 6 mA for a 1.4-micron stripe.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

PubMed Central

Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C.; Ma, Zhenqiang

2016-01-01

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics. PMID:27795570

Radio Frequency Transistors Using Aligned Semiconducting Carbon Nanotubes with Current-Gain Cutoff Frequency and Maximum Oscillation Frequency Simultaneously Greater than 70 GHz.

PubMed

Cao, Yu; Brady, Gerald J; Gui, Hui; Rutherglen, Chris; Arnold, Michael S; Zhou, Chongwu

2016-07-26

In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding direct current (DC) performance with on-current density of 350 μA/μm, transconductance as high as 310 μS/μm, and superior current saturation with normalized output resistance greater than 100 kΩ·μm. These transistors create a record as carbon nanotube RF transistors that demonstrate both the current-gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) greater than 70 GHz. Furthermore, these transistors exhibit good linearity performance with 1 dB gain compression point (P1dB) of 14 dBm and input third-order intercept point (IIP3) of 22 dBm. Our study advances state-of-the-art of carbon nanotube RF electronics, which have the potential to be made flexible and may find broad applications for signal amplification, wireless communication, and wearable/flexible electronics.

The woven fiber organic electrochemical transistors based on polypyrrole nanowires/reduced graphene oxide composites for glucose sensing.

PubMed

Wang, Yuedan; Qing, Xing; Zhou, Quan; Zhang, Yang; Liu, Qiongzhen; Liu, Ke; Wang, Wenwen; Li, Mufang; Lu, Zhentan; Chen, Yuanli; Wang, Dong

2017-09-15

Novel woven fiber organic electrochemical transistors based on polypyrrole (PPy) nanowires and reduced graphene oxide (rGO) have been prepared. SEM revealed that the introduction of rGO nanosheets could induce the growth and increase the amount of PPy nanowires. Moreover, it could enhance the electrical performance of fiber transistors. The hybrid transistors showed high on/off ratio of 10 2 , fast switch speed, and long cycling stability. The glucose sensors based on the fiber organic electrochemical transistors have also been investigated, which exhibited outstanding sensitivity, as high as 0.773 NCR/decade, with a response time as fast as 0.5s, a linear range of 1nM to 5μM, a low detection concentration as well as good repeatability. In addition, the glucose could be selectively detected in the presence of ascorbic acid and uric acid interferences. The reliability of the proposed glucose sensor was evaluated in real samples of rabbit blood. All the results indicate that the novel fiber transistors pave the way for portable and wearable electronics devices, which have a promising future for healthcare and biological applications. Copyright © 2017 Elsevier B.V. All rights reserved.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

PubMed

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

PubMed

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

1.55 Micrometer Sub-Micron Finger, Interdigitated MSM Photodetector Arrays with Low Dark Current

DTIC Science & Technology

2010-02-02

pf a- IGZO TFTs. IV. RF Characteristics of Room Temperature Deposited Indium Zinc Oxide Thin - Film Transistors Depletion-mode indium zinc...III. High Performance Indium Gallium Zinc Oxide Thin Film Transistors Fabricated On Polyethylene Terephthalate Substrates High-performance...amorphous (a-) InGaZnO-based thin film transistors (TFTs) were fabricated on flexible polyethylene terephthalate (PET) substrates coated with indium

Power Supply Fault Tolerant Reliability Study

DTIC Science & Technology

1991-04-01

easier to design than for equivalent bipolar transistors. MCDONNELL DOUGLAS ELECTRONICS SYSTEMS COMPANY 9. Base circuitry should be designed to drive...SWITCHING REGULATORS (Ref. 28), SWITCHING AND LINEAR POWER SUPPLY DESIGN (Ref. 25) 6. Sequence the turn-off/turn-on logic in an orderly and controllable ...for equivalent bipolar transistors. MCDONNELL DOUGLAS ELECTRONICS SYSTEMS COMPANY 8. Base circuitry should be designed to drive the transistor into

PH-Sensitive WO(3)-Based Microelectrochemical Transistors.

DTIC Science & Technology

1986-09-22

electronics, microelectrochemistry, microelectrodes, surface L- modification, molecuale based transistors, polyaniline , poly-3-methylthiophene Chemical...polymer, as in the cases of polypyrrole,8 poly(N-methyl pyrrole), 8b polyaniline , 9 or poly(3-methylthiophene),1 0 the polymer- % .4_. connected...Polypyrrole, 8 polyaniline , 9 and poly(3-methylthiophene) I0 are similar in that they are conducting when oxidized, and transistors based on these materials

Ultraviolet Electrically Injected Light Sources With Epitaxial ZnO-Based Heterojunctions

DTIC Science & Technology

2007-08-01

ohmic contacts to ZnO , UV photoconductors, and thin film transistors . The integration of ferroelectric oxide thin films with ZnO was also investigated... transistors . The integration of ferroelectric oxide thin films with ZnO was also investigated, as a potential means of locally inverting ZnO to p-type, and to...low contact resistivity ......................... 8 ZnO Thin Film Transistors

Spin Coherence in Semiconductor Nanostructures

DTIC Science & Technology

2006-12-10

to the collector under the operating conditions of the unipolar spin transistor. This work has appeared in Journal of Applied Physics. (Left...Original proposal of the homojunction unipolar spin transistor, showing the dropping of the barrier for carriers to leak from base to collector ...Right) new proposal of the heterostructure unipolar spin transistor, showing that the barrier for majority carriers to leak from base to collector is

Rail-to-rail differential input amplification stage with main and surrogate differential pairs

DOEpatents

Britton, Jr., Charles Lanier; Smith, Stephen Fulton

2007-03-06

An operational amplifier input stage provides a symmetrical rail-to-rail input common-mode voltage without turning off either pair of complementary differential input transistors. Secondary, or surrogate, transistor pairs assume the function of the complementary differential transistors. The circuit also maintains essentially constant transconductance, constant slew rate, and constant signal-path supply current as it provides rail-to-rail operation.

Low Temperature Photoluminescence (PL) from High Electron Mobility Transistors (HEMTs)

DTIC Science & Technology

2015-03-01

Photoluminescence Form InxAl1-xN Films Deposited by Plasma-Assisted Molecular Beam Epitaxy ,” Submitted to Applied Physics Letters, July 2014. 8 LIST OF...TECHNICAL REPORT RDMR-WD-14-55 LOW TEMPERATURE PHOTOLUMINESCENCE (PL) FROM HIGH ELECTRON MOBILITY TRANSISTORS ( HEMTS ...Mobility Transistors ( HEMTs ) 5. FUNDING NUMBERS 6. AUTHOR(S) Adam T. Roberts and Henry O. Everitt 7. PERFORMING ORGANIZATION NAME(S

Automatic load sharing in inverter modules

NASA Technical Reports Server (NTRS)

Nagano, S.

1979-01-01

Active feedback loads transistor equally with little power loss. Circuit is suitable for balancing modular inverters in spacecraft, computer power supplies, solar-electric power generators, and electric vehicles. Current-balancing circuit senses differences between collector current for power transistor and average value of load currents for all power transistors. Principle is effective not only in fixed duty-cycle inverters but also in converters operating at variable duty cycles.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

Osteoblastic cells trigger gate currents on nanocrystalline diamond transistor.

PubMed

Izak, Tibor; Krátká, Marie; Kromka, Alexander; Rezek, Bohuslav

2015-05-01

We show the influence of osteoblastic SAOS-2 cells on the transfer characteristics of nanocrystalline diamond solution-gated field-effect transistors (SGFET) prepared on glass substrates. Channels of these fully transparent SGFETs are realized by hydrogen termination of undoped diamond film. After cell cultivation, the transistors exhibit about 100× increased leakage currents (up to 10nA). During and after the cell delamination, the transistors return to original gate currents. We propose a mechanism where this triggering effect is attributed to ions released from adhered cells, which depends on the cell adhesion morphology, and could be used for cell culture monitoring. Copyright © 2015 Elsevier B.V. All rights reserved.

Effect of temperature on the characteristics of silicon nanowire transistor.

PubMed

Hashim, Yasir; Sidek, Othman

2012-10-01

This paper presents the temperature characteristics of silicon nanowire transistors (SiNWTs) and examines the effect of temperature on transfer characteristics, threshold voltage, I(ON)/I(OFF) ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The (MuGFET) simulation tool was used to investigate the temperature characteristics of a transistor. The findings reveal the negative effect of higher working temperature on the use of SiNWTs in electronic circuits, such as digital circuits and amplifiers circuits, because of the lower I(ON)/I(OFF) ratio, higher DIBL, and higher SS at higher temperature. Moreover, the ON state is the optimum condition for using a transistor as a temperature nano-sensor.

Equivalent input spectrum and drain current spectrum for 1/ƒ noise in short channel MOS transistors

NASA Astrophysics Data System (ADS)

Gentil, P.; Mounib, A.

1981-05-01

Flicker noise in MOS transistors can be evaluated by measuring the spectrum SID of the drain current fluctuation or the spectrum Sve of an equivalent gate fluctuation. We show here that experimental variations of {S I D}/{Sve} are in good agreement with gm2 by considering a model of the transconductance gm which takes into account the variations of the channel carriers mobility with the surface electric field. The model agrees with the experimental results obtained on short channel MOS transistors which exhibit large variations of mobility with the gate voltage. The validity of physical interpretations of noise data on MOS transistors is examined.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

PubMed

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

A random access memory immune to single event upset using a T-Resistor

DOEpatents

Ochoa, A. Jr.

1987-10-28

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

2014-04-01

In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

Paired-pulse facilitation achieved in protonic/electronic hybrid indium gallium zinc oxide synaptic transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Li Qiang, E-mail: guoliqiang@ujs.edu.cn; Ding, Jian Ning; Huang, Yu Kai

2015-08-15

Neuromorphic devices with paired pulse facilitation emulating that of biological synapses are the key to develop artificial neural networks. Here, phosphorus-doped nanogranular SiO{sub 2} electrolyte is used as gate dielectric for protonic/electronic hybrid indium gallium zinc oxide (IGZO) synaptic transistor. In such synaptic transistors, protons within the SiO{sub 2} electrolyte are deemed as neurotransmitters of biological synapses. Paired-pulse facilitation (PPF) behaviors for the analogous information were mimicked. The temperature dependent PPF behaviors were also investigated systematically. The results indicate that the protonic/electronic hybrid IGZO synaptic transistors would be promising candidates for inorganic synapses in artificial neural network applications.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ning; Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Hui Liu, Yang

2015-02-16

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.

2014-08-18

With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

Random access memory immune to single event upset using a T-resistor

DOEpatents

Ochoa, Jr., Agustin

1989-01-01

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Silicon Field Effect Transistors as Dual-Use Sensor-Heater Hybrids

PubMed Central

Reddy, Bobby; Elibol, Oguz H.; Nair, Pradeep R.; Dorvel, Brian R.; Butler, Felice; Ahsan, Zahab; Bergstrom, Donald E.; Alam, Muhammad A.; Bashir, Rashid

2011-01-01

We demonstrate the temperature mediated applications of a previously proposed novel localized dielectric heating method on the surface of dual purpose silicon field effect transistor (FET) sensor-heaters and perform modeling and characterization of the underlying mechanisms. The FETs are first shown to operate as electrical sensors via sensitivity to changes in pH in ionic fluids. The same devices are then demonstrated as highly localized heaters via investigation of experimental heating profiles and comparison to simulation results. These results offer further insight into the heating mechanism and help determine the spatial resolution of the technique. Two important biosensor platform applications spanning different temperature ranges are then demonstrated: a localized heat-mediated DNA exchange reaction and a method for dense selective functionalization of probe molecules via the heat catalyzed complete desorption and reattachment of chemical functionalization to the transistor surfaces. Our results show that the use of silicon transistors can be extended beyond electrical switching and field-effect sensing to performing localized temperature controlled chemical reactions on the transistor itself. PMID:21214189

Influence of pre-annealing of printed silver electrodes on ultrafast laser ablation of short thin-film transistor channels on flexible substrates

NASA Astrophysics Data System (ADS)

Wiig, M. S.; You, C. C.; Brox-Nilsen, C.; Foss, S. E.

2018-02-01

The cutoff frequency and current from an organic thin-film transistor (OTFT) are strongly dependent on the length and to some extent on the uniformity of the transistor channel. Reducing the channel length can improve the OTFT performance with the increase in the current and frequency. Picosecond laser ablation of the printed Ag electrodes, compatible with roll-to-roll fabrication, has been investigated. The ablation threshold was found to be similar for the laser wavelengths tested: 515 nm and 1030 nm. Short transistor channels could be opened both after light annealing at 70 °C and after annealing at 140 °C. The channels in the lightly cured films had a significantly less scale formation, which is critical for avoiding shunts in the device. By moving from bottom electrodes fully defined by printing to the bottom electrodes where the transistor channel is opened by the laser, the channel length could be reduced from 40 μm to less than 5 μm.

Development and fabrication of an augmented power transistor

NASA Technical Reports Server (NTRS)

Geisler, M. J.; Hill, F. E.; Ostop, J. A.

1983-01-01

The development of device design and processing techniques for the fabrication of an augmented power transistor capable of fast switching and high voltage power conversion is discussed. The major device goals sustaining voltages in the range of 800 to 1000 V at 80 A and 50 A, respectively, at a gain of 14. The transistor switching rise and fall times were both to have been less than 0.5 microseconds. The development of a passivating glass technique to shield the device high voltage junction from moisture and ionic contaminants is discussed as well as the development of an isolated package that separates the thermal and electrical interfaces. A new method was found to alloy the transistors to the molybdenum disc at a relatively low temperature. The measured electrical performance compares well with the predicted optimum design specified in the original proposed design. A 40 mm diameter transistor was fabricated with seven times the emitter area of the earlier 23 mm diameter device.

Microcrystalline silicon thin-film transistors for large area electronic applications

NASA Astrophysics Data System (ADS)

Chan, Kah-Yoong; Bunte, Eerke; Knipp, Dietmar; Stiebig, Helmut

2007-11-01

Thin-film transistors (TFTs) based on microcrystalline silicon (µc-Si:H) exhibit high charge carrier mobilities exceeding 35 cm2 V-1 s-1. The devices are fabricated by plasma-enhanced chemical vapor deposition at substrate temperatures below 200 °C. The fabrication process of the µc-Si:H TFTs is similar to the low temperature fabrication of amorphous silicon TFTs. The electrical characteristics of the µc-Si:H-based transistors will be presented. As the device charge carrier mobility of short channel TFTs is limited by the contacts, the influence of the drain and source contacts on the device parameters including the device charge carrier mobility and the device threshold voltage will be discussed. The experimental data will be described by a modified standard transistor model which accounts for the contact effects. Furthermore, the transmission line method was used to extract the device parameters including the contact resistance. The modified standard transistor model and the transmission line method will be compared in terms of the extracted device parameters and contact resistances.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Faber, Hendrik; Anthopoulos, Thomas D., E-mail: t.anthopoulos@imperial.ac.uk

2015-03-02

Indium oxide (In{sub 2}O{sub 3}) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm{sup 2}V{sup −1}s{sup −1} and 16 cm{sup 2}V{sup −1}s{sup −1} for coplanar and staggered architectures, respectively. Integration of In{sub 2}O{sub 3} transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (≤250 °C) of In{sub 2}O{sub 3} also allowed transistor fabrication on free-standing 50 μm-thick polyimide foils. The resulting flexible In{sub 2}O{sub 3} transistors exhibit good characteristics and remain fully functional even whenmore » bent to tensile radii of 4 mm.« less

A 10-kW series resonant converter design, transistor characterization, and base-drive optimization

NASA Technical Reports Server (NTRS)

Robson, R. R.; Hancock, D. J.

1982-01-01

The development, components, and performance of a transistor-based 10 kW series resonant converter for use in resonant circuits in space applications is described. The transistors serve to switch on the converter current, which has a half-sinusoid waveform when the transistor is in saturation. The goal of the program was to handle an input-output voltage range of 230-270 Vdc, an output voltage range of 200-500 Vdc, and a current limit range of 0-20 A. Testing procedures for the D60T and D7ST transistors are outlined and base drive waveforms are presented. The total device dissipation was minimized and found to be independent of the regenerative feedback ratio at lower current levels. Dissipation was set at within 10% and rise times were found to be acceptable. The finished unit displayed a 91% efficiency at full power levels of 500 V and 20 A and 93.7% at 500 V and 10 A.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Intrinsically stretchable and transparent thin-film transistors based on printable silver nanowires, carbon nanotubes and an elastomeric dielectric

PubMed Central

Liang, Jiajie; Li, Lu; Chen, Dustin; Hajagos, Tibor; Ren, Zhi; Chou, Shu-Yu; Hu, Wei; Pei, Qibing

2015-01-01

Thin-film field-effect transistor is a fundamental component behind various mordern electronics. The development of stretchable electronics poses fundamental challenges in developing new electronic materials for stretchable thin-film transistors that are mechanically compliant and solution processable. Here we report the fabrication of transparent thin-film transistors that behave like an elastomer film. The entire fabrication is carried out by solution-based techniques, and the resulting devices exhibit a mobility of ∼30 cm2 V−1 s−1, on/off ratio of 103–104, switching current >100 μA, transconductance >50 μS and relative low operating voltages. The devices can be stretched by up to 50% strain and subjected to 500 cycles of repeated stretching to 20% strain without significant loss in electrical property. The thin-film transistors are also used to drive organic light-emitting diodes. The approach and results represent an important progress toward the development of stretchable active-matrix displays. PMID:26173436

Transport spectroscopy of coupled donors in silicon nano-transistors

PubMed Central

Moraru, Daniel; Samanta, Arup; Anh, Le The; Mizuno, Takeshi; Mizuta, Hiroshi; Tabe, Michiharu

2014-01-01

The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed: dopant-atom-based transistors. So far, most studies report transport through dopants randomly located in the channel. However, for practical applications, it is critical to control the location of the donors with simple techniques. Here, we fabricate silicon transistors with selectively nanoscale-doped channels using nano-lithography and thermal-diffusion doping processes. Coupled phosphorus donors form a quantum dot with the ground state split into a number of levels practically equal to the number of coupled donors, when the number of donors is small. Tunneling-transport spectroscopy reveals fine features which can be correlated with the different numbers of donors inside the quantum dot, as also suggested by first-principles simulation results. PMID:25164032

Thickness-dependent electron mobility of single and few-layer MoS{sub 2} thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Ji Heon; Kim, Tae Ho; Lee, Hyunjea

We investigated the dependence of electron mobility on the thickness of MoS{sub 2} nanosheets by fabricating bottom-gate single and few-layer MoS{sub 2} thin-film transistors with SiO{sub 2} gate dielectrics and Au electrodes. All the fabricated MoS{sub 2} transistors showed on/off-current ratio of ∼10{sup 7} and saturated output characteristics without high-k capping layers. As the MoS{sub 2} thickness increased from 1 to 6 layers, the field-effect mobility of the fabricated MoS{sub 2} transistors increased from ∼10 to ∼18 cm{sup 2}V{sup −1}s{sup −1}. The increased subthreshold swing of the fabricated transistors with MoS{sub 2} thickness suggests that the increase of MoS{sub 2}more » mobility with thickness may be related to the dependence of the contact resistance and the dielectric constant of MoS{sub 2} layer on its thickness.« less

Light-Stimulated Synaptic Devices Utilizing Interfacial Effect of Organic Field-Effect Transistors.

PubMed

Dai, Shilei; Wu, Xiaohan; Liu, Dapeng; Chu, Yingli; Wang, Kai; Yang, Ben; Huang, Jia

2018-06-14

Synaptic transistors stimulated by light waves or photons may offer advantages to the devices, such as wide bandwidth, ultrafast signal transmission, and robustness. However, previously reported light-stimulated synaptic devices generally require special photoelectric properties from the semiconductors and sophisticated device's architectures. In this work, a simple and effective strategy for fabricating light-stimulated synaptic transistors is provided by utilizing interface charge trapping effect of organic field-effect transistors (OFETs). Significantly, our devices exhibited highly synapselike behaviors, such as excitatory postsynaptic current (EPSC) and pair-pulse facilitation (PPF), and presented memory and learning ability. The EPSC decay, PPF curves, and forgetting behavior can be well expressed by mathematical equations for synaptic devices, indicating that interfacial charge trapping effect of OFETs can be utilized as a reliable strategy to realize organic light-stimulated synapses. Therefore, this work provides a simple and effective strategy for fabricating light-stimulated synaptic transistors with both memory and learning ability, which enlightens a new direction for developing neuromorphic devices.

High-frequency self-aligned graphene transistors with transferred gate stacks

PubMed Central

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Sub-10 nm Gate Length Graphene Transistors: Operating at Terahertz Frequencies with Current Saturation

PubMed Central

Zheng, Jiaxin; Wang, Lu; Quhe, Ruge; Liu, Qihang; Li, Hong; Yu, Dapeng; Mei, Wai-Ning; Shi, Junjie; Gao, Zhengxiang; Lu, Jing

2013-01-01

Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (fT) of graphene transistor generally increases with the reduced gate length (Lgate) till Lgate = 40 nm, and the maximum measured fT has reached 300 GHz. Using ab initio quantum transport simulation, we reveal for the first time that fT of a graphene transistor still increases with the reduced Lgate when Lgate scales down to a few nm and reaches astonishing a few tens of THz. We observe a clear drain current saturation when a band gap is opened in graphene, with the maximum intrinsic voltage gain increased by a factor of 20. Our simulation strongly suggests it is possible to design a graphene transistor with an extraordinary high fT and drain current saturation by continuously shortening Lgate and opening a band gap. PMID:23419782

PH Sensitive WO3-Based Microelectrochemical Transistors.

DTIC Science & Technology

1986-09-22

molecular electronics, microelectrochemistr microelectrodes, sur ace modtfication, molecule-based transistors, .... " polyaniline , poly-3-methylthiophene...polypyrrole,8 poly(N-methyl pyrrole),8b polyaniline , 9 or poly(3-methylthiophene),1 0 the polymer- ’-p2 ’ -p " ; , Q ’ , : ’ ’ ’ ... , , ’ i connected...VD. Polypyrrole, 8 polyaniline , 9 and poly(3-methylthiophene)1 0 are similar in that they are conducting when oxidized, and transistors based on these

Planar-Processed Polymer Transistors.

PubMed

Xu, Yong; Sun, Huabin; Shin, Eul-Yong; Lin, Yen-Fu; Li, Wenwu; Noh, Yong-Young

2016-10-01

Planar-processed polymer transistors are proposed where the effective charge injection and the split unipolar charge transport are all on the top surface of the polymer film, showing ideal device characteristics with unparalleled performance. This technique provides a great solution to the problem of fabrication limitations, the ambiguous operating principle, and the performance improvements in practical applications of conjugated-polymer transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

S-MMICs: Sub-mm-Wave Transistors and Integrated Circuits

DTIC Science & Technology

2008-09-01

Research Lab BAA DAAD19-03-R-0017 Research area 2.35: RF devices—Dr. Alfred Hung Submitted by: Mark Rodwell, Department of Electrical and Computer ...MOTIVATION / APPLICATION 3 TECHNOLOGY STATUS 4 TRANSISTOR SCALING LAWS 5 256 NM GENERATION 6 HBT POWER AMPLIFIER DEVELOPMENT 7 DRY-ETCHED EMITTER...TECHNOLOGY: 256 NM GENERATION 9 SCALED EPITAXY 11 CONCLUSIONS 12 20081103013 Executive Summary Transistor and power amplifier IC technology was

Sub-parts per million NO2 chemi-transistor sensors based on composite porous silicon/gold nanostructures prepared by metal-assisted etching.

PubMed

Sainato, Michela; Strambini, Lucanos Marsilio; Rella, Simona; Mazzotta, Elisabetta; Barillaro, Giuseppe

2015-04-08

Surface doping of nano/mesostructured materials with metal nanoparticles to promote and optimize chemi-transistor sensing performance represents the most advanced research trend in the field of solid-state chemical sensing. In spite of the promising results emerging from metal-doping of a number of nanostructured semiconductors, its applicability to silicon-based chemi-transistor sensors has been hindered so far by the difficulties in integrating the composite metal-silicon nanostructures using the complementary metal-oxide-semiconductor (CMOS) technology. Here we propose a facile and effective top-down method for the high-yield fabrication of chemi-transistor sensors making use of composite porous silicon/gold nanostructures (cSiAuNs) acting as sensing gate. In particular, we investigate the integration of cSiAuNs synthesized by metal-assisted etching (MAE), using gold nanoparticles (NPs) as catalyst, in solid-state junction-field-effect transistors (JFETs), aimed at the detection of NO2 down to 100 parts per billion (ppb). The chemi-transistor sensors, namely cSiAuJFETs, are CMOS compatible, operate at room temperature, and are reliable, sensitive, and fully recoverable for the detection of NO2 at concentrations between 100 and 500 ppb, up to 48 h of continuous operation.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

PubMed Central

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Low-frequency 1/f noise in MoS{sub 2} transistors: Relative contributions of the channel and contacts

DOE Office of Scientific and Technical Information (OSTI.GOV)

Renteria, J.; Jiang, C.; Samnakay, R.

2014-04-14

We report on the results of the low-frequency (1/f, where f is frequency) noise measurements in MoS{sub 2} field-effect transistors revealing the relative contributions of the MoS{sub 2} channel and Ti/Au contacts to the overall noise level. The investigation of the 1/f noise was performed for both as fabricated and aged transistors. It was established that the McWhorter model of the carrier number fluctuations describes well the 1/f noise in MoS{sub 2} transistors, in contrast to what is observed in graphene devices. The trap densities extracted from the 1/f noise data for MoS{sub 2} transistors, are 2 × 10{sup 19} eV{sup −1}cm{sup −3}more » and 2.5 × 10{sup 20} eV{sup −1}cm{sup −3} for the as fabricated and aged devices, respectively. It was found that the increase in the noise level of the aged MoS{sub 2} transistors is due to the channel rather than the contact degradation. The obtained results are important for the proposed electronic applications of MoS{sub 2} and other van der Waals materials.« less

Fabrication of amorphous InGaZnO thin-film transistor-driven flexible thermal and pressure sensors

NASA Astrophysics Data System (ADS)

Park, Ick-Joon; Jeong, Chan-Yong; Cho, In-Tak; Lee, Jong-Ho; Cho, Eou-Sik; Kwon, Sang Jik; Kim, Bosul; Cheong, Woo-Seok; Song, Sang-Hun; Kwon, Hyuck-In

2012-10-01

In this work, we present the results concerning the use of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) as a driving transistor of the flexible thermal and pressure sensors which are applicable to artificial skin systems. Although the a-IGZO TFT has been attracting much attention as a driving transistor of the next-generation flat panel displays, no study has been performed about the application of this new device to the driving transistor of the flexible sensors yet. The proposed thermal sensor pixel is composed of the series-connected a-IGZO TFT and ZnO-based thermistor fabricated on a polished metal foil, and the ZnO-based thermistor is replaced by the pressure sensitive rubber in the pressure sensor pixel. In both sensor pixels, the a-IGZO TFT acts as the driving transistor and the temperature/pressure-dependent resistance of the ZnO-based thermistor/pressure-sensitive rubber mainly determines the magnitude of the output currents. The fabricated a-IGZO TFT-driven flexible thermal sensor shows around a seven times increase in the output current as the temperature increases from 20 °C to 100 °C, and the a-IGZO TFT-driven flexible pressure sensors also exhibit high sensitivity under various pressure environments.

Controlling the mode of operation of organic transistors through side-chain engineering.

PubMed

Giovannitti, Alexander; Sbircea, Dan-Tiberiu; Inal, Sahika; Nielsen, Christian B; Bandiello, Enrico; Hanifi, David A; Sessolo, Michele; Malliaras, George G; McCulloch, Iain; Rivnay, Jonathan

2016-10-25

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors.

Multibit data storage states formed in plasma-treated MoS₂ transistors.

PubMed

Chen, Mikai; Nam, Hongsuk; Wi, Sungjin; Priessnitz, Greg; Gunawan, Ivan Manuel; Liang, Xiaogan

2014-04-22

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

PubMed

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

PubMed

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

Controlling the mode of operation of organic transistors through side-chain engineering

PubMed Central

Giovannitti, Alexander; Sbircea, Dan-Tiberiu; Inal, Sahika; Nielsen, Christian B.; Bandiello, Enrico; Hanifi, David A.; Sessolo, Michele; Malliaras, George G.; McCulloch, Iain; Rivnay, Jonathan

2016-01-01

Electrolyte-gated organic transistors offer low bias operation facilitated by direct contact of the transistor channel with an electrolyte. Their operation mode is generally defined by the dimensionality of charge transport, where a field-effect transistor allows for electrostatic charge accumulation at the electrolyte/semiconductor interface, whereas an organic electrochemical transistor (OECT) facilitates penetration of ions into the bulk of the channel, considered a slow process, leading to volumetric doping and electronic transport. Conducting polymer OECTs allow for fast switching and high currents through incorporation of excess, hygroscopic ionic phases, but operate in depletion mode. Here, we show that the use of glycolated side chains on a thiophene backbone can result in accumulation mode OECTs with high currents, transconductance, and sharp subthreshold switching, while maintaining fast switching speeds. Compared with alkylated analogs of the same backbone, the triethylene glycol side chains shift the mode of operation of aqueous electrolyte-gated transistors from interfacial to bulk doping/transport and show complete and reversible electrochromism and high volumetric capacitance at low operating biases. We propose that the glycol side chains facilitate hydration and ion penetration, without compromising electronic mobility, and suggest that this synthetic approach can be used to guide the design of organic mixed conductors. PMID:27790983

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

GaN transistors on Si for switching and high-frequency applications

NASA Astrophysics Data System (ADS)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

Magnetophoretic transistors in a tri-axial magnetic field.

PubMed

Abedini-Nassab, Roozbeh; Joh, Daniel Y; Albarghouthi, Faris; Chilkoti, Ashutosh; Murdoch, David M; Yellen, Benjamin B

2016-10-18

The ability to direct and sort individual biological and non-biological particles into spatially addressable locations is fundamentally important to the emerging field of single cell biology. Towards this goal, we demonstrate a new class of magnetophoretic transistors, which can switch single magnetically labeled cells and magnetic beads between different paths in a microfluidic chamber. Compared with prior work on magnetophoretic transistors driven by a two-dimensional in-plane rotating field, the addition of a vertical magnetic field bias provides significant advantages in preventing the formation of particle clumps and in better replicating the operating principles of circuits in general. However, the three-dimensional driving field requires a complete redesign of the magnetic track geometry and switching electrodes. We have solved this problem by developing several types of transistor geometries which can switch particles between two different tracks by either presenting a local energy barrier or by repelling magnetic objects away from a given track, hereby denoted as "barrier" and "repulsion" transistors, respectively. For both types of transistors, we observe complete switching of magnetic objects with currents of ∼40 mA, which is consistent over a range of particle sizes (8-15 μm). The switching efficiency was also tested at various magnetic field strengths (50-90 Oe) and driving frequencies (0.1-0.6 Hz); however, we again found that the device performance only weakly depended on these parameters. These findings support the use of these novel transistor geometries to form circuit architectures in which cells can be placed in defined locations and retrieved on demand.

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

NASA Technical Reports Server (NTRS)

Duong, Tuan A.

2012-01-01

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2011 CFR

2011-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2012 CFR

2012-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2013 CFR

2013-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

14 CFR 145.59 - Ratings.

Code of Federal Regulations, 2014 CFR

2014-01-01

... tubes, transistors, or similar devices, including capacitance type quantity gauges, system amplifiers... depends on the use of an electron tube transistor, or similar device, including supercharger, temperature...

Selective Dry Etch for Defining Ohmic Contacts for High Performance ZnO TFTs

DTIC Science & Technology

2014-03-27

scale, high-frequency ZnO thin - film transistors (TFTs) could be fabricated. Molybdenum, tantalum, titanium tungsten 10-90, and tungsten metallic contact... thin - film transistor layout utilized in the thesis research . . . . . 42 3.4 Process Flow Diagram for Optical and e-Beam Devices...TFT thin - film transistor TLM transmission line model UV ultra-violet xvii SELECTIVE DRY ETCH FOR DEFINING OHMIC CONTACTS FOR HIGH PERFORMANCE ZnO TFTs

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

Flexible low-voltage organic transistors with high thermal stability at 250 °C.

PubMed

Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Zschieschang, Ute; Klauk, Hagen; Takimiya, Kazuo; Sadamitsu, Yuji; Hamada, Masahiro; Sekitani, Tsuyoshi; Someya, Takao

2013-07-19

Low-operating-voltage flexible organic thin-film transistors with high thermal stability using DPh-DNTT and SAM gate dielectrics are reported. The mobility of the transistors are decreased by 23% after heating to 250 °C for 30 min. Furthermore, flexible organic pseudo-CMOS inverter circuits, which are functional after heating to 200 °C, are demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Organic electrochemical transistor array for recording transepithelial ion transport of human airway epithelial cells.

PubMed

Yao, Chunlei; Xie, Changyan; Lin, Peng; Yan, Feng; Huang, Pingbo; Hsing, I-Ming

2013-12-03

An organic electrochemical transistor array is integrated with human airway epithelial cells. This integration provides a novel method to couple transepithelial ion transport with electrical current. Activation and inhibition of transepithelial ion transport are readily detected with excellent time resolution. The organic electrochemical transistor array serves as a promising platform for physiological studies and drug testing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks

NASA Technical Reports Server (NTRS)

Kim, Jae-Hoon; Lin, Steven H.

1991-01-01

High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.

Energy-Filtered Tunnel Transistor: A New Device Concept Toward Extremely-Low Energy Consumption Electronics

DTIC Science & Technology

2015-12-17

temperature . New device architecture that utilizes cold-electron transport for ultra-low energy consumption electronics has been designed in a configuration...the oxygen has also been found important for the SiC>2 sputter deposition. The sputter was carried out at room temperature . Our optimized process...have been pursued for two electronic devices, 1) room- temperature single-electron transistors, and 2) ultralow energy consumption transistors. For

Solid-state X-band Combiner Study

NASA Technical Reports Server (NTRS)

Pitzalis, O., Jr.; Russell, K. J.

1979-01-01

The feasibility of developing solid-state amplifiers at 4 and 10 GHz for application in spacecraft altimeters was studied. Bipolar-transistor, field-effect-transistor, and Impatt-diode amplifier designs based on 1980 solid-state technology are investigated. Several output power levels of the pulsed, low-duty-factor amplifiers are considered at each frequency. Proposed transistor and diode amplifier designs are illustrated in block diagrams. Projections of size, weight, and primary power requirements are given for each design.

An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

NASA Astrophysics Data System (ADS)

Shen, Yanfei; Cui, Jie; Mohammadi, Saeed

2017-05-01

A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45 nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40 GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26 GHz. The developed model is simple and easy to extract, yet very accurate.

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

NASA Astrophysics Data System (ADS)

Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Molecular gated-AlGaN/GaN high electron mobility transistor for pH detection.

PubMed

Ding, Xiangzhen; Yang, Shuai; Miao, Bin; Gu, Le; Gu, Zhiqi; Zhang, Jian; Wu, Baojun; Wang, Hong; Wu, Dongmin; Li, Jiadong

2018-04-18

A molecular gated-AlGaN/GaN high electron mobility transistor has been developed for pH detection. The sensing surface of the sensor was modified with 3-aminopropyltriethoxysilane to provide amphoteric amine groups, which would play the role of receptors for pH detection. On modification with 3-aminopropyltriethoxysilane, the transistor exhibits good chemical stability in hydrochloric acid solution and is sensitive for pH detection. Thus, our molecular gated-AlGaN/GaN high electron mobility transistor acheived good electrical performances such as chemical stability (remained stable in hydrochloric acid solution), good sensitivity (37.17 μA/pH) and low hysteresis. The results indicate a promising future for high-quality sensors for pH detection.

A Klein-tunneling transistor with ballistic graphene

NASA Astrophysics Data System (ADS)

Wilmart, Quentin; Berrada, Salim; Torrin, David; Nguyen, V. Hung; Fève, Gwendal; Berroir, Jean-Marc; Dollfus, Philippe; Plaçais, Bernard

2014-06-01

Today, the availability of high mobility graphene up to room temperature makes ballistic transport in nanodevices achievable. In particular, p-n-p transistors in the ballistic regime give access to Klein tunneling physics and allow the realization of devices exploiting the optics-like behavior of Dirac Fermions (DFs) as in the Veselago lens or the Fabry-Pérot cavity. Here we propose a Klein tunneling transistor based on the geometrical optics of DFs. We consider the case of a prismatic active region delimited by a triangular gate, where total internal reflection may occur, which leads to the tunable suppression of transistor transmission. We calculate the transmission and the current by means of scattering theory and the finite bias properties using non-equilibrium Green's function (NEGF) simulation.

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Fossum, Eric R.; Baier, Steven M.

1992-01-01

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Development of a measurement technique for qualitative analysis of MOS transistors using Kuhn's method for MOS varactors

NASA Astrophysics Data System (ADS)

Krautschneider, W.

The semiconductor junction region up to the oxidized surface layer is studied. The object of study is a MOS capacitor, but it is shown that the obtained values of the surface characteristics apply to more complicated MOS transistors. The metal oxide-silicon system is discussed in terms of an ideal varactor, the actual MOS structure, and the MOS system with p-n junction. The determination of the phase interface state density in MOS varactors and MOS transistors is addressed, as the quasistatic C(V) experiment of Kuhn (1970) is theoretically and experimentally extended from MOS varactors to MOS transistors. The surface recombination speed is treated, and the experimental results are compared with theoretical predictions.

Fully transparent conformal organic thin-film transistor array and its application as LED front driving.

PubMed

Cui, Nan; Ren, Hang; Tang, Qingxin; Zhao, Xiaoli; Tong, Yanhong; Hu, Wenping; Liu, Yichun

2018-02-22

A fully transparent conformal organic thin-film field-effect transistor array is demonstrated based on a photolithography-compatible ultrathin metallic grid gate electrode and a solution-processed C 8 -BTBT film. The resulting organic field-effect transistor array exhibits a high optical transparency of >80% over the visible spectrum, mobility up to 2 cm 2 V -1 s -1 , on/off ratio of 10 5 -10 6 , switching current of >0.1 mA, and excellent light stability. The transparent conformal transistor array is demonstrated to adhere well to flat and curved LEDs as front driving. These results present promising applications of the solution-processed wide-bandgap organic semiconductor thin films in future large-scale transparent conformal active-matrix displays.

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

NASA Technical Reports Server (NTRS)

MacLeod, Todd, C.; Ho, Fat Duen

2006-01-01

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

High Stability Pentacene Transistors Using Polymeric Dielectric Surface Modifier.

PubMed

Wang, Xiaohong; Lin, Guangqing; Li, Peng; Lv, Guoqiang; Qiu, Longzhen; Ding, Yunsheng

2015-08-01

1,6-bis(trichlorosilyl)hexane (C6Cl), polystyrene (PS), and cross-linked polystyrene (CPS) were investigated as gate dielectric modified layers for high performance organic transistors. The influence of the surface energy, roughness and morphology on the charge transport of the organic thin-film transistors (OTFTs) was investigated. The surface energy and roughness both affect the grain size of the pentacene films which will control the charge carrier mobility of the devices. Pentacene thin-film transistors fabricated on the CPS modified dielectric layers exhibited charge carrier mobility as high as 1.11 cm2 V-1 s-1. The bias stress stability for the CPS devices shows that the drain current only decays 1% after 1530 s and the mobility never decreases until 13530 s.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

Polymer-based doping control for performance enhancement of wet-processed short-channel CNTFETs

NASA Astrophysics Data System (ADS)

Hartmann, Martin; Schubel, René; Claus, Martin; Jordan, Rainer; Schulz, Stefan E.; Hermann, Sascha

2018-01-01

The electrical transport properties of short-channel transistors based on single-walled carbon nanotubes (CNT) are significantly affected by bundling along with solution processing. We report that especially high off currents of CNT transistors are not only related to the incorporation of metallic CNTs but also to the incorporation of CNT bundles. By applying device passivation with poly(4-vinylpyridine), the impact of CNT bundling on the device performance can be strongly reduced due to increased gate efficiency as well as reduced oxygen and water-induced p-type doping, boosting essential field-effect transistor performance parameters by several orders of magnitude. Moreover, this passivation approach allows the hysteresis and threshold voltage of CNT transistors to be tuned.

MMIC DHBT Common-Base Amplifier for 172 GHz

NASA Technical Reports Server (NTRS)

Paidi, Vamsi; Griffith, Zack; Wei, Yun; Dahlstrom, Mttias; Urteaga, Miguel; Rodwell, Mark; Samoska, Lorene; Fung, King Man; Schlecht, Erich

2006-01-01

Figure 1 shows a single-stage monolithic microwave integrated circuit (MMIC) power amplifier in which the gain element is a double-heterojunction bipolar transistor (DHBT) connected in common-base configuration. This amplifier, which has been demonstrated to function well at a frequency of 172 GHz, is part of a continuing effort to develop compact, efficient amplifiers for scientific instrumentation, wide-band communication systems, and radar systems that will operate at frequencies up to and beyond 180 GHz. The transistor is fabricated from a layered structure formed by molecular beam epitaxy in the InP/InGaAs material system. A highly doped InGaAs base layer and a collector layer are fabricated from the layered structure in a triple mesa process. The transistor includes two separate emitter fingers, each having dimensions of 0.8 by 12 m. The common-base configuration was chosen for its high maximum stable gain in the frequency band of interest. The input-matching network is designed for high bandwidth. The output of the transistor is matched to a load line for maximum saturated output power under large-signal conditions, rather than being matched for maximum gain under small-signal conditions. In a test at a frequency of 172 GHz, the amplifier was found to generate an output power of 7.5 mW, with approximately 5 dB of large-signal gain (see Figure 2). Moreover, the amplifier exhibited a peak small-signal gain of 7 dB at a frequency of 176 GHz. This performance of this MMIC single-stage amplifier containing only a single transistor represents a significant advance in the state of the art, in that it rivals the 170-GHz performance of a prior MMIC three-stage, four-transistor amplifier. [The prior amplifier was reported in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11 (November 2003), page 49.] This amplifier is the first heterojunction- bipolar-transistor (HBT) amplifier built for medium power operation in this frequency band. The performance of the amplifier as measured in the aforementioned tests suggests that InP/InGaAs HBTs may be superior to high-electron-mobility (HEMT) transistors in that the HBTs may offer more gain per stage and more output power per transistor.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Nanoelectronics and Plasma Processing---The Next 15 Years and Beyond

NASA Astrophysics Data System (ADS)

Lieberman, Michael A.

2006-10-01

The number of transistors per chip has doubled every 2 years since 1959, and this doubling will continue over the next 15 years as transistor sizes shrink. There has been a 25 million-fold decrease in cost for the same performance, and in 15 years a desktop computer will be hundreds of times more powerful than one today. Transistors now have 37 nm (120 atoms) gate lengths and 1.5 nm (5 atoms) gate oxide thicknesses. The smallest working transistor has a 5 nm (17 atoms) gate length, close to the limiting gate length, from simulations, of about 4 nm. Plasma discharges are used to fabricate hundreds of billions of these nano-size transistors on a silicon wafer. These discharges have evolved from a first generation of ``low density'' reactors capacitively driven by a single source, to a second generation of ``high density'' reactors (inductive and electron cyclotron resonance) having two rf power sources, in order to control independently the ion flux and ion bombarding energy to the substrate. A third generation of ``moderate density'' reactors, driven capacitively by one high and one low frequency rf source, is now widely used. Recently, triple frequency and combined dc/dual frequency discharges have been investigated, to further control processing characteristics, such as ion energy distributions, uniformity, and plasma etch selectivities. There are many interesting physics issues associated with these discharges, including stochastic heating of discharge electrons by dual frequency sheaths, nonlinear frequency interactions, powers supplied by the multi-frequency sources, and electromagnetic effects such as standing waves and skin effects. Beyond the 4 nm transistor limit lies a decade of further performance improvements for conventional nanoelectronics, and beyond that, a dimly-seen future of spintronics, single-electron transistors, cross-bar latches, and molecular electronics.

Automating analog design: Taming the shrew

NASA Technical Reports Server (NTRS)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Quantum structures for recombination control in the light-emitting transistor

NASA Astrophysics Data System (ADS)

Chen, Kanuo; Hsiao, Fu-Chen; Joy, Brittany; Dallesasse, John M.

2017-02-01

Recombination of carriers in the direct-bandgap base of a transistor-injected quantum cascade laser (TI-QCL) is shown to be controllable through the field applied across the quantum cascade region located in the transistor's base-collector junction. The influence of the electric field on the quantum states in the cascade region's superlattice allows free flow of electrons out of the transistor base only for field values near the design field that provides optimal QCL gain. Quantum modulation of base recombination in the light-emitting transistor is therefore observed. In a GaAs-based light-emitting transistor, a periodic superlattice is grown between the p-type base and the n-type collector. Under different base-collector biasing conditions the distribution of quantum states, and as a consequence transition probabilities through the wells and barriers forming the cascade region, leads to strong field-dependent mobility for electrons in transit through the base-collector junction. The radiative base recombination, which is influenced by minority carrier transition lifetime, can be modulated through the quantum states alignment in the superlattice. A GaAs-based transistor-injected quantum cascade laser with AlGaAs/GaAs superlattice is designed and fabricated. Radiative base recombination is measured under both common-emitter and common-base configuration. In both configurations the optical output from the base is proportional to the emitter injection. When the quantum states in the superlattice are aligned the optical output in the base is reduced as electrons encounter less impedance entering the collector; when the quantum states are misaligned electrons have longer lifetime in the base and the radiative base recombination process is enhanced.

Development of an algorithm for controlling a multilevel three-phase converter

NASA Astrophysics Data System (ADS)

Taissariyeva, Kyrmyzy; Ilipbaeva, Lyazzat

2017-08-01

This work is devoted to the development of an algorithm for controlling transistors in a three-phase multilevel conversion system. The developed algorithm allows to organize a correct operation and describes the state of transistors at each moment of time when constructing a computer model of a three-phase multilevel converter. The developed algorithm of operation of transistors provides in-phase of a three-phase converter and obtaining a sinusoidal voltage curve at the converter output.

A Study of Electrical and Optical Stability of GSZO THin Film Transisitors

DTIC Science & Technology

2014-01-01

introduces an overview of the research carried out on IGZO , ZnO, and GSZO thin film transistors that is relevant to the work discussed in this...dangling bonds or electron trapping near the gate insulator interface in IGZO thin film transistors . Mathews et al. [13] indicated that subjecting TFTs to...Ping David Shieh, Hideo Hosono, and Jerzy Kanicki, Photofield-Effect in Amporphous In-Ga-Zn-O (a- IGZO ) Thin - Film Transistors . Journal of Information

Bit Error Ratio Test Equipment for High Speed Vertical Cavity Transistor Laser and MicroCavity VCSEL and Photo Receiver

DTIC Science & Technology

2015-08-31

Ratio Test Equipment for High Speed Vertical Cavity Transistor Laser & MicroCavity VCSEL and Photo Receiver The views, opinions and/or findings...suggesstions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis...for High Speed Vertical Cavity Transistor Laser & MicroCavity VCSEL and Photo Receiver Report Title In the previous DURIP award (W911NF-13-1-0287

Development of a Planar Heterojunction Bipolar Transistor for Very High Speed Logic.

DTIC Science & Technology

1983-12-01

AD- R136 341 DEVELOPMENT OF A PLANAR HETEROJUNCTION BIPOLAR i/i TRANSISTOR FOR VERV HIGH S..(U) CALIFORNIA UNIV SANTA BARBARA DEPT OF ELECTRICAL AND...GaAs material systems . Emphasis has been placed on growth and char- acterization of the above heterojunctions by Holecular Beam Epitaxy and on the...GaAs material system is used to fabricate discrete single heterojunction bipolar transistor structures. Conventional mesa-etch tech- niques will be used

A Probe for Measuring Spacecraft Surface Potentials Using a Direct-Gate Field Effect Transistor.

DTIC Science & Technology

1983-09-30

SURFACE POTENTIALS USING A DIRECT-GATE FIELD EFFECT TRANSISTOR Mark N. Horenstein Anton Havretic Trustees of Boston University 881 Commonwealth Avenue...1933 Transistor 6. PERFORMING ORG. REPORT NUMBER 7. AUTHOR(s) S. CONTRACT OR GRANT NUMBER(&) ’_5 Mark N. Horenstein Anton Mavretic F19628-82-K-00 34...at AFGL. These tests can be considered the bench mark tests for device performance, with all elements of the monitoring system optimized to eliminate

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Mapping of trap densities and hotspots in pentacene thin-film transistors by frequency-resolved scanning photoresponse microscopy.

PubMed

Westermeier, Christian; Fiebig, Matthias; Nickel, Bert

2013-10-25

Frequency-resolved scanning photoresponse microscopy of pentacene thin-film transistors is reported. The photoresponse pattern maps the in-plane distribution of trap states which is superimposed by the level of trap filling adjusted by the gate voltage of the transistor. Local hotspots in the photoresponse map thus indicate areas of high trap densities within the pentacene thin film. © 2013 WILEY-VCH Verlag GmbH 8 Co. KGaA, Weinheim.

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Low Voltage, Low Power Organic Light Emitting Transistors for AMOLED Displays

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCarthy, M. A.; Liu, B.; Donoghue, E. P.

2011-01-01

Low voltage, low power dissipation, high aperture ratio organic light emitting transistors are demonstrated. The high level of performance is enabled by a carbon nanotube source electrode that permits integration of the drive transistor and the organic light emitting diode into an efficient single stacked device. Given the demonstrated performance, this technology could break the technical logjam holding back widespread deployment of active matrix organic light emitting displays at flat panel screen sizes.

Integration of Organic Electrochemical and Field-Effect Transistors for Ultraflexible, High Temporal Resolution Electrophysiology Arrays.

PubMed

Lee, Wonryung; Kim, Dongmin; Rivnay, Jonathan; Matsuhisa, Naoji; Lonjaret, Thomas; Yokota, Tomoyuki; Yawo, Hiromu; Sekino, Masaki; Malliaras, George G; Someya, Takao

2016-11-01

Integration of organic electrochemical transistors and organic field-effect transistors is successfully realized on a 600 nm thick parylene film toward an electrophysiology array. A single cell of an integrated device and a 2 × 2 electrophysiology array succeed in detecting electromyogram with local stimulation of the motor nerve bundle of a transgenic rat by a laser pulse. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Heterojunction bipolar transistor technology for data acquisition and communication

NASA Technical Reports Server (NTRS)

Wang, C.; Chang, M.; Beccue, S.; Nubling, R.; Zampardi, P.; Sheng, N.; Pierson, R.

1992-01-01

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Abnormal Multiple Charge Memory States in Exfoliated Few-Layer WSe2 Transistors.

PubMed

Chen, Mikai; Wang, Yifan; Shepherd, Nathan; Huard, Chad; Zhou, Jiantao; Guo, L J; Lu, Wei; Liang, Xiaogan

2017-01-24

To construct reliable nanoelectronic devices based on emerging 2D layered semiconductors, we need to understand the charge-trapping processes in such devices. Additionally, the identified charge-trapping schemes in such layered materials could be further exploited to make multibit (or highly desirable analog-tunable) memory devices. Here, we present a study on the abnormal charge-trapping or memory characteristics of few-layer WSe 2 transistors. This work shows that multiple charge-trapping states with large extrema spacing, long retention time, and analog tunability can be excited in the transistors made from mechanically exfoliated few-layer WSe 2 flakes, whereas they cannot be generated in widely studied few-layer MoS 2 transistors. Such charge-trapping characteristics of WSe 2 transistors are attributed to the exfoliation-induced interlayer deformation on the cleaved surfaces of few-layer WSe 2 flakes, which can spontaneously form ambipolar charge-trapping sites. Our additional results from surface characterization, charge-retention characterization at different temperatures, and density functional theory computation strongly support this explanation. Furthermore, our research also demonstrates that the charge-trapping states excited in multiple transistors can be calibrated into consistent multibit data storage levels. This work advances the understanding of the charge memory mechanisms in layered semiconductors, and the observed charge-trapping states could be further studied for enabling ultralow-cost multibit analog memory devices.

Quantum Optical Transistor and Other Devices Based on Nanostructures

NASA Astrophysics Data System (ADS)

Li, Jin-Jin; Zhu, Ka-Di

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to nanostructures. This provides an important clue toward the realization of quantum optical devices, such as quantum optical transistor, slow light device, fast light device, or light storage device. In contrast to conventional electronic transistor, a quantum optical transistor uses photons as signal carriers rather than electrons, which has a faster and more powerful transfer efficiency. Under the radiation of a strong pump laser, a signal laser can be amplified or attenuated via passing through a single quantum dot coupled to a photonic crystal (PC) nanocavity system. Such a switching and amplifying behavior can really implement the quantum optical transistor. By simply turning on or off the input pump laser, the amplified or attenuated signal laser can be obtained immediately. Based on this transistor, we further propose a method to measure the vacuum Rabi splitting of exciton in all-optical domain. Besides, we study the light propagation in a coupled QD and nanomechanical resonator (NR) system. We demonstrate that it is possible to achieve the slow light, fast light, and quantum memory for light on demand, which is based on the mechanically induced coherent population oscillation (MICPO) and exciton polaritons. These QD devices offer a route toward the use of all-optical technique to investigate the coupled QD systems and will make contributions to quantum internets and quantum computers.

Single-phase frequency converter

NASA Astrophysics Data System (ADS)

Baciu, I.; Cunţan, C. D.

2017-01-01

The paper presents a continuous voltage inverter - AC (12V / 230V) made with IGBT and two-stage voltage transformer. The sequence control transistors is achieved using a ring counter whose clock signal is obtained with a monostable circuit LM 555. The frequency of the clock signal can be adjustment with a potentiometer that modifies the charging current of the capacitor which causes constant monostable circuit time. Command sequence consists of 8 intervals of which 6 are assigned to command four transistors and two for the period break at the beginning and end of the sequence control. To obtain an alternation consisting of two different voltage level, two transistors will be comanded, connected to different windings of the transformer and the one connected to the winding providing lower voltage must be comanded twice. The output of the numerator goes through an inverter type MOS and a current amplifier with bipolar transistor.To achieve galvanic separation, an optocoupler will be used for each IGBT transistor, while protection is achieved with resistance and diode circuit. At the end there is connected an LC filter for smoothing voltage variations.

'Soft' amplifier circuits based on field-effect ionic transistors.

PubMed

Boon, Niels; Olvera de la Cruz, Monica

2015-06-28

Soft materials can be used as the building blocks for electronic devices with extraordinary properties. We introduce a theoretical model for a field-effect transistor in which ions are the gated species instead of electrons. Our model incorporates readily-available soft materials, such as conductive porous membranes and polymer-electrolytes to represent a device that regulates ion currents and can be integrated as a component in larger circuits. By means of Nernst-Planck numerical simulations as well as an analytical description of the steady-state current we find that the responses of the system to various input voltages can be categorized into ohmic, sub-threshold, and active modes. This is fully analogous to what is known for the electronic field-effect transistor (FET). Pivotal FET properties such as the threshold voltage and the transconductance crucially depend on the half-cell redox potentials of the source and drain electrodes as well as on the polyelectrolyte charge density and the gate material work function. We confirm the analogy with the electronic FETs through numerical simulations of elementary amplifier circuits in which we successfully substitute the electronic transistor by an ionic transistor.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

A Flush Toilet Model for the Transistor

NASA Astrophysics Data System (ADS)

Organtini, Giovanni

2012-04-01

In introductory physics textbooks, diodes working principles are usually well described in a relatively simple manner. According to our experience, they are well understood by students. Even when no formal derivation of the physics laws governing the current flow through a diode is given, the use of this device as a check valve is easily accepted. This is not true for transistors. In most textbooks the behavior of a transistor is given without formal explanation. When the amplification is computed, for some reason, students have difficulties in identifying the basic physical mechanisms that give rise to such an effect. In this paper we give a simple and captivating illustration of the working principles of a transistor as an amplifier, tailored to high school students even with almost no background in electronics nor in modern physics. We assume that the target audience is familiar with the idea that a diode works as a check valve for currents. The lecture emphasis is on the illustration of physics principles governing the behavior of a transistor, rather than on a formal description of the processes leading to amplification.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

NASA Astrophysics Data System (ADS)

Liu, Xuhai; Kasemann, Daniel; Leo, Karl

2015-03-01

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

High-mobility pyrene-based semiconductor for organic thin-film transistors.

PubMed

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

PubMed

Park, Rebecca Sejung; Shulaker, Max Marcel; Hills, Gage; Suriyasena Liyanage, Luckshitha; Lee, Seunghyun; Tang, Alvin; Mitra, Subhasish; Wong, H-S Philip

2016-04-26

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chao, Jin Yu; Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn

Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor inmore » series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.« less

Flexible black phosphorus ambipolar transistors, circuits and AM demodulator.

PubMed

Zhu, Weinan; Yogeesh, Maruthi N; Yang, Shixuan; Aldave, Sandra H; Kim, Joon-Seok; Sonde, Sushant; Tao, Li; Lu, Nanshu; Akinwande, Deji

2015-03-11

High-mobility two-dimensional (2D) semiconductors are desirable for high-performance mechanically flexible nanoelectronics. In this work, we report the first flexible black phosphorus (BP) field-effect transistors (FETs) with electron and hole mobilities superior to what has been previously achieved with other more studied flexible layered semiconducting transistors such as MoS2 and WSe2. Encapsulated bottom-gated BP ambipolar FETs on flexible polyimide afforded maximum carrier mobility of about 310 cm(2)/V·s with field-effect current modulation exceeding 3 orders of magnitude. The device ambipolar functionality and high-mobility were employed to realize essential circuits of electronic systems for flexible technology including ambipolar digital inverter, frequency doubler, and analog amplifiers featuring voltage gain higher than other reported layered semiconductor flexible amplifiers. In addition, we demonstrate the first flexible BP amplitude-modulated (AM) demodulator, an active stage useful for radio receivers, based on a single ambipolar BP transistor, which results in audible signals when connected to a loudspeaker or earphone. Moreover, the BP transistors feature mechanical robustness up to 2% uniaxial tensile strain and up to 5000 bending cycles.

a High-Level Technique for Estimation and Optimization of Leakage Power for Full Adder

NASA Astrophysics Data System (ADS)

Shrivas, Jayram; Akashe, Shyam; Tiwari, Nitesh

2013-06-01

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

2002-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Electric bistability induced by incorporating self-assembled monolayers/aggregated clusters of azobenzene derivatives in pentacene-based thin-film transistors.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2012-10-24

Composite films of pentacene and a series of azobenzene derivatives are prepared and used as the active channel material in top-contact, bottom-gate field-effect transistors. The transistors exhibit high field-effect mobility as well as large I-V hysteresis as a function of the gate bias history. The azobenzene moieties, incorporated either in the form of self-assembled monolayer or discrete multilayer clusters at the dielectric surface, result in electric bistability of the pentacene-based transistor either by photoexcitation or gate biasing. The direction of threshold voltage shifts, size of hysteresis, response time, and retention characteristics all strongly depend on the substituent on the benzene ring. The results show that introducing a monolayer of azobenzene moieties results in formation of charge carrier traps responsible for slower switching between the bistable states and longer retention time. With clusters of azobenzene moieties as the trap sites, the switching is faster but the retention is shorter. Detailed film structure analyses and correlation with the transistor/memory properties of these devices are provided.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

PubMed

Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

2018-05-09

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Throwing computing into reverse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Frank, Michael P.

For more than 50 years, computers have made steady and dramatic improvements, all thanks to Moore’s Law—the exponential increase over time in the number of transistors that can be fabricated on an integrated circuit of a given size. Moore’s Law owed its success to the fact that as transistors were made smaller, they became simultaneously cheaper, faster, and more energy efficient. The payoff from this win-win-win scenario enabled reinvestment in semiconductor fabrication technology that could make even smaller, more densely-packed transistors. And so this virtuous cycle continued, decade after decade. Now though, experts in industry, academia, and government laboratories anticipatemore » that semiconductor miniaturization won’t continue much longer—maybe 10 years or so, at best. Making transistors smaller no longer yields the improvements it used to. The physical characteristics of small transistors forced clock speeds to cease getting faster more than a decade ago, which drove the industry to start building chips with multiple cores. But even multi-core architectures must contend with increasing amounts of “dark silicon,” areas of the chip that must be powered off to avoid overheating.« less

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

NASA Astrophysics Data System (ADS)

Kiani, Ahmed; Hasko, David G.; Milne, William I.; Flewitt, Andrew J.

2013-04-01

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation.

Quantum Thermal Transistor.

PubMed

Joulain, Karl; Drevillon, Jérémie; Ezzahri, Younès; Ordonez-Miranda, Jose

2016-05-20

We demonstrate that a thermal transistor can be made up with a quantum system of three interacting subsystems, coupled to a thermal reservoir each. This thermal transistor is analogous to an electronic bipolar one with the ability to control the thermal currents at the collector and at the emitter with the imposed thermal current at the base. This is achieved by determining the heat fluxes by means of the strong-coupling formalism. For the case of three interacting spins, in which one of them is coupled to the other two, that are not directly coupled, it is shown that high amplification can be obtained in a wide range of energy parameters and temperatures. The proposed quantum transistor could, in principle, be used to develop devices such as a thermal modulator and a thermal amplifier in nanosystems.

Powerful, Efficient Electric Vehicle Chargers: Low-Cost, Highly-Integrated Silicon Carbide (SiC) Multichip Power Modules (MCPMs) for Plug-In Hybrid Electric

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-09-14

ADEPT Project: Currently, charging the battery of an electric vehicle (EV) is a time-consuming process because chargers can only draw about as much power from the grid as a hair dryer. APEI is developing an EV charger that can draw as much power as a clothes dryer, which would drastically speed up charging time. APEI's charger uses silicon carbide (SiC)-based power transistors. These transistors control the electrical energy flowing through the charger's circuits more effectively and efficiently than traditional transistors made of straight silicon. The SiC-based transistors also require less cooling, enabling APEI to create EV chargers that are 10more » times smaller than existing chargers.« less

Low-Temperature, Solution-Processed, Transparent Zinc Oxide-Based Thin-Film Transistors for Sensing Various Solvents.

PubMed

You, Hsin-Chiang; Wang, Cheng-Jyun

2017-02-26

A low temperature solution-processed thin-film transistor (TFT) using zinc oxide (ZnO) film as an exposed sensing semiconductor channel was fabricated to detect and identify various solution solvents. The TFT devices would offer applications for low-cost, rapid and highly compatible water-soluble detection and could replace conventional silicon field effect transistors (FETs) as bio-sensors. In this work, we demonstrate the utility of the TFT ZnO channel to sense various liquids, such as polar solvents (ethanol), non-polar solvents (toluene) and deionized (DI) water, which were dropped and adsorbed onto the channel. It is discussed how different dielectric constants of polar/non-polar solvents and DI water were associated with various charge transport properties, demonstrating the main detection mechanisms of the thin-film transistor.

Transport Mechanisms in Organic Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fung, A. W. P.

1996-03-01

Recent success in fabricating field-effect transistors with polycrystalline α-sexithiophene (α-6T) has allowed us to study charge transport in this organic semiconductor. The appealing structural property that the oligomer chains are seated almost perpendicular to the substrate provides a model π-conjugated system which we find exhibits band transport at low temperatures. We observe a behavioral transition around 50K which is consistent with the metal-insulator transition in Holstein's small-polaron theory. The fact that we can observe intrinsic behavior means that the ambient-temperature mobility obtained in these transistors is optimal for α-6T. Agreement with the Holstein theory provides us with a prescription for rational design of materials for organic transistor applications. Work done in collaboration with L. Torsi, A. Dodabalapur, L. J. Rothberg and H. E. Katz.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

NASA Astrophysics Data System (ADS)

Lee, Sungsik; Nathan, Arokia

2016-10-01

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Optical Probe of the Density of Defect States in Organic Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Breban, Mihaela; Romero, Danilo; Ballarotto, Vincent; Williams, Ellen

2006-03-01

We investigate the role of defect states associated with different gate dielectric materials on charge transport in organic thin film transistors. Using a modulation technique we measure the magnitude and the phase of the photocurrent^1 in pentacene thin film transistors as a function of the modulation frequency. The photocurrent generation process is modeled as exciton dissociation due to interaction with localized traps. A time domain analyses of this multi-step process allows us to extract the density of defect states. We use this technique to compare the physical mechanism underlying performances of pentacene devices fabricated with different dielectric materials. *Supported by the Laboratory for Physical Science ^1 M. Breban, et al. ``Photocurrent probe of field-dependent mobility in organic thin-film transistors'' Appl. Phys. Letts. 87, 203503 (2005)

Chemical free device fabrication of two dimensional van der Waals materials based transistors by using one-off stamping

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Young Tack, E-mail: 023273@kist.re.kr, E-mail: stunalren@gmail.com; Choi, Won Kook; Materials and Life Science Research Division, Korea Institute of Science and Technology

We report on a chemical free one-off imprinting method to fabricate two dimensional (2D) van der Waals (vdWs) materials based transistors. Such one-off imprinting technique is the simplest and effective way to prevent unintentional chemical reaction or damage of 2D vdWs active channel during device fabrication process. 2D MoS{sub 2} nanosheets based transistors with a hexagonal-boron-nitride (h-BN) passivation layer, prepared by one-off imprinting, show negligible variations of transfer characteristics after chemical vapor deposition process. In addition, this method enables the fabrication of all 2D MoS{sub 2} transistors consisting of h-BN gate insulator, and graphene source/drain and gate electrodes without anymore » chemical damage.« less

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Phase-locked loop based on nanoelectromechanical resonant-body field effect transistor

NASA Astrophysics Data System (ADS)

Bartsch, S. T.; Rusu, A.; Ionescu, A. M.

2012-10-01

We demonstrate the room-temperature operation of a silicon nanoelectromechanical resonant-body field effect transistor (RB-FET) embedded into phase-locked loop (PLL). The very-high frequency resonator uses on-chip electrostatic actuation and transistor-based displacement detection. The heterodyne frequency down-conversion based on resistive FET mixing provides a loop feedback signal with high signal-to-noise ratio. We identify key parameters for PLL operation, and analyze the performance of the RB-FET at the system level. Used as resonant mass detector, the experimental frequency stability in the ppm-range translates into sub atto-gram (10-18 g) sensitivity in high vacuum. The feedback and control system are generic and may be extended to other mechanical resonators with transistor properties, such as graphene membranes and carbon nanotubes.

Field effects in graphene in an interface contact with aqueous solutions of acetic acid and potassium hydroxide

NASA Astrophysics Data System (ADS)

Butko, A. V.; Butko, V. Yu.; Lebedev, S. P.; Lebedev, A. A.; Kumzerov, Yu. A.

2017-10-01

For the creation of new promising chemical sensors, it is very important to study the influence of the interface between graphene and aqueous solutions of acids and alkalis on the transistor characteristics of graphene. Transistor structures on the basis of graphene grown by thermal decomposition of silicon carbide were created and studied. For the interface of graphene with aqueous solutions of acetic acid and potassium hydroxide in the transistor geometry, with a variation in the gate-to-source voltage, the field effect corresponding to the hole type of charge carriers in graphene was observed. It is established that an increase in the concentration of molecular ions in these solutions leads to an increase in the dependence of the resistance of the transistor on the gate voltage.

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

Effect of random inhomogeneities in the spatial distribution of radiation-induced defect clusters on carrier transport through the thin base of a heterojunction bipolar transistor upon neutron irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Puzanov, A. S.; Obolenskiy, S. V., E-mail: obolensk@rf.unn.ru; Kozlov, V. A.

We analyze the electron transport through the thin base of a GaAs heterojunction bipolar transistor with regard to fluctuations in the spatial distribution of defect clusters induced by irradiation with a fissionspectrum fast neutron flux. We theoretically demonstrate that the homogeneous filling of the working region with radiation-induced defect clusters causes minimum degradation of the dc gain of the heterojunction bipolar transistor.

Gallium Arsenide Pilot Line for High Performance Components

DTIC Science & Technology

1992-05-28

two transistors’ characteristics were a close enough match to use as pull -up, high resistance loads in the cell. FET Data Unfortunately, data obtained...length transistors in 4K SRAM II, we can predict the performance of the memory chip. Since there is essentially no active pull up capability in the c a...Second, the 2/2 Am DFET’s threshold and "ON" current could be adjusted. Or third, a different size DFET pull -up transistor could be used which more

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Circuit-level simulation of transistor lasers and its application to modelling of microwave photonic links

NASA Astrophysics Data System (ADS)

Iezekiel, Stavros; Christou, Andreas

2015-03-01

Equivalent circuit models of a transistor laser are used to investigate the suitability of this relatively new device for analog microwave photonic links. The three-terminal nature of the device enables transistor-based circuit design techniques to be applied to optoelectronic transmitter design. To this end, we investigate the application of balanced microwave amplifier topologies in order to enable low-noise links to be realized with reduced intermodulation distortion and improved RF impedance matching compared to conventional microwave photonic links.

Test simulation of neutron damage to electronic components using accelerator facilities

NASA Astrophysics Data System (ADS)

King, D. B.; Fleming, R. M.; Bielejec, E. S.; McDonald, J. K.; Vizkelethy, G.

2015-12-01

The purpose of this work is to demonstrate equivalent bipolar transistor damage response to neutrons and silicon ions. We report on irradiation tests performed at the White Sands Missile Range Fast Burst Reactor, the Sandia National Laboratories (SNL) Annular Core Research Reactor, the SNL SPHINX accelerator, and the SNL Ion Beam Laboratory using commercial silicon npn bipolar junction transistors (BJTs) and III-V Npn heterojunction bipolar transistors (HBTs). Late time and early time gain metrics as well as defect spectra measurements are reported.

Programmable, automated transistor test system

NASA Technical Reports Server (NTRS)

Truong, L. V.; Sundburg, G. R.

1986-01-01

A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.

Vertical GaN Devices for Power Electronics in Extreme Environments

DTIC Science & Technology

2016-03-31

electronics applications. In this paper vertical p-n diodes and transistors fabricated on pseudo bulk low defect density (104 to 106 cm-2) GaN substrates are...holes in p-GaN has deleterious effect on p-n junction behavior (Fig. 2), p-GaN contacts, and channel control in junction field-effect transistors at...and transistors ) utilizing p-n junctions are suitable for most practical applications including automotive (210K < T < 423K) but may have limitations

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures.

PubMed

Liu, Yuan; Sheng, Jiming; Wu, Hao; He, Qiyuan; Cheng, Hung-Chieh; Shakir, Muhammad Imran; Huang, Yu; Duan, Xiangfeng

2016-06-01

Scalable fabrication of vertical-tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm(-2) . This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene-silicon heterostructures. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Multiplexing of Radio-Frequency Single Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, Thomas R.; Pellerano, F. A.; Stahle, C. M.; Aidala, K.; Schoelkopf, R. J.; Krebs, Carolyn (Technical Monitor)

2001-01-01

We present results on wavelength division multiplexing of radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. A two-channel demonstration of this concept using discrete components successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.

Integration of Peptides into Organic Thin Film Transistor (OTFT)-based Printable Sensors

DTIC Science & Technology

2017-02-10

AFRL-AFOSR-JP-TR-2017-0009 Integration of Peptides into Organic Thin Film Transistor (OTFT)-based Printable Sensors Paul Dastoor UNIVERSITY OF...collection of information   if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ORGANIZATION . 1...Peptides into Organic Thin Film Transistor (OTFT)-based Printable Sensors 5a.  CONTRACT NUMBER 5b.  GRANT NUMBER FA2386-15-1-4002 5c.  PROGRAM ELEMENT

Ideal Channel Field Effect Transistors

DTIC Science & Technology

2010-03-01

well as on /?-GaAs/w-GaAs homojunctions grown by molecular beam epitaxy (MBE). The diode I-Vs at reverse bias are plotted below. The measured breakdown...transistors and composite channel InAlAs/InGaAs/lnP/InAlAs high electron mobility transistors ( HEMTs ), which have taken the full advantage of the matched...result in a large number of dislocations in GaAs films epitaxially grown on wurtzite GaN. In this work, we have successfully integrated GaAs with GaN

Analysis of Proton Radiation Effects on Gallium Nitride High Electron Mobility Transistors

DTIC Science & Technology

2017-03-01

energy levels on a GaN-on-silicon high electron mobility transistor was created. Based on physical results of 2.0-MeV protons irradiation to fluence...and the physical device at 2.0-MeV proton irradiation , predictions were made for 5.0, 10.0, 20.0 and 40.0-MeV proton irradiation . The model generally...nitride, high electron mobility transistor, electronics, 2 MeV proton irradiation , radiation effects 15. NUMBER OF PAGES 87 16. PRICE CODE 17. SECURITY

JAN transistor and diode characterization test program

NASA Technical Reports Server (NTRS)

Takeda, H.

1977-01-01

A statistical summary of electrical characterization was performed on JAN diodes and transistors. Parameters are presented with test conditions, mean, standard deviation, lowest reading, 10% point, 90% point and highest reading.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

30 CFR 18.68 - Tests for intrinsic safety.

Code of Federal Regulations, 2014 CFR

2014-07-01

... normal use. (iii) Semiconductors shall be amply sized. Rectifiers and transistors shall be operated at... battery, or installed as close to the battery terminal as practicable. (3) Transistors of battery-operated...

Transferred substrate heterojunction bipolar transistors for submillimeter wave applications

NASA Technical Reports Server (NTRS)

Fung, A.; Samoska, L.; Siegel, P.; Rodwell, M.; Urteaga, M.; Paidi, V.

2003-01-01

We present ongoing work towards the development of submillimeter wave transistors with goals of realizing advanced high frequency amplifiers, voltage controlled oscillators, active multipliers, and traditional high-speed digital circuits.

Field-effect transistor improves electrometer amplifier

NASA Technical Reports Server (NTRS)

Munoz, R.

1964-01-01

An electrometer amplifier uses a field effect transistor to measure currents of low amperage. The circuit, developed as an ac amplifier, is used with an external filter which limits bandwidth to achieve optimum noise performance.

Computer-aided design of high-frequency transistor amplifiers.

NASA Technical Reports Server (NTRS)

Hsieh, C.-C.; Chan, S.-P.

1972-01-01

A systematic step-by-step computer-aided procedure for designing high-frequency transistor amplifiers is described. The technique makes it possible to determine the optimum source impedance which gives a minimum noise figure.

Silicon Carbide Transistor For Detecting Hydrocarbon Gases

NASA Technical Reports Server (NTRS)

Shields, Virgil B.; Ryan, Margaret A.; Williams, Roger M.

1996-01-01

Proposed silicon carbide variable-potential insulated-gate field-effect transistor specially designed for use in measuring concentrations of hydrocarbon gases. Devices like this prove useful numerous automotive, industrial, aeronautical, and environmental monitoring applications.

Quantum engineering of transistors based on 2D materials heterostructures

NASA Astrophysics Data System (ADS)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Low-frequency switching in a transistor amplifier.

PubMed

Carroll, T L

2003-04-01

It is known from extensive work with the diode resonator that the nonlinear properties of a P-N junction can lead to period doubling, chaos, and other complicated behaviors in a driven circuit. There has been very little work on what happens when more than one P-N junction is present. In this work, the first step towards multiple P-N junction circuits is taken by doing both experiments and simulations with a single-transistor amplifier using a bipolar transistor. Period doubling and chaos are seen when the amplifier is driven with signals between 100 kHz and 1 MHz, and they coincide with a very low frequency switching between different period doubled (or chaotic) wave forms. The switching frequencies are between 5 and 10 Hz. The switching behavior was confirmed in a simplified model of the transistor amplifier.

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

NASA Astrophysics Data System (ADS)

Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

2018-04-01

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

Molecular thermal transistor: Dimension analysis and mechanism

NASA Astrophysics Data System (ADS)

Behnia, S.; Panahinia, R.

2018-04-01

Recently, large challenge has been spent to realize high efficient thermal transistors. Outstanding properties of DNA make it as an excellent nano material in future technologies. In this paper, we introduced a high efficient DNA based thermal transistor. The thermal transistor operates when the system shows an increase in the thermal flux despite of decreasing temperature gradient. This is what called as negative differential thermal resistance (NDTR). Based on multifractal analysis, we could distinguish regions with NDTR state from non-NDTR state. Moreover, Based on dimension spectrum of the system, it is detected that NDTR state is accompanied by ballistic transport regime. The generalized correlation sum (analogous to specific heat) shows that an irregular decrease in the specific heat induces an increase in the mean free path (mfp) of phonons. This leads to the occurrence of NDTR.

Combinatorial study of zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

2008-01-01

Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

Noise characteristics of single-walled carbon nanotube network transistors.

PubMed

Kim, Un Jeong; Kim, Kang Hyun; Kim, Kyu Tae; Min, Yo-Sep; Park, Wanjun

2008-07-16

The noise characteristics of randomly networked single-walled carbon nanotubes grown directly by plasma enhanced chemical vapor deposition (PECVD) are studied with field effect transistors (FETs). Due to the geometrical complexity of nanotube networks in the channel area and the large number of tube-tube/tube-metal junctions, the inverse frequency, 1/f, dependence of the noise shows a similar level to that of a single single-walled carbon nanotube transistor. Detailed analysis is performed with the parameters of number of mobile carriers and mobility in the different environment. This shows that the change in the number of mobile carriers resulting in the mobility change due to adsorption and desorption of gas molecules (mostly oxygen molecules) to the tube surface is a key factor in the 1/f noise level for carbon nanotube network transistors.

Fabrication of metal nanopatterns for organic field effect transistor electrodes by cracking and transfer printing

NASA Astrophysics Data System (ADS)

Wang, Xiaonan; Fu, Tingting; Wang, Zhe

2018-04-01

In this paper, we demonstrate a novel method for fabricating metal nanopatterns using cracking to address the limitations of traditional techniques. Parallel crack arrays were created in a polydimethylsiloxane (PDMS) mold using a combination of surface modification and control of strain fields. The elastic PDMS containing the crack arrays was subsequently used as a stamp to prepare nanoscale metal patterns on a substrate by transfer printing. To illustrate the functionality of this technique, we employed the metal patterns as the source and drain contacts of an organic field effect transistor. Using this approach, we fabricated transistors with channel lengths ranging from 70-600 nm. The performance of these devices when the channel length was reduced was studied. The drive current density increases as expected, indicating the creation of operational transistors with recognizable properties.

Four quadrant control circuit for a brushless three-phase dc motor

NASA Technical Reports Server (NTRS)

Nola, Frank J. (Inventor)

1987-01-01

A control circuit is provided for a brushless three-phase dc motor which affords four quadrant control from a single command. The control circuit probes acceleration of the motor in both clockwise and counterclockwise directions and braking and generation in both clockwise and counterclockwise directions. In addition to turning on individual transistors of the transistor pairs connected to the phase windings of the motor for 120 deg periods while the other transistor of that pair is off, the control circuit also provides, in a future mode of operation, turning the two transistors of each pair on and off alternately at a phase modulation frequency during such a 120 deg period. A feedback signal is derived which is proportional to the motor current and which has a polarity consistent with the command signal, such that negative feedback results.

Low-Temperature, Solution-Processed, Transparent Zinc Oxide-Based Thin-Film Transistors for Sensing Various Solvents

PubMed Central

You, Hsin-Chiang; Wang, Cheng-Jyun

2017-01-01

A low temperature solution-processed thin-film transistor (TFT) using zinc oxide (ZnO) film as an exposed sensing semiconductor channel was fabricated to detect and identify various solution solvents. The TFT devices would offer applications for low-cost, rapid and highly compatible water-soluble detection and could replace conventional silicon field effect transistors (FETs) as bio-sensors. In this work, we demonstrate the utility of the TFT ZnO channel to sense various liquids, such as polar solvents (ethanol), non-polar solvents (toluene) and deionized (DI) water, which were dropped and adsorbed onto the channel. It is discussed how different dielectric constants of polar/non-polar solvents and DI water were associated with various charge transport properties, demonstrating the main detection mechanisms of the thin-film transistor. PMID:28772592

Advanced technology component derating

NASA Astrophysics Data System (ADS)

Jennings, Timothy A.

1992-02-01

A technical study performed to determine the derating criteria of advanced technology components is summarized. The study covered existing criteria from AFSC Pamphlet 800-27 and the development of new criteria based on data, literature searches, and the use of advanced technology prediction methods developed in RADC-TR-90-72. The devices that were investigated were as follows: VHSIC, ASIC, MIMIC, Microprocessor, PROM, Power Transistors, RF Pulse Transistors, RF Multi-Transistor Packages, Photo Diodes, Photo Transistors, Opto-Electronic Couplers, Injection Laser Diodes, LED, Hybrid Deposited Film Resistors, Chip Resistors, and Capacitors and SAW devices. The results of the study are additional derating criteria that extend the range of AFSC Pamphlet 800-27. These data will be transitioned from the report to AFSC Pamphlet 800-27 for use by government and contractor personnel in derating electronics systems yielding increased safety margins and improved system reliability.

Field-induced strain degradation of AlGaN/GaN high electron mobility transistors on a nanometer scale

NASA Astrophysics Data System (ADS)

Lin, Chung-Han; Doutt, D. R.; Mishra, U. K.; Merz, T. A.; Brillson, L. J.

2010-11-01

Nanoscale Kelvin probe force microscopy and depth-resolved cathodoluminescence spectroscopy reveal an electronic defect evolution inside operating AlGaN/GaN high electron mobility transistors with degradation under electric-field-induced stress. Off-state electrical stress results in micron-scale areas within the extrinsic drain expanding and decreasing in electric potential, midgap defects increasing by orders-of-magnitude at the AlGaN layer, and local Fermi levels lowering as gate-drain voltages increase above a characteristic stress threshold. The pronounced onset of defect formation, Fermi level movement, and transistor degradation at the threshold gate-drain voltage of J. A. del Alamo and J. Joh [Microelectron. Reliab. 49, 1200 (2009)] is consistent with crystal deformation and supports the inverse piezoelectric model of high electron mobility transistor degradation.

Localized heating on silicon field effect transistors: device fabrication and temperature measurements in fluid.

PubMed

Elibol, Oguz H; Reddy, Bobby; Nair, Pradeep R; Dorvel, Brian; Butler, Felice; Ahsan, Zahab S; Bergstrom, Donald E; Alam, Muhammad A; Bashir, Rashid

2009-10-07

We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications.

Temperature dependence of ballistic mobility in a metamorphic InGaAs/InAlAs high electron mobility transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Jongkyong; Gang, Suhyun; Jo, Yongcheol

We have investigated the temperature dependence of ballistic mobility in a 100 nm-long InGaAs/InAlAs metamorphic high-electron-mobility transistor designed for millimeter-wavelength RF applications. To extract the temperature dependence of quasi-ballistic mobility, our experiment involves measurements of the effective mobility in the low-bias linear region of the transistor and of the collision-dominated Hall mobility using a gated Hall bar of the same epitaxial structure. The data measured from the experiment are consistent with that of modeled ballistic mobility based on ballistic transport theory. These results advance the understanding of ballistic transport in various transistors with a nano-scale channel length that is comparable tomore » the carrier's mean free path in the channel.« less

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application.

PubMed

Liang, Xuelei; Xia, Jiye; Dong, Guodong; Tian, Boyuan; Peng, Lianmao

2016-12-01

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

Quantum engineering of transistors based on 2D materials heterostructures.

PubMed

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain.

PubMed

Lee, Sungsik; Nathan, Arokia

2016-10-21

The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (<1 volt) and ultralow power (<1 nanowatt). By using a Schottky-barrier at the source and drain contacts, the current-voltage characteristics of the transistor were virtually channel-length independent with an infinite output resistance. It exhibited high intrinsic gain (>400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation. Copyright © 2016, American Association for the Advancement of Science.

Thermal transistor behavior of a harmonic chain

NASA Astrophysics Data System (ADS)

Kim, Sangrak

2017-09-01

Thermal transistor behavior of a harmonic chain with three heat reservoirs is explicitly analyzed. Temperature profile and heat currents of the rather general system are formulated and then heat currents for the simplest system are exactly calculated. The matrix connecting the three temperatures of the reservoirs and those of the particles comprises a stochastic matrix. The ratios R 1 and R 2 between heat currents, characterizing thermal signals can be expressed in terms of two external variables and two material parameters. It is shown that the ratios R 1 and R 2 can have wide range of real values. The thermal system shows a thermal transistor behavior such as the amplification of heat current by appropriately controlling the two variables and two parameters. We explicitly demonstrate the characteristics and mechanisms of thermal transistor with the simplest model.

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

Magnetic vortex based transistor operations.

PubMed

Kumar, D; Barman, S; Barman, A

2014-02-17

Transistors constitute the backbone of modern day electronics. Since their advent, researchers have been seeking ways to make smaller and more efficient transistors. Here, we demonstrate a sustained amplification of magnetic vortex core gyration in coupled two and three vortices by controlling their relative core polarities. This amplification is mediated by a cascade of antivortex solitons travelling through the dynamic stray field. We further demonstrated that the amplification can be controlled by switching the polarity of the middle vortex in a three vortex sequence and the gain can be controlled by the input signal amplitude. An attempt to show fan-out operation yielded gain for one of the symmetrically placed branches which can be reversed by switching the core polarity of all the vortices in the network. The above observations promote the magnetic vortices as suitable candidates to work as stable bipolar junction transistors (BJT).

Magnetic Vortex Based Transistor Operations

NASA Astrophysics Data System (ADS)

Kumar, D.; Barman, S.; Barman, A.

2014-02-01

Transistors constitute the backbone of modern day electronics. Since their advent, researchers have been seeking ways to make smaller and more efficient transistors. Here, we demonstrate a sustained amplification of magnetic vortex core gyration in coupled two and three vortices by controlling their relative core polarities. This amplification is mediated by a cascade of antivortex solitons travelling through the dynamic stray field. We further demonstrated that the amplification can be controlled by switching the polarity of the middle vortex in a three vortex sequence and the gain can be controlled by the input signal amplitude. An attempt to show fan-out operation yielded gain for one of the symmetrically placed branches which can be reversed by switching the core polarity of all the vortices in the network. The above observations promote the magnetic vortices as suitable candidates to work as stable bipolar junction transistors (BJT).

Negative differential transconductance in silicon quantum well metal-oxide-semiconductor field effect/bipolar hybrid transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naquin, Clint; Lee, Mark; Edwards, Hal

2014-11-24

Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (V{sub G}). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures >200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on V{sub G} that reduces drain-source current through the QW. These devices establish the feasibility ofmore » exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.« less

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Analysis of low-offset CTIA amplifier for small-size-pixel infrared focal plane array

NASA Astrophysics Data System (ADS)

Zhang, Xue; Huang, Zhangcheng; Shao, Xiumei

2014-11-01

The design of input stage amplifier becomes more and more difficult as the expansion of format arrays and reduction of pixel size. A design method of low-offset amplifier based on 0.18-μm process used in small-size pixel is analyzed in order to decrease the dark signal of extended wavelength InGaAs infrared focal plane arrays (IRFPA). Based on an example of a cascode operational amplifier (op-amp), the relationship between input offset voltage and size of each transistor is discussed through theoretical analysis and Monte Carlo simulation. The results indicate that input transistors and load transistors have great influence on the input offset voltage while common-gate transistors are negligible. Furthermore, the offset voltage begins to increase slightly when the width and length of transistors decrease along with the diminution of pixel size, and raises rapidly when the size is smaller than a proximate threshold value. The offset voltage of preamplifiers with differential architecture and single-shared architecture in small pitch pixel are studied. After optimization under same conditions, simulation results show that single-shared architecture has smaller offset voltage than differential architecture.

Current-Induced Transistor Sensorics with Electrogenic Cells

PubMed Central

Fromherz, Peter

2016-01-01

The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned. PMID:27120627

A pattern recognition approach to transistor array parameter variance

NASA Astrophysics Data System (ADS)

da F. Costa, Luciano; Silva, Filipi N.; Comin, Cesar H.

2018-06-01

The properties of semiconductor devices, including bipolar junction transistors (BJTs), are known to vary substantially in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters. All in all, this work yielded interesting results from both semiconductor engineering and pattern recognition perspectives.

VO2-based radiative thermal transistor with a semi-transparent base

NASA Astrophysics Data System (ADS)

Prod'homme, Hugo; Ordonez-Miranda, Jose; Ezzahri, Younès; Drévillon, Jérémie; Joulain, Karl

2018-05-01

We study a radiative thermal transistor analogous to an electronic one made of a VO2 base placed between two silica semi-infinite plates playing the roles of the transistor collector and emitter. The fact that VO2 exhibits an insulator to metal transition is exploited to modulate and/or amplify heat fluxes between the emitter and the collector, by applying a thermal current on the VO2 base. We extend the work of precedent studies considering the case where the base can be semi-transparent so that heat can be exchanged directly between the collector and the emitter. Both near and far field cases are considered leading to 4 typical regimes resulting from the fact that the emitter-base and base-collector separation distances can be larger or smaller than the thermal wavelength for a VO2 layer opaque or semi-transparent. Thermal currents variations with the base temperatures are calculated and analyzed. It is found that the transistor can operate in an amplification mode as already stated in [1] or in a switching mode as seen in [2]. An optimum configuration for the base thickness and separation distance maximizing the thermal transistor modulation factor is found.

Ambipolar pentacene field-effect transistor with double-layer organic insulator

NASA Astrophysics Data System (ADS)

Kwak, Jeong-Hun; Baek, Heume-Il; Lee, Changhee

2006-08-01

Ambipolar conduction in organic field-effect transistor is very important feature to achieve organic CMOS circuitry. We fabricated an ambipolar pentacene field-effect transistors consisted of gold source-drain electrodes and double-layered PMMA (Polymethylmethacrylate) / PVA (Polyvinyl Alcohol) organic insulator on the ITO(Indium-tin-oxide)-patterned glass substrate. These top-contact geometry field-effect transistors were fabricated in the vacuum of 10 -6 Torr and minimally exposed to atmosphere before its measurement and characterized in the vacuum condition. Our device showed reasonable p-type characteristics of field-effect hole mobility of 0.2-0.9 cm2/Vs and the current ON/OFF ratio of about 10 6 compared to prior reports with similar configurations. For the n-type characteristics, field-effect electron mobility of 0.004-0.008 cm2/Vs and the current ON/OFF ratio of about 10 3 were measured, which is relatively high performance for the n-type conduction of pentacene field-effect transistors. We attributed these ambipolar properties mainly to the hydroxyl-free PMMA insulator interface with the pentacene active layer. In addition, an increased insulator capacitance due to double-layer insulator structure with high-k PVA layer also helped us to observe relatively good n-type characteristics.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

A Novel SPM Probe with MOS Transistor and Nano Tip for Surface Electric Properties

NASA Astrophysics Data System (ADS)

Lee, Sang H.; Lim, Geunbae; Moon, Wonkyu

2007-03-01

In this paper, the novel SPM (Scanning Probe Microscope) probe with the planar MOS (Metal-Oxide-Semiconductor) transistor and the FIB (Focused Ion Beam) nano tip is fabricated for the surface electric properties. Since the MOS transistor has high working frequency, the device can overcome the speed limitation of EFM (Electrostatic Force Microscope) system. The sensitivity is also high, and no bulky device such as lock-in-amplifier is required. Moreover, the nano tip with nanometer scale tip radius is fabricated with FIB system, and the resolution can be improved. Therefore, the probe can rapidly detect small localized electric properties with high sensitivity and high resolution. The MOS transistor is fabricated with the common semiconductor process, and the nano tip is grown by the FIB system. The planar structure of the MOS transistor makes the fabrication process easier, which is the advantage on the commercial production. Various electric signals are applied using the function generator, and the measured data represent the well-established electric properties of the device. It shows the promising aspect of the local surface electric property detection with high sensitivity and high resolution.

Design, fabrication, and performance analysis of GaN vertical electron transistors with a buried p/n junction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeluri, Ramya, E-mail: ramyay@ece.ucsb.edu; Lu, Jing; Keller, Stacia

2015-05-04

The Current Aperture Vertical Electron Transistor (CAVET) combines the high conductivity of the two dimensional electron gas channel at the AlGaN/GaN heterojunction with better field distribution offered by a vertical design. In this work, CAVETs with buried, conductive p-GaN layers as the current blocking layer are reported. The p-GaN layer was regrown by metalorganic chemical vapor deposition and the subsequent channel regrowth was done by ammonia molecular beam epitaxy to maintain the p-GaN conductivity. Transistors with high ON current (10.9 kA/cm{sup 2}) and low ON-resistance (0.4 mΩ cm{sup 2}) are demonstrated. Non-planar selective area regrowth is identified as the limiting factormore » to transistor breakdown, using planar and non-planar n/p/n structures. Planar n/p/n structures recorded an estimated electric field of 3.1 MV/cm, while non-planar structures showed a much lower breakdown voltage. Lowering the p-GaN regrowth temperature improved breakdown in the non-planar n/p/n structure. Combining high breakdown voltage with high current will enable GaN vertical transistors with high power densities.« less

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

PubMed

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

PubMed Central

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Photosensitive graphene transistors.

PubMed

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Electrolyte-gated transistors based on phenyl-C61-butyric acid methyl ester (PCBM) films: bridging redox properties, charge carrier transport and device performance.

PubMed

Lan, Tian; Soavi, Francesca; Marcaccio, Massimo; Brunner, Pierre-Louis; Sayago, Jonathan; Santato, Clara

2018-05-24

The n-type organic semiconductor phenyl-C61-butyric acid methyl ester (PCBM), a soluble fullerene derivative well investigated for organic solar cells and transistors, can undergo several successive reversible, diffusion-controlled, one-electron reduction processes. We exploited such processes to shed light on the correlation between electron transfer properties, ionic and electronic transport as well as device performance in ionic liquid (IL)-gated transistors. Two ILs were considered, based on bis(trifluoromethylsulfonyl)imide [TFSI] as the anion and 1-ethyl-3-methylimidazolium [EMIM] or 1-butyl-1-methylpyrrolidinium [PYR14] as the cation. The aromatic structure of [EMIM] and its lower steric hindrance with respect to [PYR14] favor a 3D (bulk) electrochemical doping. As opposed to this, for [PYR14] the doping seems to be 2D (surface-confined). If the n-doping of the PCBM is pursued beyond the first electrochemical process, the transistor current vs. gate-source voltage plots in [PYR14][TFSI] feature a maximum that points to the presence of finite windows of high conductivity in IL-gated PCBM transistors.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Reversible and Precisely Controllable p/n-Type Doping of MoTe2 Transistors through Electrothermal Doping.

PubMed

Chang, Yuan-Ming; Yang, Shih-Hsien; Lin, Che-Yi; Chen, Chang-Hung; Lien, Chen-Hsin; Jian, Wen-Bin; Ueno, Keiji; Suen, Yuen-Wuu; Tsukagoshi, Kazuhito; Lin, Yen-Fu

2018-03-01

Precisely controllable and reversible p/n-type electronic doping of molybdenum ditelluride (MoTe 2 ) transistors is achieved by electrothermal doping (E-doping) processes. E-doping includes electrothermal annealing induced by an electric field in a vacuum chamber, which results in electron (n-type) doping and exposure to air, which induces hole (p-type) doping. The doping arises from the interaction between oxygen molecules or water vapor and defects of tellurium at the MoTe 2 surface, and allows the accurate manipulation of p/n-type electrical doping of MoTe 2 transistors. Because no dopant or special gas is used in the E-doping processes of MoTe 2 , E-doping is a simple and efficient method. Moreover, through exact manipulation of p/n-type doping of MoTe 2 transistors, quasi-complementary metal oxide semiconductor adaptive logic circuits, such as an inverter, not or gate, and not and gate, are successfully fabricated. The simple method, E-doping, adopted in obtaining p/n-type doping of MoTe 2 transistors undoubtedly has provided an approach to create the electronic devices with desired performance. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

More Efficient Power Conversion for EVs: Gallium-Nitride Advanced Power Semiconductor and Packaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

2010-02-01

Broad Funding Opportunity Announcement Project: Delphi is developing power converters that are smaller and more energy efficient, reliable, and cost-effective than current power converters. Power converters rely on power transistors which act like a very precisely controlled on-off switch, controlling the electrical energy flowing through an electrical circuit. Most power transistors today use silicon (Si) semiconductors. However, Delphi is using semiconductors made with a thin layer of gallium-nitride (GaN) applied on top of the more conventional Si material. The GaN layer increases the energy efficiency of the power transistor and also enables the transistor to operate at much higher temperatures,more » voltages, and power-density levels compared to its Si counterpart. Delphi is packaging these high-performance GaN semiconductors with advanced electrical connections and a cooling system that extracts waste heat from both sides of the device to further increase the device’s efficiency and allow more electrical current to flow through it. When combined with other electronic components on a circuit board, Delphi’s GaN power transistor package will help improve the overall performance and cost-effectiveness of HEVs and EVs.« less

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

NASA Astrophysics Data System (ADS)

Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

2009-12-01

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

NASA Astrophysics Data System (ADS)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by using a UV-Ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of strain sensors which maps the strain field on a PVDF film surface is demonstrated in this work. The strain sensor experience inspires a tone analyzer built using distributed resonator architecture on a tensioned piezoelectric PVDF sheet. This sheet is used as both the resonator and detection element. Two architectures are demonstrated; one uses distributed directly addressed elements as a proof of concept, and the other integrates organic thin film transistor-based transimpedance amplifiers monolithically with the PVDF sheet to convert the piezoelectric charge signal into a current signal for future applications such as sound field imaging. The PVDF sheet material is instrumented along its length and the amplitude response at 15 sites is recorded and analyzed as a function of the frequency of excitation. The determination of the dominant frequency component of an incoming sound is demonstrated using linear system decomposition of the time-averaged response of the sheet using no time domain detection. Our design allows for the determination of the spectral composition of a sound using the mechanical signal processing provided by the amplitude response and eliminates the need for time-domain electronic signal processing of the incoming signal. The concepts of the PVDF strain sensor and the tone analyzer trigger the idea of an active matrix microphone through the integration of organic thin film transistors with a freestanding piezoelectric polymer sheet. Localized acoustic pressure detection is enabled by switch transistors and local transimpedance amplification built into the active matrix architecture. The frequency of detection ranges from DC to 15KHz; the bandwidth is extended using an architecture that provides for virtually zero gate/source and gate/drain capacitance at the sensing transistors and low overlap capacitance at the switch transistors. A series of measurements are taken to demonstrate localized acoustic wave detection, high pitch sound diffraction pattern mapping, and directional listening. This system permits the direct visualization of a two dimensional sound field in a format that was previously inaccessible. In addition to the piezoelectric property, pyroelectricity is also exhibited by PVDF and is essential in the world of sensors. An integration of PVDF and OFET for the IR heat sensing is demonstrated to prove the concept of converting pyroelectric charge signal to a electric current signal. The basic pyroelectricity of PVDF sheet is first examined before making a organic transistor integrated IR sensor. Then, two types of architectures are designed and tested. The first one uses the structure similar to the PVDF strain sensor, and the second one uses a PVDF capacitor to gate the integrated OFETs. The conversion from pyroelectric signal to transistor current signal is observed and characterized. This design provides a flexible and gain-tunable version for IR heat sensors.

A Field-Effect Transistor (FET) model for ASAP

NASA Technical Reports Server (NTRS)

Ming, L.

1965-01-01

The derivation of the circuitry of a field effect transistor (FET) model, the procedure for adapting the model to automated statistical analysis program (ASAP), and the results of applying ASAP on this model are described.

U. H. F. Power Transistors and Lecher Line Oscillators.

ERIC Educational Resources Information Center

Howes, R. W.

1980-01-01

Describes the use of transistors instead of valves for Lecher line and radiation demonstrations. Two oscillator circuits which provide power for Lecher line use are described. Impedance of Lecher line is also discussed. (HM)

Teaching the Common Emitter Amplifier.

ERIC Educational Resources Information Center

Ellse, Mark D.

1984-01-01

Describes experiments in which a bipolar transistor is used to examine the behavior of a simple circuit. Also addresses problems in teaching the related concepts. (The experiments can be modified to incorporate devices other than bipolar transistors.) (JN)

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

Review of Heterojunctin Bipolar Transistor Structure, Applications, and Reliability

NASA Technical Reports Server (NTRS)

Lee, C.; Kayali, S.

1993-01-01

Heterojunction Bipolar Transistors (HBTs) are increasingly employed in high frequency, high linerity, and high efficiency applications. As the utilization of these devices becomes more widespread, their operation will be viewed with more scrutiny.

All diamond self-aligned thin film transistor

DOEpatents

Gerbi, Jennifer [Champaign, IL

2008-07-01

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Probing organic field effect transistors in situ during operation using SFG.

PubMed

Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

2006-05-24

In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

Ordered polymer nanofibers enhance output brightness in bilayer light-emitting field-effect transistors.

PubMed

Hsu, Ben B Y; Seifter, Jason; Takacs, Christopher J; Zhong, Chengmei; Tseng, Hsin-Rong; Samuel, Ifor D W; Namdas, Ebinazar B; Bazan, Guillermo C; Huang, Fei; Cao, Yong; Heeger, Alan J

2013-03-26

Polymer light emitting field effect transistors are a class of light emitting devices that reveal interesting device physics. Device performance can be directly correlated to the most fundamental polymer science. Control over surface properties of the transistor dielectric can dramatically change the polymer morphology, introducing ordered phase. Electronic properties such as carrier mobility and injection efficiency on the interface can be promoted by ordered nanofibers in the polymer. Moreover, by controlling space charge in the polymer interface, the recombination zone can be spatially extended and thereby enhance the optical output.

VHDL simulation with access to transistor models

NASA Technical Reports Server (NTRS)

Gibson, J.

1991-01-01

Hardware description languages such as VHDL have evolved to aid in the design of systems with large numbers of elements and a wide range of electronic and logical abstractions. For high performance circuits, behavioral models may not be able to efficiently include enough detail to give designers confidence in a simulation's accuracy. One option is to provide a link between the VHDL environment and a transistor level simulation environment. The coupling of the Vantage Analysis Systems VHDL simulator and the NOVA simulator provides the combination of VHDL modeling and transistor modeling.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Optical pulse generation in a transistor laser via intra-cavity photon-assisted tunneling and excess base carrier redistribution

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, M.; Iverson, E. W.; Wang, C. Y.

2015-11-02

For a direct-gap semiconductor (e.g., a p-n junction), photon-assisted tunneling is known to exhibit a high nonlinear absorption. In a transistor laser, as discussed here, the coherent photons generated at the quantum well interact with the collector junction field and “assist” electron tunneling from base to collector, thus resulting in the nonlinear modulation of the laser and the realization of optical pulse generation. 1 and 2 GHz optical pulses are demonstrated in the transistor laser using collector voltage control.

Growth front nucleation of rubrene thin films for high mobility organic transistors

NASA Astrophysics Data System (ADS)

Hsu, C. H.; Deng, J.; Staddon, C. R.; Beton, P. H.

2007-11-01

We demonstrate a mode of thin film growth in which amorphous islands crystallize into highly oriented platelets. A cascade of crystallization is observed, in which platelets growing outward from a central nucleation point impinge on neighboring amorphous islands and provide a seed for further nucleation. Through control of growth parameters, it is possible to produce high quality thin films which are well suited to the formation of organic transistors. We demonstrate this through the fabrication of rubrene thin film transistors with high carrier mobility.

Analytic model for low-frequency noise in nanorod devices.

PubMed

Lee, Jungil; Yu, Byung Yong; Han, Ilki; Choi, Kyoung Jin; Ghibaudo, Gerard

2008-10-01

In this work analytic model for generation of excess low-frequency noise in nanorod devices such as field-effect transistors are developed. In back-gate field-effect transistors where most of the surface area of the nanorod is exposed to the ambient, the surface states could be the major noise source via random walk of electrons for the low-frequency or 1/f noise. In dual gate transistors, the interface states and oxide traps can compete with each other as the main noise source via random walk and tunneling, respectively.

The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

NASA Technical Reports Server (NTRS)

Armstrong, C. Duane; Humphreys, William M.; Fijany, Amir

2002-01-01

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

Conjugated polymers and their use in optoelectronic devices

DOEpatents

Marks, Tobin J.; Guo, Xugang; Zhou, Nanjia; Chang, Robert P. H.; Drees, Martin; Facchetti, Antonio

2016-10-18

The present invention relates to certain polymeric compounds and their use as organic semiconductors in organic and hybrid optical, optoelectronic, and/or electronic devices such as photovoltaic cells, light emitting diodes, light emitting transistors, and field effect transistors. The present compounds can provide improved device performance, for example, as measured by power conversion efficiency, fill factor, open circuit voltage, field-effect mobility, on/off current ratios, and/or air stability when used in photovoltaic cells or transistors. The present compounds can have good solubility in common solvents enabling device fabrication via solution processes.

Fully transparent thin film transistors based on zinc oxide channel layer and molybdenum doped indium oxide electrodes

NASA Astrophysics Data System (ADS)

MÄ dzik, Mateusz; Elamurugu, Elangovan; Viegas, Jaime

2016-03-01

In this work we report the fabrication of thin film transistors (TFT) with zinc oxide channel and molybdenum doped indium oxide (IMO) electrodes, achieved by room temperature sputtering. A set of devices was fabricated, with varying channel width and length from 5μm to 300μm. Output and transfer characteristics were then extracted to study the performance of thin film transistors, namely threshold voltage and saturation current, enabling to determine optimal fabrication process parameters. Optical transmission in the UV-VIS-IR are also reported.

Electron transporting water-gated thin film transistors

NASA Astrophysics Data System (ADS)

Al Naim, Abdullah; Grell, Martin

2012-10-01

We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Overload protection circuit for output driver

DOEpatents

Stewart, Roger G.

1982-05-11

A protection circuit for preventing excessive power dissipation in an output transistor whose conduction path is connected between a power terminal and an output terminal. The protection circuit includes means for sensing the application of a turn on signal to the output transistor and the voltage at the output terminal. When the turn on signal is maintained for a period of time greater than a given period without the voltage at the output terminal reaching a predetermined value, the protection circuit decreases the turn on signal to, and the current conduction through, the output transistor.

A Staged Reading of the Play: W=S:Transistor Shock

NASA Astrophysics Data System (ADS)

2014-03-01

A university is offered funding, but only if they'll name a building for William Shockley. William Shockley was an American physicist and inventor who won the Nobel Prize for his work on the transistor, but was infamous for his support of eugenics. What do they do? Join us for a dramatic staged reading of Transistor Shock, a new play by Ivan K. Schuller and Adam J. Smith, performed by the Boulder Ensemble Theatre Company. After the performance, the director, actors, and playwrights will be available for audience discussion.

Detection of glutamate and acetylcholine with organic electrochemical transistors based on conducting polymer/platinum nanoparticle composites.

PubMed

Kergoat, Loïg; Piro, Benoît; Simon, Daniel T; Pham, Minh-Chau; Noël, Vincent; Berggren, Magnus

2014-08-27

The aim of the study is to open a new scope for organic electrochemical transistors based on PEDOT:PSS, a material blend known for its stability and reliability. These devices can leverage molecular electrocatalysis by incorporating small amounts of nano-catalyst during the transistor manufacturing (spin coating). This methodology is very simple to implement using the know-how of nanochemistry and results in efficient enzymatic activity transduction, in this case utilizing choline oxidase and glutamate oxidase. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of the Sensitivity, Selectivity, and Reversibility of the Chemically-Sensitive Field-Effect Transistor (CHEMFET) to Detect Nitrogen Dioxide, Dimethyl Methylphosphonate, and Boron Trifluoride

DTIC Science & Technology

1993-09-01

SENSITIVE FIELD- EFFECT TRANSISTOR (CHEMFET) TO DETECT NITROGEN DIOXIDE, DIMETHYL METHYLPHOSPHONATE, AND BORON TRIFLUORIDE CHAPTER 1 1 Introduction Our rapidly...AND REVERSIBILITY OF THE CHEMICALLY-SENSITIVE FIELD- EFFECT TRANSISTOR (CHEMFET) TO DETECT NITROGEN 3 E I1• DIOXIDE, DIMETHYL METHYLPHOSPHONATE, ELECTE...AND BORON TRIFLUORIDE Neal Terence Hauschild Second Lieutenant, USAF AFIT/GE/ENG/9 3S-10 93-23815I II11l11l11 l gll I 1i 1111 11 I DEPARTMENT OF THE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gelinck, G. H., E-mail: Gerwin.Gelinck@tno.nl; Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven; Breemen, A. J. J. M. van

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Silicone substrate with in situ strain relief for stretchable thin-film transistors

NASA Astrophysics Data System (ADS)

Graz, Ingrid M.; Cotton, Darryl P. J.; Robinson, Adam; Lacour, Stéphanie P.

2011-03-01

We have manufactured stretchable thin-film transistors and interconnects directly onto an engineered silicone matrix with localized and graded mechanical compliance. The fabrication only involves planar and standard processing. Brittle active device materials are patterned on non deformable elastomer regions (strain <1% at all times) while interconnects run smoothly from "stiff" to "soft" elastomer. Pentacene thin-film transistors sustain applied strain up to 13% without electrical degradation and mechanical fracture. This integrated approach opens promising options for the manufacture of physically adaptable and transformable circuitry.

Switching Characteristics of Ferroelectric Transistor Inverters

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

2010-01-01

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

Wavelength Division Multiplexing Scheme for Radio-Frequency Single Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, Thomas R.; Pellerano, F. A.; Stahle, C. M.; Aidala, K.; Schoelkopf, R. J.; Krebs, Carolyn (Technical Monitor)

2001-01-01

We describe work on a wavelength division multiplexing scheme for radio-frequency single electron transistors. We use a network of resonant impedance matching circuits to direct applied rf carrier waves to different transistors depending on carrier frequency. Using discrete components, we made a two-channel demonstration of this concept and successfully reconstructed input signals with small levels of cross coupling. A lithographic version of the rf circuits had measured parameters in agreement with electromagnetic modeling, with reduced cross capacitance and inductance, and should allow 20 to 50 channels to be multiplexed.

Controlling Chain Conformations of High-k Fluoropolymer Dielectrics to Enhance Charge Mobilities in Rubrene Single-Crystal Field-Effect Transistors.

PubMed

Adhikari, Jwala M; Gadinski, Matthew R; Li, Qi; Sun, Kaige G; Reyes-Martinez, Marcos A; Iagodkine, Elissei; Briseno, Alejandro L; Jackson, Thomas N; Wang, Qing; Gomez, Enrique D

2016-12-01

A novel photopatternable high-k fluoropolymer, poly(vinylidene fluoride-bromotrifluoroethylene) P(VDF-BTFE), with a dielectric constant (k) between 8 and 11 is demonstrated in thin-film transistors. Crosslinking P(VDF-BTFE) reduces energetic disorder at the dielectric-semiconductor interface by controlling the chain conformations of P(VDF-BTFE), thereby leading to approximately a threefold enhancement in the charge mobility of rubrene single-crystal field-effect transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Johnson, R. Wayne; Askew, Ray; Bromstead, James; Weir, Bennett

1991-01-01

The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter.

The use of harmonic analysis to investigate processes in irradiated transistor structures

NASA Astrophysics Data System (ADS)

Gnap, A. K.; Zaliubovskii, I. I.; Dakhov, V. M.; Pelikhatyi, N. M.; Filippenko, V. E.

A theoretical model is developed for analyzing the behavior of transistor structures under irradiation by high-energy particles. Specifically, attention is given to the operation of a transistor switch under irradiation by 2-MeV neutrons. The proposed approach involves the replacement of the actual voltage pulse by a trapezoidal pulse, and the application of harmonic analysis to the latter. The parameters of the actual pulse can then be determined from an analysis of the constant component of the signal and the value of one of its harmonics.

Transistor and memory devices based on novel organic and biomaterials

NASA Astrophysics Data System (ADS)

Tseng, Jia-Hung

Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with platinum nanoparticles. It is established that the effective barrier height in the materials systems needs to be further engineered in order to have sufficiently long retention times. Finally other novel architectures such as negative differential resistance devices and high density memory arrays are investigated for their influence on memory technology.

Interplay between Vacuum-Grown Monolayers of Alkylphosphonic Acids and the Performance of Organic Transistors Based on Dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene.

PubMed

Hannah, Stuart; Cardona, Javier; Lamprou, Dimitrios A; Šutta, Pavol; Baran, Peter; Al Ruzaiqi, Afra; Johnston, Karen; Gleskova, Helena

2016-09-28

Monolayers of six alkylphosphonic acids ranging from C8 to C18 were prepared by vacuum evaporation and incorporated into low-voltage organic field-effect transistors based on dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). Similar to solution-assembled monolayers, the molecular order for vacuum-deposited monolayers improved with increasing length of the aliphatic tail. At the same time, Fourier transform infrared (FTIR) measurements suggested lower molecular coverage for longer phosphonic acids. The comparison of FTIR and vibration frequencies calculated by density functional theory indicated that monodentate bonding does not occur for any phosphonic acid. All monolayers exhibited low surface energy of ∼17.5 mJ/m(2) with a dominating Lifshitz-van der Waals component. Their surface roughness was comparable, while the nanomechanical properties were varied but not correlated to the length of the molecule. However, large improvement in transistor performance was observed with increasing length of the aliphatic tail. Upon going from C8 to C18, the mean threshold voltage decreased from -1.37 to -1.24 V, the field-effect mobility increased from 0.03 to 0.33 cm(2)/(V·s), the off-current decreased from ∼8 × 10(-13) to ∼3 × 10(-13) A, and for transistors with L = 30 μm the on-current increased from ∼3 × 10(-8) to ∼2 × 10(-6) A, and the on/off-current ratio increased from ∼3 × 10(4) to ∼4 × 10(6). Similarly, transistors with longer phosphonic acids exhibited much better air and bias-stress stability. The achieved transistor performance opens up a completely "dry" fabrication route for ultrathin dielectrics and low-voltage organic transistors.

75 FR 30794 - Notice of Intent To Grant Exclusive Patent License; AmberWave Systems Corporation

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-02

..., power transistor devices, and power devices in the United States, the Government-owned inventions... amplifiers, radio frequency power transistor devices, and power devices and their use for the fabrication of...

Overload-protector/fault-indicator circuit

NASA Technical Reports Server (NTRS)

Paluka, J. R.; Moore, S. F.

1977-01-01

Circuit incorporates three-terminal current limiter (78M24) to increase overall reliability and to eliminate transistor burnouts resulting from shorted interconnection lines and other overloads. Fact-acting light emitting diodes across the limiters show status of transistor output circuits.

Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

1993-01-01

This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

DIRECT COUPLED AMPLIFIER

DOEpatents

Dandl, R.A.

1961-09-19

A transistor amplifier is designed for vyery small currents below 10/sup -8/ amperes. The filrst and second amplifier stages use unusual selected transistors in which the current amplification increases markedly for values of base current below 10/sup -6/ amperes.

77 FR 3386 - Export and Reexport License Requirements for Certain Microwave and Millimeter Wave Electronic...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-01-24

... electronic components. The two components are packaged high electron mobility transistors and packaged..., 2012, FR Doc. 2012- 135). The two components are packaged high electron mobility transistors (HEMT) and...

MOSFET's for Cryogenic Amplifiers

NASA Technical Reports Server (NTRS)

Dehaye, R.; Ventrice, C. A.

1987-01-01

Study seeks ways to build transistors that function effectively at liquid-helium temperatures. Report discusses physics of metaloxide/semiconductor field-effect transistors (MOSFET's) and performances of these devices at cryogenic temperatures. MOSFET's useful in highly sensitive cryogenic preamplifiers for infrared astronomy.

Development of paper-gate transistor toward direct detection from microbiological fluids

NASA Astrophysics Data System (ADS)

Kajisa, Taira; Sakata, Toshiya

2017-04-01

In this study, a paper-gate transistor was developed to detect glucose using an extended-gate field-effect transistor (FET). A filter paper was used as an extended gate electrode, in which Au nanoparticles (AuNPs) modified with phenylboronic acids (PBAs) were included. PBA-AuNPs play an important role as a support to not only be entrapped in cellulose fibrils but also bind to the targeted glucose in a paper. The surface properties of PBA-AuNPs were investigated to elucidate the electrical properties of the paper-gate electrode using an absorption spectrum and a zeta potential analysis. Moreover, the paper-gate electrode enabled us to detect glucose at the micromolar level on the basis of the principle of FET devices. A platform based on the paper-gate transistor is suitable for a highly sensitive system to detect glucose in trace samples such as tears, sweat, and saliva in the future.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

PubMed Central

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

Organic Power Electronics: Transistor Operation in the kA/cm2 Regime

PubMed Central

Klinger, Markus P.; Fischer, Axel; Kaschura, Felix; Widmer, Johannes; Kheradmand-Boroujeni, Bahman; Ellinger, Frank; Leo, Karl

2017-01-01

In spite of interesting features as flexibility, organic thin-film transistors have commercially lagged behind due to the low mobilities of organic semiconductors associated with hopping transport. Furthermore, organic transistors usually have much larger channel lengths than their inorganic counterparts since high-resolution structuring is not available in low-cost production schemes. Here, we present an organic permeable-base transistor (OPBT) which, despite extremely simple processing without any high-resolution structuring, achieve a performance beyond what has so far been possible using organic semiconductors. With current densities above 1 kA cm−2 and switching speeds towards 100 MHz, they open the field of organic power electronics. Finding the physical limits and an effective mobility of only 0.06 cm2 V−1 s−1, this OPBT device architecture has much more potential if new materials optimized for its geometry will be developed. PMID:28303924

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

PubMed

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

PubMed

Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

2018-03-06

Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, C.; Li, J.; Song, X. B.

2016-01-04

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density I{sub ds} of 4.2 A/mm, and a peak transconductance g{sub m} of 2880 mS/mm. Intrinsic current-gain cutoff frequency f{sub T} of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standingmore » bilayer epitaxial graphene transistor show the great application potential of this material system.« less

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

PubMed

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

A light-stimulated synaptic transistor with synaptic plasticity and memory functions based on InGaZnO{sub x}–Al{sub 2}O{sub 3} thin film structure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, H. K.; Chen, T. P., E-mail: echentp@ntu.edu.sg; Liu, P.

In this work, a synaptic transistor based on the indium gallium zinc oxide (IGZO)–aluminum oxide (Al{sub 2}O{sub 3}) thin film structure, which uses ultraviolet (UV) light pulses as the pre-synaptic stimulus, has been demonstrated. The synaptic transistor exhibits the behavior of synaptic plasticity like the paired-pulse facilitation. In addition, it also shows the brain's memory behaviors including the transition from short-term memory to long-term memory and the Ebbinghaus forgetting curve. The synapse-like behavior and memory behaviors of the transistor are due to the trapping and detrapping processes of the holes, which are generated by the UV pulses, at the IGZO/Al{submore » 2}O{sub 3} interface and/or in the Al{sub 2}O{sub 3} layer.« less

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures.

PubMed

Yan, Xiao; Zhang, David Wei; Liu, Chunsen; Bao, Wenzhong; Wang, Shuiyuan; Ding, Shijin; Zheng, Gengfeng; Zhou, Peng

2018-04-01

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS 2 /GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Pseudo-diode based on protonic/electronic hybrid oxide transistor

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Polarization dependent photo-induced bias stress effect in organic transistors.

NASA Astrophysics Data System (ADS)

Podzorov, Vitaly; Choi, Hyun Ho; Najafov, Hikmet; Saranin, Danila; Kharlamov, Nikolai A.; Kuznetzov, Denis V.; Didenko, Sergei I.; Cho, Kilwon; Briseno, Alejandro L.; Rutgers-Misis Collaboration; Ru-P Collaboration; Ru-Um Collaboration; Um-P Collaboration

Photo-induced charge transfer between a semiconductor and a gate insulator that occurs in organic transistors operating under illumination leads to a shift of the onset gate voltage in these devices. Here we report an observation of a polarization dependent photo-induced bias-stress effect in two prototypical single-crystal organic field-effect transistors, based on rubrene and TPBIQ. We find that the rate of the effect is a periodic function of polarization angle of a linearly polarized photoexcitation, with a periodicity of π. The observed phenomenon provides an effective tool for addressing the relationship between molecular packing and parameter drift in organic transistors under illumination. The work was carried out with financial support from the Ministry of Education and Science of the Russian Federation in the framework of Increase Competitiveness Program of NUST «MISiS» (No. K3-2016-004), by gov. decree 16/03/2013, N 211.

Planar edge Schottky barrier-tunneling transistors using epitaxial graphene/SiC junctions.

PubMed

Kunc, Jan; Hu, Yike; Palmer, James; Guo, Zelei; Hankinson, John; Gamal, Salah H; Berger, Claire; de Heer, Walt A

2014-09-10

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Elimination of current spikes in buck power converters

NASA Technical Reports Server (NTRS)

Mclyman, W. T. (Inventor)

1981-01-01

Current spikes in a buck power converter due to commutating diode turn-off time are eliminated by using a tapped inductor in the converter with the tap connected to the switching transistor. The commutating diode is not in the usual place, but is instead connected to conduct current from one end of the tapped inductor remote from the load during the interval in which the transistor is not conducting. In the case of a converter having a center-tapped (primary and secondary) transformer between two switching power transistors operated in a push-pull mode and two rectifying diodes in the secondary circuit, current spikes due to transformer saturation are also eliminated by using a tapped inductor in the converter with the tap connected to the rectifying diodes and a diode connected to conduct current from one end of the tapped inductor remote from the load during the interval in which the transistors are not conducting.

Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

NASA Astrophysics Data System (ADS)

Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

Electrically controlled wire-channel GaN/AlGaN transistor for terahertz plasma applications

NASA Astrophysics Data System (ADS)

Cywiński, G.; Yahniuk, I.; Kruszewski, P.; Grabowski, M.; Nowakowski-Szkudlarek, K.; Prystawko, P.; Sai, P.; Knap, W.; Simin, G. S.; Rumyantsev, S. L.

2018-03-01

We report on a design of fin-shaped channel GaN/AlGaN field-effect transistors developed for studying resonant terahertz plasma oscillations. Unlike common two dimensional FinFET transistor design, the gates were deposited only to the sides of the two dimensional electron gas channel, i.e., metal layers were not deposited on the top of the AlGaN. This side gate configuration allowed us to electrically control the conductivity of the channel by changing its width while keeping the carrier density and mobility virtually unchanged. Computer simulations and analytical model describe well the general shape of the characteristics. The side gate control of the channel width of these transistors allowed us to eliminate the so-called oblique plasma wave modes and paves the way towards future terahertz detectors and emitters using high quality factor plasma wave resonances.