Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

PubMed

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

PubMed Central

Penumatcha, Ashish V.; Salazar, Ramon B.; Appenzeller, Joerg

2015-01-01

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses. PMID:26563458

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

NASA Technical Reports Server (NTRS)

Rafferty, Connor S.; Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario G.; Bude, J.; Dutton, Robert W.; Saini, Subhash (Technical Monitor)

1998-01-01

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Electron transporting water-gated thin film transistors

NASA Astrophysics Data System (ADS)

Al Naim, Abdullah; Grell, Martin

2012-10-01

We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

Looking for Speed!! Go Optical Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin; Frazier, Donald O.; Penn, Benjamin; Paley, Mark S.

2003-01-01

Recently, we developed two ultra-fast all-optical switches in the nanosecond and picosecond regimes. The picosecond switch is made of a polydiacetylene thin film coated on the interior wall of a hollow capillary of approximately 50 micron diameter by a photo-polymerization process. In the setup a picosecond Nd:YAG laser at 10 Hz and at 532 nm with a pulse duration of approximately 40 ps was sent collinearly along a cw He-Ne laser beam and both were waveguided through the hollow capillary. The setup functioned as an Exclusive OR gate. On the other hand, the material used in the nanosecond switch is a phthalocyanine thin film, deposited on a glass substrate by a vapor deposition technique. In the setup a nanosecond, 10 Hz, Nd:YAG laser of 8 ns pulse duration was sent collinearly along a cw He-Ne laser beam and both were wave-guided through the phthalocyanine thin film. The setup in this case functioned as an all-optical AND logic gate. The characteristic table of the ExOR gate in polydiacetylene film was attributed to an excited state absorption process, while that of the AND gate was attributed to a saturation process of the first excited state. Both mechanisms were thoroughly investigated theoretically and found to agree remarkably well with the experimental results. An all-optical inverter gate has been designed but has not yet been demonstrated. The combination of all these three gates form the foundation for building all the necessary gates needed to build a prototype of an all-optical system.

TOPICAL REVIEW: Ultra-thin film encapsulation processes for micro-electro-mechanical devices and systems

NASA Astrophysics Data System (ADS)

Stoldt, Conrad R.; Bright, Victor M.

2006-05-01

A range of physical properties can be achieved in micro-electro-mechanical systems (MEMS) through their encapsulation with solid-state, ultra-thin coatings. This paper reviews the application of single source chemical vapour deposition and atomic layer deposition (ALD) in the growth of submicron films on polycrystalline silicon microstructures for the improvement of microscale reliability and performance. In particular, microstructure encapsulation with silicon carbide, tungsten, alumina and alumina-zinc oxide alloy ultra-thin films is highlighted, and the mechanical, electrical, tribological and chemical impact of these overlayers is detailed. The potential use of solid-state, ultra-thin coatings in commercial microsystems is explored using radio frequency MEMS as a case study for the ALD alloy alumina-zinc oxide thin film.

Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

DOE PAGES

Leng, X.; Bozovic, I.; Bollinger, A. T.

2016-08-10

Epitaxial indium tin oxide films have been grown on both LaAlO 3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers amore » pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

PubMed Central

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-01-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process. PMID:27184121

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

NASA Astrophysics Data System (ADS)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Electronic structure evolution in doping of fullerene (C{sub 60}) by ultra-thin layer molybdenum trioxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Chenggong; Wang, Congcong; Kauppi, John

2015-08-28

Ultra-thin layer molybdenum oxide doping of fullerene has been investigated using ultraviolet photoemission spectroscopy (UPS) and X-ray photoemission spectroscopy (XPS). The highest occupied molecular orbital (HOMO) can be observed directly with UPS. It is observed that the Fermi level position in fullerene is modified by ultra-thin-layer molybdenum oxide doping, and the HOMO onset is shifted to less than 1.3 eV below the Fermi level. The XPS results indicate that charge transfer was observed from the C{sub 60} to MoO{sub x} and Mo{sup 6+} oxides is the basis as hole dopants.

Instability analysis of charges trapped in the oxide of metal-ultra thin oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Aziz, A.; Kassmi, K.; Maimouni, R.; Olivié, F.; Sarrabayrouse, G.; Martinez, A.

2005-09-01

In this paper, we present the theoretical and experimental results of the influence of a charge trapped in ultra-thin oxide of metal/ultra-thin oxide/semiconductor structures (MOS) on the I(Vg) current-voltage characteristics when the conduction is of the Fowler-Nordheim (FN) tunneling type. The charge, which is negative, is trapped near the cathode (metal/oxide interface) after constant current injection by the metal (Vg<0). Of particular interest is the influence on the Δ Vg(Vg) shift over the whole I(Vg) characteristic at high field (greater than the injection field (>12.5 MV/cm)). It is shown that the charge centroid varies linearly with respect to the voltage Vg. The behavior at low field (<12.5 MV/cm) is analyzed in référence A. Aziz, K. Kassmi, Ka. Kassmi, F. Olivié, Semicond. Sci. Technol. 19, 877 (2004) and considers that the trapped charge centroid is fixed. The results obtained make it possible to analyze the influence of the injected charge and the applied field on the centroid position of the trapped charge, and to highlight the charge instability in the ultra-thin oxide of MOS structures.

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Priyanka; Sahu, P. K.

2016-01-01

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

PubMed

Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

2013-06-11

We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO2/Si interfaces with low defect densities

NASA Astrophysics Data System (ADS)

Stegemann, Bert; Gad, Karim M.; Balamou, Patrice; Sixtensson, Daniel; Vössing, Daniel; Kasemann, Martin; Angermann, Heike

2017-02-01

Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO2/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO2/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO2/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO2/Si interfaces have been shown to generate less interface defect states.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Charge injection from gate electrode by simultaneous stress of optical and electrical biases in HfInZnO amorphous oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kwon, Dae Woong; Kim, Jang Hyun; Chang, Ji Soo; Kim, Sang Wan; Sun, Min-Chul; Kim, Garam; Kim, Hyun Woo; Park, Jae Chul; Song, Ihun; Kim, Chang Jung; Jung, U. In; Park, Byung-Gook

2010-11-01

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

Structural and electrical properties of single crystalline SrZrO3 epitaxially grown on Ge (001)

NASA Astrophysics Data System (ADS)

Lim, Z. H.; Ahmadi-Majlan, K.; Grimley, E. D.; Du, Y.; Bowden, M.; Moghadam, R.; LeBeau, J. M.; Chambers, S. A.; Ngai, J. H.

2017-08-01

We present structural and electrical characterization of SrZrO3 that has been epitaxially grown on Ge(001) by oxide molecular beam epitaxy. Single crystalline SrZrO3 can be nucleated on Ge via deposition at low temperatures followed by annealing at 550 °C in ultra-high vacuum. Photoemission spectroscopy measurements reveal that SrZrO3 exhibits a type-I band arrangement with respect to Ge, with conduction and valence band offsets of 1.4 eV and 3.66 eV, respectively. Capacitance-voltage and current-voltage measurements on 4 nm thick films reveal low leakage current densities and an unpinned Fermi level at the interface that allows modulation of the surface potential of Ge. Ultra-thin films of epitaxial SrZrO3 can thus be explored as a potential gate dielectric for Ge.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

Charge transfer from an adsorbed ruthenium-based photosensitizer through an ultra-thin aluminium oxide layer and into a metallic substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gibson, Andrew J.; Temperton, Robert H.; Handrup, Karsten

2014-06-21

The interaction of the dye molecule N3 (cis-bis(isothiocyanato)bis(2,2-bipyridyl-4,4′-dicarbo-xylato) -ruthenium(II)) with the ultra-thin oxide layer on a AlNi(110) substrate, has been studied using synchrotron radiation based photoelectron spectroscopy, resonant photoemission spectroscopy, and near edge X-ray absorption fine structure spectroscopy. Calibrated X-ray absorption and valence band spectra of the monolayer and multilayer coverages reveal that charge transfer is possible from the molecule to the AlNi(110) substrate via tunnelling through the ultra-thin oxide layer and into the conduction band edge of the substrate. This charge transfer mechanism is possible from the LUMO+2 and 3 in the excited state but not from the LUMO,more » therefore enabling core-hole clock analysis, which gives an upper limit of 6.0 ± 2.5 fs for the transfer time. This indicates that ultra-thin oxide layers are a viable material for use in dye-sensitized solar cells, which may lead to reduced recombination effects and improved efficiencies of future devices.« less

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of Inmore » metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.« less

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Structural, electronic and chemical properties of metal/oxide and oxide/oxide interfaces and thin film structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lad, Robert J.

1999-12-14

This project focused on three different aspects of oxide thin film systems: (1) Model metal/oxide and oxide/oxide interface studies were carried out by depositing ultra-thin metal (Al, K, Mg) and oxide (MgO, AlO{sub x}) films on TiO{sub 2}, NiO and {alpha}-Al{sub 2}O{sub 3} single crystal oxide substrates. (2) Electron cyclotron resonance (ECR) oxygen plasma deposition was used to fabricate AlO{sub 3} and ZrO{sub 2} films on sapphire substrates, and film growth mechanisms and structural characteristics were investigated. (3) The friction and wear characteristics of ZrO{sub 2} films on sapphire substrates in unlubricated sliding contact were studied and correlated with filmmore » microstructure. In these studies, thin film and interfacial regions were characterized using diffraction (RHEED, LEED, XRD), electron spectroscopies (XPS, UPS, AES), microscopy (AFM) and tribology instruments (pin-on-disk, friction microprobe, and scratch tester). By precise control of thin film microstructure, an increased understanding of the structural and chemical stability of interface regions and tribological performance of ultra-thin oxide films was achieved in these important ceramic systems.« less

Stable indium oxide thin-film transistors with fast threshold voltage recovery

NASA Astrophysics Data System (ADS)

Vygranenko, Yuriy; Wang, Kai; Nathan, Arokia

2007-12-01

Stable thin-film transistors (TFTs) with semiconducting indium oxide channel and silicon dioxide gate dielectric were fabricated by reactive ion beam assisted evaporation and plasma-enhanced chemical vapor deposition. The field-effect mobility is 3.3cm2/Vs, along with an on/off current ratio of 106, and subthreshold slope of 0.5V/decade. When subject to long-term gate bias stress, the TFTs show fast recovery of the threshold voltage (VT) when relaxed without annealing, suggesting that charge trapping at the interface and/or in the bulk gate dielectric to be the dominant mechanism underlying VT instability. Device performance and stability make indium oxide TFTs promising for display applications.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

Development of an ultra-thin film comprised of a graphene membrane and carbon nanotube vein support.

PubMed

Lin, Xiaoyang; Liu, Peng; Wei, Yang; Li, Qunqing; Wang, Jiaping; Wu, Yang; Feng, Chen; Zhang, Lina; Fan, Shoushan; Jiang, Kaili

2013-01-01

Graphene, exhibiting superior mechanical, thermal, optical and electronic properties, has attracted great interest. Considering it being one-atom-thick, and the reduced mechanical strength at grain boundaries, the fabrication of large-area suspended chemical vapour deposition graphene remains a challenge. Here we report the fabrication of an ultra-thin free-standing carbon nanotube/graphene hybrid film, inspired by the vein-membrane structure found in nature. Such a square-centimetre-sized hybrid film can realize the overlaying of large-area single-layer chemical vapour deposition graphene on to a porous vein-like carbon nanotube network. The vein-membrane-like hybrid film, with graphene suspended on the carbon nanotube meshes, possesses excellent mechanical performance, optical transparency and good electrical conductivity. The ultra-thin hybrid film features an electron transparency close to 90%, which makes it an ideal gate electrode in vacuum electronics and a high-performance sample support in transmission electron microscopy.

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

NASA Astrophysics Data System (ADS)

Huang, Cheng-Ying

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal- oxide-semiconductor ?eld-e?ect transistors (MOSFETs) are promising candidates for replacing Si-based MOSFETs for future very-large-scale integration (VLSI) logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower VDD and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current and low standby power consumption. In this dissertation, we will report InGaAs/InAs ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in InGaAs/InAs MOSFETs are reported as described below. 1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match to InP by molecular beam epitaxy (MBE), and studied the electron transport in In0.53Ga0.47As/AlAs 0.44Sb0.56 heterostructures. The InGaAs channel MOSFETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52 Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage. 2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (t ch ~ 2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current. 3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The raised InGaAs source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing BTBT leakage. With further replacement of raised InGaAs spacers by recessed, doping-graded InP spacers at high field regions, BTBT leakage can be reduced ~100:1. Using the above-mentioned techniques, record high performance InAs MOSFETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstrated with Ion = 500 microA/microm at Ioff = 100 nA/microm and VDS =0.5 V, showing the highest on-state performance among all the III-V MOSFETs and comparable performance to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InP source/drain spacers were also demonstrated with minimum I off = 60 pA/microm at 30 nm-Lg , and Ion = 150 microA/microm at I off = 1 nA/microm and VDS =0.5 V. This recessed InP source/drain spacer technique improves device scalability and enables III-V MOSFETs for low standby power logic applications. Furthermore, ultra-thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting high yield and high transconductance gm ~2.0 mS/microm at 20 nm- Lg and VDS =0.5 V. With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown maximum Ion/Ioff ratio ~8.3x105 , confirming that III-V MOSFETs are scalable to sub-10-nm technology nodes.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

PubMed

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

A unified physical model of Seebeck coefficient in amorphous oxide semiconductor thin-film transistors

NASA Astrophysics Data System (ADS)

Lu, Nianduan; Li, Ling; Sun, Pengxiao; Banerjee, Writam; Liu, Ming

2014-09-01

A unified physical model for Seebeck coefficient was presented based on the multiple-trapping and release theory for amorphous oxide semiconductor thin-film transistors. According to the proposed model, the Seebeck coefficient is attributed to the Fermi-Dirac statistics combined with the energy dependent trap density of states and the gate-voltage dependence of the quasi-Fermi level. The simulation results show that the gate voltage, energy disorder, and temperature dependent Seebeck coefficient can be well described. The calculation also shows a good agreement with the experimental data in amorphous In-Ga-Zn-O thin-film transistor.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Three dimensional graphene transistor for ultra-sensitive pH sensing directly in biological media.

PubMed

Ameri, Shideh Kabiri; Singh, Pramod K; Sonkusale, Sameer R

2016-08-31

In this work, pH sensing directly in biological media using three dimensional liquid gated graphene transistors is presented. The sensor is made of suspended network of graphene coated all around with thin layer of hafnium oxide (HfO2), showing high sensitivity and sensing beyond the Debye-screening limit. The performance of the pH sensor is validated by measuring the pH of isotonic buffered, Dulbecco's phosphate buffered saline (DPBS) solution, and of blood serum derived from Sprague-Dawley rat. The pH sensor shows high sensitivity of 71 ± 7 mV/pH even in high ionic strength media with molarities as high as 289 ± 1 mM. High sensitivity of this device is owing to suspension of three dimensional graphene in electrolyte which provides all around liquid gating of graphene, leading to higher electrostatic coupling efficiency of electrolyte to the channel and higher gating control of transistor channel by ions in the electrolyte. Coating graphene with hafnium oxide film (HfO2) provides binding sites for hydrogen ions, which results in higher sensitivity and sensing beyond the Debye-screening limit. The 3D graphene transistor offers the possibility of real-time pH measurement in biological media without the need for desaltation or sample preparation. Copyright © 2016 Elsevier B.V. All rights reserved.

Ultra-thin Oxide Membranes: Synthesis and Carrier Transport

NASA Astrophysics Data System (ADS)

Sim, Jai Sung

Self-supported freestanding membranes are films that are devoid of any underlying supporting layers. The key advantage of such structures is that, due to the lack of substrate effects - both mechanical and chemical, the true native properties of the material can be probed. This is crucial since many of the studies done on materials that are used as freestanding membranes are done as films clamped to substrates or in the bulk form. This thesis focuses on the synthesis and fabrication as well as electrical studies of free standing ultrathin < 40nm oxide membranes. It also is one of the first demonstrations for electrically probing nanoscale freestanding oxide membranes. Fabrication of such membranes is non-trivial as oxide materials are often brittle and difficult to handle. Therefore, it requires an understanding of thin plate mechanics coupled with controllable thin film deposition process. Taking things a step further, to electrically probe these membranes required design of complex device architecture and extensive optimization of nano-fabrication processes. The challenges and optimized fabrication method of such membranes are demonstrated. Three materials are probed in this study, VO2, TiO2, and CeO2. VO2 for understanding structural considerations for electronic phase change and nature of ionic liquid gating, TiO2 and CeO2 for understanding surface conduction properties and surface chemistry. The VO2 study shows shift in metal-insulator transition (MIT) temperature arising from stress relaxation and opening of the hysteresis. The ionic liquid gating studies showed reversible modulation of channel resistance and allowed distinguishing bulk process from the surface effects. Comparing the ionic liquid gating experiments to hydrogen doping experiments illustrated that ionic liquid gating can be a surface limited electrostatic effect, if the critical voltage threshold is not exceeded. TiO2 study shows creation of non-stoichiometric forms under ion milling. Utilizing focused ion beam milling, thin membranes of Ti xOy of 100-300 nm thickness have been created. TEM studies indicated polycrystallinity and presence of twins in the FIB-milled nanowalls. Compositional analysis in the transmission electron microscope also showed reduced content of oxygen, confirming non-stoichiometry. Temperature dependence of the electrical resistivity of the nanowall showed semiconducting behavior with an activation energy different from that of TiO2 single crystals and was attributed to formation of TinO2n-1 phases after FIB processing. The CeO2 study involved high temperature conductivity studies on substrate-free self-supported nano-crystalline ceria membranes up to 800 K. Increasing conductivity with oxygen partial pressure directly opposing the behavior of thin film devices 'clamped' by substrate has been observed. This illustrate that the relaxed nature of free standing membranes, and increased surface to volume ratio enables more sensitive electrical response to oxygen adsorption which could have implications for their use in oxygen storage devices, solid oxide fuel cells, and chemical sensors. The work in this thesis advances the understanding of materials in freestanding membrane form and advances fabrication techniques that have not been explored before, having implications for sensors, actuators, SOFC, memristors, and physics of quasi-2D materials.

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Positive Bias Instability of Bottom-Gate Zinc Oxide Thin-Film Transistors with a SiOx/SiNx-Stacked Gate Insulator

NASA Astrophysics Data System (ADS)

Furuta, Mamoru; Kamada, Yudai; Hiramatsu, Takahiro; Li, Chaoyang; Kimura, Mutsumi; Fujita, Shizuo; Hirao, Takashi

2011-03-01

The positive bias instabilities of the zinc oxide thin-film transistors (ZnO TFTs) with a SiOx/SiNx-stacked gate insulator have been investigated. The film quality of a gate insulator of SiOx, which forms an interface with the ZnO channel, was varied by changing the gas mixture ratio of SiH4/N2O/N2 during plasma-enhanced chemical vapor deposition. The positive bias stress endurance of ZnO TFT strongly depended on the deposition condition of the SiOx gate insulator. From the relaxations of the transfer curve shift after imposition of positive bias stress, transfer curves could not be recovered completely without any thermal annealing. A charge trapping in a gate insulator rather than that in bulk ZnO and its interface with a gate insulator is a dominant instability mechanism of ZnO TFTs under positive bias stress.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Surface passivation investigation on ultra-thin atomic layer deposited aluminum oxide layers for their potential application to form tunnel layer passivated contacts

NASA Astrophysics Data System (ADS)

Xin, Zheng; Ling, Zhi Peng; Nandakumar, Naomi; Kaur, Gurleen; Ke, Cangming; Liao, Baochen; Aberle, Armin G.; Stangl, Rolf

2017-08-01

The surface passivation performance of atomic layer deposited ultra-thin aluminium oxide layers with different thickness in the tunnel layer regime, i.e., ranging from one atomic cycle (∼0.13 nm) to 11 atomic cycles (∼1.5 nm) on n-type silicon wafers is studied. The effect of thickness and thermal activation on passivation performance is investigated with corona-voltage metrology to measure the interface defect density D it(E) and the total interface charge Q tot. Furthermore, the bonding configuration variation of the AlO x films under various post-deposition thermal activation conditions is analyzed by Fourier transform infrared spectroscopy. Additionally, poly(3,4-ethylenedioxythiophene) poly(styrene sulfonate) is used as capping layer on ultra-thin AlO x tunneling layers to further reduce the surface recombination current density to values as low as 42 fA/cm2. This work is a useful reference for using ultra-thin ALD AlO x layers as tunnel layers in order to form hole selective passivated contacts for silicon solar cells.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Understanding Metal-Insulator transitions in ultra-thin films of LaNiO3

NASA Astrophysics Data System (ADS)

Ravichandran, Jayakanth; King, Philip D. C.; Schlom, Darrell G.; Shen, Kyle M.; Kim, Philip

2014-03-01

LaNiO3 (LNO) is a bulk paramagnetic metal and a member of the family of RENiO3 Nickelates (RE = Rare Earth Metals), which is on the verge of the metal-insulator transition. Ultra-thin films of LNO has been studied extensively in the past and due to its sensitivity to disorder, the true nature of the metal-insulator transition in these films have been hard to decipher. We grow high quality ultra-thin films of LNO using reactive molecular beam epitaxy (MBE) and use a combination of ionic liquid gating and magneto-transport measurements to understand the nature and tunability of metal-insulator transition as a function of thickness for LNO. The underlying mechanisms for the transition are discussed in the framework of standard transport models. These results are discussed in the light of other Mott insulators such as Sr2IrO4, where we have performed similar measurements around the insulating state.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

Ion Sensitive Transparent-Gate Transistor for Visible Cell Sensing.

PubMed

Sakata, Toshiya; Nishimura, Kotaro; Miyazawa, Yuuya; Saito, Akiko; Abe, Hiroyuki; Kajisa, Taira

2017-04-04

In this study, we developed an ion-sensitive transparent-gate transistor (IS-TGT) for visible cell sensing. The gate sensing surface of the IS-TGT is transparent in a solution because a transparent amorphous oxide semiconductor composed of amorphous In-Ga-Zn-oxide (a-IGZO) with a thin SiO 2 film gate that includes an indium tin oxide (ITO) film as the source and drain electrodes is utilized. The pH response of the IS-TGT was found to be about 56 mV/pH, indicating approximately Nernstian response. Moreover, the potential signals of the IS-TGT for sodium and potassium ions, which are usually included in biological environments, were evaluated. The optical and electrical properties of the IS-TGT enable cell functions to be monitored simultaneously with microscopic observation and electrical measurement. A platform based on the IS-TGT can be used as a simple and cost-effective plate-cell-sensing system based on thin-film fabrication technology in the research field of life science.

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

NASA Astrophysics Data System (ADS)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable insights into the electrolyte-redox systems. In summary, this work provides fundamental insights into the interaction of redox-energy states with silicon substrate and realistic approaches for exploiting the unique properties of the molecules that may enable solutions for nanoscale high density, low-voltage, long retention and multiple bit memory applications.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Permanent and Transient Radiation Effects on Thin-Oxide (200-A) MOS Transistors

DTIC Science & Technology

1976-06-01

n-channel technology using a SiO, gate-oxide thickness ol ’ 200 A and a %hallow phiosphorus diffusion of 0.5 pin on a 0.7-ohm)-cmn 8-doped > Si...substrate. The thickness of the sell-aligned it polysilicon gate was kept at 3500 A. The oxide was grown in dry 0, at a temperature ot 1000C, followed...semiconductor work function difference (equal to 0 V for the polysilicon gates’ studied here). The effect of the ionizing radiation is to introduce

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

PubMed Central

Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-01-01

The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

PubMed

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Structural phase diagram for ultra-thin epitaxial Fe 3O 4 / MgO(0 01) films: thickness and oxygen pressure dependence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alraddadi, S.; Hines, W.; Yilmaz, T.

2016-02-19

A systematic investigation of the thickness and oxygen pressure dependence for the structural properties of ultra-thin epitaxial magnetite (Fe 3O 4) films has been carried out; for such films, the structural properties generally differ from those for the bulk when the thickness ≤10 nm. Iron oxide ultra-thin films with thicknesses varying from 3 nm to 20 nm were grown on MgO (001) substrates using molecular beam epitaxy under different oxygen pressures ranging from 1 × 10 -7 torr to 1 × 10 -5 torr. The crystallographic and electronic structures of the films were characterized using low energy electron diffraction (LEED)more » and x-ray photoemission spectroscopy (XPS), respectively. Moreover, the quality of the epitaxial Fe 3O 4 ultra-thin films was judged by magnetic measurements of the Verwey transition, along with complementary XPS spectra. We observed that under the same growth conditions the stoichiometry of ultra-thin films under 10 nm transforms from the Fe 3O 4 phase to the FeO phase. In this work, a phase diagram based on thickness and oxygen pressure has been constructed to explain the structural phase transformation. It was found that high-quality magnetite films with thicknesses ≤20 nm formed within a narrow range of oxygen pressure. An optimal and controlled growth process is a crucial requirement for the accurate study of the magnetic and electronic properties for ultra-thin Fe 3O 4 films. Furthermore, these results are significant because they may indicate a general trend in the growth of other oxide films, which has not been previously observed or considered.« less

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Rafferty, Conor S.; Yu, Zhiping; Dutton, Robert W.; Ancona, Mario G.; Saini, Subhash (Technical Monitor)

1998-01-01

We describe an electronic transport model and an implementation approach that respond to the challenges of device modeling for gigascale integration. We use the density-gradient (DG) transport model, which adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We present the current implementation of the DG model in PROPHET, a partial differential equation solver developed by Lucent Technologies. This implementation approach permits rapid development and enhancement of models, as well as run-time modifications and model switching. We show that even in typical bulk transport devices such as P-N diodes and BJTs, DG quantum effects can significantly modify the I-V characteristics. Quantum effects are shown to be even more significant in small, surface transport devices, such as sub-0.1 micron MOSFETs. In thin-oxide MOS capacitors, we find that quantum effects may reduce gate capacitance by 25% or more. The inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements. Significant quantum corrections also occur in the I-V characteristics of short-channel MOSFETs due to the gate capacitance correction.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

On the role of ultra-thin oxide cathode synthesis on the functionality of micro-solid oxide fuel cells: Structure, stress engineering and in situ observation of fuel cell membranes during operation

NASA Astrophysics Data System (ADS)

Lai, Bo-Kuai; Kerman, Kian; Ramanathan, Shriram

Microstructure and stresses in dense La 0.6Sr 0.4Co 0.8Fe 0.2O 3 (LSCF) ultra-thin films have been investigated to increase the physical thickness of crack-free cathodes and active area of thermo-mechanically robust micro-solid oxide fuel cell (μSOFC) membranes. Processing protocols employ low deposition rates to create a highly granular nanocrystalline microstructure in LSCF thin films and high substrate temperatures to produce linear temperature-dependent stress evolution that is dominated by compressive stresses in μSOFC membranes. Insight and trade-off on the synthesis are revealed by probing microstructure evolution and electrical conductivity in LSCF thin films, in addition to in situ monitoring of membrane deformation while measuring μSOFC performance at varying temperatures. From these studies, we were able to successfully fabricate failure-resistant square μSOFC (LSCF/YSZ/Pt) membranes with width of 250 μm and crack-free cathodes with thickness of ∼70 nm. Peak power density of ∼120 mW cm -2 and open circuit voltage of ∼0.6 V at 560 °C were achieved on a μSOFC array chip containing ten such membranes. Mechanisms affecting fuel cell performance are discussed. Our results provide fundamental insight to pathways of microstructure and stress engineering of ultra-thin, dense oxide cathodes and μSOFC membranes.

Aerosol-assisted chemical vapor deposition of ultra-thin CuOx films as hole transport material for planar perovskite solar cells

NASA Astrophysics Data System (ADS)

Zhang, Zhixin; Chen, Shuqun; Li, Pingping; Li, Hongyi; Wu, Junshu; Hu, Peng; Wang, Jinshu

This paper reports on the fabrication of CuOx films to be used as hole transporting layer (HTL) in CH3NH3PbI3 perovskite solar cells (PSCs). Ultra-thin CuOx coatings were grown onto FTO substrates for the first time via aerosol-assisted chemical vapor deposition (AACVD) of copper acetylacetonate in methanol. After incorporating into the PSCs prepared at ambient air, a highest power conversion efficiency (PCE) of 8.26% with HTL and of 3.34% without HTL were achieved. Our work represents an important step in the development of low-cost CVD technique for fabricating ultra-thin metal oxide functional layers in thin film photovoltaics.

A method to monitor the quality of ultra-thin nitride for trench DRAM with a buried strap structure

NASA Astrophysics Data System (ADS)

Wu, Yung-Hsien; Wang, Chun-Yao; Chang, Ian; Kao, Chien-Kang; Kuo, Chia-Ming; Ku, Alex

2007-02-01

A new approach to monitor the quality of an ultra-thin nitride film has been proposed. The nitride quality is monitored by observing the oxide thickness for the nitride film after wet oxidation since the resistance to oxidation strongly depends on its quality. To obtain a stable oxide thickness without interference from extrinsic factors for process monitoring, monitor wafers without dilute HF solution clean are suggested because the native-oxide containing surface is less sensitive to oxygen and therefore forms the nitride film with stable quality. In addition, the correlation between variable retention time (VRT) performance of a real dynamic random access memory (DRAM) product and oxide thickness from different nitride process temperatures can be successfully explained and this correlation can also be used to establish the appropriate oxide thickness range for process monitoring.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

NASA Astrophysics Data System (ADS)

Ahn, Min-Ju; Cho, Won-Ju

2017-10-01

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer's length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer's length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm-2eV-1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Fabrication of ultra thin anodic aluminium oxide membranes by low anodization voltages

NASA Astrophysics Data System (ADS)

Pastore, I.; Poplausks, R.; Apsite, I.; Pastare, I.; Lombardi, F.; Erts, D.

2011-06-01

Formation of ultrathin anodised aluminium oxide (AAO) membranes with high aspect ratio by Al anodization in sulphuric and oxalic acids at low potentials was investigated. Low anodization potentials ensure slow electrochemical reaction speeds and formation of AAO membranes with pore diameter and thickness below 20 nm and 70 nm respectively. Minimum time necessary for formation of continuous AAO membranes was determined. AAO membrane pore surface was covered with polymer Paraloid B72TM to transport it to the selected substrate. The fabricated ultra thin AAO membranes could be used to fabricate nanodot arrays on different surfaces.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario; Rafferty, Conor; Saini, Subhash (Technical Monitor)

1999-01-01

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals

NASA Astrophysics Data System (ADS)

Wei Shih, Chen; Chin, Albert; Fu Lu, Chun; Fang Su, Wei

2016-01-01

High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm2/Vs field-effect mobility, high ION/IOFF of 2.3 × 107, small 110 mV/dec sub-threshold slope, and a low VD of 2.5 V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals.

Remarkably high mobility ultra-thin-film metal-oxide transistor with strongly overlapped orbitals

PubMed Central

Wei Shih, Chen; Chin, Albert; Fu Lu, Chun; Fang Su, Wei

2016-01-01

High mobility channel thin-film-transistor (TFT) is crucial for both display and future generation integrated circuit. We report a new metal-oxide TFT that has an ultra-thin 4.5 nm SnO2 thickness for both active channel and source-drain regions, very high 147 cm2/Vs field-effect mobility, high ION/IOFF of 2.3 × 107, small 110 mV/dec sub-threshold slope, and a low VD of 2.5 V for low power operation. This mobility is already better than chemical-vapor-deposition grown multi-layers MoS2 TFT. From first principle quantum-mechanical calculation, the high mobility TFT is due to strongly overlapped orbitals. PMID:26744240

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Microgravity

NASA Image and Video Library

1999-11-10

Space Vacuum Epitaxy Center works with industry and government laboratories to develop advanced thin film materials and devices by utilizing the most abundant free resource in orbit: the vacuum of space. SVEC, along with its affiliates, is developing semiconductor mid-IR lasers for environmental sensing and defense applications, high efficiency solar cells for space satellite applications, oxide thin films for computer memory applications, and ultra-hard thin film coatings for wear resistance in micro devices. Performance of these vacuum deposited thin film materials and devices can be enhanced by using the ultra-vacuum of space for which SVEC has developed the Wake Shield Facility---a free flying research platform dedicated to thin film materials development in space.

Microgravity

NASA Image and Video Library

2000-11-10

Space Vacuum Epitaxy Center works with industry and government laboratories to develop advanced thin film materials and devices by utilizing the most abundant free resource in orbit: the vacuum of space. SVEC, along with its affiliates, is developing semiconductor mid-IR lasers for environmental sensing and defense applications, high efficiency solar cells for space satellite applications, oxide thin films for computer memory applications, and ultra-hard thin film coatings for wear resistance in micro devices. Performance of these vacuum deposited thin film materials and devices can be enhanced by using the ultra-vacuum of space for which SVEC has developed the Wake Shield Facility---a free flying research platform dedicated to thin film materials development in space.

Unusual instability mode of transparent all oxide thin film transistor under dynamic bias condition

NASA Astrophysics Data System (ADS)

Oh, Himchan; Hwang, Chi-Sun; Pi, Jae-Eun; Ki Ryu, Min; Ko Park, Sang-Hee; Yong Chu, Hye

2013-09-01

We report a degradation behavior of fully transparent oxide thin film transistor under dynamic bias stress which is the condition similar to actual pixel switching operation in active matrix display. After the stress test, drain current increased while the threshold voltage was almost unchanged. We found that shortening of effective channel length is leading cause of increase in drain current. Electrons activate the neutral donor defects by colliding with them during short gate-on period. These ionized donors are stabilized during the subsequent gate-off period due to electron depletion. This local increase in doping density reduces the channel length.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-mobility low-temperature ZnO transistors with low-voltage operation

NASA Astrophysics Data System (ADS)

Bong, Hyojin; Lee, Wi Hyoung; Lee, Dong Yun; Kim, Beom Joon; Cho, Jeong Ho; Cho, Kilwon

2010-05-01

Low voltage high mobility n-type thin film transistors (TFTs) based on sol-gel processed zinc oxide (ZnO) were fabricated using a high capacitance ion gel gate dielectric. The ion gel gated solution-processed ZnO TFTs were found to exhibit excellent electrical properties. TFT carrier mobilities were 13 cm2/V s, ON/OFF current ratios were 105, regardless of the sintering temperature used for the preparation of the ZnO thin films. Ion gel gated ZnO TFTs are successfully demonstrated on plastic substrates for the large area flexible electronics.

High-Resolution Inkjet-Printed Oxide Thin-Film Transistors with a Self-Aligned Fine Channel Bank Structure.

PubMed

Zhang, Qing; Shao, Shuangshuang; Chen, Zheng; Pecunia, Vincenzo; Xia, Kai; Zhao, Jianwen; Cui, Zheng

2018-05-09

A self-aligned inkjet printing process has been developed to construct small channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gates on transparent glass substrates. Poly(methylsilsesquioxane) was used to pattern hydrophobic banks on the transparent substrate instead of commonly used self-assembled octadecyltrichlorosilane. Photolithographic exposure from backside using bottom-gate electrodes as mask formed hydrophilic channel areas for the TFTs. IGZO ink was selectively deposited by an inkjet printer in the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. Inkjet-printed IGZO TFTs with independent gate electrodes of 10 μm width have been demonstrated, avoiding completely printed channel beyond the broad of the gate electrodes. The TFTs showed on/off ratios of 10 8 , maximum mobility of 3.3 cm 2 V -1 s -1 , negligible hysteresis, and good uniformity. This method is conductive to minimizing the area of printed TFTs so as to the development of high-resolution printing displays.

Multi-oxide active layer deposition using Applied Materials Pivot array coater for high-mobility metal oxide TFT

NASA Astrophysics Data System (ADS)

Park, Hyun Chan; Scheer, Evelyn; Witting, Karin; Hanika, Markus; Bender, Marcus; Hsu, Hao Chien; Yim, Dong Kil

2015-11-01

By controlling a thin indium tin oxide (ITO), indium zinc oxide interface layer between gate insulator and indium gallium zinc oxide (IGZO), the thin-film transistor (TFT) performance can reach higher mobility as conventional IGZO as well as superior stability. For large-area display application, Applied Materials static PVD array coater (Applied Materials GmbH & Co. KG, Alzenau, Germany) using rotary targets has been developed to enable uniform thin layer deposition in display industry. Unique magnet motion parameter optimization in Pivot sputtering coater is shown to provide very uniform thin ITO layer to reach TFT performance with high mobility, not only on small scale, but also on Gen8.5 (2500 × 2200 mm glass size) production system.

Drying Temperature Dependence of Sol-gel Spin Coated Bilayer Composite ZnO/TiO2 Thin Films for Extended Gate Field Effect Transistor pH Sensor

NASA Astrophysics Data System (ADS)

Rahman, R. A.; Zulkefle, M. A.; Yusoff, K. A.; Abdullah, W. F. H.; Rusop, M.; Herman, S. H.

2018-03-01

This study presents an investigation on zinc oxide (ZnO) and titanium dioxide (TiO2) bilayer film applied as the sensing membrane for extended-gate field effect transistor (EGFET) for pH sensing application. The influences of the drying temperatures on the pH sensing capability of ZnO/TiO2 were investigated. The sensing performance of the thin films were measured by connecting the thin film to a commercial MOSFET to form the extended gates. By varying the drying temperature, we found that the ZnO/TiO2 thin film dried at 150°C gave the highest sensitivity compared to other drying conditions, with the sensitivity value of 48.80 mV/pH.

Synthesis, integration, and characterization of metal oxide films as alternative gate dielectric materials

NASA Astrophysics Data System (ADS)

Lin, You-Sheng

ZrO2 and HfO2 were investigated in this study to replace SiO2 as the potential gate dielectric materials in metal-oxide-semiconductor field effect transistors. ZrO2 and HfO2 films were deposited on p-type Si (100) wafers by an atomic layer chemical vapor deposition (ALCVD) process using zirconium (IV) t-butoxide and hafnium (IV) t-butoxide as the metal precursors, respectively. Oxygen was used alternatively with these metal alkoxide precursors into the reactor with purging and evacuation in between. The as-deposited ZrO2 and HfO2 films were stoichiometric and uniform based on X-ray photoemission spectroscopy and ellipsometry measurements. X-ray diffraction analysis indicated that the deposited films were amorphous, however, the high-resolution transmission electron microscopy showed an interfacial layer formation on the silicon substrate. Time-of-flight secondary ion mass spectrometry and medium energy ion scattering analysis showed significant intermixing between metal oxides and Si, indicating the formation of metal silicates, which were confirmed by their chemical etching resistance in HF solutions. The thermal stability of ZrO2 and HfO2 thin films on silicon was examined by monitoring their decomposition temperatures in ultra-high vacuum, using in-situ synchrotron radiation ultra-violet photoemission spectroscopy. The as-deposited ZrO2 and HfO2 thin films were thermally stable up to 880°C and 950°C in vacuum, respectively. The highest achieveable dielectric constants of as-deposited ZrO 2 and HfO2 were 21 and 24, respectively, which were slightly lower than the reported dielectric constants of bulk ZrO2 and HfO 2. These slight reductions in dielectric constants were attributed to the formation of the interfacial metal silicate layers. Very small hysteresis and interface state density were observed for both metal oxide films. Their leakage currents were a few orders of magnitude lower than that of SiO 2 at the same equivalent oxide thickness. NMOSFETs were also fabricated with the as-deposited metal oxide films, and reasonable ID-V D and IG-VG results were obtained. The electron mobilities were high from devices built using a plasma etching process to pattern the metal oxide films. However, they can be degraded if an HF wet etching process was used due to the large contact resistences. Upon oxygen annealing, the formation of SiOx at the interface improved the thermal stability of the as-deposited metal oxide films, however, lower overall dielectric constant and higher leakage current were observed. Upon ammonia annealing, the formation of SiOxNy improved not only the thermal stability but also reduced the leakage current. However, the overall dielectric constant of the film was still reduced due to the formation of the additional interfacial layer.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

NASA Astrophysics Data System (ADS)

Priydarshi, A.; Chattopadhyay, M. K.

2016-10-01

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;

Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Kawamura, Yumi; Tani, Mai; Hattori, Nozomu; Miyatake, Naomasa; Horita, Masahiro; Ishikawa, Yasuaki; Uraoka, Yukiharu

2012-02-01

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2 V-1 s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3 thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3 gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3 film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

Solution-processed flexible fluorine-doped indium zinc oxide thin-film transistors fabricated on plastic film at low temperature.

PubMed

Seo, Jin-Suk; Jeon, Jun-Hyuck; Hwang, Young Hwan; Park, Hyungjin; Ryu, Minki; Park, Sang-Hee Ko; Bae, Byeong-Soo

2013-01-01

Transparent flexible fluorine-doped indium zinc oxide (IZO:F) thin-film transistors (TFTs) were demonstrated using the spin-coating method of the metal fluoride precursor aqueous solution with annealing at 200°C for 2 hrs on polyethylene naphthalate films. The proposed thermal evolution mechanism of metal fluoride aqueous precursor solution examined by thermogravimetric analysis and Raman spectroscopy can easily explain oxide formation. The chemical composition analysed by XPS confirms that the fluorine was doped in the thin films annealed below 250°C. In the IZO:F thin films, a doped fluorine atom substitutes for an oxygen atom generating a free electron or occupies an oxygen vacancy site eliminating an electron trap site. These dual roles of the doped fluorine can enhance the mobility and improve the gate bias stability of the TFTs. Therefore, the transparent flexible IZO:F TFT shows a high mobility of up to 4.1 cm(2)/V·s and stable characteristics under the various gate bias and temperature stresses.

Solution-Processed Flexible Fluorine-doped Indium Zinc Oxide Thin-Film Transistors Fabricated on Plastic Film at Low Temperature

PubMed Central

Seo, Jin-Suk; Jeon, Jun-Hyuck; Hwang, Young Hwan; Park, Hyungjin; Ryu, Minki; Park, Sang-Hee Ko; Bae, Byeong-Soo

2013-01-01

Transparent flexible fluorine-doped indium zinc oxide (IZO:F) thin-film transistors (TFTs) were demonstrated using the spin-coating method of the metal fluoride precursor aqueous solution with annealing at 200°C for 2 hrs on polyethylene naphthalate films. The proposed thermal evolution mechanism of metal fluoride aqueous precursor solution examined by thermogravimetric analysis and Raman spectroscopy can easily explain oxide formation. The chemical composition analysed by XPS confirms that the fluorine was doped in the thin films annealed below 250°C. In the IZO:F thin films, a doped fluorine atom substitutes for an oxygen atom generating a free electron or occupies an oxygen vacancy site eliminating an electron trap site. These dual roles of the doped fluorine can enhance the mobility and improve the gate bias stability of the TFTs. Therefore, the transparent flexible IZO:F TFT shows a high mobility of up to 4.1 cm2/V·s and stable characteristics under the various gate bias and temperature stresses. PMID:23803977

Ultra-Flexible, Invisible Thin-Film Transistors Enabled by Amorphous Metal Oxide/Polymer Channel Layer Blends

DTIC Science & Technology

2015-02-25

all the In 2 O 3 : x %PVP blends, where the polymer chains disrupt oxide lattice forma - tion at the nanoscale grain level rather than at the atomic...oxidative stability. [ 51,52 ] This result can be qualitatively ascribed to the endothermic M–O–M lattice forma - tion acting as heat absorber and the ultra... Irie , M. Komiyama , H. Yui , Supramol. Sci. 1998 , 5 , 411 . [40] D. B. Buchholz , J. Liu , T. J. Marks , M. Zhang , R. P. Chang

Ionic liquid gating reveals trap-filled limit mobility in low temperature amorphous zinc oxide

NASA Astrophysics Data System (ADS)

Bubel, S.; Meyer, S.; Kunze, F.; Chabinyc, M. L.

2013-10-01

In low-temperature solution processed amorphous zinc oxide (a-ZnO) thin films, we show the thin film transistor (TFT) characteristics for the trap-filled limit (TFL), when the quasi Fermi energy exceeds the conduction band edge and all tail-states are filled. In order to apply gate fields that are high enough to reach the TFL, we use an ionic liquid tape gate. Performing capacitance voltage measurements to determine the accumulated charge during TFT operation, we find the TFL at biases higher than predicted by the electronic structure of crystalline ZnO. We conclude that the density of states in the conduction band of a-ZnO is higher than in its crystalline state. Furthermore, we find no indication of percolative transport in the conduction band but trap assisted transport in the tail-states of the band.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

NASA Astrophysics Data System (ADS)

Yang, Xiaolei; Tao, Yonghong; Yang, Tongtong; Huang, Runhua; Song, Bai

2018-03-01

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices, n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications. In this paper, backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs. The thickness of a drift layer was 120 μm, which was designed for a blocking voltage of 13 kV. The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V, with a differential specific on-resistance of 140 mΩ·cm2.

Influence of Surface Passivation on AlN Barrier Stress and Scattering Mechanism in Ultra-thin AlN/GaN Heterostructure Field-Effect Transistors.

PubMed

Lv, Y J; Song, X B; Wang, Y G; Fang, Y L; Feng, Z H

2016-12-01

Ultra-thin AlN/GaN heterostructure field-effect transistors (HFETs) with, and without, SiN passivation were fabricated by the same growth and device processes. Based on the measured DC characteristics, including the capacitance-voltage (C-V) and output current-voltage (I-V) curves, the variation of electron mobility with gate bias was found to be quite different for devices with, and without, SiN passivation. Although the AlN barrier layer is ultra thin (c. 3 nm), it was proved that SiN passivation induces no additional tensile stress and has no significant influence on the piezoelectric polarization of the AlN layer using Hall and Raman measurements. The SiN passivation was found to affect the surface properties, thereby increasing the electron density of the two-dimensional electron gas (2DEG) under the access region. The higher electron density in the access region after SiN passivation enhanced the electrostatic screening for the non-uniform distributed polarization charges, meaning that the polarization Coulomb field scattering has a weaker effect on the electron drift mobility in AlN/GaN-based devices.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

PubMed

Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

2016-01-27

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

Impact of ultra-thin Al2O3-y layers on TiO2-x ReRAM switching characteristics

NASA Astrophysics Data System (ADS)

Trapatseli, Maria; Cortese, Simone; Serb, Alexander; Khiat, Ali; Prodromakis, Themistoklis

2017-05-01

Transition metal-oxide resistive random access memory devices have demonstrated excellent performance in switching speed, versatility of switching and low-power operation. However, this technology still faces challenges like poor cycling endurance, degradation due to high electroforming (EF) switching voltages and low yields. Approaches such as engineering of the active layer by doping or addition of thin oxide buffer layers have been often adopted to tackle these problems. Here, we have followed a strategy that combines the two; we have used ultra-thin Al2O3-y buffer layers incorporated between TiO2-x thin films taking into account both 3+/4+ oxidation states of Al/Ti cations. Our devices were tested by DC and pulsed voltage sweeping and in both cases demonstrated improved switching voltages. We believe that the Al2O3-y layers act as reservoirs of oxygen vacancies which are injected during EF, facilitate a filamentary switching mechanism and provide enhanced filament stability, as shown by the cycling endurance measurements.

Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

NASA Astrophysics Data System (ADS)

Fan, Wei

To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers, compared with pure TiO2. A modified 3-element model was adopted to extract the true C-V behavior of the TiAlOx-based MOS capacitor. Extremely small equivalent oxide thickness (EOT) less than 0.5 nm with dielectric leakage 4˜5 magnitude lower than that for SiO2 has been achieved on TiAlOx layer as a result of its excellent dielectric properties.

Trap States of the Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Yuh, Jin Tae; Park, Sang Hee Ko; Ryu, Min Ki; Yun, Eui Jung; Bae, Byung Seong

2013-10-01

We investigated the temperature dependent recovery of the threshold voltage shift observed in both ZnO and indium gallium zinc oxide (IGZO) thin film transistors (TFTs) after application of gate bias and light illumination. Two types of recovery were observed for both the ZnO and IGZO TFTs; low temperature recovery (below 110 °C) which is attributed to the trapped charge and high temperature recovery (over 110 °C) which is related to the annihilation of trap states generated during stresses. From a comparison study of the recovery rate with the analysis of hydrogen diffusion isochronal annealing, a similar behavior was observed for both TFT recovery and hydrogen diffusion. This result suggests that hydrogen plays an important role in the generation and annihilation of trap states in oxide TFTs under gate bias or light illumination stresses.

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

Characteristics of high-k gate dielectric formed by the oxidation of sputtered Hf/Zr/Hf thin films on the Si substrate

NASA Astrophysics Data System (ADS)

Kim, H. D.; Roh, Y.; Lee, J. E.; Kang, H.-B.; Yang, C.-W.; Lee, N.-E.

2004-07-01

We have investigated the effects of high temperature annealing on the physical and electrical properties of multilayered high-k gate oxide [HfSixOy/HfO2/intermixed-layer(IL)/ZrO2/intermixed-layer(IL)/HfO2] in metal-oxide-semiconductor device. The multilayered high-k films were formed after oxidizing the Hf/Zr/Hf films deposited directly on the Si substrate. The subsequent N2 annealing at high temperature (>= 700 °C) not only results in the polycrystallization of the multilayered high-k films, but also causes the diffusion of Zr. The latter transforms the HfSixOy/HfO2/IL/ZrO2/IL/HfO2 film into the Zr-doped HfO2 film, and improves electrical properties in general. However, the thin SiOx interfacial layer starts to form if annealing temperature increases over 700 °C, deteriorating the equivalent oxide thickness. .

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

PubMed

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

Bio-sorbable, liquid electrolyte gated thin-film transistor based on a solution-processed zinc oxide layer.

PubMed

Singh, Mandeep; Palazzo, Gerardo; Romanazzi, Giuseppe; Suranna, Gian Paolo; Ditaranto, Nicoletta; Di Franco, Cinzia; Santacroce, Maria Vittoria; Mulla, Mohammad Yusuf; Magliulo, Maria; Manoli, Kyriaki; Torsi, Luisa

2014-01-01

Among the metal oxide semiconductors, ZnO has been widely investigated as a channel material in thin-film transistors (TFTs) due to its excellent electrical properties, optical transparency and simple fabrication via solution-processed techniques. Herein, we report a solution-processable ZnO-based thin-film transistor gated through a liquid electrolyte with an ionic strength comparable to that of a physiological fluid. The surface morphology and chemical composition of the ZnO films upon exposure to water and phosphate-buffered saline (PBS) are discussed in terms of the operation stability and electrical performance of the ZnO TFT devices. The improved device characteristics upon exposure to PBS are associated with the enhancement of the oxygen vacancies in the ZnO lattice due to Na(+) doping. Moreover, the dissolution kinetics of the ZnO thin film in a liquid electrolyte opens the possible applicability of these devices as an active element in "transient" implantable systems.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasingmore » temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.« less

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

PubMed

Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

2017-06-14

We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

A study on the high temperature-dependence of the electrical properties in a solution-deposited zinc-tin-oxide thin-film transistor operated in the saturation region

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Bae, Byung Seong; Jung, Myunghee; Yun, Eui-Jung

2016-06-01

We investigate the effects of high temperatures in the range of 292 - 393 K on the electrical properties of solution-processed amorphous zinc-tin-oxide (a-ZTO) thin-film transistors (TFTs) operated in the saturation region. The fabricated a-ZTO TFTs have a non-patterned bottom gate and top contact structure, and they use a heavily-doped Si wafer and SiO2 as a gate electrode and a gate insulator layer, respectively. In a-ZTO TFTs, the trap release energy ( E TR ) was deduced by using Maxwell-Boltzmann statistics. The decreasing E TR toward zero with increasing gate voltage (the density of trap states ( n s )) in the a-ZTO active layer can be attributed to a shift of the Fermi level toward the mobility edge with increasing gate voltage. The TFTs with low gate voltage (low n s ) exhibit multiple trap and release characteristics and show thermally-activated behavior. In TFTs with a high gate voltage (high n s ), however, we observe decreasing mobility and conductivity with increasing temperature at temperatures ranging from 303 to 363 K. This confirms that the E TR can drop to zero, indicating a shift of the Fermi level beyond the mobility edge. Hence, the mobility edge is detected at the cusp between thermally-activated transport and band transport.

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

NASA Astrophysics Data System (ADS)

Kiani, Ahmed; Hasko, David G.; Milne, William I.; Flewitt, Andrew J.

2013-04-01

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation.

Aerosol jet printed p- and n-type electrolyte-gated transistors with a variety of electrode materials: exploring practical routes to printed electronics.

PubMed

Hong, Kihyon; Kim, Se Hyun; Mahajan, Ankit; Frisbie, C Daniel

2014-11-12

Printing electrically functional liquid inks is a promising approach for achieving low-cost, large-area, additive manufacturing of flexible electronic circuits. To print thin-film transistors, a basic building block of thin-film electronics, it is important to have several options for printable electrode materials that exhibit high conductivity, high stability, and low-cost. Here we report completely aerosol jet printed (AJP) p- and n-type electrolyte-gated transistors (EGTs) using a variety of different electrode materials including highly conductive metal nanoparticles (Ag), conducting polymers (polystyrenesulfonate doped poly(3,4-ethylendedioxythiophene, PEDOT:PSS), transparent conducting oxides (indium tin oxide), and carbon-based materials (reduced graphene oxide). Using these source-drain electrode materials and a PEDOT:PSS/ion gel gate stack, we demonstrated all-printed p- and n-type EGTs in combination with poly(3-hexythiophene) and ZnO semiconductors. All transistor components (including electrodes, semiconductors, and gate insulators) were printed by AJP. Both kinds of devices showed typical p- and n-type transistor characteristics, and exhibited both low-threshold voltages (<2 V) and high hole and electron mobilities. Our assessment suggests Ag electrodes may be the best option in terms of overall performance for both types of EGTs.

Temporal and voltage stress stability of high performance indium-zinc-oxide thin film transistors

NASA Astrophysics Data System (ADS)

Song, Yang; Katsman, Alexander; Butcher, Amy L.; Paine, David C.; Zaslavsky, Alexander

2017-10-01

Thin film transistors (TFTs) based on transparent oxide semiconductors, such as indium zinc oxide (IZO), are of interest due to their improved characteristics compared to traditional a-Si TFTs. Previously, we reported on top-gated IZO TFTs with an in-situ formed HfO2 gate insulator and IZO active channel, showing high performance: on/off ratio of ∼107, threshold voltage VT near zero, extracted low-field mobility μ0 = 95 cm2/V·s, and near-perfect subthreshold slope at 62 mV/decade. Since device stability is essential for technological applications, in this paper we report on the temporal and voltage stress stability of IZO TFTs. Our devices exhibit a small negative VT shift as they age, consistent with an increasing carrier density resulting from an increasing oxygen vacancy concentration in the channel. Under gate bias stress, freshly annealed TFTs show a negative VT shift during negative VG gate bias stress, while aged (>1 week) TFTs show a positive VT shift during negative VG stress. This indicates two competing mechanisms, which we identify as the field-enhanced generation of oxygen vacancies and the field-assisted migration of oxygen vacancies, respectively. A simplified kinetic model of the vacancy concentration evolution in the IZO channel under electrical stress is provided.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

NASA Astrophysics Data System (ADS)

Tran, P. X.

2017-06-01

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Enhancement of emission efficiency of colloidal CdSe quantum dots on silicon substrate via an ultra-thin layer of aluminum oxide.

PubMed

Patty, K; Sadeghi, S M; Nejat, A; Mao, C-B

2014-04-18

We demonstrate that an ultra-thin layer of aluminum oxide can significantly enhance the emission efficiency of colloidal quantum dots on a Si substrate. For an ensemble of single quantum dots, our results show that this super brightening process can increase the fluorescence of CdSe quantum dots, forming well-resolved spectra, while in the absence of this layer the emission remains mostly at the noise level. We demonstrate that this process can be further enhanced with irradiation of the quantum dots, suggesting a significant photo-induced fluorescence enhancement via considerable suppression of non-radiative decay channels of the quantum dots. We study the impact of the Al oxide thickness on Si and interdot interactions, and discuss the results in terms of photo-induced catalytic properties of the Al oxide and the effects of such an oxide on the Coulomb blockade responsible for suppression of photo-ionization of the quantum dots.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Effect of gate voltage polarity on the ionic liquid gating behavior of NdNiO 3/NdGaO 3 heterostructures

DOE PAGES

Dong, Yongqi; Xu, Haoran; Luo, Zhenlin; ...

2017-05-16

The effect of gate voltage polarity on the behavior of NdNiO 3 epitaxial thin films during ionic liquid gating is studied using in situ synchrotron X-ray techniques. We show that while negative biases have no discernible effect on the structure or composition of the films, large positive gate voltages result in the injection of a large concentration of oxygen vacancies (similar to 3%) and pronounced lattice expansion (0.17%) in addition to a 1000-fold increase in sheet resistance at room temperature. Despite the creation of large defect densities, the heterostructures exhibit a largely reversible switching behavior when sufficient time is providedmore » for the vacancies to migrate in and out of the thin film surface. The results confirm that electrostatic gating takes place at negative gate voltages for p-type complex oxides while positive voltages favor the electrochemical reduction of Ni 3+. Switching between positive and negative gate voltages therefore involves a combination of electronic and ionic doping processes that may be utilized in future electrochemical transistors.« less

Ultra-fast switching of light by absorption saturation in vacuum ultra-violet region.

PubMed

Yoneda, Hitoki; Inubushi, Yuichi; Tanaka, Toshihiro; Yamaguchi, Yuta; Sato, Fumiya; Morimoto, Shunsuke; Kumagai, Taisuke; Nagasono, Mitsuru; Higashiya, Atsushi; Yabashi, Makina; Ishikawa, Tetsuya; Ohashi, Haruhiko; Kimura, Hiroaki; Kitamura, Hikaru; Kodama, Ryosuke

2009-12-21

Advances in free electron lasers producing high energy photons [Nat. Photonics 2(9), 555-559 (2008)] are expected to open up a new science of nonlinear optics of high energy photons. Specifically, lasers of photon energy higher than the plasma frequency of a metal can show new interaction features because they can penetrate deeply into metals without strong reflection. Here we show the observation of ultra-fast switching of vacuum ultra-violet (VUV) light caused by saturable absorption of a solid metal target. A strong gating is observed at energy fluences above 6J/cm2 at wavelength of 51 nm with tin metal thin layers. The ratio of the transmission at high intensity to low intensity is typically greater than 100:1. This means we can design new nonlinear photonic devices such as auto-correlator and pulse slicer for the VUV region.

Self-assembled Co-BaZrO 3 nanocomposite thin films with ultra-fine vertically aligned Co nanopillars

DOE PAGES

Huang, Jijie; Li, Leigang; Lu, Ping; ...

2017-05-11

A simple one-step pulsed laser deposition (PLD) method has been applied to grow self-assembled metal-oxide nanocomposite thin films. The as-deposited Co-BaZrO 3 films show high epitaxial quality with ultra-fine vertically aligned Co nanopillars (diameter <5 nm) embeded in BZO matrix. The diameter of the nanopillars can be further tuned by varying the deposition frequency. The metal and oxide phases grow separately without inter-diffusion or mixing. Taking advantage of this unique structure, a high saturation magnetization of ~1375 emu/cm 3 in the Co- BaZrO 3 nanocomposites has been achieved and further confirmed by Lorentz microscopy imaging in TEM. Furthermore, the coercivitymore » values of this nanocomposite thin films range from 600 Oe (20 Hz) to 1020 Oe (2 Hz), which makes the nanocomposite an ideal candidate for high-density perpendicular recording media.« less

Structure of a zinc oxide ultra-thin film on Rh(100)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yuhara, J.; Kato, D.; Matsui, T.

The structural parameters of ultra-thin zinc oxide films on Rh(100) are investigated using low-energy electron diffraction intensity (LEED I–V) curves, scanning tunneling microscopy (STM), and first-principles density functional theory (DFT) calculations. From the analysis of LEED I–V curves and DFT calculations, two optimized models A and B are determined. Their structures are basically similar to the planer h-BN ZnO(0001) structure, although some oxygen atoms protrude from the surface, associated with an in-plane shift of Zn atoms. From a comparison of experimental STM images and simulated STM images, majority and minority structures observed in the STM images represent the two optimizedmore » models A and B, respectively.« less

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Kwang-Won; Cho, Won-Ju, E-mail: chowj@kw.ac.kr

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristicmore » trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.« less

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Niang, K. M.; Flewitt, A. J., E-mail: ajf@eng.cam.ac.uk; Barquinha, P. M. C.

Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys.more » 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.« less

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

NASA Astrophysics Data System (ADS)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Effect of Al-diffusion-induced positive flatband voltage shift on the electrical characteristics of Al-incorporated high-k metal-oxide-semiconductor field-effective transistor

NASA Astrophysics Data System (ADS)

Wang, Wenwu; Akiyama, Koji; Mizubayashi, Wataru; Nabatame, Toshihide; Ota, Hiroyuki; Toriumi, Akira

2009-03-01

We systematically studied what effect Al diffusion from high-k dielectrics had on the flatband voltage (Vfb) of Al-incorporated high-k gate stacks. An anomalous positive shift fin Vfb with the decreasing equivalent oxide thickness (EOT) of high-k gate stacks is reported. As the SiO2 interfacial layer is aggressively thinned in Al-incorporated HfxAl1-xOy gate stacks with a metal-gate electrode, the Vfb first lies on the well known linear Vfb-EOT plot and deviates toward the positive-voltage direction (Vfb roll-up), followed by shifting toward negative voltage (Vfb roll-off). We demonstrated that the Vfb roll-up behavior remarkably decreases the threshold voltage (Vth) of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs), and does not cause severe degradation in the characteristics of hole mobility. The Vfb roll-up behavior, which is independent of gate materials but strongly dependent on high-k dielectrics, was ascribed to variations in fixed charges near the SiO2/Si interface, which are caused by Al diffusion from HfxAl1-xOy through SiO2 to the SiO2/Si interface. These results indicate that anomalous positive shift in Vfb, i.e., Vfb roll-up, should be taken into consideration in quantitatively adjusting Vfb in thin EOT regions and that it could be used to further tune Vth in p-MOSFETs.

Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor.

PubMed

Nomura, Kenji; Ohta, Hiromichi; Ueda, Kazushige; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

2003-05-23

We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO3(ZnO)5, as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of approximately 106 and a field-effect mobility of approximately 80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

PubMed Central

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies

NASA Astrophysics Data System (ADS)

Roy, Pradip K.; Chacon, Carlos M.; Ma, Yi; Horner, Gregory

1997-09-01

The advent of ultra-large and giga-scale-integration (ULSI/GSI) has placed considerable emphasis on the development of new gate oxides and interlevel dielectrics capable of meeting strict performance and reliability requirements. The costs and demands associated with ULSI fabrication have in turn fueled the need for cost-effective, rapid and accurate in-line characterization techniques for evaluating dielectric quality. The use of non-contact surface photovoltage characterization techniques provides cost-effective rapid feedback on dielectric quality, reducing costs through the reutilization of control wafers and the elimination of processing time. This technology has been applied to characterize most of the relevant C-V parameters, including flatband voltage (Vfb), density of interface traps (Dit), mobile charge density (Qm), oxide thickness (Tox), oxide resistivity (pox) and total charge (Qtot) for gate and interlevel (ILO) oxides. A novel method of measuring tunneling voltage by this technique on various gate oxides is discussed. For ILO, PECVD and high density plasma dielectrics, surface voltage maps are also presented. Measurements of near-surface silicon quality are described, including minority carrier generation lifetime, and examples of their application in diagnosing manufacturing problems.

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

NASA Astrophysics Data System (ADS)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a negative flat band voltage shift and larger hysteresis relative to the HF-dipped samples. The IL EOT reduction by mtridation increases with increasing HE Surface nitridation also induces extra charge, more considerable at the Si/IL interface. The leakage current is reduced in the Hf-rich samples with a nitride layer. Electron mobility degradation by surface nitridation was also observed.

Modification of FN tunneling provoking gate-leakage current in ZTO (zinc-tin oxide) TFT by regulating the ZTO/SiO2 area ratio

NASA Astrophysics Data System (ADS)

Li, Jeng-Ting; Tsai, Ho-Lin; Lai, Wei-Yao; Hwang, Weng-Sing; Chen, In-Gann; Chen, Jen-Sue

2018-04-01

This study addresses the variation in gate-leakage current due to the Fowler-Nordheim (FN) tunneling of electrons through a SiO2 dielectric layer in zinc-tin oxide (ZTO) thin film transistors. It is shown that the gate-leakage current is not related to the absolute area of the ZTO active layer, but it is reduced by reducing the ZTO/SiO2 area ratio. The ZTO/SiO2 area ratio modulates the ZTO-SiO2 interface dipole strength as well as the ZTO-SiO2 conduction band offset and subsequently affects the FN tunneling current through the SiO2 layer, which provides a route that modifies the gate-leakage current.

Static and low frequency noise characterization of ultra-thin body InAs MOSFETs

NASA Astrophysics Data System (ADS)

Karatsori, T. A.; Pastorek, M.; Theodorou, C. G.; Fadjie, A.; Wichmann, N.; Desplanque, L.; Wallart, X.; Bollaert, S.; Dimitriadis, C. A.; Ghibaudo, G.

2018-05-01

A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.

Atomic layer epitaxy of hematite on indium tin oxide for application in solar energy conversion

DOEpatents

Martinson, Alex B.; Riha, Shannon; Guo, Peijun; Emery, Jonathan D.

2016-07-12

A method to provide an article of manufacture of iron oxide on indium tin oxide for solar energy conversion. An atomic layer epitaxy method is used to deposit an uncommon bixbytite-phase iron (III) oxide (.beta.-Fe.sub.2O.sub.3) which is deposited at low temperatures to provide 99% phase pure .beta.-Fe.sub.2O.sub.3 thin films on indium tin oxide. Subsequent annealing produces pure .alpha.-Fe.sub.2O.sub.3 with well-defined epitaxy via a topotactic transition. These highly crystalline films in the ultra thin film limit enable high efficiency photoelectrochemical chemical water splitting.

Ultra-small, self-holding, optical gate switch using Ge2Sb2Te5 with a multi-mode Si waveguide.

PubMed

Tanaka, Daiki; Shoji, Yuya; Kuwahara, Masashi; Wang, Xiaomin; Kintaka, Kenji; Kawashima, Hitoshi; Toyosaki, Tatsuya; Ikuma, Yuichiro; Tsuda, Hiroyuki

2012-04-23

We report a multi-mode interference-based optical gate switch using a Ge(2)Sb(2)Te(5) thin film with a diameter of only 1 µm. The switching operation was demonstrated by laser pulse irradiation. This switch had a very wide operating wavelength range of 100 nm at around 1575 nm, with an average extinction ratio of 12.6 dB. Repetitive switching over 2,000 irradiation cycles was also successfully demonstrated. In addition, self-holding characteristics were confirmed by observing the dynamic responses, and the rise and fall times were 130 ns and 400 ns, respectively. © 2012 Optical Society of America

Color-selective photodetection from intermediate colloidal quantum dots buried in amorphous-oxide semiconductors.

PubMed

Cho, Kyung-Sang; Heo, Keun; Baik, Chan-Wook; Choi, Jun Young; Jeong, Heejeong; Hwang, Sungwoo; Lee, Sang Yeol

2017-10-10

We report color-selective photodetection from intermediate, monolayered, quantum dots buried in between amorphous-oxide semiconductors. The proposed active channel in phototransistors is a hybrid configuration of oxide-quantum dot-oxide layers, where the gate-tunable electrical property of silicon-doped, indium-zinc-oxide layers is incorporated with the color-selective properties of quantum dots. A remarkably high detectivity (8.1 × 10 13 Jones) is obtained, along with three major findings: fast charge separation in monolayered quantum dots; efficient charge transport through high-mobility oxide layers (20 cm 2  V -1  s -1 ); and gate-tunable drain-current modulation. Particularly, the fast charge separation rate of 3.3 ns -1 measured with time-resolved photoluminescence is attributed to the intermediate quantum dots buried in oxide layers. These results facilitate the realization of efficient color-selective detection exhibiting a photoconductive gain of 10 7 , obtained using a room-temperature deposition of oxide layers and a solution process of quantum dots. This work offers promising opportunities in emerging applications for color detection with sensitivity, transparency, and flexibility.The development of highly sensitive photodetectors is important for image sensing and optical communication applications. Cho et al., report ultra-sensitive photodetectors based on monolayered quantum dots buried in between amorphous-oxide semiconductors and demonstrate color-detecting logic gates.

Facile design of ultra-thin anodic aluminum oxide membranes for the fabrication of plasmonic nanoarrays.

PubMed

Hao, Qi; Huang, Hao; Fan, Xingce; Hou, Xiangyu; Yin, Yin; Li, Wan; Si, Lifang; Nan, Haiyan; Wang, Huaiyu; Mei, Yongfeng; Qiu, Teng; Chu, Paul K

2017-03-10

Ultra-thin anodic aluminum oxide (AAO) membranes are efficient templates for the fabrication of patterned nanostructures. Herein, a three-step etching method to control the morphology of AAO is described. The morphological evolution of the AAO during phosphoric acid etching is systematically investigated and a nonlinear growth mechanism during unsteady-state anodization is revealed. The thickness of the AAO can be quantitatively controlled from ∼100 nm to several micrometers while maintaining the tunablity of the pore diameter. The AAO membranes are robust and readily transferable to different types of substrates to prepare patterned plasmonic nanoarrays such as nanoislands, nanoclusters, ultra-small nanodots, and core-satellite superstructures. The localized surface plasmon resonance from these nanostructures can be easily tuned by adjusting the morphology of the AAO template. The custom AAO template provides a platform for the fabrication of low-cost and large-scale functional nanoarrays suitable for fundamental studies as well as applications including biochemical sensing, imaging, photocatalysis, and photovoltaics.

Facile design of ultra-thin anodic aluminum oxide membranes for the fabrication of plasmonic nanoarrays

NASA Astrophysics Data System (ADS)

Hao, Qi; Huang, Hao; Fan, Xingce; Hou, Xiangyu; Yin, Yin; Li, Wan; Si, Lifang; Nan, Haiyan; Wang, Huaiyu; Mei, Yongfeng; Qiu, Teng; Chu, Paul K.

2017-03-01

Ultra-thin anodic aluminum oxide (AAO) membranes are efficient templates for the fabrication of patterned nanostructures. Herein, a three-step etching method to control the morphology of AAO is described. The morphological evolution of the AAO during phosphoric acid etching is systematically investigated and a nonlinear growth mechanism during unsteady-state anodization is revealed. The thickness of the AAO can be quantitatively controlled from ˜100 nm to several micrometers while maintaining the tunablity of the pore diameter. The AAO membranes are robust and readily transferable to different types of substrates to prepare patterned plasmonic nanoarrays such as nanoislands, nanoclusters, ultra-small nanodots, and core-satellite superstructures. The localized surface plasmon resonance from these nanostructures can be easily tuned by adjusting the morphology of the AAO template. The custom AAO template provides a platform for the fabrication of low-cost and large-scale functional nanoarrays suitable for fundamental studies as well as applications including biochemical sensing, imaging, photocatalysis, and photovoltaics.

Complex oxide thin films for microelectronics

NASA Astrophysics Data System (ADS)

Suvorova, Natalya

The rapid scaling of the device dimensions, namely in metal oxide semiconductor field effect transistor (MOSFET), is reaching its fundamental limit which includes the increase in allowable leakage current due to direct tunneling with decrease of physical thickness of SiO2 gate dielectric. The significantly higher relative dielectric constant (in the range 9--25) of the gate dielectric beyond the 3.9 value of silicon dioxide will allow increasing the physical thickness. Among the choices for the high dielectric constant (K) materials for future generation MOSFET application, barium strontium titanate (BST) and strontium titanate (STO) possess one of the highest attainable K values making them the promising candidates for alternative gate oxide. However, the gate stack engineering does not imply the simple replacement of the SiO2 with the new dielectric. Several requirements should be met for successful integration of a new material. The major one is a production of high level of interface states (Dit) compared to that of SiO 2 on Si. An insertion of a thin SiO2 layer prior the growth of high-K thin film is a simple solution that helps to limit reaction with Si substrate and attains a high quality interface. However, the combination of two thin films reduces the overall K of the dielectric stack. An optimization of the SiO2 underlayer in order to maintain the interface quality yet minimize the effect on K is the focus of this work. The results from our study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST and STO films sputter deposited on thermally oxidized Si substrates spectroscopic ellipsometry in combination with time of flight ion scattering and recoil spectrometry have been employed. Studies of material properties have been complemented with analytical electron microscopy. To evaluate the interface quality the electrical characterization has been employed using capacitance-voltage and conductance-voltage measurements. Special attention was given to the extraction of static dielectric constant of BST and STO from the multiple film stack. The K value was found to be sensitive to the input parameters such as dielectric constant and thickness of interface layers.

Tunneling in BP-MoS2 heterostructure

NASA Astrophysics Data System (ADS)

Liu, Xiaochi; Qu, Deshun; Kim, Changsik; Ahmed, Faisal; Yoo, Won Jong

Tunnel field effect transistor (TFET) is considered to be a leading option for achieving SS <60 mV/dec. In this work, black phosphorus (BP) and molybdenum disulfide (MoS2) heterojunction devices are fabricated. We find that thin BP flake and MoS2 form normal p-n junctions, tunneling phenomena can be observed when BP thickness increases to certain level. PEO:CsClO4 is applied on the surface of the device together with a side gate electrode patterned together with source and drain electrodes. The Fermi level of MoS2 on top of BP layer can be modulated by the side gating, and this enables to vary the MoS2-BP tunnel diode property from off-state to on-state. Since tunneling is the working mechanism of MoS2-BP junction, and PEO:CsClO4\\ possesses ultra high dielectric constant and small equivalent oxide thickness (EOT), a low SS of 55 mV/dec is obtained from MoS2-BP TFET. This work was supported by the Global Research Laboratory and Global Frontier R&D Programs at the Center for Hybrid Interface Materials, both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea (NRF).

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Development of a high efficiency thin silicon solar cell

NASA Technical Reports Server (NTRS)

Lindmayer, J.; Wrigley, C. Y.

1977-01-01

A key to the success of this program was the breakthrough development of a technology for producing ultra-thin silicon slices which are very flexible, resilient, and tolerant of moderate handling abuse. Experimental topics investigated were thinning technology, gaseous junction diffusion, aluminum back alloying, internal reflectance, tantalum oxide anti-reflective coating optimization, slice flexibility, handling techniques, production rate limiting steps, low temperature behavior, and radiation tolerance.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

NASA Astrophysics Data System (ADS)

Xu, Hao; Yang, Hong; Luo, Wei-Chun; Xu, Ye-Feng; Wang, Yan-Rong; Tang, Bo; Wang, Wen-Wu; Qi, Lu-Wei; Li, Jun-Feng; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2016-08-01

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it/N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of MicroElectronics of Chinese Academy of Sciences.

Ultrahigh Detective Heterogeneous Photosensor Arrays with In-Pixel Signal Boosting Capability for Large-Area and Skin-Compatible Electronics.

PubMed

Kim, Jaehyun; Kim, Jaekyun; Jo, Sangho; Kang, Jingu; Jo, Jeong-Wan; Lee, Myungwon; Moon, Juhyuk; Yang, Lin; Kim, Myung-Gil; Kim, Yong-Hoon; Park, Sung Kyu

2016-04-01

An ultra-thin and large-area skin-compatible heterogeneous organic/metal-oxide photosensor array is demonstrated which is capable of sensing and boosting signals with high detectivity and signal-to-noise ratio. For the realization of ultra-flexible and high-sensitive heterogeneous photosensor arrays on a polyimide substrate having organic sensor arrays and metal-oxide boosting circuitry, solution-processing and room-temperature alternating photochemical conversion routes are applied. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Contact resistance and overlapping capacitance in flexible sub-micron long oxide thin-film transistors for above 100 MHz operation

NASA Astrophysics Data System (ADS)

Münzenrieder, Niko; Salvatore, Giovanni A.; Petti, Luisa; Zysset, Christoph; Büthe, Lars; Vogt, Christian; Cantarella, Giuseppe; Tröster, Gerhard

2014-12-01

In recent years new forms of electronic devices such as electronic papers, flexible displays, epidermal sensors, and smart textiles have become reality. Thin-film transistors (TFTs) are the basic blocks of the circuits used in such devices and need to operate above 100 MHz to efficiently treat signals in RF systems and address pixels in high resolution displays. Beyond the choice of the semiconductor, i.e., silicon, graphene, organics, or amorphous oxides, the junctionless nature of TFTs and its geometry imply some limitations which become evident and important in devices with scaled channel length. Furthermore, the mechanical instability of flexible substrates limits the feature size of flexible TFTs. Contact resistance and overlapping capacitance are two parasitic effects which limit the transit frequency of transistors. They are often considered independent, while a deeper analysis of TFTs geometry imposes to handle them together; in fact, they both depend on the overlapping length (LOV) between source/drain and the gate contacts. Here, we conduct a quantitative analysis based on a large number of flexible ultra-scaled IGZO TFTs. Devices with three different values of overlap length and channel length down to 0.5 μm are fabricated to experimentally investigate the scaling behavior of the transit frequency. Contact resistance and overlapping capacitance depend in opposite ways on LOV. These findings establish routes for the optimization of the dimension of source/drain contact pads and suggest design guidelines to achieve megahertz operation in flexible IGZO TFTs and circuits.

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizingmore » controllable high-performance stable transistors.« less

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

NASA Astrophysics Data System (ADS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Control of magnetism in Co by an electric field

NASA Astrophysics Data System (ADS)

Chiba, D.; Ono, T.

2013-05-01

In this paper, we review the recent experimental developments on electric-field switching of ferromagnetism in ultra-thin Co films. The application of an electric field changes the electron density at the surface of the Co film, which results in modulation of its Curie temperature. A capacitor structure consisting of a gate electrode, a solid-state dielectric insulator and a Co bottom electrode is used to observe the effect. To obtain a larger change in the electron density, we also fabricated an electric double-layer capacitor structure using an ionic liquid. A large change in the Curie temperature of ∼100 K across room temperature is achieved with this structure. The application of the electric field influences not only the Curie temperature but also the domain-wall motion. A change in the velocity of a domain wall prepared in a Co micro-wire of more than one order of magnitude is observed. Possible mechanisms to explain the above-mentioned electric-field effects in Co ultra-thin films are discussed.

Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

NASA Astrophysics Data System (ADS)

Yun, Ho-Jin; Kim, Young-Su; Jeong, Kwang-Seok; Kim, Yu-Mi; Yang, Seung-dong; Lee, Hi-Deok; Lee, Ga-Won

2014-01-01

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = -20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

Oxide-based materials by atomic layer deposition

NASA Astrophysics Data System (ADS)

Godlewski, Marek; Pietruszka, Rafał; Kaszewski, Jarosław; Witkowski, Bartłomiej S.; Gierałtowska, Sylwia; Wachnicki, Łukasz; Godlewski, Michał M.; Slonska, Anna; Gajewski, Zdzisław

2017-02-01

Thin films of wide band-gap oxides grown by Atomic Layer Deposition (ALD) are suitable for a range of applications. Some of these applications will be presented. First of all, ALD-grown high-k HfO2 is used as a gate oxide in the electronic devices. Moreover, ALD-grown oxides can be used in memory devices, in transparent transistors, or as elements of solar cells. Regarding photovoltaics (PV), ALD-grown thin films of Al2O3 are already used as anti-reflection layers. In addition, thin films of ZnO are tested as replacement of ITO in PV devices. New applications in organic photovoltaics, electronics and optoelectronics are also demonstrated Considering new applications, the same layers, as used in electronics, can also find applications in biology, medicine and in a food industry. This is because layers of high-k oxides show antibacterial activity, as discussed in this work.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors

NASA Astrophysics Data System (ADS)

Tsao, Yu-Ching; Chang, Ting-Chang; Chen, Hua-Mao; Chen, Bo-Wei; Chiang, Hsiao-Cheng; Chen, Guan-Fu; Chien, Yu-Chieh; Tai, Ya-Hsiang; Hung, Yu-Ju; Huang, Shin-Ping; Yang, Chung-Yi; Chou, Wu-Ching

2017-01-01

This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software.

Crystalline-like temperature dependence of the electrical characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors

NASA Astrophysics Data System (ADS)

Estrada, M.; Hernandez-Barrios, Y.; Cerdeira, A.; Ávila-Herrera, F.; Tinoco, J.; Moldovan, O.; Lime, F.; Iñiguez, B.

2017-09-01

A crystalline-like temperature dependence of the electrical characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) is reported, in which the drain current reduces as the temperature is increased. This behavior appears for values of drain and gate voltages above which a change in the predominant conduction mechanism occurs. After studying the possible conduction mechanisms, it was determined that, for gate and drain voltages below these values, hopping is the predominant mechanism with the current increasing with temperature, while for values above, the predominant conduction mechanism becomes percolation in the conduction band or band conduction and IDS reduces as the temperature increases. It was determined that this behavior appears, when the effect of trapping is reduced, either by varying the density of states, their characteristic energy or both. Simulations were used to further confirm the causes of the observed behavior.

Influences of Gate Bias and Light Stresses on Device Characteristics of High-Energy Electron-Beam-Irradiated Indium Gallium Zinc Oxide Based Thin Film Transistors

NASA Astrophysics Data System (ADS)

Yu, Kyeong Min; Moon, Hye Ji; Ryu, Min Ki; Cho, Kyoung Ik; Yun, Eui-Jung; Bae, Byung Seong

2012-09-01

Under white light illumination, amorphous indium-gallium-zinc oxide (a-IGZO)-based thin-film transistors (TFTs) showed a large negative shift of threshold voltage of more than -15 V depending on the process conditions. We investigated the influences of both gate bias and white light illumination on device properties of IGZO-based TFTs untreated and treated with high-energy electron beam irradiation (HEEBI). The TFTs were treated with HEEBI in air at room temperature (RT), electron beam energy of 0.8 MeV, and a dose of 1×1014 electrons/cm2. The HEEBI-treated TFTs showed an improved stability under negative bias illumination stress (NBIS) and positive bias illumination stress (PBIS) compared with non-HEEBI-treated TFTs, suggesting that the acceptor-like defects might be generated by HEEBI treatment near the valence band edge.

Oxide Semiconductor-Based Flexible Organic/Inorganic Hybrid Thin-Film Transistors Fabricated on Polydimethylsiloxane Elastomer.

PubMed

Jung, Soon-Won; Choi, Jeong-Seon; Park, Jung Ho; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lim, Sang Chul; Lee, Sang Seok; Chu, Hye Yong

2016-03-01

We demonstrate flexible organic/inorganic hybrid thin-film transistors (TFTs) on a polydimethysilox- ane (PDMS) elastomer substrate. The active channel and gate insulator of the hybrid TFT are composed of In-Ga-Zn-O (IGZO) and blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF- TrFE)] with poly(methyl methacrylate) (PMMA), respectively. It has been confirmed that the fabri- cated TFT display excellent characteristics: the recorded field-effect mobility, sub-threshold voltage swing, and I(on)/I(off) ratio were approximately 0.35 cm2 V(-1) s(-1), 1.5 V/decade, and 10(4), respectively. These characteristics did not experience any degradation at a bending radius of 15 mm. These results correspond to the first demonstration of a hybrid-type TFT using an organic gate insulator/oxide semiconducting active channel structure fabricated on PDMS elastomer, and demonstrate the feasibility of a promising device in a flexible electronic system.

Fabrication of Stretchable Organic-Inorganic Hybrid Thin-Film Transistors on Polyimide Stiff-Island Structures.

PubMed

Jung, Soon-Won; Koo, Jae Bon; Park, Chan Woo; Na, Bock Soon; Oh, Ji-Young; Lee, Sang Seok

2015-10-01

In this study, stretchable organic-inorganic hybrid thin-film transistors (TFTs) are fabricated on a polyimide (PI) stiff-island/elastomer substrate using blends of poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) and oxide semiconductor In-Ga-Zn-O as the gate dielectric and semiconducting layer, respectively. Carrier mobility, Ion/Ioff ratio, and subthreshold swing (SS) values of 6.1 cm2 V(-1) s(-1), 10(7), and 0.2 V/decade, respectively, were achieved. For the hybrid TFTs, the endurable maximum strain without degradation of electrical properties was approximately 49%. These results correspond to those obtained in the first study on fabrication of stretchable hybrid-type TFTs on elastomer substrate using an organic gate insulator and oxide semiconducting active channel structure, thus indicating the feasibility of a promising device for stretchable electronic systems.

Defect generation in amorphous-indium-gallium-zinc-oxide thin-film transistors by positive bias stress at elevated temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Um, Jae Gwang; Mativenga, Mallory; Jang, Jin, E-mail: jjang@khu.ac.kr

2014-04-07

We report on the generation and characterization of a hump in the transfer characteristics of amorphous indium gallium zinc-oxide thin-film transistors by positive bias temperature stress. The hump depends strongly on the gate bias stress at 100 °C. Due to the hump, the positive shift of the transfer characteristic in deep depletion is always smaller that in accumulation. Since, the latter shift is twice the former, with very good correlation, we conclude that the effect is due to creation of a double acceptor, likely to be a cation vacancy. Our results indicate that these defects are located near the gate insulator/activemore » layer interface, rather than in the bulk. Migration of donor defects from the interface towards the bulk may also occur under PBST at 100 °C.« less

Light-induced hysteresis and recovery behaviors in photochemically activated solution-processed metal-oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Jeong-Wan; Park, Sung Kyu, E-mail: yhkim76@skku.edu, E-mail: skpark@cau.ac.kr; Kim, Yong-Hoon, E-mail: yhkim76@skku.edu, E-mail: skpark@cau.ac.kr

2014-07-28

In this report, photo-induced hysteresis, threshold voltage (V{sub T}) shift, and recovery behaviors in photochemically activated solution-processed indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are investigated. It was observed that a white light illumination caused negative V{sub T} shift along with creation of clockwise hysteresis in electrical characteristics which can be attributed to photo-generated doubly ionized oxygen vacancies at the semiconductor/gate dielectric interface. More importantly, the photochemically activated IGZO TFTs showed much reduced overall V{sub T} shift compared to thermally annealed TFTs. Reduced number of donor-like interface states creation under light illumination and more facile neutralization of ionized oxygen vacancies bymore » electron capture under positive gate potential are claimed to be the origin of the less V{sub T} shift in photochemically activated TFTs.« less

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.

2013-11-25

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

NASA Astrophysics Data System (ADS)

Chen, Ya-Yi; Liu, Yuan; Wu, Zhao-Hui; Wang, Li; Li, Bin; En, Yun-Fei; Chen, Yi-Qiang

2018-04-01

Not Available Supported by the National Natural Science Foundation of China under Grant No 61574048, the Science and Technology Research Project of Guangdong Province under Grant Nos 2015B090912002 and 2015B090901048, and the Pearl River S&T Nova Program of Guangzhou under Grant No 201710010172.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

NASA Astrophysics Data System (ADS)

Mativenga, Mallory; Kang, Dong Han; Lee, Ung Gi; Jang, Jin

2012-09-01

Bias instability of top-gate amorphous-indium-gallium-zinc-oxide thin-film transistors with source- and drain-offsets is reported. Positive and negative gate bias-stress (VG_STRESS) respectively induce reversible negative threshold-voltage shift (ΔVTH) and reduction in on-current. Migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in the abnormal negative ΔVTH under positive VG_STRESS. The reduction in on-current under negative VG_STRESS is due to increase in resistance of the offsets when positive charges migrate away from the offsets. Appropriate drain and source bias-stresses applied simultaneously with VG_STRESS either suppress or enhance the instability, verifying lateral ion migration to be the instability mechanism.

Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric

PubMed Central

Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

2017-01-01

Two-dimensional layered semiconductors such as molybdenum disulfide (MoS2) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS2 and an ultra-thin HfO2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS2-HfO2 interface is responsible for the generation of interface states with a density (Dit) reaching ~7.03 × 1011 cm−2 eV−1. This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in Dit could be achieved by thermally diffusing S atoms to the MoS2-HfO2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS2 devices with carrier transport enhancement. PMID:28084434

Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

PubMed

Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

2017-01-13

Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Precursor-route ZnO films from a mixed casting solvent for high performance aqueous electrolyte-gated transistors.

PubMed

Althagafi, Talal M; Algarni, Saud A; Al Naim, Abdullah; Mazher, Javed; Grell, Martin

2015-12-14

We significantly improved the performance of precursor-route semiconducting zinc oxide (ZnO) films in electrolyte-gated thin film transistors (TFTs). We find that the organic precursor to ZnO, zinc acetate (ZnAc), dissolves more readily in a 1 : 1 mixture of ethanol (EtOH) and acetone than in pure EtOH, pure acetone, or pure isopropanol. XPS and SEM characterisation show improved morphology of ZnO films converted from a mixed solvent cast ZnAc precursor compared to the EtOH cast precursor. When gated with a biocompatible electrolyte, phosphate buffered saline (PBS), ZnO thin film transistors (TFTs) derived from mixed solvent cast ZnAc give 4 times larger field effect current than similar films derived from ZnAc cast from pure EtOH. The sheet resistance at VG = VD = 1 V is 30 kΩ □(-1), lower than for any organic TFT, and lower than for any electrolyte-gated ZnO TFT reported to date.

Pronounced photogating effect in atomically thin WSe2 with a self-limiting surface oxide layer

NASA Astrophysics Data System (ADS)

Yamamoto, Mahito; Ueno, Keiji; Tsukagoshi, Kazuhito

2018-04-01

The photogating effect is a photocurrent generation mechanism that leads to marked responsivity in two-dimensional (2D) semiconductor-based devices. A key step to promote the photogating effect in a 2D semiconductor is to integrate it with a high density of charge traps. Here, we show that self-limiting surface oxides on atomically thin WSe2 can serve as effective electron traps to facilitate p-type photogating. By examining the gate-bias-induced threshold voltage shift of a p-type transistor based on single-layer WSe2 with surface oxide, the electron trap density and the trap rate of the oxide are determined to be >1012 cm-2 and >1010 cm-2 s-1, respectively. White-light illumination on an oxide-covered 4-layer WSe2 transistor leads to the generation of photocurrent, the magnitude of which increases with the hole mobility. During illumination, the photocurrent evolves on a timescale of seconds, and a portion of the current persists even after illumination. These observations indicate that the photogenerated electrons are trapped deeply in the surface oxide and effectively gate the underlying WSe2. Owing to the pronounced photogating effect, the responsivity of the oxide-covered WSe2 transistor is observed to exceed 3000 A/W at an incident optical power of 1.1 nW, suggesting the effectiveness of surface oxidation in facilitating the photogating effect in 2D semiconductors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori

We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{submore » 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.« less

Passivation of Si(111) surfaces with electrochemically grafted thin organic films

NASA Astrophysics Data System (ADS)

Roodenko, K.; Yang, F.; Hunger, R.; Esser, N.; Hinrichs, K.; Rappich, J.

2010-09-01

Ultra thin organic films (about 5 nm thick) of nitrobenzene and 4-methoxydiphenylamine were deposited electrochemically on p-Si(111) surfaces from benzene diazonium compounds. Studies based on atomic force microscopy, infrared spectroscopic ellipsometry and x-ray photoelectron spectroscopy showed that upon exposure to atmospheric conditions the oxidation of the silicon interface proceed slower on organically modified surfaces than on unmodified hydrogen passivated p-Si(111) surfaces. Effects of HF treatment on the oxidized organic/Si interface and on the organic layer itself are discussed.

Investigations into the impact of various substrates and ZnO ultra thin seed layers prepared by atomic layer deposition on growth of ZnO nanowire array

PubMed Central

2012-01-01

The impact of various substrates and zinc oxide (ZnO) ultra thin seed layers prepared by atomic layer deposition on the geometric morphology of subsequent ZnO nanowire arrays (NWs) fabricated by the hydrothermal method was investigated. The investigated substrates included B-doped ZnO films, indium tin oxide films, single crystal silicon (111), and glass sheets. Scanning electron microscopy and X-ray diffraction measurements revealed that the geometry and aligment of the NWs were controlled by surface topography of the substrates and thickness of the ZnO seed layers, respectively. According to atomic force microscopy data, we suggest that the substrate, fluctuate amplitude and fluctuate frequency of roughness on ZnO seed layers have a great impact on the alignment of the resulting NWs, whereas the influence of the seed layers' texture was negligible. PMID:22759838

Performance regeneration of InGaZnO transistors with ultra-thin channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Binglei; Li, He; Zhang, Xijian, E-mail: zhangxijian@sdu.edu.cn, E-mail: songam@sdu.edu.cn

2015-03-02

Thin-film transistors (TFTs) based on ultra-thin amorphous indium gallium zinc oxide (a-IGZO) semiconductors down to 4 nm were studied motivated by the increasing cost of indium. At and below 5 nm, it was found that the field-effect mobility was severely degraded, the threshold voltage increased, and the output characteristics became abnormal showing no saturated current. By encapsulating a layer of polymethyl methacrylate on the IGZO TFTs, the performance of the 5-nm-thick device was effectively recovered. The devices also showed much higher on/off ratios, improved hysteresis, and normal output characteristic curves as compared with devices not encapsulated. The stability of the encapsulated devicesmore » was also studied over a four month period.« less

Improvement of Self-Heating of Indium Gallium Zinc Aluminum Oxide Thin-Film Transistors Using Al2O3 Barrier Layer

NASA Astrophysics Data System (ADS)

Jian, Li-Yi; Lee, Hsin-Ying; Lin, Yung-Hao; Lee, Ching-Ting

2018-02-01

To study the self-heating effect, aluminum oxide (Al2O3) barrier layers of various thicknesses have been inserted between the channel layer and insulator layer in bottom-gate-type indium gallium zinc aluminum oxide (IGZAO) thin-film transistors (TFTs). Each IGZAO channel layer was deposited on indium tin oxide (ITO)-coated glass substrate by using a magnetron radiofrequency cosputtering system with dual targets composed of indium gallium zinc oxide (IGZO) and Al. The 3 s orbital of Al cation provided an extra transport pathway and widened the conduction-band bottom, thus increasing the electron mobility of the IGZAO films. The Al-O bonds were able to sustain the oxygen stability of the IGZAO films. The self-heating behavior of the resulting IGZAO TFTs was studied by Hall measurements on the IGZAO films as well as the electrical performance of the IGZAO TFTs with Al2O3 barrier layers of various thicknesses at different temperatures. IGZAO TFTs with 50-nm-thick Al2O3 barrier layer were stressed by positive gate bias stress (PGBS, at gate-source voltage V GS = 5 V and drain-source voltage V DS = 0 V); at V GS = 5 V and V DS = 10 V, the threshold voltage shifts were 0.04 V and 0.2 V, respectively, much smaller than for the other IGZAO TFTs without Al2O3 barrier layer, which shifted by 0.2 V and 1.0 V when stressed under the same conditions.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

ZnO thin film transistor immunosensor with high sensitivity and selectivity

NASA Astrophysics Data System (ADS)

Reyes, Pavel Ivanoff; Ku, Chieh-Jen; Duan, Ziqing; Lu, Yicheng; Solanki, Aniruddh; Lee, Ki-Bum

2011-04-01

A zinc oxide thin film transistor-based immunosensor (ZnO-bioTFT) is presented. The back-gate TFT has an on-off ratio of 108 and a threshold voltage of 4.25 V. The ZnO channel surface is biofunctionalized with primary monoclonal antibodies that selectively bind with epidermal growth factor receptor (EGFR). Detection of the antibody-antigen reaction is achieved through channel carrier modulation via pseudo double-gating field effect caused by the biochemical reaction. The sensitivity of 10 fM detection of pure EGFR proteins is achieved. The ZnO-bioTFT immunosensor also enables selectively detecting 10 fM of EGFR in a 5 mg/ml goat serum solution containing various other proteins.

Single crystal functional oxides on silicon

PubMed Central

Bakaul, Saidur Rahman; Serrao, Claudy Rayan; Lee, Michelle; Yeung, Chun Wing; Sarker, Asis; Hsu, Shang-Lin; Yadav, Ajay Kumar; Dedon, Liv; You, Long; Khan, Asif Islam; Clarkson, James David; Hu, Chenming; Ramesh, Ramamoorthy; Salahuddin, Sayeef

2016-01-01

Single-crystalline thin films of complex oxides show a rich variety of functional properties such as ferroelectricity, piezoelectricity, ferro and antiferromagnetism and so on that have the potential for completely new electronic applications. Direct synthesis of such oxides on silicon remains challenging because of the fundamental crystal chemistry and mechanical incompatibility of dissimilar interfaces. Here we report integration of thin (down to one unit cell) single crystalline, complex oxide films onto silicon substrates, by epitaxial transfer at room temperature. In a field-effect transistor using a transferred lead zirconate titanate layer as the gate insulator, we demonstrate direct reversible control of the semiconductor channel charge with polarization state. These results represent the realization of long pursued but yet to be demonstrated single-crystal functional oxides on-demand on silicon. PMID:26853112

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

X-Ray Spectroscopy of Ultra-Thin Oxide/Oxide Heteroepitaxial Films: A Case Study of Single-Nanometer VO2/TiO2.

PubMed

Quackenbush, Nicholas F; Paik, Hanjong; Woicik, Joseph C; Arena, Dario A; Schlom, Darrell G; Piper, Louis F J

2015-08-21

Epitaxial ultra-thin oxide films can support large percent level strains well beyond their bulk counterparts, thereby enabling strain-engineering in oxides that can tailor various phenomena. At these reduced dimensions (typically < 10 nm), contributions from the substrate can dwarf the signal from the epilayer, making it difficult to distinguish the properties of the epilayer from the bulk. This is especially true for oxide on oxide systems. Here, we have employed a combination of hard X-ray photoelectron spectroscopy (HAXPES) and angular soft X-ray absorption spectroscopy (XAS) to study epitaxial VO2/TiO2 (100) films ranging from 7.5 to 1 nm. We observe a low-temperature (300 K) insulating phase with evidence of vanadium-vanadium (V-V) dimers and a high-temperature (400 K) metallic phase absent of V-V dimers irrespective of film thickness. Our results confirm that the metal insulator transition can exist at atomic dimensions and that biaxial strain can still be used to control the temperature of its transition when the interfaces are atomically sharp. More generally, our case study highlights the benefits of using non-destructive XAS and HAXPES to extract out information regarding the interfacial quality of the epilayers and spectroscopic signatures associated with exotic phenomena at these dimensions.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

NASA Astrophysics Data System (ADS)

Yan, Shi-Li; Xie, Zhi-Jian; Chen, Jian-Hao; Taniguchi, Takashi; Watanabe, Kenji

2017-03-01

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10V/nm to 0.83V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors.

PubMed

Singh, Shaivalini; Chakrabarti, P

2014-05-01

ZnO based bottom-gate thin film transistor (TFT) with SiO2 as insulating layer has been fabricated with two different structures. The effect of formation of mesa structure on the electrical characteristics of the TFTs has been studied. The formation of mesa structure of ZnO channel region can definitely result in better control over channel region and enhance value of channel mobility of ZnO TFT. As a result, by fabricating a mesa structured TFT, a better value of mobility and on-state current are achieved at low voltages. A typical saturation current of 1.85 x 10(-7) A under a gate bias of 50 V is obtained for non mesa structure TFT while for mesa structured TFT saturation current of 5 x 10(-5) A can be obtained at comparatively very low gate bias of 6.4 V.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain currentmore » after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.« less

Highly sensitive graphene biosensor by monomolecular self-assembly of receptors on graphene surface

NASA Astrophysics Data System (ADS)

Kim, Ji Eun; No, Young Hyun; Kim, Joo Nam; Shin, Yong Seon; Kang, Won Tae; Kim, Young Rae; Kim, Kun Nyun; Kim, Yong Ho; Yu, Woo Jong

2017-05-01

Graphene has attracted a great deal of interest for applications in bio-sensing devices because of its ultra-thin structure, which enables strong electrostatic coupling with target molecules, and its excellent electrical mobility promising for ultra-fast sensing speeds. However, thickly stacked receptors on the graphene's surface interrupts electrostatic coupling between graphene and charged biomolecules, which can reduce the sensitivity of graphene biosensors. Here, we report a highly sensitive graphene biosensor by the monomolecular self-assembly of designed peptide protein receptors. The graphene channel was non-covalently functionalized using peptide protein receptors via the π-π interaction along the graphene's Bravais lattice, allowing ultra-thin monomolecular self-assembly through the graphene lattice. In thickness dependent characterization, a graphene sensor with a monomolecular receptor (thickness less than 3 nm) showed five times higher sensitivity and three times higher voltage shifts than graphene sensors with thick receptor stacks (thicknesses greater than 20 nm), which is attributed to excellent gate coupling between graphene and streptavidin via an ultrathin receptor insulator. In addition to having a fast-inherent response time (less than 0.6 s) based on fast binding speed between biotin and streptavidin, our graphene biosensor is a promising platform for highly sensitive real-time monitoring of biomolecules with high spatiotemporal resolution.

Control of magnetism by electrical charge doping or redox reactions in a surface-oxidized Co thin film with a solid-state capacitor structure

NASA Astrophysics Data System (ADS)

Hirai, T.; Koyama, T.; Chiba, D.

2018-03-01

We have investigated the electric field (EF) effect on magnetism in a Co thin film with a naturally oxidized surface. The EF was applied to the oxidized Co surface through a gate insulator layer made of HfO2, which was formed using atomic layer deposition (ALD). The efficiency of the EF effect on the magnetic anisotropy in the sample with the HfO2 layer deposited at the appropriate temperature for the ALD process was relatively large compared to the previously reported values with an unoxidized Co film. The coercivity promptly and reversibly followed the variation in gate voltage. The modulation of the channel resistance was at most ˜0.02%. In contrast, a dramatic change in the magnetic properties including the large change in the saturation magnetic moment and a much larger EF-induced modulation of the channel resistance (˜10%) were observed in the sample with a HfO2 layer deposited at a temperature far below the appropriate temperature range. The response of these properties to the gate voltage was very slow, suggesting that a redox reaction dominated the EF effect on the magnetism in this sample. The frequency response for the capacitive properties was examined to discuss the difference in the mechanism of the EF effect observed here.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Solid-State Densification of Spun-Cast Self-Assembled Monolayers for Use in Ultra-Thin Hybrid Dielectrics.

PubMed

Hutchins, Daniel O; Acton, Orb; Weidner, Tobias; Cernetic, Nathan; Baio, Joe E; Castner, David G; Ma, Hong; Jen, Alex K-Y

2012-11-15

Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlO x (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7×10 -8 A cm -2 and capacitance density of 0.62 µF cm -2 at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to 1.1 cm 2 V -1 s -1 .

Solid-State Densification of Spun-Cast Self-Assembled Monolayers for Use in Ultra-Thin Hybrid Dielectrics

PubMed Central

Hutchins, Daniel O.; Acton, Orb; Weidner, Tobias; Cernetic, Nathan; Baio, Joe E.; Castner, David G.; Ma, Hong; Jen, Alex K.-Y.

2013-01-01

Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlOx (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7×10−8 A cm−2 and capacitance density of 0.62 µF cm−2 at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to 1.1 cm2 V−1 s−1. PMID:24288423

High Mobility Thin Film Transistors Based on Amorphous Indium Zinc Tin Oxide

PubMed Central

Noviyana, Imas; Lestari, Annisa Dwi; Putri, Maryane; Won, Mi-Sook; Bae, Jong-Seong; Heo, Young-Woo; Lee, Hee Young

2017-01-01

Top-contact bottom-gate thin film transistors (TFTs) with zinc-rich indium zinc tin oxide (IZTO) active layer were prepared at room temperature by radio frequency magnetron sputtering. Sintered ceramic target was prepared and used for deposition from oxide powder mixture having the molar ratio of In2O3:ZnO:SnO2 = 2:5:1. Annealing treatment was carried out for as-deposited films at various temperatures to investigate its effect on TFT performances. It was found that annealing treatment at 350 °C for 30 min in air atmosphere yielded the best result, with the high field effect mobility value of 34 cm2/Vs and the minimum subthreshold swing value of 0.12 V/dec. All IZTO thin films were amorphous, even after annealing treatment of up to 350 °C. PMID:28773058

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

NASA Technical Reports Server (NTRS)

Biegal, Bryan A.; Rafferty, Connor S.; Yu, Zhiping; Ancona, Mario G.; Dutton, Robert W.; Saini, Subhash (Technical Monitor)

1998-01-01

The continued down-scaling of electronic devices, in particular the commercially dominant MOSFET, will force a fundamental change in the process of new electronics technology development in the next five to ten years. The cost of developing new technology generations is soaring along with the price of new fabrication facilities, even as competitive pressure intensifies to bring this new technology to market faster than ever before. To reduce cost and time to market, device simulation must become a more fundamental, indeed dominant, part of the technology development cycle. In order to produce these benefits, simulation accuracy must improve markedly. At the same time, device physics will become more complex, with the rapid increase in various small-geometry and quantum effects. This work describes both an approach to device simulator development and a physical model which advance the effort to meet the tremendous electronic device simulation challenge described above. The device simulation approach is to specify the physical model at a high level to a general-purpose (but highly efficient) partial differential equation solver (in this case PROPHET, developed by Lucent Technologies), which then simulates the model in 1-D, 2-D, or 3-D for a specified device and test regime. This approach allows for the rapid investigation of a wide range of device models and effects, which is certainly essential for device simulation to catch up with, and then stay ahead of, electronic device technology of the present and future. The physical device model used in this work is the density-gradient (DG) quantum correction to the drift-diffusion model [Ancona, Phys. Rev. B 35(5), 7959 (1987)]. This model adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We used the DG model in 1-D and 2-D (for the first time) to simulate both bipolar and unipolar devices. Simulations of heavily-doped, short-base diodes indicated that the DG quantum corrections do not have a large effect on the IN characteristics of electronic devices without heteroj unction s. On the other hand, ultra-small MOSFETs certainly exhibit important quantum effects that the DG model will include: quantum repulsion of the inversion and gate charges from the oxide interfaces, and quantum tunneling through thin gate oxides. We present initial results of 2-D DG simulations of ultra-small MOSFETs. Subtle but important issues involving the specification of the model, boundary conditions, and interface constraints for DG simulation of MOSFETs will also be illuminated.

Insulator to metal transition in WO 3 induced by electrolyte gating

DOE PAGES

Leng, X.; Pereiro, J.; Strle, J.; ...

2017-07-03

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Investigation of Gate-Stacked In-Ga-Zn-O TFTs with Ga-Zn-O Source/Drain Electrodes by Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition.

PubMed

Wu, Chien-Hung; Chang, Kow-Ming; Chen, Yi-Ming; Huang, Bo-Wen; Zhang, Yu-Xin; Wang, Shui-Jinn; Hsu, Jui-Mei

2018-03-01

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) was employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO TFTs) with high transparent gallium zinc oxide (GZO) source/drain electrodes. The influence of post-deposition annealing (PDA) temperature on GZO source/drain and device performance was studied. Device with a 300 °C annealing demonstrated excellent electrical characteristics with on/off current ratio of 2.13 × 108, saturation mobility of 10 cm2/V-s, and low subthreshold swing of 0.2 V/dec. The gate stacked LaAlO3/ZrO2 of AP-IGZO TFTs with highly transparent and conductive AP-GZO source/drain electrode show excellent gate control ability at a low operating voltage.

A graphene oxide-carbon nanotube grid for high-resolution transmission electron microscopy of nanomaterials.

PubMed

Zhang, Lina; Zhang, Haoxu; Zhou, Ruifeng; Chen, Zhuo; Li, Qunqing; Fan, Shoushan; Ge, Guanglu; Liu, Renxiao; Jiang, Kaili

2011-09-23

A novel grid for use in transmission electron microscopy is developed. The supporting film of the grid is composed of thin graphene oxide films overlying a super-aligned carbon nanotube network. The composite film combines the advantages of graphene oxide and carbon nanotube networks and has the following properties: it is ultra-thin, it has a large flat and smooth effective supporting area with a homogeneous amorphous appearance, high stability, and good conductivity. The graphene oxide-carbon nanotube grid has a distinct advantage when characterizing the fine structure of a mass of nanomaterials over conventional amorphous carbon grids. Clear high-resolution transmission electron microscopy images of various nanomaterials are obtained easily using the new grids.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

NASA Astrophysics Data System (ADS)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

NASA Tech Briefs, April 2008

NASA Technical Reports Server (NTRS)

2008-01-01

Topics covered include: Gas Sensors Based on Coated and Doped Carbon Nanotubes; Tactile Robotic Topographical Mapping Without Force or Contact Sensors; Thin-Film Magnetic-Field-Response Fluid-Level Sensor for Non-Viscous Fluids; Progress in Development of Improved Ion-Channel Biosensors; Simulating Operation of a Complex Sensor Network; Using Transponders on the Moon to Increase Accuracy of GPS; Controller for Driving a Piezoelectric Actuator at Resonance; Coaxial Electric Heaters; Dual-Input AND Gate From Single-Channel Thin-Film FET; High-Density, High-Bandwidth, Multilevel Holographic Memory; Fabrication of Gate-Electrode Integrated Carbon-Nanotube Bundle Field Emitters; Hydroxide-Assisted Bonding of Ultra-Low-Expansion Glass; Photochemically Synthesized Polyimides; Optimized Carbonate and Ester-Based Li-Ion Electrolytes; Compact 6-DOF Stage for Optical Adjustments; Ultrasonic/Sonic Impacting Penetrators; Miniature, Lightweight, One-Time-Opening Valve; Supplier Management System; Improved CLARAty Functional-Layer/Decision-Layer Interface; JAVA Stereo Display Toolkit; Remote-Sensing Time Series Analysis, a Vegetation Monitoring Tool; PyPele Rewritten To Use MPI; Data Assimilation Cycling for Weather Analysis; Hydrocyclone/Filter for Concentrating Biomarkers from Soil; Activating STAT3 Alpha for Promoting Healing of Neurons; and Probing a Spray Using Frequency-Analyzed Light Scattering.

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

PubMed Central

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-01-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration. PMID:24599023

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

An Ultra-Precise Method for the Nano Thin-Film Removal

NASA Astrophysics Data System (ADS)

Pa, P. S.

In this research an electrode-set is used to investigate via an ultra-precise method for the removal of Indium Tin Oxide (ITO) thin-film microstructure from defective display panels to conquer the low yield rate in display panel production as to from imperfect Indium Tin Oxide layer deposition is well known. This process, which involves the removal of ITO layer substructure by means of an electrochemical removal (ECMR), is of major interest to the optoelectronics semiconductor industry. In this electro machining process a high current flow and high feed rate of the display (color filter) achieves complete and efficient removal of the ITO layer. The ITO thin-film can be removed completely by a proper combination of feed rate and electric power. A small gap between the diameter cathode virtual rotation circle and the diameter virtual rotation circle also corresponds to a higher removal rate. A small anode edge radius with a small cathode edge radius effectively improves dregs discharge and is an advantage when associated with a high workpiece feed rate. This precision method for the recycling of defective display screen color filters is presented as an effective tool for use in the screen manufacturing process. The defective Indium Tin Oxide thin-film can be removed easily and cleanly in a short time. The complete removal of the ITO layer makes it possible to put these panels back into the production line for reuse with a considerable reduction of both waste and production cost.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Achieving high carrier mobility exceeding 70 cm2/Vs in amorphous zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Tae; Shin, Yeonwoo; Yun, Pil Sang; Bae, Jong Uk; Chung, In Jae; Jeong, Jae Kyeong

2017-09-01

This paper proposes a new defect engineering concept for low-cost In- and Ga-free zinc tin oxide (ZTO) thin-film transistors (TFTs). This concept is comprised of capping ZTO films with tantalum (Ta) and a subsequent modest thermal annealing treatment at 200 °C. The Ta-capped ZTO TFTs exhibited a remarkably high carrier mobility of 70.8 cm2/Vs, low subthreshold gate swing of 0.18 V/decade, threshold voltage of -1.3 V, and excellent ION/OFF ratio of 2 × 108. The improvement (> two-fold) in the carrier mobility compared to the uncapped ZTO TFT can be attributed to the effective reduction of the number of adverse tailing trap states, such as hydroxyl groups or oxygen interstitial defects, which stems from the scavenging effect of the Ta capping layer on the ZTO channel layer. Furthermore, the Ta-capped ZTO TFTs showed excellent positive and negative gate bias stress stabilities. [Figure not available: see fulltext.

Analytical drain current model for symmetric dual-gate amorphous indium gallium zinc oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Qin, Ting; Liao, Congwei; Huang, Shengxiang; Yu, Tianbao; Deng, Lianwen

2018-01-01

An analytical drain current model based on the surface potential is proposed for amorphous indium gallium zinc oxide (a-InGaZnO) thin-film transistors (TFTs) with a synchronized symmetric dual-gate (DG) structure. Solving the electric field, surface potential (φS), and central potential (φ0) of the InGaZnO film using the Poisson equation with the Gaussian method and Lambert function is demonstrated in detail. The compact analytical model of current-voltage behavior, which consists of drift and diffusion components, is investigated by regional integration, and voltage-dependent effective mobility is taken into account. Comparison results demonstrate that the calculation results obtained using the derived models match well with the simulation results obtained using a technology computer-aided design (TCAD) tool. Furthermore, the proposed model is incorporated into SPICE simulations using Verilog-A to verify the feasibility of using DG InGaZnO TFTs for high-performance circuit designs.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Naphthacene Based Organic Thin Film Transistor With Rare Earth Oxide

NASA Astrophysics Data System (ADS)

Konwar, K.; Baishya, B.

2010-12-01

Naphthacene based organic thin film transistors (OTFTs) have been fabricated using La2O3, as the gate insulator. All the OTFTs have been fabricated by the process of thermal evaporation in vacuum on perfectly cleaned glass substrates with aluminium as source-drain and gate electrodes. The naphthacene film morphology on the glass substrate has been studied by XRD and found to be polycrystalline in nature. The field effect mobility, output resistance, amplification factor, transconductance and gain bandwidth product of the OTFTs have been calculated by using theoretical TFT model. The highest value of field effect mobility is found to be 0.07×10-3 cm2V-1s-1 for the devices annealed in vacuum at 90° C for 5 hours.

Stress analysis of ultra-thin silicon chip-on-foil electronic assembly under bending

NASA Astrophysics Data System (ADS)

Wacker, Nicoleta; Richter, Harald; Hoang, Tu; Gazdzicki, Pawel; Schulze, Mathias; Angelopoulos, Evangelos A.; Hassan, Mahadi-Ul; Burghartz, Joachim N.

2014-09-01

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness \\leqslant 20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the built-in devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chip's edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

Ultra-thin distributed Bragg reflectors via stacked single-crystal silicon nanomembranes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Minkyu; Seo, Jung-Hun; Lee, Jaeseong

2015-05-04

In this paper, we report ultra-thin distributed Bragg reflectors (DBRs) via stacked single-crystal silicon (Si) nanomembranes (NMs). Mesh hole-free single-crystal Si NMs were released from a Si-on-insulator substrate and transferred to quartz and Si substrates. Thermal oxidation was applied to the transferred Si NM to form high-quality SiO{sub 2} and thus a Si/SiO{sub 2} pair with uniform and precisely controlled thicknesses. The Si/SiO{sub 2} layers, as smooth as epitaxial grown layers, minimize scattering loss at the interface and in between the layers. As a result, a reflection of 99.8% at the wavelength range from 1350 nm to 1650 nm can be measuredmore » from a 2.5-pair DBR on a quartz substrate and 3-pair DBR on a Si substrate with thickness of 0.87 μm and 1.14 μm, respectively. The high reflection, ultra-thin DBRs developed here, which can be applied to almost any devices and materials, holds potential for application in high performance optoelectronic devices and photonics applications.« less

Polarity compensation in ultra-thin films of complex oxides: The case of a perovskite nickelate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Middey, S.; Rivero, P.; Meyers, D.

2014-10-29

In this study, we address the fundamental issue of growth of perovskite ultra-thin films under the condition of a strong polar mismatch at the heterointerface exemplified by the growth of a correlated metal LaNiO 3 on the band insulator SrTiO 3 along the pseudo cubic [111] direction. While in general the metallic LaNiO 3 film can effectively screen this polarity mismatch, we establish that in the ultra-thin limit, films are insulating in nature and require additional chemical and structural reconstruction to compensate for such mismatch. A combination of in-situ reflection high-energy electron diffraction recorded during the growth, X-ray diffraction, andmore » synchrotron based resonant X-ray spectroscopy reveal the formation of a chemical phase La 2Ni 2O 5 (Ni 2+) for a few unit-cell thick films. First-principles layer-resolved calculations of the potential energy across the nominal LaNiO 3/SrTiO 3 interface confirm that the oxygen vacancies can efficiently reduce the electric field at the interface.« less

Ultra-thin passivating film induced by vinylene carbonate on highly oriented pyrolytic graphite negative electrode in lithium-ion cell

NASA Astrophysics Data System (ADS)

Matsuoka, O.; Hiwara, A.; Omi, T.; Toriida, M.; Hayashi, T.; Tanaka, C.; Saito, Y.; Ishida, T.; Tan, H.; Ono, S. S.; Yamamoto, S.

We investigated the influence of vinylene carbonate, as an additive molecule, on the decomposition phenomena of electrolyte solution [ethylene carbonate (EC)—ethyl methyl carbonate (EMC) (1:2 by volume) containing 1 M LiPF 6] on a highly oriented pyrolytic graphite (HOPG) negative electrode by using cyclic voltammetry (CV) and atomic force microscopy (AFM). Vinylene carbonate deactivated reactive sites (e.g. radicals and oxides at the defects and the edge of carbon layer) on the cleaved surface of the HOPG negative electrode, and prevented further decomposition of the other solvents there. Further, vinylene carbonate induced an ultra-thin film (less than 1.0 nm in thickness) on the terrace of the basal plane of the HOPG negative electrode, and this film suppressed the decomposition of electrolyte solution on the terraces of the basal plane. We consider that this ultra-thin passivating film is composed of a reduction product of vinylene carbonate (VC), and might have a polymer structure. These induced effects might explain how VC improves the life performance of lithium-ion cells.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

The uniformity study of non-oxide thin film at device level using electron energy loss spectroscopy

NASA Astrophysics Data System (ADS)

Li, Zhi-Peng; Zheng, Yuankai; Li, Shaoping; Wang, Haifeng

2018-05-01

Electron energy loss spectroscopy (EELS) has been widely used as a chemical analysis technique to characterize materials chemical properties, such as element valence states, atoms/ions bonding environment. This study provides a new method to characterize physical properties (i.e., film uniformity, grain orientations) of non-oxide thin films in the magnetic device by using EELS microanalysis on scanning transmission electron microscope. This method is based on analyzing white line ratio of spectra and related extended energy loss fine structures so as to correlate it with thin film uniformity. This new approach can provide an effective and sensitive method to monitor/characterize thin film quality (i.e., uniformity) at atomic level for thin film development, which is especially useful for examining ultra-thin films (i.e., several nanometers) or embedded films in devices for industry applications. More importantly, this technique enables development of quantitative characterization of thin film uniformity and it would be a remarkably useful technique for examining various types of devices for industrial applications.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Polyelectrolyte/Graphene Oxide Barrier Film for Flexible OLED.

PubMed

Yang, Seung-Yeol; Park, Jongwhan; Kim, Yong-Seog

2015-10-01

Ultra-thin flexible nano-composite barrier layer consists of graphene oxide and polyelectrolyte was prepared using the layer-by-layer processing method. Microstructures of the barrier layer was optimized via modifying coating conditions and inducing chemical reactions. Although the barrier layer consists of hydrophilic polyelectrolyte was not effective in blocking the water vapor permeation, the chemical reduction of graphene oxide as well as conversion of polyelectrolyte to hydrophobic nature were very effective in reducing the permeation.

X-Ray Spectroscopy of Ultra-Thin Oxide/Oxide Heteroepitaxial Films: A Case Study of Single-Nanometer VO2/TiO2

PubMed Central

Quackenbush, Nicholas F.; Paik, Hanjong; Woicik, Joseph C.; Arena, Dario A.; Schlom, Darrell G.; Piper, Louis F. J.

2015-01-01

Epitaxial ultra-thin oxide films can support large percent level strains well beyond their bulk counterparts, thereby enabling strain-engineering in oxides that can tailor various phenomena. At these reduced dimensions (typically < 10 nm), contributions from the substrate can dwarf the signal from the epilayer, making it difficult to distinguish the properties of the epilayer from the bulk. This is especially true for oxide on oxide systems. Here, we have employed a combination of hard X-ray photoelectron spectroscopy (HAXPES) and angular soft X-ray absorption spectroscopy (XAS) to study epitaxial VO2/TiO2 (100) films ranging from 7.5 to 1 nm. We observe a low-temperature (300 K) insulating phase with evidence of vanadium-vanadium (V-V) dimers and a high-temperature (400 K) metallic phase absent of V-V dimers irrespective of film thickness. Our results confirm that the metal insulator transition can exist at atomic dimensions and that biaxial strain can still be used to control the temperature of its transition when the interfaces are atomically sharp. More generally, our case study highlights the benefits of using non-destructive XAS and HAXPES to extract out information regarding the interfacial quality of the epilayers and spectroscopic signatures associated with exotic phenomena at these dimensions. PMID:28793516

X-ray Spectroscopy of Ultra-thin Oxide/oxide Heteroepitaxial Films: A Case Study of Single-nanometer VO2/TiO2

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quackenbush, Nicholas F.; Paik, Hanjong; Woicik, Joseph C.

2015-08-21

Epitaxial ultra-thin oxide films can support large percent level strains well beyond their bulk counterparts, thereby enabling strain-engineering in oxides that can tailor various phenomena. At these reduced dimensions (typically < 10 nm), contributions from the substrate can dwarf the signal from the epilayer, making it difficult to distinguish the properties of the epilayer from the bulk. This is especially true for oxide on oxide systems. Here, we have employed a combination of hard X-ray photoelectron spectroscopy (HAXPES) and angular soft X-ray absorption spectroscopy (XAS) to study epitaxial VO2/TiO2 (100) films ranging from 7.5 to 1 nm. We observe amore » low-temperature (300 K) insulating phase with evidence of vanadium-vanadium (V-V) dimers and a high-temperature (400 K) metallic phase absent of V-V dimers irrespective of film thickness. Results confirm that the metal insulator transition can exist at atomic dimensions and that biaxial strain can still be used to control the temperature of its transition when the interfaces are atomically sharp. Generally, our case study highlights the benefits of using non-destructive XAS and HAXPES to extract out information regarding the interfacial quality of the epilayers and spectroscopic signatures associated with exotic phenomena at these dimensions.« less

Direct imprinting of indium-tin-oxide precursor gel and simultaneous formation of channel and source/drain in thin-film transistor

NASA Astrophysics Data System (ADS)

Haga, Ken-ichi; Kamiya, Yuusuke; Tokumitsu, Eisuke

2018-02-01

We report on a new fabrication process for thin-film transistors (TFTs) with a new structure and a new operation principle. In this process, both the channel and electrode (source/drain) are formed simultaneously, using the same oxide material, using a single nano-rheology printing (n-RP) process, without any conventional lithography process. N-RP is a direct thermal imprint technique and deforms oxide precursor gel. To reduce the source/drain resistance, the material common to the channel and electrode is conductive indium-tin-oxide (ITO). The gate insulator is made of a ferroelectric material, whose high charge density can deplete the channel of the thin ITO film, which realizes the proposed operation principle. First, we have examined the n-RP conditions required for the channel and source/drain patterning, and found that the patterning properties are strongly affected by the cooling rate before separating the mold. Second, we have fabricated the TFTs as proposed and confirmed their TFT operation.

Cyclical Annealing Technique To Enhance Reliability of Amorphous Metal Oxide Thin Film Transistors.

PubMed

Chen, Hong-Chih; Chang, Ting-Chang; Lai, Wei-Chih; Chen, Guan-Fu; Chen, Bo-Wei; Hung, Yu-Ju; Chang, Kuo-Jui; Cheng, Kai-Chung; Huang, Chen-Shuo; Chen, Kuo-Kuang; Lu, Hsueh-Hsing; Lin, Yu-Hsin

2018-02-26

This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional long-term annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

Growth, stability and decomposition of Mg2Si ultra-thin films on Si (100)

NASA Astrophysics Data System (ADS)

Sarpi, B.; Zirmi, R.; Putero, M.; Bouslama, M.; Hemeryck, A.; Vizzini, S.

2018-01-01

Using Auger Electron Spectroscopy (AES), Scanning Tunneling Microscopy/Spectroscopy (STM/STS) and Low Energy Electron Diffraction (LEED), we report an in-situ study of amorphous magnesium silicide (Mg2Si) ultra-thin films grown by thermally enhanced solid-phase reaction of few Mg monolayers deposited at room temperature (RT) on a Si(100) surface. Silicidation of magnesium films can be achieved in the nanometric thickness range with high chemical purity and a high thermal stability after annealing at 150 °C, before reaching a regime of magnesium desorption for temperatures higher than 350 °C. The thermally enhanced reaction of one Mg monolayer (ML) results in the appearance of Mg2Si nanometric crystallites leaving the silicon surface partially uncovered. For thicker Mg deposition nevertheless, continuous 2D silicide films are formed with a volcano shape surface topography characteristic up to 4 Mg MLs. Due to high reactivity between magnesium and oxygen species, the thermal oxidation process in which a thin Mg2Si film is fully decomposed (0.75 eV band gap) into a magnesium oxide layer (6-8 eV band gap) is also reported.

Ultra-high aspect ratio copper nanowires as transparent conductive electrodes for dye sensitized solar cells

NASA Astrophysics Data System (ADS)

Zhu, Zhaozhao; Mankowski, Trent; Shikoh, Ali Sehpar; Touati, Farid; Benammar, Mohieddine A.; Mansuripur, Masud; Falco, Charles M.

2016-09-01

We report the synthesis of ultra-high aspect ratio copper nanowires (CuNW) and fabrication of CuNW-based transparent conductive electrodes (TCE) with high optical transmittance (>80%) and excellent sheet resistance (Rs <30 Ω/sq). These CuNW TCEs are subsequently hybridized with aluminum-doped zinc oxide (AZO) thin-film coatings, or platinum thin film coatings, or nickel thin-film coatings. Our hybrid transparent electrodes can replace indium tin oxide (ITO) films in dye-sensitized solar cells (DSSCs) as either anodes or cathodes. We highlight the challenges of integrating bare CuNWs into DSSCs, and demonstrate that hybridization renders the solar cell integrations feasible. The CuNW/AZO-based DSSCs have reasonably good open-circuit voltage (Voc = 720 mV) and short-circuit current-density (Jsc = 0.96 mA/cm2), which are comparable to what is obtained with an ITO-based DSSC fabricated with a similar process. Our CuNW-Ni based DSSCs exhibit a good open-circuit voltage (Voc = 782 mV) and a decent short-circuit current (Jsc = 3.96 mA/cm2), with roughly 1.5% optical-to-electrical conversion efficiency.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Interface effects in ultra-thin films: Magnetic and chemical properties

NASA Astrophysics Data System (ADS)

Park, Sungkyun

When the thickness of a magnetic layer is comparable to (or smaller than) the electron mean free path, the interface between magnetic and non-magnetic layers becomes very important factor to determine magnetic properties of the ultra-thin films. The quality of interface can enhance (or reduce) the desired properties. Several interesting physical phenomena were studied using these interface effects. The magnetic anisotropy of ultra-thin Co films is studied as function of non-magnetic underlayer thickness and non- magnetic overlayer materials using ex situ Brillouin light scattering (BLS). I observed that perpendicular magnetic anisotropy (PMA) increases with underlayer thickness and saturates after 5 ML. This saturation can be understood as a relaxation of the in-plane lattice parameter of Au(111) on top of Cu(111) to its bulk value. For the overlayer study, Cu, Al, and Au are used. An Au overlayer gives the largest PMA due to the largest in-plane lattice mismatch between Co and Au. An unusual effect was found by adding an additional layer on top of the Au overlayer. An additional Al capping layer on top of the Au overlayer reduces the PMA significantly. The possible explanation is that the misfit strain at the interface between the Al and the Au can be propagated through the Au layer to affect the magnetic properties of Co even though the in- plane lattice mismatch is less than 1%. Another interesting problem in interface interdiffusion and thermal stability in magnetic tunnel junction (MTJ) structures is studied using X-ray photoelectron spectroscopy (XPS). Since XPS is a very chemically sensitive technique, it allows us to monitor interface interdiffusion of the MTJ structures as-deposited and during post-deposition processing. For the plasma- oxidized samples, Fe only participates in the oxidation reduction process. In contrast to plasma-oxidized samples, there were no noticeable chemical shifts as- deposited and during post-deposition processing in air- oxidized samples. However, peak intensity variations were observed due to interface interdiffusion.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

PubMed

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

The ZnO-FET Biosensor for Cardiac Troponin I

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md; Nuzaihan, M. N. M.; Gopinath, Subash C. B.; Ruslinda, A. R.; Hashim, U.

2018-03-01

This paper investigates the influence of substrate-gate coupling on the ZnO-FET biosensor’s sensitivity for detection of cardiac troponin I (cTnI), a ‘gold standard’ biomarker for acute myocardial infarction (AMI). The FET-based device with introduction of substrate-gate coupling on p-type silicon-on-insulator (SOI) substrate is fabricated using conventional lithography processes. An n-type zinc oxide (ZnO) thin film deposited via electron-beam evaporator is used as transducer for bridging the source and drain regions. Surface modifications via functionalization with 3-aminopropyltriethoxysilane (APTES) and glutaraldehyde (GA) as chemical linkers, followed by immobilization of cTnI monoclonal antibody (MAb-cTnI) as bio-receptor on the ZnO thin film allow different concentration of cTnI detection with high selectivity. The device’s sensitivity increases up to 9 %·(g/ml)-1 with the increase of the substrate-gate voltage (VSG) up to -10 V at very low limit of detection (LOD) down to 1.6 fg/ml.

Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

PubMed Central

Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

2015-01-01

Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

Deposition and characterization of vanadium oxide based thin films for MOS device applications

NASA Astrophysics Data System (ADS)

Rakshit, Abhishek; Biswas, Debaleen; Chakraborty, Supratic

2018-04-01

Vanadium Oxide films are deposited on Si (100) substrate by reactive RF-sputtering of a pure Vanadium metallic target in an Argon-Oxygen plasma environment. The ratio of partial pressures of Argon to Oxygen in the sputtering-chamber is varied by controlling their respective flow rates and the resultant oxide films are obtained. MOS Capacitor based devices are then fabricated using the deposited oxide films. High frequency Capacitance-Voltage (C-V) and gate current-gate voltage (I-V) measurements reveal a significant dependence of electrical characteristics of the deposited films on their sputtering deposition parameters mainly, the relative content of Argon/Oxygen in the plasma chamber. A noteworthy change in the electrical properties is observed for the films deposited under higher relative oxygen content in the plasma atmosphere. Our results show that reactive sputtering serves as an indispensable deposition-setup for fabricating vanadium oxide based MOS devices tailor-made for Non-Volatile Memory (NVM) applications.

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction

NASA Astrophysics Data System (ADS)

Mohamad, B.; Leroux, C.; Reimbold, G.; Ghibaudo, G.

2018-01-01

For advanced gate stacks, effective work function (WFeff) and equivalent oxide thickness (EOT) are fundamental parameters for technology optimization. On FDSOI transistors, and contrary to the bulk technologies, while EOT can still be extracted at strong inversion from the typical gate-to-channel capacitance (Cgc), it is no longer the case for WFeff due to the disappearance of an observable flat band condition on capacitance characteristics. In this work, a new experimental method, the Cbg(VBG) characteristic, is proposed in order to extract the well flat band condition (VFB, W). This characteristic enables an accurate and direct evaluation of WFeff. Moreover, using the previous extraction of the gate oxide (tfox), and buried oxide (tbox) from typical capacitance characteristics (Cgc and Cbc), it allows the extraction of the channel thickness (tch). Furthermore, the measurement of the well flat band condition on Cbg(VBG) characteristics for two different Si and SiGe channel also proves the existence of a dipole at the SiGe/SiO2 interface.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Jong Woo; Nathan, Arokia, E-mail: an299@cam.ac.uk; Barquinha, Pedro

2016-08-15

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (V{sub TH}) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarizationmore » density. The second type of anomaly is negative V{sub TH} shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H{sub 2}O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.« less

On-chip surface modified nanostructured ZnO as functional pH sensors

NASA Astrophysics Data System (ADS)

Zhang, Qing; Liu, Wenpeng; Sun, Chongling; Zhang, Hao; Pang, Wei; Zhang, Daihua; Duan, Xuexin

2015-09-01

Zinc oxide (ZnO) nanostructures are promising candidates as electronic components for biological and chemical applications. In this study, ZnO ultra-fine nanowire (NW) and nanoflake (NF) hybrid structures have been prepared by Au-assisted chemical vapor deposition (CVD) under ambient pressure. Their surface morphology, lattice structures, and crystal orientation were investigated by scanning electron microscopy (SEM), x-ray diffraction (XRD), and transmission electron microscopy (TEM). Two types of ZnO nanostructures were successfully integrated as gate electrodes in extended-gate field-effect transistors (EGFETs). Due to the amphoteric properties of ZnO, such devices function as pH sensors. We found that the ultra-fine NWs, which were more than 50 μm in length and less than 100 nm in diameter, performed better in the pH sensing process than NW-NF hybrid structures because of their higher surface-to-volume ratio, considering the Nernst equation and the Gouy-Chapman-Stern model. Furthermore, the surface coating of (3-Aminopropyl)triethoxysilane (APTES) protects ZnO nanostructures in both acidic and alkaline environments, thus enhancing the device stability and extending its pH sensing dynamic range.

Fabrication of Ultra-thin Color Films with Highly Absorbing Media Using Oblique Angle Deposition.

PubMed

Yoo, Young Jin; Lee, Gil Ju; Jang, Kyung-In; Song, Young Min

2017-08-29

Ultra-thin film structures have been studied extensively for use as optical coatings, but performance and fabrication challenges remain.  We present an advanced method for fabricating ultra-thin color films with improved characteristics. The proposed process addresses several fabrication issues, including large area processing. Specifically, the protocol describes a process for fabricating ultra-thin color films using an electron beam evaporator for oblique angle deposition of germanium (Ge) and gold (Au) on silicon (Si) substrates.  Film porosity produced by the oblique angle deposition induces color changes in the ultra-thin film. The degree of color change depends on factors such as deposition angle and film thickness. Fabricated samples of the ultra-thin color films showed improved color tunability and color purity. In addition, the measured reflectance of the fabricated samples was converted into chromatic values and analyzed in terms of color. Our ultra-thin film fabricating method is expected to be used for various ultra-thin film applications such as flexible color electrodes, thin film solar cells, and optical filters. Also, the process developed here for analyzing the color of the fabricated samples is broadly useful for studying various color structures.

Bi-layer channel structure-based oxide thin-film transistors consisting of ZnO and Al-doped ZnO with different Al compositions and stacking sequences

NASA Astrophysics Data System (ADS)

Cho, Sung Woon; Yun, Myeong Gu; Ahn, Cheol Hyoun; Kim, So Hee; Cho, Hyung Koun

2015-03-01

Zinc oxide (ZnO)-based bi-layers, consisting of ZnO and Al-doped ZnO (AZO) layers grown by atomic layer deposition, were utilized as the channels of oxide thin-film transistors (TFTs). Thin AZO layers (5 nm) with different Al compositions (5 and 14 at. %) were deposited on top of and beneath the ZnO layers in a bi-layer channel structure. All of the bi-layer channel TFTs that included the AZO layers showed enhanced stability (Δ V Th ≤ 3.2 V) under a positive bias stress compared to the ZnO single-layer channel TFT (Δ V Th = 4.0 V). However, the AZO/ZnO bi-layer channel TFTs with an AZO interlayer between the gate dielectric and the ZnO showed a degraded field effect mobility (0.3 cm2/V·s for 5 at. % and 1.8 cm2/V·s for 14 at. %) compared to the ZnO single-layer channel TFT (5.5 cm2/V·s) due to increased scattering caused by Al-related impurities near the gate dielectric/channel interface. In contrast, the ZnO/AZO bi-layer channel TFTs with an AZO layer on top of the ZnO layer exhibited an improved field effect mobility (7.8 cm2/V·s for 14 at. %) and better stability. [Figure not available: see fulltext.

Comparison and characterization of different tunnel layers, suitable for passivated contact formation

NASA Astrophysics Data System (ADS)

Ling, Zhi Peng; Xin, Zheng; Ke, Cangming; Jammaal Buatis, Kitz; Duttagupta, Shubham; Lee, Jae Sung; Lai, Archon; Hsu, Adam; Rostan, Johannes; Stangl, Rolf

2017-08-01

Passivated contacts for solar cells can be realized using a variety of differently formed ultra-thin tunnel oxide layers. Assessing their interface properties is important for optimization purposes. In this work, we demonstrate the ability to measure the interface defect density distribution D it(E) and the fixed interface charge density Q f for ultra-thin passivation layers operating within the tunnel regime (<2 nm). Various promising tunnel layer candidates [i.e., wet chemically formed SiO x , UV photo-oxidized SiO x , and atomic layer deposited (ALD) AlO x ] are investigated for their potential application forming electron or hole selective tunnel layer passivated contacts. In particular, ALD AlO x is identified as a promising tunnel layer candidate for hole-extracting passivated contact formation, stemming from its high (negative) fixed interface charge density in the order of -6 × 1012 cm-2. This is an order of magnitude higher compared to wet chemically or UV photo-oxidized formed silicon oxide tunnel layers, while keeping the density of interface defect states D it at a similar level (in the order of ˜2 × 1012 cm-2 eV-1). This leads to additional field effect passivation and therefore to significantly higher measured effective carrier lifetimes (˜2 orders of magnitude). A surface recombination velocity of ˜40 cm/s has been achieved for a 1.5 nm thin ALD AlO x tunnel layer prior to capping by an additional hole transport material, like p-doped poly-Si or PEDOT:PSS.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ao; Liu, Guoxia, E-mail: gxliu@qdu.edu.cn, E-mail: fukaishan@yahoo.com; Zhu, Huihui

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiO{sub x}) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiO{sub x} TFTs, together with the characteristics of NiO{sub x} thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric, the electrical performance of NiO{sub x} TFT was improved significantly compared with those based on SiO{submore » 2} dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm{sup 2}/V s, which is mainly beneficial from the high areal capacitance of the Al{sub 2}O{sub 3} dielectric and high-quality NiO{sub x}/Al{sub 2}O{sub 3} interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.« less

Coaxially gated in-wire thin-film transistors made by template assembly.

PubMed

Kovtyukhova, Nina I; Kelley, Brian K; Mallouk, Thomas E

2004-10-13

Nanowire field effect transistors were prepared by a wet chemical template replication method using anodic aluminum oxide membranes. The membrane pores were first lined with a thin SiO2 layer by the surface sol-gel method. Au, CdS (or CdSe), and Au wire segments were then sequentially electrodeposited within the pores, and the resulting nanowires were released by dissolution of the membrane. Electrofluidic alignment of these nanowires between source and drain leads and evaporation of gold over the central CdS (CdSe) stripe affords a "wrap-around gate" structure. At VDS = -2 V, the Au/CdS/Au devices had an ON/OFF current ratio of 103, a threshold voltage of 2.4 V, and a subthreshold slope of 2.2 V/decade. A 3-fold decrease in the subthreshold slope relative to that of planar nanocrystalline CdSe devices can be attributed to coaxial gating. The control of dimensions afforded by template synthesis should make it possible to reduce the gate dielectric thickness, channel length, and diameter of the semiconductor segment to sublithographic dimensions while retaining the simplicity of the wet chemical synthetic method.

A Survey of Solid-State Microwave Power Devices

DTIC Science & Technology

1977-04-29

from the channel by a thin oxide layer (insulated gate FET or IGFET), it may be a diffused junction at the top of the channel (junction FET or JFET...greater than 100 GHz. YIG-tuned units are finding increasing use as extremely stable sources, whereas varactor tuning is used where tuning speed is

Stability study of solution-processed zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Zhang, Xue; Ndabakuranye, Jean Pierre; Kim, Dong Wook; Choi, Jong Sun; Park, Jaehoon

2015-11-01

In this study, the environmental dependence of the electrical stability of solution-processed n-channel zinc tin oxide (ZTO) thin-film transistors (TFTs) is reported. Under a prolonged negative gate bias stress, a negative shift in threshold voltage occurs in atmospheric air, whereas a negligible positive shift in threshold voltage occurs under vacuum. In the positive bias-stress experiments, a positive shift in threshold voltage was invariably observed both in atmospheric air and under vacuum. In this study, the negative gate-bias-stress-induced instability in atmospheric air is explained through an internal potential in the ZTO semiconductor, which can be generated owing to the interplay between H2O molecules and majority carrier electrons at the surface of the ZTO film. The positive bias-stress-induced instability is ascribed to electron-trapping phenomenon in and around the TFT channel region, which can be further augmented in the presence of air O2 molecules. These results suggest that the interaction between majority carriers and air molecules will have crucial implications for a reliable operation of solution-processed ZTO TFTs. [Figure not available: see fulltext.

Characterizing the structure of topological insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Richardella, Anthony; Kandala, Abhinav; Lee, Joon Sue

2015-08-01

We describe the characterization of structural defects that occur during molecular beam epitaxy of topological insulator thin films on commonly used substrates. Twinned domains are ubiquitous but can be reduced by growth on smooth InP (111)A substrates, depending on details of the oxide desorption. Even with a low density of twins, the lattice mismatch between (Bi, Sb){sub 2}Te{sub 3} and InP can cause tilts in the film with respect to the substrate. We also briefly discuss transport in simultaneously top and back electrically gated devices using SrTiO{sub 3} and the use of capping layers to protect topological insulator films frommore » oxidation and exposure.« less

Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax

PubMed Central

Lyu, Hongming; Lu, Qi; Liu, Jinbiao; Wu, Xiaoming; Zhang, Jinyu; Li, Junfeng; Niu, Jiebin; Yu, Zhiping; Wu, Huaqiang; Qian, He

2016-01-01

In order to conquer the short-channel effects that limit conventional ultra-scale semiconductor devices, two-dimensional materials, as an option of ultimate thin channels, receive wide attention. Graphene, in particular, bears great expectations because of its supreme carrier mobility and saturation velocity. However, its main disadvantage, the lack of bandgap, has not been satisfactorily solved. As a result, maximum oscillation frequency (fmax) which indicates transistors’ power amplification ability has been disappointing. Here, we present submicron field-effect transistors with specially designed low-resistance gate and excellent source/drain contact, and therefore significantly improved fmax. The fabrication was assisted by the advanced 8-inch CMOS back-end-of-line technology. A 200-nm-gate-length GFET achieves fT/fmax = 35.4/50 GHz. All GFET samples with gate lengths ranging from 200 nm to 400 nm possess fmax 31–41% higher than fT, closely resembling Si n-channel MOSFETs at comparable technology nodes. These results re-strengthen the promise of graphene field-effect transistors in next generation semiconductor electronics. PMID:27775009

A study on the optics of copper indium gallium (di)selenide (CIGS) solar cells with ultra-thin absorber layers.

PubMed

Xu, Man; Wachters, Arthur J H; van Deelen, Joop; Mourad, Maurice C D; Buskens, Pascal J P

2014-03-10

We present a systematic study of the effect of variation of the zinc oxide (ZnO) and copper indium gallium (di)selenide (CIGS) layer thickness on the absorption characteristics of CIGS solar cells using a simulation program based on finite element method (FEM). We show that the absorption in the CIGS layer does not decrease monotonically with its layer thickness due to interference effects. Ergo, high precision is required in the CIGS production process, especially when using ultra-thin absorber layers, to accurately realize the required thickness of the ZnO, cadmium sulfide (CdS) and CIGS layer. We show that patterning the ZnO window layer can strongly suppress these interference effects allowing a higher tolerance in the production process.

UTBB FDSOI: Evolution and opportunities

NASA Astrophysics Data System (ADS)

Monfray, Stephane; Skotnicki, Thomas

2016-11-01

As today's 28 nm FDSOI (Fully Depleted Silicon On Insulator) technology is at the industrialization level, this paper aims to summarize the key advantages allowed by the thin BOX (Buried Oxide) of the FDSOI, through the technology evolution but also new opportunities, among logic applications and extending the possibilities offered by the platform. We will summarize how the advantages provided by the thin BOX have been first explored and developed, and how the back biasing techniques are the key to the outstanding performances provided by the FDSOI at low voltage. Then, as the FDSOI technology is also a solution to develop innovative platforms and applications, we will detail some opportunities. In particular, we will present monolithic 3D integration, ultra-low power devices for IoT (Internet of Things) and ultra-sensitive sensors.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

Enhancing the carbon capture capacities of a rigid ultra-microporous MOF through gate-opening at low CO2 pressures assisted by swiveling oxalate pillars.

PubMed

Banerjee, Aparna; Nandi, Shyamapada; Nasa, Parveen; Vaidhyanathan, Ramanathan

2016-01-31

Porosity enhancement assisted by an unusual gate opening has been realized in an exceptionally rigid ultra-microporous framework. The gate-opening has been attributed to the presence of symmetrically positioned Zn-O bonds of the Zn-oxalate units that facilitate subtle swiveling motion resulting in a drastic improvement (42%) in the CO2 capacity without compromising the CO2/N2 selectivity.

Restorative effect of oxygen annealing on device performance in HfIZO thin-film transistors

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2015-03-01

Metal-oxide based thin-film transistors (oxide-TFTs) are very promising for use in next generation electronics such as transparent displays requiring high switching and driving performance. In this study, we demonstrate an optimized process to secure excellent device performance with a favorable shift of the threshold voltage toward 0V in amorphous hafnium-indium-zinc-oxide (a-HfIZO) TFTs by using post-treatment with oxygen annealing. This enhancement results from the improved interfacial characteristics between gate dielectric and semiconductor layers due to the reduction in the density of interfacial states related to oxygen vacancies afforded by oxygen annealing. The device statistics confirm the improvement in the device-to-device and run-to-run uniformity. We also report on the photo-induced stability in such oxide-TFTs against long-term UV irradiation, which is significant for transparent displays.

Polydiacetylene as an all-optical picosecond Switch

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin A.; Frazier, D. O.; Paley, M. S.; Whitaker, Ann F. (Technical Monitor)

2001-01-01

Polydiacetylene derivative of 2-methyl-4-nitroaniline (PDAMNA) shows a picosecond switching property, which illustrated a partial all-optical picosecond NAND logic gate. The switching phenomenon was demonstrated by waveguiding two collinear beams at 633 nm and 532 nm through a hollow fiber of 50 micrometers diameter, coated from inside with a thin film of PDAMNA. A Z-scan investigations of a PDAMNA thin film on quartz substrate revealed that the switching effect was attributed to an excited state absorption in the systems. The studies also showed that the polymer suffers a photo-oxidation beyond an intensity level of 2.9 x 10(exp 6) w/square cm. The photo-oxidized film has different physical properties that are different from the original film before oxidation. The life time of both excited states before and after oxidation as well as their absorption coefficients were estimated by fitting a three level system model to the experimental results.

Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

DTIC Science & Technology

1993-04-01

CLASSIFICATION 18. SECURITY CLASSIFICATION 19. SECURIlY CLASSIFICATION 20. UMITATION OF ABSTRACT OF REPORT OF THIS PAGE OF ABSTRACT UNCLASSIFIED UNCLASSIFIED...with the silicon underneath, growing a thin nitride layer. This layer of Si 3 N 4 , if not completely removed, will retard oxidation in the area...C. Shatas, K. C. Saraswat and J. D. Meindl, "Interfacial and Breakdown Characteristics of MOS Devices with Rapidly Grown Ultrathin SiO Gate

Optimal thickness of silicon membranes to achieve maximum thermoelectric efficiency: A first principles study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mangold, Claudia; Neogi, Sanghamitra; Max Planck Institut für Polymerforschung, Ackermannweg 10, D-55128 Mainz

2016-08-01

Silicon nanostructures with reduced dimensionality, such as nanowires, membranes, and thin films, are promising thermoelectric materials, as they exhibit considerably reduced thermal conductivity. Here, we utilize density functional theory and Boltzmann transport equation to compute the electronic properties of ultra-thin crystalline silicon membranes with thickness between 1 and 12 nm. We predict that an optimal thickness of ∼7 nm maximizes the thermoelectric figure of merit of membranes with native oxide surface layers. Further thinning of the membranes, although attainable in experiments, reduces the electrical conductivity and worsens the thermoelectric efficiency.

Fabrication of one-transistor-capacitor structure of nonvolatile TFT ferroelectric RAM devices using Ba(Zr0.1Ti0.9)O3 gated oxide film.

PubMed

Yang, Cheng-Fu; Chen, Kai-Huang; Chen, Ying-Chung; Chang, Ting-Chang

2007-09-01

In this study, the Ba(Zr0.1Ti0.9)O3 (BZ1T9) thin films have been well deposited on the Pt/Ti/SiO2/Si substrate. The optimum radio frequency (RF) deposition parameters are developed, and the BZ1T9 thin films deposition at the optimum parameters have the maximum capacitance and dielectric constant of 4.4 nF and 190. As the applied voltage is increased to 8 V, the remnant polarization and coercive field of BZ1T9 thin films are about 4.5 microC/cm2 and 80 kV/cm. The counterclockwise current hysteresis and memory window of n-channel thin-film transistor property are observed, and that can be used to indicate the switching of ferroelectric polarization of BZ1T9 thin films. One-transistor-capacitor (1TC) structure of BZ1T9 ferroelectric random access memory device using bottom-gate amorphous silicon thin-film transistor was desirable because of the smaller size and better sensitivity. The BZ1T9 ferroelectric RAM devices with channel width = 40 microm and channel length = 8 microm has been successfully fabricated and the ID-VG transfer characteristics also are investigated in this study.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

NASA Astrophysics Data System (ADS)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p-channel MOSFETs. Band engineering, strain induced valence band splitting and quantum confinement is used to improve channel hole mobility. Experimental results on the Hall hole mobility is presented for InxGa1-xAs channels with varying In content, thickness of the quantum well and temperature. Then, high mobility InxGa 1-xAs heterostructure thus obtained are integrated with in-situ deposited high-k gate oxide required for high performance p-MOSFET and discuss the challenges associated with the gated structure and draw conclusions on this material system. Antimonide based channel materials such as GaSb and InxGa 1-xSb are explored for III-V based p-MOSFETs in last two chapters. Options for Sb based strained QW channels to obtain maximum hole mobility by varying the strain, channel and barrier material, thickness of the layers etc. is discussed followed by the growth of these Sb channels on GaAs and InP substrates using molecular beam epitaxy. The physical properties of the structures such as the heterostructure quality, alloy content and surface roughness are examined via TEM, XRD and AFM. Following this, electrical measurement results on Hall hole mobility is presented. The effect of strain, alloy content, temperature and thickness on channel mobility and concentration is reported. Development of GaSb n- and p-MOS capacitor structures with in-situ deposited HfO2 gate oxide dielectric using in-situ deposited amorphous Si (a-Si) interface passivation layer (IPL) to improve the interface quality of high-k oxide and (In)GaSb surface is presented. In-situ deposited gate oxides such as Al2O3 and combination oxide of Al 2O3 and HfO2 with and without the a-Si IPL are also explored as alternate gate dielectrics. Subsequently, MOS capacitor structures using buried InGaSb QWs are demonstrated. Development of an inversion type bulk GaSb with implanted source-drain contacts and in-situ deposited gate oxide HfO2 gate oxide is discussed. The merits of biaxial compressive strain is demonstrated on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

Zinc Oxide Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Fortunato, E.; Barquinha, P.; Pimentel, A.; Gonçalves, A.; Marques, A.; Pereira, L.; Martins, R.

ZnO thin film transistors (ZnO-TFT) have been fabricated by rf magnetron sputtering at room temperature with a bottom-gate configuration. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 21 V, a field effect mobility of 20 cm2/Vs, a gate voltage swing of 1.24 V/decade and an on/off ratio of 2×105. The ZnO-TFT present an average optical transmission (including the glass substrate) of 80 % in the visible part of the spectrum. The combination of transparency, high channel mobility and room temperature processing makes the ZnO-TFT a very promising low cost optoelectronic device for the next generation of invisible and flexible electronics. Moreover, the processing technology used to fabricate this device is relatively simple and it is compatible with inexpensive plastic/flexible substrate technology.

Electrochemical Corrosion Properties of Commercial Ultra-Thin Copper Foils

NASA Astrophysics Data System (ADS)

Yen, Ming-Hsuan; Liu, Jen-Hsiang; Song, Jenn-Ming; Lin, Shih-Ching

2017-08-01

Ultra-thin electrodeposited Cu foils have been developed for substrate thinning for mobile devices. Considering the corrosion by residual etchants from the lithography process for high-density circuit wiring, this study investigates the microstructural features of ultra-thin electrodeposited Cu foils with a thickness of 3 μm and their electrochemical corrosion performance in CuCl2-based etching solution. X-ray diffraction and electron backscatter diffraction analyses verify that ultra-thin Cu foils exhibit a random texture and equi-axed grains. Polarization curves show that ultra-thin foils exhibit a higher corrosion potential and a lower corrosion current density compared with conventional (220)-oriented foils with fan-like distributed fine-elongated columnar grains. Chronoamperometric results also suggest that ultra-thin foils possess superior corrosion resistance. The passive layer, mainly composed of CuCl and Cu2O, forms and dissolves in sequence during polarization.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Leakage current conduction and reliability assessment of passivating thin silicon dioxide films on n-4H-SiC

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2016-09-01

We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO2) films grown on (0 0 0 1) silicon (Si) face of n-type 4H-SiC (silicon carbide). It was observed that the experimentally measured gate current density in metal-oxide-silicon carbide (MOSiC) structures under positive gate bias at an oxide field Eox above 5 MV/cm is comprised of Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps in the SiO2 gap, IFN and IPF, respectively at temperatures between 27 and 200 °C. In MOSiC structures, PF mechanism dominates FN tunneling of electrons from the accumulation layer of n-4H-SiC due to high density (up to 1013 cm-2) of carbon-related acceptor-like traps located at about 2.5 eV below the SiO2 conduction band (CB). These current conduction mechanisms were taken into account in studying hole injection/trapping into 10 nm-thick tunnel oxide on the Si face of 4H-SiC during electron injection from n-4H-SiC under high-field electrical stress with positive bias on the heavily doped n-type polysilicon (n+-polySi) gate at a wide range of temperatures between 27 and 200 °C. Holes were generated in the n+-polySi anode material by the hot-electrons during their transport through thin oxide films at oxide electric fields Eox from 5.6 to 8.0 MV/cm (prior to the intrinsic oxide breakdown field). Time-to-breakdown tBD of the gate dielectric was found to follow reciprocal field (1/E) model irrespective of stress temperatures. Despite the significant amount of process-induced interfacial electron traps contributing to a large amount of leakage current via PF emission in thermally grown SiO2 on the Si-face of n-4H-SiC, MOSiC devices having a 10 nm-thick SiO2 film can be safely used in 5 V TTL logic circuits over a period of 10 years.

Bulk and Thin Film Synthesis of Compositionally Variant Entropy-stabilized Oxides.

PubMed

Sivakumar, Sai; Zwier, Elizabeth; Meisenheimer, Peter Benjamin; Heron, John T

2018-05-29

Here, we present a procedure for the synthesis of bulk and thin film multicomponent (Mg0.25(1-x)CoxNi0.25(1-x)Cu0.25(1-x)Zn0.25(1-x))O (Co variant) and (Mg0.25(1-x)Co0.25(1-x)Ni0.25(1-x)CuxZn0.25(1-x))O (Cu variant) entropy-stabilized oxides. Phase pure and chemically homogeneous (Mg0.25(1-x)CoxNi0.25(1-x)Cu0.25(1-x)Zn0.25(1-x))O (x = 0.20, 0.27, 0.33) and (Mg0.25(1-x)Co0.25(1-x)Ni0.25(1-x)CuxZn0.25(1-x))O (x = 0.11, 0.27) ceramic pellets are synthesized and used in the deposition of ultra-high quality, phase pure, single crystalline thin films of the target stoichiometry. A detailed methodology for the deposition of smooth, chemically homogeneous, entropy-stabilized oxide thin films by pulsed laser deposition on (001)-oriented MgO substrates is described. The phase and crystallinity of bulk and thin film materials are confirmed using X-ray diffraction. Composition and chemical homogeneity are confirmed by X-ray photoelectron spectroscopy and energy dispersive X-ray spectroscopy. The surface topography of thin films is measured with scanning probe microscopy. The synthesis of high quality, single crystalline, entropy-stabilized oxide thin films enables the study of interface, size, strain, and disorder effects on the properties in this new class of highly disordered oxide materials.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leng, X.; Pereiro, J.; Strle, J.

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Liquid metals as ultra-stretchable, soft, and shape reconfigurable conductors

NASA Astrophysics Data System (ADS)

Eaker, Collin B.; Dickey, Michael D.

2015-05-01

Conventional, rigid materials remain the key building blocks of most modern electronic devices, but they are limited in their ability to conform to curvilinear surfaces. It is possible to make electronic components that are flexible and in some cases stretchable by utilizing thin films, engineered geometries, or inherently soft and stretchable materials that maintain their function during deformation. Here, we describe the properties and applications of a micromoldable liquid metal that can form conductive components that are ultra-stretchable, soft, and shape-reconfigurable. This liquid metal is a gallium-based alloy with low viscosity and high conductivity. The metal develops spontaneously a thin, passivating oxide layer on the surface that allows the metal to be molded into non-spherical shapes, including films and wires, and patterned by direct-write techniques or microfluidic injection. Furthermore, unlike mercury, the liquid metal has low toxicity and negligible vapor pressure. This paper discusses the mechanical and electrical properties of the metal in the context of electronics, and discusses how the properties of the oxide layer have been exploited for new patterning techniques that enable soft, stretchable and reconfigurable devices.

Atomic Layer Deposition of HfO2 and Si Nitride on Ge Substrates

NASA Astrophysics Data System (ADS)

Zhu, Shiyang; Nakajima, Anri

2007-12-01

Hafnium oxide (HfO2) thin films were deposited on Ge substrates at 300 °C using atomic layer deposition (ALD) with tetrakis(diethylamino)hafnium (termed as TDEAH) as a precursor and water as an oxidant. The deposition rate was estimated to be 0.09 nm/cycle and the deposited HfO2 films have a smooth surface and an almost stoichiometric composition, indicating that the growth follows a layer-by-layer kinetics, similarly to that on Si substrates. Si nitride thin films were also deposited on Ge by ALD using SiCl4 as a precursor and NH3 as an oxidant. Si nitride has a smaller deposition rate of about 0.055 nm/cycle and a larger gate leakage current than HfO2 deposited on Ge by ALD.

An ultra-thin, un-doped NiO hole transporting layer of highly efficient (16.4%) organic-inorganic hybrid perovskite solar cells.

PubMed

Seo, Seongrok; Park, Ik Jae; Kim, Myungjun; Lee, Seonhee; Bae, Changdeuck; Jung, Hyun Suk; Park, Nam-Gyu; Kim, Jin Young; Shin, Hyunjung

2016-06-02

NiO is a wide band gap p-type oxide semiconductor and has potential for applications in solar energy conversion as a hole-transporting layer (HTL). It also has good optical transparency and high chemical stability, and the capability of aligning the band edges to the perovskite (CH3NH3PbI3) layers. Ultra-thin and un-doped NiO films with much less absorption loss were prepared by atomic layer deposition (ALD) with highly precise control over thickness without any pinholes. Thin enough (5-7.5 nm in thickness) NiO films with the thickness of few time the Debye length (LD = 1-2 nm for NiO) show enough conductivities achieved by overlapping space charge regions. The inverted planar perovskite solar cells with NiO films as HTLs exhibited the highest energy conversion efficiency of 16.40% with high open circuit voltage (1.04 V) and fill factor (0.72) with negligible current-voltage hysteresis.

Highly-flexible, ultra-thin, and transparent single-layer graphene/silver composite electrodes for organic light emitting diodes

NASA Astrophysics Data System (ADS)

Li, Kun; Wang, Hu; Li, Huiying; Li, Ye; Jin, Guangyong; Gao, Lanlan; Marco, Mazzeo; Duan, Yu

2017-08-01

Transparent conductive electrode (TCE) platforms are required in many optoelectronic devices, including organic light emitting diodes (OLEDs). To date, indium tin oxide based electrodes are widely used in TCEs but they still have few limitations in term of achieving flexible OLEDs and display techniques. In this paper, highly-flexible and ultra-thin TCEs were fabricated for use in OLEDs by combining single-layer graphene (SLG) with thin silver layers of only several nanometers in thickness. The as-prepared SLG + Ag (8 nm) composite electrodes showed low sheet resistances of 8.5 Ω/□, high stability over 500 bending cycles, and 74% transmittance at 550 nm wavelength. Furthermore, SLG + Ag composite electrodes employed as anodes in OLEDs delivered turn-on voltages of 2.4 V, with luminance exceeding 1300 cd m-2 at only 5 V, and maximum luminance reaching up 40 000 cd m-2 at 9 V. Also, the devices could work normally under less than the 1 cm bending radius.

Low voltage-driven oxide phototransistors with fast recovery, high signal-to-noise ratio, and high responsivity fabricated via a simple defect-generating process

PubMed Central

Yun, Myeong Gu; Kim, Ye Kyun; Ahn, Cheol Hyoun; Cho, Sung Woon; Kang, Won Jun; Cho, Hyung Koun; Kim, Yong-Hoon

2016-01-01

We have demonstrated that photo-thin film transistors (photo-TFTs) fabricated via a simple defect-generating process could achieve fast recovery, a high signal to noise (S/N) ratio, and high sensitivity. The photo-TFTs are inverted-staggered bottom-gate type indium-gallium-zinc-oxide (IGZO) TFTs fabricated using atomic layer deposition (ALD)-derived Al2O3 gate insulators. The surfaces of the Al2O3 gate insulators are damaged by ion bombardment during the deposition of the IGZO channel layers by sputtering and the damage results in the hysteresis behavior of the photo-TFTs. The hysteresis loops broaden as the deposition power density increases. This implies that we can easily control the amount of the interface trap sites and/or trap sites in the gate insulator near the interface. The photo-TFTs with large hysteresis-related defects have high S/N ratio and fast recovery in spite of the low operation voltages including a drain voltage of 1 V, positive gate bias pulse voltage of 3 V, and gate voltage pulse width of 3 V (0 to 3 V). In addition, through the hysteresis-related defect-generating process, we have achieved a high responsivity since the bulk defects that can be photo-excited and eject electrons also increase with increasing deposition power density. PMID:27553518

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Solution-processed high-mobility neodymium-substituted indium oxide thin-film transistors formed by facile patterning based on aqueous precursors

NASA Astrophysics Data System (ADS)

Lin, Zhenguo; Lan, Linfeng; Sun, Sheng; Li, Yuzhi; Song, Wei; Gao, Peixiong; Song, Erlong; Zhang, Peng; Li, Meiling; Wang, Lei; Peng, Junbiao

2017-03-01

Solution-processed neodymium-substituted indium oxide (InNdO) thin-film transistors (TFTs) based on gel-like aqueous precursors were fabricated with a surface-selective deposition technique associated with ultraviolet irradiation. The Nd concentration can be easily tuned by changing the ratio of Nd2O3 to In2O3 precursors. It was found that Nd played roles of suppressing grain growth, suppressing oxygen vacancy formation, and increasing the electrical stability of TFTs. The InNdO TFT with a Nd:In ratio of 0.02:1 exhibited a mobility of as high as 15.6 cm2 V-1 s-1 with improved stability under gate-bias stress.

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. Themore » device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.« less

Low-Voltage InGaZnO Thin Film Transistors with Small Sub-Threshold Swing.

PubMed

Cheng, C H; Chou, K I; Hsu, H H

2015-02-01

We demonstrate a low-voltage driven, indium-gallium-zinc oxide thin-film transistor using high-κ LaAlO3 gate dielectric. A low VT of 0.42 V, very small sub-threshold swing of 68 mV/dec, field-effect mobility of 4.1 cm2/Ns and low operation voltage of 1.4 V were reached simultaneously in LaAlO3/IGZO TFT device. This low-power and small SS TFT has the potential for fast switching speed and low power applications.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

Characterization of ultrathin SOI film and application to short channel MOSFETs.

PubMed

Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

2008-04-23

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

Ultra-long Pt nanolawns supported on TiO2-coated carbon fibers as 3D hybrid catalyst for methanol oxidation

PubMed Central

2012-01-01

In this study, TiO2 thin film photocatalyst on carbon fibers was used to synthesize ultra-long single crystalline Pt nanowires via a simple photoreduction route (thermally activated photoreduction). It also acted as a co-catalytic material with Pt. Taking advantage of the high-aspect ratio of the Pt nanostructure as well as the excellent catalytic activity of TiO2, this hybrid structure has the great potential as the active anode in direct methanol fuel cells. The electrochemical results indicate that TiO2 is capable of transforming CO-like poisoning species on the Pt surface during methanol oxidation and contributes to a high CO tolerance of this Pt nanowire/TiO2 hybrid structure. PMID:22546416

Ultra-long Pt nanolawns supported on TiO2-coated carbon fibers as 3D hybrid catalyst for methanol oxidation

NASA Astrophysics Data System (ADS)

Shen, Yu-Lin; Chen, Shih-Yun; Song, Jenn-Ming; Chen, In-Gann

2012-06-01

In this study, TiO2 thin film photocatalyst on carbon fibers was used to synthesize ultra-long single crystalline Pt nanowires via a simple photoreduction route (thermally activated photoreduction). It also acted as a co-catalytic material with Pt. Taking advantage of the high-aspect ratio of the Pt nanostructure as well as the excellent catalytic activity of TiO2, this hybrid structure has the great potential as the active anode in direct methanol fuel cells. The electrochemical results indicate that TiO2 is capable of transforming CO-like poisoning species on the Pt surface during methanol oxidation and contributes to a high CO tolerance of this Pt nanowire/TiO2 hybrid structure.

High Responsivity MgZnO Ultraviolet Thin-Film Phototransistor Developed Using Radio Frequency Sputtering

PubMed Central

Li, Jyun-Yi; Chang, Sheng-Po; Hsu, Ming-Hung; Chang, Shoou-Jinn

2017-01-01

We investigated the electrical and optoelectronic properties of a magnesium zinc oxide thin-film phototransistor. We fabricate an ultraviolet phototransistor by using a wide-bandgap MgZnO thin film as the active layer material of the thin film transistor (TFT). The fabricated device demonstrated a threshold voltage of 3.1 V, on–off current ratio of 105, subthreshold swing of 0.8 V/decade, and mobility of 5 cm2/V·s in a dark environment. As a UV photodetector, the responsivity of the device was 3.12 A/W, and the rejection ratio was 6.55 × 105 at a gate bias of −5 V under 290 nm illumination. PMID:28772487

High Responsivity MgZnO Ultraviolet Thin-Film Phototransistor Developed Using Radio Frequency Sputtering.

PubMed

Li, Jyun-Yi; Chang, Sheng-Po; Hsu, Ming-Hung; Chang, Shoou-Jinn

2017-02-04

We investigated the electrical and optoelectronic properties of a magnesium zinc oxide thin-film phototransistor. We fabricate an ultraviolet phototransistor by using a wide-bandgap MgZnO thin film as the active layer material of the thin film transistor (TFT). The fabricated device demonstrated a threshold voltage of 3.1 V, on-off current ratio of 10⁵, subthreshold swing of 0.8 V/decade, and mobility of 5 cm²/V·s in a dark environment. As a UV photodetector, the responsivity of the device was 3.12 A/W, and the rejection ratio was 6.55 × 10⁵ at a gate bias of -5 V under 290 nm illumination.

Thin films of fullerene-like MoS2 nanoparticles with ultra-low friction and wear

PubMed

Chhowalla; Amaratunga

2000-09-14

The tribological properties of solid lubricants such as graphite and the metal dichalcogenides MX2 (where M is molybdenum or tungsten and X is sulphur or selenium) are of technological interest for reducing wear in circumstances where liquid lubricants are impractical, such as in space technology, ultra-high vacuum or automotive transport. These materials are characterized by weak interatomic interactions (van der Waals forces) between their layered structures, allowing easy, low-strength shearing. Although these materials exhibit excellent friction and wear resistance and extended lifetime in vacuum, their tribological properties remain poor in the presence of humidity or oxygen, thereby limiting their technological applications in the Earth's atmosphere. But using MX2 in the form of isolated inorganic fullerene-like hollow nanoparticles similar to carbon fullerenes and nanotubes can improve its performance. Here we show that thin films of hollow MoS2 nanoparticles, deposited by a localized high-pressure arc discharge method, exhibit ultra-low friction (an order of magnitude lower than for sputtered MoS2 thin films) and wear in nitrogen and 45% humidity. We attribute this 'dry' behaviour in humid environments to the presence of curved S-Mo-S planes that prevent oxidation and preserve the layered structure.

Thin films of fullerene-like MoS2 nanoparticles with ultra-low friction and wear

NASA Astrophysics Data System (ADS)

Chhowalla, Manish; Amaratunga, Gehan A. J.

2000-09-01

The tribological properties of solid lubricants such as graphite and the metal dichalcogenides MX2 (where M is molybdenum or tungsten and X is sulphur or selenium) are of technological interest for reducing wear in circumstances where liquid lubricants are impractical, such as in space technology, ultra-high vacuum or automotive transport. These materials are characterized by weak interatomic interactions (van der Waals forces) between their layered structures, allowing easy, low-strength shearing. Although these materials exhibit excellent friction and wear resistance and extended lifetime in vacuum, their tribological properties remain poor in the presence of humidity or oxygen, thereby limiting their technological applications in the Earth's atmosphere. But using MX2 in the form of isolated inorganic fullerene-like hollow nanoparticles similar to carbon fullerenes and nanotubes can improve its performance. Here we show that thin films of hollow MoS2 nanoparticles, deposited by a localized high-pressure arc discharge method, exhibit ultra-low friction (an order of magnitude lower than for sputtered MoS2 thin films) and wear in nitrogen and 45% humidity. We attribute this `dry' behaviour in humid environments to the presence of curved S-Mo-S planes that prevent oxidation and preserve the layered structure.

Ultra-wideband radar motion sensor

DOEpatents

McEwan, Thomas E.

1994-01-01

A motion sensor is based on ultra-wideband (UWB) radar. UWB radar range is determined by a pulse-echo interval. For motion detection, the sensors operate by staring at a fixed range and then sensing any change in the averaged radar reflectivity at that range. A sampling gate is opened at a fixed delay after the emission of a transmit pulse. The resultant sampling gate output is averaged over repeated pulses. Changes in the averaged sampling gate output represent changes in the radar reflectivity at a particular range, and thus motion.

Ultra-wideband radar motion sensor

DOEpatents

McEwan, T.E.

1994-11-01

A motion sensor is based on ultra-wideband (UWB) radar. UWB radar range is determined by a pulse-echo interval. For motion detection, the sensors operate by staring at a fixed range and then sensing any change in the averaged radar reflectivity at that range. A sampling gate is opened at a fixed delay after the emission of a transmit pulse. The resultant sampling gate output is averaged over repeated pulses. Changes in the averaged sampling gate output represent changes in the radar reflectivity at a particular range, and thus motion. 15 figs.

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

NASA Astrophysics Data System (ADS)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-05-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W /L=10μm/50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2/Vs, a subthreshold gate swing value of 0.59V/decade, a thrseshold voltage of 5.9V, and an Ion/off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

NASA Astrophysics Data System (ADS)

Kukita, Kentaro; Uechi, Tadayoshi; Shimokawa, Junji; Goto, Masakazu; Yokota, Yoshinori; Kawanaka, Shigeru; Tanamoto, Tetsufumi; Tanimoto, Hiroyoshi; Takagi, Shinichi

2018-04-01

Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have proposed the formation of a pocket region, which needs very difficult implantation process. In this work, a planar SG Si TFET without pocket was proposed by using the technology computer-aided design (TCAD) simulations. An average S.S. of less than 60 mV/decade for 0.3 V (= V gs = V ds) operation was obtained. It is found that both low average S.S. (= 27.8 mV/decade) and high on-current I on (= 3.8 µA/µm) are achieved without pocket doping by scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length L ov.

High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

NASA Astrophysics Data System (ADS)

Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

2016-02-01

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun

We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al{sub 2}O{sub 3}, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔV{sub th}) was 0 V even after a PBS time (t{sub stress}) of 3000 s under a gate voltage (V{submore » G}) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔV{sub th} value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔV{sub th} values resulting from PBS quantitatively, the average oxide charge trap density (N{sub T}) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N{sub T} resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N{sub T} near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.« less

Electronic Devices Based on Oxide Thin Films Fabricated by Fiber-to-Film Process.

PubMed

Meng, You; Liu, Ao; Guo, Zidong; Liu, Guoxia; Shin, Byoungchul; Noh, Yong-Young; Fortunato, Elvira; Martins, Rodrigo; Shan, Fukai

2018-05-30

Technical development for thin-film fabrication is essential for emerging metal-oxide (MO) electronics. Although impressive progress has been achieved in fabricating MO thin films, the challenges still remain. Here, we report a versatile and general thermal-induced nanomelting technique for fabricating MO thin films from the fiber networks, briefly called fiber-to-film (FTF) process. The high quality of the FTF-processed MO thin films was confirmed by various investigations. The FTF process is generally applicable to numerous technologically relevant MO thin films, including semiconducting thin films (e.g., In 2 O 3 , InZnO, and InZrZnO), conducting thin films (e.g., InSnO), and insulating thin films (e.g., AlO x ). By optimizing the fabrication process, In 2 O 3 /AlO x thin-film transistors (TFTs) were successfully integrated by fully FTF processes. High-performance TFT was achieved with an average mobility of ∼25 cm 2 /(Vs), an on/off current ratio of ∼10 7 , a threshold voltage of ∼1 V, and a device yield of 100%. As a proof of concept, one-transistor-driven pixel circuit was constructed, which exhibited high controllability over the light-emitting diodes. Logic gates based on fully FTF-processed In 2 O 3 /AlO x TFTs were further realized, which exhibited good dynamic logic responses and voltage amplification by a factor of ∼4. The FTF technique presented here offers great potential in large-area and low-cost manufacturing for flexible oxide electronics.

Semiconductor/dielectric interface engineering and characterization

NASA Astrophysics Data System (ADS)

Lucero, Antonio T.

The focus of this dissertation is the application and characterization of several, novel interface passivation techniques for III-V semiconductors, and the development of an in-situ electrical characterization. Two different interface passivation techniques were evaluated. The first is interface nitridation using a nitrogen radical plasma source. The nitrogen radical plasma generator is a unique system which is capable of producing a large flux of N-radicals free of energetic ions. This was applied to Si and the surface was studied using x-ray photoelectron spectroscopy (XPS). Ultra-thin nitride layers could be formed from 200-400° C. Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated using this passivation technique. Interface nitridation was able to reduce leakage current and improve the equivalent oxide thickness of the devices. The second passivation technique studied is the atomic layer deposition (ALD) diethylzinc (DEZ)/water treatment of sulfur treated InGaAs and GaSb. On InGaAs this passivation technique is able to chemically reduce higher oxidation states on the surface, and the process results in the deposition of a ZnS/ZnO interface passivation layer, as determined by XPS. Capacitance-voltage (C-V) measurements of MOSCAPs made on p-InGaAs reveal a large reduction in accumulation dispersion and a reduction in the density of interfacial traps. The same technique was applied to GaSb and the process was studied in an in-situ half-cycle XPS experiment. DEZ/H2O is able to remove all Sb-S from the surface, forming a stable ZnS passivation layer. This passivation layer is resistant to further reoxidation during dielectric deposition. The final part of this dissertation is the design and construction of an ultra-high vacuum cluster tool for in-situ electrical characterization. The system consists of three deposition chambers coupled to an electrical probe station. With this setup, devices can be processed and subsequently electrically characterized without exposing the sample to air. This is the first time that such a system has been reported. A special air-gap C-V probe will allow top gated measurements to be made, allowing semiconductor-dielectric interfaces to be studied during device processing.

Sputtered Thin Film Research

DTIC Science & Technology

1974-11-01

yield (100) oriented wafers, which were lapped and chemi-mechanically polished in sulf uric-peroxide or sodium hypochlorite etches. Prior to mounting...This material will viot oxidize, melt, or diffuse during the subsequent high temperature processing. Platinum silicide contacts are used because...formation of the platinum silicide contacts, the gate region was opened and the wafer was placed in the sput- tering chamber. The same deposition

Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang

We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{submore » O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.« less

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Correlation of film morphology and defect content with the charge-carrier transport in thin-film transistors based on ZnO nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Polster, S.; Jank, M. P. M.; Frey, L.

2016-01-14

The correlation of defect content and film morphology with the charge-carrier transport in field-effect devices based on zinc oxide nanoparticles was investigated. Changes in the defect content and the morphology were realized by annealing and sintering of the nanoparticle thin films. Temperature-dependent electrical measurements reveal that the carrier transport is thermally activated for both the unsintered and sintered thin films. Reduced energetic barrier heights between the particles have been determined after sintering. Additionally, the energetic barrier heights between the particles can be reduced by increasing the drain-to-source voltage and the gate-to-source voltage. The changes in the barrier height are discussedmore » with respect to information obtained by scanning electron microscopy and photoluminescence measurements. It is found that a reduction of surface states and a lower roughness at the interface between the particle layer and the gate dielectric lead to lower barrier heights. Both surface termination and layer morphology at the interface affect the barrier height and thus are the main criteria for mobility improvement and device optimization.« less

Operational stability of solution-processed indium-oxide thin-film transistors: Environmental condition and electrical stress

NASA Astrophysics Data System (ADS)

Baang, Sungkeun; Lee, Hyeonju; Zhang, Xue; Park, Jaehoon; Kim, Won-Pyo; Ko, Young-Woong; Piao, Shang Hao; Choi, Hyoung Jin; Kwon, Jin-Hyuk; Bae, Jin-Hyuk

2018-01-01

We investigate the operational stability of bottom-gate/top-contact-structured indium-oxide (In2O3) thin-film transistors (TFTs) in atmospheric air and under vacuum. Based on the thermogravimetric analysis of the In2O3 precursor solution, we utilize a thermal annealing process at 400 °C for 40 min to prepare the In2O3 films. The results of X-ray photoemission spectroscopy and field-emission scanning electron microscopy show that the electron is the majority carrier in the In2O3 semiconductor film prepared by a spin-coating method and that the film has a polycrystalline morphology with grain boundaries. The fabricated In2O3 TFTs operate in an n-type enhancement mode. When constant drain and gate voltages are applied, these TFTs in atmospheric air exhibit a more acute decay in the drain currents with time compared to that observed under vacuum. In the positive gate-bias stress experiments, a decrease in the field-effect mobility and a positive shift in the threshold voltage are invariably observed both in atmospheric air and under vacuum, but such characteristic variations are also found to be more pronounced for the atmospheric-air case. These results are explained in terms of the electron-trapping phenomenon at the grain boundaries in the In2O3 semiconductor, as well as the electrostatic interactions between electrons and polar water molecules.

PREFACE: Proceedings Symposium G of E-MRS Spring Meeting on Fundamentals and Technology of Multifunctional Oxide Thin Films

NASA Astrophysics Data System (ADS)

2010-07-01

Oxide materials exhibit a large variety of functional properties that are useful in a plethora of applications. Symposium G focused on oxide thin films that include dielectric or switching properties. Its program mirrored very well the strong worldwide search for high-K thin films for gate, memory, and on-chip capacitors, as well as the emerging field of functional thin films for MEMS. A complete session was devoted to the colossal effect of dielectric response in (Ca,Cu)TiO3, representing the major European research groups in this field. A comprehensive overview on this phenomenon was given by D Sinclair J Wolfman presented the latest results on CCTO thin films obtained by wafer scale pulsed laser deposition. A Loidl showed the analytical power of dielectric spectroscopy when covering the complete frequency range from 1-1012 Hz, i.e. from space charge to phonon contributions at the example of CCTO. Another session was devoted to applications in non-volatile memories, covering various effects including ferroelectric and resistive switching, the complex behavior of oxide tunnel junctions (H Kohlstedt), the possibility to manipulate the magnetic state of a 2d-electron gas by the polarization of an adjacent ferroelectric gate (I Stolitchnov). Latest advancements in ALD processing for high-K thin films in dynamic RAM were reported by S Ramanathan. The advancement of piezoelectric PZT thin film MEMS devices was well documented by outstanding talks on their developments in industry (M Klee, F Tyholdt), new possibilities in GHz filters (T Matshushima), advancements in sol-gel processing (B Tuttle, H Suzuki), and low temperature integration approaches by UV light curing (S Trolier-McKinstry). Recent advances in incipient ferroelectric thin films and nano composites for tunable capacitors in microwave applications were present by A Vorobiev and T Yamada. Integrated electro-optics is another field to be conquered by thin film structures. The impressive progress made in this field was highlighted by P Günter. Many contributions were devoted to processing techniques, showing the increasing importance of CVD techniques to deposit for instance perovskite thin films (G Malandrino). Nevertheless, stunning results were obtained by a sophisticated MBE tool allowing for precise compositional control of individual oxide monolayers and thus enabling High-Tc supraconductivity in individual monolayers to be addressed (I Bosovic). Oxides do not only gleam with giant dielectric properties, giant electronic conduction (superconductivity), there is also a giant electro-caloric effect, as explained by Z Kutnjak. The symposium could take advantage of the EU projects NUOTO and CAMELIA that organized a joint session on giant K dielectrics to present their project results to the scientific and industrial community. The symposium organizers Paul Muralt, EPFL, Lausanne, Switzerland Marija Kosec, Josef Stefan Institute, Ljubljana, Slovenia Vito Raineri, IMM-CNR, Catania, Italy Sebastiano Ravesi, STMicroelectronics, Catania, Italy Scientific Committee Robert Blinc (Josef Stefan Inst., Slovenia) Wolfgang Kleemann (Univ. Duisburg, Germany) Raffaella Lo Nigro (IMM-CNR, Italy) Ian M Reaney (Univ. Sheffield, Great Britain) T Metzger (EPCOS, Germany) Rainer Waser (TH Aachen, Germany)

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Producing CCD imaging sensor with flashed backside metal film

NASA Technical Reports Server (NTRS)

Janesick, James R. (Inventor)

1988-01-01

A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning. This metal film (flash gate), which improves and stabilizes the quantum efficiency of a CCD imaging sensor, will also improve the QE of any p-n junction photodetector.

CCD imaging sensor with flashed backside metal film

NASA Technical Reports Server (NTRS)

Janesick, James R. (Inventor)

1991-01-01

A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning. This metal film (flash gate), which improves and stabilizes the quantum efficiency of a CCD imaging sensor, will also improve the QE of any p-n junction photodetector.

KEY COMPARISON: CCQM-K32 key comparison and P84 pilot study: Amount of silicon oxide as a thickness of SiO2 on Si

NASA Astrophysics Data System (ADS)

Seah, M. P.

2008-01-01

CCQM-K32 and P84 were conducted following the pilot study P-38 to demonstrate and document the capability of interested National Metrology Institutes to measure the amount of silicon oxide on silicon wafers expressed as a thickness of SiO2 for nominal thicknesses in the range 1.5 nm to 8 nm. 'Amount of substance' may be expressed in many ways and here the measurand is the thickness of the silicon oxide layer on each of a total of 9 samples of nominal thicknesses in the range 1.5 to 8 nm on (100) and (111) Si substrates, expressed as the thickness of SiO2. This report presents the results from K32 and P84. It includes the data received for the measured values and their associated uncertainties, at 95% confidence, for the 9 samples prior to the deadline for receipt of data. The materials are grown by thermal oxidation in very clean furnaces designed for high quality gate oxides on Si wafers in European and US facilities at the same time as those for the pilot study, P-38. Separate samples were provided to each institute in special containers limiting the carbonaceous contamination to below about 0.3 nm. The 9 samples included 5 samples of ultra-thin SiO2 on (100) orientated wafers of Si and 4 samples of ultra-thin SiO2 on (111) orientated wafers of Si. The measurements from the 11 participating laboratories were conducted using ellipsometry, neutron reflectivity (NR), x-ray photoelectron spectroscopy (XPS) or x-ray reflectivity measurements (XRR), guided by the protocol developed in the pilot study P-38 and reproduced in the Appendix. The measurements are given in tables 2 and 3. A very small correction is then made for the different samples that each laboratory received as in table 4. Where appropriate, method offset values deduced from the pilot study P-38 are given in table 5 leading to comparative data in tables 6 and 7. Values for the key comparison reference values (KCRVs) and their associated uncertainties are made from the weighted means and the expanded weighted standard deviations of the means from table 6. This is provided in table 8. Graphical plots of equivalence from tables 6 and 8 are provided in figure 1 and equivalence statements are presented in Annex A. Additional XPS and XRR data from NMIJ for K32 were withdrawn from the KCRV evaluation and are given in Annex B. Main text. To reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/. The final report has been peer-reviewed and approved for publication by the CCQM, according to the provisions of the CIPM Mutual Recognition Arrangement (MRA).

Fabrication and stability investigation of ultra-thin transparent and flexible Cu-Ag-Au tri-layer film on PET

NASA Astrophysics Data System (ADS)

Prakasarao, Ch Surya; D'souza, Slavia Deeksha; Hazarika, Pratim; Karthiselva N., S.; Ramesh Babu, R.; Kovendhan, M.; Kumar, R. Arockia; Joseph, D. Paul

2018-04-01

The need for transparent conducting electrodes with high transmittance, low sheet resistance and flexibility to replace Indium Tin Oxide is ever growing. We have deposited and studied the performance of ultra-thin Cu-Ag-Au tri-layer films over a flexible poly-ethylene terephthalate substrate. Scotch tape test showed good adhesion of the metallic film. Transmittance of the tri-layer was around 40 % in visible region. Optical profiler measurements were done to study the surface features. The XRD pattern revealed that film was amorphous. Sheet resistance measured by four probe technique was around 7.7 Ohm/Δ and was stable up to 423 K. The transport parameters by Hall effect showed high conductivity and carrier concentration with a mobility of 5.58 cm2/Vs. Tests performed in an indigenously designed bending unit indicated the films to be stable both mechanically and electrically even after 50,000 bending cycles.

Fabrication and Characterization of Fully Transparent ZnO Thin-Film Transistors and Self-Switching Nano-Diodes

NASA Astrophysics Data System (ADS)

Sun, Y.; Ashida, K.; Sasaki, S.; Koyama, M.; Maemoto, T.; Sasa, S.; Kasai, S.; Iñiguez-de-la-Torre, I.; González, T.

2015-10-01

Fully transparent zinc oxide (ZnO) based thin-film transistors (TFTs) and a new type of rectifiers calls self-switching nano-diodes (SSDs) were fabricated on glass substrates at room temperature by using low resistivity and transparent conducting Al- doped ZnO (AZO) thin-films. The deposition conditions of AZO thin-films were optimized with pulsed laser deposition (PLD). AZO thin-films on glass substrates were characterized and the transparency of 80% and resistivity with 1.6*10-3 Ωcm were obtained of 50 nm thickness. Transparent ZnO-TFTs were fabricated on glass substrates by using AZO thin-films as electrodes. A ZnO-TFT with 2 μm long gate device exhibits a transconductance of 400 μS/mm and an ON/OFF ratio of 2.8*107. Transparent ZnO-SSDs were also fabricated by using ZnO based materials and clear diode-like characteristics were observed.

Summary and Evaluation of NRC-Sponsored Stellite 6 Aging and Friction Tests

DOE Office of Scientific and Technical Information (OSTI.GOV)

J. C. Watkins; K. G. DeWall; D. Bramwell

1999-04-01

This report describes four sets of tests sponsored by the U.S. Nuclear Regulatory Commission and conducted by the Idaho National Engineering and Environmental Laboratory. The tests support research addressing the need to provide assurance that motor-operated valves are able to perform their intended safety function, usually to open or close against specified (design basis) flow and pressure loads. One of the parameters that affects a gate valve's operability is the friction between the disc seats and the valve body seats. In most gate valves, these surfaces are hardfaced with Stellite 6, a cobalt-based alloy. The tests described in this reportmore » investigate the changes that occur in the friction as the Stellite 6 surfaces develop an oxide film as they age. Stellite 6 specimens were aged in a corrosion autoclave, the oxide films were examined and characterized, and the specimens were subjected to friction testing in a friction autoclave. A very thin oxide film formed after only a fe w days of natural aging. Even a very thin oxide film caused an increase in friction. The surface structure of the oxide film was dominated by a hard crystalline structure, such that the friction response was analogous to rubbing two pieces of sandpaper together. In the limited data provided by naturally aged specimens (78 days maximum exposure, very thin oxide films), the friction increased with greater aging time, approaching an as-yet-undetermined plateau. Although the thickness of the oxide film increased with greater aging time, the mechanical properties of the oxide film (larger granules with greater aging time) appeared to play a greater role in the friction response. Friction testing of specimens subjected to simulated in-service testing strokes at intervals during the aging process showed only a slight decrease in friction, compared to other specimens. Results from specimens subjected to accelerated aging were inconclusive, because of differences in the structure and comp osition of the oxide films, compared to naturally aged specimens. For the naturally aged specimens, the highest friction occurred on the first stroke. The first stroke smeared the oxide film and dislodged some of the granules, so that subsequent strokes saw lower friction values and less variation in the friction. This result underscores the importance of planning in-plant tests so that data are collected from the first stroke following a period of inactivity.« less

Low-cost label-free electrical detection of artificial DNA nanostructures using solution-processed oxide thin-film transistors.

PubMed

Kim, Si Joon; Jung, Joohye; Lee, Keun Woo; Yoon, Doo Hyun; Jung, Tae Soo; Dugasani, Sreekantha Reddy; Park, Sung Ha; Kim, Hyun Jae

2013-11-13

A high-sensitivity, label-free method for detecting deoxyribonucleic acid (DNA) using solution-processed oxide thin-film transistors (TFTs) was developed. Double-crossover (DX) DNA nanostructures with different concentrations of divalent Cu ion (Cu(2+)) were immobilized on an In-Ga-Zn-O (IGZO) back-channel surface, which changed the electrical performance of the IGZO TFTs. The detection mechanism of the IGZO TFT-based DNA biosensor is attributed to electron trapping and electrostatic interactions caused by negatively charged phosphate groups on the DNA backbone. Furthermore, Cu(2+) in DX DNA nanostructures generates a current path when a gate bias is applied. The direct effect on the electrical response implies that solution-processed IGZO TFTs could be used to realize low-cost and high-sensitivity DNA biosensors.

Using KrF ELA to Improve Gate-Stacked LaAlO₃/ZrO₂ Indium Gallium Zinc Oxide Thin-Film Transistors with Novel Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition Technique.

PubMed

Wu, Chien-Hung; Chang, Kow-Ming; Chen, Yi-Ming; Huang, Bo-Wen; Zhang, Yu-Xin; Wang, Shui-Jinn

2018-03-01

Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique and KrF excimer laser annealing (ELA) were employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO-TFTs). Device with a 150 mJ/cm2 laser annealing densities demonstrated excellent electrical characteristics with improved on/off current ratio of 4.7×107, high channel mobility of 10 cm2/V-s, and low subthreshold swing of 0.15 V/dec. The improvements are attributed to the adjustment of oxygen vacancies in the IGZO channel to an appropriate range of around 28.3% and the reduction of traps at the high-k/IGZO interface.

The Electrochemical Behavior of Mo-Ta Alloy in Phosphoric Acid Solution for TFT-LCD Application.

PubMed

Lee, Sang-Hyuk; Kim, Byoung O; Seo, Jong Hyun

2015-10-01

Molybdenum-tantalum alloy thin film is a suitable material for the higher corrosion resistance and low resistivity for gate and data metal lines. In this study, Mo-Ta alloy thin films were prepared by using a DC magnetron co-sputtering system on a glass substrate. An abrupt increase in the etching rates of low Mo-Ta alloys was observed. From the observed impedance analysis, the defect densities in the MoTa oxide films increased from 5.4 x 10(21) (cm(-3)) to 8.02 x 10(21) (cm(-3)) up to the 6 at% of tantalum level; and above the 6 at% of tantalum level, the defect densities decreased. This electrochemical behavior is explained by the mechanical instability of the MoTa oxide film.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Advanced germanium layer transfer for ultra thin body on insulator structure

NASA Astrophysics Data System (ADS)

Maeda, Tatsuro; Chang, Wen-Hsin; Irisawa, Toshifumi; Ishii, Hiroyuki; Hattori, Hiroyuki; Poborchii, Vladimir; Kurashima, Yuuichi; Takagi, Hideki; Uchida, Noriyuki

2016-12-01

We present the HEtero-Layer Lift-Off (HELLO) technique to obtain ultra thin body (UTB) Ge on insulator (GeOI) substrates. The transferred ultra thin Ge layers are characterized by the Raman spectroscopy measurements down to the thickness of ˜1 nm, observing a strong Raman intensity enhancement for high quality GeOI structure in ultra thin regime due to quantum size effect. This advanced Ge layer transfer technique enabled us to demonstrate UTB-GeOI nMOSFETs with the body thickness of only 4 nm.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Ultra wide band 3-D cross section (RCS) holography

NASA Astrophysics Data System (ADS)

Collins, H. D.; Hall, T. E.

1992-07-01

Ultra wide band impulse holography is an exciting new concept for predictive radar cross section (RCS) evaluation employing near-field measurements. Reconstruction of the near-field hologram data maps the target's scattering areas, and uniquely identifies the 'hot spot' locations on the target. In addition, the target and calibration sphere's plane wave angular spectrums are computed (via digital algorithm) and used to generate the target's far-field RCS values in three dimensions for each frequency component in the impulse. Thin and thick targets are defined in terms of their near-field amplitude variations in range. Range gating and computer holographic techniques are applied to correct these variations. Preliminary experimental results on various targets verify the concept of RCS holography. The unique 3-D presentation (i.e., typically containing 524,288 RCS values for a 1024 (times) 512 sampled aperture for every frequency component) illustrates the efficacy of target recognition in terms of its far-field plane wave angular spectrum image. RCS images can then be viewed at different angles for target recognition, etc.

Magnetism and electronic structure at the interface of a metal CaRuO3 and Mott insulator CaMnO3.

NASA Astrophysics Data System (ADS)

Boris, Alexander; Freeland, John; Kavich, Jerald; Lee, Ho Nyung; Yordanov, Petar; Khaliullin, Giniyat; Keimer, Bernhard; Chakhalian, Jak

2007-03-01

Recent advances in fabrication of ultra-thin complex oxide heterostructures have opened new opportunities to investigate possible novel quantum states at the correlated interfaces. With this aim we fabricated ultra-thin superlattices of CaMnO3(CMO)/CaRuO3(CRO) with the thickness of CRO layers from 1 to 12 unit cells by laser MBE. Electronic properties of CRO/CMO were investigated by soft x-ray spectroscopies at the L-edges of Mn and Ru. SQUID and optical reflectivity revealed a ferromagnetic thickness-independent transition at Tc 100K and CRO thickness-dependent negative magnetoresistance. This behavior is in marked contrast to the individual layers. At the interface we found a clear sign of net magnetic moment on Mn, which saturates only at magnetic field of 5T. Unlike CMO, similar measurements at the Ru L3-edge showed no detectable magnetism in the field up to 5T. Comparison with Ru references confirmed Ru(IV) oxidation state. These findings are in the sharp contrast with previously suggested models involving Ru(IV-V) valency exchange and thus reveal intricate nature of the interface between a metal and Mott insulator.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

NASA Astrophysics Data System (ADS)

Ye, Fan; Xiaorong, Luo; Kun, Zhou; Yuanhang, Fan; Yongheng, Jiang; Qi, Wang; Pei, Wang; Yinchun, Luo; Bo, Zhang

2014-03-01

A low specific on-resistance (Ron,sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron,sp. Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron,sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron,sp by 80% at the same BV.

Ionic liquid gating on atomic layer deposition passivated GaN: Ultra-high electron density induced high drain current and low contact resistance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Hong; Du, Yuchen; Ye, Peide D., E-mail: yep@purdue.edu

2016-05-16

Herein, we report on achieving ultra-high electron density (exceeding 10{sup 14 }cm{sup −2}) in a GaN bulk material device by ionic liquid gating, through the application of atomic layer deposition (ALD) of Al{sub 2}O{sub 3} to passivate the GaN surface. Output characteristics demonstrate a maximum drain current of 1.47 A/mm, the highest reported among all bulk GaN field-effect transistors, with an on/off ratio of 10{sup 5} at room temperature. An ultra-high electron density exceeding 10{sup 14 }cm{sup −2} accumulated at the surface is confirmed via Hall-effect measurement and transfer length measurement. In addition to the ultra-high electron density, we also observe a reductionmore » of the contact resistance due to the narrowing of the Schottky barrier width on the contacts. Taking advantage of the ALD surface passivation and ionic liquid gating technique, this work provides a route to study the field-effect and carrier transport properties of conventional semiconductors in unprecedented ultra-high charge density regions.« less

Effects of substrate heating and post-deposition annealing on characteristics of thin MOCVD HfO2 films

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Ramesh, Sivaramakrishnan; Dutta, Shibesh; Virajit Garbhapu, Venkata

2018-02-01

It is well known that Hf-based dielectrics have replaced the traditional SiO2 and SiON as gate dielectric materials for conventional CMOS devices. By using thicker high-k materials such as HfO2 rather than ultra-thin SiO2, we can bring down leakage current densities in MOS devices to acceptable levels. HfO2 is also one of the potential candidates as a blocking dielectric for Flash memory applications for the same reason. In this study, effects of substrate heating and oxygen flow rate while depositing HfO2 thin films using CVD and effects of post deposition annealing on the physical and electrical characteristics of HfO2 thin films are presented. It was observed that substrate heating during deposition helps improve the density and electrical characteristics of the films. At higher substrate temperature, Vfb moved closer to zero and also resulted in significant reduction in hysteresis. Higher O2 flow rates may improve capacitance, but also results in slightly higher leakage. The effect of PDA depended on film thickness and O2 PDA improved characteristics only for thick films. For thinner films forming gas anneal resulted in better electrical characteristics.

Comparison of the agglomeration behavior of thin metallic films on SiO2

NASA Astrophysics Data System (ADS)

Gadkari, P. R.; Warren, A. P.; Todi, R. M.; Petrova, R. V.; Coffey, K. R.

2005-07-01

The stability of continuous metallic thin films on insulating oxide surfaces is of interest to applications such as semiconductor interconnections and gate engineering. In this work, we report the study of the formation of voids and agglomeration of initially continuous Cu, Au, Ru and Pt thin films deposited on amorphous thermally grown SiO2 surfaces. Polycrystalline thin films having thicknesses in the range of 10-100 nm were ultrahigh vacuum sputter deposited on thermally grown SiO2 surfaces. The films were annealed at temperatures in the range of 150-800 °C in argon and argon+3% hydrogen gases. Scanning electron microscopy was used to investigate the agglomeration behavior, and transmission electron microscopy was used to characterize the microstructure of the as-deposited and annealed films. The agglomeration sequence in all of the films is found to follow a two step process of void nucleation and void growth. However, void growth in Au and Pt thin films is different from Cu and Ru thin films. Residual stress and adhesion were observed to play an important part in deciding the mode of void growth in Au and Pt thin films. Last, it is also observed that the tendency for agglomeration can be reduced by encapsulating the metal film with an oxide overlayer.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Designable ultra-smooth ultra-thin solid-electrolyte interphases of three alkali metal anodes.

PubMed

Gu, Yu; Wang, Wei-Wei; Li, Yi-Juan; Wu, Qi-Hui; Tang, Shuai; Yan, Jia-Wei; Zheng, Ming-Sen; Wu, De-Yin; Fan, Chun-Hai; Hu, Wei-Qiang; Chen, Zhao-Bin; Fang, Yuan; Zhang, Qing-Hong; Dong, Quan-Feng; Mao, Bing-Wei

2018-04-09

Dendrite growth of alkali metal anodes limited their lifetime for charge/discharge cycling. Here, we report near-perfect anodes of lithium, sodium, and potassium metals achieved by electrochemical polishing, which removes microscopic defects and creates ultra-smooth ultra-thin solid-electrolyte interphase layers at metal surfaces for providing a homogeneous environment. Precise characterizations by AFM force probing with corroborative in-depth XPS profile analysis reveal that the ultra-smooth ultra-thin solid-electrolyte interphase can be designed to have alternating inorganic-rich and organic-rich/mixed multi-layered structure, which offers mechanical property of coupled rigidity and elasticity. The polished metal anodes exhibit significantly enhanced cycling stability, specifically the lithium anodes can cycle for over 200 times at a real current density of 2 mA cm -2 with 100% depth of discharge. Our work illustrates that an ultra-smooth ultra-thin solid-electrolyte interphase may be robust enough to suppress dendrite growth and thus serve as an initial layer for further improved protection of alkali metal anodes.

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

PubMed Central

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-01-01

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials. PMID:28772579

Characterisation of Nd2O3 thick gate dielectric for silicon

NASA Astrophysics Data System (ADS)

Dakhel, A. A.

2004-03-01

Thin neodymium films were prepared by the reactive synthesis method on Si (P) substrates to form MOS devices. The oxide films were characterised by UV absorption spectroscopy, X-ray fluorescence (EDXRF) and X-ray diffraction (XRD). The ac conductance and capacitance of the devices were studied as a function of frequency in the range 100 Hz-100 kHz, of temperature in the range 293-473 K and of gate voltage. It was proved that a suitable formalism to explain the frequency dependence of the ac conductivity and capacitance of the insulator is controlled by a universal power law based on the relaxation processes of the hopping or tunnelling of the current carriers between equilibrium sites. The temperature dependence of the ac conductance at the accumulation state shows a small activation energy of about 0.07 eV for a MOS device with amorphous neodymium oxide. The temperature dependence of the accumulation capacitance for a MOS structure with crystalline neodymium oxide shows a maximum at about 390 K; such a maximum was not observed for the structure with amorphous neodymium oxide. The method of capacitance-gate voltage (C-Vg) measurements was used to investigate the effect of annealing in air and in vacuum on the surface density of states (Nss) at the insulator/semiconductor (I/S) interface. It was concluded that the density of surface states in the mid-gap increases by about five times while the density of the trapped charges in the oxide layer decreases by about eight times when the oxide crystallises into a polycrystalline structure.

Analysis of indium zinc oxide thin films by laser-induced breakdown spectroscopy

NASA Astrophysics Data System (ADS)

Popescu, A. C.; Beldjilali, S.; Socol, G.; Craciun, V.; Mihailescu, I. N.; Hermann, J.

2011-10-01

We have performed spectroscopic analysis of the plasma generated by Nd:YAG (λ = 266 nm) laser irradiation of thin indium zinc oxide films with variable In content deposited by combinatorial pulsed laser deposition on glass substrates. The samples were irradiated in 5 × 104 Pa argon using laser pulses of 5 ns duration and 10 mJ energy. The plasma emission spectra were recorded with an Echelle spectrometer coupled to a gated detector with different delays with respect to the laser pulse. The relative concentrations of indium and zinc were evaluated by comparing the measured spectra to the spectral radiance computed for a plasma in local thermal equilibrium. Plasma temperature and electron density were deduced from the relative intensities and Stark broadening of spectral lines of atomic zinc. Analyses at different locations on the deposited thin films revealed that the In/(In + Zn) concentration ratio significantly varies over the sample surface, from 0.4 at the borders to about 0.5 in the center of the film. The results demonstrate that laser-induced breakdown spectroscopy allows for precise and fast characterization of thin films with variable composition.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

NASA Astrophysics Data System (ADS)

Carl, D. A.; Hess, D. W.; Lieberman, M. A.; Nguyen, T. D.; Gronsky, R.

1991-09-01

Thin (3-300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O-, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5-60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K. High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4-30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm-2) and interface traps (≳1012 cm-2 eV-1). The fixed charge level could be reduced to ≊4×1010 cm-2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1-2)×1011 cm-2 eV-1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm-1. Electrical properties of the 5.4-8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.

Hafnium oxide films for application as gate dielectrics

NASA Astrophysics Data System (ADS)

Hsu, Shuo-Lin

The deposition and characterization of HfO2 films for potential application as a high-kappa gate dielectric in MOS devices has been investigated. DC magnetron reactive sputtering was utilized to prepare the HfO2 films. Structural, chemical, and electrical analyses were performed to characterize the various physical, chemical and electrical properties of the sputtered HfO2 films. The sputtered HfO2 films were annealed to simulate the dopant activation process used in semiconductor processing, and to study the thermal stability of the high-kappa, films. The changes in the film properties due to the annealing are also discussed in this work. Glancing angle XRD was used to analyse the atomic scale structure of the films. The as deposited films exhibit an amorphous, regardless of the film thickness. During post-deposition annealing, the thicker films crystallized at lower temperature (< 600°C), and ultra-thin (5.8 nm) film crystallized at higher temperature (600--720°C). The crystalline phase which formed depended on the thickness of the films. The low temperature phase (monoclinic) formed in the 10--20 nm annealed films, and high temperature phase (tetragonal) formed in the ultra-thin annealed HfO2 film. TEM cross-section studies of as deposited samples show that an interfacial layer (< 1nm) exists between HfO2/Si for all film thicknesses. The interfacial layer grows thicker during heat treatment, and grows more rapidly when grain boundaries are present. XPS surface analysis shows the as deposited films are fully oxidized with an excess of oxygen. Interfacial chemistry analysis indicated that the interfacial layer is a silicon-rich silicate layer, which tends to transform to silica-like layer during heat treatment. I-V measurements show the leakage current density of the Al/as deposited-HfO 2/Si MOS diode is of the order of 10-3 A/cm 2, two orders of magnitude lower than that of a ZrO2 film with similar physical thickness. Carrier transport is dominated by Schottky emission at lower electric fields, and by Frenkel-Poole emission in the higher electric field region. After annealing, the leakage current density decreases significantly as the structure remains amorphous structure. It is suggested that this decrease is assorted with the densification and defect healing which accures when the porous as-deposited amorphous structure is annealed. The leakage current density increases of the HfO2 layer crystallizes on annealing, which is attributed to the presence of grain boundaries. C-V measurements of the as deposited film shows typical C-V characteristics, with negligible hystersis, a small flat band voltage shift, but great frequency dispersion. The relative permittivity of HfO2/interfacial layer stack obtained from the capacitance at accumulation is 15, which corresponds to an EOT (equivalent oxide thickness) = 1.66 nm. After annealing, the frequency dispersion is greatly enhanced, and the C-V curve is shifted toward the negative voltage. Reliability tests show that the HfO2 films which remain amorphous after annealing possess superior resistance to constant voltage stress and ambient aging. This study concluded that the sputtered HfO 2 films exhibit an amorphous as deposited. Postdeposition annealing alters the crystallinity, interfacial properties, and electrical characteristics. The HfO2 films which remain amorphous structure after annealing possess the best electrical properties.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Li-Chih; Chen, Jen-Sue, E-mail: jenschen@mail.ncku.edu.tw, E-mail: jsjeng@mail.nutn.edu.tw; Jeng, Jiann-Shing, E-mail: jenschen@mail.ncku.edu.tw, E-mail: jsjeng@mail.nutn.edu.tw

Solution-processed ultra-thin (∼3 nm) zinc tin oxide (ZTO) thin film transistors (TFTs) with a mobility of 8 cm{sup 2}/Vs are obtained with post spin-coating annealing at only 350 °C. The effect of light illumination (at wavelengths of 405 nm or 532 nm) on the stability of TFT transfer characteristics under various gate bias stress conditions (zero, positive, and negative) is investigated. It is found that the ΔV{sub th} (V{sub th}{sup stress} {sup 3400} {sup s − stress} {sup 0} {sup s}) window is significantly positive when ZTO TFTs are under positive bias stress (PBS, ΔV{sub th} = 9.98 V) and positive bias illumination stress (λ = 405 nm and ΔV{sub th} = 6.96 V), butmore » ΔV{sub th} is slightly negative under only light illumination stress (λ = 405 nm and ΔV{sub th} = −2.02 V) or negative bias stress (ΔV{sub th} = −2.27 V). However, the ΔV{sub th} of ZTO TFT under negative bias illumination stress is substantial, and it will efficiently recover the ΔV{sub th} caused by PBS. The result is attributed to the photo-ionization and subsequent transition of electronic states of oxygen vacancies (i.e., V{sub o}, V{sub o}{sup +}, and V{sub o}{sup ++}) in ZTO. A detailed mechanism is discussed to better understand the bias stress stability of solution processed ZTO TFTs.« less

STIR: Novel Electronic States by Gating Strongly Correlated Materials

DTIC Science & Technology

2016-03-01

plan built on my group’s recent demonstration of electrolyte gating in Strontium Titanate, using an atomically thin hexagonal Boron Nitride barrier to...demonstration of electrolyte gating in Strontium Titanate, using an atomically thin hexagonal Boron Nitride barrier to prevent disorder and chemical...techniques and learned to apply thin hexagonal Boron Nitride to single crystals of materials expected to show some of the most exciting correlated

Oxidation preventative capping layer for deep-ultra-violet and soft x-ray multilayers

DOEpatents

Prisbrey, Shon T.

2004-07-06

The invention uses iridium and iridium compounds as a protective capping layer on multilayers having reflectivity in the deep ultra-violet to soft x-ray regime. The iridium compounds can be formed in one of two ways: by direct deposition of the iridium compound from a prepared target or by depositing a thin layer (e.g., 5-50 angstroms) of iridium directly onto an element. The deposition energy of the incoming iridium is sufficient to activate the formation of the desired iridium compound. The compounds of most interest are iridium silicide (IrSi.sub.x) and iridium molybdenide (IrMo.sub.x).

Production of pulsed ultra slow muons and first /μSR experiments on thin metallic and magnetic films

NASA Astrophysics Data System (ADS)

Träger, K.; Breitrück, A.; Trigo, M. Diaz; Grossmann, A.; Jungmann, K.; Merkel, J.; Meyer, V.; Neumayer, P.; Pachl, B.; zu Putlitz, G.; Santra, R.; William, L.; Allodi, G.; Bucci, C.; Renzi, R. De; Galli, F.; Guidi, G.; Shiroka, T.; Eaton, G. H.; King, P. J. C.; Scott, C. A.; Williams, G. W.; Roduner, E.; Scheuermann, R.; Charlton, M. C.; Donnelly, P.; Pareti, L.; Turilli, G.

2000-08-01

At ISIS, RAL (UK) we have produced a pulsed ultra-slow muon beam (E≲20 eV) and performed the first μSR experiments. Thanks to the pulsed feature, the implantation time is automatically determined and, by adjusting the final muon energy between ∼8 keV and 20 eV, depth slicing experiments are possible down to monolayers distances. We report slicing experiments across a 20 nm copper film on quartz substrate with evidence for a 2 nm copper oxide surface layer. A preliminary experiment on a hexagonal cobalt film suggests the existence of muon precession in the local magnetic field.

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo

2016-03-01

In order to improve the reliability of TFT, an Al2O3 insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al2O3 layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V o2+ toward the interface between the gate insulator and the semiconductor. The inserted Al2O3 triple layer exhibits a noticeably low turn on voltage shift of -0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm2/V ṡ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Scanning probes for lithography: Manipulation and devices

NASA Astrophysics Data System (ADS)

Rolandi, Marco

2005-11-01

Scanning probes are relatively low cost equipment that can push the limit of lithography in the nanometer range, with the advantages of high resolution, accuracy in the positioning of the overlayers and no proximity aberrations. We have developed three novel scanning probe lithography (SPL) resists based on thin films of Titanium, Molybdenum and Tungsten and we have manipulated single walled carbon nanotubes using the sharp tip of an atomic force microscope (AFM) for the fabrication of nanostructures. A dendrimer-passivated Ti film was imaged in the positive and the negative tone using SPL. This is the first example of SPL imaging in both tones using a unique resist. Positive tone patterning was obtained by locally scribing the dendrimer molecules and subsequent acid etch of the deprotected Ti film. Local anodic oxidation transforms Ti into TiO2 and deposits a thin layer of amorphous carbon on the patterned areas. This is very resistive to base etch and affords negative tone imaging of the Ti surface. Molybdenum and Tungsten were patterned using local anodic oxidation. This scheme is particularly flexible thanks to the solubility in water of the fully oxidized states of the two metals. We will present the facile fabrication of several nanostructures such as of trenches, dots wires and nanoelectrodes and show the potential of this scheme for competing with conventional lithographic techniques based on radiation. Quasi one dimensional electrodes for molecular electronics applications were also fabricated by creating nanogaps in single walled carbon nanotubes. The tubes, connected to microscopic contacts, were controllably cut via local anodic oxidation using the tip of the AFM. This technique leads to nanoscopic carboxyl terminated wires to which organic molecules can be linked using covalent chemistry. This geometry is particularly useful for the high gate efficiency without the need of a thin gate dielectric and the stability of the junction. Room temperature and low temperature measurements were performed and show single electron transistor behavior for the molecular junction.

Characterization of ultrathin insulators in CMOS technology: Wearout and failure mechanisms due to processing and operation

NASA Astrophysics Data System (ADS)

Okandan, Murat

In the CMOS technology the gate dielectric is the most critical layer, as its condition directly dictates the ultimate performance of the devices. In this thesis, the wear-out and failure mechanisms in ultra-thin (around 50A and lower) oxides are investigated. A new degradation phenomenon, quasi-breakdown (or soft-breakdown), and the annealing and stressing behavior of devices after quasi-breakdown are considered in detail. Devices that are in quasi-breakdown continue to operate as switches, but the gate leakage current is two orders of magnitude higher than the leakage in healthy devices and the stressing/annealing behavior of the devices are completely altered. This phenomenon is of utmost interest, since the reduction in SiO2 dielectric thickness has reached its physical limits, and the quasi-breakdown behavior is seen to dominate as a failure mode in this regime. The quasi-breakdown condition can be brought on by stresses during operation or processing. To further study this evolution through stresses and anneals, cyclic current-voltage (I-V) measurement has been further developed and utilized in this thesis. Cyclic IV is a simple and fast, two terminal measurement technique that looks at the transient current flowing in an MOS system during voltage sweeps from accumulation to inversion and back. During these sweeps, carrier trapping/detrapping, generation and recombination are observed. An experimental setup using a fast electrometer and analog to digital conversion (A/D) card and the software for control of the setup and data analysis were also developed to gain further insight into the detailed physics involved. Overall, the crucial aspects of wear-out and quasi-breakdown of ultrathin dielectrics, along with the methods for analyzing this evolution are presented in this thesis.

Strain-induced phase variation and dielectric constant enhancement of epitaxial Gd{sub 2}O{sub 3}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shekhter, P., E-mail: Pini@tx.technion.ac.il; Amouyal, Y.; Eizenberg, M.

2016-07-07

One of the approaches for realizing advanced high k insulators for metal oxide semiconductor field effect transistors based devices is the use of rare earth oxides. When these oxides are deposited as epitaxial thin films, they demonstrate dielectric properties that differ greatly from those that are known for bulk oxides. Using structural and spectroscopic techniques, as well as first-principles calculations, Gd{sub 2}O{sub 3} films deposited on Si (111) and Ge (111) were characterized. It was seen that the same 4 nm thick film, grown simultaneously on Ge and Si, presents an unstrained lattice on Ge while showing a metastable phase onmore » Si. This change from the cubic lattice to the distorted metastable phase is characterized by an increase in the dielectric constant of more than 30% and a change in band gap. The case in study shows that extreme structural changes can occur in ultra-thin epitaxial rare earth oxide films and modify their dielectric properties when the underlying substrate is altered.« less

Exploring synchrotron radiation capabilities: The ALS-Intel CRADA

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gozzo, F.; Cossy-Favre, A; Trippleet, B.

1997-04-01

Synchrotron radiation spectroscopy and spectromicroscopy were applied, at the Advanced Light Source, to the analysis of materials and problems of interest to the commercial semiconductor industry. The authors discuss some of the results obtained at the ALS using existing capabilities, in particular the small spot ultra-ESCA instrument on beamline 7.0 and the AMS (Applied Material Science) endstation on beamline 9.3.2. The continuing trend towards smaller feature size and increased performance for semiconductor components has driven the semiconductor industry to invest in the development of sophisticated and complex instrumentation for the characterization of microstructures. Among the crucial milestones established by themore » Semiconductor Industry Association are the needs for high quality, defect free and extremely clean silicon wafers, very thin gate oxides, lithographies near 0.1 micron and advanced material interconnect structures. The requirements of future generations cannot be met with current industrial technologies. The purpose of the ALS-Intel CRADA (Cooperative Research And Development Agreement) is to explore, compare and improve the utility of synchrotron-based techniques for practical analysis of substrates of interest to semiconductor chip manufacturing. The first phase of the CRADA project consisted in exploring existing ALS capabilities and techniques on some problems of interest. Some of the preliminary results obtained on Intel samples are discussed here.« less

Excitation of epsilon-near-zero resonance in ultra-thin indium tin oxide shell embedded nanostructured optical fiber.

PubMed

Minn, Khant; Anopchenko, Aleksei; Yang, Jingyi; Lee, Ho Wai Howard

2018-02-05

We report a novel optical waveguide design of a hollow step index fiber modified with a thin layer of indium tin oxide (ITO). We show an excitation of highly confined waveguide mode in the proposed fiber near the wavelength where permittivity of ITO approaches zero. Due to the high field confinement within thin ITO shell inside the fiber, the epsilon-near-zero (ENZ) mode can be characterized by a peak in modal loss of the hybrid waveguide. Our results show that such in-fiber excitation of ENZ mode is due to the coupling of the guided core mode to the thin-film ENZ mode. We also show that the phase matching wavelength, where the coupling takes place, varies depending on the refractive index of the constituents inside the central bore of the fiber. These ENZ nanostructured optical fibers have many potential applications, for example, in ENZ nonlinear and magneto-optics, as in-fiber wavelength-dependent filters, and as subwavelength fluid channel for optical and bio-photonic sensing.

Extended-gate-type IGZO electric-double-layer TFT immunosensor with high sensitivity and low operation voltage

NASA Astrophysics Data System (ADS)

Liang, Lingyan; Zhang, Shengnan; Wu, Weihua; Zhu, Liqiang; Xiao, Hui; Liu, Yanghui; Zhang, Hongliang; Javaid, Kashif; Cao, Hongtao

2016-10-01

An immunosensor is proposed based on the indium-gallium-zinc-oxide (IGZO) electric-double-layer thin-film transistor (EDL TFT) with a separating extended gate. The IGZO EDL TFT has a field-effect mobility of 24.5 cm2 V-1 s-1 and an operation voltage less than 1.5 V. The sensors exhibit the linear current response to label-free target immune molecule in the concentrations ranging from 1.6 to 368 × 10-15 g/ml with a detection limit of 1.6 × 10-15 g/ml (0.01 fM) under an ultralow operation voltage of 0.5 V. The IGZO TFT component demonstrates a consecutive assay stability and recyclability due to the unique structure with the separating extended gate. With the excellent electrical properties and the potential for plug-in-card-type multifunctional sensing, extended-gate-type IGZO EDL TFTs can be promising candidates for the development of a label-free biosensor for public health applications.

Experimental investigation on On-Off current ratio behavior near onset voltage for a pentacene based organic thin film transistor

NASA Astrophysics Data System (ADS)

Amrani, Aumeur El; Es-saghiri, Abdeljabbar; Boufounas, El-Mahjoub; Lucas, Bruno

2018-06-01

The performance of a pentacene based organic thin film transistor (OTFT) with polymethylmethacrylate as a dielectric insulator and indium tin oxide based electrical gate is investigated. On the one hand, we showed that the threshold voltage increases with gate voltage, and on the other hand that it decreases with drain voltage. Thus, we noticed that the onset voltage shifts toward positive voltage values with the drain voltage increase. In addition, threshold-onset differential voltage (TODV) is proposed as an original approach to estimate an averaged carrier density in pentacene. Indeed, a value of about 4.5 × 1016 cm-3 is reached at relatively high gate voltage of -50 V; this value is in good agreement with that reported in literature with other technique measurements. However, at a low applied gate voltage, the averaged pentacene carrier density remains two orders of magnitude lower; it is of about 2.8 × 1014 cm-3 and remains similar to that obtained from space charge limited current approach for low applied bias voltage of about 2.2 × 1014 cm-3. Furthermore, high IOn/IOff and IOn/IOnset current ratios of 5 × 106 and 7.5 × 107 are reported for lower drain voltage, respectively. The investigated OTFTs also showed good electrical performance including carrier mobility increasing with gate voltage; mobility values of 4.5 × 10-2 cm2 V-1 s-1 and of 4.25 × 10-2 cm2 V-1 s-1 are reached for linear and saturation regimes, respectively. These results remain enough interesting since current modulation ratio exceeds a value of 107 that is a quite important requirement than high mobility for some particular logic gate applications.

An ultra-lightweight design for imperceptible plastic electronics.

PubMed

Kaltenbrunner, Martin; Sekitani, Tsuyoshi; Reeder, Jonathan; Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Drack, Michael; Schwödiauer, Reinhard; Graz, Ingrid; Bauer-Gogonea, Simona; Bauer, Siegfried; Someya, Takao

2013-07-25

Electronic devices have advanced from their heavy, bulky origins to become smart, mobile appliances. Nevertheless, they remain rigid, which precludes their intimate integration into everyday life. Flexible, textile and stretchable electronics are emerging research areas and may yield mainstream technologies. Rollable and unbreakable backplanes with amorphous silicon field-effect transistors on steel substrates only 3 μm thick have been demonstrated. On polymer substrates, bending radii of 0.1 mm have been achieved in flexible electronic devices. Concurrently, the need for compliant electronics that can not only be flexed but also conform to three-dimensional shapes has emerged. Approaches include the transfer of ultrathin polyimide layers encapsulating silicon CMOS circuits onto pre-stretched elastomers, the use of conductive elastomers integrated with organic field-effect transistors (OFETs) on polyimide islands, and fabrication of OFETs and gold interconnects on elastic substrates to realize pressure, temperature and optical sensors. Here we present a platform that makes electronics both virtually unbreakable and imperceptible. Fabricated directly on ultrathin (1 μm) polymer foils, our electronic circuits are light (3 g m(-2)) and ultraflexible and conform to their ambient, dynamic environment. Organic transistors with an ultra-dense oxide gate dielectric a few nanometres thick formed at room temperature enable sophisticated large-area electronic foils with unprecedented mechanical and environmental stability: they withstand repeated bending to radii of 5 μm and less, can be crumpled like paper, accommodate stretching up to 230% on prestrained elastomers, and can be operated at high temperatures and in aqueous environments. Because manufacturing costs of organic electronics are potentially low, imperceptible electronic foils may be as common in the future as plastic wrap is today. Applications include matrix-addressed tactile sensor foils for health care and monitoring, thin-film heaters, temperature and infrared sensors, displays, and organic solar cells.

Effect of organic buffer layer in the electrical properties of amorphous-indium gallium zinc oxide thin film transistor.

PubMed

Wang, Jian-Xun; Hyung, Gun Woo; Li, Zhao-Hui; Son, Sung-Yong; Kwon, Sang Jik; Kim, Young Kwan; Cho, Eou Sik

2012-07-01

In this research, we reported on the fabrication of top-contact amorphous-indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with an organic buffer layer between inorganic gate dielectric and active layer in order to improve the electrical properties of devices. By inserting an organic buffer layer, it was possible to make an affirmation of the improvements in the electrical characteristics of a-IGZO TFTs such as subthreshold slope (SS), on/off current ratio (I(ON/OFF)), off-state current, and saturation field-effect mobility (muFE). The a-IGZO TFTs with the cross-linked polyvinyl alcohol (c-PVA) buffer layer exhibited the pronounced improvements of the muFE (17.4 cm2/Vs), SS (0.9 V/decade), and I(ON/OFF) (8.9 x 10(6)).

Effects of structure and oxygen flow rate on the photo-response of amorphous IGZO-based photodetector devices

NASA Astrophysics Data System (ADS)

Jang, Jun Tae; Ko, Daehyun; Choi, Sungju; Kang, Hara; Kim, Jae-Young; Yu, Hye Ri; Ahn, Geumho; Jung, Haesun; Rhee, Jihyun; Lee, Heesung; Choi, Sung-Jin; Kim, Dong Myong; Kim, Dae Hwan

2018-02-01

In this study, we investigated how the structure and oxygen flow rate (OFR) during the sputter-deposition affects the photo-responses of amorphous indium-gallium-zinc-oxide (a-IGZO)-based photodetector devices. As the result of comparing three types of device structures with one another, which are a global Schottky diode, local Schottky diode, and thin-film transistor (TFT), the IGZO TFT with the gate pulse technique suppressing the persistent photoconductivity (PPC) is the most promising photodetector in terms of a high photo-sensitivity and uniform sensing characteristic. In order to analyze the IGZO TFT-based photodetectors more quantitatively, the time-evolution of sub-gap density-of-states (DOS) was directly observed under photo-illumination and consecutively during the PPC-compensating period with applying the gate pulse. It shows that the increased ionized oxygen vacancy (VO2+) defects under photo-illumination was fully recovered by the positive gate pulse and even overcompensated by additional electron trapping. Based on experimentally extracted sub-gap DOS, the origin on PPC was successfully decomposed into the hole trapping and the VO ionization. Although the VO ionization is enhanced in lower OFR (O-poor) device, the PPC becomes more severe in high OFR (O-rich) device because the hole trapping dominates the PPC in IGZO TFT under photo-illumination rather than the VO ionization and more abundant holes are trapped into gate insulator and/or interface in O-rich TFTs. Similarly, the electron trapping during the PPC-compensating period with applying the positive gate pulse becomes more prominent in O-rich TFTs. It is attributed to more hole/electron traps in the gate insulator and/or interface, which is associated with oxygen interstitials, or originates from the ion bombardment-related lower quality gate oxide in O-rich devices.

Self-aligned top-gate amorphous indium zinc oxide thin-film transistors exceeding low-temperature poly-Si transistor performance.

PubMed

Park, Jae Chul; Lee, Ho-Nyeon; Im, Seongil

2013-08-14

Thin-film transistor (TFT) is a key component of active-matrix flat-panel displays (AMFPDs). These days, the low-temperature poly silicon (LTPS) TFTs are to match with advanced AMFPDs such as the active matrix organic light-emitting diode (AMOLED) display, because of their high mobility for fast pixel switching. However, the manufacturing process of LTPS TFT is quite complicated, costly, and scale-limited. Amorphous oxide semiconductor (AOS) TFT technology is another candidate, which is as simple as that of conventioanl amorphous (a)-Si TFTs in fabrication but provides much superior device performances to those of a-Si TFTs. Hence, various AOSs have been compared with LTPS for active channel layer of the advanced TFTs, but have always been found to be relatively inferior to LTPS. In the present work, we clear the persistent inferiority, innovating the device performaces of a-IZO TFT by adopting a self-aligned coplanar top-gate structure and modifying the surface of a-IZO material. Herein, we demonstrate a high-performance simple-processed a-IZO TFT with mobility of ∼157 cm(2) V(-1) s(-1), SS of ∼190 mV dec(-1), and good bias/photostabilities, which overall surpass the performances of high-cost LTPS TFTs.

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

NASA Technical Reports Server (NTRS)

Toshishige, Yamada; Biegel, Bryan A. (Technical Monitor)

2002-01-01

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

PubMed Central

Oh, Young Jun; Noh, Hyeon-Kyun; Chang, Kee Joo

2015-01-01

Oxygen vacancies have been considered as the origin of threshold voltage instability under negative bias illumination stress in amorphous oxide thin film transistors. Here we report the results of first-principles molecular dynamics simulations for the drift motion of oxygen vacancies. We show that oxygen vacancies, which are initially ionized by trapping photoexcited hole carriers, can easily migrate under an external electric field. Thus, accumulated hole traps near the channel/dielectric interface cause negative shift of the threshold voltage, supporting the oxygen vacancy model. In addition, we find that ionized oxygen vacancies easily recover their neutral defect configurations by capturing electrons when the Fermi level increases. Our results are in good agreement with the experimental observation that applying a positive gate bias pulse of short duration eliminates hole traps and thus leads to the recovery of device stability from persistent photoconductivity. PMID:27877799

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Non-Volatile High Speed & Low Power Charge Trapping Devices

NASA Astrophysics Data System (ADS)

Kim, Moon Kyung; Tiwari, Sandip

2007-06-01

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO2/SiO2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO2/SiO2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ˜0.44 eV for the write process and ˜0.47 eV for the erase process in SiO2/SiO2 structural device which is somewhat more efficient than those of SONOS structure memory.

Directed-Assembly of Carbon Nanotubes on Soft Substrates for Flexible Biosensor Array

NASA Astrophysics Data System (ADS)

Lee, Hyoung Woo; Koh, Juntae; Lee, Byung Yang; Kim, Tae Hyun; Lee, Joohyung; Hong, Seunghun; Yi, Mihye; Jhon, Young Min

2009-03-01

We developed a method to selectively assemble and align carbon nanotubes (CNTs) on soft substrates for flexible biosensors. In this strategy, thin oxide layer was deposited on soft substrates via low temperature plasma enhanced chemical vapor deposition, and linker-free assembly process was applied onto the oxide surface where the assembly of carbon nanotubes was guided by methyl-terminated molecular patterns on the oxide surface. The electrical characterization of the fabricated CNT devices exhibited typical p-type gating effect and 1/f noise behavior. The bare oxide regions near CNTs were functionalized with glutamate oxidase to fabricate selective biosensors to detect two forms of glutamate substances existing in different situations: L-glutamic acid, a neuro-transmitting material, and monosodium glutamate, a food additive.

High-performance single-crystalline arsenic-doped indium oxide nanowires for transparent thin-film transistors and active matrix organic light-emitting diode displays.

PubMed

Chen, Po-Chiang; Shen, Guozhen; Chen, Haitian; Ha, Young-geun; Wu, Chao; Sukcharoenchoke, Saowalak; Fu, Yue; Liu, Jun; Facchetti, Antonio; Marks, Tobin J; Thompson, Mark E; Zhou, Chongwu

2009-11-24

We report high-performance arsenic (As)-doped indium oxide (In(2)O(3)) nanowires for transparent electronics, including their implementation in transparent thin-film transistors (TTFTs) and transparent active-matrix organic light-emitting diode (AMOLED) displays. The As-doped In(2)O(3) nanowires were synthesized using a laser ablation process and then fabricated into TTFTs with indium-tin oxide (ITO) as the source, drain, and gate electrodes. The nanowire TTFTs on glass substrates exhibit very high device mobilities (approximately 1490 cm(2) V(-1) s(-1)), current on/off ratios (5.7 x 10(6)), steep subthreshold slopes (88 mV/dec), and a saturation current of 60 microA for a single nanowire. By using a self-assembled nanodielectric (SAND) as the gate dielectric, the device mobilities and saturation current can be further improved up to 2560 cm(2) V(-1) s(-1) and 160 microA, respectively. All devices exhibit good optical transparency (approximately 81% on average) in the visible spectral range. In addition, the nanowire TTFTs were utilized to control green OLEDs with varied intensities. Furthermore, a fully integrated seven-segment AMOLED display was fabricated with a good transparency of 40% and with each pixel controlled by two nanowire transistors. This work demonstrates that the performance enhancement possible by combining nanowire doping and self-assembled nanodielectrics enables silicon-free electronic circuitry for low power consumption, optically transparent, high-frequency devices assembled near room temperature.

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

NASA Astrophysics Data System (ADS)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Transfer printing of thermoreversible ion gels for flexible electronics.

PubMed

Lee, Keun Hyung; Zhang, Sipei; Gu, Yuanyan; Lodge, Timothy P; Frisbie, C Daniel

2013-10-09

Thermally assisted transfer printing was employed to pattern thin films of high capacitance ion gels on polyimide, poly(ethylene terephthalate), and SiO2 substrates. The ion gels consisted of 20 wt % block copolymer poly(styrene-b-ethylene oxide-b-styrene and 80 wt % ionic liquid 1-ethyl-3-methylimidazolium bis(trifluoromethyl sulfonyl)amide. Patterning resolution was on the order of 10 μm. Importantly, ion gels containing the block polymer with short PS end blocks (3.4 kg/mol) could be transfer-printed because of thermoreversible gelation that enabled intimate gel-substrate contact at 100 °C, while gels with long PS blocks (11 kg/mol) were not printable at the same temperature due to poor wetting contact between the gel and substrates. By using printed ion gels as high-capacitance gate insulators, electrolyte-gated thin-film transistors were fabricated that operated at low voltages (<1 V) with high on/off current ratios (∼10(5)). Statistical analysis of carrier mobility, turn-on voltage, and on/off ratio for an array of printed transistors demonstrated the excellent reproducibility of the printing technique. The results show that transfer printing is an attractive route to pattern high-capacitance ion gels for flexible thin-film devices.

Enhanced performance of solution-processed organic thin-film transistors with a low-temperature-annealed alumina interlayer between the polyimide gate insulator and the semiconductor.

PubMed

Yoon, Jun-Young; Jeong, Sunho; Lee, Sun Sook; Kim, Yun Ho; Ka, Jae-Won; Yi, Mi Hye; Jang, Kwang-Suk

2013-06-12

We studied a low-temperature-annealed sol-gel-derived alumina interlayer between the organic semiconductor and the organic gate insulator for high-performance organic thin-film transistors. The alumina interlayer was deposited on the polyimide gate insulator by a simple spin-coating and 200 °C-annealing process. The leakage current density decreased by the interlayer deposition: at 1 MV/cm, the leakage current densities of the polyimide and the alumina/polyimide gate insulators were 7.64 × 10(-7) and 3.01 × 10(-9) A/cm(2), respectively. For the first time, enhancement of the organic thin-film transistor performance by introduction of an inorganic interlayer between the organic semiconductor and the organic gate insulator was demonstrated: by introducing the interlayer, the field-effect mobility of the solution-processed organic thin-film transistor increased from 0.35 ± 0.15 to 1.35 ± 0.28 cm(2)/V·s. Our results suggest that inorganic interlayer deposition could be a simple and efficient surface treatment of organic gate insulators for enhancing the performance of solution-processed organic thin-film transistors.

Highly stable field emission from ZnO nanowire field emitters controlled by an amorphous indium–gallium–zinc-oxide thin film transistor

NASA Astrophysics Data System (ADS)

Li, Xiaojie; Wang, Ying; Zhang, Zhipeng; Ou, Hai; She, Juncong; Deng, Shaozhi; Xu, Ningsheng; Chen, Jun

2018-04-01

Lowering the driving voltage and improving the stability of nanowire field emitters are essential for them to be applied in devices. In this study the characteristics of zinc oxide (ZnO) nanowire field emitter arrays (FEAs) controlled by an amorphous indium–gallium–zinc-oxide thin film transistor (a-IGZO TFT) were studied. A low driving voltage along with stabilization of the field emission current were achieved. Modulation of field emission currents up to three orders of magnitude was achieved at a gate voltage of 0–32 V for a constant anode voltage. Additionally, a-IGZO TFT control can dramatically reduce the emission current fluctuation (i.e., from 46.11 to 1.79% at an emission current of ∼3.7 µA). Both the a-IGZO TFT and ZnO nanowire FEAs were prepared on glass substrates in our research, demonstrating the feasibility of realizing large area a-IGZO TFT-controlled ZnO nanowire FEAs.

Thin-Film Transistors Fabricated Using Sputter Deposition of Zinc Oxide

NASA Astrophysics Data System (ADS)

Xiao, Nan

2013-01-01

Development of thin film transistors (TFTs) with conventional channel layer materials, such as amorphous silicon (a-Si) and polysilicon (poly-Si), has been extensively investigated. A-Si TFT currently serves the large flat panel industry; however advanced display products are demanding better TFT performance because of the associated low electron mobility of a-Si. This has motivated interest in semiconducting metal oxides, such as Zinc Oxide (ZnO), for TFT backplanes. This work involves the fabrication and characterization of TFTs using ZnO deposited by sputtering. An overview of the process details and results from recently fabricated TFTs following a full-factorial designed experiment will be presented. Material characterization and analysis of electrical results will be described. The investigated process variables were the gate dielectric and ZnO sputtering process parameters including power density and oxygen partial pressure. Electrical results showed clear differences in treatment combinations, with certain I-V characteristics demonstrating superior performance to preliminary work. A study of device stability will also be discussed.

3.4-Inch Quarter High Definition Flexible Active Matrix Organic Light Emitting Display with Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Hatano, Kaoru; Chida, Akihiro; Okano, Tatsuya; Sugisawa, Nozomu; Inoue, Tatsunori; Seo, Satoshi; Suzuki, Kunihiko; Oikawa, Yoshiaki; Miyake, Hiroyuki; Koyama, Jun; Yamazaki, Shunpei; Eguchi, Shingo; Katayama, Masahiro; Sakakura, Masayuki

2011-03-01

In this paper, we report a 3.4-in. flexible active matrix organic light emitting display (AMOLED) display with remarkably high definition (quarter high definition: QHD) in which oxide thin film transistors (TFTs) are used. We have developed a transfer technology in which a TFT array formed on a glass substrate is separated from the substrate by physical force and then attached to a flexible plastic substrate. Unlike a normal process in which a TFT array is directly fabricated on a thin plastic substrate, our transfer technology permits a high integration of high performance TFTs, such as low-temperature polycrystalline silicon TFTs (LTPS TFTs) and oxide TFTs, on a plastic substrate, because a flat, rigid, and thermally-stable glass substrate can be used in the TFT fabrication process in our transfer technology. As a result, this technology realized an oxide TFT array for an AMOLED on a plastic substrate. Furthermore, in order to achieve a high-definition AMOLED, color filters were incorporated in the TFT array and a white organic light-emitting diode (OLED) was combined. One of the features of this device is that the whole body of the device can be bent freely because a source driver and a gate driver can be integrated on the substrate due to the high mobility of an oxide TFT. This feature means “true” flexibility.

Low-temperature sol-gel oxide TFT with a fluoropolymer dielectric to enhance the effective mobility at low operation voltage

NASA Astrophysics Data System (ADS)

Yu, Shang-Yu; Wang, Kuan-Hsun; Zan, Hsiao-Wen; Soppera, Olivier

2017-06-01

In this article, we propose a solution-processed high-performance amorphous indium-zinc oxide (a-IZO) thin-film transistor (TFT) gated with a fluoropolymer dielectric. Compared with a conventional IZO TFT with a silicon nitride dielectric, a fluoropolymer dielectric effectively reduces the operation voltage to less than 3 V and greatly increases the effective mobility 40-fold. We suggest that the dipole layer formed at the dielectric surface facilitates electron accumulation and induces the electric double-layer effect. The dipole-induced hysteresis effect is also investigated.

Ultra-sensitive suspended atomically thin-layered black phosphorus mercury sensors.

PubMed

Li, Peng; Zhang, Dongzhi; Jiang, Chuanxing; Zong, Xiaoqi; Cao, Yuhua

2017-12-15

The extraordinary properties of black phosphorus (BP) make it a promising candidate for next-generation transistor chemical sensors. However, BP films reported so far are supported on substrate, and substrate scattering drastically deteriorates its electrical properties. Consequentially, the potential sensing capability of intrinsic BP is highly underestimated and its sensing mechanism is masked. Additionally, the optimum sensing regime of BP remains unexplored. This article is the first demonstration of suspended BP sensor operated in subthreshold regime. BP exhibited significant enhancement of sensitivity for ultra-low-concentration mercury detection in the absence of substrate, and the sensitivity reached maximum in subthreshold regime. Without substrate scattering, the suspended BP device demonstrated 10 times lower 1/f noise which contributed to better signal-to-noise ratio. Therefore, rapid label-free trace detection of Hg 2+ was achieved with detection limit of 0.01 ppb, lower than the world health organization (WHO) tolerance level (1 ppb). The time constant for ion detection extracted was 3s. Additionally, experimental results revealed that good stability, repeatability, and selectivity were achieved. BP sensors also demonstrated the ability of detecting mercury ions in environment water samples. The underling sensing mechanism of intrinsic BP was ascribed to the carrier density variation resulted from surface charge gating effect, so suspended BP in subthreshold regime with optimum gating effect demonstrated the best sensitivity. Our results show the prominent advantages of intrinsic BP as a sensing material. Copyright © 2017 The Authors. Published by Elsevier B.V. All rights reserved.

The low temperature oxidation of lithium thin films on HOPG by O 2 and H 2O

DOE PAGES

Wulfsberg, Steven M.; Koel, Bruce E.; Bernasek, Steven L.

2016-04-16

Lithiated graphite and lithium thin films have been used in fusion devices. In this environment, lithiated graphite will undergo oxidation by background gases. In order to gain insight into this oxidation process, thin (< 15 monolayer (ML)) lithium films on highly ordered pyrolytic graphite (HOPG) were exposed in this paper to O 2(g) and H 2O (g) in an ultra-high vacuum chamber. High resolution electron energy loss spectroscopy (HREELS) was used to identify the surface species formed during O 2(g) and H 2O (g) exposure. Auger electron spectroscopy (AES) was used to obtain the relative oxidation rates during O 2(g)more » and H 2O (g) exposure. AES showed that as the lithium film thickness decreased from 15 to 5 to 1 ML, the oxidation rate decreased for both O 2(g) and H 2O (g). HREELS showed that a 15 ML lithium film was fully oxidized after 9.7 L (L) of O 2(g) exposure and Li 2O was formed. HREELS also showed that during initial exposure (< 0.5 L) H 2O (g), lithium hydride and lithium hydroxide were formed on the surface of a 15 ML lithium film. Finally, after 0.5 L of H 2O (g) exposure, the H 2O (g) began to physisorb, and after 15 L of H 2O (g) exposure, the 15 ML lithium film was not fully oxidized.« less

The low temperature oxidation of lithium thin films on HOPG by O 2 and H 2O

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wulfsberg, Steven M.; Koel, Bruce E.; Bernasek, Steven L.

Lithiated graphite and lithium thin films have been used in fusion devices. In this environment, lithiated graphite will undergo oxidation by background gases. In order to gain insight into this oxidation process, thin (< 15 monolayer (ML)) lithium films on highly ordered pyrolytic graphite (HOPG) were exposed in this paper to O 2(g) and H 2O (g) in an ultra-high vacuum chamber. High resolution electron energy loss spectroscopy (HREELS) was used to identify the surface species formed during O 2(g) and H 2O (g) exposure. Auger electron spectroscopy (AES) was used to obtain the relative oxidation rates during O 2(g)more » and H 2O (g) exposure. AES showed that as the lithium film thickness decreased from 15 to 5 to 1 ML, the oxidation rate decreased for both O 2(g) and H 2O (g). HREELS showed that a 15 ML lithium film was fully oxidized after 9.7 L (L) of O 2(g) exposure and Li 2O was formed. HREELS also showed that during initial exposure (< 0.5 L) H 2O (g), lithium hydride and lithium hydroxide were formed on the surface of a 15 ML lithium film. Finally, after 0.5 L of H 2O (g) exposure, the H 2O (g) began to physisorb, and after 15 L of H 2O (g) exposure, the 15 ML lithium film was not fully oxidized.« less

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

PubMed Central

Park, Jae Hyo; Jang, Gil Su; Kim, Hyung Yoon; Seok, Ki Hwan; Chae, Hee Jae; Lee, Sol Kyu; Joo, Seung Ki

2016-01-01

Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature. PMID:27098115

Development of a radiation-hard CMOS process

NASA Technical Reports Server (NTRS)

Power, W. L.

1983-01-01

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samanta, Piyas, E-mail: piyas@vcfw.org; Mandal, Krishna C., E-mail: mandalk@cec.sc.edu

2016-08-14

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV belowmore » the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

Nanowire decorated, ultra-thin, single crystalline silicon for photovoltaic devices.

PubMed

Aurang, Pantea; Turan, Rasit; Unalan, Husnu Emrah

2017-10-06

Reducing silicon (Si) wafer thickness in the photovoltaic industry has always been demanded for lowering the overall cost. Further benefits such as short collection lengths and improved open circuit voltages can also be achieved by Si thickness reduction. However, the problem with thin films is poor light absorption. One way to decrease optical losses in photovoltaic devices is to minimize the front side reflection. This approach can be applied to front contacted ultra-thin crystalline Si solar cells to increase the light absorption. In this work, homojunction solar cells were fabricated using ultra-thin and flexible single crystal Si wafers. A metal assisted chemical etching method was used for the nanowire (NW) texturization of ultra-thin Si wafers to compensate weak light absorption. A relative improvement of 56% in the reflectivity was observed for ultra-thin Si wafers with the thickness of 20 ± 0.2 μm upon NW texturization. NW length and top contact optimization resulted in a relative enhancement of 23% ± 5% in photovoltaic conversion efficiency.

Influence of preparation design and ceramic thicknesses on fracture resistance and failure modes of premolar partial coverage restorations

PubMed Central

Guess, Petra C.; Schultheis, Stefan; Wolkewitz, Martin; Zhang; Strub, Joerg R.

2015-01-01

Statement of problem Preparation designs and ceramic thicknesses are key factors for the long-term success of minimally invasive premolar partial coverage restorations. However, only limited information is presently available on this topic. Purpose The aim of this in vitro study was to evaluate the fracture resistance and failure modes of ceramic premolar partial coverage restorations with different preparation designs and ceramic thicknesses. Material and methods Caries-free human premolars (n= 144) were divided into 9 groups. Palatal onlay preparation comprised reduction of the palatal cusp by 2 mm (Palatal-Onlay-Standard), 1 mm (Palatal-Onlay-Thin), or 0.5 mm (Palatal-Onlay-Ultra-Thin). Complete-coverage onlay preparation additionally included the buccal cusp (Occlusal-Onlay-Standard; Occlusal-Onlay-Thin; Occlusal-Onlay-Ultra-Thin). Labial surface preparations with chamfer reductions of 0.8 mm (Complete-Veneer-Standard), 0.6 mm (Complete-Veneer-Thin) and 0.4 mm (Complete-Veneer-Ultra-Thin) were implemented for complete veneer restorations. Restorations were fabricated from a pressable lithium-disilicate ceramic (IPS-e.max-Press) and cemented adhesively (Syntac-Classic/Variolink-II). All specimens were subjected to cyclic mechanical loading (F= 49 N, 1.2 million cycles) and simultaneous thermocycling (5°C to 55°C) in a mouth-motion simulator. After fatigue, restorations were exposed to single-load-to-failure. Two-way ANOVA was used to identify statistical differences. Pair-wise differences were calculated and P-values were adjusted by the Tukey–Kramer method (α= .05). Results All specimens survived fatigue. Mean (SD) load to failure values (N) were as follows: 837 (320/Palatal-Onlay-Standard), 1055 (369/Palatal-Onlay-Thin), 1192 (342/Palatal-Onlay-Ultra-Thin), 963 (405/Occlusal-Onlay-Standard), 1108 (340/Occlusal-Onlay-Thin), 997 (331/Occlusal-Onlay-Ultra-Thin), 1361 (333/Complete-Veneer-Standard), 1087 (251/Complete-Veneer-Thin), 883 (311/Complete-Veneer-Ultra-Thin). Palatal-onlay restorations revealed a significantly higher fracture resistance with ultra-thin thicknesses than with standard thicknesses (P=.015). Onlay restorations were not affected by thickness variations. Fracture loads of standard complete veneers were significantly higher than thin (P=.03) and ultra-thin (P<.001) restorations. Conclusions In this in vitro study, the reduction of preparation depth to 1.00 and 0.5 mm did not impair fracture resistance of pressable lithium-disilicate ceramic onlay restorations but resulted in lower failure loads in complete veneer restorations on premolars. PMID:24079561

Ultra-low voltage and ultra-low power consumption nonvolatile operation of a three-terminal atomic switch.

PubMed

Wang, Qi; Itoh, Yaomi; Tsuruoka, Tohru; Aono, Masakazu; Hasegawa, Tsuyoshi

2015-10-21

Nonvolatile three-terminal operation, with a very small range of bias sweeping (-80 to 250 mV), a high on/off ratio of up to six orders of magnitude, and a very small gate leakage current (<1 pA), is demonstrated using an Ag (gate)/Ta2 O5 (ionic transfer layer)/Pt (source), Pt (drain) three-terminal atomic switch structure. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Enhanced Electroluminescence from Silicon Quantum Dots Embedded in Silicon Nitride Thin Films Coupled with Gold Nanoparticles in Light Emitting Devices

PubMed Central

Muñoz-Rosas, Ana Luz; Alonso-Huitrón, Juan Carlos

2018-01-01

Nowadays, the use of plasmonic metal layers to improve the photonic emission characteristics of several semiconductor quantum dots is a booming tool. In this work, we report the use of silicon quantum dots (SiQDs) embedded in a silicon nitride thin film coupled with an ultra-thin gold film (AuNPs) to fabricate light emitting devices. We used the remote plasma enhanced chemical vapor deposition technique (RPECVD) in order to grow two types of silicon nitride thin films. One with an almost stoichiometric composition, acting as non-radiative spacer; the other one, with a silicon excess in its chemical composition, which causes the formation of silicon quantum dots imbibed in the silicon nitride thin film. The ultra-thin gold film was deposited by the direct current (DC)-sputtering technique, and an aluminum doped zinc oxide thin film (AZO) which was deposited by means of ultrasonic spray pyrolysis, plays the role of the ohmic metal-like electrode. We found that there is a maximum electroluminescence (EL) enhancement when the appropriate AuNPs-spacer-SiQDs configuration is used. This EL is achieved at a moderate turn-on voltage of 11 V, and the EL enhancement is around four times bigger than the photoluminescence (PL) enhancement of the same AuNPs-spacer-SiQDs configuration. From our experimental results, we surmise that EL enhancement may indeed be due to a plasmonic coupling. This kind of silicon-based LEDs has the potential for technology transfer. PMID:29565267

Low-cost ultra-thin broadband terahertz beam-splitter.

PubMed

Ung, Benjamin S-Y; Fumeaux, Christophe; Lin, Hungyen; Fischer, Bernd M; Ng, Brian W-H; Abbott, Derek

2012-02-27

A low-cost terahertz beam-splitter is fabricated using ultra-thin LDPE plastic sheeting coated with a conducting silver layer. The beam splitting ratio is determined as a function of the thickness of the silver layer--thus any required splitting ratio can be printed on demand with a suitable rapid prototyping technology. The low-cost aspect is a consequence of the fact that ultra-thin LDPE sheeting is readily obtainable, known more commonly as domestic plastic wrap or cling wrap. The proposed beam-splitter has numerous advantages over float zone silicon wafers commonly used within the terahertz frequency range. These advantages include low-cost, ease of handling, ultra-thin thickness, and any required beam splitting ratio can be readily fabricated. Furthermore, as the beam-splitter is ultra-thin, it presents low loss and does not suffer from Fabry-Pérot effects. Measurements performed on manufactured prototypes with different splitting ratios demonstrate a good agreement with our theoretical model in both P and S polarizations, exhibiting nearly frequency-independent splitting ratios in the terahertz frequency range.

Ultra-thin whitetopping for general aviation airports in New Mexico.

DOT National Transportation Integrated Search

2002-06-01

Whitetopping is a pavement rehabilitation construction practice where portland cement concrete (PCC) is placed over an existing asphalt concrete pavement as an overlay. Ultra-thin whitetopping (UTW) is generally a thin overlay with a thickness betwee...

Sub-2 nm Thick Fluoroalkylsilane Self-Assembled Monolayer-Coated High Voltage Spinel Crystals as Promising Cathode Materials for Lithium Ion Batteries

PubMed Central

Zettsu, Nobuyuki; Kida, Satoru; Uchida, Shuhei; Teshima, Katsuya

2016-01-01

We demonstrate herein that an ultra-thin fluoroalkylsilane self-assembled monolayer coating can be used as a modifying agent at LiNi0.5Mn1.5O4−δcathode/electrolyte interfaces in 5V-class lithium-ion batteries. Bare LiNi0.5Mn1.5O4−δ cathode showed substantial capacity fading, with capacity dropping to 79% of the original capacity after 100 cycles at a rate of 1C, which was entirely due to dissolution of Mn3+ from the spinel lattice via oxidative decomposition of the organic electrolyte. Capacity retention was improved to 97% on coating ultra-thin FAS17-SAM onto the LiNi0.5Mn1.5O4 cathode surface. Such surface protection with highly ordered fluoroalkyl chains insulated the cathode from direct contact with the organic electrolyte and led to increased tolerance to HF. PMID:27553901

Ultra-violet absorption induced modifications in bulk and nanoscale electrical transport properties of Al-doped ZnO thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Mohit; Basu, Tanmoy; Som, Tapobrata, E-mail: tsom@iopb.res.in

Using conductive atomic force microscopy and Kelvin probe force microscopy, we study local electrical transport properties in aluminum-doped zinc oxide (ZnO:Al or AZO) thin films. Current mapping shows a spatial variation in conductivity which corroborates well with the local mapping of donor concentration (∼10{sup 20 }cm{sup −3}). In addition, a strong enhancement in the local current at grains is observed after exposing the film to ultra-violet (UV) light which is attributed to persistent photocurrent. Further, it is shown that UV absorption gives a smooth conduction in AZO film which in turn gives rise to an improvement in the bulk photoresponsivity ofmore » an n-AZO/p-Si heterojunction diode. This finding is in contrast to the belief that UV absorption in an AZO layer leads to an optical loss for the underneath absorbing layer of a heterojunction solar cell.« less

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Ultra-Low-Cost Room Temperature SiC Thin Films

NASA Technical Reports Server (NTRS)

Faur, Maria

1997-01-01

The research group at CSU has conducted theoretical and experimental research on 'Ultra-Low-Cost Room Temperature SiC Thin Films. The effectiveness of a ultra-low-cost room temperature thin film SiC growth technique on Silicon and Germanium substrates and structures with applications to space solar sells, ThermoPhotoVoltaic (TPV) cells and microelectronic and optoelectronic devices was investigated and the main result of this effort are summarized.

Epitaxial pentacene films grown on the surface of ion-beam-processed gate dielectric layer

NASA Astrophysics Data System (ADS)

Chou, W. Y.; Kuo, C. W.; Cheng, H. L.; Mai, Y. S.; Tang, F. C.; Lin, S. T.; Yeh, C. Y.; Horng, J. B.; Chia, C. T.; Liao, C. C.; Shu, D. Y.

2006-06-01

The following research describes the process of fabrication of pentacene films with submicron thickness, deposited by thermal evaporation in high vacuum. The films were fabricated with the aforementioned conditions and their characteristics were analyzed using x-ray diffraction, scanning electron microscopy, polarized Raman spectroscopy, and photoluminescence. Organic thin-film transistors (OTFTs) were fabricated on an indium tin oxide coated glass substrate, using an active layer of ordered pentacene molecules, which were grown at room temperature. Pentacene film was aligned using the ion-beam aligned method, which is typically employed to align liquid crystals. Electrical measurements taken on a thin-film transistor indicated an increase in the saturation current by a factor of 15. Pentacene-based OTFTs with argon ion-beam-processed gate dielectric layers of silicon dioxide, in which the direction of the ion beam was perpendicular to the current flow, exhibited a mobility that was up to an order of magnitude greater than that of the controlled device without ion-beam process; current on/off ratios of approximately 106 were obtained. Polarized Raman spectroscopy investigation indicated that the surface of the gate dielectric layer, treated with argon ion beam, enhanced the intermolecular coupling of pentacene molecules. The study also proposes the explanation for the mechanism of carrier transportation in pentacene films.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Masuda, Takuya; PRESTO, Japan Science and Technology Agency; Yoshikawa, Hideki

In situ electrochemical X-ray photoelectron spectroscopy (XPS) apparatus, which allows XPS at solid/liquid interfaces under potential control, was constructed utilizing a microcell with an ultra-thin Si membrane, which separates vacuum and a solution. Hard X-rays from a synchrotron source penetrate into the Si membrane surface exposed to the solution. Electrons emitted at the Si/solution interface can pass through the membrane and be analyzed by an analyzer placed in vacuum. Its operation was demonstrated for potential-induced Si oxide growth in water. Effect of potential and time on the thickness of Si and Si oxide layers was quantitatively determined at sub-nanometer resolution.

Determining thickness and refractive index from free-standing ultra-thin polymer films with spectroscopic ellipsometry

DOE PAGES

Hilfiker, James N.; Stadermann, Michael; Sun, Jianing; ...

2016-08-27

It is a well-known challenge to determine refractive index (n) from ultra-thin films where the thickness is less than about 10 nm. In this paper, we discovered an interesting exception to this issue while characterizing spectroscopic ellipsometry (SE) data from isotropic, free-standing polymer films. Ellipsometry analysis shows that both thickness and refractive index can be independently determined for free-standing films as thin as 5 nm. Simulations further confirm an orthogonal separation between thickness and index effects on the experimental SE data. Effects of angle of incidence and wavelength on the data and sensitivity are discussed. Finally, while others have demonstratedmore » methods to determine refractive index from ultra-thin films, our analysis provides the first results to demonstrate high-sensitivity to the refractive index from ultra-thin layers.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

NASA Astrophysics Data System (ADS)

Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

2018-06-01

Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lai, Hsin-Cheng; Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw; Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan

In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100 °C. The a-IGZO TFT exhibit a mobility of 5.13 cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4 mm (strain = 1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10 V for 1500 s. Thus, this technology ismore » suitable for use in flexible displays.« less

Numerical simulation of offset-drain amorphous oxide-based thin-film transistors

NASA Astrophysics Data System (ADS)

Jeong, Jaewook

2016-11-01

In this study, we analyzed the electrical characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with an offset-drain structure by technology computer aided design (TCAD) simulation. When operating in a linear region, an enhancement-type TFT shows poor field-effect mobility because most conduction electrons are trapped in acceptor-like defects in an offset region when the offset length (L off) exceeds 0.5 µm, whereas a depletion-type TFT shows superior field-effect mobility owing to the high free electron density in the offset region compared with the trapped electron density. When operating in the saturation region, both types of TFTs show good field-effect mobility comparable to that of a reference TFT with a large gate overlap. The underlying physics of the depletion and enhancement types of offset-drain TFTs are systematically analyzed.

Fabrication and Characteristics of High Mobility InSnZnO Thin Film Transistors.

PubMed

Choi, Pyungho; Lee, Junki; Park, Hyoungsun; Baek, Dohyun; Lee, Jaehyeong; Yi, Junsin; Kim, Sangsoo; Choi, Byoungdeog

2016-05-01

In this paper, we describe the fabrication of thin film transistors (TFTs) with amorphous indium-tin-zinc-oxide (ITZO) as the active material. A transparent ITZO channel layer was formed under an optimized oxygen partial pressure (OPP (%) = O2/(Ar + O2)) and subsequent annealing process. The electrical properties exhibited by this device include field-effect mobility (μ(eff)), sub-threshold swing (SS), and on/off current ratio (I(ON/OFF)) values of 28.97 cm2/V x s, 0.2 V/decade, and 2.64 x 10(7), respectively. The average transmittance values for each OPP condition in the visible range were greater than 80%. The positive gate bias stress resulted in a positive threshold voltage (V(th)) shift in the transfer curves and degraded the parameters μ(eff) and SS. These phenomena originated from electron trapping from the ITZO channel layer into the oxide/ITZO interface trap sites.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate.

PubMed

Han, Dedong; Zhang, Yi; Cong, Yingying; Yu, Wen; Zhang, Xing; Wang, Yi

2016-12-12

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O 2 /Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O 2 /Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (I off ) of 3 pA, a high on/off current ratio of 2 × 10 7 , a high saturation mobility (μ sat ) of 66.7 cm 2 /V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (V th ) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Fully transparent flexible tin-doped zinc oxide thin film transistors fabricated on plastic substrate

NASA Astrophysics Data System (ADS)

Han, Dedong; Zhang, Yi; Cong, Yingying; Yu, Wen; Zhang, Xing; Wang, Yi

2016-12-01

In this work, we have successfully fabricated bottom gate fully transparent tin-doped zinc oxide thin film transistors (TZO TFTs) fabricated on flexible plastic substrate at low temperature by RF magnetron sputtering. The effect of O2/Ar gas flow ratio during channel deposition on the electrical properties of TZO TFTs was investigated, and we found that the O2/Ar gas flow ratio have a great influence on the electrical properties. TZO TFTs on flexible substrate has very nice electrical characteristics with a low off-state current (Ioff) of 3 pA, a high on/off current ratio of 2 × 107, a high saturation mobility (μsat) of 66.7 cm2/V•s, a steep subthreshold slope (SS) of 333 mV/decade and a threshold voltage (Vth) of 1.2 V. Root-Mean-Square (RMS) roughness of TZO thin film is about 0.52 nm. The transmittance of TZO thin film is about 98%. These results highlight that the excellent device performance can be realized in TZO film and TZO TFT can be a promising candidate for flexible displays.

Front and backside processed thin film electronic devices

DOEpatents

Evans, Paul G [Madison, WI; Lagally, Max G [Madison, WI; Ma, Zhenqiang [Middleton, WI; Yuan, Hao-Chih [Lakewood, CO; Wang, Guogong [Madison, WI; Eriksson, Mark A [Madison, WI

2012-01-03

This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

A Novel Femtosecond-gated, High-resolution, Frequency-shifted Shearing Interferometry Technique for Probing Pre-plasma Expansion in Ultra-intense Laser Experiments

DTIC Science & Technology

2014-07-17

frequency-shifted shearing interferometry technique for probing pre-plasma expansion in ultra-intense laser experimentsa) Ultra-intense laser -matter...interaction experiments (>1018 W/cm2) with dense targets are highly sensitive to the effect of laser “noise” (in the form of pre-pulses) preceding the...interferometry technique for probing pre- plasma expansion in ultra-intense laser experimentsa) Report Title Ultra-intense laser -matter interaction

High transconductance zinc oxide thin-film transistors on flexible plastic substrates

NASA Astrophysics Data System (ADS)

Kimura, Yuta; Higaki, Tomohiro; Maemoto, Toshihiko; Sasa, Shigehiko; Inoue, Masataka

2012-02-01

We report the fabrication and characterization on high-performance ZnO based TFTs on unheated plastic substrate. ZnO films were grown by pulsed laser deposition (PLD) on polyethylene napthalate (PEN) substrates. Top-gate ZnO-TFTs were fabricated by photolithography and wet chemical etching. The source and drain contacts were formed by lift-off of e-beam deposited Ti(20 nm)/Au(200 nm). An HfO2 with thickness 100 nm was selected as the gate insulator, and top gate electrode Ti(20 nm)/Au(200 nm) was deposited by e-beam evaporation. We prepared a set of the structure with SiO2/TiO2 to investigate the characteristic changes that appear in the film characteristics in response to bending. From the ID-VDS and the transfer characteristics which are affected by bending and return for the ZnO-TFT with SiO2/TiO2 buffers, the TFTs were bent to a curvature radius of 8.5 mm. The transconductance, gm is obtained 1.7 mS/mm on flat, 1.4 mS/mm on bending and 1.3 mS/mm on returning the film, respectively. The ID-VDS characteristics were therefore not changed by bending. All of the devices exhibited a clear pinch-off behavior and a high on/off current ratio of ˜10^6. The threshold voltages, Vth were not changed drastically. Furthermore, TFT structures were changed from a conventional top-gate type to a bottom-gate type. A high transconductance of 95.8 mS/mm was achieved in the bottom-gate type TFT by using Al2O3 oxide buffer.

Commercial aspects of epitaxial thin film growth in outer space

NASA Technical Reports Server (NTRS)

Ignatiev, Alex; Chu, C. W.

1988-01-01

A new concept for materials processing in space exploits the ultra vacuum component of space for thin film epitaxial growth. The unique low earth orbit space environment is expected to yield 10 to the -14th torr or better pressures, semiinfinite pumping speeds and large ultra vacuum volume (about 100 cu m) without walls. These space ultra vacuum properties promise major improvement in the quality, unique nature, and the throughput of epitaxially grown materials especially in the area of semiconductors for microelectronics use. For such thin film materials there is expected a very large value added from space ultra vacuum processing, and as a result the application of the epitaxial thin film growth technology to space could lead to major commercial efforts in space.

Directed assembly of carbon nanotubes on soft substrates for use as a flexible biosensor array.

PubMed

Koh, Juntae; Yi, Mihye; Yang Lee, Byung; Kim, Tae Hyun; Lee, Joohyung; Jhon, Young Min; Hong, Seunghun

2008-12-17

We have developed a method to selectively assemble and align carbon nanotubes (CNTs) on soft substrates for use as flexible biosensors. In this strategy, a thin oxide layer was deposited on soft substrates via low temperature plasma enhanced chemical vapor deposition, and a linker-free assembly process was applied on the oxide surface where the assembly of carbon nanotubes was guided by methyl-terminated molecular patterns on the oxide surface. The electrical characterization of the fabricated CNT devices exhibited a typical p-type gating effect and 1/f noise behavior. The bare oxide regions near CNTs were functionalized with glutamate oxidase to fabricate selective biosensors to detect two forms of glutamate substances existing in different situations: L-glutamic acid, a neurotransmitting material, and monosodium glutamate, a food additive.

Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Choi, Woo Young

2017-04-01

The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal-oxide-semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Scaling behavior of fully spin-coated TFT

NASA Astrophysics Data System (ADS)

Mondal, Sandip; Kumar, Arvind; Rao, K. S. R. Koteswara; Venkataraman, V.

2017-05-01

We studied channel scaling behavior of fully spin coated, low temperature solution processed thin film transistor (TFT) fabricated on p++ - Si (˜1021 cm-3) as bottom gate. The solution processed, spin coated 40 nm thick amorphous Indium Gallium Zinc Oxide (a-IGZO) and 50 nm thick amorphous zirconium di-oxide (a-ZrO2) has been used as channel and low leakage dielectric at 350°C respectively. The channel scaling effect of the TFT with different width/length ratio (W/L= 2.5, 5 and 15) for same channel length (L = 10 μm) has been demonstrated. The lowest threshold voltage (Vth) is 6.25 V for the W/L=50/10. The maximum field effect mobility (μFE) has been found to be 0.123 cm2/Vs from W/L of 50/10 with the drain to source voltage (VD) of 10V and 20V gate to source voltage (VG). We also demonstrated that there is no contact resistance effect on the mobility of the fully sol-gel spin coated TFT.

Optimization of exchange bias in Co/CoO magnetic nanocaps by tuning deposition parameters

NASA Astrophysics Data System (ADS)

Sharma, A.; Tripathi, J.; Ugochukwu, K. C.; Tripathi, S.

2017-03-01

In the present work, we report exchange bias tuning by varying thin film deposition parameters such as synthesis method and underlying layer patterning. The patterned substrates for this study were prepared by self-assembly of polystyrene (PS) latex spheres ( 530 nm) on Si (100) substrate. The desired magnetic nanocaps composed of CoO/Co bilayer film on these patterned substrates were prepared by molecular beam epitaxy technique under ultra-high vacuum conditions. For this, a Co layer of 10 nm thickness was deposited on the substrates and then oxidized in-situ to form CoO/Co/PS in-situ oxidized film or ex-situ in ambiance which also gives CoO/Co/PS naturally oxidized film. Simultaneously, reference thin films of Co ( 10 nm) were also prepared on plane Si substrate and similar oxidation treatments were performed on them respectively. The magnetic properties studied using SQUID technique revealed higher exchange bias ( 1736 Oe) in the in-situ oxidized Co/PS film as compared to that in naturally oxidized Co/PS film ( 1544 Oe) and also compared to the reference film. The observed variations in the magnetic properties are explained in terms of surface patterning induced structural changes of the deposited films and different oxidation methods.

Threshold voltage tuning in AlGaN/GaN HFETs with p-type Cu2O gate synthesized by magnetron reactive sputtering

NASA Astrophysics Data System (ADS)

Wang, Lei; Li, Liuan; Xie, Tian; Wang, Xinzhi; Liu, Xinke; Ao, Jin-Ping

2018-04-01

In present study, copper oxide films were prepared at different sputtering powers (10-100 W) using magnetron reactive sputtering. The crystalline structure, surface morphologies, composition, and optical band gap of the as-grown films are dependent on sputtering power. As the sputtering power decreasing from 100 to 10 W, the composition of films changed from CuO to quasi Cu2O domination. Moreover, when the sputtering power is 10 W, a relative high hole carrier density and high-surface-quality quasi Cu2O thin film can be achieved. AlGaN/GaN HFETs were fabricated with the optimized p-type quasi Cu2O film as gate electrode, the threshold voltage of the device shows a 0.55 V positive shift, meanwhile, a lower gate leakage current, a higher ON/OFF drain current ratio of ∼108, a higher electron mobility (1465 cm2/Vs), and a lower subthreshold slope of 74 mV/dec are also achieved, compared with the typical Ni/Au-gated HFETs. Therefore, Cu2O have a great potential to develop high performance p-type gate AlGaN/GaN HFETs.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Growth and Surface Modification of LaFeO3 Thin Films Induced By Reductive Annealing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Flynn, Brendan T.; Zhang, Hongliang; Shutthanandan, V.

2015-03-01

The electronic and ionic conductivity of perovskite oxides has enabled their use in diverse applications such as automotive exhaust catalysts, solid oxide fuel cell cathodes, and visible light photocatalysts. The redox chemistry at the surface of perovskite oxides is largely dependent on the oxidation state of the metal cations as well as the oxide surface stoichiometry. In this study, LaFeO3 (LFO) thin films grown on yttria-stabilized zirconia (YSZ) was characterized using both bulk and surface sensitive techniques. A combination of in situ reflection high energy electron diffraction (RHEED), x-ray diffraction (XRD), transmission electron microscopy (TEM) and Rutherford backscattering spectrometry (RBS)more » demonstrated that the film is highly oriented and stoichiometric. The film was annealed in an ultra-high vacuum chamber to simulate reducing conditions and studied by angle-resolved x-ray photoelectron spectroscopy (XPS). Iron was found to exist as Fe(0), Fe(II), and Fe(III) depending on the annealing conditions and the depth within the film. A decrease in the concentration of surface oxygen species was correlated with iron reduction. These results should help guide and enhance the design of perovskite materials for catalysts.« less

Ultra thin metallic coatings to control near field radiative heat transfer

NASA Astrophysics Data System (ADS)

Esquivel-Sirvent, R.

2016-09-01

We present a theoretical calculation of the changes in the near field radiative heat transfer between two surfaces due to the presence of ultra thin metallic coatings on semiconductors. Depending on the substrates, the radiative heat transfer is modulated by the thickness of the ultra thin film. In particular we consider gold thin films with thicknesses varying from 4 to 20 nm. The ultra-thin film has an insulator-conductor transition close to a critical thickness of dc = 6.4 nm and there is an increase in the near field spectral heat transfer just before the percolation transition. Depending on the substrates (Si or SiC) and the thickness of the metallic coatings we show how the near field heat transfer can be increased or decreased as a function of the metallic coating thickness. The calculations are based on available experimental data for the optical properties of ultrathin coatings.

Fabrication of high-performance InGaZnOx thin film transistors based on control of oxidation using a low-temperature plasma

NASA Astrophysics Data System (ADS)

Takenaka, Kosuke; Endo, Masashi; Uchida, Giichiro; Setsuhara, Yuichi

2018-04-01

This work demonstrated the low-temperature control of the oxidation of Amorphous InGaZnOx (a-IGZO) films using inductively coupled plasma as a means of precisely tuning the properties of thin film transistors (TFTs) and as an alternative to post-deposition annealing at high temperatures. The effects of the plasma treatment of the as-deposited a-IGZO films were investigated by assessing the electrical properties of TFTs incorporating these films. A TFT fabricated using an a-IGZO film exposed to an Ar-H2-O2 plasma at substrate temperatures as low as 300 °C exhibited the best performance, with a field effect mobility as high as 42.2 cm2 V-1 s-1, a subthreshold gate voltage swing of 1.2 V decade-1, and a threshold voltage of 2.8 V. The improved transfer characteristics of TFTs fabricated with a-IGZO thin films treated using an Ar-H2-O2 plasma are attributed to the termination of oxygen vacancies around Ga and Zn atoms by OH radicals in the gas phase.

Evolution of zirconyl-stearate Langmuir monolayers and the synthesized ZrO2 thin films with pH

NASA Astrophysics Data System (ADS)

Choudhary, Raveena; Sharma, Rajni; Brar, Loveleen K.

2018-04-01

ZrO2 thin films have a wide range of applications ranging from photonics, antireflection coatings, and resistive oxygen gas sensors, as a gate dielectric and in high temperature fuel cells. We have used the deposition of zirconyl stearate monolayers followed by their oxidation as a method for the synthesis of zirconium oxide thin films. The zirconyl stearate films have been studied and deposited for first time to the best of our knowledge. The Langmuir monolayers are studied using pressure-Area (π-A) isotherms and oscillatory barrier method. The morphology of the films for limited number of layers was studied with FE-SEM to determine the effect of pH on the final ZrO2 film. The 200 layer deposition films show pure monoclinic phase. The films have a band gap ˜6.0eV with a strong PL emission peak is at 490 nm and a weak peak is at 423 nm. So the films formed by this deposition method are suitable for luminescent applications

Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique

NASA Astrophysics Data System (ADS)

Qiang, Lei; Liang, Xiaoci; Cai, Guangshuo; Pei, Yanli; Yao, Ruohe; Wang, Gang

2018-06-01

Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: EC - EF > 3kT and EC - EF ≤ 3kT, where kT is the thermal energy, EF and EC represent the Fermi level and the conduction band edge, respectively. Additionally, in order to describe conduction mechanisms more accurately, the extended mobility edge model is conjoined, which can also get rid of the complicated and lengthy computations. The good agreement between measured and calculated results confirms the efficiency of this model for the design of integrated large-area thin film circuits.

Highly improved photo-induced bias stability of sandwiched triple layer structure in sol-gel processed fluorine-doped indium zinc oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Dongha; Park, Hyungjin; Bae, Byeong-Soo, E-mail: bsbae@kaist.ac.kr

In order to improve the reliability of TFT, an Al{sub 2}O{sub 3} insulating layer is inserted between active fluorine doped indium zinc oxide (IZO:F) thin films to form a sandwiched triple layer. All the thin films were fabricated via low-cost sol-gel process. Due to its large energy bandgap and high bonding energy with oxygen atoms, the Al{sub 2}O{sub 3} layer acts as a photo-induced positive charge blocking layer that effectively blocks the migration of both holes and V {sub o}{sup 2+} toward the interface between the gate insulator and the semiconductor. The inserted Al{sub 2}O{sub 3} triple layer exhibits amore » noticeably low turn on voltage shift of −0.7 V under NBIS as well as the good TFT performance with a mobility of 10.9 cm{sup 2}/V ⋅ s. We anticipate that this approach can be used to solve the stability issues such as NBIS, which is caused by inescapable oxygen vacancies.« less

Temporally and Spatially Resolved Plasma Spectroscopy in Pulsed Laser Deposition of Ultra-Thin Boron Nitride Films (Postprint)

DTIC Science & Technology

2015-04-24

AFRL-RX-WP-JA-2016-0196 TEMPORALLY AND SPATIALLY RESOLVED PLASMA SPECTROSCOPY IN PULSED LASER DEPOSITION OF ULTRA-THIN BORON NITRIDE...AND SPATIALLY RESOLVED PLASMA SPECTROSCOPY IN PULSED LASER DEPOSITION OF ULTRA-THIN BORON NITRIDE FILMS (POSTPRINT) 5a. CONTRACT NUMBER FA8650...distributions within a PVD plasma plume ablated from a boron nitride (BN) target by a KrF laser at different pressures of nitrogen gas were investigated

Post-growth process for flexible CdS/CdTe thin film solar cells with high specific power.

PubMed

Cho, Eunwoo; Kang, Yoonmook; Kim, Donghwan; Kim, Jihyun

2016-05-16

We demonstrated a flexible CdS/CdTe thin film solar cell with high specific power of approximately 254 W/kg. A flexible and ultra-light weight CdS/CdTe cell treated with pre-NP etch process exhibited high conversion efficiency of 13.56% in superstrate configuration. Morphological, structural and optical changes of CdS/CdTe thin films were characterized when pre-NP etch step was incorporated to the conventional post-deposition process. Improvement of photovoltaic parameters can be attributed to the removal of the oxide and the formation of Te-rich layer, which benefit the activation process. Pre-NP etched cell maintained their flexibility and performance under the repeated tensile strain of 0.13%. Our method can pave a way for manufacturing flexible CdS/CdTe thin film solar cells with high specific power for mobile and aerospace applications.

Highly flexible electronics from scalable vertical thin film transistors.

PubMed

Liu, Yuan; Zhou, Hailong; Cheng, Rui; Yu, Woojong; Huang, Yu; Duan, Xiangfeng

2014-03-12

Flexible thin-film transistors (TFTs) are of central importance for diverse electronic and particularly macroelectronic applications. The current TFTs using organic or inorganic thin film semiconductors are usually limited by either poor electrical performance or insufficient mechanical flexibility. Here, we report a new design of highly flexible vertical TFTs (VTFTs) with superior electrical performance and mechanical robustness. By using the graphene as a work-function tunable contact for amorphous indium gallium zinc oxide (IGZO) thin film, the vertical current flow across the graphene-IGZO junction can be effectively modulated by an external gate potential to enable VTFTs with a highest on-off ratio exceeding 10(5). The unique vertical transistor architecture can readily enable ultrashort channel devices with very high delivering current and exceptional mechanical flexibility. With large area graphene and IGZO thin film available, our strategy is intrinsically scalable for large scale integration of VTFT arrays and logic circuits, opening up a new pathway to highly flexible macroelectronics.

Fusion of Night Vision and Thermal Images

DTIC Science & Technology

2006-12-01

with the walls of the MCP channels. Thus, a thin metal oxide coating commonly known as an ion barrier film is added to the input side of the MCP to...with film ion barrier to filmless gated tubes. An important improvement for Gen 4 products is a greater target identification range and higher target...Metal Seals with S-25 Cathode Mircro-channel plate Ceramic/Metal Seals with GaAS Cathode Mircro-channel plate with ion barrier film Ceramic

Effect of Rapid Thermal Annealing on the Electrical Characteristics of ZnO Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Remashan, Kariyadan; Hwang, Dae-Kue; Park, Seong-Ju; Jang, Jae-Hyung

2008-04-01

Thin-film transistors (TFTs) with a bottom-gate configuration were fabricated with an RF magnetron sputtered undoped zinc oxide (ZnO) channel layer and plasma-enhanced chemical vapor deposition (PECVD) grown silicon nitride as a gate dielectric. Postfabrication rapid thermal annealing (RTA) and subsequent nitrous oxide (N2O) plasma treatment were employed to improve the performance of ZnO TFTs in terms of on-current and on/off current ratio. The RTA treatment increases the on-current of the TFT significantly, but it also increases its off-current. The off-current of 2×10-8 A and on/off current ratio of 3×103 obtained after the RTA treatment were improved to 10-10 A and 105, respectively, by the subsequent N2O plasma treatment. The better device performance can be attributed to the reduction of oxygen vacancies at the top region of the channel due to oxygen incorporation from the N2O plasma. X-ray photoelectron spectroscopy (XPS) analysis of the TFT samples showed that the RTA-treated ZnO surface has more oxygen vacancies than as-deposited samples, which results in the increased drain current. The XPS study also showed that the subsequent N2O plasma treatment reduces oxygen vacancies only at the surface of ZnO so that the better off-current and on/off current ratio can be obtained.

Detection of saliva-range glucose concentrations using organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elkington, D.; Belcher, W. J.; Dastoor, P. C.

We describe the development of a glucose sensor through direct incorporation of an enzyme (glucose oxidase) into the gate of an organic thin film transistor (OTFT). We show that glucose diffusion is the key determinant of the device response time and present a mechanism of glucose sensing in these devices that involves protonic doping of the transistor channel via enzymatic oxidation of glucose. The integrated OTFT sensor is sensitive across 4 decades of glucose concentration; a range that encompasses both the blood and salivary glucose concentration levels. As such, this work acts as a proof-of-concept for low-cost printed biosensors formore » salivary glucose.« less

Laser cutting of ultra-thin glasses based on a nonlinear laser interaction effect

NASA Astrophysics Data System (ADS)

Chen, Jian; Wu, Zhouling

2013-07-01

Glass panel substrates have been widely used in consumer electronics such as in flat panel TVs, laptops, and cell phones. With the advancement in the industry, the glass substrates are becoming thinner and stronger for reduced weight and volume, which brings great challenges for traditional mechanical processes in terms of cut quality, yield, and throughput. Laser glass cutting provides a non-contact process with minimum impact and superior quality compared to the mechanical counterparts. In this paper, we presented recent progresses in advanced laser processing of ultra-thin glass substrates, especially laser-cutting of ultra-thin glasses by a high power laser through a nonlinear interaction effect. Our results indicate that this technique has great potential of application for mass production of ultra-thin glass substrates.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Achieving Ohmic Contact for High-quality MoS2 Devices on Hexagonal Boron Nitride

NASA Astrophysics Data System (ADS)

Cui, Xu

MoS2, among many other transition metal dichalcogenides (TMDCs), holds great promise for future applications in nano-electronics, opto-electronics and mechanical devices due to its ultra-thin nature, flexibility, sizable band-gap, and unique spin-valley coupled physics. However, there are two main challenges that hinder careful study of this material. Firstly, it is hard to achieve Ohmic contacts to mono-layer MoS2, particularly at low temperatures (T) and low carrier densities. Secondly, materials' low quality and impurities introduced during the fabrication significantly limit the electron mobility of mono- and few-layer MoS2 to be substantially below theoretically predicted limits, which has hampered efforts to observe its novel quantum transport behaviours. Traditional low work function metals doesn't necessary provide good electron injection to thin MoS2 due to metal oxidation, Fermi level pinning, etc. To address the first challenge, we tried multiple contact schemes and found that mono-layer hexagonal boron nitride (h-BN) and cobalt (Co) provide robust Ohmic contact. The mono-layer spacer serves two advantageous purposes: it strongly interacts with the transition metal, reducing its work function by over 1 eV; and breaks the metal-TMDCs interaction to eliminate the interfacial states that cause Fermi level pinning. We measure a flat-band Schottky barrier of 16 meV, which makes thin tunnel barriers upon doping the channels, and thus achieve low-T contact resistance of 3 kohm.um at a carrier density of 5.3x10. 12/cm. 2. Similar to graphene, eliminating all potential sources of disorder and scattering is the key to achieving high performance in MoS2 devices. We developed a van der Waals heterostructure device platform where MoS2 layers are fully encapsulated within h-BN and electrically contacted in a multi-terminal geometry using gate-tunable graphene electrodes. The h-BN-encapsulation provides excellent protection from environmental factors, resulting in highly stable device performance, even at elevated temperatures. Both optical and electrical characterization confirms our high quality devices, including an ultra-clean interface, a record-high Hall mobility reaching 34,000 cm. 2/Vs, and first observation of Shubnikov–de Haas oscillations. The development of Ohmic contact and fabrication of high quality devices are critical to MoS2 application and studying its intrinsic properties. Therefore, the progress made in this work will facilitate efforts to study novel physical phenomena of MoS2 that were not accessible before.

Wireless thin film transistor based on micro magnetic induction coupling antenna.

PubMed

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-12-22

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the 'internet of things' (IoT).

Wireless thin film transistor based on micro magnetic induction coupling antenna

PubMed Central

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-01-01

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the ‘internet of things’ (IoT). PMID:26691929

Wireless thin film transistor based on micro magnetic induction coupling antenna

NASA Astrophysics Data System (ADS)

Jun, Byoung Ok; Lee, Gwang Jun; Kang, Jong Gu; Kim, Seunguk; Choi, Ji-Woong; Cha, Seung Nam; Sohn, Jung Inn; Jang, Jae Eun

2015-12-01

A wireless thin film transistor (TFT) structure in which a source/drain or a gate is connected directly to a micro antenna to receive or transmit signals or power can be an important building block, acting as an electrical switch, a rectifier or an amplifier, for various electronics as well as microelectronics, since it allows simple connection with other devices, unlike conventional wire connections. An amorphous indium gallium zinc oxide (α-IGZO) TFT with magnetic antenna structure was fabricated and studied for this purpose. To enhance the induction coupling efficiency while maintaining the same small antenna size, a magnetic core structure consisting of Ni and nanowires was formed under the antenna. With the micro-antenna connected to a source/drain or a gate of the TFT, working electrical signals were well controlled. The results demonstrated the device as an alternative solution to existing wire connections which cause a number of problems in various fields such as flexible/wearable devices, body implanted devices, micro/nano robots, and sensors for the ‘internet of things’ (IoT).

Fabrication and characterization of high mobility spin-coated zinc oxide thin film transistors

NASA Astrophysics Data System (ADS)

Singh, Shaivalini; Chakrabarti, P.

2012-10-01

A ZnO based thin film transistor (TFT) with bottom-gate configuration and SiO2 as insulating layer has been fabricated and characterized. The ZnO thin film was prepared by spin coating the sol-gel solution on the p-type Si wafers. The optical and structural properties of ZnO films were investigated using UV measurements and scanning electron microscope (SEM). The result of UV-visible study confirms that the films have a good absorbance in UV region and relatively low absorbance in the visible region. The TFT exhibited an off-current of 2.5×10-7 A. The values of field effect channel mobility and on/off current ratio extracted for the device, measured 11 cm2/V.s and ~102 respectively. The value of threshold voltage was found to be 1.3 V.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Fabrication and characterization of heterojunction transistors

NASA Astrophysics Data System (ADS)

Lo, Chien-Fong

2011-12-01

Submircon emitter finger high-speed double heterojunction InAlAs/InGaAsSb/InGaAs bipolar transistors (DHBTs) and a variety of nitride high electron mobility transistors (HEMTs) including AlGaN/GaN, InAlN/GaN, and AlN/GaN were fabricated and characterized. DHBT structures were grown by solid source molecular beam epitaxy (SSMBE) on Fe-doped semiinsulating InP substrates and nitride HEMTs were grown with a metal organic chemical vapor deposition (MOCVD) system on sapphire or SiC substrates. AlN/GaN HEMTs were grown with a RF-VMBE on sapphire substrates. Ultra low base contact resistance of 3.7 x 10-7 ohm-cm2 after 1 min 250¢XC thermal treatment on noval InGaAsSb base of DHBTs was achieved and a long-term thermal stability of base metallization was studied. Regarding small scale DHBT fabrication, tri-layer system was introduced to improve the resolution for submicron emitter patterning and help to pile up a thicker emitter metal stack; guard-ring technique was applied around the emitter periphery in order to preserve the current gain at small emitter dimensions. Ultra low turn-on voltage and high current gain can be realized with InGaAsSb-base DHBTs as compared to the conventional InGaAs-base DHBTs. A peak current gain cutoff frequency (fT) of 268 GHz and power gain cutoff frequency (fmax) of 485 GHz were achieved. GaN-based HEMTs herein were fabricated with gate lengths from 400 nm to 1im, and were deposited Ti/Al/Ni/Au as their Ohmic contact metallization. Effects of the Ohmic contact annealing for lattice-matched InAlN/GaN HEMTs with and without a thin GaN cap layer were exhibited and their optimal annealing temperature were obtained. A maximum drain current of 1.3 A/mm and an extrinsic transconductance of 366 mS/mm were demonstrated for InAlN/GaN HEMTs with the shortest gate length. A unity-gain cutoff frequency (fT) of 69 GHz and a maximum frequency of oscillation (fmax) of 80 GHz for InAlN/GaN HEMTs were extracted from measured scattering parameters. Passivation is one of the most important parts in device processing for preventing degradation from various environmental conditions and promising a better device performance. Simply, ozone treatment of AlN on AlN/GaN heterostructures produced effective aluminum oxide surface passivation and chemical resistance to the AZ positive photoresist developer used for subsequent device fabrication. Metal oxide semiconductor diode-like gate current-voltage characteristics and minimal drain current degradation during gate pulse measurements were observed. With an additional oxygen plasma treatment on the gate area prior to the gate metal deposition, enhancement-mode AlN/GaN HEMTs were realized. In addition, for AlGaN/GaN HEMTs in high electrical field applications, a high-dielectric-strength SiNx passivation over an optimum thickness was needed to suppress surface flashover during a high voltage or high power operation. An excellent isolation blocking voltage of 900 V with a leakage current at 1 muA/mm was obtained across a nitrogen-implanted isolation-gap of 10 mum between two Ohmic pads. The radiation hardness of HBTs and HEMTs is one of the critical factors that need to be established for military, space, and nuclear industry applications. The effects of proton radiation on the dc performance of InAlAs/InGaAsSb/InGaAs HBTs and AlN/GaN HEMTs were investigated. Both of these devices showed a remarkable resistance to high energy protoninduced degradation and appeared very promising for terrestrial or space-borne applications. The proton-irradiated devices with a dose of 2 x 1011 cm-2 (estimated to be equivalent to more than 40 years of exposure in low-earth orbit) showed only small changes in dc transfer characteristics, threshold voltage shift, and gate-lag with a high frequency pulse on the gate of the HEMTs and showed small changes in junction ideality factor, generation recombination leakage current, and output conductance for the HBTs. The effect the gate metallization on the nitride HEMT reliability was also examined. By replacing the conventional Ni/Au gate metallization with Pt/Ti/Au, the critical voltage for degradation of AlGaN/GaN HEMTs during off-state biasing stress was significantly improved from -55 V to over larger than -100 V. Besides the irradiation or high voltage stresses, the effects of ambient on the Pt-gated HEMT sensor for gas sensing application were also explored. For the hydrogen sensing, the sensitivity decreased proportional to the relative humidity but the presence of humidity dramatically improved the sensor recovery characteristics after exposure to the hydrogen ambient.

Optically transparent thin-film transistors based on 2D multilayer MoS₂ and indium zinc oxide electrodes.

PubMed

Kwon, Junyeon; Hong, Young Ki; Kwon, Hyuk-Jun; Park, Yu Jin; Yoo, Byungwook; Kim, Jiwan; Grigoropoulos, Costas P; Oh, Min Suk; Kim, Sunkook

2015-01-21

We report on optically transparent thin film transistors (TFTs) fabricated using multilayered molybdenum disulfide (MoS2) as the active channel, indium tin oxide (ITO) for the back-gated electrode and indium zinc oxide (IZO) for the source/drain electrodes, respectively, which showed more than 81% transmittance in the visible wavelength. In spite of a relatively large Schottky barrier between MoS2 and IZO, the n-type behavior with a field-effect mobility (μ(eff)) of 1.4 cm(2) V(-1) s(-1) was observed in as-fabricated transparent MoS2 TFT. In order to enhance the performances of transparent MoS2 TFTs, a picosecond pulsed laser was selectively irradiated onto the contact region of the IZO electrodes. Following laser annealing, μ(eff) increased to 4.5 cm(2) V(-1) s(-1), and the on-off current ratio (I(on)/I(off)) increased to 10(4), which were attributed to the reduction of the contact resistance between MoS2 and IZO.

All 2D, high mobility, flexible, transparent thin film transistor

DOEpatents

Das, Saptarshi; Sumant, Anirudha V.; Roelofs, Andreas

2017-01-17

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

Rutherford forward scattering and elastic recoil detection (RFSERD) as a method for characterizing ultra-thin films

DOE PAGES

Lohn, Andrew J.; Doyle, Barney L.; Stein, Gregory J.; ...

2014-04-03

We present a novel ion beam analysis technique combining Rutherford forward scattering and elastic recoil detection (RFSERD) and demonstrate its ability to increase efficiency in determining stoichiometry in ultrathin (5-50 nm) films as compared to Rutherford backscattering. In the conventional forward geometries, scattering from the substrate overwhelms the signal from light atoms but in RFSERD, scattered ions from the substrate are ranged out while forward scattered ions and recoiled atoms from the thin film are simultaneously detected in a single detector. Lastly, the technique is applied to tantalum oxide memristors but can be extended to a wide range of materialsmore » systems.« less

Away from silicon era: the paper electronics

NASA Astrophysics Data System (ADS)

Martins, R.; Brás, B.; Ferreira, I.; Pereira, L.; Barquinha, P.; Correia, N.; Costa, R.; Busani, T.; Gonçalves, A.; Pimentel, A.; Fortunato, E.

2011-02-01

Today there is a strong interest in the scientific and industrial community concerning the use of biopolymers for electronic applications, mainly driven by low-cost and disposable applications. Adding to this interest, we must recognize the importance of the wireless auto sustained and low energy consumption electronics dream. This dream can be fulfilled by cellulose paper, the lightest and the cheapest known substrate material, as well as the Earth's major biopolymer and of tremendous global economic importance. The recent developments of oxide thin film transistors and in particular the production of paper transistors at room temperature had contributed, as a first step, for the development of disposable, low cost and flexible electronic devices. To fulfil the wireless demand, it is necessary to prove the concept of self powered devices. In the case of paper electronics, this implies demonstrating the idea of self regenerated thin film paper batteries and its integration with other electronic components. Here we demonstrate this possibility by actuating the gate of paper transistors by paper batteries. We found that when a sheet of cellulose paper is covered in both faces with thin layers of opposite electrochemical potential materials, a voltage appears between both electrodes -paper battery, which is also self-regenerated. The value of the potential depends upon the materials used for anode and cathode. An open circuit voltage of 0.5V and a short-circuit current density of 1μA/cm2 were obtained in the simplest structure produced (Cu/paper/Al). For actuating the gate of the paper transistor, seven paper batteries were integrated in the same substrate in series, supplying a voltage of 3.4V. This allows proper ON/OFF control of the paper transistor. Apart from that transparent conductive oxides can be also used as cathode/anode materials allowing so the production of thin film batteries with transparent electrodes compatible with flexible, invisible, self powered and wireless electronics.

Tunneling contact IGZO TFTs with reduced saturation voltages

NASA Astrophysics Data System (ADS)

Wang, Longyan; Sun, Yin; Zhang, Xintong; Zhang, Lining; Zhang, Shengdong; Chan, Mansun

2017-04-01

We report a tunneling contact indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with a graphene interlayer technique in this paper. A Schottky junction is realized between a metal and IGZO with a graphene interlayer, leading to a quantum tunneling of the TFT transport in saturation regions. This tunneling contact enables a significant reduction in the saturation drain voltage Vdsat compared to that of the thermionic emission TFTs, which is usually equal to the gate voltage minus their threshold voltages. Measured temperature independences of the subthreshold swing confirm a transition from the thermionic emission to quantum tunneling transports depending on the gate bias voltages in the proposed device. The tunneling contact TFTs with the graphene interlayer have implications to reduce the power consumptions of certain applications such as the active matrix OLED display.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Hyun-Sik; Jeon, Sanghun, E-mail: jeonsh@korea.ac.kr

Upon light exposure, an indium-zinc-oxide (IZO) thin-film transistor (TFT) presents higher photoconductivity by several orders of magnitude at the negative gate bias region. Among various device geometrical factors, scaling down the channel length of the photo-transistor results in an anomalous increase in photoconductivity. To probe the origin of this high photoconductivity in short-channel device, we measured transient current, current–voltage, and capacitance–voltage characteristics of IZO–TFTs with various channel lengths and widths before and after illumination. Under the illumination, the equilibrium potential region which lies far from front interface exists only in short-channel devices, forming the un-depleted conducting back channel. This regionmore » plays an important role in carrier transport under the illumination, leading to high photoconductivity in short-channel devices. Photon exposure coupled with gate-modulated band bending for short-channel devices leads to the accumulation of V{sub o}{sup ++} at the front channel and screening negative gate bias, thereby generating high current flow in the un-depleted back-channel region.« less

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk; Mazzocco, R.

2015-05-18

We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currentsmore » (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.« less

Pinch-off dynamics, extensional viscosity and relaxation time of dilute and ultradilute aqueous polymer solutions

NASA Astrophysics Data System (ADS)

Biagioli, Madeleine; Dinic, Jelena; Jimenez, Leidy Nallely; Sharma, Vivek

Free surface flows and drop formation processes present in printing, jetting, spraying, and coating involve the development of columnar necks that undergo spontaneous surface-tension driven instability, thinning, and pinch-off. Stream-wise velocity gradients that arise within the thinning neck create and extensional flow field, which induces micro-structural changes within complex fluids that contribute elastic stresses, changing the thinning and pinch-off dynamics. In this contribution, we use dripping-onto-substrate (DoS) extensional rheometry technique for visualization and analysis of the pinch-off dynamics of dilute and ultra-dilute aqueous polyethylene oxide (PEO) solutions. Using a range of molecular weights, we study the effect of both elasticity and finite extensibility. Both effective relaxation time and the transient extensional viscosity are found to be strongly concentration-dependent even for highly dilute solutions.

Method of forming ultra thin film devices by vacuum arc vapor deposition

NASA Technical Reports Server (NTRS)

Schramm, Harry F. (Inventor)

2005-01-01

A method for providing an ultra thin electrical circuit integral with a portion of a surface of an object, including using a focal Vacuum Arc Vapor Deposition device having a chamber, a nozzle and a nozzle seal, depressing the nozzle seal against the portion of the object surface to create an airtight compartment in the chamber and depositing one or more ultra thin film layer(s) only on the portion of the surface of the object, the layers being of distinct patterns such that they form the circuit.

Method for laser welding ultra-thin metal foils

DOEpatents

Pernicka, J.C.; Benson, D.K.; Tracy, C.E.

1996-03-26

A method for simultaneously cutting and welding ultra-thin foils having a thickness of less than 0.002 inches wherein two ultra-thin films are stacked and clamped together. A pulsed laser such as of the Neodymium: YAG type is provided and the beam of the laser is directed onto the stacked films to cut a channel through the films. The laser is moved relative to the stacked foils to cut the stacked foils at successive locations and to form a plurality of connected weld beads to form a continuous weld. 5 figs.

Method for laser welding ultra-thin metal foils

DOEpatents

Pernicka, John C.; Benson, David K.; Tracy, C. Edwin

1996-01-01

A method for simultaneously cutting and welding ultra-thin foils having a thickness of less than 0.002 inches wherein two ultra-thin films are stacked and clamped together. A pulsed laser such as of the Neodymium: YAG type is provided and the beam of the laser is directed onto the stacked films to cut a channel through the films. The laser is moved relative to the stacked foils to cut the stacked foils at successive locations and to form a plurality of connected weld beads to form a continuous weld.

Template-free synthesis of vanadium oxides nanobelt arrays as high-rate cathode materials for lithium ion batteries

NASA Astrophysics Data System (ADS)

Qin, Mulan; Liang, Qiang; Pan, Anqiang; Liang, Shuquan; Zhang, Qing; Tang, Yan; Tan, Xiaoping

2014-12-01

A facile hydrothermal route has been developed to fabricate the metastable VO2 (B) ultra-thin nanobelt arrays, which can be converted into V2O5 porous nanobelt arrays after calcinating VO2 (B) in air at 400 °C for 1 h. The influence of hydrothermal time to the crystallinity and morphology of the VO2 phase has been studied. A possible mechanism for the formation of VO2 nanobelt arrays has been proposed in this paper. As a cathode material for lithium ion batteries, the V2O5 nanobelt arrays show excellent rate capability and cycling stability. An initial discharge capacity of 142 mA h g-1 can be delivered at a current density of 50 mA g-1 with almost no capacity fading after 100 cycles. Even at a current density of 1000 mA g-1, they still exhibit the capacity of 130 mA h g-1 and superior capacity retention capability. The excellent electrochemical properties are attributed to the ultra-thin thickness and the porous structures of the nanobelts.

In-situ observation of equilibrium transitions in Ni films; agglomeration and impurity effects.

PubMed

Thron, Andrew M; Greene, Peter; Liu, Kai; van Benthem, Klaus

2014-02-01

Dewetting of ultra-thin Ni films deposited on SiO2 layers was observed, in cross-section, by in situ scanning transmission electron microscopy. Holes were observed to nucleate by voids which formed at the Ni/SiO2 interface rather than at triple junctions at the free surface of the Ni film. Ni islands were observed to retract, in attempt to reach equilibrium on the SiO2 layer. SiO2 layers with 120 nm thickness were found to limit in situ heating experiments due to poor thermal conductivity of SiO2. The formation of graphite was observed during the agglomeration of ultra-thin Ni films. Graphite was observed to wet both the free surface and the Ni/SiO2 interface of the Ni islands. Cr forms surface oxide layers on the free surface of the SiO2 layer and the Ni islands. Cr does not prevent the dewetting of Ni, however it will likely alter the equilibrium shape of the Ni islands. © 2013 Published by Elsevier B.V.

Optimized ultra-thin manganin alloy passivated fine-pitch damascene compatible bump-less Cu-Cu bonding at sub 200 °C for three-dimensional Integration applications

NASA Astrophysics Data System (ADS)

Panigrahi, Asisa Kumar; Hemanth Kumar, C.; Bonam, Satish; Ghosh, Tamal; Rama Krishna Vanjari, Siva; Govind Singh, Shiv

2018-02-01

Enhanced Cu diffusion, Cu surface passivation, and smooth surface at the bonding interface are the key essentials for high quality Cu-Cu bonding. Previously, we have demonstrated optimized 3 nm thin Manganin metal-alloy passivation from oxidation and also helps to reduce the surface roughness to about 0.8 nm which substantially led to high quality Cu-Cu bonding. In this paper, we demonstrated an ultra fine-pitch (<25 µm) Cu-Cu bonding using an optimized Manganin metal-alloy passivation. This engineered surface passivation approach led to high quality bonding at sub 200 °C temperature and 0.4 MPa. Very low specific contact resistance of 1.4 × 10-7 Ω cm2 and the defect free bonded interface is clear indication of high quality bonding for future multilayer integrations. Furthermore, electrical characterization of the bonded structure was performed under various robust conditions as per International Technology Roadmap for Semiconductors (ITRS Roadmap) in order to satisfy the stability of the bonded structure.

Ultra-thin plasma panel radiation detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedman, Peter S.

An ultra-thin radiation detector includes a radiation detector gas chamber having at least one ultra-thin chamber window and an ultra-thin first substrate contained within the gas chamber. The detector further includes a second substrate generally parallel to and coupled to the first substrate and defining a gas gap between the first substrate and the second substrate. The detector further includes a discharge gas between the substrates and contained within the gas chamber, where the discharge gas is free to circulate within the gas chamber and between the first and second substrates at a given gas pressure. The detector further includesmore » a first electrode coupled to one of the substrates and a second electrode electrically coupled to the first electrode. The detector further includes a first discharge event detector coupled to at least one of the electrodes for detecting a gas discharge counting event in the electrode.« less

Large electron concentration modulation using capacitance enhancement in SrTiO{sub 3}/SmTiO{sub 3} Fin-field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Verma, Amit, E-mail: averma@cornell.edu; Nomoto, Kazuki; School of Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853

2016-05-02

Solid-state modulation of 2-dimensional electron gases (2DEGs) with extreme (∼3.3 × 10{sup 14 }cm{sup −2}) densities corresponding to 1/2 electron per interface unit cell at complex oxide heterointerfaces (such as SrTiO{sub 3}/GdTiO{sub 3} or SrTiO{sub 3}/SmTiO{sub 3}) is challenging because it requires enormous gate capacitances. One way to achieve large gate capacitances is by geometrical capacitance enhancement in fin structures. In this work, we fabricate both Au-gated planar field effect transistors (FETs) and Fin-FETs with varying fin-widths on 60 nm SrTiO{sub 3}/5 nm SmTiO{sub 3} thin films grown by hybrid molecular beam epitaxy. We find that the FinFETs exhibit higher gate capacitance comparedmore » to planar FETs. By scaling down the SrTiO{sub 3}/SmTiO{sub 3} fin widths, we demonstrate further gate capacitance enhancement, almost twice compared to the planar FETs. In the FinFETs with narrowest fin-widths, we demonstrate a record 2DEG electron concentration modulation of ∼2.4 × 10{sup 14 }cm{sup −2}.« less

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells

PubMed Central

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-01

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping. PMID:28336851

Effect of processing parameters on microstructure of MoS{sub 2} ultra-thin films synthesized by chemical vapor deposition method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Yang; You, Suping; Sun, Kewei

2015-06-15

MoS{sub 2} ultra-thin layers are synthesized using a chemical vapor deposition method based on the sulfurization of molybdenum trioxide (MoO{sub 3}). The ultra-thin layers are characterized by X-ray diffraction (XRD), photoluminescence (PL) spectroscopy and atomic force microscope (AFM). Based on our experimental results, all the processing parameters, such as the tilt angle of substrate, applied voltage, heating time and the weight of source materials have effect on the microstructures of the layers. In this paper, the effects of such processing parameters on the crystal structures and morphologies of the as-grown layers are studied. It is found that the film obtainedmore » with the tilt angle of 0.06° is more uniform. A larger applied voltage is preferred to the growth of MoS{sub 2} thin films at a certain heating time. In order to obtain the ultra-thin layers of MoS{sub 2}, the weight of 0.003 g of source materials is preferred. Under our optimal experimental conditions, the surface of the film is smooth and composed of many uniformly distributed and aggregated particles, and the ultra-thin MoS{sub 2} atomic layers (1∼10 layers) covers an area of more than 2 mm×2 mm.« less

Nano-photonic structures for light trapping in ultra-thin crystalline silicon solar cells

DOE PAGES

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-13

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a densemore » mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. Furthermore, this architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.« less

Nano-photonic structures for light trapping in ultra-thin crystalline silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pathi, Prathap; Peer, Akshit; Biswas, Rana

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a densemore » mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. Furthermore, this architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.« less

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells.

PubMed

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-13

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%-2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm² photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.

Time-gated flow cytometry: an ultra-high selectivity method to recover ultra-rare-event μ-targets in high-background biosamples

NASA Astrophysics Data System (ADS)

Jin, Dayong; Piper, James A.; Leif, Robert C.; Yang, Sean; Ferrari, Belinda C.; Yuan, Jingli; Wang, Guilan; Vallarino, Lidia M.; Williams, John W.

2009-03-01

A fundamental problem for rare-event cell analysis is auto-fluorescence from nontarget particles and cells. Time-gated flow cytometry is based on the temporal-domain discrimination of long-lifetime (>1 μs) luminescence-stained cells and can render invisible all nontarget cell and particles. We aim to further evaluate the technique, focusing on detection of ultra-rare-event 5-μm calibration beads in environmental water dirt samples. Europium-labeled 5-μm calibration beads with improved luminescence homogeneity and reduced aggregation were evaluated using the prototype UV LED excited time-gated luminescence (TGL) flow cytometer (FCM). A BD FACSAria flow cytometer was used to sort accurately a very low number of beads (<100 events), which were then spiked into concentrated samples of environmental water. The use of europium-labeled beads permitted the demonstration of specific detection rates of 100%+/-30% and 91%+/-3% with 10 and 100 target beads, respectively, that were mixed with over one million nontarget autofluorescent background particles. Under the same conditions, a conventional FCM was unable to recover rare-event fluorescein isothiocyanate (FITC) calibration beads. Preliminary results on Giardia detection are also reported. We have demonstrated the scientific value of lanthanide-complex biolabels in flow cytometry. This approach may augment the current method that uses multifluorescence-channel flow cytometry gating.

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Pandey, R. K.; Sathiyanarayanan, Rajesh; Kwon, Unoh; Narayanan, Vijay; Murali, K. V. R. M.

2013-07-01

We investigate the physical properties of a portion of the gate stack of an ultra-scaled complementary metal-oxide-semiconductor (CMOS) device. The effects of point defects, such as oxygen vacancy, oxygen, and aluminum interstitials at the HfO2/TiN interface, on the effective work function of TiN are explored using density functional theory. We compute the diffusion barriers of such point defects in the bulk TiN and across the HfO2/TiN interface. Diffusion of these point defects across the HfO2/TiN interface occurs during the device integration process. This results in variation of the effective work function and hence in the threshold voltage variation in the devices. Further, we simulate the effects of varying the HfO2/TiN interface stoichiometry on the effective work function modulation in these extremely-scaled CMOS devices. Our results show that the interface rich in nitrogen gives higher effective work function, whereas the interface rich in titanium gives lower effective work function, compared to a stoichiometric HfO2/TiN interface. This theoretical prediction is confirmed by the experiment, demonstrating over 700 meV modulation in the effective work function.

Selective UV–O3 treatment for indium zinc oxide thin film transistors with solution-based multiple active layer

NASA Astrophysics Data System (ADS)

Kim, Yu-Jung; Jeong, Jun-Kyo; Park, Jung-Hyun; Jeong, Byung-Jun; Lee, Hi-Deok; Lee, Ga-Won

2018-06-01

In this study, a method to control the electrical performance of solution-based indium zinc oxide (IZO) thin film transistors (TFTs) is proposed by ultraviolet–ozone (UV–O3) treatment on the selective layer during multiple IZO active layer depositions. The IZO film is composed of triple layers formed by spin coating and UV–O3 treatment only on the first layer or last layer. The IZO films are compared by X-ray photoelectron spectroscopy, and the results show that the atomic ratio of oxygen vacancy (VO) increases in the UV–O3 treatment on the first layer, while it decreases on last layer. The device characteristics of the bottom gated structure are also improved in the UV–O3 treatment on the first layer. This indicates that the selective UV–O3 treatment in a multi-stacking active layer is an effective method to optimize TFT properties by controlling the amount of VO in the IZO interface and surface independently.

Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Faber, Hendrik; Anthopoulos, Thomas D., E-mail: t.anthopoulos@imperial.ac.uk

2015-03-02

Indium oxide (In{sub 2}O{sub 3}) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm{sup 2}V{sup −1}s{sup −1} and 16 cm{sup 2}V{sup −1}s{sup −1} for coplanar and staggered architectures, respectively. Integration of In{sub 2}O{sub 3} transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (≤250 °C) of In{sub 2}O{sub 3} also allowed transistor fabrication on free-standing 50 μm-thick polyimide foils. The resulting flexible In{sub 2}O{sub 3} transistors exhibit good characteristics and remain fully functional even whenmore » bent to tensile radii of 4 mm.« less

Crystallization behavior of amorphous indium-gallium-zinc-oxide films and its effects on thin-film transistor performance

NASA Astrophysics Data System (ADS)

Suko, Ayaka; Jia, JunJun; Nakamura, Shin-ichi; Kawashima, Emi; Utsuno, Futoshi; Yano, Koki; Shigesato, Yuzo

2016-03-01

Amorphous indium-gallium-zinc oxide (a-IGZO) films were deposited by DC magnetron sputtering and post-annealed in air at 300-1000 °C for 1 h to investigate the crystallization behavior in detail. X-ray diffraction, electron beam diffraction, and high-resolution electron microscopy revealed that the IGZO films showed an amorphous structure after post-annealing at 300 °C. At 600 °C, the films started to crystallize from the surface with c-axis preferred orientation. At 700-1000 °C, the films totally crystallized into polycrystalline structures, wherein the grains showed c-axis preferred orientation close to the surface and random orientation inside the films. The current-gate voltage (Id-Vg) characteristics of the IGZO thin-film transistor (TFT) showed that the threshold voltage (Vth) and subthreshold swing decreased markedly after the post-annealing at 300 °C. The TFT using the totally crystallized films also showed the decrease in Vth, whereas the field-effect mobility decreased considerably.

P-channel thin film transistors using reduced graphene oxide

NASA Astrophysics Data System (ADS)

Chakraborty, S.; Resmi, A. N.; Renuka Devi, P.; Jinesh, K. B.

2017-04-01

Chemically reduced graphene oxide (rGO) samples with various degrees of reduction were prepared using hydrazine hydrate as the reducing agent. Scanning tunnelling microscope imaging shows that rGO contains rows of randomly distributed patches of epoxy groups. The local density of states of the rGO samples were mapped with scanning tunnelling spectroscopy, which shows that the bandgap in rGO originates from the epoxide regions itself. The Fermi level of the epoxide regions is shifted towards the valence band, making rGO locally p-type and a range of bandgaps from 0-2.2 eV was observed in these regions. Thin film transistors were fabricated using rGO as the channel layer. The devices show excellent output characteristics with clear saturation and gate dependence. The transfer characteristics show that rGO behaves as a p-type semiconductor; the devices exhibit an on/off ratio of 104, with a low-bias hole mobility of 3.9 cm2 V-1 s-1.

Intrinsic hydrophilic nature of epitaxial thin-film of rare-earth oxide grown by pulsed laser deposition.

PubMed

Prakash, Saurav; Ghosh, Siddhartha; Patra, Abhijeet; Annamalai, Meenakshi; Motapothula, Mallikarjuna Rao; Sarkar, Soumya; Tan, Sherman J R; Zhunan, Jia; Loh, Kian Ping; Venkatesan, T

2018-02-15

Herein, we report a systematic study of water contact angle (WCA) of rare-earth oxide thin-films. These ultra-smooth and epitaxial thin-films were grown using pulsed laser deposition and then characterized using X-Ray diffraction (XRD), Rutherford backscattering spectroscopy (RBS), and atomic force microscopy (AFM). Through both the traditional sessile drop and the novel f-d method, we found that the films were intrinsically hydrophilic (WCA < 10°) just after being removed from the growth chamber, but their WCAs evolved with an exposure to the atmosphere with time to reach their eventual saturation values near 90° (but always stay 'technically' hydrophilic). X-Ray photoelectron spectroscopy analysis was used to further investigate qualitatively the nature of hydrocarbon contamination on the freshly prepared as well as the environmentally exposed REO thin-film samples as a function of the exposure time after they were removed from the deposition chamber. A clear correlation between the carbon coverage of the surface and the increase in WCA was observed for all of the rare-earth films, indicating the extrinsic nature of the surface wetting properties of these films and having no relation to the electronic configuration of the rare-earth atoms as proposed by Azimi et al.

Electrical properties of thin film transistors with zinc tin oxide channel layer

NASA Astrophysics Data System (ADS)

Hong, Seunghwan; Oh, Gyujin; Kim, Eun Kyu

2017-10-01

We have investigated thin film transistors (TFTs) with zinc tin oxide (ZTO) channel layer fabricated by using an ultra-high vacuum radio frequency sputter. ZTO thin films were grown at room temperature by co-sputtering of ZnO and SnO2, which applied power for SnO2 target was varied from 15 W to 90 W under a fixed sputtering power of 70 W for ZnO target. A post-annealing treatment to improve the film quality was done at temperature ranges from 300 to 600 °C by using the electrical furnace. The ZTO thin films showed good electrical and optical properties such as Hall mobility of more than 9 cm2/V·s, specific resistivity of about 2 × 102 Ω·cm, and optical transmittance of 85% in visible light region by optical bandgap of 3.3 eV. The ZTO-TFT with an excellent performance of channel mobility of 19.1 cm2/V·s and on-off ratio ( I on / I off ) of 104 was obtained from the films grown with SnO2 target power of 25 W and post-annealed at 450 °C. This result showed that ZTO film is promising on application to a high performance transparent TFTs.

Structural and electrical properties of single crystalline SrZrO 3 epitaxially grown on Ge (001)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lim, Z. H.; Ahmadi-Majlan, K.; Grimley, E. D.

We present structural and electrical characterization of SrZrO3 that has been epitaxially grown on Ge(001) by oxide molecular beam epitaxy. Single crystalline SrZrO3 can be nucleated on Ge via deposition at low temperatures followed by annealing at 550 ºC in ultra-high vacuum. Photoemission spectroscopy measurements reveal that SrZrO3 exhibits a type-I band arrangement with respect to Ge, with conduction and valence band offsets of 1.4 eV and 3.65 eV, respectively. As a standalone film, SrZrO3 exhibits several characteristics that are ideal for applications as a gate dielectric on Ge. We find that 4 nm thick films exhibit low leakage currentmore » densities, and a dielectric constant of κ ~ 25 that corresponds to an equivalent oxide thickness of 0.70 nm.« less

Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

PubMed Central

Rolin, Cedric; Kang, Enpu; Lee, Jeong-Hwan; Borghs, Gustaaf; Heremans, Paul; Genoe, Jan

2017-01-01

Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects. PMID:28397852

Effect of Gallium Doping on the Characteristic Properties of Polycrystalline Cadmium Telluride Thin Film

NASA Astrophysics Data System (ADS)

Ojo, A. A.; Dharmadasa, I. M.

2017-08-01

Ga-doped CdTe polycrystalline thin films were successfully electrodeposited on glass/fluorine doped tin oxide substrates from aqueous electrolytes containing cadmium nitrate (Cd(NO3)2·4H2O) and tellurium oxide (TeO2). The effects of different Ga-doping concentrations on the CdTe:Ga coupled with different post-growth treatments were studied by analysing the structural, optical, morphological and electronic properties of the deposited layers using x-ray diffraction (XRD), ultraviolet-visible spectrophotometry, scanning electron microscopy, photoelectrochemical cell measurement and direct-current conductivity test respectively. XRD results show diminishing (111)C CdTe peak above 20 ppm Ga-doping and the appearance of (301)M GaTe diffraction above 50 ppm Ga-doping indicating the formation of two phases; CdTe and GaTe. Although, reductions in the absorption edge slopes were observed above 20 ppm Ga-doping for the as-deposited CdTe:Ga layer, no obvious influence on the energy gap of CdTe films with Ga-doping were detected. Morphologically, reductions in grain size were observed at 50 ppm Ga-doping and above with high pinhole density within the layer. For the as-deposited CdTe:Ga layers, conduction type change from n- to p- were observed at 50 ppm, while the n-type conductivity were retained after post-growth treatment. Highest conductivity was observed at 20 ppm Ga-doping of CdTe. These results are systematically reported in this paper.

Disordering of ultra thin WO3 films by high-energy ions

NASA Astrophysics Data System (ADS)

Matsunami, N.; Kato, M.; Sataka, M.; Okayasu, S.

2017-10-01

We have studied disordering or atomic structure modification of ultra thin WO3 films under impact of high-energy ions with non-equilibrium and equilibrium charge incidence, by means of X-ray diffraction (XRD). WO3 films were prepared by thermal oxidation of W deposited on MgO substrate. Film thickness obtained by Rutherford backscattering spectrometry (RBS) is as low as 2 nm. Smoothness of film surface was observed by atomic force microscopy. It is found that the ratio of XRD intensity degradation per 90 MeV Ni+10 ion (the incident charge is lower than the equilibrium charge) to that per 90 MeV Ni ion with the equilibrium charge depends on the film thickness. Also, film thickness dependence is observed for 100 MeV Xe+14. By comparison of the experimental result with a simple model calculation based on the assumption that the mean charge of ions along the depth follows a saturation curve with power-law approximation to the charge dependent electronic stopping power, the characteristic length attaining the equilibrium charge is obtained to be ∼7 nm for 90 MeV Ni+10 ion incidence or the electron loss cross section of ∼1016 cm2, demonstrating that disordering of ultra WO3 films has been observed and a fundamental quantity can be derived through material modification.

Organic Field Effect Transistor Using Amorphous Fluoropolymer as Gate Insulating Film

NASA Astrophysics Data System (ADS)

Kitajima, Yosuke; Kojima, Kenzo; Mizutani, Teruyoshi; Ochiai, Shizuyasu

Organic field effect transistors are fabricated by the active layer of Regioregular poly (3-hexylthiophene-2,5-diy)(P3HT) thin film. CYTOP thin film made from Amorphous Fluoropolymer and fabricated by spin-coating is adopted to a gate dielectric layer on Polyethylenenaphthalate (PEN) thin film that is the substrate of an organic field effect transistor. The surface morphology and molecular orientation of P3HT thin films is observed by atomic force microscope (AFM) and X-Ray diffractometer (XRD). Grains are observed on the CYTOP thin film via an AFM image and the P3HT molecule is oriented perpendicularly on the CYTOP thin film. Based on the performance of the organic field effect transistor, the carrier mobility is 0.092 cm2/Vs, the ON/OFF ratio is 7, and the threshold voltage is -12 V. The ON/OFF ratio is relatively low and to improve On/Off ratio, the CYTOP/Polyimide double gate insulating layer is adopted to OFET.

A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Saremi, Mehdi

2018-02-01

In this paper, the influence of ultra-scaled physical symmetrical contraction on electrical characteristics of ultra-thin silicon-on-insulator nanowires with circular gate-all-around structure is investigated by using a 3D Atlas numerical quantum simulator based on non-equilibrium green's function formalism. It is demonstrated that local cross-section variation in a nanowire transistor results in the establishment of tunnel energy barriers at the source-channel and drain-channel junctions which change device physics and cause a transmission from a quantum wire (1-D) to a floating quantum dot nanowire (0-D) introducing a resonant tunneling nanowire FET (RT-NWFET) as an interesting concept of nanoscale MOSFETs. The barriers construct resonance energy levels in the channel region of nanowires because of the longitudinal confinement in three directions causing some fluctuation in I D- V GS characteristic. In addition, these barriers remarkably improve the subthreshold swing and minimize the ON/OFF-current ratio degradation at a low operation voltage of 0.5 V. As a result, RT-NWFETs are intrinsically preserved from drain-source tunneling and are an interesting candidate for developing the roadmap below 10 nm.

Structural performance of ultra-thin whitetopping on Illinois roadways and parking lots.

DOT National Transportation Integrated Search

2014-08-01

A performance evaluation of ultra-thin whitetopping (UTW) pavements in Illinois was undertaken in 20122014 : to evaluate current design procedures and to determine design life criteria for future projects. The two main : components of this evaluat...

Surface Passivation in Empirical Tight Binding

NASA Astrophysics Data System (ADS)

He, Yu; Tan, Yaohua; Jiang, Zhengping; Povolotskyi, Michael; Klimeck, Gerhard; Kubis, Tillmann

2016-03-01

Empirical Tight Binding (TB) methods are widely used in atomistic device simulations. Existing TB methods to passivate dangling bonds fall into two categories: 1) Method that explicitly includes passivation atoms is limited to passivation with atoms and small molecules only. 2) Method that implicitly incorporates passivation does not distinguish passivation atom types. This work introduces an implicit passivation method that is applicable to any passivation scenario with appropriate parameters. This method is applied to a Si quantum well and a Si ultra-thin body transistor oxidized with SiO2 in several oxidation configurations. Comparison with ab-initio results and experiments verifies the presented method. Oxidation configurations that severely hamper the transistor performance are identified. It is also shown that the commonly used implicit H atom passivation overestimates the transistor performance.

A sextuple-band ultra-thin metamaterial absorber with perfect absorption

NASA Astrophysics Data System (ADS)

Yu, Dingwang; Liu, Peiguo; Dong, Yanfei; Zhou, Dongming; Zhou, Qihui

2017-08-01

This paper presents the design, simulation and measurement of a sextuple-band ultra-thin metamaterial absorber (MA). The unit cell of this proposed structure is composed of triangular spiral-shaped complementary structures imprinted on the dielectric substrate backed by a metal ground. The measured results are in good agreement with simulations with high absorptivities of more than 90% at all six absorption frequencies. In addition, this proposed absorber has good performances of ultra-thin, polarization insensitivity and a wide-angle oblique incidence, which can easily be used in many potential applications such as detection, imaging and sensing.

Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact

PubMed Central

Lin, Yu-Ru; Tsai, Wan-Ting; Wu, Yung-Chun; Lin, Yu-Hsien

2017-01-01

This study demonstrated an ultra thin poly-Si junctionless nanosheet field-effect transistor (JL NS-FET) with nickel silicide contact. For the nickel silicide film, two-step annealing and a Ti capping layer were adopted to form an ultra thin uniform nickel silicide film with low sheet resistance (Rs). The JL NS-FET with nickel silicide contact exhibited favorable electrical properties, including a high driving current (>107A), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this study compared the electrical characteristics of JL NS-FETs with and without nickel silicide contact. PMID:29112139

Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact.

PubMed

Lin, Yu-Ru; Tsai, Wan-Ting; Wu, Yung-Chun; Lin, Yu-Hsien

2017-11-07

This study demonstrated an ultra thin poly-Si junctionless nanosheet field-effect transistor (JL NS-FET) with nickel silicide contact. For the nickel silicide film, two-step annealing and a Ti capping layer were adopted to form an ultra thin uniform nickel silicide film with low sheet resistance (Rs). The JL NS-FET with nickel silicide contact exhibited favorable electrical properties, including a high driving current (>10⁷A), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this study compared the electrical characteristics of JL NS-FETs with and without nickel silicide contact.

Electron transport in ultra-thin films and ballistic electron emission microscopy

NASA Astrophysics Data System (ADS)

Claveau, Y.; Di Matteo, S.; de Andres, P. L.; Flores, F.

2017-03-01

We have developed a calculation scheme for the elastic electron current in ultra-thin epitaxial heterostructures. Our model uses a Keldysh’s non-equilibrium Green’s function formalism and a layer-by-layer construction of the epitaxial film. Such an approach is appropriate to describe the current in a ballistic electron emission microscope (BEEM) where the metal base layer is ultra-thin and generalizes a previous one based on a decimation technique appropriated for thick slabs. This formalism allows a full quantum mechanical description of the transmission across the epitaxial heterostructure interface, including multiple scattering via the Dyson equation, which is deemed a crucial ingredient to describe interfaces of ultra-thin layers properly in the future. We introduce a theoretical formulation needed for ultra-thin layers and we compare with results obtained for thick Au(1 1 1) metal layers. An interesting effect takes place for a width of about ten layers: a BEEM current can propagate via the center of the reciprocal space (\\overlineΓ ) along the Au(1 1 1) direction. We associate this current to a coherent interference finite-width effect that cannot be found using a decimation technique. Finally, we have tested the validity of the handy semiclassical formalism to describe the BEEM current.

Layered ultra-thin coherent structures used as electrical resistors having low-temperature coefficient of resistivity

DOEpatents

Werner, T.R.; Falco, C.M.; Schuller, I.K.

1982-08-31

A thin film resistor having a controlled temperature coefficient of resistance (TCR) ranging from negative to positive degrees kelvin and having relatively high resistivity. The resistor is a multilayer superlattice crystal containing a plurality of alternating, ultra-thin layers of two different metals. TCR is varied by controlling the thickness of the individual layers. The resistor can be readily prepared by methods compatible with thin film circuitry manufacturing techniques.

High-frequency electromechanical resonators based on thin GaTe

NASA Astrophysics Data System (ADS)

Chitara, Basant; Ya'akobovitz, Assaf

2017-10-01

Gallium telluride (GaTe) is a layered material, which exhibits a direct bandgap (˜1.65 eV) regardless of its thickness and therefore holds great potential for integration as a core element in stretchable optomechanical and optoelectronic devices. Here, we characterize and demonstrate the elastic properties and electromechanical resonators of suspended thin GaTe nanodrums. We used atomic force microscopy to extract the Young’s modulus of GaTe (average value ˜39 GPa) and to predict the resonance frequencies of suspended GaTe nanodrums of various geometries. Electromechanical resonators fabricated from suspended GaTe revealed fundamental resonance frequencies in the range of 10-25 MHz, which closely match predicted values. Therefore, this study paves the way for creating a new generation of GaTe based nanoelectromechanical devices with a direct bandgap vibrating element, which can serve as optomechanical sensors and actuators.

The significance of ultra-refracted surface gravity waves on sheltered coasts, with application to San Francisco Bay

USGS Publications Warehouse

Hanes, D.M.; Erikson, L.H.

2013-01-01

Ocean surface gravity waves propagating over shallow bathymetry undergo spatial modification of propagation direction and energy density, commonly due to refraction and shoaling. If the bathymetric variations are significant the waves can undergo changes in their direction of propagation (relative to deepwater) greater than 90° over relatively short spatial scales. We refer to this phenomenon as ultra-refraction. Ultra-refracted swell waves can have a powerful influence on coastal areas that otherwise appear to be sheltered from ocean waves. Through a numerical modeling investigation it is shown that San Francisco Bay, one of the earth's largest and most protected natural harbors, is vulnerable to ultra-refracted ocean waves, particularly southwest incident swell. The flux of wave energy into San Francisco Bay results from wave transformation due to the bathymetry and orientation of the large ebb tidal delta, and deep, narrow channel through the Golden Gate. For example, ultra-refracted swell waves play a critical role in the intermittent closure of the entrance to Crissy Field Marsh, a small restored tidal wetland located on the sheltered north-facing coast approximately 1.5 km east of the Golden Gate Bridge.

An adiabatic quantum flux parametron as an ultra-low-power logic device

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Ozawa, Dan; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2013-03-01

Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of IcΦ0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

Anion control as a strategy to achieve high-mobility and high-stability oxide thin-film transistors.

PubMed

Kim, Hyun-Suk; Jeon, Sang Ho; Park, Joon Seok; Kim, Tae Sang; Son, Kyoung Seok; Seon, Jong-Baek; Seo, Seok-Jun; Kim, Sun-Jae; Lee, Eunha; Chung, Jae Gwan; Lee, Hyungik; Han, Seungwu; Ryu, Myungkwan; Lee, Sang Yoon; Kim, Kinam

2013-01-01

Ultra-definition, large-area displays with three-dimensional visual effects represent megatrend in the current/future display industry. On the hardware level, such a "dream" display requires faster pixel switching and higher driving current, which in turn necessitate thin-film transistors (TFTs) with high mobility. Amorphous oxide semiconductors (AOS) such as In-Ga-Zn-O are poised to enable such TFTs, but the trade-off between device performance and stability under illumination critically limits their usability, which is related to the hampered electron-hole recombination caused by the oxygen vacancies. Here we have improved the illumination stability by substituting oxygen with nitrogen in ZnO, which may deactivate oxygen vacancies by raising valence bands above the defect levels. Indeed, the stability under illumination and electrical bias is superior to that of previous AOS-based TFTs. By achieving both mobility and stability, it is highly expected that the present ZnON TFTs will be extensively deployed in next-generation flat-panel displays.

A strong electro-optically active lead-free ferroelectric integrated on silicon

NASA Astrophysics Data System (ADS)

Abel, Stefan; Stöferle, Thilo; Marchiori, Chiara; Rossel, Christophe; Rossell, Marta D.; Erni, Rolf; Caimi, Daniele; Sousa, Marilyne; Chelnokov, Alexei; Offrein, Bert J.; Fompeyrine, Jean

2013-04-01

The development of silicon photonics could greatly benefit from the linear electro-optical properties, absent in bulk silicon, of ferroelectric oxides, as a novel way to seamlessly connect the electrical and optical domain. Of all oxides, barium titanate exhibits one of the largest linear electro-optical coefficients, which has however not yet been explored for thin films on silicon. Here we report on the electro-optical properties of thin barium titanate films epitaxially grown on silicon substrates. We extract a large effective Pockels coefficient of reff=148 pm V-1, which is five times larger than in the current standard material for electro-optical devices, lithium niobate. We also reveal the tensor nature of the electro-optical properties, as necessary for properly designing future devices, and furthermore unambiguously demonstrate the presence of ferroelectricity. The integration of electro-optical active films on silicon could pave the way towards power-efficient, ultra-compact integrated devices, such as modulators, tuning elements and bistable switches.

Channel scaling and field-effect mobility extraction in amorphous InZnO thin film transistors

NASA Astrophysics Data System (ADS)

Lee, Sunghwan; Song, Yang; Park, Hongsik; Zaslavsky, A.; Paine, D. C.

2017-09-01

Amorphous oxide semiconductors (AOSs) based on indium oxides are of great interest for next generation ultra-high definition displays that require much smaller pixel driving elements. We describe the scaling behavior in amorphous InZnO thin film transistors (TFTs) with a significant decrease in the extracted field-effect mobility μFE with channel length L (from 39.3 to 9.9 cm2/V·s as L is reduced from 50 to 5 μm). Transmission line model measurements reveal that channel scaling leads to a significant μFE underestimation due to contact resistance (RC) at the metallization/channel interface. Therefore, we suggest a method of extracting correct μFE when the TFT performance is significantly affected by RC. The corrected μFE values are higher (45.4 cm2/V·s) and nearly independent of L. The results show the critical effect of contact resistance on μFE measurements and suggest strategies to determine accurate μFE when a TFT channel is scaled.

Anion control as a strategy to achieve high-mobility and high-stability oxide thin-film transistors

PubMed Central

Kim, Hyun-Suk; Jeon, Sang Ho; Park, Joon Seok; Kim, Tae Sang; Son, Kyoung Seok; Seon, Jong-Baek; Seo, Seok-Jun; Kim, Sun-Jae; Lee, Eunha; Chung, Jae Gwan; Lee, Hyungik; Han, Seungwu; Ryu, Myungkwan; Lee, Sang Yoon; Kim, Kinam

2013-01-01

Ultra-definition, large-area displays with three-dimensional visual effects represent megatrend in the current/future display industry. On the hardware level, such a “dream” display requires faster pixel switching and higher driving current, which in turn necessitate thin-film transistors (TFTs) with high mobility. Amorphous oxide semiconductors (AOS) such as In-Ga-Zn-O are poised to enable such TFTs, but the trade-off between device performance and stability under illumination critically limits their usability, which is related to the hampered electron-hole recombination caused by the oxygen vacancies. Here we have improved the illumination stability by substituting oxygen with nitrogen in ZnO, which may deactivate oxygen vacancies by raising valence bands above the defect levels. Indeed, the stability under illumination and electrical bias is superior to that of previous AOS-based TFTs. By achieving both mobility and stability, it is highly expected that the present ZnON TFTs will be extensively deployed in next-generation flat-panel displays. PMID:23492854

Study of Direct-Contact HfO2/Si Interfaces

PubMed Central

Miyata, Noriyuki

2012-01-01

Controlling monolayer Si oxide at the HfO2/Si interface is a challenging issue in scaling the equivalent oxide thickness of HfO2/Si gate stack structures. A concept that the author proposes to control the Si oxide interface by using ultra-high vacuum electron-beam HfO2 deposition is described in this review paper, which enables the so-called direct-contact HfO2/Si structures to be prepared. The electrical characteristics of the HfO2/Si metal-oxide-semiconductor capacitors are reviewed, which suggest a sufficiently low interface state density for the operation of metal-oxide-semiconductor field-effect-transistors (MOSFETs) but reveal the formation of an unexpected strong interface dipole. Kelvin probe measurements of the HfO2/Si structures provide obvious evidence for the formation of dipoles at the HfO2/Si interfaces. The author proposes that one-monolayer Si-O bonds at the HfO2/Si interface naturally lead to a large potential difference, mainly due to the large dielectric constant of the HfO2. Dipole scattering is demonstrated to not be a major concern in the channel mobility of MOSFETs. PMID:28817060

Mechanical flip-chip for ultra-high electron mobility devices

DOE PAGES

Bennaceur, Keyan; Schmidt, Benjamin A.; Gaucher, Samuel; ...

2015-09-22

In this study, electrostatic gates are of paramount importance for the physics of devices based on high-mobility two-dimensional electron gas (2DEG) since they allow depletion of electrons in selected areas. This field-effect gating enables the fabrication of a wide range of devices such as, for example, quantum point contacts (QPC), electron interferometers and quantum dots. To fabricate these gates, processing is usually performed on the 2DEG material, which is in many cases detrimental to its electron mobility. Here we propose an alternative process which does not require any processing of the 2DEG material other than for the ohmic contacts. Thismore » approach relies on processing a separate wafer that is then mechanically mounted on the 2DEG material in a flip-chip fashion. This technique proved successful to fabricate quantum point contacts on both GaAs/AlGaAs materials with both moderate and ultra-high electron mobility.« less

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

NASA Astrophysics Data System (ADS)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.