Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu Shiyang; Nakajima, Anri; Ohashi, Takuo

2005-12-01

The interface trap generation ({delta}N{sub it}) and fixed oxide charge buildup ({delta}N{sub ot}) under negative bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current-current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for {delta}N{sub it} and {delta}N{sub ot}. At the earlier stress times, {delta}N{sub it} dominates the threshold voltage shift ({delta}V{sub th}) and {delta}N{sub ot} is negligible. With increasing stress time, the rate of increase of {delta}N{sub it} decreases continuously, showing a saturating trend for longer stress times, while {delta}N{submore » ot} still has a power-law dependence on stress time so that the relative contribution of {delta}N{sub ot} increases. The thermal activation energy of {delta}N{sub it} and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.« less

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Silicon-ion-implanted PMMA with nanostructured ultrathin layers for plastic electronics

NASA Astrophysics Data System (ADS)

Hadjichristov, G. B.; Ivanov, Tz E.; Marinov, Y. G.

2014-12-01

Being of interest for plastic electronics, ion-beam produced nanostructure, namely silicon ion (Si+) implanted polymethyl-methacrylate (PMMA) with ultrathin nanostructured dielectric (NSD) top layer and nanocomposite (NC) buried layer, is examined by electric measurements. In the proposed field-effect organic nanomaterial structure produced within the PMMA network by ion implantation with low energy (50 keV) Si+ at the fluence of 3.2 × 1016 cm-2 the gate NSD is ion-nanotracks-modified low-conductive surface layer, and the channel NC consists of carbon nanoclusters. In the studied ion-modified PMMA field-effect configuration, the gate NSD and the buried NC are formed as planar layers both with a thickness of about 80 nm. The NC channel of nano-clustered amorphous carbon (that is an organic semiconductor) provides a huge increase in the electrical conduction of the material in the subsurface region, but also modulates the electric field distribution in the drift region. The field effect via the gate NSD is analyzed. The most important performance parameters, such as the charge carrier field-effect mobility and amplification of this particular type of PMMA- based transconductance device with NC n-type channel and gate NSD top layer, are determined.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Magneto-Ionic Control of Interfacial Magnetic Anisotorpy

NASA Astrophysics Data System (ADS)

Bauer, Uwe; Emori, Satoru; Beach, Geoffrey

2014-03-01

Voltage control of magnetism could bring about revolutionary new spintronic memory and logic devices. Here, we examine domain wall (DW) dynamics in ultrathin Co films and nanowires under the influence of a voltage applied across a gadolinium oxide gate dielectric that simultaneously acts as an oxygen ion conductor. We investigate two electrode configurations, one with a continuous gate dielectric and the other with a patterned gate dielectric which exhibits an open oxide edge right underneath the electrode perimeter. We demonstrate that the open oxide edge acts as a fast diffusion path for oxygen ions and allows voltage-induced switching of magnetic anisotropy at the nanoscale by modulating interfacial chemistry rather than charge density. At room temperature this effect is limited to the vicinity of the open oxide edge, but at a temperature of 100°C it allows complete control over magnetic anisotropy across the whole electrode area, due to higher oxygen ion mobility at elevated temperature. We then harness this novel ``magneto-ionic'' effect to create unprecedentedly strong voltage-induced anisotropy modifications of 3000 fJ/Vm and create electrically programmable DW traps with pinning strengths of 650 Oe, enough to bring to a standstill DWs travelling at speeds of at least 20 m/s. This work is supported by the National Science Foundation through grant ECCS-1128439.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

PubMed

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

NASA Astrophysics Data System (ADS)

Xu, Hao; Yang, Hong; Luo, Wei-Chun; Xu, Ye-Feng; Wang, Yan-Rong; Tang, Bo; Wang, Wen-Wu; Qi, Lu-Wei; Li, Jun-Feng; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2016-08-01

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it/N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of MicroElectronics of Chinese Academy of Sciences.

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

PubMed

Zhang, Liangliang; Guo, Yuzheng; Hassan, Vinayak Vishwanath; Tang, Kechao; Foad, Majeed A; Woicik, Joseph C; Pianetta, Piero; Robertson, John; McIntyre, Paul C

2016-07-27

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Highly scaled equivalent oxide thickness of 0.66 nm for TiN/HfO2/GaSb MOS capacitors by using plasma-enhanced atomic layer deposition

NASA Astrophysics Data System (ADS)

Tsai, Ming-Li; Wang, Shin-Yuan; Chien, Chao-Hsin

2017-08-01

Through in situ hydrogen plasma treatment (HPT) and plasma-enhanced atomic-layer-deposited TiN (PEALD-TiN) layer capping, we successfully fabricated TiN/HfO2/GaSb metal-oxide-semiconductor capacitors with an ultrathin equivalent oxide thickness of 0.66 nm and a low density of states of approximately 2 × 1012 cm-2 eV-1 near the valence band edge. After in situ HPT, a native oxide-free surface was obtained through efficient etching. Moreover, the use of the in situ PEALD-TiN layer precluded high-κ dielectric damage that would have been caused by conventional sputtering, thereby yielding a superior high-κ dielectric and low gate leakage current.

Ultrathin ZnO interfacial passivation layer for atomic layer deposited ZrO2 dielectric on the p-In0.2Ga0.8As substrate

NASA Astrophysics Data System (ADS)

Liu, Chen; Lü, Hongliang; Yang, Tong; Zhang, Yuming; Zhang, Yimen; Liu, Dong; Ma, Zhenqiang; Yu, Weijian; Guo, Lixin

2018-06-01

Interfacial and electrical properties were investigated on metal-oxidesemiconductor capacitors (MOSCAPs) fabricated with bilayer ZnO/ZrO2 films by atomic layer deposition (ALD) on p-In0.2Ga0.8As substrates. The ZnO passivated In0.2Ga0.8As MOSCAPs have exhibited significantly improved capacitance-voltage (C-V) characteristics with the suppressed "stretched out" effect, increased accumulation capacitance and reduced accumulation frequency dispersion as well as the lower gate leakage current. In addition, the interface trap density (Dit) estimated by the Terman method was decreased dramatically for ZnO passivated p-In0.2Ga0.8As. The inherent mechanism is attributed to the fact that an ultrathin ZnO IPL employed by ALD prior to ZrO2 dielectric deposition can effectively suppress the formation of defect-related low-k oxides and As-As dimers at the interface, thus effectively improving the interface quality by largely removing the border traps aligned near the valence band edge of the p-In0.2Ga0.8As substrate.

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Nano-scale zirconia and hafnia dielectrics grown by atomic layer deposition: Crystallinity, interface structures and electrical properties

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub

With the continued scaling of transistors, leakage current densities across the SiO2 gate dielectric have increased enormously through direct tunneling. Presently, metal oxides having higher dielectric constants than SiO2 are being investigated to reduce the leakage current by increasing the physical thickness of the dielectric. Many possible techniques exist for depositing high-kappa gate dielectrics. Atomic layer deposition (ALD) has drawn attention as a method for preparing ultrathin metal oxide layers with excellent electrical characteristics and near-perfect film conformality due to the layer-by-layer nature of the deposition mechanism. For this research, an ALD system using ZrCl4/HfCl4 and H2O was built and optimized. The microstructural and electrical properties of ALD-ZrO2 and HfO2 grown on SiO2/Si substrates were investigated and compared using various characterization tools. In particular, the crystallization kinetics of amorphous ALD-HfO2 films were studied using in-situ annealing experiments in a TEM. The effect of crystallization on the electrical properties of ALD-HfO 2 was also investigated using various in-situ and ex-situ post-deposition anneals. Our results revealed that crystallization had little effect on the magnitude of the gate leakage current or on the conduction mechanisms. Building upon the results for each metal oxide separately, more advanced investigations were made. Several nanolaminate structures using ZrO2 and HfO2 with different sequences and layer thicknesses were characterized. The effects of the starting microstructure on the microstructural evolution of nanolaminate stacks were studied. Additionally, a promising new approach for engineering the thickness of the SiO2-based interface layer between the metal oxide and silicon substrate after deposition of the metal oxide layer was suggested. Through experimental measurements and thermodynamic analysis, it is shown that a Ti overlayer, which exhibits a high oxygen solubility, can effectively getter oxygen from the interface layer, thus decomposing SiO2 and reducing the interface layer thickness in a controllable fashion. As one of several possible applications, ALD-ZrO2 and HfO 2 gate dielectric films were deposited on Ge (001) substrates with different surface passivations. After extensive characterization using various microstructural, electrical, and chemical analyses, excellent MOS electrical properties of high-kappa gate dielectrics on Ge were successfully demonstrated with optimized surface nitridation of the Ge substrates.

Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

NASA Astrophysics Data System (ADS)

Wong, Hei; Iwai, Hiroshi; Liou, J. J.

2005-05-01

It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

Electron Doping of Ultrathin Black Phosphorus with Cu Adatoms.

PubMed

Koenig, Steven P; Doganov, Rostislav A; Seixas, Leandro; Carvalho, Alexandra; Tan, Jun You; Watanabe, Kenji; Taniguchi, Takashi; Yakovlev, Nikolai; Castro Neto, Antonio H; Özyilmaz, Barbaros

2016-04-13

Few-layer black phosphorus is a monatomic two-dimensional crystal with a direct band gap that has high carrier mobility for both holes and electrons. Similarly to other layered atomic crystals, like graphene or layered transition metal dichalcogenides, the transport behavior of few-layer black phosphorus is sensitive to surface impurities, adsorbates, and adatoms. Here we study the effect of Cu adatoms onto few-layer black phosphorus by characterizing few-layer black phosphorus field effect devices and by performing first-principles calculations. We find that the addition of Cu adatoms can be used to controllably n-dope few layer black phosphorus, thereby lowering the threshold voltage for n-type conduction without degrading the transport properties. We demonstrate a scalable 2D material-based complementary inverter which utilizes a boron nitride gate dielectric, a graphite gate, and a single bP crystal for both the p- and n-channels. The inverter operates at matched input and output voltages, exhibits a gain of 46, and does not require different contact metals or local electrostatic gating.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

PubMed Central

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-01-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process. PMID:27184121

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

NASA Astrophysics Data System (ADS)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Engineering epitaxial γ-Al2O3 gate dielectric films on 4H-SiC

NASA Astrophysics Data System (ADS)

Tanner, Carey M.; Toney, Michael F.; Lu, Jun; Blom, Hans-Olof; Sawkar-Mathur, Monica; Tafesse, Melat A.; Chang, Jane P.

2007-11-01

The formation of epitaxial γ-Al2O3 thin films on 4H-SiC was found to be strongly dependent on the film thickness. An abrupt interface was observed in films up to 200 Å thick with an epitaxial relationship of γ-Al2O3(111)‖4H-SiC(0001) and γ-Al2O3(44¯0)‖4H-SiC(112¯0). The in-plane alignment between the film and the substrate is nearly complete for γ-Al2O3 films up to 115 Å thick, but quickly diminishes in thicker films. The films are found to be slightly strained laterally in tension; the strain increases with thickness and then decreases in films thicker than 200 Å, indicating strain relaxation which is accompanied by increased misorientation. By controlling the structure of ultrathin Al2O3 films, metal-oxide-semiconductor capacitors with Al2O3 gate dielectrics on 4H-SiC were found to have a very low leakage current density, suggesting suitability of Al2O3 for SiC device integration.

Flexible active-matrix organic light-emitting diode display enabled by MoS2 thin-film transistor.

PubMed

Choi, Minwoo; Park, Yong Ju; Sharma, Bhupendra K; Bae, Sa-Rang; Kim, Soo Young; Ahn, Jong-Hyun

2018-04-01

Atomically thin molybdenum disulfide (MoS 2 ) has been extensively investigated in semiconductor electronics but has not been applied in a backplane circuitry of organic light-emitting diode (OLED) display. Its applicability as an active drive element is hampered by the large contact resistance at the metal/MoS 2 interface, which hinders the transport of carriers at the dielectric surface, which in turn considerably deteriorates the mobility. Modified switching device architecture is proposed for efficiently exploiting the high- k dielectric Al 2 O 3 layer, which, when integrated in an active matrix, can drive the ultrathin OLED display even in dynamic folding states. The proposed architecture exhibits 28 times increase in mobility compared to a normal back-gated thin-film transistor, and its potential as a wearable display attached to a human wrist is demonstrated.

Flexible active-matrix organic light-emitting diode display enabled by MoS2 thin-film transistor

PubMed Central

Park, Yong Ju

2018-01-01

Atomically thin molybdenum disulfide (MoS2) has been extensively investigated in semiconductor electronics but has not been applied in a backplane circuitry of organic light-emitting diode (OLED) display. Its applicability as an active drive element is hampered by the large contact resistance at the metal/MoS2 interface, which hinders the transport of carriers at the dielectric surface, which in turn considerably deteriorates the mobility. Modified switching device architecture is proposed for efficiently exploiting the high-k dielectric Al2O3 layer, which, when integrated in an active matrix, can drive the ultrathin OLED display even in dynamic folding states. The proposed architecture exhibits 28 times increase in mobility compared to a normal back-gated thin-film transistor, and its potential as a wearable display attached to a human wrist is demonstrated. PMID:29713686

Tunneling-injection in vertical quasi-2D heterojunctions enabled efficient and adjustable optoelectronic conversion

PubMed Central

Tan, Wei-Chun; Chiang, Chia-Wei; Hofmann, Mario; Chen, Yang-Fang

2016-01-01

The advent of 2D materials integration has enabled novel heterojunctions where carrier transport proceeds thrsough different ultrathin layers. We here demonstrate the potential of such heterojunctions on a graphene/dielectric/semiconductor vertical stack that combines several enabling features for optoelectronic devices. Efficient and stable light emission was achieved through carrier tunneling from the graphene injector into prominent states of a luminescent material. Graphene’s unique properties enable fine control of the band alignment in the heterojunction. This advantage was used to produce vertical tunneling-injection light-emitting transistors (VtiLET) where gating allows adjustment of the light emission intensity independent of applied bias. This device was shown to simultaneously act as a light detecting transistor with a linear and gate tunable sensitivity. The presented development of an electronically controllable multifunctional light emitter, light detector and transistor open up a new route for future optoelectronics. PMID:27507171

Tunneling-injection in vertical quasi-2D heterojunctions enabled efficient and adjustable optoelectronic conversion

NASA Astrophysics Data System (ADS)

Tan, Wei-Chun; Chiang, Chia-Wei; Hofmann, Mario; Chen, Yang-Fang

2016-08-01

The advent of 2D materials integration has enabled novel heterojunctions where carrier transport proceeds thrsough different ultrathin layers. We here demonstrate the potential of such heterojunctions on a graphene/dielectric/semiconductor vertical stack that combines several enabling features for optoelectronic devices. Efficient and stable light emission was achieved through carrier tunneling from the graphene injector into prominent states of a luminescent material. Graphene’s unique properties enable fine control of the band alignment in the heterojunction. This advantage was used to produce vertical tunneling-injection light-emitting transistors (VtiLET) where gating allows adjustment of the light emission intensity independent of applied bias. This device was shown to simultaneously act as a light detecting transistor with a linear and gate tunable sensitivity. The presented development of an electronically controllable multifunctional light emitter, light detector and transistor open up a new route for future optoelectronics.

Control of magnetism in Co by an electric field

NASA Astrophysics Data System (ADS)

Chiba, D.; Ono, T.

2013-05-01

In this paper, we review the recent experimental developments on electric-field switching of ferromagnetism in ultra-thin Co films. The application of an electric field changes the electron density at the surface of the Co film, which results in modulation of its Curie temperature. A capacitor structure consisting of a gate electrode, a solid-state dielectric insulator and a Co bottom electrode is used to observe the effect. To obtain a larger change in the electron density, we also fabricated an electric double-layer capacitor structure using an ionic liquid. A large change in the Curie temperature of ∼100 K across room temperature is achieved with this structure. The application of the electric field influences not only the Curie temperature but also the domain-wall motion. A change in the velocity of a domain wall prepared in a Co micro-wire of more than one order of magnitude is observed. Possible mechanisms to explain the above-mentioned electric-field effects in Co ultra-thin films are discussed.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sanne, A.; Movva, H. C. P.; Kang, S.

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriersmore » as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.« less

Paramagnetic defects and charge trapping behavior of ZrO2 films deposited on germanium by plasma-enhanced CVD

NASA Astrophysics Data System (ADS)

Mahata, C.; Bera, M. K.; Bose, P. K.; Maiti, C. K.

2009-02-01

Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping behavior and chemical nature of defects in ultrathin (~14 nm) high-k ZrO2 dielectric films deposited on p-Ge (1 0 0) substrates at low temperature (<200 °C) by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma at a pressure of ~65 Pa. Both the band and defect-related electron states have been characterized using electron paramagnetic resonance, internal photoemission, capacitance-voltage and current-voltage measurements under UV illumination. Capacitance-voltage and photocurrent-voltage measurements were used to determine the centroid of oxide charge within the high-k gate stack. The observed shifts in photocurrent response of the Al/ZrO2/GeO2/p-Ge metal-insulator-semiconductor (MIS) capacitors indicate the location of the centroids to be within the ZrO2 dielectric near to the gate electrode. Moreover, the measured flat band voltage and photocurrent shifts also indicate a large density of traps in the dielectric. The impact of plasma nitridation on the interfacial quality of the oxides has been investigated. Different N sources, such as NO and NH3, have been used for nitrogen engineering. Oxynitride samples show a lower defect density and trapping over the non-nitrided samples. The charge trapping and detrapping properties of MIS capacitors under stressing in constant current and voltage modes have been investigated in detail.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

NASA Astrophysics Data System (ADS)

Chaisantikulwat, W.; Mouis, M.; Ghibaudo, G.; Cristoloveanu, S.; Widiez, J.; Vinet, M.; Deleonibus, S.

2007-11-01

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition

NASA Astrophysics Data System (ADS)

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-05-01

In situ-formed SiO2 was introduced into HfO2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO2/SiO2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10-3 A/cm2 at gate bias of Vfb + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO2/SiO2/Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition.

PubMed

Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

2017-12-01

In situ-formed SiO 2 was introduced into HfO 2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO 2 /SiO 2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO 2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO 2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10 -3 A/cm 2 at gate bias of V fb  + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO 2 /SiO 2 /Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO 2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

Polarization Converter with Controllable Birefringence Based on Hybrid All-Dielectric-Graphene Metasurface

NASA Astrophysics Data System (ADS)

Owiti, Edgar O.; Yang, Hanning; Liu, Peng; Ominde, Calvine F.; Sun, Xiudong

2018-02-01

Previous studies on hybrid dielectric-graphene metasurfaces have been used to implement induced transparency devices, while exhibiting high Q-factors based on trapped magnetic resonances. Typically, the transparency windows are single wavelength and less appropriate for polarization conversion structures. In this work, a quarter-wave plate based on a hybrid silicon-graphene metasurface with controllable birefringence is numerically designed. The phenomena of trapped magnetic mode resonance and high Q-factors are modulated by inserting graphene between silicon and silica. This results in a broader transmission wavelength in comparison to the all-dielectric structure without graphene. The birefringence tunability is based on the dimensions of silicon and the Fermi energy of graphene. Consequently, a linear-to-circular polarization conversion is achieved at a high degree of 96%, in the near-infrared. Moreover, the polarization state of the scattered light is switchable between right and left hand circular polarizations, based on an external gate biasing voltage. Unlike in plasmonic metasurfaces, these achievements demonstrate an efficient structure that is free from radiative and ohmic losses. Furthermore, the ultrathin thickness and the compactness of the structure are demonstrated as key components in realizing integrable and CMOS compatible photonic sensors.

Effects of substrate heating and post-deposition annealing on characteristics of thin MOCVD HfO2 films

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Ramesh, Sivaramakrishnan; Dutta, Shibesh; Virajit Garbhapu, Venkata

2018-02-01

It is well known that Hf-based dielectrics have replaced the traditional SiO2 and SiON as gate dielectric materials for conventional CMOS devices. By using thicker high-k materials such as HfO2 rather than ultra-thin SiO2, we can bring down leakage current densities in MOS devices to acceptable levels. HfO2 is also one of the potential candidates as a blocking dielectric for Flash memory applications for the same reason. In this study, effects of substrate heating and oxygen flow rate while depositing HfO2 thin films using CVD and effects of post deposition annealing on the physical and electrical characteristics of HfO2 thin films are presented. It was observed that substrate heating during deposition helps improve the density and electrical characteristics of the films. At higher substrate temperature, Vfb moved closer to zero and also resulted in significant reduction in hysteresis. Higher O2 flow rates may improve capacitance, but also results in slightly higher leakage. The effect of PDA depended on film thickness and O2 PDA improved characteristics only for thick films. For thinner films forming gas anneal resulted in better electrical characteristics.

Polarization Converter with Controllable Birefringence Based on Hybrid All-Dielectric-Graphene Metasurface.

PubMed

Owiti, Edgar O; Yang, Hanning; Liu, Peng; Ominde, Calvine F; Sun, Xiudong

2018-02-03

Previous studies on hybrid dielectric-graphene metasurfaces have been used to implement induced transparency devices, while exhibiting high Q-factors based on trapped magnetic resonances. Typically, the transparency windows are single wavelength and less appropriate for polarization conversion structures. In this work, a quarter-wave plate based on a hybrid silicon-graphene metasurface with controllable birefringence is numerically designed. The phenomena of trapped magnetic mode resonance and high Q-factors are modulated by inserting graphene between silicon and silica. This results in a broader transmission wavelength in comparison to the all-dielectric structure without graphene. The birefringence tunability is based on the dimensions of silicon and the Fermi energy of graphene. Consequently, a linear-to-circular polarization conversion is achieved at a high degree of 96%, in the near-infrared. Moreover, the polarization state of the scattered light is switchable between right and left hand circular polarizations, based on an external gate biasing voltage. Unlike in plasmonic metasurfaces, these achievements demonstrate an efficient structure that is free from radiative and ohmic losses. Furthermore, the ultrathin thickness and the compactness of the structure are demonstrated as key components in realizing integrable and CMOS compatible photonic sensors.

Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

Few-layer nanoplates of Bi 2 Se 3 and Bi 2 Te 3 with highly tunable chemical potential.

PubMed

Kong, Desheng; Dang, Wenhui; Cha, Judy J; Li, Hui; Meister, Stefan; Peng, Hailin; Liu, Zhongfan; Cui, Yi

2010-06-09

A topological insulator (TI) represents an unconventional quantum phase of matter with insulating bulk band gap and metallic surface states. Recent theoretical calculations and photoemission spectroscopy measurements show that group V-VI materials Bi(2)Se(3), Bi(2)Te(3), and Sb(2)Te(3) are TIs with a single Dirac cone on the surface. These materials have anisotropic, layered structures, in which five atomic layers are covalently bonded to form a quintuple layer, and quintuple layers interact weakly through van der Waals interaction to form the crystal. A few quintuple layers of these materials are predicted to exhibit interesting surface properties. Different from our previous nanoribbon study, here we report the synthesis and characterizations of ultrathin Bi(2)Te(3) and Bi(2)Se(3) nanoplates with thickness down to 3 nm (3 quintuple layers), via catalyst-free vapor-solid (VS) growth mechanism. Optical images reveal thickness-dependent color and contrast for nanoplates grown on oxidized silicon (300 nm SiO(2)/Si). As a new member of TI nanomaterials, ultrathin TI nanoplates have an extremely large surface-to-volume ratio and can be electrically gated more effectively than the bulk form, potentially enhancing surface state effects in transport measurements. Low-temperature transport measurements of a single nanoplate device, with a high-k dielectric top gate, show decrease in carrier concentration by several times and large tuning of chemical potential.

Loss/gain-induced ultrathin antireflection coatings

PubMed Central

Luo, Jie; Li, Sucheng; Hou, Bo; Lai, Yun

2016-01-01

Tradional antireflection coatings composed of dielectric layers usually require the thickness to be larger than quarter wavelength. Here, we demonstrate that materials with permittivity or permeability dominated by imaginary parts, i.e. lossy or gain media, can realize non-resonant antireflection coatings in deep sub-wavelength scale. Interestingly, while the reflected waves are eliminated as in traditional dielectric antireflection coatings, the transmitted waves can be enhanced or reduced, depending on whether gain or lossy media are applied, respectively. We provide a unified theory for the design of such ultrathin antireflection coatings, showing that under different polarizations and incident angles, different types of ultrathin coatings should be applied. Especially, under transverse magnetic polarization, the requirement shows a switch between gain and lossy media at Brewster angle. As a proof of principle, by using conductive films as a special type of lossy antireflection coatings, we experimentally demonstrate the suppression of Fabry-Pérot resonances in a broad frequency range for microwaves. This valuable functionality can be applied to remove undesired resonant effects, such as the frequency-dependent side lobes induced by resonances in dielectric coverings of antennas. Our work provides a guide for the design of ultrathin antireflection coatings as well as their applications in broadband reflectionless devices. PMID:27349750

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric

PubMed Central

Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

2017-01-01

Two-dimensional layered semiconductors such as molybdenum disulfide (MoS2) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS2 and an ultra-thin HfO2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS2-HfO2 interface is responsible for the generation of interface states with a density (Dit) reaching ~7.03 × 1011 cm−2 eV−1. This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in Dit could be achieved by thermally diffusing S atoms to the MoS2-HfO2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS2 devices with carrier transport enhancement. PMID:28084434

Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

PubMed

Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

2017-01-13

Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

Hot-Carrier Immunity of Polycrystalline Silicon Thin Film Transistors Using Silicon Oxynitride Gate Dielectric Formed with Plasma-Enhanced Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Kunii, Masafumi

2009-11-01

An analysis is presented of the hot-carrier degradation in a polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon oxynitride gate dielectric formed with plasma-enhanced chemical vapor deposition. An introduction of silicon oxynitride into a gate dielectric significantly improves hot-carrier immunity even under the severe stressing mode of drain avalanche hot carriers. To compensate the initial negative shift of threshold voltage for TFTs with a silicon oxynitride gate dielectric, high-pressure water vapor annealing (HWA) is applied. A comparison of TFTs with and without HWA reveals that the improvement in hot-carrier immunity is mainly attributed to the introduction of Si≡N bonds into a gate dielectric.

High quality HfO{sub 2}/p-GaSb(001) metal-oxide-semiconductor capacitors with 0.8 nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, Michael; Datta, Suman, E-mail: sdatta@engr.psu.edu; Bruce Rayner, G.

2014-12-01

We investigate in-situ cleaning of GaSb surfaces and its effect on the electrical performance of p-type GaSb metal-oxide-semiconductor capacitor (MOSCAP) using a remote hydrogen plasma. Ultrathin HfO{sub 2} films grown by atomic layer deposition were used as a high permittivity gate dielectric. Compared to conventional ex-situ chemical cleaning methods, the in-situ GaSb surface treatment resulted in a drastic improvement in the impedance characteristics of the MOSCAPs, directly evidencing a much lower interface trap density and enhanced Fermi level movement efficiency. We demonstrate that by using a combination of ex-situ and in-situ surface cleaning steps, aggressively scaled HfO{sub 2}/p-GaSb MOSCAP structuresmore » with a low equivalent oxide thickness of 0.8 nm and efficient gate modulation of the surface potential are achieved, allowing to push the Fermi level far away from the valence band edge high up into the band gap of GaSb.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakhri, M.; Theisen, M.; Behrendt, A.

Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices withmore » encapsulation.« less

Broadband enhancement of dielectric light trapping nanostructure used in ultra-thin solar cells

NASA Astrophysics Data System (ADS)

Yang, Dong; Xu, Zhaopeng; Bian, Fei; Wang, Haiyan; Wang, Jiazhuang; Sun, Lu

2018-03-01

A dielectric fishnet nanostructure is designed to increase the light trapping capability of ultra-thin solar cells. The complex performance of ultra-thin cells such as the optical response and electrical response are fully quantified in simulation through a complete optoelectronic investigation. The results show that the optimized light trapping nanostructure can enhances the electromagnetic resonance in active layer then lead to extraordinary enhancement of both absorption and light-conversion capabilities in the solar cell. The short-circuit current density increases by 49.46% from 9.40 mA/cm2 to 14.05 mA/cm2 and light-conversion efficiency increases by 51.84% from 9.51% to 14.44% compared to the benchmark, a solar cell with an ITO-GaAs-Ag structure.

Fabrication of ultrathin film capacitors by chemical solution deposition

DOE PAGES

Brennecka, Geoff L.; Tuttle, Bruce A.

2007-10-01

We present that a facile solution-based processing route using standard spin-coating deposition techniques has been developed for the production of reliable capacitors based on lead lanthanum zirconate titanate (PLZT) with active areas of ≥1 mm 2 and dielectric layer thicknesses down to 50 nm. With careful control of the dielectric phase development through improved processing, ultrathin capacitors exhibited slim ferroelectric hysteresis loops and dielectric constants of >1000, similar to those of much thicker films. Furthermore, it has been demonstrated that chemical solution deposition is a viable route to the production of capacitor films which are as thin as 50 nmmore » but are still macroscopically addressable with specific capacitance values >160 nF/mm 2.« less

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Manipulation of Spin-Torque Generation Using Ultrathin Au

NASA Astrophysics Data System (ADS)

An, Hongyu; Haku, Satoshi; Kanno, Yusuke; Nakayama, Hiroyasu; Maki, Hideyuki; Shi, Ji; Ando, Kazuya

2018-06-01

The generation and the manipulation of current-induced spin-orbit torques are of essential interest in spintronics. However, in spite of the vital progress in spin orbitronics, electric control of the spin-torque generation still remains elusive and challenging. We report on electric control of the spin-torque generation using ionic-liquid gating of ultrathin Au. We show that by simply depositing a SiO2 capping layer on an ultrathin-Au /Ni81Fe19 bilayer, the spin-torque generation efficiency is drastically enhanced by a maximum of 7 times. This enhancement is verified to be originated from the rough ultrathin-Au /Ni81Fe19 interface induced by the SiO2 deposition, which results in the enhancement of the interface spin-orbit scattering. We further show that the spin-torque generation efficiency from the ultrathin Au film can be reversibly manipulated by a factor of 2 using the ionic gating with an external electric field within a small range of 1 V. These results pave a way towards the efficient control of the spin-torque generation in spintronic applications.

Solid-State Densification of Spun-Cast Self-Assembled Monolayers for Use in Ultra-Thin Hybrid Dielectrics.

PubMed

Hutchins, Daniel O; Acton, Orb; Weidner, Tobias; Cernetic, Nathan; Baio, Joe E; Castner, David G; Ma, Hong; Jen, Alex K-Y

2012-11-15

Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlO x (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7×10 -8 A cm -2 and capacitance density of 0.62 µF cm -2 at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to 1.1 cm 2 V -1 s -1 .

Solid-State Densification of Spun-Cast Self-Assembled Monolayers for Use in Ultra-Thin Hybrid Dielectrics

PubMed Central

Hutchins, Daniel O.; Acton, Orb; Weidner, Tobias; Cernetic, Nathan; Baio, Joe E.; Castner, David G.; Ma, Hong; Jen, Alex K.-Y.

2013-01-01

Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlOx (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7×10−8 A cm−2 and capacitance density of 0.62 µF cm−2 at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to 1.1 cm2 V−1 s−1. PMID:24288423

On the persistence of polar domains in ultrathin ferroelectric capacitors.

PubMed

Zubko, Pavlo; Lu, Haidong; Bark, Chung-Wung; Martí, Xavi; Santiso, José; Eom, Chang-Beom; Catalan, Gustau; Gruverman, Alexei

2017-07-19

The instability of ferroelectric ordering in ultra-thin films is one of the most important fundamental issues pertaining realization of a number of electronic devices with enhanced functionality, such as ferroelectric and multiferroic tunnel junctions or ferroelectric field effect transistors. In this paper, we investigate the polarization state of archetypal ultrathin (several nanometres) ferroelectric heterostructures: epitaxial single-crystalline BaTiO 3 films sandwiched between the most habitual perovskite electrodes, SrRuO 3 , on top of the most used perovskite substrate, SrTiO 3 . We use a combination of piezoresponse force microscopy, dielectric measurements and structural characterization to provide conclusive evidence for the ferroelectric nature of the relaxed polarization state in ultrathin BaTiO 3 capacitors. We show that even the high screening efficiency of SrRuO 3 electrodes is still insufficient to stabilize polarization in SrRuO 3 /BaTiO 3 /SrRuO 3 heterostructures at room temperature. We identify the key role of domain wall motion in determining the macroscopic electrical properties of ultrathin capacitors and discuss their dielectric response in the light of the recent interest in negative capacitance behaviour.

The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

PubMed

Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

2014-11-12

Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

PubMed Central

Reddy, Bobby; Dorvel, Brian R.; Go, Jonghyun; Nair, Pradeep R.; Elibol, Oguz H.; Credo, Grace M.; Daniels, Jonathan S.; Chow, Edmond K. C.; Su, Xing; Varma, Madoo; Alam, Muhammad A.

2011-01-01

Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems. PMID:21203849

Low-voltage organic strain sensor on plastic using polymer/high- K inorganic hybrid gate dielectrics

NASA Astrophysics Data System (ADS)

Jung, Soyoun; Ji, Taeksoo; Varadan, Vijay K.

2007-12-01

In this paper, gate-induced pentacene semiconductor strain sensors based on hybrid-gate dielectrics using poly-vinylphenol (PVP) and high-K inorganic, Ta IIO 5 are fabricated on flexible substrates, polyethylene naphthalate (PEN). The Ta IIO 5 gate dielectric layer is combined with a thin PVP layer to obtain very smooth and hydrophobic surfaces which improve the molecular structures of pentacene films. The PVP-Ta IIO 5 hybrid-gate dielectric films exhibit a high dielectric capacitance and low leakage current. The sensors adopting thin film transistor (TFT)-like structures show a significantly reduced operating voltage (~6V), and good device characteristics with a field-effect mobility of 1.89 cm2/V•s, a threshold voltage of -0.5 V, and an on/off ratio of 10 3. The strain sensor, one of the practical applications in large-area organic electronics, was characterized with different bending radii of 50, 40, 30, and 20 mm. The sensor output signals were significantly improved with low-operating voltages.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Duan, Guo Xing; Hatchtel, Jordan; Shen, Xiao

Here, we investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The activation energies we measured for interface-trap charge buildup during negative-bias temperature stress were lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce themore » strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Moreover, activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2.« less

Designing hybrid gate dielectric for fully printing high-performance carbon nanotube thin film transistors

NASA Astrophysics Data System (ADS)

Li, Qian; Li, Shilong; Yang, Dehua; Su, Wei; Wang, Yanchun; Zhou, Weiya; Liu, Huaping; Xie, Sishen

2017-10-01

The electrical characteristics of carbon nanotube (CNT) thin-film transistors (TFTs) strongly depend on the properties of the gate dielectric that is in direct contact with the semiconducting CNT channel materials. Here, we systematically investigated the dielectric effects on the electrical characteristics of fully printed semiconducting CNT-TFTs by introducing the organic dielectrics of poly(methyl methacrylate) (PMMA) and octadecyltrichlorosilane (OTS) to modify SiO2 dielectric. The results showed that the organic-modified SiO2 dielectric formed a favorable interface for the efficient charge transport in s-SWCNT-TFTs. Compared to single-layer SiO2 dielectric, the use of organic-inorganic hybrid bilayer dielectrics dramatically improved the performances of SWCNT-TFTs such as mobility, threshold voltage, hysteresis and on/off ratio due to the suppress of charge scattering, gate leakage current and charge trapping. The transport mechanism is related that the dielectric with few charge trapping provided efficient percolation pathways for charge carriers, while reduced the charge scattering. High density of charge traps which could directly act as physical transport barriers and significantly restrict the charge carrier transport and, thus, result in decreased mobile carriers and low device performance. Moreover, the gate leakage phenomenon is caused by conduction through charge traps. So, as a component of TFTs, the gate dielectric is of crucial importance to the manufacture of high quality TFTs from the aspects of affecting the gate leakage current and device operation voltage, as well as the charge carrier transport. Interestingly, the OTS-modified SiO2 allows to directly print horizontally aligned CNT film, and the corresponding devices exhibited a higher mobility than that of the devices with the hybrid PMMA/SiO2 dielectric although the thickness of OTS layer is only ˜2.5 nm. Our present result may provide key guidance for the further development of printed nanomaterial electronics.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

NASA Astrophysics Data System (ADS)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

NASA Astrophysics Data System (ADS)

Verma, Madhulika; Sharma, Dheeraj; Pandey, Sunil; Nigam, Kaushal; Kondekar, P. N.

2017-01-01

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM 1 and ϕM 2 are used in short-gate DMTFET, where ϕM 1 represents the work-function of gate M1 near to the drain end, while ϕM 2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

Interface plasmonic properties of silver coated by ultrathin metal oxides

NASA Astrophysics Data System (ADS)

Sytchkova, A.; Zola, D.; Grilli, M. L.; Piegari, A.; Fang, M.; He, H.; Shao, J.

2011-09-01

Many fields of high technology take advantage of conductor-dielectric interface properties. Deeper knowledge of physical processes that determine the optical response of the structures containing metal-dielectric interfaces is important for improving the performance of thin film devices containing such materials. Here we present a study on optical properties of several ultrathin metal oxides deposited over thin silver layers. Some widely used materials (Al2O3, SiO2, Y2O3, HfO2) were selected for deposition by r.f. sputtering, and the created metal-dielectric structures with two of them, alumina and silica, were investigated in this work using attenuated total reflectance (ATR) technique and by variable-angle spectroscopic ellipsometry (VASE). VASE was performed with a help of a commercial ellipsometer at various incident angles and in a wide spectral range. A home-made sample holder manufactured for WVASE ellipsometer and operational in Otto configuration has been implemented for angle-resolved and spectral ATR measurements. Simultaneous analysis of data obtained by these two independent techniques allows elaboration of a representative model for plasmonic-related phenomena at metal-dielectric interface. The optical constants of the interface layers formed between metal and ultrathin oxide layers are investigated. A series of oxides chosen for this study allows a comparative analysis aimed for selection of the most appropriate materials for different applications.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Atomic Layer Engineering of High-κ Ferroelectricity in 2D Perovskites.

PubMed

Li, Bao-Wen; Osada, Minoru; Kim, Yoon-Hyun; Ebina, Yasuo; Akatsuka, Kosho; Sasaki, Takayoshi

2017-08-09

Complex perovskite oxides offer tremendous potential for controlling their rich variety of electronic properties, including high-T C superconductivity, high-κ ferroelectricity, and quantum magnetism. Atomic-scale control of these intriguing properties in ultrathin perovskites is an important challenge for exploring new physics and device functionality at atomic dimensions. Here, we demonstrate atomic-scale engineering of dielectric responses using two-dimensional (2D) homologous perovskite nanosheets (Ca 2 Na m-3 Nb m O 3m+1 ; m = 3-6). In this homologous 2D material, the thickness of the perovskite layers can be incrementally controlled by changing m, and such atomic layer engineering enhances the high-κ dielectric response and local ferroelectric instability. The end member (m = 6) attains a high dielectric constant of ∼470, which is the highest among all known dielectrics in the ultrathin region (<10 nm). These results provide a new strategy for achieving high-κ ferroelectrics for use in ultrascaled high-density capacitors and post-graphene technology.

Gate-Variable Mid-Infrared Optical Transitions in a (Bi1-xSbx)2Te3 Topological Insulator.

PubMed

Whitney, William S; Brar, Victor W; Ou, Yunbo; Shao, Yinming; Davoyan, Artur R; Basov, D N; He, Ke; Xue, Qi-Kun; Atwater, Harry A

2017-01-11

We report mid-infrared spectroscopy measurements of ultrathin, electrostatically gated (Bi 1-x Sb x ) 2 Te 3 topological insulator films in which we observe several percent modulation of transmittance and reflectance as gating shifts the Fermi level. Infrared transmittance measurements of gated films were enabled by use of an epitaxial lift-off method for large-area transfer of topological insulator films from infrared-absorbing SrTiO 3 growth substrates to thermal oxidized silicon substrates. We combine these optical experiments with transport measurements and angle-resolved photoemission spectroscopy to identify the observed spectral modulation as a gate-driven transfer of spectral weight between both bulk and 2D topological surface channels and interband and intraband channels. We develop a model for the complex permittivity of gated (Bi 1-x Sb x ) 2 Te 3 and find a good match to our experimental data. These results open the path for layered topological insulator materials as a new candidate for tunable, ultrathin infrared optics and highlight the possibility of switching topological optoelectronic phenomena between bulk and spin-polarized surface regimes.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

PubMed

Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

2015-10-21

The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

Organic transistors manufactured using inkjet technology with subfemtoliter accuracy

PubMed Central

Sekitani, Tsuyoshi; Noguchi, Yoshiaki; Zschieschang, Ute; Klauk, Hagen; Someya, Takao

2008-01-01

A major obstacle to the development of organic transistors for large-area sensor, display, and circuit applications is the fundamental compromise between manufacturing efficiency, transistor performance, and power consumption. In the past, improving the manufacturing efficiency through the use of printing techniques has inevitably resulted in significantly lower performance and increased power consumption, while attempts to improve performance or reduce power have led to higher process temperatures and increased manufacturing cost. Here, we lift this fundamental limitation by demonstrating subfemtoliter inkjet printing to define metal contacts with single-micrometer resolution on the surface of high-mobility organic semiconductors to create high-performance p-channel and n-channel transistors and low-power complementary circuits. The transistors employ an ultrathin low-temperature gate dielectric based on a self-assembled monolayer that allows transistors and circuits on rigid and flexible substrates to operate with very low voltages. PMID:18362348

Structural and electrical properties of single crystalline SrZrO3 epitaxially grown on Ge (001)

NASA Astrophysics Data System (ADS)

Lim, Z. H.; Ahmadi-Majlan, K.; Grimley, E. D.; Du, Y.; Bowden, M.; Moghadam, R.; LeBeau, J. M.; Chambers, S. A.; Ngai, J. H.

2017-08-01

We present structural and electrical characterization of SrZrO3 that has been epitaxially grown on Ge(001) by oxide molecular beam epitaxy. Single crystalline SrZrO3 can be nucleated on Ge via deposition at low temperatures followed by annealing at 550 °C in ultra-high vacuum. Photoemission spectroscopy measurements reveal that SrZrO3 exhibits a type-I band arrangement with respect to Ge, with conduction and valence band offsets of 1.4 eV and 3.66 eV, respectively. Capacitance-voltage and current-voltage measurements on 4 nm thick films reveal low leakage current densities and an unpinned Fermi level at the interface that allows modulation of the surface potential of Ge. Ultra-thin films of epitaxial SrZrO3 can thus be explored as a potential gate dielectric for Ge.

Charge Transfer and Orbital Level Alignment at Inorganic/Organic Interfaces: The Role of Dielectric Interlayers.

PubMed

Hollerer, Michael; Lüftner, Daniel; Hurdax, Philipp; Ules, Thomas; Soubatch, Serguei; Tautz, Frank Stefan; Koller, Georg; Puschnig, Peter; Sterrer, Martin; Ramsey, Michael G

2017-06-27

It is becoming accepted that ultrathin dielectric layers on metals are not merely passive decoupling layers, but can actively influence orbital energy level alignment and charge transfer at interfaces. As such, they can be important in applications ranging from catalysis to organic electronics. However, the details at the molecular level are still under debate. In this study, we present a comprehensive analysis of the phenomenon of charge transfer promoted by a dielectric interlayer with a comparative study of pentacene adsorbed on Ag(001) with and without an ultrathin MgO interlayer. Using scanning tunneling microscopy and photoemission tomography supported by density functional theory, we are able to identify the orbitals involved and quantify the degree of charge transfer in both cases. Fractional charge transfer occurs for pentacene adsorbed on Ag(001), while the presence of the ultrathin MgO interlayer promotes integer charge transfer with the lowest unoccupied molecular orbital transforming into a singly occupied and singly unoccupied state separated by a large gap around the Fermi energy. Our experimental approach allows a direct access to the individual factors governing the energy level alignment and charge-transfer processes for molecular adsorbates on inorganic substrates.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

NASA Astrophysics Data System (ADS)

Vijayvargiya, V.; Reniwal, B. S.; Singh, P.; Vishvakarma, S. K.

2017-06-01

The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

NASA Astrophysics Data System (ADS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-06-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr0.52Ti0.48)-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (gm-Vg) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

Gate bias stress in pentacene field-effect-transistors: Charge trapping in the dielectric or semiconductor

NASA Astrophysics Data System (ADS)

Häusermann, R.; Batlogg, B.

2011-08-01

Gate bias stress instability in organic field-effect transistors (OFETs) is a major conceptual and device issue. This effect manifests itself by an undesirable shift of the transfer characteristics and is associated with long term charge trapping. We study the role of the dielectric and the semiconductor separately by producing OFETs with the same semiconductor (pentacene) combined with different dielectrics (SiO2 and Cytop). We show that it is possible to fabricate devices which are immune to gate bias stress. For other material combinations, charge trapping occurs in the semiconductor alone or in the dielectric.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L.; Holland, Christopher; Chichester, David

2016-08-23

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Integrated field emission array for ion desorption

DOEpatents

Resnick, Paul J; Hertz, Kristin L; Holland, Christopher; Chichester, David; Schwoebel, Paul

2013-09-17

An integrated field emission array for ion desorption includes an electrically conductive substrate; a dielectric layer lying over the electrically conductive substrate comprising a plurality of laterally separated cavities extending through the dielectric layer; a like plurality of conically-shaped emitter tips on posts, each emitter tip/post disposed concentrically within a laterally separated cavity and electrically contacting the substrate; and a gate electrode structure lying over the dielectric layer, including a like plurality of circular gate apertures, each gate aperture disposed concentrically above an emitter tip/post to provide a like plurality of annular gate electrodes and wherein the lower edge of each annular gate electrode proximate the like emitter tip/post is rounded. Also disclosed herein are methods for fabricating an integrated field emission array.

Rhenium Disulfide Depletion-Load Inverter

NASA Astrophysics Data System (ADS)

McClellan, Connor; Corbet, Chris; Rai, Amritesh; Movva, Hema C. P.; Tutuc, Emanuel; Banerjee, Sanjay K.

2015-03-01

Many semiconducting Transition Metal Dichalcogenide (TMD) materials have been effectively used to create Field-Effect Transistor (FET) devices but have yet to be used in logic designs. We constructed a depletion-load voltage inverter using ultrathin layers of Rhenium Disulfide (ReS2) as the semiconducting channel. This ReS2 inverter was fabricated on a single micromechanically-exfoliated flake of ReS2. Electron beam lithography and physical vapor deposition were used to construct Cr/Au electrical contacts, an Alumina top-gate dielectric, and metal top-gate electrodes. By using both low (Aluminum) and high (Palladium) work-function metals as two separate top-gates on a single ReS2 flake, we create a dual-gated depletion mode (D-mode) and enhancement mode (E-mode) FETs in series. Both FETs displayed current saturation in the output characteristics as a result of the FET ``pinch-off'' mechanism and On/Off current ratios of 105. Field-effect mobilities of 23 and 17 cm2V-1s-1 and subthreshold swings of 97 and 551 mV/decade were calculated for the E-mode and D-mode FETs, respectively. With a supply voltage of 1V, at low/negative input voltages the inverter output was at a high logic state of 900 mV. Conversely with high/positive input voltages, the inverter output was at a low logic state of 500 mV. The inversion of the input signal demonstrates the potential for using ReS2 in future integrated circuit designs and the versatility of depletion-load logic devices for TMD research. NRI SWAN Center and ARL STTR Program.

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

NASA Astrophysics Data System (ADS)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is still necessary to understand what is intrinsic we can not change, or what is extrinsic one we can improve.

Effect of dual-dielectric hydrogen-diffusion barrier layers on the performance of low-temperature processed transparent InGaZnO thin-film transistors

NASA Astrophysics Data System (ADS)

Tari, Alireza; Wong, William S.

2018-02-01

Dual-dielectric SiOx/SiNx thin-film layers were used as back-channel and gate-dielectric barrier layers for bottom-gate InGaZnO (IGZO) thin-film transistors (TFTs). The concentration profiles of hydrogen, indium, gallium, and zinc oxide were analyzed using secondary-ion mass spectroscopy characterization. By implementing an effective H-diffusion barrier, the hydrogen concentration and the creation of H-induced oxygen deficiency (H-Vo complex) defects during the processing of passivated flexible IGZO TFTs were minimized. A bilayer back-channel passivation layer, consisting of electron-beam deposited SiOx on plasma-enhanced chemical vapor-deposition (PECVD) SiNx films, effectively protected the TFT active region from plasma damage and minimized changes in the chemical composition of the semiconductor layer. A dual-dielectric PECVD SiOx/PECVD SiNx gate-dielectric, using SiOx as a barrier layer, also effectively prevented out-diffusion of hydrogen atoms from the PECVD SiNx-gate dielectric to the IGZO channel layer during the device fabrication.

Ultrahigh near infrared photoresponsive organic field-effect transistors with lead phthalocyanine/C60 heterojunction on poly(vinyl alcohol) gate dielectric.

PubMed

Sun, Lei; Zhang, Jianping; Zhao, Feiyu; Luo, Xiao; Lv, Wenli; li, Yao; Ren, Qiang; Wen, Zhanwei; Peng, Yingquan; Liu, Xingyuan

2015-05-08

Performances of photoresponsive organic field-effect transistors (photOFETs) operating in the near infrared (NIR) region utilizing SiO2 as the gate dielectric is generally low due to low carrier mobility of the channel. We report on NIR photOFETs based on lead phthalocyanine (PbPc)/C60 heterojunction with ultrahigh photoresponsivity by utilizing poly(vinyl alcohol) (PVA) as the gate dielectric. For 808 nm NIR illumination of 1.69 mW cm(-2), an ultrahigh photoresponsivity of 21 A W(-1), and an external quantum efficiency of 3230% were obtained at a gate voltage of 30 V and a drain voltage of 80 V, which are 124 times and 126 times as large as the reference device with SiO2 as the gate dielectric, respectively. The ultrahigh enhancement of photoresponsivity is resulted from the huge increase of electron mobility of C60 film grown on PVA dielectric. AFM investigations revealed that the C60 film grown on PVA is much smooth and uniform and the grain size is much larger than that grown on SiO2 dielectric, which together results in four orders of magnitude increase of the field-effect electron mobility of C60 film.

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

NASA Astrophysics Data System (ADS)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

HIGH-k GATE DIELECTRIC: AMORPHOUS Ta/La2O3 FILMS GROWN ON Si AT LOW PRESSURE

NASA Astrophysics Data System (ADS)

Bahari, Ali; Khorshidi, Zahra

2014-09-01

In the present study, Ta/La2O3 films (La2O3 doped with Ta2O5) as a gate dielectric were prepared using a sol-gel method at low pressure. Ta/La2O3 film has some hopeful properties as a gate dielectric of logic device. The structure and morphology of Ta/La2O3 films were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). Electrical properties of films were performed using capacitance-voltage (C-V) and current density-voltage (J-V) measurements. The optical bandgap of samples was studied by UV-visible optical absorbance measurement. The optical bandgap, Eopt, is determined from the absorbance spectra. The obtained results show that Ta/La2O3 film as a good gate dielectric has amorphous structure, good thermal stability, high dielectric constant (≈ 25), low leakage current and wide bandgap (≈ 4.7 eV).

A low-frequency noise model with carrier generation-recombination process for pentacene organic thin-film transistor

NASA Astrophysics Data System (ADS)

Han, C. Y.; Qian, L. X.; Leung, C. H.; Che, C. M.; Lai, P. T.

2013-07-01

By including the generation-recombination process of charge carriers in conduction channel, a model for low-frequency noise in pentacene organic thin-film transistors (OTFTs) is proposed. In this model, the slope and magnitude of power spectral density for low-frequency noise are related to the traps in the gate dielectric and accumulation layer of the OTFT for the first time. The model can well fit the measured low-frequency noise data of pentacene OTFTs with HfO2 or HfLaO gate dielectric, which validates this model, thus providing an estimate on the densities of traps in the gate dielectric and accumulation layer. It is revealed that the traps in the accumulation layer are much more than those in the gate dielectric, and so dominate the low-frequency noise of pentacene OTFTs.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells

PubMed Central

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-01

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping. PMID:28336851

Nano-photonic structures for light trapping in ultra-thin crystalline silicon solar cells

DOE PAGES

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-13

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a densemore » mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. Furthermore, this architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.« less

Nano-photonic structures for light trapping in ultra-thin crystalline silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pathi, Prathap; Peer, Akshit; Biswas, Rana

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a densemore » mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. Furthermore, this architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.« less

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells.

PubMed

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-13

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%-2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm² photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors.

PubMed

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-04-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc 6 ) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO 2 ) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10 -2 cm 2 V -1 s -1 and 10 6 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

PubMed Central

Chaure, Nandu B; Cammidge, Andrew N; Chambrier, Isabelle; Cook, Michael J; Cain, Markys G; Murphy, Craig E; Pal, Chandana; Ray, Asim K

2011-01-01

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc6) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones. PMID:27877383

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors.

PubMed

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; Kisslinger, Kim; Stach, Eric A; Shahrjerdi, Davood

2017-07-25

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). Here, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increases proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. These findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

PubMed

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Energy-loss return gate via liquid dielectric polarization.

PubMed

Kim, Taehun; Yong, Hyungseok; Kim, Banseok; Kim, Dongseob; Choi, Dukhyun; Park, Yong Tae; Lee, Sangmin

2018-04-12

There has been much research on renewable energy-harvesting techniques. However, owing to increasing energy demands, significant energy-related issues remain to be solved. Efforts aimed at reducing the amount of energy loss in electric/electronic systems are essential for reducing energy consumption and protecting the environment. Here, we design an energy-loss return gate system that reduces energy loss from electric/electronic systems by utilizing the polarization of liquid dielectrics. The use of a liquid dielectric material in the energy-loss return gate generates electrostatic potential energy while reducing the dielectric loss of the electric/electronic system. Hence, an energy-loss return gate can make breakthrough impacts possible by amplifying energy-harvesting efficiency, lowering the power consumption of electronics, and storing the returned energy. Our study indicates the potential for enhancing energy-harvesting technologies for electric/electronics systems, while increasing the widespread development of these systems.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Early stage oxynitridation process of Si(001) surface by NO gas: Reactive molecular dynamics simulation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cao, Haining; Kim, Seungchul; Lee, Kwang-Ryeol, E-mail: krlee@kist.re.kr

2016-03-28

Initial stage of oxynitridation process of Si substrate is of crucial importance in fabricating the ultrathin gate dielectric layer of high quality in advanced MOSFET devices. The oxynitridation reaction on a relaxed Si(001) surface is investigated via reactive molecular dynamics (MD) simulation. A total of 1120 events of a single nitric oxide (NO) molecule reaction at temperatures ranging from 300 to 1000 K are statistically analyzed. The observed reaction kinetics are consistent with the previous experimental or calculation results, which show the viability of the reactive MD technique to study the NO dissociation reaction on Si. We suggest the reaction pathwaymore » for NO dissociation that is characterized by the inter-dimer bridge of a NO molecule as the intermediate state prior to NO dissociation. Although the energy of the inter-dimer bridge is higher than that of the intra-dimer one, our suggestion is supported by the ab initio nudged elastic band calculations showing that the energy barrier for the inter-dimer bridge formation is much lower. The growth mechanism of an ultrathin Si oxynitride layer is also investigated via consecutive NO reactions simulation. The simulation reveals the mechanism of self-limiting reaction at low temperature and the time evolution of the depth profile of N and O atoms depending on the process temperature, which would guide to optimize the oxynitridation process condition.« less

Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

2017-07-01

In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

Direct visualization and in-depth physical study of metal filament formation in percolated high-κ dielectrics

NASA Astrophysics Data System (ADS)

Li, X.; Pey, K. L.; Bosman, M.; Liu, W. H.; Kauerauf, T.

2010-01-01

The migration of Ta atoms from a transistor gate electrode into the percolated high-κ (HK) gate dielectrics is directly shown using transmission electron microscopy analysis. A nanoscale metal filament that formed under high current injection is identified to be the physical defect responsible for the ultrafast transient breakdown (BD) of the metal-gate/high-κ (MG/HK) gate stacks. This highly conductive metal filament poses reliability concerns for MG/HK gate stacks as it significantly reduces the post-BD reliability margin of a transistor.

Microwave Characterization of Ba-Substituted PZT and ZnO Thin Films.

PubMed

Tierno, Davide; Dekkers, Matthijn; Wittendorp, Paul; Sun, Xiao; Bayer, Samuel C; King, Seth T; Van Elshocht, Sven; Heyns, Marc; Radu, Iuliana P; Adelmann, Christoph

2018-05-01

The microwave dielectric properties of (Ba 0.1 Pb 0.9 )(Zr 0.52 Ti 0.48 )O 3 (BPZT) and ZnO thin films with thicknesses below were investigated. No significant dielectric relaxation was observed for both BPZT and ZnO up to 30 GHz. The intrinsic dielectric constant of BPZT was as high as 980 at 30 GHz. The absence of strong dielectric dispersion and loss peaks in the studied frequency range can be linked to the small grain diameters in these ultrathin films.

Interfacial fields in organic field-effect transistors and sensors

NASA Astrophysics Data System (ADS)

Dawidczyk, Thomas J.

Organic electronics are currently being commercialized and present a viable alternative to conventional electronics. These organic materials offer the ability to chemically manipulate the molecule, allowing for more facile mass processing techniques, which in turn reduces the cost. One application where organic semiconductors (OSCs) are being investigated is sensors. This work evaluates an assortment of n- and p-channel semiconductors as organic field-effect transistor (OFET) sensors. The sensor responses to dinitrotoluene (DNT) vapor and solid along with trinitrotoluene (TNT) solid were studied. Different semiconductor materials give different magnitude and direction of electrical current response upon exposure to DNT. Additional OFET parameters---mobility and threshold voltage---further refine the response to the DNT with each OFET sensor requiring a certain gate voltage for an optimized response to the vapor. The pattern of responses has sufficient diversity to distinguish DNT from other vapors. To effectively use these OFET sensors in a circuit, the threshold voltage needs to be tuned for each transistor to increase the efficiency of the circuit and maximize the sensor response. The threshold voltage can be altered by embedding charges into the dielectric layer of the OFET. To study the quantity and energy of charges needed to alter the threshold voltage, charge carriers were injected into polystyrene (PS) and investigated with scanning Kelvin probe microscopy (SKPM) and thermally stimulated discharge current (TSDC). Lateral heterojunctions of pentacene/PS were scanned using SKPM, effectively observing polarization along a side view of a lateral nonvolatile organic field-effect transistor dielectric interface. TSDC was used to observe charge migration out of PS films and to estimate the trap energy level inside the PS, using the initial rise method. The process was further refined to create lateral heterojunctions that were actual working OFETs, consisting of a PS or poly (3-trifluoro)styrene (F-PS) gate dielectric and a pentacene OSC. The charge storage inside the dielectric was visualized with SKPM, correlated to a threshold voltage shift in the transistor operation, and related to bias stress as well. The SKPM method allows the dielectric/OSC interface of the OFET to be visualized without any alteration of the OFET. Furthermore, this technique allows for the observation of charge distribution between the two dielectric interfaces, PS and F-PS. The SKPM is used to visualize the charge from conventional gate biasing and also as a result of embedding charges deliberately into the dielectric to shift the threshold voltage. Conventional gate biasing shows considerable residual charge in the PS dielectric, which results in gate bias stress. Gate bias stress is one of the major hurdles left in the commercialization of OFETs. To prevent this bias stress, additives of different energy levels were inserted into the dielectric to limit the gate bias stress. Additionally, the dielectrics were pre-charged to try and prevent further bias stress. Neither pre-charging the dielectric or the addition of additive has been used in gate bias prevention, but both methods offer improved resistance to gate bias stress, and help to further refine the dielectric design.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

A sextuple-band ultra-thin metamaterial absorber with perfect absorption

NASA Astrophysics Data System (ADS)

Yu, Dingwang; Liu, Peiguo; Dong, Yanfei; Zhou, Dongming; Zhou, Qihui

2017-08-01

This paper presents the design, simulation and measurement of a sextuple-band ultra-thin metamaterial absorber (MA). The unit cell of this proposed structure is composed of triangular spiral-shaped complementary structures imprinted on the dielectric substrate backed by a metal ground. The measured results are in good agreement with simulations with high absorptivities of more than 90% at all six absorption frequencies. In addition, this proposed absorber has good performances of ultra-thin, polarization insensitivity and a wide-angle oblique incidence, which can easily be used in many potential applications such as detection, imaging and sensing.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

NASA Astrophysics Data System (ADS)

Lagger, P.; Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J.; Pogany, D.; Ostermaier, C.

2014-07-01

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Comparison of conductor and dielectric inks in printed organic complementary transistors

NASA Astrophysics Data System (ADS)

Ng, Tse Nga; Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Abraham, Biby; Wu, Yiliang; Veres, Janos

2014-10-01

Two types of printable conductor and a bilayer gate dielectric are evaluated for use in all-additive, inkjetprinted complementary OTFTs. The Ag nanoparticle ink based on nonpolar alkyl amine surfactant or stabilizer enables good charge injection into p-channel devices, but this ink also leaves residual stabilizer that modifies the transistor backchannel and shifts the turn-on voltage to negative values. The Ag ink based on polar solvent requires dopant modification to improve charge injection to p-channel devices, but this ink allows the OTFT turn-on voltage to be close to 0 V. The reverse trend is observed for n-channel OTFTs. For gate insulator, a bilayer dielectric is demonstrated that combines the advantages of two types of insulator materials, in which a fluoropolymer reduces dipolar disorder at the semiconductor-dielectric interface, while a high-k PVDF terpolymer dielectric facilitates high gate capacitance. The dielectric is incorporated into an inverter and a three-stage ring oscillator, and the resulting circuits were demonstrated to operate at a supply voltage as low as 2 V, with bias stress levels comparable to circuits with other types of dielectrics.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

FAST TRACK COMMUNICATION High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Xia, D. X.; Xu, J. B.

2010-11-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm2 V-1 s-1 and 2.1 cm2 V-1 s-1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics.

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE PAGES

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; ...

2017-06-21

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

All 2D, high mobility, flexible, transparent thin film transistor

DOEpatents

Das, Saptarshi; Sumant, Anirudha V.; Roelofs, Andreas

2017-01-17

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

Electrical properties of spin coated ultrathin titanium oxide films on GaAs

NASA Astrophysics Data System (ADS)

Dutta, Shankar; Pal, Ramjay; Chatterjee, Ratnamala

2015-04-01

In recent years, ultrathin (<50 nm) metal oxide films have been being extensively studied as high-k dielectrics for future metal oxide semiconductor (MOS) technology. This paper discusses deposition of ultrathin TiO2 films (˜10 nm) on GaAs substrates (one sulfur-passivated, another unpassivated) by spin coating technique. The sulfur passivation is done to reduce the surface states of GaAs substrate. After annealing at 400 °C in a nitrogen environment, the TiO2 films are found to be polycrystalline in nature with rutile phase. The TiO2 films exhibit consistent grain size of 10-20 nm with thickness around 10-12 nm. Dielectric constants of the films are found to be 65.4 and 47.1 corresponding to S-passivated and unpassivated substrates, respectively. Corresponding threshold voltages of the MOS structures are measured to be -0.1 V to -0.3 V for the S-passivated and unpassivated samples, respectively. The S-passivated TiO2 film showed improved (lower) leakage current density (5.3 × 10-4 A cm-2 at 3 V) compared to the unpassivated film (1.8 × 10-3 A/cm2 at 3 V). Dielectric breakdown-field of the TiO2 films on S-passivated and unpassivated GaAs samples are found to be 8.4 MV cm-1 and 7.2 MV cm-1 respectively.

Critical current enhancement driven by suppression of superconducting fluctuation in ion-gated ultrathin FeSe

NASA Astrophysics Data System (ADS)

Harada, T.; Shiogai, J.; Miyakawa, T.; Nojima, T.; Tsukazaki, A.

2018-05-01

The framework of phase transition, such as superconducting transition, occasionally depends on the dimensionality of materials. Superconductivity is often weakened in the experimental conditions of two-dimensional thin films due to the fragile superconducting state against defects and interfacial effects. In contrast to this general trend, superconductivity in the thin limit of FeSe exhibits an opposite trend, such as an increase in critical temperature (T c) and the superconducting gap exceeding the bulk values; however, the dominant mechanism is still under debate. Here, we measured thickness-dependent electrical transport properties of the ion-gated FeSe thin films to evaluate the superconducting critical current (I c) in the ultrathin FeSe. Upon systematically decreasing the FeSe thickness by the electrochemical etching technique in the Hall bar-shaped electric double-layer transistors, we observed a dramatic enhancement of I c reaching about 10 mA and corresponding to about 107 A cm‑2 in the thinnest condition. By analyzing the transition behavior, we clarify that the suppressed superconducting fluctuation is one of the origins of the large I c in the ion-gated ultrathin FeSe films. These results indicate the existence of a robust superconducting state possibly with dense Cooper pairs at the thin limit of FeSe.

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

NASA Astrophysics Data System (ADS)

Kumar, Narendra; Sutradhar, Moitri; Kumar, Jitendra; Panda, Siddhartha

2017-03-01

The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ˜25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of C top/C bottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH-1, which is about 6.8 times the Nernst limit (59 mV pH-1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (˜2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Electric-field control of magnetic domain-wall velocity in ultrathin cobalt with perpendicular magnetization.

PubMed

Chiba, D; Kawaguchi, M; Fukami, S; Ishiwata, N; Shimamura, K; Kobayashi, K; Ono, T

2012-06-06

Controlling the displacement of a magnetic domain wall is potentially useful for information processing in magnetic non-volatile memories and logic devices. A magnetic domain wall can be moved by applying an external magnetic field and/or electric current, and its velocity depends on their magnitudes. Here we show that the applying an electric field can change the velocity of a magnetic domain wall significantly. A field-effect device, consisting of a top-gate electrode, a dielectric insulator layer, and a wire-shaped ferromagnetic Co/Pt thin layer with perpendicular anisotropy, was used to observe it in a finite magnetic field. We found that the application of the electric fields in the range of ± 2-3 MV cm(-1) can change the magnetic domain wall velocity in its creep regime (10(6)-10(3) m s(-1)) by more than an order of magnitude. This significant change is due to electrical modulation of the energy barrier for the magnetic domain wall motion.

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minohara, M.; Hikita, Y.; Bell, C.

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE PAGES

Minohara, M.; Hikita, Y.; Bell, C.; ...

2017-08-25

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Morphology and electronic transport of polycrystalline pentacene thin-film transistors

NASA Astrophysics Data System (ADS)

Knipp, D.; Street, R. A.; Völkel, A. R.

2003-06-01

Temperature-dependent measurements of thin-film transistors were performed to gain insight in the electronic transport of polycrystalline pentacene. Devices were fabricated with plasma-enhanced chemical vapor deposited silicon nitride gate dielectrics. The influence of the dielectric roughness and the deposition temperature of the thermally evaporated pentacene films were studied. Although films on rougher gate dielectrics and films prepared at low deposition temperatures exhibit similar grain size, the electronic properties are different. Increasing the dielectric roughness reduces the free carrier mobility, while low substrate temperature leads to more and deeper hole traps.

High kappa Dielectrics on InGaAs and GaN - Growth, Interfacial Structural Studies, and Surface Fermi Level Unpinning

DTIC Science & Technology

2011-04-20

ALD-Al2O3 and in-situ MBE-Al2O3/ Ga2O3 (Gd2O3) [GGO] as the gate dielectrics. The advances of the InGaAs MOSFETs achieved will enable future CMOS...and GaN MOSFETs:  High-performance self-aligned inversion-channel In0.53Ga0.47As and In0.75Ga0.25As MOSFET’s with Al2O3/ Ga2O3 (Gd2O3) as gate... Ga2O3 (Gd2O3) as gate dielectrics Key accomplishments in devices of 1m gate length: High drain current of 1.23 mA/m High transcoductance of 714

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

NASA Astrophysics Data System (ADS)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Ultrathin free-standing graphene oxide film based flexible touchless sensor

NASA Astrophysics Data System (ADS)

Liu, Lin; Wang, Yingyi; Li, Guanghui; Qin, Sujie; Zhang, Ting

2018-01-01

Ultrathin free-standing graphene oxide (GO) films were fabricated by vacuum filtration method assisted with Ni(OH)2 nanosheets as the sacrifice layer. The surface of the obtained GO film is very clean as the Ni(OH)2 nanosheets can be thoroughly etched by HCl. The thickness of the GO films can be well-controlled by changing the volume of GO dispersion, and the thinnest GO film reached ~12 nm. As a novel and transparent dielectric material, the GO film has been applied as the dielectric layer for the flexible touchless capacitive sensor which can effectively distinguish the approaching of an insulator or a conductor. Project supported by the National Natural Science Foundation of China (No. 61574163) and the Foundation Research Project of Jiangsu Province (Nos. BK20160392, BK20170008).

Method of doping organic semiconductors

DOEpatents

Kloc,; Christian Leo; Ramirez; Arthur Penn; So, Woo-Young

2010-10-26

An apparatus has a crystalline organic semiconducting region that includes polyaromatic molecules. A source electrode and a drain electrode of a field-effect transistor are both in contact with the crystalline organic semiconducting region. A gate electrode of the field-effect transistor is located to affect the conductivity of the crystalline organic semiconducting region between the source and drain electrodes. A dielectric layer of a first dielectric that is substantially impermeable to oxygen is in contact with the crystalline organic semiconducting region. The crystalline organic semiconducting region is located between the dielectric layer and a substrate. The gate electrode is located on the dielectric layer. A portion of the crystalline organic semiconducting region is in contact with a second dielectric via an opening in the dielectric layer. A physical interface is located between the second dielectric and the first dielectric.

Enhancement of absorption and color contrast in ultra-thin highly absorbing optical coatings

NASA Astrophysics Data System (ADS)

Kats, Mikhail A.; Byrnes, Steven J.; Blanchard, Romain; Kolle, Mathias; Genevet, Patrice; Aizenberg, Joanna; Capasso, Federico

2013-09-01

Recently a new class of optical interference coatings was introduced which comprises ultra-thin, highly absorbing dielectric layers on metal substrates. We show that these lossy coatings can be augmented by an additional transparent subwavelength layer. We fabricated a sample comprising a gold substrate, an ultra-thin film of germanium with a thickness gradient, and several alumina films. The experimental reflectivity spectra showed that the additional alumina layer increases the color range that can be obtained, in agreement with calculations. More generally, this transparent layer can be used to enhance optical absorption, protect against erosion, or as a transparent electrode for optoelectronic devices.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.

2001-06-11

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSGmore » oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. {copyright} 2001 American Institute of Physics.« less

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO₂ Gate Dielectrics by CF₄ Plasma Treatment.

PubMed

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-05-17

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO₂ gate insulator and CF₄ plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO₂ gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm²/V∙s (without treatment) to 54.6 cm²/V∙s (with CF₄ plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO₂ gate dielectric has also been improved by the CF₄ plasma treatment. By applying the CF₄ plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device's immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF₄ plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO₂ gate dielectric, but also enhances the device's reliability.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

Fluorinated graphene as high performance dielectric materials and the applications for graphene nanoelectronics.

PubMed

Ho, Kuan-I; Huang, Chi-Hsien; Liao, Jia-Hong; Zhang, Wenjing; Li, Lain-Jong; Lai, Chao-Sung; Su, Ching-Yuan

2014-07-31

There is broad interest in surface functionalization of 2D materials and its related applications. In this work, we present a novel graphene layer transistor fabricated by introducing fluorinated graphene (fluorographene), one of the thinnest 2D insulator, as the gate dielectric material. For the first time, the dielectric properties of fluorographene, including its dielectric constant, frequency dispersion, breakdown electric field and thermal stability, were comprehensively investigated. We found that fluorographene with extremely thin thickness (5 nm) can sustain high resistance at temperature up to 400 °C. The measured breakdown electric field is higher than 10 MV cm(-1), which is the heightest value for dielectric materials in this thickness. Moreover, a proof-of-concept methodology, one-step fluorination of 10-layered graphene, is readily to obtain the fluorographene/graphene heterostructures, where the top-gated transistor based on this structure exhibits an average carrier mobility above 760 cm(2)/Vs, higher than that obtained when SiO₂ and GO were used as gate dielectric materials. The demonstrated fluorographene shows excellent dielectric properties with fast and scalable processing, providing a universal applications for the integration of versatile nano-electronic devices.

Fluorinated Graphene as High Performance Dielectric Materials and the Applications for Graphene Nanoelectronics

PubMed Central

Ho, Kuan-I; Huang, Chi-Hsien; Liao, Jia-Hong; Zhang, Wenjing; Li, Lain-Jong; Lai, Chao-Sung; Su, Ching-Yuan

2014-01-01

There is broad interest in surface functionalization of 2D materials and its related applications. In this work, we present a novel graphene layer transistor fabricated by introducing fluorinated graphene (fluorographene), one of the thinnest 2D insulator, as the gate dielectric material. For the first time, the dielectric properties of fluorographene, including its dielectric constant, frequency dispersion, breakdown electric field and thermal stability, were comprehensively investigated. We found that fluorographene with extremely thin thickness (5 nm) can sustain high resistance at temperature up to 400°C. The measured breakdown electric field is higher than 10 MV cm−1, which is the heightest value for dielectric materials in this thickness. Moreover, a proof-of-concept methodology, one-step fluorination of 10-layered graphene, is readily to obtain the fluorographene/graphene heterostructures, where the top-gated transistor based on this structure exhibits an average carrier mobility above 760 cm2/Vs, higher than that obtained when SiO2 and GO were used as gate dielectric materials. The demonstrated fluorographene shows excellent dielectric properties with fast and scalable processing, providing a universal applications for the integration of versatile nano-electronic devices. PMID:25081226

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

High efficient light absorption and nanostructure-dependent birefringence of a metal-dielectric symmetrical layered structure

NASA Astrophysics Data System (ADS)

Jen, Yi-Jun; Jhang, Yi-Ciang; Liu, Wei-Chih

2017-08-01

A multilayer that comprises ultra-thin metal and dielectric films has been investigated and applied as a layered metamaterial. By arranging metal and dielectric films alternatively and symmetrically, the equivalent admittance and refractive index can be tailored separately. The tailored admittance and refractive index enable us to design optical filters with more flexibility. The admittance matching is achieved via the admittance tracing in the normalized admittance diagram. In this work, an ultra-thin light absorber is designed as a multilayer composed of one or several cells. Each cell is a seven-layered film stack here. The design concept is to have the extinction as large as possible under the condition of admittance matching. For a seven-layered symmetrical film stack arranged as Ta2O5 (45 nm)/ a-Si (17 nm)/ Cr (30 nm)/ Al (30 nm)/ Cr (30 nm)/ a-Si (17 nm)/ Ta2O5 (45 nm), its mean equivalent admittance and extinction coefficient over the visible regime is 1.4+0.2i and 2.15, respectively. The unit cell on a transparent BK7 glass substrate absorbs 99% of normally incident light energy for the incident medium is glass. On the other hand, a transmission-induced metal-dielectric film stack is investigated by using the admittance matching method. The equivalent anisotropic property of the metal-dielectric multilayer varied with wavelength and nanostructure are investigated here.

Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

NASA Astrophysics Data System (ADS)

Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

2011-07-01

We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

Magneto-optical Kerr rotation and color in ultrathin lossy dielectric

NASA Astrophysics Data System (ADS)

Zhang, Jing; Wang, Hai; Qu, Xin; Zhou, Yun song; Li, Li na

2017-05-01

Ultra-thin optical coating comprising nanometer-thick silicon absorbing films on iron substrates can display strong optical interference effects. A resonance peak of ∼1.6^\\circ longitudinal Kerr rotation with the silicon thickness of ∼47 \\text{nm} was found at the wavelength of 660 nm. The optical properties of silicon thin films were well controlled by the sputtering power. Non-iridescence color exhibition and Kerr rotation enhancement can be manipulated and encoded individually.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Tao; Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016; Xu, Ruimin

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectricmore » constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.« less

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Xu, Wangying; Dai, Mingzhi; Liang, Lingyan; Liu, Zhimin; Sun, Xilian; Wan, Qing; Cao, Hongtao

2012-05-01

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

Threshold Voltage Instability in A-Si:H TFTS and the Implications for Flexible Displays and Circuits

DTIC Science & Technology

2008-12-01

and negative gate voltages with and without elevated drain voltages for FDC TFTs. Extending techniques used to localize hot electron degradation...in MOSFETs, experiments in our lab have localized the degradation of a-Si:H to the gate dielectric/a-Si:H channel interface [Shringarpure, et al...saturation, increased drain source current measured with the source and drain reversed indicates localization of ΔVth to the gate dielectric/amorphous

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Jong Woo; Nathan, Arokia, E-mail: an299@cam.ac.uk; Barquinha, Pedro

2016-08-15

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (V{sub TH}) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarizationmore » density. The second type of anomaly is negative V{sub TH} shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H{sub 2}O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.« less

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Low leakage current gate dielectrics prepared by ion beam assisted deposition for organic thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Chang Su; Jo, Sung Jin; Kim, Jong Bok; Ryu, Seung Yoon; Noh, Joo Hyon; Baik, Hong Koo; Lee, Se Jong; Kim, Youn Sang

2007-12-01

This communication reports on the fabrication of low operating voltage pentacene thin-film transistors with high-k gate dielectrics by ion beam assisted deposition (IBAD). These densely packed dielectric layers by IBAD show a much lower level of leakage current than those created by e-beam evaporation. These results, from the fact that those thin films deposited with low adatom mobility, have an open structure, consisting of spherical grains with pores in between, that acts as a significant path for leakage current. By contrast, our results demonstrate the potential to limit this leakage. The field effect mobility, on/off current ratio, and subthreshold slope obtained from pentacene thin-film transistors (TFTs) were 1.14 cm2/V s, 105, and 0.41 V/dec, respectively. Thus, the high-k gate dielectrics obtained by IBAD show promise in realizing low leakage current, low voltage, and high mobility pentacene TFTs.

Broadening of Distribution of Trap States in PbS Quantum Dot Field-Effect Transistors with High-k Dielectrics

PubMed Central

2017-01-01

We perform a quantitative analysis of the trap density of states (trap DOS) in PbS quantum dot field-effect transistors (QD-FETs), which utilize several polymer gate insulators with a wide range of dielectric constants. With increasing gate dielectric constant, we observe increasing trap DOS close to the lowest unoccupied molecular orbital (LUMO) of the QDs. In addition, this increase is also consistently followed by broadening of the trap DOS. We rationalize that the increase and broadening of the spectral trap distribution originate from dipolar disorder as well as polaronic interactions, which are appearing at strong dielectric polarization. Interestingly, the increased polaron-induced traps do not show any negative effect on the charge carrier mobility in our QD devices at the highest applied gate voltage, giving the possibility to fabricate efficient low-voltage QD devices without suppressing carrier transport. PMID:28084725

Materials properties of hafnium and zirconium silicates: Metal interdiffusion and dopant penetration studies

NASA Astrophysics Data System (ADS)

Quevedo Lopez, Manuel Angel

Hafnium and Zirconium based gate dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in CMOS processing. Furthermore, the addition of nitrogen into this pseudo-binary alloy has been shown to improve their thermal stability, electrical properties, and reduce dopant penetration. Because CMOS processing requires high temperature anneals (up to 1050°C), it is important to understand the diffusion properties of any metal associated with the gate dielectric in silicon at these temperatures. In addition, dopant penetration from the doped polysilicon gate into the Si channel at these temperatures must also be studied. Impurity outdiffusion (Hf, Zr) from the dielectric, or dopant (B, As, P) penetration through the dielectric into the channel region would likely result in deleterious effects upon the carrier mobility. In this dissertation extensive thermal stability studies of alternate gate dielectric candidates ZrSixOy and HfSixO y are presented. Dopant penetration studies from doped-polysilicon through HfSixOy and HfSixOyNz are also presented. Rutherford Backscattering Spectroscopy (RBS), Heavy Ion RBS (HI-RBS), X-ray Photoelectron Spectroscopy (XPS), High Resolution Transmission Electron Microscopy (HR-TEM), and Time of Flight and Dynamic Secondary Ion Mass Spectroscopy (ToF-SIMS, D-SIMS) methods were used to characterize these materials. The dopant diffusivity is calculated by modeling of the dopant profiles in the Si substrate. In this disseration is reported that Hf silicate films are more stable than Zr silicate films, from the metal interdiffusion point of view. On the other hand, dopant (B, As, and P) penetration is observed for HfSixO y films. However, the addition of nitrogen to the Hf - Si - O systems improves the dopant penetration properties of the resulting HfSi xOyNz films.

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

PubMed Central

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Electric field effect on exchange interaction in ultrathin Co films with ionic liquids

NASA Astrophysics Data System (ADS)

Ishibashi, Mio; Yamada, Kihiro T.; Shiota, Yoichi; Ando, Fuyuki; Koyama, Tomohiro; Kakizakai, Haruka; Mizuno, Hayato; Miwa, Kazumoto; Ono, Shimpei; Moriyama, Takahiro; Chiba, Daichi; Ono, Teruo

2018-06-01

Electric-field modulations of magnetic properties have been extensively studied not only for practical applications but also for fundamental interest. In this study, we investigated the electric field effect on the exchange interaction in ultrathin Co films with ionic liquids. The exchange coupling J was characterized from the direct magnetization measurement as a function of temperature using Pt/ultrathin Co/MgO structures. The trend of the electric field effect on J is in good agreement with that of the theoretical prediction, and a large change in J by applying a gate voltage was observed by forming an electric double layer using ionic liquids.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

NASA Astrophysics Data System (ADS)

Kojima, Eiji; Chokawa, Kenta; Shirakawa, Hiroki; Araidai, Masaaki; Hosoi, Takuji; Watanabe, Heiji; Shiraishi, Kenji

2018-06-01

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena, E-mail: vmisra@ncsu.edu

2015-06-15

Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps withmore » a variety of ALD dielectrics. High-k dielectrics (HfO{sub 2}, HfAlO, and Al{sub 2}O{sub 3}) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO{sub 2} shows the lowest interface trap density (<2 × 10{sup 12 }cm{sup −2}) after annealing above 600 °C in N{sub 2} for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.« less

Hybrid nanomembrane-based capacitors for the determination of the dielectric constant of semiconducting molecular ensembles.

PubMed

Petrini, Paula A; Silva, Ricardo M L; de Oliveira, Rafael F; Merces, Leandro; Bof Bufon, Carlos C

2018-06-29

Considerable advances in the field of molecular electronics have been achieved over the recent years. One persistent challenge, however, is the exploitation of the electronic properties of molecules fully integrated into devices. Typically, the molecular electronic properties are investigated using sophisticated techniques incompatible with a practical device technology, such as the scanning tunneling microscopy. The incorporation of molecular materials in devices is not a trivial task as the typical dimensions of electrical contacts are much larger than the molecular ones. To tackle this issue, we report on hybrid capacitors using mechanically-compliant nanomembranes to encapsulate ultrathin molecular ensembles for the investigation of molecular dielectric properties. As the prototype material, copper (II) phthalocyanine (CuPc) has been chosen as information on its dielectric constant (k CuPc ) at the molecular scale is missing. Here, hybrid nanomembrane-based capacitors containing metallic nanomembranes, insulating Al 2 O 3 layers, and the CuPc molecular ensembles have been fabricated and evaluated. The Al 2 O 3 is used to prevent short circuits through the capacitor plates as the molecular layer is considerably thin (<30 nm). From the electrical measurements of devices with molecular layers of different thicknesses, the CuPc dielectric constant has been reliably determined (k CuPc  = 4.5 ± 0.5). These values suggest a mild contribution of the molecular orientation on the CuPc dielectric properties. The reported nanomembrane-based capacitor is a viable strategy for the dielectric characterization of ultrathin molecular ensembles integrated into a practical, real device technology.

Hybrid nanomembrane-based capacitors for the determination of the dielectric constant of semiconducting molecular ensembles

NASA Astrophysics Data System (ADS)

Petrini, Paula A.; Silva, Ricardo M. L.; de Oliveira, Rafael F.; Merces, Leandro; Bof Bufon, Carlos C.

2018-06-01

Considerable advances in the field of molecular electronics have been achieved over the recent years. One persistent challenge, however, is the exploitation of the electronic properties of molecules fully integrated into devices. Typically, the molecular electronic properties are investigated using sophisticated techniques incompatible with a practical device technology, such as the scanning tunneling microscopy. The incorporation of molecular materials in devices is not a trivial task as the typical dimensions of electrical contacts are much larger than the molecular ones. To tackle this issue, we report on hybrid capacitors using mechanically-compliant nanomembranes to encapsulate ultrathin molecular ensembles for the investigation of molecular dielectric properties. As the prototype material, copper (II) phthalocyanine (CuPc) has been chosen as information on its dielectric constant (k CuPc) at the molecular scale is missing. Here, hybrid nanomembrane-based capacitors containing metallic nanomembranes, insulating Al2O3 layers, and the CuPc molecular ensembles have been fabricated and evaluated. The Al2O3 is used to prevent short circuits through the capacitor plates as the molecular layer is considerably thin (<30 nm). From the electrical measurements of devices with molecular layers of different thicknesses, the CuPc dielectric constant has been reliably determined (k CuPc = 4.5 ± 0.5). These values suggest a mild contribution of the molecular orientation on the CuPc dielectric properties. The reported nanomembrane-based capacitor is a viable strategy for the dielectric characterization of ultrathin molecular ensembles integrated into a practical, real device technology.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics.

PubMed

Alshammari, Fwzah H; Nayak, Pradipta K; Wang, Zhenwei; Alshareef, Husam N

2016-09-07

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm(2) V(-1) s(-1), but increased to 13.3 cm(2) V(-1) s(-1) using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance.

Interface and gate bias dependence responses of sensing organic thin-film transistors.

PubMed

Tanese, Maria Cristina; Fine, Daniel; Dodabalapur, Ananth; Torsi, Luisa

2005-11-15

The effects of the exposure of organic thin-film transistors, comprising different organic semiconductors and gate dielectrics, to 1-pentanol are investigated. The transistor sensors exhibited an increase or a decrease of the transient source-drain current in the presence of the analyte, most likely as a result of a trapping or of a doping process of the organic active layer. The occurrence of these two effects, that can also coexist, depend on the gate-dielectric/organic semiconductor interface and on the applied gate field. Evidence of a systematic and sizable response enhancement for an OTFT sensor operated in the enhanced mode is also presented.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

NASA Astrophysics Data System (ADS)

Sharma, Dheeraj; Singh, Deepika; Pandey, Sunil; Yadav, Shivendra; Kondekar, P. N.

2017-11-01

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

NASA Astrophysics Data System (ADS)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Label Free Detection of Biomolecules Using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET

NASA Astrophysics Data System (ADS)

Wadhwa, Girish; Raj, Balwinder

2018-05-01

Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.

Acoustic Phonons and Mechanical Properties of Ultra-Thin Porous Low-k Films: A Surface Brillouin Scattering Study

NASA Astrophysics Data System (ADS)

Zizka, J.; King, S.; Every, A.; Sooryakumar, R.

2018-04-01

To reduce the RC (resistance-capacitance) time delay of interconnects, a key development of the past 20 years has been the introduction of porous low-k dielectrics to replace the traditional use of SiO2. Moreover, in keeping pace with concomitant reduction in technology nodes, these low-k materials have reached thicknesses below 100 nm wherein the porosity becomes a significant fraction of the film volume. The large degree of porosity not only reduces mechanical strength of the dielectric layer but also renders a need for non-destructive approaches to measure the mechanical properties of such ultra-thin films within device configurations. In this study, surface Brillouin scattering (SBS) is utilized to determine the elastic constants, Poisson's ratio, and Young's modulus of these porous low-k SiOC:H films (˜ 25-250 nm thick) grown on Si substrates by probing surface acoustic phonons and their dispersions.

Conformal surface plasmons propagating on ultrathin and flexible films

PubMed Central

Shen, Xiaopeng; Cui, Tie Jun; Martin-Cano, Diego; Garcia-Vidal, Francisco J.

2013-01-01

Surface plasmon polaritons (SPPs) are localized surface electromagnetic waves that propagate along the interface between a metal and a dielectric. Owing to their inherent subwavelength confinement, SPPs have a strong potential to become building blocks of a type of photonic circuitry built up on 2D metal surfaces; however, SPPs are difficult to control on curved surfaces conformably and flexibly to produce advanced functional devices. Here we propose the concept of conformal surface plasmons (CSPs), surface plasmon waves that can propagate on ultrathin and flexible films to long distances in a wide broadband range from microwave to mid-infrared frequencies. We present the experimental realization of these CSPs in the microwave regime on paper-like dielectric films with a thickness 600-fold smaller than the operating wavelength. The flexible paper-like films can be bent, folded, and even twisted to mold the flow of CSPs. PMID:23248311

Ultrathin microwave absorber based on metamaterial

NASA Astrophysics Data System (ADS)

Kim, Y. J.; Yoo, Y. J.; Hwang, J. S.; Lee, Y. P.

2016-11-01

We suggest that ultrathin broadband metamaterial is a perfect absorber in the microwave regime by utilizing the properties of a resistive sheet and metamaterial. Meta-atoms are composed of four-leaf clover-shape metallic patterns and a metal plane separated by three intermediate resistive sheet layers between four dielectric layers. We interpret the absorption mechanism of the broadband by using the distribution of surface currents at specific frequencies. The simulated absorption was over 99% in 1.8-4.2 GHz. The corresponding experimental absorption was also over 99% in 2.62-4.2 GHz; however, the absorption was slightly lower than 99% in 1.8-2.62 GHz because of the sheet resistance and the changed values for the dielectric constant. Furthermore, it is independent of incident angle. The results of this research indicate the possibility of applications, due to the suppression of noxious exposure, in cell phones, computers and microwave equipments.

Acoustic Phonons and Mechanical Properties of Ultra-Thin Porous Low- k Films: A Surface Brillouin Scattering Study

NASA Astrophysics Data System (ADS)

Zizka, J.; King, S.; Every, A.; Sooryakumar, R.

2018-07-01

To reduce the RC (resistance-capacitance) time delay of interconnects, a key development of the past 20 years has been the introduction of porous low- k dielectrics to replace the traditional use of SiO2. Moreover, in keeping pace with concomitant reduction in technology nodes, these low- k materials have reached thicknesses below 100 nm wherein the porosity becomes a significant fraction of the film volume. The large degree of porosity not only reduces mechanical strength of the dielectric layer but also renders a need for non-destructive approaches to measure the mechanical properties of such ultra-thin films within device configurations. In this study, surface Brillouin scattering (SBS) is utilized to determine the elastic constants, Poisson's ratio, and Young's modulus of these porous low- k SiOC:H films (˜ 25-250 nm thick) grown on Si substrates by probing surface acoustic phonons and their dispersions.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

PubMed

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

NASA Astrophysics Data System (ADS)

Chatterjee, Sulagna; Chattopadhyay, Sanatan

2016-10-01

An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La2O3 and TiO2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires.

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

NASA Astrophysics Data System (ADS)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

High-κ/Metal Gate Science and Technology

NASA Astrophysics Data System (ADS)

Guha, Supratik; Narayanan, Vijay

2009-08-01

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss some of the key materials issues that complicated the introduction of high-κ dielectrics, including reduced electron mobility, oxygen-based thermal instabilities, and the absence of thermally stable dual-metal electrodes. We show that through a combination of materials innovations and engineering ingenuity these issues were successfully overcome, thereby paving the way for high-κ/metal gate implementation.

Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and On/Off Ratio.

PubMed

Oh, Gwangtaek; Kim, Jin-Soo; Jeon, Ji Hoon; Won, EunA; Son, Jong Wan; Lee, Duk Hyun; Kim, Cheol Kyeom; Jang, Jingon; Lee, Takhee; Park, Bae Ho

2015-07-28

High-quality channel layer is required for next-generation flexible electronic devices. Graphene is a good candidate due to its high carrier mobility and unique ambipolar transport characteristics but typically shows a low on/off ratio caused by gapless band structure. Popularly investigated organic semiconductors, such as pentacene, suffer from poor carrier mobility. Here, we propose a graphene/pentacene channel layer with high-k ion-gel gate dielectric. The graphene/pentacene device shows both high on/off ratio and carrier mobility as well as excellent mechanical flexibility. Most importantly, it reveals ambipolar behaviors and related negative differential resistance, which are controlled by external bias. Therefore, our graphene/pentacene barristor with ion-gel gate dielectric can offer various flexible device applications with high performances.

Solution processed flexible organic thin film back-gated transistors based on polyimide dielectric films

NASA Astrophysics Data System (ADS)

Park, Janghoon; Min, Yoonki; Lee, Dongjin

2018-04-01

An organic thin film back-gated transistor (OBGT) was fabricated and characterized. The gate electrode was printed on the back side of substrate, and the dielectric layer was omitted by substituting the dielectric layer with the polyimide (PI) film substrate. Roll-to-roll (R2R) gravure printing, doctor blading, and drop casting methods were used to fabricate the OBGT. The printed OBGT device shows better performance compared with an OTFT device based on dielectric layer of BaTiO3. Additionally, a calendering process enhanced the performance by a factor of 3 to 7 (mobility: 0.016 cm2/V.s, on/off ratio: 9.17×103). A bending test was conducted to confirm the flexibility and durability of the OBGT device. The results show the fabricated device endures 20000-cyclic motions. The realized OBGT device was successfully fabricated and working, which is meaningful for production engineering from the viewpoint of process development.

High-performance pentacene OTFT by incorporating Ti in LaON gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Y. X.; Han, C. Y.; Tang, W. M.; Lai, P. T.

2017-07-01

Pentacene organic thin-film transistors (OTFT) using high-k LaTiON gate dielectric with different Ti contents are investigated. The LaxTi(1-x)ON films (with x = 1, 0.87, 0.76, and 0.67) are deposited by reactive sputtering followed by an annealing in N2 at 200 °C. The OTFT with La0.87Ti0.13ON can achieve a high carrier mobility of 2.6 cm2/V.s, a small threshold voltage of -1.5 V, a small sub-threshold swing of 0.07 V/dec, and a small hysteresis of 0.17 V. AFM and X-ray photoelectron spectroscopy reveal that Ti can suppress the hygroscopicity of La oxide to achieve a smoother dielectric surface, which can result in larger pentacene grains and thus higher carrier mobility. All the devices show a clockwise hysteresis because both the LaOH formation and Ti incorporation can generate acceptor-like traps in the gate dielectric.

Intrinsic Electron Mobility Exceeding 10³ cm²/(V s) in Multilayer InSe FETs.

PubMed

Sucharitakul, Sukrit; Goble, Nicholas J; Kumar, U Rajesh; Sankar, Raman; Bogorad, Zachary A; Chou, Fang-Cheng; Chen, Yit-Tsong; Gao, Xuan P A

2015-06-10

Graphene-like two-dimensional (2D) materials not only are interesting for their exotic electronic structure and fundamental electronic transport or optical properties but also hold promises for device miniaturization down to atomic thickness. As one material belonging to this category, InSe, a III-VI semiconductor, not only is a promising candidate for optoelectronic devices but also has potential for ultrathin field effect transistor (FET) with high mobility transport. In this work, various substrates such as PMMA, bare silicon oxide, passivated silicon oxide, and silicon nitride were used to fabricate multilayer InSe FET devices. Through back gating and Hall measurement in four-probe configuration, the device's field effect mobility and intrinsic Hall mobility were extracted at various temperatures to study the material's intrinsic transport behavior and the effect of dielectric substrate. The sample's field effect and Hall mobilities over the range of 20-300 K fall in the range of 0.1-2.0 × 10(3) cm(2)/(V s), which are comparable or better than the state of the art FETs made of widely studied 2D transition metal dichalcogenides.

Electron tunneling through atomically flat and ultrathin hexagonal boron nitride

NASA Astrophysics Data System (ADS)

Lee, Gwan-Hyoung; Yu, Young-Jun; Lee, Changgu; Dean, Cory; Shepard, Kenneth L.; Kim, Philip; Hone, James

2011-12-01

Electron tunneling through atomically flat and ultrathin hexagonal boron nitride (h-BN) on gold-coated mica was investigated using conductive atomic force microscopy. Low-bias direct tunneling was observed in mono-, bi-, and tri-layer h-BN. For all thicknesses, Fowler-Nordheim tunneling (FNT) occurred at high bias, showing an increase of breakdown voltage with thickness. Based on the FNT model, the barrier height for tunneling (3.07 eV) and dielectric strength (7.94 MV/cm) of h-BN are obtained; these values are comparable to those of SiO2.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

NASA Astrophysics Data System (ADS)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies

NASA Astrophysics Data System (ADS)

Roy, Pradip K.; Chacon, Carlos M.; Ma, Yi; Horner, Gregory

1997-09-01

The advent of ultra-large and giga-scale-integration (ULSI/GSI) has placed considerable emphasis on the development of new gate oxides and interlevel dielectrics capable of meeting strict performance and reliability requirements. The costs and demands associated with ULSI fabrication have in turn fueled the need for cost-effective, rapid and accurate in-line characterization techniques for evaluating dielectric quality. The use of non-contact surface photovoltage characterization techniques provides cost-effective rapid feedback on dielectric quality, reducing costs through the reutilization of control wafers and the elimination of processing time. This technology has been applied to characterize most of the relevant C-V parameters, including flatband voltage (Vfb), density of interface traps (Dit), mobile charge density (Qm), oxide thickness (Tox), oxide resistivity (pox) and total charge (Qtot) for gate and interlevel (ILO) oxides. A novel method of measuring tunneling voltage by this technique on various gate oxides is discussed. For ILO, PECVD and high density plasma dielectrics, surface voltage maps are also presented. Measurements of near-surface silicon quality are described, including minority carrier generation lifetime, and examples of their application in diagnosing manufacturing problems.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

2018-03-01

In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Carbon nanotube network thin-film transistors on flexible/stretchable substrates

DOEpatents

Takei, Kuniharu; Takahashi, Toshitake; Javey, Ali

2016-03-29

This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.

SEGR in SiO$${}_2$$ –Si$$_3$$ N$$_4$$ Stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Javanainen, Arto; Ferlet-Cavrois, Veronique; Bosser, Alexandre

2014-04-17

This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO 2–Si 3N 4 structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

NASA Astrophysics Data System (ADS)

Ortiz, Deliris N.; Ramos, Idalia; Pinto, Nicholas J.; Zhao, Meng-Qiang; Kumar, Vinayak; Johnson, A. T. Charlie

2018-03-01

CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET) configuration using an ionic liquid (IL) as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (˜7 μF/cm2) IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ˜2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

NASA Astrophysics Data System (ADS)

Ren, Zeyang; Zhang, Jinfeng; Zhang, Jincheng; Zhang, Chunfu; Chen, Dazheng; Quan, Rudai; Yang, Jiayin; Lin, Zhiyu; Hao, Yue

2017-12-01

We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Fully Printed Flexible and Stretchable Electronics

NASA Astrophysics Data System (ADS)

Zhang, Suoming

Through this thesis proposal, the author has demonstrated series of flexible or stretchable sensors including strain gauge, pressure sensors, display arrays, thin film transistors and photodetectors fabricated by a direct printing process. By adopting the novel serpentine configuration with conventional non-stretchable materials silver nanoparticles, the fully printed stretchable devices are successfully fabricated on elastomeric substrate with the demonstration of stretchable conductors that can maintain the electrical properties under strain and the strain gauge, which could be used to measure the strain in desired locations and also to monitor individual person's finger motion. And by investigating the intrinsic stretchable materials silver nanowires (AgNWs) with the conventional configuration, the fully printed stretchable conductors are achieved on various substrates including Si, glass, Polyimide, Polydimethylsiloxane (PDMS) and Very High Bond (VHB) tape with the illustration of the capacitive pressure sensor and stretchable electroluminescent displays. In addition, intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits are directly printed on elastomeric PDMS substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO3) nanoparticles. The BaTiO3/PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. Finally, by applying the SWNTs as the channel layer of the thin film transistor, we successfully fabricate the fully printed flexible photodetector which exhibits good electrical characteristics and the transistors exhibit good reliability under bending conditions owing to the ultrathin polyimide substrate as well as the superior mechanical flexibility of the gate dielectric and carbon nanotube network. Furthermore, we have demonstrated that by using two types of SWCNT samples with different optical absorption characteristics, the photoresponse exhibits unique wavelength selectivity, as manifested by the good correlation between the responsive wavelengths of the devices with the absorption peaks of the corresponding carbon nanotubes. All the proposed materials above together with the unique direct printing process may offer an entry into more sophisticated flexible or stretchable electronic systems with monolithically integrated sensors, actuators, and displays for real life applications.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Complex oxide thin films for microelectronics

NASA Astrophysics Data System (ADS)

Suvorova, Natalya

The rapid scaling of the device dimensions, namely in metal oxide semiconductor field effect transistor (MOSFET), is reaching its fundamental limit which includes the increase in allowable leakage current due to direct tunneling with decrease of physical thickness of SiO2 gate dielectric. The significantly higher relative dielectric constant (in the range 9--25) of the gate dielectric beyond the 3.9 value of silicon dioxide will allow increasing the physical thickness. Among the choices for the high dielectric constant (K) materials for future generation MOSFET application, barium strontium titanate (BST) and strontium titanate (STO) possess one of the highest attainable K values making them the promising candidates for alternative gate oxide. However, the gate stack engineering does not imply the simple replacement of the SiO2 with the new dielectric. Several requirements should be met for successful integration of a new material. The major one is a production of high level of interface states (Dit) compared to that of SiO 2 on Si. An insertion of a thin SiO2 layer prior the growth of high-K thin film is a simple solution that helps to limit reaction with Si substrate and attains a high quality interface. However, the combination of two thin films reduces the overall K of the dielectric stack. An optimization of the SiO2 underlayer in order to maintain the interface quality yet minimize the effect on K is the focus of this work. The results from our study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST and STO films sputter deposited on thermally oxidized Si substrates spectroscopic ellipsometry in combination with time of flight ion scattering and recoil spectrometry have been employed. Studies of material properties have been complemented with analytical electron microscopy. To evaluate the interface quality the electrical characterization has been employed using capacitance-voltage and conductance-voltage measurements. Special attention was given to the extraction of static dielectric constant of BST and STO from the multiple film stack. The K value was found to be sensitive to the input parameters such as dielectric constant and thickness of interface layers.

A solid dielectric gated graphene nanosensor in electrolyte solutions.

PubMed

Zhu, Yibo; Wang, Cheng; Petrone, Nicholas; Yu, Jaeeun; Nuckolls, Colin; Hone, James; Lin, Qiao

2015-03-23

This letter presents a graphene field effect transistor (GFET) nanosensor that, with a solid gate provided by a high- κ dielectric, allows analyte detection in liquid media at low gate voltages. The gate is embedded within the sensor and thus is isolated from a sample solution, offering a high level of integration and miniaturization and eliminating errors caused by the liquid disturbance, desirable for both in vitro and in vivo applications. We demonstrate that the GFET nanosensor can be used to measure pH changes in a range of 5.3-9.3. Based on the experimental observations and quantitative analysis, the charging of an electrical double layer capacitor is found to be the major mechanism of pH sensing.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

NASA Astrophysics Data System (ADS)

Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

2016-02-01

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

PubMed

Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

2018-02-14

Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

PubMed Central

Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-01-01

The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

PubMed

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

NASA Astrophysics Data System (ADS)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Influence of Gate Dielectrics, Electrodes and Channel Width on OFET Characteristics

NASA Astrophysics Data System (ADS)

Liyana, V. P.; Stephania, A. M.; Shiju, K.; Predeep, P.

2015-06-01

Organic Field Effect Transistors (OFET) possess wide applications in large area electronics owing to their attractive features like easy fabrication process, light weight, flexibility, cost effectiveness etc. But instability, high operational voltages and low carrier mobility act as inhibitors to commercialization of OFETs and various approaches were tried on a regular basis so as to make it viable. In this work, Poly 3-hexylthiophene-2,5diyl (P3HT) based OFETs with bottom-contact top-gate configuration using Poly vinyl alcohol (PVA) and Poly (methyl methacrylate) (PMMA) as gate dielectrics, aluminium and copper as source-drain electrodes are investigated. An effort is made to compare the effect of these dielectric materials and electrodes on the performance of OFET. Also, an attempt has been made to optimize the channel width of the device. These devices are characterised with mobility (μ), threshold voltage (VT), on-off ratio (Ion/Ioff) and their comparative analysis is reported.

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Y.; Li, H.; Robertson, J.

2016-05-28

AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed tomore » its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.« less

Electron-beam irradiation-induced gate oxide degradation

NASA Astrophysics Data System (ADS)

Cho, Byung Jin; Chong, Pei Fen; Chor, Eng Fong; Joo, Moon Sig; Yeo, In Seok

2000-12-01

Gate oxide degradation induced by electron-beam irradiation has been studied. A large increase in the low-field excess leakage current was observed on irradiated oxides and this was very similar to electrical stress-induced leakage currents. Unlike conventional electrical stress-induced leakage currents, however, electron-beam induced leakage currents exhibit a power law relationship with fluency without any signs of saturation. It has also been found that the electron-beam neither accelerates nor initiates quasibreakdown of the ultrathin gate oxide. Therefore, the traps generated by electron-beam irradiation do not contribute to quasibreakdown, only to the leakage current.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori

We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{submore » 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.« less

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

NASA Astrophysics Data System (ADS)

Tayal, Shubham; Nandi, Ashutosh

2018-06-01

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Ester-free cross-linker molecules for ultraviolet-light-cured polysilsesquioxane gate dielectric layers of organic thin-film transistors

NASA Astrophysics Data System (ADS)

Okada, Shuichi; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2018-04-01

Pentacene thin-film transistors (TFTs) were fabricated with ultraviolet-light (UV)-cured polysilsesquioxane (PSQ) gate dielectric layers using cross-linker molecules with or without ester groups. To polymerize PSQ without ester groups, thiol-ene reaction was adopted. The TFTs fabricated with PSQ layers comprising ester-free cross-linkers showed a higher carrier mobility than the TFTs with PSQ layers cross-linked with ester groups, which had large electric dipole moments that limited the carrier mobility. It was demonstrated that the thiol-ene reaction is more suitable than the conventional radical reaction for UV-cured PSQ with small dielectric constant.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

An ultrathin wide-band planar metamaterial absorber based on a fractal frequency selective surface and resistive film

NASA Astrophysics Data System (ADS)

Fan, Yue-Nong; Cheng, Yong-Zhi; Nie, Yan; Wang, Xian; Gong, Rong-Zhou

2013-06-01

We propose an ultrathin wide-band metamaterial absorber (MA) based on a Minkowski (MIK) fractal frequency selective surface and resistive film. This absorber consists of a periodic arrangement of dielectric substrates sandwiched with an MIK fractal loop structure electric resonator and a resistive film. The finite element method is used to simulate and analyze the absorption of the MA. Compared with the MA-backed copper film, the designed MA-backed resistive film exhibits an absorption of 90% at a frequency region of 2 GHz-20 GHz. The power loss density distribution of the MA is further illustrated to explain the mechanism of the proposed MA. Simulated absorptions at different incidence cases indicate that this absorber is polarization-insensitive and wide-angled. Finally, further simulated results indicate that the surface resistance of the resistive film and the dielectric constant of the substrate can affect the absorbing property of the MA. This absorber may be used in many military fields.

Probing nanoscale ion dynamics in ultrathin films of polymerized ionic liquids by broadband dielectric spectroscopy

NASA Astrophysics Data System (ADS)

Sangoro, Joshua; Heres, Maximilian; Cosby, Tyler

Continuous progress in energy storage and conversion technologies necessitates novel experimental approaches that can provide fundamental insights regarding the impact of reduced dimensions on the functional properties of materials. In this talk, a nondestructive experimental approach to probe nanoscale ion dynamics in ultrathin films of polymerized ionic liquids over a broad frequency range spanning over six orders of magnitude by broadband dielectric spectroscopy will be presented. The approach involves using an electrode configuration with lithographically patterned silica nanostructures, which allow for an air gap between the confined ion conductor and one of the electrodes. It is observed that the characteristic ion dynamics rates significantly slow down with decreasing film thicknesses above the calorimetric glass transition of the bulk polymer. However, the mean rates remain bulk-like at lower temperatures. These results highlight the increasing influence of the polymer/substrate interactions with decreasing film thickness on ion dynamics. The authors gratefully acknowledge the National Science Foundation for financial support through the Polymers Program award DMR-1508394.

Reversible optical switching of highly confined phonon-polaritons with an ultrathin phase-change material

NASA Astrophysics Data System (ADS)

Li, Peining; Yang, Xiaosheng; Maß, Tobias W. W.; Hanss, Julian; Lewin, Martin; Michel, Ann-Katrin U.; Wuttig, Matthias; Taubner, Thomas

2016-08-01

Surface phonon-polaritons (SPhPs), collective excitations of photons coupled with phonons in polar crystals, enable strong light-matter interaction and numerous infrared nanophotonic applications. However, as the lattice vibrations are determined by the crystal structure, the dynamical control of SPhPs remains challenging. Here, we realize the all-optical, non-volatile, and reversible switching of SPhPs by controlling the structural phase of a phase-change material (PCM) employed as a switchable dielectric environment. We experimentally demonstrate optical switching of an ultrathin PCM film (down to 7 nm, <λ/1,200) with single laser pulses and detect ultra-confined SPhPs (polariton wavevector kp > 70k0, k0 = 2π/λ) in quartz. Our proof of concept allows the preparation of all-dielectric, rewritable SPhP resonators without the need for complex fabrication methods. With optimized materials and parallelized optical addressing we foresee application potential for switchable infrared nanophotonic elements, for example, imaging elements such as superlenses and hyperlenses, as well as reconfigurable metasurfaces and sensors.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Radiation Effects On Emerging Electronic Materials And Devices

DTIC Science & Technology

2010-01-17

RADIATION EFFECTS ON EMERGING ELECTRONIC MATERIALS AND DEVICES FINAL PERFORMANCE REPORT PREPARED FOR: Kitt Reinhardt AFOSR/NE 875 N...and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage... metal gate process GIDL method Fig. 1. Sensing margin as a function of total ionizing dose for nMOS 1T-DRAM cells programmed by back-gate pulse and

Effect of dielectric layers on device stability of pentacene-based field-effect transistors.

PubMed

Di, Chong-an; Yu, Gui; Liu, Yunqi; Guo, Yunlong; Sun, Xiangnan; Zheng, Jian; Wen, Yugeng; Wang, Ying; Wu, Weiping; Zhu, Daoben

2009-09-07

We report stable organic field-effect transistors (OFETs) based on pentacene. It was found that device stability strongly depends on the dielectric layer. Pentacene thin-film transistors based on the bare or polystyrene-modified SiO(2) gate dielectrics exhibit excellent electrical stabilities. In contrast, the devices with the octadecyltrichlorosilane (OTS)-treated SiO(2) dielectric layer showed the worst stabilities. The effects of the different dielectrics on the device stabilities were investigated. We found that the surface energy of the gate dielectric plays a crucial role in determining the stability of the pentacene thin film, device performance and degradation of electrical properties. Pentacene aggregation, phase transfer and film morphology are also important factors that influence the device stability of pentacene devices. As a result of the surface energy mismatch between the dielectric layer and organic semiconductor, the electronic performance was degraded. Moreover, when pentacene was deposited on the OTS-treated SiO(2) dielectric layer with very low surface energy, pentacene aggregation occurred and resulted in a dramatic decrease of device performance. These results demonstrated that the stable OFETs could be obtained by using pentacene as a semiconductor layer.

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

NASA Astrophysics Data System (ADS)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Gate-tunable carbon nanotube-MoS2 heterojunction p-n diode.

PubMed

Jariwala, Deep; Sangwan, Vinod K; Wu, Chung-Chiang; Prabhumirashi, Pradyumna L; Geier, Michael L; Marks, Tobin J; Lauhon, Lincoln J; Hersam, Mark C

2013-11-05

The p-n junction diode and field-effect transistor are the two most ubiquitous building blocks of modern electronics and optoelectronics. In recent years, the emergence of reduced dimensionality materials has suggested that these components can be scaled down to atomic thicknesses. Although high-performance field-effect devices have been achieved from monolayered materials and their heterostructures, a p-n heterojunction diode derived from ultrathin materials is notably absent and constrains the fabrication of complex electronic and optoelectronic circuits. Here we demonstrate a gate-tunable p-n heterojunction diode using semiconducting single-walled carbon nanotubes (SWCNTs) and single-layer molybdenum disulfide as p-type and n-type semiconductors, respectively. The vertical stacking of these two direct band gap semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias to achieve a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 10(4). This heterojunction diode also responds strongly to optical irradiation with an external quantum efficiency of 25% and fast photoresponse <15 μs. Because SWCNTs have a diverse range of electrical properties as a function of chirality and an increasing number of atomically thin 2D nanomaterials are being isolated, the gate-tunable p-n heterojunction concept presented here should be widely generalizable to realize diverse ultrathin, high-performance electronics and optoelectronics.

Gate-tunable carbon nanotube–MoS2 heterojunction p-n diode

PubMed Central

Jariwala, Deep; Sangwan, Vinod K.; Wu, Chung-Chiang; Prabhumirashi, Pradyumna L.; Geier, Michael L.; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2013-01-01

The p-n junction diode and field-effect transistor are the two most ubiquitous building blocks of modern electronics and optoelectronics. In recent years, the emergence of reduced dimensionality materials has suggested that these components can be scaled down to atomic thicknesses. Although high-performance field-effect devices have been achieved from monolayered materials and their heterostructures, a p-n heterojunction diode derived from ultrathin materials is notably absent and constrains the fabrication of complex electronic and optoelectronic circuits. Here we demonstrate a gate-tunable p-n heterojunction diode using semiconducting single-walled carbon nanotubes (SWCNTs) and single-layer molybdenum disulfide as p-type and n-type semiconductors, respectively. The vertical stacking of these two direct band gap semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias to achieve a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 104. This heterojunction diode also responds strongly to optical irradiation with an external quantum efficiency of 25% and fast photoresponse <15 μs. Because SWCNTs have a diverse range of electrical properties as a function of chirality and an increasing number of atomically thin 2D nanomaterials are being isolated, the gate-tunable p-n heterojunction concept presented here should be widely generalizable to realize diverse ultrathin, high-performance electronics and optoelectronics. PMID:24145425

Lateral amorphous selenium metal-insulator-semiconductor-insulator-metal photodetectors using ultrathin dielectric blocking layers for dark current suppression

NASA Astrophysics Data System (ADS)

Chang, Cheng-Yi; Pan, Fu-Ming; Lin, Jian-Siang; Yu, Tung-Yuan; Li, Yi-Ming; Chen, Chieh-Yang

2016-12-01

We fabricated amorphous selenium (a-Se) photodetectors with a lateral metal-insulator-semiconductor-insulator-metal (MISIM) device structure. Thermal aluminum oxide, plasma-enhanced chemical vapor deposited silicon nitride, and thermal atomic layer deposited (ALD) aluminum oxide and hafnium oxide (ALD-HfO2) were used as the electron and hole blocking layers of the MISIM photodetectors for dark current suppression. A reduction in the dark current by three orders of magnitude can be achieved at electric fields between 10 and 30 V/μm. The effective dark current suppression is primarily ascribed to electric field lowering in the dielectric layers as a result of charge trapping in deep levels. Photogenerated carriers in the a-Se layer can be transported across the blocking layers to the Al electrodes via Fowler-Nordheim tunneling because a high electric field develops in the ultrathin dielectric layers under illumination. Since the a-Se MISIM photodetectors have a very low dark current without significant degradation in the photoresponse, the signal contrast is greatly improved. The MISIM photodetector with the ALD-HfO2 blocking layer has an optimal signal contrast more than 500 times the contrast of the photodetector without a blocking layer at 15 V/μm.

Dielectric discontinuity at interfaces in the atomic-scale limit: permittivity of ultrathin oxide films on silicon.

PubMed

Giustino, Feliciano; Umari, Paolo; Pasquarello, Alfredo

2003-12-31

Using a density-functional approach, we study the dielectric permittivity across interfaces at the atomic scale. Focusing on the static and high-frequency permittivities of SiO2 films on silicon, for oxide thicknesses from 12 A down to the atomic scale, we find a departure from bulk values in accord with experiment. A classical three-layer model accounts for the calculated permittivities and is supported by the microscopic polarization profile across the interface. The local screening varies on length scales corresponding to first-neighbor distances, indicating that the dielectric transition is governed by the chemical grading. Silicon-induced gap states are shown to play a minor role.

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

NASA Astrophysics Data System (ADS)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable insights into the electrolyte-redox systems. In summary, this work provides fundamental insights into the interaction of redox-energy states with silicon substrate and realistic approaches for exploiting the unique properties of the molecules that may enable solutions for nanoscale high density, low-voltage, long retention and multiple bit memory applications.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

An ultra-lightweight design for imperceptible plastic electronics.

PubMed

Kaltenbrunner, Martin; Sekitani, Tsuyoshi; Reeder, Jonathan; Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Drack, Michael; Schwödiauer, Reinhard; Graz, Ingrid; Bauer-Gogonea, Simona; Bauer, Siegfried; Someya, Takao

2013-07-25

Electronic devices have advanced from their heavy, bulky origins to become smart, mobile appliances. Nevertheless, they remain rigid, which precludes their intimate integration into everyday life. Flexible, textile and stretchable electronics are emerging research areas and may yield mainstream technologies. Rollable and unbreakable backplanes with amorphous silicon field-effect transistors on steel substrates only 3 μm thick have been demonstrated. On polymer substrates, bending radii of 0.1 mm have been achieved in flexible electronic devices. Concurrently, the need for compliant electronics that can not only be flexed but also conform to three-dimensional shapes has emerged. Approaches include the transfer of ultrathin polyimide layers encapsulating silicon CMOS circuits onto pre-stretched elastomers, the use of conductive elastomers integrated with organic field-effect transistors (OFETs) on polyimide islands, and fabrication of OFETs and gold interconnects on elastic substrates to realize pressure, temperature and optical sensors. Here we present a platform that makes electronics both virtually unbreakable and imperceptible. Fabricated directly on ultrathin (1 μm) polymer foils, our electronic circuits are light (3 g m(-2)) and ultraflexible and conform to their ambient, dynamic environment. Organic transistors with an ultra-dense oxide gate dielectric a few nanometres thick formed at room temperature enable sophisticated large-area electronic foils with unprecedented mechanical and environmental stability: they withstand repeated bending to radii of 5 μm and less, can be crumpled like paper, accommodate stretching up to 230% on prestrained elastomers, and can be operated at high temperatures and in aqueous environments. Because manufacturing costs of organic electronics are potentially low, imperceptible electronic foils may be as common in the future as plastic wrap is today. Applications include matrix-addressed tactile sensor foils for health care and monitoring, thin-film heaters, temperature and infrared sensors, displays, and organic solar cells.

Stable indium oxide thin-film transistors with fast threshold voltage recovery

NASA Astrophysics Data System (ADS)

Vygranenko, Yuriy; Wang, Kai; Nathan, Arokia

2007-12-01

Stable thin-film transistors (TFTs) with semiconducting indium oxide channel and silicon dioxide gate dielectric were fabricated by reactive ion beam assisted evaporation and plasma-enhanced chemical vapor deposition. The field-effect mobility is 3.3cm2/Vs, along with an on/off current ratio of 106, and subthreshold slope of 0.5V/decade. When subject to long-term gate bias stress, the TFTs show fast recovery of the threshold voltage (VT) when relaxed without annealing, suggesting that charge trapping at the interface and/or in the bulk gate dielectric to be the dominant mechanism underlying VT instability. Device performance and stability make indium oxide TFTs promising for display applications.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Electrical in-situ characterisation of interface stabilised organic thin-film transistors

PubMed Central

Striedinger, Bernd; Fian, Alexander; Petritz, Andreas; Lassnig, Roman; Winkler, Adolf; Stadlober, Barbara

2015-01-01

We report on the electrical in-situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom-gate/bottom-contact (coplanar) configuration are electrically characterised in-situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO2 with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor parameters is studied on a bi-layer dielectric of a 150 nm of SiO2 and 20 nm of poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO2 dielectric. The thin layer of PNDPE, which is an intrinsically photo-patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. PMID:26457122

High-performance, low-operating voltage, and solution-processable organic field-effect transistor with silk fibroin as the gate dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Leilei; Xu, Xinjun, E-mail: xuxj@mater.ustb.edu.cn, E-mail: lidong@mater.ustb.edu.cn; Ma, Mingchao

2014-01-13

We report the use of silk fibroin as the gate dielectric material in solution-processed organic field-effect transistors (OFETs) with poly(3-hexylthiophene) (P3HT) as the semiconducting layer. Such OFETs exhibit a low threshold of −0.77 V and a low-operating voltage (0 to −3 V) compatible with the voltage level commonly-used in current electronic industry. The carrier mobility of such OFETs is as high as 0.21 cm{sup 2} V{sup −1} s{sup −1} in the saturation regime, comparable to the best value of P3HT-based OFETs with dielectric layer that is not solution-processed. The high-performance of this kind of OFET is related with the high contentmore » of β strands in fibroin dielectric which leads to an array of fibers in a highly ordered structure, thus reducing the trapping sites at the semiconductor/dielectric interface.« less

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk; Mazzocco, R.

2015-05-18

We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currentsmore » (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.« less

Electrical Characterization of Semiconductor and Dielectric Materials with a Non-Damaging FastGateTM Probe

NASA Astrophysics Data System (ADS)

Robert, Hillard; William, Howland; Bryan, Snyder

2002-03-01

Determination of the electrical properties of semiconductor materials and dielectrics is highly desirable since these correlate best to final device performance. The properties of SiO2 and high k dielectrics such as Equivalent Oxide Thickness(EOT), Interface Trap Density(Dit), Oxide Effective Charge(Neff), Flatband Voltage Hysteresis(Delta Vfb), Threshold Voltage(VT) and, bulk properties such as carrier density profile and channel dose are all important parameters that require monitoring during front end processing. Conventional methods for determining these parameters involve the manufacturing of polysilicon or metal gate MOS capacitors and subsequent measurements of capacitance-voltage(CV) and/or current-voltage(IV). These conventional techniques are time consuming and can introduce changes to the materials being monitored. Also, equivalent circuit effects resulting from excessive leakage current, series resistance and stray inductance can introduce large errors in the measured results. In this paper, a new method is discussed that provides rapid determination of these critical parameters and is robust against equivalent circuit errors. This technique uses a small diameter(30 micron), elastically deformed probe to form a gate for MOSCAP CV and IV and can be used to measure either monitor wafers or test areas within scribe lines on product wafers. It allows for measurements of dielectrics thinner than 10 Angstroms. A detailed description and applications such as high k dielectrics, will be presented.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

PubMed

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Spatially and momentum resolved energy electron loss spectra from an ultra-thin PrNiO{sub 3} layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kinyanjui, M. K., E-mail: michael.kinyanjui@uni-ulm.de; Kaiser, U.; Benner, G.

2015-05-18

We present an experimental approach which allows for the acquisition of spectra from ultra-thin films at high spatial, momentum, and energy resolutions. Spatially and momentum (q) resolved electron energy loss spectra have been obtained from a 12 nm ultra-thin PrNiO{sub 3} layer using a nano-beam electron diffraction based approach which enabled the acquisition of momentum resolved spectra from individual, differently oriented nano-domains and at different positions of the PrNiO{sub 3} thin layer. The spatial and wavelength dependence of the spectral excitations are obtained and characterized after the analysis of the experimental spectra using calculated dielectric and energy loss functions. The presentedmore » approach makes a contribution towards obtaining momentum-resolved spectra from nanostructures, thin film, heterostructures, surfaces, and interfaces.« less

Ultrathin niobium nanofilms on fiber optical tapers - a new route towards low-loss hybrid plasmonic modes

NASA Astrophysics Data System (ADS)

Wieduwilt, Torsten; Tuniz, Alessandro; Linzen, Sven; Goerke, Sebastian; Dellith, Jan; Hübner, Uwe; Schmidt, Markus A.

2015-11-01

Due to the ongoing improvement in nanostructuring technology, ultrathin metallic nanofilms have recently gained substantial attention in plasmonics, e.g. as building blocks of metasurfaces. Typically, noble metals such as silver or gold are the materials of choice, due to their excellent optical properties, however they also possess some intrinsic disadvantages. Here, we introduce niobium nanofilms (~10 nm thickness) as an alternate plasmonic platform. We demonstrate functionality by depositing a niobium nanofilm on a plasmonic fiber taper, and observe a dielectric-loaded niobium surface-plasmon excitation for the first time, with a modal attenuation of only 3-4 dB/mm in aqueous environment and a refractive index sensitivity up to 15 μm/RIU if the analyte index exceeds 1.42. We show that the niobium nanofilm possesses bulk optical properties, is continuous, homogenous, and inert against any environmental influence, thus possessing several superior properties compared to noble metal nanofilms. These results demonstrate that ultrathin niobium nanofilms can serve as a new platform for biomedical diagnostics, superconducting photonics, ultrathin metasurfaces or new types of optoelectronic devices.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Treesearch

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

NASA Astrophysics Data System (ADS)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

NASA Astrophysics Data System (ADS)

Bolshakov, Pavel; Zhao, Peng; Azcatl, Angelica; Hurley, Paul K.; Wallace, Robert M.; Young, Chadwin D.

2017-07-01

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ˜69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V.s, indicating a positive influence on top-gate device performance even without any backside bias.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Electrical Double Layer Capacitance in a Graphene-embedded Al2O3 Gate Dielectric

PubMed Central

Ki Min, Bok; Kim, Seong K.; Jun Kim, Seong; Ho Kim, Sung; Kang, Min-A; Park, Chong-Yun; Song, Wooseok; Myung, Sung; Lim, Jongsun; An, Ki-Seok

2015-01-01

Graphene heterostructures are of considerable interest as a new class of electronic devices with exceptional performance in a broad range of applications has been realized. Here, we propose a graphene-embedded Al2O3 gate dielectric with a relatively high dielectric constant of 15.5, which is about 2 times that of Al2O3, having a low leakage current with insertion of tri-layer graphene. In this system, the enhanced capacitance of the hybrid structure can be understood by the formation of a space charge layer at the graphene/Al2O3 interface. The electrical properties of the interface can be further explained by the electrical double layer (EDL) model dominated by the diffuse layer. PMID:26530817

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Improved dc and power performance of AlGaN/GaN high electron mobility transistors with Sc 2O 3 gate dielectric or surface passivation

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R. C.; Moser, N.; Gillespie, J. K.; Jessen, G. H.; Jenkins, T. J.; Yannuzi, M. J.; Via, G. D.; Crespo, A.

2003-10-01

The dc and power characteristics of AlGaN/GaN MOS-HEMTs with Sc 2O 3 gate dielectrics were compared with that of conventional metal-gate HEMTs fabricated on the same material. The MOS-HEMT shows higher saturated drain-source current (˜0.75 A/mm) and significantly better power-added efficiency (PAE, 27%) relative to the HEMT (˜0.6 A/mm and ˜5%). The Sc 2O 3 also provides effective surface passivation, with higher drain current, lower leakage currents and higher three-terminal breakdown voltage in passivated devices relative to unpassivated devices. The PAE also increases (from ˜5% to 12%) on the surface passivated HEMTs, showing that Sc 2O 3 is an attractive option for reducing gate and surface leakage in AlGaN/GaN heterostructure transistors.

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

NASA Astrophysics Data System (ADS)

Caraveo-Frescas, J. A.; Hedhili, M. N.; Wang, H.; Schwingenschlögl, U.; Alshareef, H. N.

2012-03-01

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ˜350 mV negative shift with the Si overlayer present and a ˜110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

Highly stable thin film transistors using multilayer channel structure

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Wang, Zhenwei; Anjum, D. H.; Hedhili, M. N.; Alshareef, H. N.

2015-03-01

We report highly stable gate-bias stress performance of thin film transistors (TFTs) using zinc oxide (ZnO)/hafnium oxide (HfO2) multilayer structure as the channel layer. Positive and negative gate-bias stress stability of the TFTs was measured at room temperature and at 60 °C. A tremendous improvement in gate-bias stress stability was obtained in case of the TFT with multiple layers of ZnO embedded between HfO2 layers compared to the TFT with a single layer of ZnO as the semiconductor. The ultra-thin HfO2 layers act as passivation layers, which prevent the adsorption of oxygen and water molecules in the ZnO layer and hence significantly improve the gate-bias stress stability of ZnO TFTs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nayak, Pradipta K.; Wang, Zhenwei; Anjum, D. H.

We report highly stable gate-bias stress performance of thin film transistors (TFTs) using zinc oxide (ZnO)/hafnium oxide (HfO{sub 2}) multilayer structure as the channel layer. Positive and negative gate-bias stress stability of the TFTs was measured at room temperature and at 60 °C. A tremendous improvement in gate-bias stress stability was obtained in case of the TFT with multiple layers of ZnO embedded between HfO{sub 2} layers compared to the TFT with a single layer of ZnO as the semiconductor. The ultra-thin HfO{sub 2} layers act as passivation layers, which prevent the adsorption of oxygen and water molecules in the ZnOmore » layer and hence significantly improve the gate-bias stress stability of ZnO TFTs.« less

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

A complementary organic inverter of porphyrazine thin films: low-voltage operation using ionic liquid gate dielectrics.

PubMed

Fujimoto, Takuya; Miyoshi, Yasuhito; Matsushita, Michio M; Awaga, Kunio

2011-05-28

We studied a complementary organic inverter consisting of a p-type semiconductor, metal-free phthalocyanine (H(2)Pc), and an n-type semiconductor, tetrakis(thiadiazole)porphyrazine (H(2)TTDPz), operated through the ionic-liquid gate dielectrics of N,N-diethyl-N-methyl(2-methoxyethyl)ammonium bis(trifluoromethylsulfonyl)imide (DEME-TFSI). This organic inverter exhibits high performance with a very low operation voltage below 1.0 V and a dynamic response up to 20 Hz. © The Royal Society of Chemistry 2011

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Tian-Li, E-mail: Tian-Li.Wu@imec.be; Groeseneken, Guido; Department of Electrical Engineering, KU Leuven, Leuven

2015-08-31

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g{sub m}), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si{sub 3}N{sub 4}, Rapid Thermal Chemical Vapor Deposition Si{sub 3}N{sub 4}, and Atomic Layer Deposition (ALD) Al{sub 2}O{sub 3}) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D{sub it}), the amount of border traps, and the threshold voltage (V{sub TH}) shift during a positive gate bias stress can be obtained. The results show that the V{sub TH} shift during a positive gate bias stress ismore » highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V{sub TH} shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D{sub it} needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g{sub m} dispersion commonly attributed to border traps might be influenced by interface states.« less

Reflectance properties of one-dimensional metal-dielectric ternary photonic crystal

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pandey, G. N., E-mail: gnpandey2009@gmail.com; Kumar, Narendra; Thapa, Khem B.

2016-05-06

Metallic photonic crystal has a very important application in absorption enhancement in solar cells. It has been found that an ultra-thin metallic layer becomes transparent due to internal scattering of light through the each interface of the dielectric and metal surfaces. The metal has absorption due to their surface plasmon and the plasmon has important parameters for changing optical properties of the metal. We consider ternary metallic-dielectric photonic crystal (MDPC) for having large probabilities to change the optical properties of the MDPC and the photonic crystals may be changed by changing dimensionality, symmetry, lattice parameters, Filling fraction and effective refractivemore » index refractive index contrast. In this present communication, we try to show that the photonic band gap in ternary metal-dielectric photonic crystal can be significantly enlarged when air dielectric constant is considered. All the theoretical analyses are made based on the transfer matrix method together with the Drude model of metal.« less

Application of high-quality SiO2 grown by multipolar ECR source to Si/SiGe MISFET

NASA Technical Reports Server (NTRS)

Sung, K. T.; Li, W. Q.; Li, S. H.; Pang, S. W.; Bhattacharya, P. K.

1993-01-01

A 5 nm-thick SiO2 gate was grown on an Si(p+)/Si(0.8)Ge(0.2) modulation-doped heterostructure at 26 C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field above 12 MV/cm and fixed charge density about 3 x 10 exp 10/sq cm. Leakage current as low as 1/micro-A was obtained with the gate biased at 4 V. The MISFET with 0.25 x 25 sq m gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

NASA Astrophysics Data System (ADS)

Huang, Cheng-Ying

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal- oxide-semiconductor ?eld-e?ect transistors (MOSFETs) are promising candidates for replacing Si-based MOSFETs for future very-large-scale integration (VLSI) logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower VDD and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current and low standby power consumption. In this dissertation, we will report InGaAs/InAs ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in InGaAs/InAs MOSFETs are reported as described below. 1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match to InP by molecular beam epitaxy (MBE), and studied the electron transport in In0.53Ga0.47As/AlAs 0.44Sb0.56 heterostructures. The InGaAs channel MOSFETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52 Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage. 2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (t ch ~ 2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current. 3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The raised InGaAs source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing BTBT leakage. With further replacement of raised InGaAs spacers by recessed, doping-graded InP spacers at high field regions, BTBT leakage can be reduced ~100:1. Using the above-mentioned techniques, record high performance InAs MOSFETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstrated with Ion = 500 microA/microm at Ioff = 100 nA/microm and VDS =0.5 V, showing the highest on-state performance among all the III-V MOSFETs and comparable performance to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InP source/drain spacers were also demonstrated with minimum I off = 60 pA/microm at 30 nm-Lg , and Ion = 150 microA/microm at I off = 1 nA/microm and VDS =0.5 V. This recessed InP source/drain spacer technique improves device scalability and enables III-V MOSFETs for low standby power logic applications. Furthermore, ultra-thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting high yield and high transconductance gm ~2.0 mS/microm at 20 nm- Lg and VDS =0.5 V. With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown maximum Ion/Ioff ratio ~8.3x105 , confirming that III-V MOSFETs are scalable to sub-10-nm technology nodes.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device andmore » thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.« less

Self-Healing Polymer Dielectric for a High Capacitance Gate Insulator.

PubMed

Ko, Jieun; Kim, Young-Jae; Kim, Youn Sang

2016-09-14

Self-healing materials are required for development of various flexible electronic devices to repair cracks and ruptures caused by repetitive bending or folding. Specifically, a self-healing dielectric layer has huge potential to achieve healing electronics without mechanical breakdown in flexible operations. Here, we developed a high performance self-healing dielectric layer with an ionic liquid and catechol-functionalized polymer which exhibited a self-healing ability for both bulk and film states under mild self-healing conditions at 55 °C for 30 min. Due to the sufficient ion mobility of the ionic liquid in the polymer matrix, it had a high capacitance value above 1 μF/cm(2) at 20 Hz. Moreover, zinc oxide (ZnO) thin-film transistors (TFTs) with a self-healing dielectric layer exhibited a high field-effect mobility of 16.1 ± 3.07 cm(2) V(-1) s(-1) at a gate bias of 3 V. Even after repetitive self-healing of the dielectric layer from mechanical breaking, the electrical performance of the TFTs was well-maintained.

Development of an ultra-thin film comprised of a graphene membrane and carbon nanotube vein support.

PubMed

Lin, Xiaoyang; Liu, Peng; Wei, Yang; Li, Qunqing; Wang, Jiaping; Wu, Yang; Feng, Chen; Zhang, Lina; Fan, Shoushan; Jiang, Kaili

2013-01-01

Graphene, exhibiting superior mechanical, thermal, optical and electronic properties, has attracted great interest. Considering it being one-atom-thick, and the reduced mechanical strength at grain boundaries, the fabrication of large-area suspended chemical vapour deposition graphene remains a challenge. Here we report the fabrication of an ultra-thin free-standing carbon nanotube/graphene hybrid film, inspired by the vein-membrane structure found in nature. Such a square-centimetre-sized hybrid film can realize the overlaying of large-area single-layer chemical vapour deposition graphene on to a porous vein-like carbon nanotube network. The vein-membrane-like hybrid film, with graphene suspended on the carbon nanotube meshes, possesses excellent mechanical performance, optical transparency and good electrical conductivity. The ultra-thin hybrid film features an electron transparency close to 90%, which makes it an ideal gate electrode in vacuum electronics and a high-performance sample support in transmission electron microscopy.

Two breakdown mechanisms in ultrathin alumina barrier magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Oliver, Bryan; Tuttle, Gary; He, Qing; Tang, Xuefei; Nowak, Janusz

2004-02-01

Two breakdown mechanisms are observed in magnetic tunnel junctions having an ultrathin alumina barrier. The two breakdown mechanisms manifest themselves differently when considering large ensembles of nominally identical devices under different stress conditions. The results suggest that one type of breakdown occurs because of the intrinsic breakdown of a well-formed oxide barrier that can be described by the E model of dielectric breakdown. The other is an extrinsic breakdown related to defects in the barrier rather than the failure of the oxide integrity. The characteristic of extrinsic breakdown suggests that a pre-existing pinhole in the barriers grows in area by means of dissipative (Joule) heating and/or an electric field across the pinhole circumference.

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

PubMed

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Deposition temperature dependent optical and electrical properties of ALD HfO{sub 2} gate dielectrics pretreated with tetrakisethylmethylamino hafnium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, J.; School of Sciences, Anhui University of Science and Technology, Huainan 232001; He, G., E-mail: hegang@ahu.edu.cn

2015-10-15

Highlights: • ALD-derived HfO{sub 2} gate dielectrics have been deposited on Si substrates. • The leakage current mechanism for different deposition temperature was discussed. • Different emission at different field region has been determined precisely. - Abstract: The effect of deposition temperature on the growth rate, band gap energy and electrical properties of HfO{sub 2} thin film deposited by atomic layer deposition (ALD) has been investigated. By means of characterization of spectroscopy ellipsometry and ultraviolet–visible spectroscopy, the growth rate and optical constant of ALD-derived HfO{sub 2} gate dielectrics are determined precisely. The deposition temperature dependent electrical properties of HfO{sub 2}more » films were determined by capacitance–voltage (C–V) and leakage current density–voltage (J–V) measurements. The leakage current mechanism for different deposition temperature has been discussed systematically. As a result, the optimized deposition temperature has been obtained to achieve HfO{sub 2} thin film with high quality.« less

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2018-02-01

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Impact of oxygen precursor flow on the forward bias behavior of MOCVD-Al2O3 dielectrics grown on GaN

NASA Astrophysics Data System (ADS)

Chan, Silvia H.; Bisi, Davide; Liu, Xiang; Yeluri, Ramya; Tahhan, Maher; Keller, Stacia; DenBaars, Steven P.; Meneghini, Matteo; Mishra, Umesh K.

2017-11-01

This paper investigates the effects of the oxygen precursor flow supplied during metalorganic chemical vapor deposition (MOCVD) of Al2O3 films on the forward bias behavior of Al2O3/GaN metal-oxide-semiconductor capacitors. The low oxygen flow (100 sccm) delivered during the in situ growth of Al2O3 on GaN resulted in films that exhibited a stable capacitance under forward stress, a lower density of stress-generated negative fixed charges, and a higher dielectric breakdown strength compared to Al2O3 films grown under high oxygen flow (480 sccm). The low oxygen grown Al2O3 dielectrics exhibited lower gate current transients in stress/recovery measurements, providing evidence of a reduced density of trap states near the GaN conduction band and an enhanced robustness under accumulated gate stress. This work reveals oxygen flow variance in MOCVD to be a strategy for controlling the dielectric properties and performance.

Interface band alignment in high-k gate stacks

NASA Astrophysics Data System (ADS)

Eric, Bersch; Hartlieb, P.

2005-03-01

In order to successfully implement alternate high-K dielectric materials into MOS structures, the interface properties of MOS gate stacks must be better understood. Dipoles that may form at the metal/dielectric and dielectric/semiconductor interfaces make the band offsets difficult to predict. We have measured the conduction and valence band densities of states for a variety MOS stacks using in situ using inverse photoemission (IPE) and photoemission spectroscopy (PES), respectively. Results obtained from clean and metallized (with Ru or Al) HfO2/Si, SiO2/Si and mixed silicate films will be presented. IPE indicates a shift of the conduction band minimum (CBM) to higher energy (i.e. away from EF) with increasing SiO2. The effect of metallization on the location of band edges depends upon the metal species. The addition of N to the dielectrics shifts the CBM in a way that is thickness dependent. Possible mechanisms for these observed effects will be discussed.

Interfacial structure and electrical properties of ultrathin HfO2 dielectric films on Si substrates by surface sol-gel method

NASA Astrophysics Data System (ADS)

Gong, You-Pin; Li, Ai-Dong; Qian, Xu; Zhao, Chao; Wu, Di

2009-01-01

Ultrathin HfO2 films with about ~3 nm thickness were deposited on n-type (1 0 0) silicon substrates using hafnium chloride (HfCl4) source by the surface sol-gel method and post-deposition annealing (PDA). The interfacial structure and electrical properties of ultrathin HfO2 films were investigated. The HfO2 films show amorphous structures and smooth surface morphologies with a very thin interfacial oxide layer of ~0.5 nm and small surface roughness (~0.45 nm). The 500 °C PDA treatment forms stronger Hf-O bonds, leading to passivated traps, and the interfacial layer is mainly Hf silicate (HfxSiyOz). Equivalent oxide thickness of around 0.84 nm of HfO2/Si has been obtained with a leakage current density of 0.7 A cm-2 at Vfb + 1 V after 500 °C PDA. It was found that the current conduction mechanism of HfO2/Si varied from Schottky-Richardson emission to Fowler-Nordheim tunnelling at an applied higher positive voltage due to the activated partial traps remaining in the ultrathin HfO2 films.

Image charge models for accurate construction of the electrostatic self-energy of 3D layered nanostructure devices.

PubMed

Barker, John R; Martinez, Antonio

2018-04-04

Efficient analytical image charge models are derived for the full spatial variation of the electrostatic self-energy of electrons in semiconductor nanostructures that arises from dielectric mismatch using semi-classical analysis. The methodology provides a fast, compact and physically transparent computation for advanced device modeling. The underlying semi-classical model for the self-energy has been established and validated during recent years and depends on a slight modification of the macroscopic static dielectric constants for individual homogeneous dielectric regions. The model has been validated for point charges as close as one interatomic spacing to a sharp interface. A brief introduction to image charge methodology is followed by a discussion and demonstration of the traditional failure of the methodology to derive the electrostatic potential at arbitrary distances from a source charge. However, the self-energy involves the local limit of the difference between the electrostatic Green functions for the full dielectric heterostructure and the homogeneous equivalent. It is shown that high convergence may be achieved for the image charge method for this local limit. A simple re-normalisation technique is introduced to reduce the number of image terms to a minimum. A number of progressively complex 3D models are evaluated analytically and compared with high precision numerical computations. Accuracies of 1% are demonstrated. Introducing a simple technique for modeling the transition of the self-energy between disparate dielectric structures we generate an analytical model that describes the self-energy as a function of position within the source, drain and gated channel of a silicon wrap round gate field effect transistor on a scale of a few nanometers cross-section. At such scales the self-energies become large (typically up to ~100 meV) close to the interfaces as well as along the channel. The screening of a gated structure is shown to reduce the self-energy relative to un-gated nanowires.

Image charge models for accurate construction of the electrostatic self-energy of 3D layered nanostructure devices

NASA Astrophysics Data System (ADS)

Barker, John R.; Martinez, Antonio

2018-04-01

Efficient analytical image charge models are derived for the full spatial variation of the electrostatic self-energy of electrons in semiconductor nanostructures that arises from dielectric mismatch using semi-classical analysis. The methodology provides a fast, compact and physically transparent computation for advanced device modeling. The underlying semi-classical model for the self-energy has been established and validated during recent years and depends on a slight modification of the macroscopic static dielectric constants for individual homogeneous dielectric regions. The model has been validated for point charges as close as one interatomic spacing to a sharp interface. A brief introduction to image charge methodology is followed by a discussion and demonstration of the traditional failure of the methodology to derive the electrostatic potential at arbitrary distances from a source charge. However, the self-energy involves the local limit of the difference between the electrostatic Green functions for the full dielectric heterostructure and the homogeneous equivalent. It is shown that high convergence may be achieved for the image charge method for this local limit. A simple re-normalisation technique is introduced to reduce the number of image terms to a minimum. A number of progressively complex 3D models are evaluated analytically and compared with high precision numerical computations. Accuracies of 1% are demonstrated. Introducing a simple technique for modeling the transition of the self-energy between disparate dielectric structures we generate an analytical model that describes the self-energy as a function of position within the source, drain and gated channel of a silicon wrap round gate field effect transistor on a scale of a few nanometers cross-section. At such scales the self-energies become large (typically up to ~100 meV) close to the interfaces as well as along the channel. The screening of a gated structure is shown to reduce the self-energy relative to un-gated nanowires.

Variations of Contact Resistance in Dual-Gated Monolayer Molybdenum Disulfide Transistors Depending on Gate Bias Selection

NASA Astrophysics Data System (ADS)

Tran, P. X.

2017-06-01

Monolayer molybdenum disulfide (MoS2) is considered an alternative two-dimensional material for high performance ultra-thin field-effect transistors. MoS2 is a triple atomic layer with a direct 1.8 eV bandgap. Bulk MoS2 has an additional indirect bandgap of 1.2 eV, which leads to high current on/off ratio around 108. Flakes of MoS2 can be obtained by mechanical exfoliation or grown by chemical vapor deposition. Intrinsic cut-off frequency of multilayer MoS2 transistor has reached 42 GHz. Chemical doping of MoS2 is challenging and results in reduction of contact resistance. This paper focuses on modeling of dual-gated monolayer MoS2 transistors with effective mobility of carriers varying from 0.6 cm2/V s to 750 cm2/V s. In agreement with experimental data, the model demonstrates that in back-gate bias devices, the contact resistance decreases almost exponentially with increasing gate bias, whereas in top-gate bias devices, the contact resistance stays invariant when varying gate bias.

Effects of plasma-induced charging damage on random telegraph noise in metal-oxide-semiconductor field-effect transistors with SiO2 and high-k gate dielectrics

NASA Astrophysics Data System (ADS)

Kamei, Masayuki; Takao, Yoshinori; Eriguchi, Koji; Ono, Kouichi

2014-01-01

We clarified in this study how plasma-induced charging damage (PCD) affects the so-called “random telegraph noise (RTN)” — a principal concern in designing ultimately scaled large-scale integrated circuits (LSIs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiO2 and high-k gate dielectric were exposed to an inductively coupled plasma (ICP) with Ar gas. Drain current vs gate voltage (Ids-Vg) characteristics were obtained before and after the ICP plasma exposure for the same device. Then, the time evolution of Ids fluctuation defined as Ids/μIds was measured, where μIds is the mean Ids. This value corresponds to an RTN feature, and RTN was obtained under various gate voltages (Vg) by a customized measurement technique. We focused on the statistical distribution width of (Ids/μIds), δ(Ids/μIds), in order to clarify the effects of PCD on RTN. δ(Ids/μIds) was increased by PCD for both MOSFETs with the SiO2 and high-k gate dielectrics, suggesting that RTN can be used as a measure of PCD, i.e., a distribution width increase directly indicates the presence of PCD. The dependence of δ(Ids/μIds) on the overdrive voltage Vg-Vth, where Vth is the threshold voltage, was investigated by the present technique. It was confirmed that δ(Ids/μIds) increased with a decrease in the overdrive voltage for MOSFETs with the SiO2 and high-k gate dielectrics. The presence of created carrier trap sites with PCD was characterized by the time constants for carrier capture and emission. The threshold voltage shift (ΔVth) induced by PCD was also evaluated and compared with the RTN change, to correlate the RTN increase with ΔVth induced by PCD. Although the estimated time constants exhibited complex behaviors due to the nature of trap sites created by PCD, δ(Ids/μIds) showed a straightforward tendency in accordance with the amount of PCD. These findings provide an in-depth understanding of plasma-induced RTN characteristic changes in future MOSFETs.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

Low-temperature sol-gel oxide TFT with a fluoropolymer dielectric to enhance the effective mobility at low operation voltage

NASA Astrophysics Data System (ADS)

Yu, Shang-Yu; Wang, Kuan-Hsun; Zan, Hsiao-Wen; Soppera, Olivier

2017-06-01

In this article, we propose a solution-processed high-performance amorphous indium-zinc oxide (a-IZO) thin-film transistor (TFT) gated with a fluoropolymer dielectric. Compared with a conventional IZO TFT with a silicon nitride dielectric, a fluoropolymer dielectric effectively reduces the operation voltage to less than 3 V and greatly increases the effective mobility 40-fold. We suggest that the dipole layer formed at the dielectric surface facilitates electron accumulation and induces the electric double-layer effect. The dipole-induced hysteresis effect is also investigated.

Nanoindentation investigation of HfO2 and Al2O3 films grown by atomic layer deposition

Treesearch

K. Tapily; Joseph E. Jakes; D. S. Stone; P. Shrestha; D. Gu; H. Baumgart; A. A. Elmustafa

2008-01-01

The challenges of reducing gate leakage current and dielectric breakdown beyond the 45 nm technology node have shifted engineers’ attention from the traditional and proven dielectric SiO2 to materials of higher dielectric constant also known as high-k materials such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). These high-k materials are projected to...

Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

Solution-Processed Transistors Using Colloidal Nanocrystals with Composition-Matched Molecular "Solders": Approaching Single Crystal Mobility.

PubMed

Jang, Jaeyoung; Dolzhnikov, Dmitriy S; Liu, Wenyong; Nam, Sooji; Shim, Moonsub; Talapin, Dmitri V

2015-10-14

Crystalline silicon-based complementary metal-oxide-semiconductor transistors have become a dominant platform for today's electronics. For such devices, expensive and complicated vacuum processes are used in the preparation of active layers. This increases cost and restricts the scope of applications. Here, we demonstrate high-performance solution-processed CdSe nanocrystal (NC) field-effect transistors (FETs) that exhibit very high carrier mobilities (over 400 cm(2)/(V s)). This is comparable to the carrier mobilities of crystalline silicon-based transistors. Furthermore, our NC FETs exhibit high operational stability and MHz switching speeds. These NC FETs are prepared by spin coating colloidal solutions of CdSe NCs capped with molecular solders [Cd2Se3](2-) onto various oxide gate dielectrics followed by thermal annealing. We show that the nature of gate dielectrics plays an important role in soldered CdSe NC FETs. The capacitance of dielectrics and the NC electronic structure near gate dielectric affect the distribution of localized traps and trap filling, determining carrier mobility and operational stability of the NC FETs. We expand the application of the NC soldering process to core-shell NCs consisting of a III-V InAs core and a CdSe shell with composition-matched [Cd2Se3](2-) molecular solders. Soldering CdSe shells forms nanoheterostructured material that combines high electron mobility and near-IR photoresponse.

Limitations of threshold voltage engineering of AlGaN/GaN heterostructures by dielectric interface charge density and manipulation by oxygen plasma surface treatments

NASA Astrophysics Data System (ADS)

Lükens, G.; Yacoub, H.; Kalisch, H.; Vescan, A.

2016-05-01

The interface charge density between the gate dielectric and an AlGaN/GaN heterostructure has a significant impact on the absolute value and stability of the threshold voltage Vth of metal-insulator-semiconductor (MIS) heterostructure field effect transistor. It is shown that a dry-etching step (as typically necessary for normally off devices engineered by gate-recessing) before the Al2O3 gate dielectric deposition introduces a high positive interface charge density. Its origin is most likely donor-type trap states shifting Vth to large negative values, which is detrimental for normally off devices. We investigate the influence of oxygen plasma annealing techniques of the dry-etched AlGaN/GaN surface by capacitance-voltage measurements and demonstrate that the positive interface charge density can be effectively compensated. Furthermore, only a low Vth hysteresis is observable making this approach suitable for threshold voltage engineering. Analysis of the electrostatics in the investigated MIS structures reveals that the maximum Vth shift to positive voltages achievable is fundamentally limited by the onset of accumulation of holes at the dielectric/barrier interface. In the case of the Al2O3/Al0.26Ga0.74N/GaN material system, this maximum threshold voltage shift is limited to 2.3 V.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Impact of geometric, thermal and tunneling effects on nano-transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Langhua; Chen, Duan, E-mail: dchen10@uncc.edu; Wei, Guo-Wei

Electronic transistors are fundamental building blocks of large scale integrated circuits in modern advanced electronic equipments, and their sizes have been down-scaled to nanometers. Modeling and simulations in the framework of quantum dynamics have emerged as important tools to study functional characteristics of these nano-devices. This work explores the effects of geometric shapes of semiconductor–insulator interfaces, phonon–electron interactions, and quantum tunneling of three-dimensional (3D) nano-transistors. First, we propose a two-scale energy functional to describe the electron dynamics in a dielectric continuum of device material. Coupled governing equations, i.e., Poisson–Kohn–Sham (PKS) equations, are derived by the variational principle. Additionally, it ismore » found that at a given channel cross section area and gate voltage, the geometry that has the smallest perimeter of the channel cross section offers the largest channel current, which indicates that ultra-thin nanotransistors may not be very efficient in practical applications. Moreover, we introduce a new method to evaluate quantum tunneling effects in nanotransistors without invoking the comparison of classical and quantum predictions. It is found that at a given channel cross section area and gate voltage, the geometry that has the smallest perimeter of the channel cross section has the smallest quantum tunneling ratio, which indicates that geometric defects can lead to higher geometric confinement and larger quantum tunneling effect. Furthermore, although an increase in the phonon–electron interaction strength reduces channel current, it does not have much impact to the quantum tunneling ratio. Finally, advanced numerical techniques, including second order elliptic interface methods, have been applied to ensure computational accuracy and reliability of the present PKS simulation.« less

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Ultrathin phase-change coatings on metals for electrothermally tunable colors

NASA Astrophysics Data System (ADS)

Bakan, Gokhan; Ayas, Sencer; Saidzoda, Tohir; Celebi, Kemal; Dana, Aykutlu

2016-08-01

Metal surfaces coated with ultrathin lossy dielectrics enable color generation through strong interferences in the visible spectrum. Using a phase-change thin film as the coating layer offers tuning the generated color by crystallization or re-amorphization. Here, we study the optical response of surfaces consisting of thin (5-40 nm) phase-changing Ge2Sb2Te5 (GST) films on metal, primarily Al, layers. A color scale ranging from yellow to red to blue that is obtained using different thicknesses of as-deposited amorphous GST layers turns dim gray upon annealing-induced crystallization of the GST. Moreover, when a relatively thick (>100 nm) and lossless dielectric film is introduced between the GST and Al layers, optical cavity modes are observed, offering a rich color gamut at the expense of the angle independent optical response. Finally, a color pixel structure is proposed for ultrahigh resolution (pixel size: 5 × 5 μm2), non-volatile displays, where the metal layer acting like a mirror is used as a heater element. The electrothermal simulations of such a pixel structure suggest that crystallization and re-amorphization of the GST layer using electrical pulses are possible for electrothermal color tuning.

Brillouin light scattering studies of the mechanical properties of ultrathin low-k dielectric films

NASA Astrophysics Data System (ADS)

Link, A.; Sooryakumar, R.; Bandhu, R. S.; Antonelli, G. A.

2006-07-01

In an effort to reduce RC time delays that accompany decreasing feature sizes, low-k dielectric films are rapidly emerging as potential replacements for silicon dioxide (SiO2) at the interconnect level in integrated circuits. The main challenge in low-k materials is their substantially weaker mechanical properties that accompany the increasing pore volume content needed to reduce k. We show that Brillouin light scattering is an excellent nondestructive technique to monitor and characterize the mechanical properties of these porous films at thicknesses well below 200nm that are pertinent to present applications. Observation of longitudinal and transverse standing wave acoustic resonances and the dispersion that accompany their transformation into traveling waves with finite in-plane wave vectors provides for a direct measure of the principal elastic constants that completely characterize the mechanical properties of these ultrathin films. The mode amplitudes of the standing waves, their variation within the film, and the calculated Brillouin intensities account for most aspects of the spectra. We further show that the values obtained by this method agree well with other experimental techniques such as nanoindentation and picosecond laser ultrasonics.

Ultralow-power organic complementary circuits.

PubMed

Klauk, Hagen; Zschieschang, Ute; Pflaum, Jens; Halik, Marcus

2007-02-15

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.

Tunable surface plasmon devices

DOEpatents

Shaner, Eric A [Rio Rancho, NM; Wasserman, Daniel [Lowell, MA

2011-08-30

A tunable extraordinary optical transmission (EOT) device wherein the tunability derives from controlled variation of the dielectric constant of a semiconducting material (semiconductor) in evanescent-field contact with a metallic array of sub-wavelength apertures. The surface plasmon resonance wavelength can be changed by changing the dielectric constant of the dielectric material. In embodiments of this invention, the dielectric material is a semiconducting material. The dielectric constant of the semiconducting material in the metal/semiconductor interfacial region is controllably adjusted by adjusting one or more of the semiconductor plasma frequency, the concentration and effective mass of free carriers, and the background high-frequency dielectric constant in the interfacial region. Thermal heating and/or voltage-gated carrier-concentration changes may be used to variably adjust the value of the semiconductor dielectric constant.

Experimental evidence for the correlation between the weak inversion hump and near midgap states in dielectric/InGaAs interfaces

NASA Astrophysics Data System (ADS)

Krylov, Igor; Kornblum, Lior; Gavrilov, Arkady; Ritter, Dan; Eizenberg, Moshe

2012-04-01

Temperature dependent capacitance-voltage (C-V) and conductance-voltage (G-V) measurements were performed to obtain activation energies (EA) for weak inversion C-V humps and parallel conductance peaks in Al2O3/InGaAs and Si3N4/InGaAs gate stacks. Values of 0.48 eV (slightly more than half of the band gap of the studied In0.53Ga0.47As) were obtained for EA of both phenomena for both gate dielectrics studied. This indicates an universal InGaAs behavior and shows that both phenomena are due to generation-recombination of minority carriers through near midgap located interface states. The C-V hump correlates with the interface states density (Dit) and can be used as a characterization tool for dielectric/InGaAs systems.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

Understanding Metal-Insulator transitions in ultra-thin films of LaNiO3

NASA Astrophysics Data System (ADS)

Ravichandran, Jayakanth; King, Philip D. C.; Schlom, Darrell G.; Shen, Kyle M.; Kim, Philip

2014-03-01

LaNiO3 (LNO) is a bulk paramagnetic metal and a member of the family of RENiO3 Nickelates (RE = Rare Earth Metals), which is on the verge of the metal-insulator transition. Ultra-thin films of LNO has been studied extensively in the past and due to its sensitivity to disorder, the true nature of the metal-insulator transition in these films have been hard to decipher. We grow high quality ultra-thin films of LNO using reactive molecular beam epitaxy (MBE) and use a combination of ionic liquid gating and magneto-transport measurements to understand the nature and tunability of metal-insulator transition as a function of thickness for LNO. The underlying mechanisms for the transition are discussed in the framework of standard transport models. These results are discussed in the light of other Mott insulators such as Sr2IrO4, where we have performed similar measurements around the insulating state.

Materials science, integration, and performance characterization of high-dielectric constant thin film based devices

NASA Astrophysics Data System (ADS)

Fan, Wei

To overcome the oxidation and diffusion problems encountered during Copper integration with oxide thin film-based devices, TiAl/Cu/Ta heterostructure has been first developed in this study. Investigation on the oxidation and diffusion resistance of the laminate structure showed high electrical conductance and excellent thermal stability in oxygen environment. Two amorphous oxide layers that were formed on both sides of the TiAl barrier after heating in oxygen have been revealed as the structure that effectively prevents oxygen penetration and protects the integrity of underlying Cu layer. Polycrystalline (BaxSr1-x)TiO3 (BST) thin films were subsequently deposited on the Cu-based bottom electrode by RF magnetron sputtering to investigate the interaction between the oxide and Cu layers. The thickness of the interfacial layer and interface roughness play critical roles in the optimization of the electrical performance of the BST capacitors using Cu-based electrode. It was determined that BST deposition at moderate temperature followed by rapid thermal annealing in pure oxygen yields BST/Cu capacitors with good electrical properties for application to high frequency devices. The knowledge obtained on the study of barrier properties of TiAl inspired a continuous research on the materials science issues related to the application of the hybrid TiAlOx, as high-k gate dielectric in MOSFET devices. Novel fabrication process such as deposition of ultra-thin TiAl alloy layer followed by oxidation with atomic oxygen has been established in this study. Stoichiometric amorphous TiAlOx layers, exhibiting only Ti4+ and Al3+ states, were produced with a large variation of oxidation temperature (700°C to room temperature). The interfacial SiOx formation between TiAlOx and Si was substantially inhibited by the use of the low temperature oxidation process. Electrical characterization revealed a large permittivity of 30 and an improved band structure for the produced TiAlOx layers, compared with pure TiO2. A modified 3-element model was adopted to extract the true C-V behavior of the TiAlOx-based MOS capacitor. Extremely small equivalent oxide thickness (EOT) less than 0.5 nm with dielectric leakage 4˜5 magnitude lower than that for SiO2 has been achieved on TiAlOx layer as a result of its excellent dielectric properties.

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

NASA Astrophysics Data System (ADS)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Water-gel for gating graphene transistors.

PubMed

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Through thick and thin: tuning the threshold voltage in organic field-effect transistors.

PubMed

Martínez Hardigree, Josué F; Katz, Howard E

2014-04-15

Organic semiconductors (OSCs) constitute a class of organic materials containing densely packed, overlapping conjugated molecular moieties that enable charge carrier transport. Their unique optical, electrical, and magnetic properties have been investigated for use in next-generation electronic devices, from roll-up displays and radiofrequency identification (RFID) to biological sensors. The organic field-effect transistor (OFET) is the key active element for many of these applications, but the high values, poor definition, and long-term instability of the threshold voltage (V(T)) in OFETs remain barriers to realization of their full potential because the power and control circuitry necessary to compensate for overvoltages and drifting set points decrease OFET practicality. The drifting phenomenon has been widely observed and generally termed "bias stress." Research on the mechanisms responsible for this poor V(T) control has revealed a strong dependence on the physical order and chemical makeup of the interfaces between OSCs and adjacent materials in the OFET architecture. In this Account, we review the state of the art for tuning OFET performance via chemical designs and physical processes that manipulate V(T). This parameter gets to the heart of OFET operation, as it determines the voltage regimes where OFETs are either ON or OFF, the basis for the logical function of the devices. One obvious way to decrease the magnitude and variability of V(T) is to work with thinner and higher permittivity gate dielectrics. From the perspective of interfacial engineering, we evaluate various methods that we and others have developed, from electrostatic poling of gate dielectrics to molecular design of substituted alkyl chains. Corona charging of dielectric surfaces, a method for charging the surface of an insulating material using a constant high-voltage field, is a brute force means of shifting the effective gate voltage applied to a gate dielectric. A gentler and more direct method is to apply surface voltage to dielectric interfaces by direct contact or postprocess biasing; these methods could also be adapted for high throughput printing sequences. Dielectric hydrophobicity is an important chemical property determining the stability of the surface charges. Functional organic monolayers applied to dielectrics, using the surface attachment chemistry made available from "self-assembled" monolayer chemistry, provide local electric fields without any biasing process at all. To the extent that the monolayer molecules can be printed, these are also suitable for high throughput processes. Finally, we briefly consider V(T) control in the context of device integration and reliability, such as the role of contact resistance in affecting this parameter.

Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs

NASA Astrophysics Data System (ADS)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena

2016-03-01

Many passivation dielectrics are pursued for suppressing current collapse due to trapping/detrapping of access-region surface traps in AlGaN/GaN based metal oxide semiconductor heterojuction field effect transistors (MOS-HFETs). The suppression of current collapse can potentially be achieved either by reducing the interaction of surface traps with the gate via surface leakage current reduction, or by eliminating surface traps that can interact with the gate. But, the latter is undesirable since a high density of surface donor traps is required to sustain a high 2D electron gas density at the AlGaN/GaN heterointerface and provide a low ON-resistance. This presents a practical trade-off wherein a passivation dielectric with the optimal surface trap characteristics and minimal surface leakage is to be chosen. In this work, we compare MOS-HFETs fabricated with popular ALD gate/passivation dielectrics like SiO2, Al2O3, HfO2 and HfAlO along with an additional thick plasma-enhanced chemical vapor deposition SiO2 passivation. It is found that after annealing in N2 at 700 °C, the stack containing ALD HfAlO provides a combination of low surface leakage and a high density of shallow donor traps. Physics-based TCAD simulations confirm that this combination of properties helps quick de-trapping and minimal current collapse along with a low ON resistance.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Diamond field effect transistors with a high-dielectric constant Ta2O5 as gate material

NASA Astrophysics Data System (ADS)

Liu, J.-W.; Liao, M.-Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

2014-06-01

A Ta2O5/Al2O3 bilayer gate oxide with a high-dielectric constant (high-k) has been successfully applied to a hydrogenated-diamond (H-diamond) metal-insulator-semiconductor field effect transistor (MISFET). The Ta2O5 layer is prepared by a sputtering-deposition (SD) technique on the Al2O3 buffer layer fabricated by an atomic layer deposition (ALD) technique. The ALD-Al2O3 plays an important role to eliminate plasma damage for the H-diamond surface during SD-Ta2O5 deposition. The dielectric constants of the SD-Ta2O5/ALD-Al2O3 bilayer and single SD-Ta2O5 are as large as 12.7 and 16.5, respectively. The k value of the single SD-Ta2O5 in this study is in good agreement with that of the SD-Ta2O5 on oxygen-terminated diamond. The capacitance-voltage characteristic suggests low interfacial trapped charge density for the SD-Ta2O5/ALD-Al2O3/H-diamond MIS diode. The MISFET with a gate length of 4 µm has a drain current maximum and an extrinsic transconductance of -97.7 mA mm-1 (normalized by gate width) and 31.0 ± 0.1 mS mm-1, respectively. The effective mobility in the H-diamond channel layer is found to be 70.1 ± 0.5 cm2 V-1 s-1.

TiO2-Based Indium Phosphide Metal-Oxide-Semiconductor Capacitor with High Capacitance Density.

PubMed

Cheng, Chun-Hu; Hsu, Hsiao-Hsuan; Chou, Kun-i

2015-04-01

We report a low-temperature InP p-MOS with a high capacitance density of 2.7 µF/cm2, low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.

Giant enhancement in Goos-Hänchen shift at the singular phase of a nanophotonic cavity

NASA Astrophysics Data System (ADS)

Sreekanth, Kandammathe Valiyaveedu; Ouyang, Qingling; Han, Song; Yong, Ken-Tye; Singh, Ranjan

2018-04-01

In this letter, we experimentally demonstrate thirtyfold enhancement in Goos-Hänchen shift at the Brewster angle of a nanophotonic cavity that operates at the wavelength of 632.8 nm. In particular, the point-of-darkness and the singular phase are achieved using a four-layered metal-dielectric-dielectric-metal asymmetric Fabry-Perot cavity. A highly absorbing ultra-thin layer of germanium in the stack gives rise to the singular phase and the enhanced Goos-Hänchen shift at the point-of-darkness. The obtained giant Goos-Hänchen shift in the lithography-free nanophotonic cavity could enable many intriguing applications including cost-effective label-free biosensors.

Impact of gate geometry on ionic liquid gated ionotronic systems

DOE PAGES

Wong, Anthony T.; Noh, Joo Hyon; Pudasaini, Pushpa Raj; ...

2017-01-23

Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard “side gate” 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. Finally, these findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

Small signal measurement of Sc 2O 3 AlGaN/GaN moshemts

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kang, B. S.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J. K.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2004-02-01

The rf performance of 1 × 200 μm 2 AlGaN/GaN MOS-HEMTs with Sc 2O 3 used as both the gate dielectric and as a surface passivation layer is reported. A maximum fT of ˜11 GHz and fMAX of 19 GHz were obtained. The equivalent device parameters were extracted by fitting this data to obtain the transconductance, drain resistance, drain-source resistance, transfer time and gate-drain and gate-source capacitance as a function of gate voltage. The transfer time is in the order 0.5-1 ps and decreases with increasing gate voltage.

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

NASA Astrophysics Data System (ADS)

Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

2016-02-01

A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

Semiconductor/dielectric interface engineering and characterization

NASA Astrophysics Data System (ADS)

Lucero, Antonio T.

The focus of this dissertation is the application and characterization of several, novel interface passivation techniques for III-V semiconductors, and the development of an in-situ electrical characterization. Two different interface passivation techniques were evaluated. The first is interface nitridation using a nitrogen radical plasma source. The nitrogen radical plasma generator is a unique system which is capable of producing a large flux of N-radicals free of energetic ions. This was applied to Si and the surface was studied using x-ray photoelectron spectroscopy (XPS). Ultra-thin nitride layers could be formed from 200-400° C. Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated using this passivation technique. Interface nitridation was able to reduce leakage current and improve the equivalent oxide thickness of the devices. The second passivation technique studied is the atomic layer deposition (ALD) diethylzinc (DEZ)/water treatment of sulfur treated InGaAs and GaSb. On InGaAs this passivation technique is able to chemically reduce higher oxidation states on the surface, and the process results in the deposition of a ZnS/ZnO interface passivation layer, as determined by XPS. Capacitance-voltage (C-V) measurements of MOSCAPs made on p-InGaAs reveal a large reduction in accumulation dispersion and a reduction in the density of interfacial traps. The same technique was applied to GaSb and the process was studied in an in-situ half-cycle XPS experiment. DEZ/H2O is able to remove all Sb-S from the surface, forming a stable ZnS passivation layer. This passivation layer is resistant to further reoxidation during dielectric deposition. The final part of this dissertation is the design and construction of an ultra-high vacuum cluster tool for in-situ electrical characterization. The system consists of three deposition chambers coupled to an electrical probe station. With this setup, devices can be processed and subsequently electrically characterized without exposing the sample to air. This is the first time that such a system has been reported. A special air-gap C-V probe will allow top gated measurements to be made, allowing semiconductor-dielectric interfaces to be studied during device processing.

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a substantial improvement over SiO(N) dielectrics, allowing for increased device scaling. High-temperature processing, consistent with the source/drain activation anneal in MOSFET processing, is performed on lanthanum-silicate based MOS devices with Ta or TaN gate electrodes and a W metal capping layer. The thermal limit of Ta is observed to be less than 800°C, resulting in a phase transformation that can result in uncontrolled shifting of the MOS device flat-band voltage. TaN is observed to be more thermally stable (up to 1000°C) and results in an increase in the capacitance density suggesting that it impedes oxygen reaction with silicon to produce SiO2. It is later observed that a W metal capping layer can serve as a high-oxygen source, which results in an increased interfacial SiO2 formation. By limiting the oxygen content in the W capping layer and by utilizing a thermally stable TaN gate electrode, control over the electrical properties of the MOS device is acquired. To determine the stability of amorphous lanthanum-silicate in contact with investigated by means of back-side secondary ion mass spectroscopy profiling. The results are the first reported data showing that the lanthanum incorporated in the silica matrix doe not diffuse into the silicon substrate after high temperature processing. The decrease in the device effective work function (φM,eff ) observed in these samples is examined in detail. First, as a La 2O3 capping layer on HfSiO(N), the shift yields ideal-φ M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of φM,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

PubMed

Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

Comparison of structural and electrical properties of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for α-InGaZnO thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw; Chen, Ching-Hung; Her, Jim-Long

We compared the structural properties and electrical characteristics of high-κ Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for amorphous indium-gallium-zinc oxide (α-InGaZnO) thin-film transistor (TFT) applications. The Lu{sub 2}O{sub 3} film has a strong Lu{sub 2}O{sub 3} (400) peak in the X-ray diffraction pattern, while the Lu{sub 2}TiO{sub 5} sample shows a relatively weak Lu{sub 2}TiO{sub 5} (102) peak. Atomic force microscopy reveals that the Lu{sub 2}O{sub 3} dielectric exhibits a rougher surface (about three times) than Lu{sub 2}TiO{sub 5} one. In X-ray photoelectron spectroscopy analysis, we found that the intensity of the O 1s peak corresponding tomore » Lu(OH){sub x} for Lu{sub 2}O{sub 3} film was higher than that of Lu{sub 2}TiO{sub 5} film. Furthermore, compared with the Lu{sub 2}O{sub 3} dielectric, the α-InGaZnO TFT using the Lu{sub 2}TiO{sub 5} gate dielectric exhibited a lower threshold voltage (from 0.43 to 0.25 V), a higher I{sub on}/I{sub off} current ratio (from 3.5 × 10{sup 6} to 1.3 × 10{sup 8}), a smaller subthreshold swing (from 276 to 130 mV/decade), and a larger field-effect mobility (from 14.5 to 24.4 cm{sup 2}/V s). These results are probably due to the incorporation of TiO{sub x} into the Lu{sub 2}O{sub 3} film to form a Lu{sub 2}TiO{sub 5} structure featuring a smooth surface, a low moisture absorption, a high dielectric constant, and a low interface state density at the oxide/channel interface. Furthermore, the stability of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} α-InGaZnO TFTs was investigated under positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS). The threshold voltage of the TFT performed under NGBS is more degradation than that under PGBS. This behavior may be attributed to the electron charge trapping at the dielectric–channel interface under PGBS, whereas the oxygen vacancies occurred in the InGaZnO under NGBS.« less

An ultra-thin compact polarization-independent hexa-band metamaterial absorber

NASA Astrophysics Data System (ADS)

Munaga, Praneeth; Bhattacharyya, Somak; Ghosh, Saptarshi; Srivastava, Kumar Vaibhav

2018-04-01

In this paper, an ultra-thin compact hexa-band metamaterial absorber has been presented using single layer of dielectric. The proposed design is polarization independent in nature owing to its fourfold symmetry and exhibits high angular stability up to 60° angles of incidences for both TE and TM polarizations. The structure is ultrathin in nature with 2 mm thickness, which corresponds to λ/11.4 ( λ is the operating wavelength with respect to the highest frequency of absorption). Six distinct absorption frequencies are obtained from the design, which can be distributed among three regions, namely lower band, middle band and higher band; each region consists of two closely spaced frequencies. Thereafter, the dimensions of the proposed structure are adjusted in such a way that bandwidth enhancement occurs at each region separately. Simultaneous bandwidth enhancements at middle and higher bands have also been achieved by proper optimization of the geometrical parameters. The structure with simultaneous bandwidth enhancements at X- and Ku-bands is later fabricated and the experimental absorptivity response is in agreement with the simulated one.

The effects of dielectric decrement and finite ion size on differential capacitance of electrolytically gated graphene

NASA Astrophysics Data System (ADS)

Daniels, Lindsey; Scott, Matthew; Mišković, Z. L.

2018-06-01

We analyze the effects of dielectric decrement and finite ion size in an aqueous electrolyte on the capacitance of a graphene electrode, and make comparisons with the effects of dielectric saturation combined with finite ion size. We first derive conditions for the cross-over from a camel-shaped to a bell-shaped capacitance of the diffuse layer. We show next that the total capacitance is dominated by a V-shaped quantum capacitance of graphene at low potentials. A broad peak develops in the total capacitance at high potentials, which is sensitive to the ion size with dielectric saturation, but is stable with dielectric decrement.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Control of spontaneous emission of quantum dots using correlated effects of metal oxides and dielectric materials

NASA Astrophysics Data System (ADS)

Sadeghi, S. M.; Wing, W. J.; Gutha, R. R.; Capps, L.

2017-03-01

We study the emission dynamics of semiconductor quantum dots in the presence of the correlated impact of metal oxides and dielectric materials. For this we used layered material structures consisting of a base substrate, a dielectric layer, and an ultrathin layer of a metal oxide. After depositing colloidal CdSe/ZnS quantum dots on the top of the metal oxide, we used spectral and time-resolved techniques to show that, depending on the type and thickness of the dielectric material, the metal oxide can characteristically change the interplay between intrinsic excitons, defect states, and the environment, offering new material properties. Our results show that aluminum oxide, in particular, can strongly change the impact of amorphous silicon on the emission dynamics of quantum dots by balancing the intrinsic near band emission and fast trapping of carriers. In such a system the silicon/aluminum oxide charge barrier can lead to large variation of the radiative lifetime of quantum dots and control of the photo-ejection rate of electrons in quantum dots. The results provide unique techniques to investigate and modify physical properties of dielectrics and manage optical and electrical properties of quantum dots.

Control of spontaneous emission of quantum dots using correlated effects of metal oxides and dielectric materials.

PubMed

Sadeghi, S M; Wing, W J; Gutha, R R; Capps, L

2017-03-03

We study the emission dynamics of semiconductor quantum dots in the presence of the correlated impact of metal oxides and dielectric materials. For this we used layered material structures consisting of a base substrate, a dielectric layer, and an ultrathin layer of a metal oxide. After depositing colloidal CdSe/ZnS quantum dots on the top of the metal oxide, we used spectral and time-resolved techniques to show that, depending on the type and thickness of the dielectric material, the metal oxide can characteristically change the interplay between intrinsic excitons, defect states, and the environment, offering new material properties. Our results show that aluminum oxide, in particular, can strongly change the impact of amorphous silicon on the emission dynamics of quantum dots by balancing the intrinsic near band emission and fast trapping of carriers. In such a system the silicon/aluminum oxide charge barrier can lead to large variation of the radiative lifetime of quantum dots and control of the photo-ejection rate of electrons in quantum dots. The results provide unique techniques to investigate and modify physical properties of dielectrics and manage optical and electrical properties of quantum dots.

Gate dielectric surface treatments for performance improvement of poly(3-hexylthiophene-2,5-diyl) based organic field-effect transistors

NASA Astrophysics Data System (ADS)

Nawaz, Ali; de, Cristiane, , Col; Cruz-Cruz, Isidro; Kumar, Anshu; Kumar, Anil; Hümmelgen, Ivo A.

2015-08-01

We report on enhanced performance in poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic field effect transistors (OFETs) achieved by improvement in hole transport along the channel near the insulator/semiconductor (I/S) interface. The improvement in hole transport is demonstrated to occur very close to the I/S interface, after treatment of the insulator layer with sodium dodecyl sulfate (SDS). SDS is an anionic surfactant, with negatively charged heads, known for formation of micelles above critical micelle concentration (CMC), which contribute to the passivation of positively charged traps. Investigation of field-effect mobility (μFET) as a function of channel bottleneck thickness in OFETs reveals the favorable gate voltage regime where mobility is the highest. In addition, it shows that the gate dielectric surface treatment not only leads to an increase in mobility in that regime, but also displaces charge transport closer to the interface, hence pointing toward passivation of the charge traps at I/S interface. OFETs with SDS treatment were compared with untreated and vitamin C or hexadecyltrimethylammonium bromide (CTAB) treated OFETs. All the treatments resulted in significant improvements in specific dielectric capacitance, μFET, on/off current ratio and transconductance.

Epitaxial pentacene films grown on the surface of ion-beam-processed gate dielectric layer

NASA Astrophysics Data System (ADS)

Chou, W. Y.; Kuo, C. W.; Cheng, H. L.; Mai, Y. S.; Tang, F. C.; Lin, S. T.; Yeh, C. Y.; Horng, J. B.; Chia, C. T.; Liao, C. C.; Shu, D. Y.

2006-06-01

The following research describes the process of fabrication of pentacene films with submicron thickness, deposited by thermal evaporation in high vacuum. The films were fabricated with the aforementioned conditions and their characteristics were analyzed using x-ray diffraction, scanning electron microscopy, polarized Raman spectroscopy, and photoluminescence. Organic thin-film transistors (OTFTs) were fabricated on an indium tin oxide coated glass substrate, using an active layer of ordered pentacene molecules, which were grown at room temperature. Pentacene film was aligned using the ion-beam aligned method, which is typically employed to align liquid crystals. Electrical measurements taken on a thin-film transistor indicated an increase in the saturation current by a factor of 15. Pentacene-based OTFTs with argon ion-beam-processed gate dielectric layers of silicon dioxide, in which the direction of the ion beam was perpendicular to the current flow, exhibited a mobility that was up to an order of magnitude greater than that of the controlled device without ion-beam process; current on/off ratios of approximately 106 were obtained. Polarized Raman spectroscopy investigation indicated that the surface of the gate dielectric layer, treated with argon ion beam, enhanced the intermolecular coupling of pentacene molecules. The study also proposes the explanation for the mechanism of carrier transportation in pentacene films.

Hybrid bilayer plasmonic metasurface efficiently manipulates visible light.

PubMed

Qin, Fei; Ding, Lu; Zhang, Lei; Monticone, Francesco; Chum, Chan Choy; Deng, Jie; Mei, Shengtao; Li, Ying; Teng, Jinghua; Hong, Minghui; Zhang, Shuang; Alù, Andrea; Qiu, Cheng-Wei

2016-01-01

Metasurfaces operating in the cross-polarization scheme have shown an interesting degree of control over the wavefront of transmitted light. Nevertheless, their inherently low efficiency in visible light raises certain concerns for practical applications. Without sacrificing the ultrathin flat design, we propose a bilayer plasmonic metasurface operating at visible frequencies, obtained by coupling a nanoantenna-based metasurface with its complementary Babinet-inverted copy. By breaking the radiation symmetry because of the finite, yet small, thickness of the proposed structure and benefitting from properly tailored intra- and interlayer couplings, such coupled bilayer metasurface experimentally yields a conversion efficiency of 17%, significantly larger than that of earlier single-layer designs, as well as an extinction ratio larger than 0 dB, meaning that anomalous refraction dominates the transmission response. Our finding shows that metallic metasurface can counterintuitively manipulate the visible light as efficiently as dielectric metasurface (~20% in conversion efficiency in Lin et al.'s study), although the metal's ohmic loss is much higher than dielectrics. Our hybrid bilayer design, still being ultrathin (~λ/6), is found to obey generalized Snell's law even in the presence of strong couplings. It is capable of efficiently manipulating visible light over a broad bandwidth and can be realized with a facile one-step nanofabrication process.

Bar-Coated Ultrathin Semiconductors from Polymer Blend for One-Step Organic Field-Effect Transistors.

PubMed

Ge, Feng; Liu, Zhen; Lee, Seon Baek; Wang, Xiaohong; Zhang, Guobing; Lu, Hongbo; Cho, Kilwon; Qiu, Longzhen

2018-06-27

One-step deposition of bi-functional semiconductor-dielectric layers for organic field-effect transistors (OFETs) is an effective way to simplify the device fabrication. However, the proposed method has rarely been reported in large-area flexible organic electronics. Herein, we demonstrate wafer-scale OFETs by bar coating the semiconducting and insulating polymer blend solution in one-step. The semiconducting polymer poly(3-hexylthiophene) (P3HT) segregates on top of the blend film, whereas dielectric polymethyl methacrylate (PMMA) acts as the bottom layer, which is achieved by a vertical phase separation structure. The morphology of blend film can be controlled by varying the concentration of P3HT and PMMA solutions. The wafer-scale one-step OFETs, with a continuous ultrathin P3HT film of 2.7 nm, exhibit high electrical reproducibility and uniformity. The one-step OFETs extend to substrate-free arrays that can be attached everywhere on varying substrates. In addition, because of the well-ordered molecular arrangement, the moderate charge transport pathway is formed, which resulted in stable OFETs under various organic solvent vapors and lights of different wavelengths. The results demonstrate that the one-step OFETs have promising potential in the field of large-area organic wearable electronics.

Hybrid bilayer plasmonic metasurface efficiently manipulates visible light

PubMed Central

Qin, Fei; Ding, Lu; Zhang, Lei; Monticone, Francesco; Chum, Chan Choy; Deng, Jie; Mei, Shengtao; Li, Ying; Teng, Jinghua; Hong, Minghui; Zhang, Shuang; Alù, Andrea; Qiu, Cheng-Wei

2016-01-01

Metasurfaces operating in the cross-polarization scheme have shown an interesting degree of control over the wavefront of transmitted light. Nevertheless, their inherently low efficiency in visible light raises certain concerns for practical applications. Without sacrificing the ultrathin flat design, we propose a bilayer plasmonic metasurface operating at visible frequencies, obtained by coupling a nanoantenna-based metasurface with its complementary Babinet-inverted copy. By breaking the radiation symmetry because of the finite, yet small, thickness of the proposed structure and benefitting from properly tailored intra- and interlayer couplings, such coupled bilayer metasurface experimentally yields a conversion efficiency of 17%, significantly larger than that of earlier single-layer designs, as well as an extinction ratio larger than 0 dB, meaning that anomalous refraction dominates the transmission response. Our finding shows that metallic metasurface can counterintuitively manipulate the visible light as efficiently as dielectric metasurface (~20% in conversion efficiency in Lin et al.’s study), although the metal’s ohmic loss is much higher than dielectrics. Our hybrid bilayer design, still being ultrathin (~λ/6), is found to obey generalized Snell’s law even in the presence of strong couplings. It is capable of efficiently manipulating visible light over a broad bandwidth and can be realized with a facile one-step nanofabrication process. PMID:26767195

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

NASA Astrophysics Data System (ADS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Micromachined mold-type double-gated metal field emitters

NASA Astrophysics Data System (ADS)

Lee, Yongjae; Kang, Seokho; Chun, Kukjin

1997-12-01

Electron field emitters with double gates were fabricated using micromachining technology and the effect of the electric potential of the focusing gate (or second gate) was experimentally evaluated. The molybdenum field emission tip was made by filling a cusplike mold formed when a conformal film was deposited on the hole-trench that had been patterned on stacked metals and dielectric layers. The hole-trench was patterned by electron beam lithography and reactive ion etching. Each field emitter has a 0960-1317/7/4/009/img1 diameter extraction gate (or first gate) and a 0960-1317/7/4/009/img2 diameter focusing gate (or second gate). To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP (ethylene-diamine pyrocatechol) solution successively. The I - V characteristics and anode current change due to the focusing gate potential were measured.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

NASA Astrophysics Data System (ADS)

Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

2018-01-01

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Strain-induced phase variation and dielectric constant enhancement of epitaxial Gd{sub 2}O{sub 3}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shekhter, P., E-mail: Pini@tx.technion.ac.il; Amouyal, Y.; Eizenberg, M.

2016-07-07

One of the approaches for realizing advanced high k insulators for metal oxide semiconductor field effect transistors based devices is the use of rare earth oxides. When these oxides are deposited as epitaxial thin films, they demonstrate dielectric properties that differ greatly from those that are known for bulk oxides. Using structural and spectroscopic techniques, as well as first-principles calculations, Gd{sub 2}O{sub 3} films deposited on Si (111) and Ge (111) were characterized. It was seen that the same 4 nm thick film, grown simultaneously on Ge and Si, presents an unstrained lattice on Ge while showing a metastable phase onmore » Si. This change from the cubic lattice to the distorted metastable phase is characterized by an increase in the dielectric constant of more than 30% and a change in band gap. The case in study shows that extreme structural changes can occur in ultra-thin epitaxial rare earth oxide films and modify their dielectric properties when the underlying substrate is altered.« less

Voltage Scaling of Graphene Device on SrTiO3 Epitaxial Thin Film.

PubMed

Park, Jeongmin; Kang, Haeyong; Kang, Kyeong Tae; Yun, Yoojoo; Lee, Young Hee; Choi, Woo Seok; Suh, Dongseok

2016-03-09

Electrical transport in monolayer graphene on SrTiO3 (STO) thin film is examined in order to promote gate-voltage scaling using a high-k dielectric material. The atomically flat surface of thin STO layer epitaxially grown on Nb-doped STO single-crystal substrate offers good adhesion between the high-k film and graphene, resulting in nonhysteretic conductance as a function of gate voltage at all temperatures down to 2 K. The two-terminal conductance quantization under magnetic fields corresponding to quantum Hall states survives up to 200 K at a magnetic field of 14 T. In addition, the substantial shift of charge neutrality point in graphene seems to correlate with the temperature-dependent dielectric constant of the STO thin film, and its effective dielectric properties could be deduced from the universality of quantum phenomena in graphene. Our experimental data prove that the operating voltage reduction can be successfully realized due to the underlying high-k STO thin film, without any noticeable degradation of graphene device performance.

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

NASA Astrophysics Data System (ADS)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Ambipolar transport of silver nanoparticles decorated graphene oxide field effect transistors

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan Jyoti; Sarkar, K.; Pal, B.; Kumar, Aparabal; Das, Anish; Banerji, P.

2018-05-01

In this article, we report ambipolar field effect transistor (FET) by using graphene oxide (GO) as a gate dielectric material for silver nanoparticles (AgNPs) decorated GO channel layer. GO was synthesized by Hummers' method. The AgNPs were prepared via photochemical reduction of silver nitrate solution by using monoethanolamine as a reducing agent. Morphological properties of channel layer were characterized by Field Effect Scanning Electron Microscopy (FESEM). Fourier Transform Infrared Spectroscopy (FTIR) was carried out to characterize GO thin film. For device fabrication gold (Au) was deposited as source-drain contact and aluminum (Al) was taken as bottom contact. Electrical measurements were performed by back gate configuration. Ambipolar transport behavior was explained from transfer characteristics. A maximum electron mobiliy of 6.65 cm2/Vs and a hole mobility of 2.46 cm2/Vs were extracted from the transfer characteristics. These results suggest that GO is a potential candidate as a gate dielectric material for thin film transistor applications and also provides new insights in GO based research.

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

PubMed

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

Separation and counting of single molecules through nanofluidics, programmable electrophoresis, and nanoelectrode-gated tunneling and dielectric detection

DOEpatents

Lee, James W.; Thundat, Thomas G.

2006-04-25

An apparatus for carrying out the separation, detection, and/or counting of single molecules at nanometer scale. Molecular separation is achieved by driving single molecules through a microfluidic or nanofluidic medium using programmable and coordinated electric fields. In various embodiments, the fluidic medium is a strip of hydrophilic material on nonconductive hydrophobic surface, a trough produced by parallel strips of hydrophobic nonconductive material on a hydrophilic base, or a covered passageway produced by parallel strips of hydrophobic nonconductive material on a hydrophilic base together with a nonconductive cover on the parallel strips of hydrophobic nonconductive material. The molecules are detected and counted using nanoelectrode-gated electron tunneling methods, dielectric monitoring, and other methods.

Large Bandgap Shrinkage from Doping and Dielectric Interface in Semiconducting Carbon Nanotubes

NASA Astrophysics Data System (ADS)

Comfort, Everett; Lee, Ji Ung

2016-06-01

The bandgap of a semiconductor is one of its most important electronic properties. It is often considered to be a fixed property of the semiconductor. As the dimensions of semiconductors reduce, however, many-body effects become dominant. Here, we show that doping and dielectric, two critical features of semiconductor device manufacturing, can dramatically shrink (renormalize) the bandgap. We demonstrate this in quasi-one-dimensional semiconducting carbon nanotubes. Specifically, we use a four-gated device, configured as a p-n diode, to investigate the fundamental electronic structure of individual, partially supported nanotubes of varying diameter. The four-gated construction allows us to combine both electrical and optical spectroscopic techniques to measure the bandgap over a wide doping range.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Zhang, Zhili; Song, Liang; Li, Weiyi; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Fan, Yaming; Deng, Xuguang; Li, Shuiming; Sun, Shichuang; Li, Xiajun; Yuan, Jie; Sun, Qian; Dong, Zhihua; Cai, Yong; Zhang, Baoshun

2017-08-01

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel-Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

Scaling of Device Variability and Subthreshold Swing in Ballistic Carbon Nanotube Transistors

NASA Astrophysics Data System (ADS)

Cao, Qing; Tersoff, Jerry; Han, Shu-Jen; Penumatcha, Ashish V.

2015-08-01

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one-dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of the nanotube device uniformity with the gate dielectric, fixed-charge density, and device dimension is qualitatively different from conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate-oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

High Efficient Ultra-Thin Flat Optics Based on Dielectric Metasurfaces

NASA Astrophysics Data System (ADS)

Ozdemir, Aytekin

Metasurfaces which emerged as two-dimensional counterparts of metamaterials, facilitate the realization of arbitrary phase distributions using large arrays with subwavelength and ultra-thin features. Even if metasurfaces are ultra-thin, they still effectively manipulate the phase, amplitude, and polarization of light in transmission or reflection mode. In contrast, conventional optical components are bulky, and they lose their functionality at sub-wavelength scales, which requires conceptually new types of nanoscale optical devices. On the other hand, as the optical systems shrink in size day by day, conventional bulky optical components will have tighter alignment and fabrication tolerances. Since metasurfaces can be fabricated lithographically, alignment can be done during lithographic fabrication, thus eliminating the need for post-fabrication alignments. In this work, various types of metasurface applications are thoroughly investigated for robust wavefront engineering with enhanced characteristics in terms of broad bandwidth, high efficiency and active tunability, while beneficial for application. Plasmonic metasurfaces are not compatible with the CMOS process flow, and, additionally their high absorption and ohmic loss is problematic in transmission based applications. Dielectric metasurfaces, however, offer a strong magnetic response at optical frequencies, and thus they can offer great opportunities for interacting not only with the electric component of a light field, but also with its magnetic component. They show great potential to enable practical device functionalities at optical frequencies, which motivates us to explore them one step further on wavefront engineering and imaging sensor platforms. Therefore, we proposed an efficient ultra-thin flat metalens at near-infrared regime constituted by silicon nanodisks which can support both electric and magnetic dipolar Mie-type resonances. These two dipole resonances can be overlapped at the same frequency by varying the geometric parameters of silicon nanodisks. Having two resonance mechanisms at the same frequency allows us to achieve full (0-2?) phase shift on the transmitted beam. To enable the miniaturization of pixel size for achieving high-resolution, planar, compact-size focal plane arrays (FPAs), we also present and explore the metasurface lens array-based FPAs. The investigated dielectric metasurface lens arrays achieved high focusing efficiency with superior optical crosstalk performance. We see a magnificent application prospect for metasurfaces in enhancing the fill factor and reducing the pixel size of FPAs and CCD, CMOS imaging sensors as well. Moreover, it is of paramount importance to design metasurfaces possessing tunable properties. Thus, we also propose a tunable beam steering device by combining phase manipulating metasurfaces concept and liquid crystals. Tunability feature is implemented by nematic liquid crystals infiltrated into nano holes in SiO2. Using electrically tunable nematic liquid crystals, dynamic beam steering is achieved.

Towards colorless transparent organic transistors: potential of benzothieno[3,2-b]benzothiophene-based wide-gap semiconductors.

PubMed

Moon, Hanul; Cho, Hyunsu; Kim, Mincheol; Takimiya, Kazuo; Yoo, Seunghyup

2014-05-21

Colorless, highly transparent organic thin-film transistors (TOTFTs) with high performance are realized based on benzothieno[3,2-b]benzothiophene (BTBT) derivatives that simultaneously exhibit a wide energy gap and high transport properties. Multilayer transparent source/drain electrodes maintain the transparency, and ultrathin fluoropolymer dielectric layers enable stable, low-voltage operation of the proposed TOTFTs. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Amorphous Boron Nitride: A Universal, Ultrathin Dielectric for 2D Nanoelectronics (Postprint)

DTIC Science & Technology

2015-03-21

the C-AFM technique using the linear breakdown method when the current reaches 1 nA. [ 44 ] The breakdown is characterized by a sharp increase in...423 . [15] K. Watanabe , T. Taniguchi , H. Kanda , Nat. Mater. 2004 , 3 , 404 . [16] A. Soltani , A. Talbi , V. Mortet , A...Phys. Lett. 2011 , 99 , 243114 . [36] Y. Hattori , T. Taniguchi , K. Watanabe , K. Nagashio , ACS Nano 2014 , 9 , 916 . [37] S. N

Organic Electronic Devices Using Crosslinked Polyelectrolyte Multilayers as an Ultra-Thin Dielectric Material

DTIC Science & Technology

2006-09-01

energy band diagram illustrating the allowed energies for valence and conducting electrons. The dashes within the band gap (Eg) represent localized ...allowed energies for valence and conducting electrons. The dashes within the band gap (Eg) represent localized electron energy states, or traps, that...been observed with the formation of alternating bond lengths along the backbone.43 The localization of the π-electrons while forming the shorter double

Stable organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

DOE PAGES

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; ...

2018-01-12

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V-1 s-1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperatureovertimeperiods upto5.9×105 s do not vary monotonically andmore » remain below 0.2 V in microcrystalline OTFTs (mc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies.« less

Stable organic thin-film transistors

PubMed Central

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Park, Youngrak; Kippelen, Bernard

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies. PMID:29340301

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Effect of Polymer Gate Dielectrics on Charge Transport in Carbon Nanotube Network Transistors: Low-k Insulator for Favorable Active Interface.

PubMed

Lee, Seung-Hoon; Xu, Yong; Khim, Dongyoon; Park, Won-Tae; Kim, Dong-Yu; Noh, Yong-Young

2016-11-30

Charge transport in carbon nanotube network transistors strongly depends on the properties of the gate dielectric that is in direct contact with the semiconducting carbon nanotubes. In this work, we investigate the dielectric effects on charge transport in polymer-sorted semiconducting single-walled carbon nanotube field-effect transistors (s-SWNT-FETs) by using three different polymer insulators: A low-permittivity (ε r ) fluoropolymer (CYTOP, ε r = 1.8), poly(methyl methacrylate) (PMMA, ε r = 3.3), and a high-ε r ferroelectric relaxor [P(VDF-TrFE-CTFE), ε r = 14.2]. The s-SWNT-FETs with polymer dielectrics show typical ambipolar charge transport with high ON/OFF ratios (up to ∼10 5 ) and mobilities (hole mobility up to 6.77 cm 2 V -1 s -1 for CYTOP). The s-SWNT-FET with the lowest-k dielectric, CYTOP, exhibits the highest mobility owing to formation of a favorable interface for charge transport, which is confirmed by the lowest activation energies, evaluated by the fluctuation-induced tunneling model (FIT) and the traditional Arrhenius model (E aFIT = 60.2 meV and E aArr = 10 meV). The operational stability of the devices showed a good agreement with the activation energies trend (drain current decay ∼14%, threshold voltage shift ∼0.26 V in p-type regime of CYTOP devices). The poor performance in high-ε r devices is accounted for by a large energetic disorder caused by the randomly oriented dipoles in high-k dielectrics. In conclusion, the low-k dielectric forms a favorable interface with s-SWNTs for efficient charge transport in s-SWNT-FETs.

Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air.

PubMed

Esro, Mazran; Kolosov, Oleg; Jones, Peter J; Milne, William I; Adamopoulos, George

2017-01-11

Silicon dioxide (SiO 2 ) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO 2 by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO 2 thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl 4 . SiO 2 dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (R RMS < 1 nm) amorphous films with a dielectric constant of about 3.8, an optical band gap of ≈8.1 eV, leakage current densities in the order of ≈10 -7 A/cm 2 at 1 MV/cm, and high dielectric strength in excess of 5 MV/cm. XPS measurements confirm the SiO 2 stoichiometry and FTIR spectra reveal features related to SiO 2 only. Thin film transistors implementing spray-coated SiO 2 gate dielectrics and C 60 and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10 6 , and high carrier mobility.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

NASA Astrophysics Data System (ADS)

Wang, Yan-Rong; Yang, Hong; Xu, Hao; Wang, Xiao-Lei; Luo, Wei-Chun; Qi, Lu-Wei; Zhang, Shu-Xiang; Wang, Wen-Wu; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2015-11-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1-x as potential gate dielectrics for GaN/AlxGa1-xN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Partida-Manzanera, T.; Roberts, J. W.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Sedghi, N.; Tripathy, S.; Potter, R. J.

2016-01-01

This paper describes a method to optimally combine wide band gap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. (Ta2O5)x(Al2O3)1-x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped AlxGa1-xN/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta2O5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al2O3 to 4.6 eV for pure Ta2O5. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al2O3 up to 25.6 for Ta2O5. The effect of post-deposition annealing in N2 at 600 °C on the interfacial properties of undoped Al2O3 and Ta-doped (Ta2O5)0.12(Al2O3)0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al2O3/GaN-HEMT and (Ta2O5)0.16(Al2O3)0.84/GaN-HEMT samples increased by ˜1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al2O3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

NASA Astrophysics Data System (ADS)

Liu, Xiaoyu; Xu, Jingping; Liu, Lu; Cheng, Zhixiang; Huang, Yong; Gong, Jingkang

2017-08-01

The effects of different NH3-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH3-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79 × 1011 eV-1 cm-2 and low gate leakage current (3.43 × 10-5 A/cm2 at {V}{{g}}=1 {{V}}) could be achieved for the sample with NH3-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH3-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO x Ny, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH3-plasma. Project supported by the National Natural Science Foundation of China (Nos. 61176100, 61274112).

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

PubMed

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Electronic Subsystem Analysis (ESA)

DTIC Science & Technology

1977-01-01

than aluminum for the gate material, 0 Ion implanted source and draia regions, 0 Dielectrically isolated transistors. The use of a doped polysilicon gate...second level of interconnect ( polysilicon ). Ion implantation is essentially a precisely controllable pre-deposition of the required dopants. It’s use...discussed below). Radiation effects on MOS devices include the following: 0 Total Dose ol Dose Rate o Neutrons Because MOS technology is based on

Hafnium oxide films for application as gate dielectrics

NASA Astrophysics Data System (ADS)

Hsu, Shuo-Lin

The deposition and characterization of HfO2 films for potential application as a high-kappa gate dielectric in MOS devices has been investigated. DC magnetron reactive sputtering was utilized to prepare the HfO2 films. Structural, chemical, and electrical analyses were performed to characterize the various physical, chemical and electrical properties of the sputtered HfO2 films. The sputtered HfO2 films were annealed to simulate the dopant activation process used in semiconductor processing, and to study the thermal stability of the high-kappa, films. The changes in the film properties due to the annealing are also discussed in this work. Glancing angle XRD was used to analyse the atomic scale structure of the films. The as deposited films exhibit an amorphous, regardless of the film thickness. During post-deposition annealing, the thicker films crystallized at lower temperature (< 600°C), and ultra-thin (5.8 nm) film crystallized at higher temperature (600--720°C). The crystalline phase which formed depended on the thickness of the films. The low temperature phase (monoclinic) formed in the 10--20 nm annealed films, and high temperature phase (tetragonal) formed in the ultra-thin annealed HfO2 film. TEM cross-section studies of as deposited samples show that an interfacial layer (< 1nm) exists between HfO2/Si for all film thicknesses. The interfacial layer grows thicker during heat treatment, and grows more rapidly when grain boundaries are present. XPS surface analysis shows the as deposited films are fully oxidized with an excess of oxygen. Interfacial chemistry analysis indicated that the interfacial layer is a silicon-rich silicate layer, which tends to transform to silica-like layer during heat treatment. I-V measurements show the leakage current density of the Al/as deposited-HfO 2/Si MOS diode is of the order of 10-3 A/cm 2, two orders of magnitude lower than that of a ZrO2 film with similar physical thickness. Carrier transport is dominated by Schottky emission at lower electric fields, and by Frenkel-Poole emission in the higher electric field region. After annealing, the leakage current density decreases significantly as the structure remains amorphous structure. It is suggested that this decrease is assorted with the densification and defect healing which accures when the porous as-deposited amorphous structure is annealed. The leakage current density increases of the HfO2 layer crystallizes on annealing, which is attributed to the presence of grain boundaries. C-V measurements of the as deposited film shows typical C-V characteristics, with negligible hystersis, a small flat band voltage shift, but great frequency dispersion. The relative permittivity of HfO2/interfacial layer stack obtained from the capacitance at accumulation is 15, which corresponds to an EOT (equivalent oxide thickness) = 1.66 nm. After annealing, the frequency dispersion is greatly enhanced, and the C-V curve is shifted toward the negative voltage. Reliability tests show that the HfO2 films which remain amorphous after annealing possess superior resistance to constant voltage stress and ambient aging. This study concluded that the sputtered HfO 2 films exhibit an amorphous as deposited. Postdeposition annealing alters the crystallinity, interfacial properties, and electrical characteristics. The HfO2 films which remain amorphous structure after annealing possess the best electrical properties.

Energy Storage via Polyvinylidene Fluoride Dielectric on the Counterelectrode of Dye-Sensitized Solar Cells.

PubMed

Huang, Xuezhen; Zhang, Xi; Jiang, Hongrui

2014-02-15

To study the fundamental energy storage mechanism of photovoltaically self-charging cells (PSCs) without involving light-responsive semiconductor materials such as Si powder and ZnO nanowires, we fabricate a two-electrode PSC with the dual functions of photocurrent output and energy storage by introducing a PVDF film dielectric on the counterelectrode of a dye-sensitized solar cell. A layer of ultrathin Au film used as a quasi-electrode establishes a shared interface for the I - /I 3 - redox reaction and for the contact between the electrolyte and the dielectric for the energy storage, and prohibits recombination during the discharging period because of its discontinuity. PSCs with a 10-nm-thick PVDF provide a steady photocurrent output and achieve a light-to-electricity conversion efficiency ( η) of 3.38%, and simultaneously offer energy storage with a charge density of 1.67 C g -1 . Using this quasi-electrode design, optimized energy storage structures may be used in PSCs for high energy storage density.

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Gate-tunable electron interaction in high-κ dielectric films

DOE PAGES

Kondovych, Svitlana; Luk’yanchuk, Igor; Baturina, Tatyana I.; ...

2017-02-20

The two-dimensional (2D) logarithmic character of Coulomb interaction between charges and the resulting logarithmic confinement is a remarkable inherent property of high dielectric constant (high-k) thin films with far reaching implications. Most and foremost, this is the charge Berezinskii-Kosterlitz-Thouless transition with the notable manifestation, low-temperature superinsulating topological phase. Here we show that the range of the confinement can be tuned by the external gate electrode and unravel a variety of electrostatic interactions in high-k films. Lastly, our findings open a unique laboratory for the in-depth study of topological phase transitions and a plethora of related phenomena, ranging from criticality ofmore » quantum metal- and superconductor-insulator transitions to the effects of charge-trapping and Coulomb scalability in memory nanodevices.« less

Characterization of SiO{sub 2}/SiN{sub x} gate insulators for graphene based nanoelectromechanical systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tóvári, E.; Csontos, M., E-mail: csontos@dept.phy.bme.hu; Kriváchy, T.

2014-09-22

The structural and magnetotransport characterization of graphene nanodevices exfoliated onto Si/SiO{sub 2}/SiN{sub x} heterostructures are presented. Improved visibility of the deposited flakes is achieved by optimal tuning of the dielectric film thicknesses. The conductance of single layer graphene Hall-bar nanostructures utilizing SiO{sub 2}/SiN{sub x} gate dielectrics were characterized in the quantum Hall regime. Our results highlight that, while exhibiting better mechanical and chemical stability, the effect of non-stoichiometric SiN{sub x} on the charge carrier mobility of graphene is comparable to that of SiO{sub 2}, demonstrating the merits of SiN{sub x} as an ideal material platform for graphene based nanoelectromechanical applications.

Study of bulk Hafnium oxide (HfO2) under compression

NASA Astrophysics Data System (ADS)

Pathak, Santanu; Mandal, Guruprasad; Das, Parnika

2018-04-01

Hafnium oxide (HfO2) is a technologically important material. This material has K-value of 25 and band gap 5.8 eV. A k value of 25-30 is preferred for a gate dielectric [1]. As it shows good insulating and capacitive properties, HfO2 is being considered as a replacement to SiO2 in microelectronic devices as gate dielectrics. On the other hand because of toughening mechanism due to phase transformation induced by stress field observed in these oxides, HFO2 has been a material of investigations in various configurations for a very long time. However the controversies about phase transition of HfO2 under pressure still exists. High quality synchrotron radiation has been used to study the structural phase transition of HfO2 under pressure.

Computation of Dielectric Response in Molecular Solids for High Capacitance Organic Dielectrics.

PubMed

Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

2016-09-20

The dielectric response of a material is central to numerous processes spanning the fields of chemistry, materials science, biology, and physics. Despite this broad importance across these disciplines, describing the dielectric environment of a molecular system at the level of first-principles theory and computation remains a great challenge and is of importance to understand the behavior of existing systems as well as to guide the design and synthetic realization of new ones. Furthermore, with recent advances in molecular electronics, nanotechnology, and molecular biology, it has become necessary to predict the dielectric properties of molecular systems that are often difficult or impossible to measure experimentally. In these scenarios, it is would be highly desirable to be able to determine dielectric response through efficient, accurate, and chemically informative calculations. A good example of where theoretical modeling of dielectric response would be valuable is in the development of high-capacitance organic gate dielectrics for unconventional electronics such as those that could be fabricated by high-throughput printing techniques. Gate dielectrics are fundamental components of all transistor-based logic circuitry, and the combination high dielectric constant and nanoscopic thickness (i.e., high capacitance) is essential to achieving high switching speeds and low power consumption. Molecule-based dielectrics offer the promise of cheap, flexible, and mass producible electronics when used in conjunction with unconventional organic or inorganic semiconducting materials to fabricate organic field effect transistors (OFETs). The molecular dielectrics developed to date typically have limited dielectric response, which results in low capacitances, translating into poor performance of the resulting OFETs. Furthermore, the development of better performing dielectric materials has been hindered by the current highly empirical and labor-intensive pace of synthetic progress. An accurate and efficient theoretical computational approach could drastically decrease this time by screening potential dielectric materials and providing reliable design rules for future molecular dielectrics. Until recently, accurate calculation of dielectric responses in molecular materials was difficult and highly approximate. Most previous modeling efforts relied on classical formalisms to relate molecular polarizability to macroscopic dielectric properties. These efforts often vastly overestimated polarizability in the subject materials and ignored crucial material properties that can affect dielectric response. Recent advances in first-principles calculations via density functional theory (DFT) with periodic boundary conditions have allowed accurate computation of dielectric properties in molecular materials. In this Account, we outline the methodology used to calculate dielectric properties of molecular materials. We demonstrate the validity of this approach on model systems, capturing the frequency dependence of the dielectric response and achieving quantitative accuracy compared with experiment. This method is then used as a guide to new high-capacitance molecular dielectrics by determining what materials and chemical properties are important in maximizing dielectric response in self-assembled monolayers (SAMs). It will be seen that this technique is a powerful tool for understanding and designing new molecular dielectric systems, the properties of which are fundamental to many scientific areas.

Molecular Self-Assembly and Interfacial Engineering for Highly Efficient Organic Field Effect Transistors and Solar Cells

DTIC Science & Technology

2012-09-23

balance between disordered SAMs to promote large pentacene grains and thick SAMs to aid in physically buffering the charge carriers in pentacene from...to 0.76 µF/cm2), and enhanced pentacene OFET device performance such as higher charge carrier mobility, current on/off ratio, and lower threshold...surface charge trap • Tuning of surface energy • Control of surface group orientation SAM/MO ultrathin dielectric: • Low-voltage operation

Light Coupling and Trapping in Ultrathin Cu(In,Ga)Se2 Solar Cells Using Dielectric Scattering Patterns.

PubMed

van Lare, Claire; Yin, Guanchao; Polman, Albert; Schmid, Martina

2015-10-27

We experimentally demonstrate photocurrent enhancement in ultrathin Cu(In,Ga)Se2 (CIGSe) solar cells with absorber layers of 460 nm by nanoscale dielectric light scattering patterns printed by substrate conformal imprint lithography. We show that patterning the front side of the device with TiO2 nanoparticle arrays results in a small photocurrent enhancement in almost the entire 400-1200 nm spectral range due to enhanced light coupling into the cell. Three-dimensional finite-difference time-domain simulations are in good agreement with external quantum efficiency measurements. Patterning the Mo/CIGSe back interface using SiO2 nanoparticles leads to strongly enhanced light trapping, increasing the efficiency from 11.1% for a flat to 12.3% for a patterned cell. Simulations show that optimizing the array geometry could further improve light trapping. Including nanoparticles at the Mo/CIGSe interface leads to substantially reduced parasitic absorption in the Mo back contact. Parasitic absorption in the back contact can be further reduced by fabricating CIGSe cells on top of a SiO2-patterned In2O3:Sn (ITO) back contact. Simulations show that these semitransparent cells have similar spectrally averaged reflection and absorption in the CIGSe active layer as a Mo-based patterned cell, demonstrating that the absorption losses in the Mo can be partially turned into transmission through the semitransparent geometry.

Electron Transporting Semiconductor Dielectric Intramolecular

DTIC Science & Technology

2012-04-27

gate dielectric, and the capacitance times mobility was 80 nS/V (10x typical pentacene /oxide), stable to heating to 70 °C in air. Remarkably...oxide/ Pentacene Bilayer Transistors: High Mobility n-Channel, Ambipolar and Nonvolatile Devices” Adv. Funct. Mater. 18, 1832-1839 (2008) Sun, J...case of layered OSC OFETs. This proposal is somewhat different from a model by deLeeuw for amorphous OFETs13 in which carriers would be locally

Direct Effect of Dielectric Surface Energy on Carrier Transport in Organic Field-Effect Transistors.

PubMed

Zhou, Shujun; Tang, Qingxin; Tian, Hongkun; Zhao, Xiaoli; Tong, Yanhong; Barlow, Stephen; Marder, Seth R; Liu, Yichun

2018-05-09

The understanding of the characteristics of gate dielectric that leads to optimized carrier transport remains controversial, and the conventional studies applied organic semiconductor thin films, which introduces the effect of dielectric on the growth of the deposited semiconductor thin films and hence only can explore the indirect effects. Here, we introduce pregrown organic single crystals to eliminate the indirect effect (semiconductor growth) in the conventional studies and to undertake an investigation of the direct effect of dielectric on carrier transport. It is shown that the matching of the polar and dispersive components of surface energy between semiconductor and dielectric is favorable for higher mobility. This new empirical finding may show the direct relationship between dielectric and carrier transport for the optimized mobility of organic field-effect transistors and hence show a promising potential for the development of next-generation high-performance organic electronic devices.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain currentmore » after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.« less

Ultra-thin, conformal, and hydratable color-absorbers using silk protein hydrogel

NASA Astrophysics Data System (ADS)

Umar, Muhammad; Min, Kyungtaek; Jo, Minsik; Kim, Sunghwan

2018-06-01

Planar and multilayered photonic devices offer unprecedented opportunities in biological and chemical sensing due to strong light-matter interactions. However, uses of rigid substances such as semiconductors and dielectrics confront photonic devices with issues of biocompatibility and a mechanical mismatch for their application on humid, uneven, and soft biological surfaces. Here, we report that favorable material traits of natural silk protein led to the fabrication of an ultra-thin, conformal, and water-permeable (hydratable) metal-insulator-metal (MIM) color absorber that was mapped on soft, curved, and hydrated biological interfaces. Strong absorption was induced in the MIM structure and could be tuned by hydration and tilting of the sample. The transferred MIM color absorbers reached the exhibition of a very strong resonant absorption in the visible and near infra-red ranges. In addition, we demonstrated that the conformal resonator could function as a refractometric glucose sensor applied on a contact lens.

Experimental validation of an ultra-thin metasurface cloak for hiding a metallic obstacle from an antenna radiation at low frequencies

NASA Astrophysics Data System (ADS)

Teperik, Tatiana V.; Burokur, Shah Nawaz; de Lustrac, André; Sabanowski, Guy; Piau, Gérard-Pascal

2017-07-01

We demonstrate numerically and experimentally an ultra-thin (≈ λ/240) metasurface-based invisibility cloak for low frequency antenna applications. We consider a monopole antenna mounted on a ground plane and a cylindrical metallic obstacle of diameter smaller than the wavelength located in its near-field. To restore the intrinsic radiation patterns of the antenna perturbed by this obstacle, a metasurface cloak consisting simply of a metallic patch printed on a dielectric substrate is wrapped around the obstacle. Using a finite element method based commercial electromagnetic solver, we show that the radiation patterns of the monopole antenna can be restored completely owing to electromagnetic modes of the resonant cavity formed between the patch and obstacle. The metasurface cloak is fabricated, and the concept is experimentally demonstrated at 125 MHz. Performed measurements are in good agreement with numerical simulations, verifying the efficiency of the proposed cloak.

Microcavity-Free Broadband Light Outcoupling Enhancement in Flexible Organic Light-Emitting Diodes with Nanostructured Transparent Metal-Dielectric Composite Electrodes.

PubMed

Xu, Lu-Hai; Ou, Qing-Dong; Li, Yan-Qing; Zhang, Yi-Bo; Zhao, Xin-Dong; Xiang, Heng-Yang; Chen, Jing-De; Zhou, Lei; Lee, Shuit-Tong; Tang, Jian-Xin

2016-01-26

Flexible organic light-emitting diodes (OLEDs) hold great promise for future bendable display and curved lighting applications. One key challenge of high-performance flexible OLEDs is to develop new flexible transparent conductive electrodes with superior mechanical, electrical, and optical properties. Herein, an effective nanostructured metal/dielectric composite electrode on a plastic substrate is reported by combining a quasi-random outcoupling structure for broadband and angle-independent light outcoupling of white emission with an ultrathin metal alloy film for optimum optical transparency, electrical conduction, and mechanical flexibility. The microcavity effect and surface plasmonic loss can be remarkably reduced in white flexible OLEDs, resulting in a substantial increase in the external quantum efficiency and power efficiency to 47.2% and 112.4 lm W(-1).

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

PubMed

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Poly(vinyl acetate)/clay nanocomposite materials for organic thin film transistor application.

PubMed

Park, B J; Sung, J H; Park, J H; Choi, J S; Choi, H J

2008-05-01

Nanocomposite materials of poly(vinyl acetate) (PVAc) and organoclay were fabricated, in order to be utilized as dielectric materials of the organic thin film transistor (OTFT). Spin coating condition of the nanocomposite solution was examined considering shear viscosity of the composite materials dissolved in chloroform. Intercalated structure of the PVAc/clay nanocomposites was characterized using both wide-angle X-ray diffraction and TEM. Fracture morphology of the composite film on silicon wafer was also observed by SEM. Dielectric constant (4.15) of the nanocomposite materials shows that the PVAc/clay nanocomposites are applicable for the gate dielectric materials.

Eco-Friendly and Biodegradable Biopolymer Chitosan/Y₂O₃ Composite Materials in Flexible Organic Thin-Film Transistors.

PubMed

Du, Bo-Wei; Hu, Shao-Ying; Singh, Ranjodh; Tsai, Tsung-Tso; Lin, Ching-Chang; Ko, Fu-Hsiang

2017-09-03

The waste from semiconductor manufacturing processes causes serious pollution to the environment. In this work, a non-toxic material was developed under room temperature conditions for the fabrication of green electronics. Flexible organic thin-film transistors (OTFTs) on plastic substrates are increasingly in demand due to their high visible transmission and small size for use as displays and wearable devices. This work investigates and analyzes the structured formation of aqueous solutions of the non-toxic and biodegradable biopolymer, chitosan, blended with high-k-value, non-toxic, and biocompatible Y₂O₃ nanoparticles. Chitosan thin films blended with Y₂O₃ nanoparticles were adopted as the gate dielectric thin film in OTFTs, and an improvement in the dielectric properties and pinholes was observed. Meanwhile, the on/off current ratio was increased by 100 times, and a low leakage current was observed. In general, the blended chitosan/Y₂O₃ thin films used as the gate dielectric of OTFTs are non-toxic, environmentally friendly, and operate at low voltages. These OTFTs can be used on surfaces with different curvature radii because of their flexibility.

Influence of interface layer on optical properties of sub-20 nm-thick TiO2 films

NASA Astrophysics Data System (ADS)

Shi, Yue-Jie; Zhang, Rong-Jun; Li, Da-Hai; Zhan, Yi-Qiang; Lu, Hong-Liang; Jiang, An-Quan; Chen, Xin; Liu, Juan; Zheng, Yu-Xiang; Wang, Song-You; Chen, Liang-Yao

2018-02-01

The sub-20 nm ultrathin titanium dioxide (TiO2) films with tunable thickness were deposited on Si substrates by atomic layer deposition (ALD). The structural and optical properties were acquired by transmission electron microscopy, atomic force microscopy and spectroscopic ellipsometry. Afterwards, a constructive and effective method of analyzing interfaces by applying two different optical models consisting of air/TiO2/Ti x Si y O2/Si and air/effective TiO2 layer/Si, respectively, was proposed to investigate the influence of interface layer (IL) on the analysis of optical constants and the determination of band gap of TiO2 ultrathin films. It was found that two factors including optical constants and changing components of the nonstoichiometric IL could contribute to the extent of the influence. Furthermore, the investigated TiO2 ultrathin films of 600 ALD cycles were selected and then annealed at the temperature range of 400-900 °C by rapid thermal annealing. Thicker IL and phase transition cause the variation of optical properties of TiO2 films after annealing and a shorter electron relaxation time reveals the strengthened electron-electron and electron-phonon interactions in the TiO2 ultrathin films at high temperature. The as-obtained results in this paper will play a role in other studies of high dielectric constants materials grown on Si substrates and in the applications of next generation metal-oxide-semiconductor devices.

Transistor-based particle detection systems and methods

DOEpatents

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dumitru, L. M.; Manoli, K.; Magliulo, M.

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Brillouin light scattering studies on the mechanical properties of ultrathin, porous low-K dielectric films

NASA Astrophysics Data System (ADS)

Zhou, Wei; Sooryakumar, R.; King, Sean

2010-03-01

Low K dielectrics have predominantly replaced silicon dioxide as the interlayer dielectric material for interconnects in state of the art integrated circuits. To further reduce interconnect resistance-capacitance (RC) delays, additional reductions in the K for these low-K materials is being pursued by the introduction of controlled levels of porosity. The main challenge for porous low-K dielectrics is the substantial reduction in mechanical properties that is accompanied by the increased pore volume content needed to reduce K. We report on the application of the nondestructive Brillouin light scattering technique to monitor and characterize the mechanical properties of these porous films at thicknesses well below 200 nm that are pertinent to present applications. Observation of longitudinal and transverse standing wave acoustic resonances and the dispersion that accompany their transformation into traveling waves with finite in-plane wave vectors provides for the principal elastic constants that completely characterize the mechanical properties of these porous films. The mode amplitudes of the standing waves, their variation within the film, and the calculated Brillouin intensities account for most aspects of the spectra. The resulting elastic constants are compared with corresponding values obtained from other experimental techniques.

Solution-processable alumina: PVP nanocomposite dielectric layer for high-performance organic thin-film transistors

NASA Astrophysics Data System (ADS)

Lin, Hui; Kong, Xiao; Li, Yiran; Kuang, Peng; Tao, Silu

2018-03-01

In this article, we have investigated the effect of nanocomposite gate dielectric layer built by alumina (Al2O3) and poly(4-vinyphenol) (PVP) with solution method which could enhance the dielectric capability and decrease the surface polarity. Then, we used modify layer to optimize the surface morphology of dielectric layer to further improve the insulation capability, and finally we fabricated the high-performance and low-voltage organic thin-film transistors by using this nanocomposite dielectric layer. The result shows that the devices with Al2O3:10%PVP dielectric layer with a modified layer exhibited a mobility of 0.49 cm2/Vs, I on/Ioff ratio of 7.8 × 104, threshold voltage of - 1.2 V, sub-threshold swing of 0.3 V/dec, and operating voltage as low as - 4 V. The improvement of devices performance was owing to the good insulation capability, appropriate capacitance of dielectric layer, and preferable interface contact, smaller crystalline size of active layer.

Low-voltage electric-double-layer paper transistors gated by microporous SiO2 processed at room temperature

NASA Astrophysics Data System (ADS)

Sun, Jia; Wan, Qing; Lu, Aixia; Jiang, Jie

2009-11-01

Battery drivable low-voltage SnO2-based paper thin-film transistors with a near-zero threshold voltage (Vth=0.06 V) gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated at room temperature. The operating voltage is found to be as low as 1.5 V due to the huge gate specific capacitance (1.34 μF/cm2 at 40 Hz) related to EDL formation. The subthreshold gate voltage swing and current on/off ratio is found to be 82 mV/decade and 2.0×105, respectively. The electron field-effect mobility is estimated to be 47.3 cm2/V s based on the measured gate specific capacitance at 40 Hz.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Chemical vapor deposition of anisotropic ultrathin gold films on optical fibers: real-time sensing by tilted fiber Bragg gratings and use of a dielectric pre-coating

NASA Astrophysics Data System (ADS)

Mandia, David J.; Zhou, Wenjun; Ward, Matthew J.; Joress, Howie; Giorgi, Javier B.; Gordon, Peter; Albert, Jacques; Barry, Seán. T.

2014-09-01

Tilted fiber Bragg gratings (TFBGs) are refractometry-based sensor platforms that have been employed herein as devices for the real-time monitoring of chemical vapour deposition (CVD) in the near-infrared range (NIR). The coreguided light launched within the TFBG core is back-reflected off a gold mirror sputtered onto the fiber-end and is scattered out into the cladding where it can interact with a nucleating thin film. Evanescent fields of the growing gold nanostructures behave differently depending on the polarization state of the core-guided light interrogating the growing film, therefore the resulting spectral profile is typically decomposed into two separate peak families for the orthogonal S- and P-polarizations. Wavelength shifts and attenuation profiles generated from gold films in the thickness regime of 5-100 nm are typically degenerate for deposition directly onto the TFBG. However, a polarization-dependence can be imposed by adding a thin dielectric pre-coating onto the TFBG prior to using the device for CVD monitoring of the ultrathin gold films. It is found that addition of the pre-coating enhances the sensitivity of the P-polarized peak family to the deposition of ultrathin gold films and renders the films optically anisotropic. It is shown herein that addition of the metal oxide coating can increase the peak-to-peak wavelength separation between orthogonal polarization modes as well as allow for easy resonance tracking during deposition. This is also the first reporting of anisotropic gold films generated from this particular gold precursor and CVD process. Using an ensemble of x-ray techniques, the local fine structure of the gold films deposited directly on the TFBG is compared to gold films of similar thicknesses deposited on the Al2O3 pre-coated TFBG and witness slides.

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Effect of Al-diffusion-induced positive flatband voltage shift on the electrical characteristics of Al-incorporated high-k metal-oxide-semiconductor field-effective transistor

NASA Astrophysics Data System (ADS)

Wang, Wenwu; Akiyama, Koji; Mizubayashi, Wataru; Nabatame, Toshihide; Ota, Hiroyuki; Toriumi, Akira

2009-03-01

We systematically studied what effect Al diffusion from high-k dielectrics had on the flatband voltage (Vfb) of Al-incorporated high-k gate stacks. An anomalous positive shift fin Vfb with the decreasing equivalent oxide thickness (EOT) of high-k gate stacks is reported. As the SiO2 interfacial layer is aggressively thinned in Al-incorporated HfxAl1-xOy gate stacks with a metal-gate electrode, the Vfb first lies on the well known linear Vfb-EOT plot and deviates toward the positive-voltage direction (Vfb roll-up), followed by shifting toward negative voltage (Vfb roll-off). We demonstrated that the Vfb roll-up behavior remarkably decreases the threshold voltage (Vth) of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs), and does not cause severe degradation in the characteristics of hole mobility. The Vfb roll-up behavior, which is independent of gate materials but strongly dependent on high-k dielectrics, was ascribed to variations in fixed charges near the SiO2/Si interface, which are caused by Al diffusion from HfxAl1-xOy through SiO2 to the SiO2/Si interface. These results indicate that anomalous positive shift in Vfb, i.e., Vfb roll-up, should be taken into consideration in quantitatively adjusting Vfb in thin EOT regions and that it could be used to further tune Vth in p-MOSFETs.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

High-mobility low-temperature ZnO transistors with low-voltage operation

NASA Astrophysics Data System (ADS)

Bong, Hyojin; Lee, Wi Hyoung; Lee, Dong Yun; Kim, Beom Joon; Cho, Jeong Ho; Cho, Kilwon

2010-05-01

Low voltage high mobility n-type thin film transistors (TFTs) based on sol-gel processed zinc oxide (ZnO) were fabricated using a high capacitance ion gel gate dielectric. The ion gel gated solution-processed ZnO TFTs were found to exhibit excellent electrical properties. TFT carrier mobilities were 13 cm2/V s, ON/OFF current ratios were 105, regardless of the sintering temperature used for the preparation of the ZnO thin films. Ion gel gated ZnO TFTs are successfully demonstrated on plastic substrates for the large area flexible electronics.

High electron mobility and quantum oscillations in non-encapsulated ultrathin semiconducting Bi2O2Se

NASA Astrophysics Data System (ADS)

Wu, Jinxiong; Yuan, Hongtao; Meng, Mengmeng; Chen, Cheng; Sun, Yan; Chen, Zhuoyu; Dang, Wenhui; Tan, Congwei; Liu, Yujing; Yin, Jianbo; Zhou, Yubing; Huang, Shaoyun; Xu, H. Q.; Cui, Yi; Hwang, Harold Y.; Liu, Zhongfan; Chen, Yulin; Yan, Binghai; Peng, Hailin

2017-07-01

High-mobility semiconducting ultrathin films form the basis of modern electronics, and may lead to the scalable fabrication of highly performing devices. Because the ultrathin limit cannot be reached for traditional semiconductors, identifying new two-dimensional materials with both high carrier mobility and a large electronic bandgap is a pivotal goal of fundamental research. However, air-stable ultrathin semiconducting materials with superior performances remain elusive at present. Here, we report ultrathin films of non-encapsulated layered Bi2O2Se, grown by chemical vapour deposition, which demonstrate excellent air stability and high-mobility semiconducting behaviour. We observe bandgap values of ˜0.8 eV, which are strongly dependent on the film thickness due to quantum-confinement effects. An ultrahigh Hall mobility value of >20,000 cm2 V-1 s-1 is measured in as-grown Bi2O2Se nanoflakes at low temperatures. This value is comparable to what is observed in graphene grown by chemical vapour deposition and at the LaAlO3-SrTiO3 interface, making the detection of Shubnikov-de Haas quantum oscillations possible. Top-gated field-effect transistors based on Bi2O2Se crystals down to the bilayer limit exhibit high Hall mobility values (up to 450 cm2 V-1 s-1), large current on/off ratios (>106) and near-ideal subthreshold swing values (˜65 mV dec-1) at room temperature. Our results make Bi2O2Se a promising candidate for future high-speed and low-power electronic applications.

X-ray measurements of the strain and shape of dielectric/metallic wrap-gated InAs nanowires

NASA Astrophysics Data System (ADS)

Eymery, J.; Favre-Nicolin, V.; Fröberg, L.; Samuelson, L.

2009-03-01

Wrap-gate (111) InAs nanowires (NWs) were studied after HfO2 dielectric coating and Cr metallic deposition by a combination of grazing incidence x-ray techniques. In-plane and out-of-plane x-ray diffraction (crystal truncation rod analysis) allow determining the strain tensor. The longitudinal contraction, increasing with HfO2 and Cr deposition, is significantly larger than the radial dilatation. For the Cr coating, the contraction along the growth axis is quite large (-0.95%), and the longitudinal/radial deformation ratio is >10, which may play a role on the NW transport properties. Small angle x-ray scattering shows a smoothening of the initial hexagonal bare InAs NW shape and gives the respective core/shell thicknesses, which are compared to flat surface values.

Enhancement of field effect mobility of poly(3-hexylthiophene) thin film transistors by soft-lithographical nanopatterning on the gate-dielectric surface

NASA Astrophysics Data System (ADS)

Park, Jeong-Ho; Kang, Seok-Ju; Park, Jeong-Woo; Lim, Bogyu; Kim, Dong-Yu

2007-11-01

The submicroscaled octadecyltrichlorosilane (OTS) line patterns on gate-dielectric surfaces were introduced into the fabrication of organic field effect transistors (OFETs). These spin-cast regioregular poly(3-hexylthiophene) films on soft-lithographically patterned SiO2 surfaces yielded a higher hole mobility (˜0.072cm2/Vs ) than those of unpatterned (˜0.015cm2/Vs) and untreated (˜5×10-3cm2/Vs) OFETs. The effect of mobility enhancement as a function of the patterned line pitch was investigated in structural and geometric characteristics. The resulting improved mobility is likely attributed to the formation of efficient π-π stacking as a result of guide-assisted, local self-organization-involved molecular interactions between the poly(3-hexylthiophene) polymer and the geometrical OTS patterns.

Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

PubMed Central

Henkel, C.; Abermann, S.; Bethge, O.; Pozzovivo, G.; Klang, P.; Stöger-Pollach, M.; Bertagnolli, E.

2011-01-01

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 1011 eV−1 cm−2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF current ratio greater than 2 × 106 are obtained. PMID:21461054

Electrical properties of solution processed highly transparent ZnO TFT with organic gate dielectric

NASA Astrophysics Data System (ADS)

Pandya, Nirav C.; Joshi, Nikhil G.; Trivedi, U. N.; Joshi, U. S.

2013-02-01

All oxide thin film transistors (TFT) with zinc oxide active layer were fabricated by chemical solution deposition (CSD) using aqueous solutions on glass substrate. Thin film transistors (TFTs) with amorphous zinc oxide as channel layers and poly-vinyl alcohol as dielectric layers were fabricated at low temperatures by chemical solution deposition (CSD). Atomic force microscopy (AFM) confirmed nano grain size with fairly smooth surface topography. Very small leakage currents were achieved in the transfer curves, while soft saturation was observed in the output current voltage (I-V) characteristics of the device. Optical transmission of better than 87% in the visible region was estimated, which is better than the organic gate insulator based ZnO TFTs reported so far. Our results offer lot of promise to TFT based display and optoelectronics.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

PubMed

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

Heterointegration of Dissimilar Materials

DTIC Science & Technology

2015-07-28

computing capabilities. This has been possible due to the aggressive scaling undertaken by the Si industry for complementary metal oxide semiconductor...current due to quantum mechanical tunneling. After years of research and development, Hf- based gate dielectric with metal gates is now being used in CMOS...the oxide in this study was 1ML or ~3.9 Å/ min. The native SiO2 was removed using a low temperature process involving the deposition of Sr metal

Electrically tunable metasurface perfect absorbers for ultrathin mid-infrared optical modulators.

PubMed

Yao, Yu; Shankar, Raji; Kats, Mikhail A; Song, Yi; Kong, Jing; Loncar, Marko; Capasso, Federico

2014-11-12

Dynamically reconfigurable metasurfaces open up unprecedented opportunities in applications such as high capacity communications, dynamic beam shaping, hyperspectral imaging, and adaptive optics. The realization of high performance metasurface-based devices remains a great challenge due to very limited tuning ranges and modulation depths. Here we show that a widely tunable metasurface composed of optical antennas on graphene can be incorporated into a subwavelength-thick optical cavity to create an electrically tunable perfect absorber. By switching the absorber in and out of the critical coupling condition via the gate voltage applied on graphene, a modulation depth of up to 100% can be achieved. In particular, we demonstrated ultrathin (thickness < λ0/10) high speed (up to 20 GHz) optical modulators over a broad wavelength range (5-7 μm). The operating wavelength can be scaled from the near-infrared to the terahertz by simply tailoring the metasurface and cavity dimensions.

Kink effect in ultrathin FDSOI MOSFETs

NASA Astrophysics Data System (ADS)

Park, H. J.; Bawedin, M.; Choi, H. G.; Cristoloveanu, S.

2018-05-01

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. He is currently working toward the Ph.D. degree in FDSOI device characterization and simulation at a laboratory of IMEP-lahc, Université Grenoble Alpes, Minatec, Grenoble, France. His research interests include residual floating body effects, electrical characterization, and device simulation for ultra FDSOI MOSFETs.

Investigation of sensing mechanism and signal amplification in carbon nanotube based microfluidic liquid-gated transistors via pulsating gate bias.

PubMed

Wijaya, I Putu Mahendra; Nie, Tey Ju; Rodriguez, Isabel; Mhaisalkar, Subodh G

2010-06-07

The advent of a carbon nanotube liquid-gated transistor (LGFET) for biosensing applications allows the possibility of real-time and label-free detection of biomolecular interactions. The use of an aqueous solution as dielectric, however, has traditionally restricted the operating gate bias (VG) within |VG| < 1 V, due to the electrolysis of water. Here, we propose pulsed-gating as a facile method to extend the operation window of LGFETs to |VG| > 1 V. A comparison between simulation and experimental results reveals that at voltages in excess of 1 V, the LGFET sensing mechanism has a contribution from two factors: electrostatic gating as well as capacitance modulation. Furthermore, the large IDS drop observed in the |VG| > 1 V region indicates that pulsed-gating may be readily employed as a simple method to amplify the signal in the LGFET and pushes the detection limit down to attomolar concentration levels, an order of magnitude improvement over conventionally employed DC VG biasing.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

DTIC Science & Technology

1993-04-01

CLASSIFICATION 18. SECURITY CLASSIFICATION 19. SECURIlY CLASSIFICATION 20. UMITATION OF ABSTRACT OF REPORT OF THIS PAGE OF ABSTRACT UNCLASSIFIED UNCLASSIFIED...with the silicon underneath, growing a thin nitride layer. This layer of Si 3 N 4 , if not completely removed, will retard oxidation in the area...C. Shatas, K. C. Saraswat and J. D. Meindl, "Interfacial and Breakdown Characteristics of MOS Devices with Rapidly Grown Ultrathin SiO Gate

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

NASA Astrophysics Data System (ADS)

Kwon, Jin-Hyuk; Bae, Jin-Hyuk; Lee, Hyeonju; Park, Jaehoon

2018-03-01

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

Efficient flat metasurface lens for terahertz imaging.

PubMed

Yang, Quanlong; Gu, Jianqiang; Wang, Dongyang; Zhang, Xueqian; Tian, Zhen; Ouyang, Chunmei; Singh, Ranjan; Han, Jiaguang; Zhang, Weili

2014-10-20

Metamaterials offer exciting opportunities that enable precise control of amplitude, polarization and phase of the light beam at a subwavelength scale. A gradient metasurface consists of a class of anisotropic subwavelength metamaterial resonators that offer abrupt amplitude and phase changes, thus enabling new applications in optical device design such as ultrathin flat lenses. We propose a highly efficient gradient metasurface lens based on a metal-dielectric-metal structure that operates in the terahertz regime. The proposed structure consists of slotted metallic resonator arrays on two sides of a thin dielectric spacer. By varying the geometrical parameters, the metasurface lens efficiently manipulates the spatial distribution of the terahertz field and focuses the beam to a spot size on the order of a wavelength. The proposed flat metasurface lens design is polarization insensitive and works efficiently even at wide angles of incidence.

Dielectric Meta-Holograms Enabled with Dual Magnetic Resonances in Visible Light.

PubMed

Li, Zile; Kim, Inki; Zhang, Lei; Mehmood, Muhammad Q; Anwar, Muhammad S; Saleem, Murtaza; Lee, Dasol; Nam, Ki Tae; Zhang, Shuang; Luk'yanchuk, Boris; Wang, Yu; Zheng, Guoxing; Rho, Junsuk; Qiu, Cheng-Wei

2017-09-26

Efficient transmission-type meta-holograms have been demonstrated using high-index dielectric nanostructures based on Huygens' principle. It is crucial that the geometry size of building blocks be judiciously optimized individually for spectral overlap of electric and magnetic dipoles. In contrast, reflection-type meta-holograms using the metal/insulator/metal scheme and geometric phase can be readily achieved with high efficiency and small thickness. Here, we demonstrate a general platform for design of dual magnetic resonance based meta-holograms based on the geometric phase using silicon nanostructures that are quarter wavelength thick for visible light. Significantly, the projected holographic image can be unambiguously observed without a receiving screen even under the illumination of natural light. Within the well-developed semiconductor industry, our ultrathin magnetic resonance-based meta-holograms may have promising applications in anticounterfeiting and information security.

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts.

PubMed

Avsar, Ahmet; Marinov, Kolyo; Marin, Enrique Gonzalez; Iannaccone, Giuseppe; Watanabe, Kenji; Taniguchi, Takashi; Fiori, Gianluca; Kis, Andras

2018-05-01

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe 2 transistor by only utilizing van der Waals bonded graphene and Co/h-BN contacts. Toward this, first the charge injection efficiencies into WSe 2 by graphene and Co/h-BN contacts are characterized. While Co/h-BN contact results in nearly Schottky-barrier-free charge injection, graphene/WSe 2 interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work-function values of graphene and Co/h-BN, vertical devices are constructed where different gate-tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Direct growth of graphene-dielectric bi-layer structure on device substrates from Si-based polymer

NASA Astrophysics Data System (ADS)

Seo, Hong-Kyu; Kim, Kyunghun; Min, Sung-Yong; Lee, Yeongjun; Eon Park, Chan; Raj, Rishi; Lee, Tae-Woo

2017-06-01

To facilitate the utilization of graphene films in conventional semiconducting devices (e.g. transistors and memories) which includes an insulating layer such as gate dielectric, facile synthesis of bi-layers composed of a graphene film and an insulating layer by one-step thermal conversion will be very important. We demonstrate a simple, inexpensive, scalable and patternable process to synthesize graphene-dielectric bi-layer films from solution-processed polydimethylsiloxane (PDMS) under a Ni capping layer. This method fabricates graphene-dielectric bi-layer structure simultaneously directly on substrate by thermal conversion of PDMS without using additional graphene transfer and patterning process or formation of an expensive dielectric layer, which makes the device fabrication process much easier. The graphene-dielectric bi-layer on a conducting substrate was used in bottom-contact pentacene field-effect transistors that showed ohmic contact and small hysteresis. Our new method will provide a way to fabricate flexible electronic devices simply and inexpensively.

Influence of LaSiOx passivation interlayer on band alignment between PEALD-Al2O3 and 4H-SiC determined by X-ray photoelectron spectroscopy

NASA Astrophysics Data System (ADS)

Wang, Qian; Cheng, Xinhong; Zheng, Li; Shen, Lingyan; Zhang, Dongliang; Gu, Ziyue; Qian, Ru; Cao, Duo; Yu, Yuehui

2018-01-01

The influence of lanthanum silicate (LaSiOx) passivation interlayer on the band alignment between plasma enhanced atomic layer deposition (PEALD)-Al2O3 films and 4H-SiC was investigated by high resolution X-ray photoelectron spectroscopy (XPS). An ultrathin in situ LaSiOx interfacial passivation layer (IPL) was introduced between the Al2O3 gate dielectric and the 4H-SiC substrate to enhance the interfacial characteristics. The valence band offset (VBO) and corresponding conduction band offset (CBO) for the Al2O3/4H-SiC interface without any passivation were extracted to be 2.16 eV and 1.49 eV, respectively. With a LaSiOx IPL, a VBO of 1.79 eV and a CBO of 1.86 eV could be obtained across the Al2O3/4H-SiC interface. The difference in the band alignments was dominated by the band bending or band shift in the 4H-SiC substrate as a result of different interfacial layers (ILs) formed at the interface. This understanding of the physical details of the band alignment could be a good foundation for Al2O3/LaSiOx/4H-SiC heterojunctions applied in the 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs).

Designing graphene absorption in a multispectral plasmon-enhanced infrared detector

DOE PAGES

Goldflam, Michael D.; Fei, Zhe; Ruiz, Isaac; ...

2017-05-18

Here, we have examined graphene absorption in a range of graphene-based infrared devices that combine either monolayer or bilayer graphene with three different gate dielectrics. Electromagnetic simulations show that the optical absorption in graphene in these devices, an important factor in a functional graphene-based detector, is strongly dielectric-dependent. Our simulations reveal that plasmonic excitation in graphene can significantly influence the percentage of light absorbed in the entire device, as well as the graphene layer itself, with graphene absorption exceeding 25% in regions where plasmonic excitation occurs. Notably, the dielectric environment of graphene has a dramatic influence on the strength andmore » wavelength range over which the plasmons can be excited, making dielectric choice paramount to final detector tunability and sensitivity.« less

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

High-mobility and low-operating voltage organic thin film transistor with epoxy based siloxane binder as the gate dielectric

NASA Astrophysics Data System (ADS)

Tewari, Amit; Gandla, Srinivas; Pininti, Anil Reddy; Karuppasamy, K.; Böhm, Siva; Bhattacharyya, Arup R.; McNeill, Christopher R.; Gupta, Dipti

2015-09-01

This paper reports the fabrication of pentacene-based organic thin-film transistors using a dielectric material, Dynasylan ®SIVO110. The devices exhibit excellent performance characterized by a low threshold voltage of -1.4 V (operating voltage: 0 to -4 V) together with a mobility of 1.9 cm2 V-1s-1. These results are promising because it uses only a single layer of dielectric without performing any intermediate treatment. The reason is attributed to the high charge storage capacity of the dielectric (κ ˜ 20.02), a low interfacial trap density (2.56 × 1011cm-2), and favorable pentacene film morphology consisting of large and interconnected grains having an average size of 234 nm.

Designing graphene absorption in a multispectral plasmon-enhanced infrared detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goldflam, Michael D.; Fei, Zhe; Ruiz, Isaac

Here, we have examined graphene absorption in a range of graphene-based infrared devices that combine either monolayer or bilayer graphene with three different gate dielectrics. Electromagnetic simulations show that the optical absorption in graphene in these devices, an important factor in a functional graphene-based detector, is strongly dielectric-dependent. Our simulations reveal that plasmonic excitation in graphene can significantly influence the percentage of light absorbed in the entire device, as well as the graphene layer itself, with graphene absorption exceeding 25% in regions where plasmonic excitation occurs. Notably, the dielectric environment of graphene has a dramatic influence on the strength andmore » wavelength range over which the plasmons can be excited, making dielectric choice paramount to final detector tunability and sensitivity.« less

Anisotropic effective permittivity of an ultrathin gold coating on optical fiber in air, water and saline solutions.

PubMed

Zhou, Wenjun; Mandia, David J; Barry, Seán T; Albert, Jacques

2014-12-29

The optical properties of an ultrathin discontinuous gold film in different dielectric surroundings are investigated experimentally by measuring the polarization-dependent wavelength shifts and amplitudes of the cladding mode resonances of a tilted fiber Bragg grating. The gold film was prepared by electron-beam evaporation and had an average thickness of 5.5 nm ( ± 1 nm). Scanning electron imaging was used to determine that the film is actually formed of individual particles with average lateral dimensions of 28 nm ( ± 8 nm). The complex refractive indices of the equivalent uniform film in air at a wavelength of 1570 nm were calculated from the measurements to be 4.84-i0.74 and 3.97-i0.85 for TM and TE polarizations respectively (compared to the value for bulk gold: 0.54-i10.9). Additionally, changes in the birefringence and dichroism of the films were measured as a function of the surrounding medium, in air, water and a saturated NaCl (salt) solution. These results show that the film has stronger dielectric behavior for TM light than for TE, a trend that increases with increasing surrounding index. Finally, the experimental results are compared to predictions from two widely used effective medium approximations, the generalized Maxwell-Garnett and Bruggeman theories for gold particles in a surrounding matrix. It is found that both of these methods fail to predict the observed behavior for the film considered.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

NASA Astrophysics Data System (ADS)

Yan, Shi-Li; Xie, Zhi-Jian; Chen, Jian-Hao; Taniguchi, Takashi; Watanabe, Kenji

2017-03-01

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10V/nm to 0.83V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

Improvement of Ion/Ioff for h-BN encapsulated bilayer graphene by graphite local back gate electrode

NASA Astrophysics Data System (ADS)

Uwanno, Teerayut; Taniguchi, Takashi; Watanabe, Kenji; Nagashio, Kosuke

The critical issue for bilayer graphene (BLG) devices is low Ion/Ioff even at the band gap of 0.3eV. Band gap in BLG can be formed by creating potential difference between the two layers of BLG. This can be done by applying external electric field perpendicularly to BLG to induce different carrier densities in the two layers. Due to such origin, the spatial uniformity of band gap in the channel is quite sensitive to charge inhomogeneity in BLG. In order to apply electric field of 3V/nm to open the maximum band gap of 0.3eV, high- k gate stack has been utilized so far. However, oxide dielectrics usually have large charge inhomogeneity causing in-plane potential fluctuation in BLG channel. Due to surface flatness and small charge inhomogeneity, h-BN has been used as dielectrics to achieve high quality graphene devices, however, Ion/Iofffor BLG/ h-BN heterostuctures has not been reported yet. In this study, we used graphite as local back gate electrode to BLG encapsulated with h-BN. This resulted in much higher Ion/Ioff, indicating the importance of screening of charge inhomogeneity from SiO2 substrate surface by local graphite back gate electrode. This research was partly supported by JSPS Core-to-Core Program, A. Advanced Research Networks.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

High-Performance Ultrathin Active Chiral Metamaterials.

PubMed

Wu, Zilong; Chen, Xiaodong; Wang, Mingsong; Dong, Jianwen; Zheng, Yuebing

2018-05-22

Ultrathin active chiral metamaterials with dynamically tunable and responsive optical chirality enable new optical sensors, modulators, and switches. Herein, we develop ultrathin active chiral metamaterials of highly tunable chiroptical responses by inducing tunable near-field coupling in the metamaterials and exploit the metamaterials as ultrasensitive sensors to detect trace amounts of solvent impurities. To demonstrate the active chiral metamaterials mediated by tunable near-field coupling, we design moiré chiral metamaterials (MCMs) as model metamaterials, which consist of two layers of identical Au nanohole arrays stacked upon one another in moiré patterns with a dielectric spacer layer between the Au layers. Our simulations, analytical fittings, and experiments reveal that spacer-dependent near-field coupling exists in the MCMs, which significantly enhances the spectral shift and line shape change of the circular dichroism (CD) spectra of the MCMs. Furthermore, we use a silk fibroin thin film as the spacer layer in the MCM. With the solvent-controllable swelling of the silk fibroin thin films, we demonstrate actively tunable near-field coupling and chiroptical responses of the silk-MCMs. Impressively, we have achieved the spectral shift over a wavelength range that is more than one full width at half-maximum and the sign inversion of the CD spectra in a single ultrathin (1/5 of wavelength in thickness) MCM. Finally, we apply the silk-MCMs as ultrasensitive sensors to detect trace amounts of solvent impurities down to 200 ppm, corresponding to an ultrahigh sensitivity of >10 5 nm/refractive index unit (RIU) and a figure of merit of 10 5 /RIU.

Highly efficient birefringent quarter-wave plate based on all-dielectric metasurface and graphene

NASA Astrophysics Data System (ADS)

Owiti, Edgar O.; Yang, Hanning; Liu, Peng; Ominde, Calvine F.; Sun, Xiudong

2018-07-01

All-dielectric metasurfaces offer remarkable properties including high efficiency and flexible control of the optical response. However, extreme, narrow bandwidth is a limitation that lowers applicability of these structures in photonic sensing applications. In this work, we numerically design and propose a switchable quarter-wave plate by hybridizing an all-dielectric metasurface with graphene. By using a single layer of graphene between a highly refractive index silicon and a silica substrate, the transmissive resonance is enhanced and broadened. Additionally, integrating graphene with silicon effectively modulates the Q-factor and the trapped magnetic modes in the silicon. A stable birefringence output is obtained and manipulated through the structure dimensions and the Fermi energy of graphene. A 95% polarization conversion ratio is achieved through converting linearly polarized light into circularly polarized light, and a 96% ellipticity ratio is obtained at the resonance wavelength. The structure is compact and has an ultrathin design thickness of 0 . 1 λ, in the telecommunication region. The above properties are essential for integration into photonic sensing devices and the structure has potential for compatibility with the CMOS devices.

Structured organic materials and devices using low-energy particle beams

DOEpatents

Vardeny, Z. Valy; Li, Sergey; Delong, Matthew C.; Jiang, Xiaomei

2005-09-13

Organic materials exposed to an electron beam for patterning a substrate (1) to make an optoelectronic organic device which includes a source, a drain, gate dielectric layer (4), and a substrate for emitting light.

DNA and RNA sequencing by nanoscale reading through programmable electrophoresis and nanoelectrode-gated tunneling and dielectric detection

DOEpatents

Lee, James W.; Thundat, Thomas G.

2005-06-14

An apparatus and method for performing nucleic acid (DNA and/or RNA) sequencing on a single molecule. The genetic sequence information is obtained by probing through a DNA or RNA molecule base by base at nanometer scale as though looking through a strip of movie film. This DNA sequencing nanotechnology has the theoretical capability of performing DNA sequencing at a maximal rate of about 1,000,000 bases per second. This enhanced performance is made possible by a series of innovations including: novel applications of a fine-tuned nanometer gap for passage of a single DNA or RNA molecule; thin layer microfluidics for sample loading and delivery; and programmable electric fields for precise control of DNA or RNA movement. Detection methods include nanoelectrode-gated tunneling current measurements, dielectric molecular characterization, and atomic force microscopy/electrostatic force microscopy (AFM/EFM) probing for nanoscale reading of the nucleic acid sequences.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

PubMed

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

An Al2O3 Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials

PubMed Central

Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Zhang, Xueao

2017-01-01

We fabricated 70 nm Al2O3 gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al2O3/Si substrate is superior to that on a traditional 300 nm SiO2/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al2O3/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS2, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices. PMID:28937619

Electrochemical formation of field emitters

DOEpatents

Bernhardt, Anthony F.

1999-01-01

Electrochemical formation of field emitters, particularly useful in the fabrication of flat panel displays. The fabrication involves field emitting points in a gated field emitter structure. Metal field emitters are formed by electroplating and the shape of the formed emitter is controlled by the potential imposed on the gate as well as on a separate counter electrode. This allows sharp emitters to be formed in a more inexpensive and manufacturable process than vacuum deposition processes used at present. The fabrication process involves etching of the gate metal and the dielectric layer down to the resistor layer, and then electroplating the etched area and forming an electroplated emitter point in the etched area.

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

NASA Astrophysics Data System (ADS)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Pushing the Material Limits in High Kappa Dielectrics on High Carrier Mobility Semiconductors for Science/Technology Beyond Si CMOS and More

DTIC Science & Technology

2014-01-28

In0.53Ga0.47As, with an Al2O3 cap, were employed as a gate dielectric. 15. SUBJECT TERMS CMOS, Magneto-optical imaging , Nanotechnology, Indium Gallium ...2012. 2. “ Thermodynamic stability of MBE-HfO2 on In0.53Ga0.47As”, T. D. Lin, P. Chang, W. C. Lee, M. L. Huang, C. A. Lin, J. Kwo, and M. Hong

Improved organic thin-film transistor performance using novel self-assembled monolayers

NASA Astrophysics Data System (ADS)

McDowell, M.; Hill, I. G.; McDermott, J. E.; Bernasek, S. L.; Schwartz, J.

2006-02-01

Pentacene-based organic thin-film transistors have been fabricated using a phosphonate-linked anthracene self-assembled monolayer as a buffer between the silicon dioxide gate dielectric and the active pentacene channel region. Vast improvements in the subthreshold slope and threshold voltage are observed compared to control devices fabricated without the buffer. Both observations are consistent with a greatly reduced density of charge trapping states at the semiconductor-dielectric interface effected by introduction of the self-assembled monolayer.

High Performance Crystalline Organic Transistors and Circuit

DTIC Science & Technology

2011-08-02

pentacene -based OFETs, low voltage operation is possible. 3 Figure 1: Device structure for a low voltage pentacene OFET using a ZrO2 gate...first SiO Z OPentacene Au Pentacene ZrO2 AuPd SiO2 4 film. Bilayer dielectrics exhibit lower defect-related leakage effects, as pinholes or...other defects in one layer may be isolated by the other layer. 350 Å of pentacene was thermally evaporated on the ZrO2 dielectric at a rate of 0.1 Å

Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

NASA Astrophysics Data System (ADS)

Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

2017-01-01

We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

Comparative Study on Graded-Barrier AlxGa1‑xN/AlN/GaN/Si Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistor by Using Ultrasonic Spray Pyrolysis Deposition Technique

NASA Astrophysics Data System (ADS)

Lee, Ching-Sung; Hsu, Wei-Chou; Huang, Yi-Ping; Liu, Han-Yin; Yang, Wen-Luh; Yang, Shen-Tin

2018-06-01

Comparative study on a novel Al2O3-dielectric graded-barrier (GB) AlxGa1‑xN/AlN/GaN/Si (x = 0.22 ∼ 0.3) metal-oxide-semiconductor heterostructure field-effect transistor (MOS-HFET) formed by using the ultrasonic spray pyrolysis deposition (USPD) technique has been made with respect to a conventional-barrier (CB) Al0.26Ga0.74N/AlN/GaN/Si MOS-HFET and the reference Schottky-gate HFET devices. The GB AlxGa1‑xN was devised to improve the interfacial quality and enhance the Schottky barrier height at the same time. A cost-effective ultrasonic spray pyrolysis deposition (USPD) method was used to form the high-k Al2O3 gate dielectric and surface passivation on the AlGaN barrier of the present MOS-HFETs. Comprehensive device performances, including maximum extrinsic transconductance (g m,max), maximum drain-source current density (I DS,max), gate-voltage swing (GVS) linearity, breakdown voltages, subthreshold swing (SS), on/off current ratio (I on /I off ), high frequencies, and power performance are investigated.

Studying tantalum-based high-κ dielectrics in terms of capacitance measurements

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, L.

2016-08-01

The trend of rapid development of microelectronics towards nano-miniaturization dictates the inevitable introduction of dielectrics with high permittivity (high-κ dielectrics), as alternative material for replacing SiO2. Therefore, studying these materials in terms of their characteristics, especially in terms of reliability, is of great importance for proper design and manufacture of devices. In this paper, alteration of capacitance in different frequency regimes is used, in order to determine the overall behavior of the material. Samples investigated here are MOS structures containing nanoscale tantalum based dielectrics. Layers of pure Ta2O5, but also Hf and Ti doped tantalum pentoxide, i.e. Ta2O5:Hf and Ta2O5:Ti are studied here. All samples are considered as ultrathin oxide layers with thicknesses less than 15 nm, obtained by radio frequent sputtering on p-type silicon substrate. Measuring capacitive characteristics enables determination of several specific parameters of the structures. The obtained results for capacitance in accumulation, the thickness and time evolution of the interfacial SiO2 layer, values of flatband and threshold voltage, density of oxide charges, interfacial and border states, and reliability properties favor the possibilities for more intensive use of studied materials in new nanoelectronic technologies.

Bio-Organic Optoelectronic Devices Using DNA

NASA Astrophysics Data System (ADS)

Singh, Thokchom Birendra; Sariciftci, Niyazi Serdar; Grote, James G.

Biomolecular DNA, as a marine waste product from salmon processing, has been exploited as biodegradable polymeric material for photonics and electronics. For preparing high optical quality thin films of DNA, a method using DNA with cationic surfactants such as DNA-cetyltrimethylammonium, CTMA has been applied. This process enhances solubility and processing for thin film fabrication. These DNA-CTMA complexes resulted in the formation of self-assembled supramolecular films. Additionally, the molecular weight can be tailored to suit the application through sonication. It revealed that DNA-CTMA complexes were thermostable up to 230 ∘ C. UV-VIS absorption shows that these thin films have high transparency from 350 to about 1,700 nm. Due to its nature of large band gap and large dielectric constant, thin films of DNA-CTMA has been successfully used in multiple applications such as organic light emitting diodes (OLED), a cladding and host material in nonlinear optical devices, and organic field-effect transistors (OFET). Using this DNA based biopolymers as a gate dielectric layer, OFET devices were fabricated that exhibits current-voltage characteristics with low voltages as compared with using other polymer-based dielectrics. Using a thin film of DNA-CTMA based biopolymer as the gate insulator and pentacene as the organic semiconductor, we have demonstrated a bio-organic FET or BioFET in which the current was modulated over three orders of magnitude using gate voltages less than 10 V. Given the possibility to functionalise the DNA film customised for specific purposes viz. biosensing, DNA-CTMA with its unique structural, optical and electronic properties results in many applications that are extremely interesting.

Effect of Oxide Interface Roughness on the Threshold Voltage Fluctuations in Decanano MOSFETs with Ultrathin Gate Oxides

NASA Technical Reports Server (NTRS)

Asenov, Asen; Kaya, S.

2000-01-01

In this paper we use the Density Gradient (DG) simulation approach to study, in 3-D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2-D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the Quantum Mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Modification of FN tunneling provoking gate-leakage current in ZTO (zinc-tin oxide) TFT by regulating the ZTO/SiO2 area ratio

NASA Astrophysics Data System (ADS)

Li, Jeng-Ting; Tsai, Ho-Lin; Lai, Wei-Yao; Hwang, Weng-Sing; Chen, In-Gann; Chen, Jen-Sue

2018-04-01

This study addresses the variation in gate-leakage current due to the Fowler-Nordheim (FN) tunneling of electrons through a SiO2 dielectric layer in zinc-tin oxide (ZTO) thin film transistors. It is shown that the gate-leakage current is not related to the absolute area of the ZTO active layer, but it is reduced by reducing the ZTO/SiO2 area ratio. The ZTO/SiO2 area ratio modulates the ZTO-SiO2 interface dipole strength as well as the ZTO-SiO2 conduction band offset and subsequently affects the FN tunneling current through the SiO2 layer, which provides a route that modifies the gate-leakage current.

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

PubMed

Dimitrakopoulos; Purushothaman; Kymissis; Callegari; Shaw

1999-02-05

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.

Realization of an Ultra-thin Metasurface to Facilitate Wide Bandwidth, Wide Angle Beam Scanning.

PubMed

Bah, Alpha O; Qin, Pei-Yuan; Ziolkowski, Richard W; Cheng, Qiang; Guo, Y Jay

2018-03-19

A wide bandwidth, ultra-thin, metasurface is reported that facilitates wide angle beam scanning. Each unit cell of the metasurface contains a multi-resonant, strongly-coupled unequal arm Jerusalem cross element. This element consists of two bent-arm, orthogonal, capacitively loaded strips. The wide bandwidth of the metasurface is achieved by taking advantage of the strong coupling within and between its multi-resonant elements. A prototype of the proposed metasurface has been fabricated and measured. The design concept has been validated by the measured results. The proposed metasurface is able to alleviate the well-known problem of impedance mismatch caused by mutual coupling when the main beam of an array is scanned. In order to validate the wideband and wide scanning ability of the proposed metasurface, it is integrated with a wideband antenna array as a wide angle impedance matching element. The metasurface-array combination facilitates wide angle scanning over a 6:1 impedance bandwidth without the need for bulky dielectrics or multi-layered structures.

Transparent and Flexible Capacitors with an Ultrathin Structure by Using Graphene as Bottom Electrodes.

PubMed

Guo, Tao; Zhang, Guozhen; Su, Xi; Zhang, Heng; Wan, Jiaxian; Chen, Xue; Wu, Hao; Liu, Chang

2017-11-28

Ultrathin, transparent and flexible capacitors using graphene as the bottom electrodes were directly fabricated on polyethylene naphthalate (PEN) substrates. ZrO₂ dielectric films were deposited on the treated surface of graphene by atomic layer deposition (ALD). The deposition process did not introduce any detectible defects in the graphene, as indicated by Raman measurements, guaranteeing the electrical performances of the graphene electrodes. The Aluminum-doped zinc oxide (AZO) films were prepared as the top electrodes using the ALD technique. The capacitors presented a high capacitance density (10.3 fF/μm² at 10 kHz) and a relatively low leakage current (5.3 × 10 -6 A/cm² at 1 V). Bending tests revealed that the capacitors were able to work normally at an outward bending radius of 10 mm without any deterioration of electrical properties. The capacitors exhibited an average optical transmittance of close to 70% at visible wavelengths. Thus, it opens the door to practical applications in transparent integrated circuits.

Transparent and Flexible Capacitors with an Ultrathin Structure by Using Graphene as Bottom Electrodes

PubMed Central

Guo, Tao; Zhang, Guozhen; Su, Xi; Zhang, Heng; Wan, Jiaxian; Chen, Xue; Wu, Hao; Liu, Chang

2017-01-01

Ultrathin, transparent and flexible capacitors using graphene as the bottom electrodes were directly fabricated on polyethylene naphthalate (PEN) substrates. ZrO2 dielectric films were deposited on the treated surface of graphene by atomic layer deposition (ALD). The deposition process did not introduce any detectible defects in the graphene, as indicated by Raman measurements, guaranteeing the electrical performances of the graphene electrodes. The Aluminum-doped zinc oxide (AZO) films were prepared as the top electrodes using the ALD technique. The capacitors presented a high capacitance density (10.3 fF/μm2 at 10 kHz) and a relatively low leakage current (5.3 × 10−6 A/cm2 at 1 V). Bending tests revealed that the capacitors were able to work normally at an outward bending radius of 10 mm without any deterioration of electrical properties. The capacitors exhibited an average optical transmittance of close to 70% at visible wavelengths. Thus, it opens the door to practical applications in transparent integrated circuits. PMID:29182551

Hysteresis mechanism and control in pentacene organic field-effect transistors with polymer dielectric

NASA Astrophysics Data System (ADS)

Huang, Wei; Shi, Wei; Han, Shijiao; Yu, Junsheng

2013-05-01

Hysteresis mechanism of pentacene organic field-effect transistors (OFETs) with polyvinyl alcohol (PVA) and/or polymethyl methacrylate (PMMA) dielectrics is studied. Through analyzing the electrical characteristics of OFETs with various PVA/PMMA arrangements, it shows that charge, which is trapped in PVA bulk and at the interface of pentacene/PVA, is one of the origins of hysteresis. The results also show that memory window is proportional to both trap amount in PVA and charge density at the gate/PVA or PVA/pentacene interfaces. Hence, the controllable memory window of around 0 ˜ 10 V can be realized by controlling the thickness and combination of triple-layer polymer dielectrics.

Materials-Process Interactions in Ternary Alloy Semiconductors.

DTIC Science & Technology

1984-08-01

high, the surface potential can be * modulated . PECVD SiO. appears to be a viable candidate as a gate dielectric for * Irf ,fO-4A)s MISFETs...it is desirable to integrate the detectors with circuits capable of performing signal processing functions. These circuits can either be fabricated in...to be a major problem in In0. 5 3Ga 0.* 47 s. 25 S. . . . . 13821 -1 R I (a) CROSS SECTION KEYBOARD 210M ANNEALING CHAMBER GATE TRIGG TRIAC

Vacuum lamination approach to fabrication of high-performance single-crystal organic field-effect transistors.

PubMed

Yi, H T; Chen, Y; Czelen, K; Podzorov, V

2011-12-22

A novel vacuum lamination approach to fabrication of high-performance single-crystal organic field-effect transistors has been developed. The non-destructive nature of this method allows a direct comparison of field-effect mobilities achieved with various gate dielectrics using the same single-crystal sample. The method also allows gating delicate systems, such as n -type crystals and SAM-coated surfaces, without perturbation. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Approach to Multifunctional Device Platform with Epitaxial Graphene on Transition Metal Oxide (Postprint)

DTIC Science & Technology

2015-09-23

with a metal oxide ( TiO2 ). Our novel direct synthesis of graphene/ TiO2 heterostructure is achieved by C60 deposition on transition Ti metal surface...of TiO2 and C 2p orbitals in the conduction band of graphene enabled by Coulomb interactions at the interface. In addition, this heterostructure...provides a platform for realization of bottom gated graphene field effect devices with graphene and TiO2 playing the roles of channel and gate dielectric

Thick layered semiconductor devices with water top-gates: High on-off ratio field-effect transistors and aqueous sensors.

PubMed

Huang, Yuan; Sutter, Eli; Wu, Liangmei; Xu, Hong; Bao, Lihong; Gao, Hong-Jun; Zhou, Xingjiang; Sutter, Peter

2018-06-21

Layered semiconductors show promise as channel materials for field-effect transistors (FETs). Usually, such devices incorporate solid back or top gate dielectrics. Here, we explore de-ionized (DI) water as a solution top gate for field-effect switching of layered semiconductors including SnS2, MoS2, and black phosphorus. The DI water gate is easily fabricated, can sustain rapid bias changes, and its efficient coupling to layered materials provides high on-off current ratios, near-ideal sub-threshold swing, and enhanced short-channel behavior even for FETs with thick, bulk-like channels where such control is difficult to realize with conventional back-gating. Screening by the high-k solution gate eliminates hysteresis due to surface and interface trap states and substantially enhances the field-effect mobility. The onset of water electrolysis sets the ultimate limit to DI water gating at large negative gate bias. Measurements in this regime show promise for aqueous sensing, demonstrated here by the amperometric detection of glucose in aqueous solution. DI water gating of layered semiconductors can be harnessed in research on novel materials and devices, and it may with further development find broad applications in microelectronics and sensing.

Probing photoresponse of aligned single-walled carbon nanotube doped ultrathin MoS2.

PubMed

Wang, Rui; Wang, Tianjiao; Hong, Tu; Xu, Ya-Qiong

2018-08-24

We report a facile method to produce ultrathin molybdenum disulfide (MoS 2 ) hybrids with polarized near-infrared (NIR) photoresponses, in which horizontally-aligned single-walled carbon nanotubes (SWNTs) are integrated with single- and few-layer MoS 2 through a two-step chemical vapor deposition process. The photocurrent generation mechanisms in SWNT-MoS 2 hybrids are systematically investigated through wavelength- and polarization-dependent scanning photocurrent measurements. When the incident photon energy is above the direct bandgap of MoS 2 , isotropic photocurrent signals are observed, which can be primarily attributed to the direct bandgap transition in MoS 2 . In contrast, if the incident photon energy in the NIR region is below the direct bandgap of MoS 2 , the maximum photocurrent response occurs when the incident light is polarized in the direction along the SWNTs, indicating that photocurrent signals mainly result from the anisotropic absorption of SWNTs. More importantly, these two-dimensional (2D) hybrid structures inherit the electrical transport properties from MoS 2 , displaying n-type characteristics at a zero gate voltage. These fundamental studies provide a new way to produce ultrathin MoS 2 hybrids with inherited electrical properties and polarized NIR photoresponses, opening doors for engineering various 2D hybrid materials for future broadband optoelectronic applications.

Highly sensitive graphene biosensor by monomolecular self-assembly of receptors on graphene surface

NASA Astrophysics Data System (ADS)

Kim, Ji Eun; No, Young Hyun; Kim, Joo Nam; Shin, Yong Seon; Kang, Won Tae; Kim, Young Rae; Kim, Kun Nyun; Kim, Yong Ho; Yu, Woo Jong

2017-05-01

Graphene has attracted a great deal of interest for applications in bio-sensing devices because of its ultra-thin structure, which enables strong electrostatic coupling with target molecules, and its excellent electrical mobility promising for ultra-fast sensing speeds. However, thickly stacked receptors on the graphene's surface interrupts electrostatic coupling between graphene and charged biomolecules, which can reduce the sensitivity of graphene biosensors. Here, we report a highly sensitive graphene biosensor by the monomolecular self-assembly of designed peptide protein receptors. The graphene channel was non-covalently functionalized using peptide protein receptors via the π-π interaction along the graphene's Bravais lattice, allowing ultra-thin monomolecular self-assembly through the graphene lattice. In thickness dependent characterization, a graphene sensor with a monomolecular receptor (thickness less than 3 nm) showed five times higher sensitivity and three times higher voltage shifts than graphene sensors with thick receptor stacks (thicknesses greater than 20 nm), which is attributed to excellent gate coupling between graphene and streptavidin via an ultrathin receptor insulator. In addition to having a fast-inherent response time (less than 0.6 s) based on fast binding speed between biotin and streptavidin, our graphene biosensor is a promising platform for highly sensitive real-time monitoring of biomolecules with high spatiotemporal resolution.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Wideband and multi-frequency infrared cloaking of spherical objects by using the graphene-based metasurface.

PubMed

Shokati, Elnaz; Granpayeh, Nosrat; Danaeifar, Mohammad

2017-04-10

The ultrathin graphene metasurface is proposed as a mantle cloak to achieve wideband tunable scattering reduction around the spherical (three-dimensional) objects. The cloaking shell over the metallic or dielectric sphere is structured by a periodic array of graphene nanodisks that operate at infrared frequencies. By using the polarizability of the graphene nanodisks and equivalent conductivity method, the metasurface reactance is obtained. To achieve the cloaking shell for both dielectric and conducting spheres, the metasurface reactance as a function of nanodisks dimensions, graphene's Fermi energy, and permittivity of the surrounding areas can be tuned from the inductive to capacitive situation. Inhomogeneous metasurfaces including graphene nanodisks with different radii provide wideband invisibility due to extra resonances. We could significantly increase the 3-dB bandwidth more than the homogenous case by simpler realistic designs compared to the multi-layer structures. The analytical results are confirmed with full-wave numerical simulations.

On bistable states retention in ferroelectric Langmuir-Blodgett films

NASA Astrophysics Data System (ADS)

Geivandov, A. R.; Palto, S. P.; Yudin, S. G.; Fridkin, V. M.; Blinov, L. M.; Ducharme, S.

2003-08-01

A new insight into the nature of ferroelectricity is emerging from the study of ultra-thin ferroelectric films prepared of poly(vinylidene fluoride with trifluoroethylene) copolymer using Langmuir-Blodgett (LB) technique. Unique properties of these films indicate the existence of two-dimensional ferroelectricity. The retention of two polarized states in ferroelectric polymer LB films is studied using nonlinear dielectric spectroscopy. The technique is based on phase sensitive measurements of nonlinear dielectric spectroscopy. The amplitude of the current response at the 2nd harmonic of the applied voltage is proportional to the magnitude of the remnant polarization, while its phase gives the sign. We have found that 10 - 20 mm thick LB films can show fast switching time and long retention of the two polarized states. Nevertheless, LB films show a pronounced asymmetry in switching to the opposite states. Possible mechanisms of such behavior are discussed.

Dielectric-based subwavelength metallic meanders for wide-angle band absorbers.

PubMed

Shen, Su; Qiao, Wen; Ye, Yan; Zhou, Yun; Chen, Linsen

2015-01-26

We propose nano-meanders that can achieve wide-angle band absorption in visible regime. The nano-meander consists of a subwavelength dielectric grating covered by continuous ultra-thin Aluminum film (less than one tenth of the incident wavelength). The excited photonic resonant modes, such as cavity mode, surface plasmonic mode and Rayleigh-Wood anomaly, are discussed in detail. Nearly total resonant absorption due to funneling mechanism in the air nano-groove is almost invariant with large incident angle in transverse magnetic polarization. From both the structural geometry and the nanofabrication point of view, the light absorber has a very simple geometrical structure and it is easy to be integrated into complex photonic devices. The highly efficient angle-robust light absorber can be potential candidate for a range of passive and active photonic applications, including solar-energy harvesting as well as producing artificial colors on a large scale substrate.

Multilayer Transparent Top Electrode for Solution Processed Perovskite/Cu(In,Ga)(Se,S)2 Four Terminal Tandem Solar Cells.

PubMed

Yang, Yang Michael; Chen, Qi; Hsieh, Yao-Tsung; Song, Tze-Bin; Marco, Nicholas De; Zhou, Huanping; Yang, Yang

2015-07-28

Halide perovskites (PVSK) have attracted much attention in recent years due to their high potential as a next generation solar cell material. To further improve perovskites progress toward a state-of-the-art technology, it is desirable to create a tandem structure in which perovskite may be stacked with a current prevailing solar cell such as silicon (Si) or Cu(In,Ga)(Se,S)2 (CIGS). The transparent top electrode is one of the key components as well as challenges to realize such tandem structure. Herein, we develop a multilayer transparent top electrode for perovskite photovoltaic devices delivering an 11.5% efficiency in top illumination mode. The transparent electrode is based on a dielectric/metal/dielectric structure, featuring an ultrathin gold seeded silver layer. A four terminal tandem solar cell employing solution processed CIGS and perovskite cells is also demonstrated with over 15% efficiency.

Broadband and wide-angle light harvesting by ultra-thin silicon solar cells with partially embedded dielectric spheres.

PubMed

Yang, Zhenhai; Shang, Aixue; Qin, Linling; Zhan, Yaohui; Zhang, Cheng; Gao, Pingqi; Ye, Jichun; Li, Xiaofeng

2016-04-01

We propose a design of crystalline silicon thin-film solar cells (c-Si TFSCs, 2 μm-thick) configured with partially embedded dielectric spheres on the light-injecting side. The intrinsic light trapping and photoconversion are simulated by the complete optoelectronic simulation. It shows that the embedding depth of the spheres provides an effective way to modulate and significantly enhance the optical absorption. Compared to the conventional planar and front sphere systems, the optimized partially embedded sphere design enables a broadband, wide-angle, and strong optical absorption and efficient carrier transportation. Optoelectronic simulation predicts that a 2 μm-thick c-Si TFSC with half-embedded spheres shows an increment of more than 10  mA/cm² in short-circuit current density and an enhancement ratio of more than 56% in light-conversion efficiency, compared to the conventional planar counterparts.

Energy band offsets of dielectrics on InGaZnO4

NASA Astrophysics Data System (ADS)

Hays, David C.; Gila, B. P.; Pearton, S. J.; Ren, F.

2017-06-01

Thin-film transistors (TFTs) with channels made of hydrogenated amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) are used extensively in the display industry. Amorphous silicon continues to dominate large-format display technology, but a-Si:H has a low electron mobility, μ ˜ 1 cm2/V s. Transparent, conducting metal-oxide materials such as Indium-Gallium-Zinc Oxide (IGZO) have demonstrated electron mobilities of 10-50 cm2/V s and are candidates to replace a-Si:H for TFT backplane technologies. The device performance depends strongly on the type of band alignment of the gate dielectric with the semiconductor channel material and on the band offsets. The factors that determine the conduction and valence band offsets for a given material system are not well understood. Predictions based on various models have historically been unreliable and band offset values must be determined experimentally. This paper provides experimental band offset values for a number of gate dielectrics on IGZO for next generation TFTs. The relationship between band offset and interface quality, as demonstrated experimentally and by previously reported results, is also explained. The literature shows significant variations in reported band offsets and the reasons for these differences are evaluated. The biggest contributor to conduction band offsets is the variation in the bandgap of the dielectrics due to differences in measurement protocols and stoichiometry resulting from different deposition methods, chemistry, and contamination. We have investigated the influence of valence band offset values of strain, defects/vacancies, stoichiometry, chemical bonding, and contamination on IGZO/dielectric heterojunctions. These measurements provide data needed to further develop a predictive theory of band offsets.

All-dielectric metamaterials

NASA Astrophysics Data System (ADS)

Jahani, Saman; Jacob, Zubin

2016-01-01

The ideal material for nanophotonic applications will have a large refractive index at optical frequencies, respond to both the electric and magnetic fields of light, support large optical chirality and anisotropy, confine and guide light at the nanoscale, and be able to modify the phase and amplitude of incoming radiation in a fraction of a wavelength. Artificial electromagnetic media, or metamaterials, based on metallic or polar dielectric nanostructures can provide many of these properties by coupling light to free electrons (plasmons) or phonons (phonon polaritons), respectively, but at the inevitable cost of significant energy dissipation and reduced device efficiency. Recently, however, there has been a shift in the approach to nanophotonics. Low-loss electromagnetic responses covering all four quadrants of possible permittivities and permeabilities have been achieved using completely transparent and high-refractive-index dielectric building blocks. Moreover, an emerging class of all-dielectric metamaterials consisting of anisotropic crystals has been shown to support large refractive index contrast between orthogonal polarizations of light. These advances have revived the exciting prospect of integrating exotic electromagnetic effects in practical photonic devices, to achieve, for example, ultrathin and efficient optical elements, and realize the long-standing goal of subdiffraction confinement and guiding of light without metals. In this Review, we present a broad outline of the whole range of electromagnetic effects observed using all-dielectric metamaterials: high-refractive-index nanoresonators, metasurfaces, zero-index metamaterials and anisotropic metamaterials. Finally, we discuss current challenges and future goals for the field at the intersection with quantum, thermal and silicon photonics, as well as biomimetic metasurfaces.

Electrochemical formation of field emitters

DOEpatents

Bernhardt, A.F.

1999-03-16

Electrochemical formation of field emitters, particularly useful in the fabrication of flat panel displays is disclosed. The fabrication involves field emitting points in a gated field emitter structure. Metal field emitters are formed by electroplating and the shape of the formed emitter is controlled by the potential imposed on the gate as well as on a separate counter electrode. This allows sharp emitters to be formed in a more inexpensive and manufacturable process than vacuum deposition processes used at present. The fabrication process involves etching of the gate metal and the dielectric layer down to the resistor layer, and then electroplating the etched area and forming an electroplated emitter point in the etched area. 12 figs.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

NASA Astrophysics Data System (ADS)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} as potential gate dielectrics for GaN/Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Partida-Manzanera, T., E-mail: sgtparti@liv.ac.uk; Institute of Materials Research and Engineering, A*STAR; Roberts, J. W.

2016-01-14

This paper describes a method to optimally combine wide band gap Al{sub 2}O{sub 3} with high dielectric constant (high-κ) Ta{sub 2}O{sub 5} for gate dielectric applications. (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta{sub 2}O{sub 5} molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al{sub 2}O{sub 3} to 4.6 eV for pure Ta{sub 2}O{sub 5}. The dielectric constant calculated from capacitance-voltage measurementsmore » also increases linearly from 7.8 for Al{sub 2}O{sub 3} up to 25.6 for Ta{sub 2}O{sub 5}. The effect of post-deposition annealing in N{sub 2} at 600 °C on the interfacial properties of undoped Al{sub 2}O{sub 3} and Ta-doped (Ta{sub 2}O{sub 5}){sub 0.12}(Al{sub 2}O{sub 3}){sub 0.88} films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al{sub 2}O{sub 3}/GaN-HEMT and (Ta{sub 2}O{sub 5}){sub 0.16}(Al{sub 2}O{sub 3}){sub 0.84}/GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al{sub 2}O{sub 3} can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.« less

Vertical dielectric screening of few-layer van der Waals semiconductors.

PubMed

Koo, Jahyun; Gao, Shiyuan; Lee, Hoonkyung; Yang, Li

2017-10-05

Vertical dielectric screening is a fundamental parameter of few-layer van der Waals two-dimensional (2D) semiconductors. However, unlike the widely-accepted wisdom claiming that the vertical dielectric screening is sensitive to the thickness, our first-principles calculation based on the linear response theory (within the weak field limit) reveals that this screening is independent of the thickness and, in fact, it is the same as the corresponding bulk value. This conclusion is verified in a wide range of 2D paraelectric semiconductors, covering narrow-gap ones and wide-gap ones with different crystal symmetries, providing an efficient and reliable way to calculate and predict static dielectric screening of reduced-dimensional materials. Employing this conclusion, we satisfactorily explain the tunable band gap in gated 2D semiconductors. We further propose to engineer the vertical dielectric screening by changing the interlayer distance via vertical pressure or hybrid structures. Our predicted vertical dielectric screening can substantially simplify the understanding of a wide range of measurements and it is crucial for designing 2D functional devices.