Challenges with Operating a Water Recovery System (WRS) in the Microgravity Environment of the International Space Station (ISS)

NASA Technical Reports Server (NTRS)

Carter, Donald Layne

2017-01-01

The ISS WRS produces potable water from crew urine, crew latent, and Sabatier product water. This system has been operational on ISS since November 2008, producing over 30,000 L of water during that time. The WRS includes a Urine Processor Assembly (UPA) to produce a distillate from the crew urine. This distillate is combined with the crew latent and Sabatier product water and further processed by the Water Processor Assembly (WPA) to the potable water. The UPA and WPA use technologies commonly used on ISS for water purification, including filtration, distillation, adsorption, ion exchange, and catalytic oxidation. The primary challenge with the design and operation of the WRS has been with implementing these technologies in microgravity. The absence of gravity has created unique issues that impact the constituency of the waste streams, alter two-phase fluid dynamics, and increases the impact of particulates on system performance. NASA personnel continue to pursue upgrades to the existing design to improve reliability while also addressing their viability for missions beyond ISS.

Investigation of DMSD Trend in the ISS Water Processor Assembly

NASA Technical Reports Server (NTRS)

Carter, Layne; Bowman, Elizabeth; Wilson, Mark; Gentry, Greg; Rector, Tony

2013-01-01

The ISS Water Recovery System (WRS) is responsible for providing potable water to the crew, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. The WRS includes the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WPA processes condensate from the cabin air and distillate produced by the UPA. In 2010, an increasing trend in the Total Organic Carbon (TOC) in the potable water was ultimately identified as dimethylsilanediol (DMSD). The increasing trend was ultimately reversed after replacing the WPA's two multifiltration beds. However, the reason for the TOC trend and the subsequent recovery was not understood. A subsequent trend occurred in 2012. This paper summarizes the current understanding of the fate of DMSD in the WPA, how the increasing TOC trend occurred, and the plan for modifying the WPA to prevent recurrence.

Marshburn updates software on the WHC UPA in the Node 3

NASA Image and Video Library

2013-01-17

ISS034-E-031133 (17 Jan. 2013) --- NASA astronaut Tom Marshburn, Expedition 34 flight engineer, updates software on the Waste and Hygiene Compartment?s Urine Processor Assembly in the Tranquility node of the International Space Station.

Marshburn updates software on the WHC UPA in the Node 3

NASA Image and Video Library

2013-01-17

ISS034-E-031130 (17 Jan. 2013) --- NASA astronaut Tom Marshburn, Expedition 34 flight engineer, updates software on the Waste and Hygiene Compartment?s Urine Processor Assembly in the Tranquility node of the International Space Station.

Status of the Node 3 Regenerative Environmental Cpntrol& Life Support System Water Recovery & Oxygen Generation Systems

NASA Technical Reports Server (NTRS)

Carrasquillo, Robyn L.

2003-01-01

NASA s Marshall Space Flight Center is providing three racks containing regenerative water recovery and oxygen generation systems (WRS and OGS) for flight on the lnternational Space Station s (ISS) Node 3 element. The major assemblies included in these racks are the Water Processor Assembly (WPA), Urine Processor Assembly (UPA), Oxygen Generation Assembly (OGA), and the Power Supply Module (PSM) supporting the OGA. The WPA and OGA are provided by Hamilton Sundstrand Space Systems lnternational (HSSSI), while the UPA and PSM are being designed and manufactured in-house by MSFC. The assemblies are currently in the manufacturing and test phase and are to be completed and integrated into flight racks this year. This paper gives an overview of the technologies and system designs, technical challenges encountered and solved, and the current status.

Upgrades to the International Space Station Water Recovery System

NASA Technical Reports Server (NTRS)

Kayatin, Matthew J.; Pruitt, Jennifer M.; Nur, Mononita; Takada, Kevin C.; Carter, Layne

2017-01-01

The International Space Station (ISS) Water Recovery System (WRS) includes the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WRS produces potable water from a combination of crew urine (first processed through the UPA), crew latent, and Sabatier product water. Though the WRS has performed well since operations began in November 2008, several modifications have been identified to improve the overall system performance. These modifications aim to reduce resupply and improve overall system reliability, which is beneficial for the ongoing ISS mission as well as for future NASA manned missions. The following paper details efforts to improve the WPA through the use of reverse osmosis membrane technology to reduce the resupply mass of the WPA Multi-filtration Bed and improved catalyst for the WPA Catalytic Reactor to reduce the operational temperature and pressure. For the UPA, this paper discusses progress on various concepts for improving the reliability of the system, including the implementation of a more reliable drive belt, improved methods for managing condensate in the stationary bowl of the Distillation Assembly, and evaluating upgrades to the UPA vacuum pump.

Ion Exchange Technology Development in Support of the Urine Processor Assembly Precipitation Prevention Project for the International Space Station

NASA Technical Reports Server (NTRS)

Mitchell, Julie L.; Broyan, James L.; Pickering, Karen D.; Adam, Niklas; Casteel, Michael; Callahan, Michael; Carrier, Chris

2012-01-01

In support of the Urine Processor Assembly Precipitation Prevention Project (UPA PPP), multiple technologies were explored to prevent CaSO4 2H2O (gypsum) precipitation during the on-orbit distillation process. Gypsum precipitation currently limits the water recovery rate onboard the International Space Station (ISS) to 70% versus the planned 85% target water recovery rate. Due to its ability to remove calcium cations in pretreated augmented urine (PTAU), ion exchange was selected as one of the technologies for further development by the PPP team. A total of 13 ion exchange resins were evaluated in various equilibrium and dynamic column tests with solutions of dissolved gypsum, urine ersatz, PTAU, and PTAU brine at 85% water recovery. While initial evaluations indicated that the Purolite SST60 resin had the highest calcium capacity in PTAU (0.30 meq/mL average), later tests showed that the Dowex G26 and Amberlite FPC12H resins had the highest capacity (0.5 meq/mL average). Testing at the Marshall Spaceflight Center (MSFC) integrates the ion exchange technology with a UPA ground article under flight-like pulsed flow conditions with PTAU. To date, no gypsum precipitation has taken place in any of the initial evaluations.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Wilson, Laura Labuda; Orozco, Nicole

2012-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2011, and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Pruitt, Jennifer; Brown, Christopher A.; Bazley, Jesse; Gazda, Daniel; Schaezler, Ryan; Bankers, Lyndsey

2016-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2016 and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Brown, Christopher; Orozco, Nicole

2014-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of June 2013, and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Tobias, Barry; Orozco, Nicole

2012-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of June 2012, and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Takada, Kevin; Gazda, Daniel; Brown, Christopher; Bazley, Jesse; Schaezler, Ryan; Bankers, Lyndsey

2017-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of June 2017 and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Pruitt, Jennifer; Brown, Christopher A.; Schaezler, Ryan; Bankers, Lyndsey

2015-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2015 and describes the technical challenges encountered and lessons learned over the past two years.

A Biologically-Based Alternative Water Processor for Long Duration Space Missions

NASA Technical Reports Server (NTRS)

Barta, Daniel J.; Pickering, Karen D.; Meyer, Caitlin; Pensinger, Stuart; Vega, Leticia; Flynn, Michael; Jackson, Andrew; Wheeler, Raymond

2015-01-01

A wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multifiltration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP was operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to maximum based on available carbon. The FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater.

Ion Exchange Technology Development in Support of the Urine Processor Assembly Precipitation Prevention Project for the International Space Station

NASA Technical Reports Server (NTRS)

Mitchell, Julie L.; Broyan, James L.; Pickering, Karen D.; Adam, Niklas; Casteel, Michael; Callaham, Michael; Carrier, Chris

2011-01-01

In support of the Urine Processor Assembly Precipitation Prevention Project (UPA PPP), multiple technologies were explored to prevent CaSO4 dot 2H2O (gypsum) precipitation during the on-orbit distillation process. Gypsum precipitation currently limits the water recovery rate onboard the International Space Station (ISS) to 70% versus the planned 85% target water recovery rate. Due to its advanced performance in removing calcium cations in pretreated augmented urine (PTAU), ion exchange was selected as one of the technologies for further development by the PPP team. A total of 12 ion exchange resins were evaluated in various equilibrium and dynamic column tests with solutions of dissolved gypsum, urine ersatz, PTAU, and PTAU brine at 85% water recovery. While initial evaluations indicated that the Purolite SST60 resin had the highest calcium capacity in PTAU (0.30 meq/mL average), later tests showed that the Dowex G26 and Amberlite FPC12H resins had the highest capacity (0.5 meq/mL average). Further dynamic column testing proved that G26 performance is +/- 10% of that value at flow rates of 0.45 and 0.79 Lph under continuous flow, and 10.45 Lph under pulsed flow. Testing at the Marshall Spaceflight Center (MSFC) integrates the ion exchange technology with a UPA ground article under flight-like pulsed flow conditions with PTAU. To date, no gypsum precipitation has taken place in any of the initial evaluations.

Evaluation of Technologies to Prevent Precipitation During Water Recovery from Urine

NASA Technical Reports Server (NTRS)

Broyan, James L., Jr.; Pickering, Karen D.; Adam, Niklas M.; Mitchell, Julie L.; Anderson, Molly S.; Carter, Layne; Muirhead, Dean; Gazda, Daniel B.

2011-01-01

The International Space Station (ISS) Urine Processor Assembly (UPA) experienced a hardware failure in the Distillation Assembly (DA) in October 2010. Initially the UPA was operated to recover 85% of the water from urine through distillation, concentrating the contaminants in the remaining urine. The DA failed due to precipitation of calcium sulfate (gypsum) which caused a loss of UPA function. The ISS UPA operations have been modified to only recover 70% of the water minimizing gypsum precipitation risk but substantially increasing water resupply needs. This paper describes the feasibility assessment of several technologies (ion exchange, chelating agents, threshold inhibitors, and Lorentz devices) to prevent gypsum precipitation. The feasibility assessment includes the development of assessment methods, chemical modeling, bench top testing, and validation testing in a flight-like ground UPA unit. Ion exchange technology has been successfully demonstrated and has been recommended for further development. The incorporation of the selected technology will enable water recovery to be increased from 70% back to the original 85% and improve the ISS water balance.

Regenerative (Regen) ECLSS Operations Water Balance

NASA Technical Reports Server (NTRS)

Tobias, Barry

2010-01-01

In November 2008, the Water Regenerative System racks were launched aboard Space Shuttle flight, STS-126 (ULF2) and installed and activated on the International Space Station (ISS). These racks, consisting of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA), completed the installation of the Regenerative (Regen) ECLSS systems which includes the Oxygen Generator Assembly (OGA) that was launched 2 years prior. With the onset of active water management on the US segment of the ISS, a new operational concept was required, that of "water balance." Even more recently, in 2010 the Sabatier system came online which converts H2 and CO2 into water and methane. The Regen ECLSS systems accept condensation from the atmosphere, urine from crew, and processes that fluid via various means into potable water which is used for crew drinking, building up skip-cycle water inventory, and water for electrolysis to produce oxygen. Specification rates of crew urine output, condensate output, O2 requirements, toilet flush water and drinking needs are well documented and used as a general plan when Regen ECLSS came online. Spec rates are useful in long term planning, however, daily or weekly rates are dependent on a number of variables. The constantly changing rates created a new challenge for the ECLSS flight controllers, who are responsible for operating the ECLSS systems onboard ISS. This paper will review the various inputs to rate changes and inputs to planning events, including but not limited to; crew personnel makeup, Regen ECLSS system operability, vehicle traffic, water containment availability, and Carbon Dioxide Removal Assembly (CDRA) capability. Along with the inputs that change the various rates, the paper will review the different systems, their constraints and finally the operational means by which flight controllers manage this new challenge of "water balance."

International Space Station (ISS) Advanced Recycle Filter Tank Assembly (ARFTA)

NASA Technical Reports Server (NTRS)

Nasrullah, Mohammed K.

2013-01-01

The International Space Station (ISS) Recycle Filter Tank Assembly (RFTA) provides the following three primary functions for the Urine Processor Assembly (UPA): volume for concentrating/filtering pretreated urine, filtration of product distillate, and filtration of the Pressure Control and Pump Assembly (PCPA) effluent. The RFTAs, under nominal operations, are to be replaced every 30 days. This poses a significant logistical resupply problem, as well as cost in upmass and new tanks purchase. In addition, it requires significant amount of crew time. To address and resolve these challenges, NASA required Boeing to develop a design which eliminated the logistics and upmass issues and minimize recurring costs. Boeing developed the Advanced Recycle Filter Tank Assembly (ARFTA) that allowed the tanks to be emptied on-orbit into disposable tanks that eliminated the need for bringing the fully loaded tanks to earth for refurbishment and relaunch, thereby eliminating several hundred pounds of upmass and its associated costs. The ARFTA will replace the RFTA by providing the same functionality, but with reduced resupply requirements

An Alternative Water Processor for Long Duration Space Missions

NASA Technical Reports Server (NTRS)

Barta, Daniel J.; Pickering, Karen D.; Meyer, Caitlin; Pennsinger, Stuart; Vega, Leticia; Flynn, Michael; Jackson, Andrew; Wheeler, Raymond

2014-01-01

A new wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration human space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multi-filtration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP has been operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to stoichiometric maximum based on available carbon. To date, the FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater

WRS2 UPA DA Removal

NASA Image and Video Library

2009-11-23

ISS021-E-032275 (23 Nov. 2009) --- NASA astronaut Leland Melvin, STS-129 mission specialist, holds the failed Urine Processor Assembly / Distillation Assembly (UPA DA) in the Destiny laboratory of the International Space Station while space shuttle Atlantis remains docked with the station. Melvin and European Space Agency astronaut Frank De Winne (out of frame), Expedition 21 commander, removed and packed the UPA DA, then transferred it from the Water Recovery System 2 (WRS-2) rack to Atlantis for stowage on the middeck.

WRS2 UPA DA Removal

NASA Image and Video Library

2009-11-23

ISS021-E-032273 (23 Nov. 2009) --- European Space Agency astronaut Frank De Winne, Expedition 21 commander, holds the failed Urine Processor Assembly / Distillation Assembly (UPA DA) in the Destiny laboratory of the International Space Station while space shuttle Atlantis remains docked with the station. De Winne and NASA astronaut Leland Melvin (out of frame), STS-129 mission specialist, removed and packed the UPA DA, then transferred it from the Water Recovery System 2 (WRS-2) rack to Atlantis for stowage on the middeck.

Cascade Distiller System Performance Testing Interim Results

NASA Technical Reports Server (NTRS)

Callahan, Michael R.; Pensinger, Stuart; Sargusingh, Miriam J.

2014-01-01

The Cascade Distillation System (CDS) is a rotary distillation system with potential for greater reliability and lower energy costs than existing distillation systems. Based upon the results of the 2009 distillation comparison test (DCT) and recommendations of the expert panel, the Advanced Exploration Systems (AES) Water Recovery Project (WRP) project advanced the technology by increasing reliability of the system through redesign of bearing assemblies and improved rotor dynamics. In addition, the project improved the CDS power efficiency by optimizing the thermoelectric heat pump (TeHP) and heat exchanger design. Testing at the NASA-JSC Advanced Exploration System Water Laboratory (AES Water Lab) using a prototype Cascade Distillation Subsystem (CDS) wastewater processor (Honeywell d International, Torrance, Calif.) with test support equipment and control system developed by Johnson Space Center was performed to evaluate performance of the system with the upgrades as compared to previous system performance. The system was challenged with Solution 1 from the NASA Exploration Life Support (ELS) distillation comparison testing performed in 2009. Solution 1 consisted of a mixed stream containing human-generated urine and humidity condensate. A secondary objective of this testing is to evaluate the performance of the CDS as compared to the state of the art Distillation Assembly (DA) used in the ISS Urine Processor Assembly (UPA). This was done by challenging the system with ISS analog waste streams. This paper details the results of the AES WRP CDS performance testing.

Environmental Control and Life Support System, Water Recovery System

NASA Technical Reports Server (NTRS)

2000-01-01

The Environmental Control and Life Support System (ECLSS) Group of the Flight Projects Directorate at the Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. This is a close-up view of ECLSS Water Recovery System (WRS) racks. The MSFC's ECLSS Group overseas much of the development of the hardware that will allow a constant supply of clean water for four to six crewmembers aboard the ISS. The WRS provides clean water through the reclamation of wastewaters, including water obtained from the Space Shuttle's fuel cells, crewmember urine, used shower, handwash and oral hygiene water cabin humidity condensate, and Extravehicular Activity (EVA) wastes. The WRS is comprised of a Urine Processor Assembly (UPA), and a Water Processor Assembly (WPA). The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the WPA, which removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. Product water quality is monitored primarily through conductivity measurements. Unacceptable water is sent back through the WPA for reprocessing. Clean water is sent to a storage tank. The water must meet stringent purity standards before consumption by the crew. The UPA provided by the MSFC and the WRA is provided by the prime contractor, Hamilton Sundstrand Space Systems, International (HSSSI) from Cornecticut.

International Space Station Water Balance Operations

NASA Technical Reports Server (NTRS)

Tobias, Barry; Garr, John D., II; Erne, Meghan

2011-01-01

In November 2008, the Water Regenerative System racks were launched aboard Space Shuttle flight, STS-126 (ULF2) and installed and activated on the International Space Station (ISS). These racks, consisting of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA), completed the installation of the Regenerative (Regen) Environmental Control and Life Support Systems (ECLSS), which includes the Oxygen Generation Assembly (OGA) that was launched 2 years prior. With the onset of active water management on the US segment of the ISS, a new operational concept was required, that of water balance . In November of 2010, the Sabatier system, which converts H2 and CO2 into water and methane, was brought on line. The Regen ECLSS systems accept condensation from the atmosphere, urine from crew, and processes that fluid via various means into potable water, which is used for crew drinking, building up skip-cycle water inventory, and water for electrolysis to produce oxygen. Specification (spec) rates of crew urine output, condensate output, O2 requirements, toilet flush water, and drinking needs are well documented and used as the best guess planning rates when Regen ECLSS came online. Spec rates are useful in long term planning, however, daily or weekly rates are dependent upon a number of variables. The constantly changing rates created a new challenge for the ECLSS flight controllers, who are responsible for operating the ECLSS systems onboard ISS from Mission Control in Houston. This paper reviews the various inputs to water planning, rate changes, and dynamic events, including but not limited to: crew personnel makeup, Regen ECLSS system operability, vehicle traffic, water storage availability, and Carbon Dioxide Removal Assembly (CDRA), Sabatier, and OGA capability. Along with the inputs that change the various rates, the paper will review the different systems, their constraints, and finally the operational challenges and means by which flight controllers manage this new concept of "water balance."

Use of DSC and DMA Techniques to Help Investigate a Material Anomaly for PTFE Used in Processing a Piston Cup for the Urine Processor Assembly (UPA) on International Space Station (ISS)

NASA Technical Reports Server (NTRS)

Wingard, Doug

2010-01-01

Human urine and flush water are eventually converted into drinking water with the Urine Processor Assembly (UPA) aboard the International Space Station (ISS). This conversion is made possible through the Distillation Assembly (DA) of the UPA. One component of the DA is a molded circular piston cup made of virgin polytetrafluoroethylene (PTFE). The piston cup is assembled to a titanium component using eight fasteners and washers. Molded PTFE produced for spare piston cups in the first quarter of 2010 was different in appearance and texture, and softer than material molded for previous cups. For the suspect newer PTFE material, cup fasteners were tightened to only one-half the required torque value, yet the washers embedded almost halfway into the material. The molded PTFE used in the DA piston cup should be Type II, based on AMS 3667D and ASTM D4894 specifications. The properties of molded PTFE are considerably different between Type I and II materials. Engineers working with the DA thought that if Type I PTFE was molded by mistake instead of Type II material, that could have resulted in the anomalous material properties. Typically, the vendor molds flat sheet PTFE from the same material lot used to mold the piston cups, and tensile testing as part of quality control should verify that the PTFE is Type II material. However, for this discrepant lot of material, such tensile data was not available. Differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA) were two of the testing techniques used at the NASA/Marshall Space Flight Center (MSFC) to investigate the anomaly for the PTFE material. Other techniques used on PTFE specimens were: Shore D hardness testing, tensile testing on dog bone specimens and a qualitative estimation of porosity by optical and scanning electron microscopy.

International Space Station (ISS)

NASA Image and Video Library

2001-03-01

The Environmental Control and Life Support System (ECLSS) Group of the Flight Projects Directorate at the Marshall Space Flight Center in Huntsville, Alabama, is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. This photograph shows the mockup of the the ECLSS to be installed in the Node 3 module of the ISS. From left to right, shower rack, waste management rack, Water Recovery System (WRS) Rack #2, WRS Rack #1, and Oxygen Generation System (OGS) rack are shown. The WRS provides clean water through the reclamation of wastewaters and is comprised of a Urine Processor Assembly (UPA) and a Water Processor Assembly (WPA). The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the WPA. The WPA removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. The OGS produces oxygen for breathing air for the crew and laboratory animals, as well as for replacing oxygen loss. The OGS is comprised of a cell stack, which electrolyzes (breaks apart the hydrogen and oxygen molecules) some of the clean water provided by the WRS, and the separators that remove the gases from the water after electrolysis.

Life Testing of the Vapor Compression Distillation/Urine Processing Assembly (VCD/UPA) at the Marshall Space Flight Center (1993 to 1997)

NASA Technical Reports Server (NTRS)

Wieland, P.; Hutchens, C.; Long, D.; Salyer, B.

1998-01-01

Wastewater and urine generated on the International Space Station will be processed to recover pure water using vapor compression distillation (VCD). To verify the long-term reliability and performance of the VCD Urine Processor Assembly (UPA), life testing was performed at the Marshall Space Flight Center (MSFC) from January 1993 to April 1996. Two UPA'S, the VCD-5 and VCD-5A, were tested for 204 days and 665 days, respectively. The compressor gears and the distillation centrifuge drive belt were found to have operating lives of approximately 4,800 hours, equivalent to 3.9 years of operation on ISS for a crew of three at an average processing rate of 1.76 kg/h (3.97 lb/h). Precise alignment of the flex-splines of the fluids and purge pump motor drives is essential to avoid premature failure after about 400 hours of operation. Results indicate that, with some design and procedural modifications and suitable quality control, the required performance and operational life can be met with the VCD/UPA.

Environmental Control and Life Support System Mockup

NASA Technical Reports Server (NTRS)

2001-01-01

The Environmental Control and Life Support System (ECLSS) Group of the Flight Projects Directorate at the Marshall Space Flight Center in Huntsville, Alabama, is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. This photograph shows the mockup of the the ECLSS to be installed in the Node 3 module of the ISS. From left to right, shower rack, waste management rack, Water Recovery System (WRS) Rack #2, WRS Rack #1, and Oxygen Generation System (OGS) rack are shown. The WRS provides clean water through the reclamation of wastewaters and is comprised of a Urine Processor Assembly (UPA) and a Water Processor Assembly (WPA). The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the WPA. The WPA removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. The OGS produces oxygen for breathing air for the crew and laboratory animals, as well as for replacing oxygen loss. The OGS is comprised of a cell stack, which electrolyzes (breaks apart the hydrogen and oxygen molecules) some of the clean water provided by the WRS, and the separators that remove the gases from the water after electrolysis.

Getting Out of Orbit: Water Recycling Requirements and Technology Needs for Long Duration Missions Away from Earth

NASA Technical Reports Server (NTRS)

Barta, Daniel J.

2017-01-01

Deep-space crewed missions will not have regular access to the Earth's resources or the ability to rapidly return to Earth if a system fails. As crewed missions extend farther from Earth for longer periods, habitation systems must become more self-sufficient and reliable for safe, healthy, and sustainable human exploration. For human missions to Mars, Environmental Control and Life Support Systems (ECLSS) must be able operate for up to 1,100 days with minimal spares and consumables. These missions will require capabilities to more fully recycle atmospheric gases and wastewater to substantially reduce mission costs. Even with relatively austere requirements for use, water represents one of the largest consumables by mass. Systems must be available to extract and recycle water from all sources of waste. And given that there will be no opportunity to send samples back to Earth for analysis, analytical measurements will be limited to monitoring hardware brought on board the spacecraft. The Earth Reliant phase of NASA's exploration strategy includes leveraging the International Space Station (ISS) to demonstrate advanced capabilities for a robust and reliable ECLSS. The ISS Water Recovery System (WRS) includes a Urine Processor Assembly (UPA) for distillation and recovery of water from urine and a Water Processor Assembly (WPA) to process humidity condensate and urine distillate into potable water. Possible enhancements to more fully "close the water loop" include recovery of water from waste brines and solid wastes. A possible game changer is the recovery of water from local planetary resources through use of In Situ Resource Utilization (ISRU) technologies. As part of the development and demonstration sequence, NASA intends to utilize cis-Lunar space as a Proving Ground to verify systems for deep space habitation by conducting extended duration missions to validate our readiness for Mars.

Coiled Brine Recovery Assembly (CoBRA): A New Approach to Recovering Water from Wastewater Brines

NASA Technical Reports Server (NTRS)

Pensinger, Stuart J.

2015-01-01

Brine water recovery represents a current technology gap in water recycling for human spaceflight. The role of a brine processor is to take the concentrated discharge from a primary wastewater processor, called brine, and recover most of the remaining water from it. The current state-of-the-art primary processor is the ISS Urine Processor Assembly (UPA) that currently achieves 70% water recovery. Recent advancements in chemical pretreatments are expected to increase this to 85% in the near future. This is a welcome improvement, yet is still not high enough for deep space transit. Mission architecture studies indicate that at least 95% is necessary for a Mars mission, as an example. Brine water recovery is the technology that bridges the gap between 85% and 95%, and moves life support systems one step closer to full closure of the water loop. Several brine water recovery systems have been proposed for human spaceflight, most of them focused on solving two major problems: operation in a weightless environment, and management and containment of brine residual. Brine residual is the leftover byproduct of the brine recovery process, and is often a viscous, sticky paste, laden with crystallized solid particles. Due to the chemical pretreatments added to wastewater prior to distillation in a primary processor, these residuals are typically toxic, which further complicates matters. Isolation of crewmembers from these hazardous materials is paramount. The Coiled Brine Recovery Assembly (CoBRA) is a recently developed concept from the Johnson Space Center that offers solutions to these challenges. CoBRA is centered on a softgoods evaporator that enables a passive fill with brine, and regeneration by discharging liquid brine residual to a collection bag. This evaporator is meant to be lightweight, which allows it to be discarded along with the accumulated brine solids contained within it. This paper discusses design and development of a first CoBRA prototype, and reports initial test results.

Ion Exchange Technology Development in Support of the Urine Processor Assembly

NASA Technical Reports Server (NTRS)

Mitchell, Julie; Broyan, James; Pickering, Karen

2013-01-01

The urine processor assembly (UPA) on the International Space Station (ISS) recovers water from urine via a vacuum distillation process. The distillation occurs in a rotating distillation assembly (DA) where the urine is heated and subjected to sub-ambient pressure. As water is removed, the original organics, salts, and minerals in the urine become more concentrated and result in urine brine. Eventually, water removal will concentrate the urine brine to super saturation of individual constituents, and precipitation occurs. Under typical UPA DA operating conditions, calcium sulfate or gypsum is the first chemical to precipitate in substantial quantity. During preflight testing with ground urine, the UPA achieved 85% water recovery without precipitation. However, on ISS, it is possible that crewmember urine can be significantly more concentrated relative to urine from ground donors. As a result, gypsum precipitated in the DA when operating at water recovery rates at or near 85%, causing the failure and subsequent re14 NASA Tech Briefs, September 2013 placement of the DA. Later investigations have demonstrated that an excess of calcium and sulfate will cause precipitation at water recovery rates greater than 70%. The source of the excess calcium is likely physiological in nature, via crewmembers' bone loss, while the excess sulfate is primarily due to the sulfuric acid component of the urine pretreatment. To prevent gypsum precipitation in the UPA, the Precipitation Prevention Project (PPP) team has focused on removing the calcium ion from pretreated urine, using ion exchange resins as calcium removal agents. The selectivity and effectiveness of ion exchange resins are determined by such factors as the mobility of the liquid phase through the polymer matrix, the density of functional groups, type of functional groups bound to the matrix, and the chemical characteristics of the liquid phase (pH, oxidation potential, and ionic strength). Previous experience with ion exchange resins has demonstrated that the most effective implementation for an ion exchange resin is a cartridge, or column, in which the resin is contained. Based on the results of equilibrium and sub-scale dynamic column testing, a possible solution for mitigating the calcium precipitation issue on the ISS has been identified. From an original pool of 13 ion exchange resins, two candidates have been identified that demonstrate substantial calcium removal on the sub-scale. The dramatic reduction in resin performance from published calcium uptake demonstrates the need for thorough evaluation of resins at the low pH and strong oxidizing environment present in the UPA. Chemical variations in the influent (calcium concentrations and pretreatment dosing) appear to have a noticeable impact on the calcium capacity of the resin. Low calcium concentrations and high pretreatment dosing will likely result in a decrease in calcium capacity. Conversely, low pre trea t - ment dosing will likely result in an increase in calcium capacity. In contrast, investigations at a variety of flow rates, length-to-diameter ratios, resin volumes, and flow regimes (continuous versus pulsed) show that changes in physical parameters do not have substantial impacts on resin performance in the very low specific velocity ranges of interest. This result is particularly useful because most commercial applications at higher specific velocities do show a relatively strong relationship between flow and capacity. The lack of a strong relationship will allow more flexibility in the implementation of an ion exchange bed for flight. Verification of subscale tests with flight-scale resin beds is recommended prior to implementation in the on-orbit UPA.

Status of the International Space Station Waste and Hygiene Compartment

NASA Technical Reports Server (NTRS)

Walker, Stephanie; Zahner, Christopher

2010-01-01

The Waste and Hygiene Compartment (WHC) serves as the primary system for removal and containment of metabolic waste and hygiene activities on board the United States segment of the International Space Station (ISS). The WHC was launched on ULF 2 and is currently in the U.S. Laboratory and is integrated into the Water Recovery System (WRS) where pretreated urine is processed by the Urine Processor Assembly (UPA). The waste collection part of the WHC system is derived from the Service Module system and was provided by RSC-Energia along with additional hardware to allow for urine delivery to the UPA. The System has been integrated in an ISS standard equipment rack structure for use on the U.S. segment of the ISS. The system has experienced several events of interest during the deployment, checkout, and operation of the system during its first year of use and these will be covered in this paper. Design and on-orbit performance will also be discussed.

Results of the Vapor Compression Distillation Flight Experiment (VCD-FE)

NASA Technical Reports Server (NTRS)

Hutchens, Cindy; Graves, Rex

2004-01-01

Vapor Compression Distillation (VCD) is the chosen technology for urine processing aboard the International Space Station (ISS). Key aspects of the VCD design have been verified and significant improvements made throughout the ground;based development history. However, an important element lacking from previous subsystem development efforts was flight-testing. Consequently, the demonstration and validation of the VCD technology and the investigation of subsystem performance in micro-gravity were the primary goals of the VCD-FE. The Vapor Compression Distillation Flight Experiment (VCD-E) was a flight experiment aboard the Space Shuttle Columbia during the STS-107 mission. The VCD-FE was a full-scale developmental version of the Space Station Urine Processor Assembly (UPA) and was designed to test some of the potential micro-gravity issues with the design. This paper summarizes the experiment results.

A debugger-interpreter with setup facilities for assembly programs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dolinskii, I.S.; Zisel`man, I.M.; Belotskii, S.L.

1995-11-01

In this paper a software program allowing one to introduce and debug the descriptions of the von Nuemann architecture processors and their assemblers, efficiently debug assembly programs, and investigate the instruction sets of the described processors is considered. For a description of the processor sematics and assembler syntax, a metassembly language is suggested.

Post-Flight Microbial Analysis of Samples from the International Space Station Water Recovery System and Oxygen Generation System

NASA Technical Reports Server (NTRS)

Birmele, Michele N.

2011-01-01

The Regenerative, Environmental Control and Life Support System (ECLSS) on the International Space Station (ISS) includes the the Water Recovery System (WRS) and the Oxygen Generation System (OGS). The WRS consists of a Urine Processor Assembly (UPA) and Water Processor Assembly (WPA). This report describes microbial characterization of wastewater and surface samples collected from the WRS and OGS subsystems, returned to KSC, JSC, and MSFC on consecutive shuttle flights (STS-129 and STS-130) in 2009-10. STS-129 returned two filters that contained fluid samples from the WPA Waste Tank Orbital Recovery Unit (ORU), one from the waste tank and the other from the ISS humidity condensate. Direct count by microscopic enumeration revealed 8.38 x 104 cells per mL in the humidity condensate sample, but none of those cells were recoverable on solid agar media. In contrast, 3.32 x lOs cells per mL were measured from a surface swab of the WRS waste tank, including viable bacteria and fungi recovered after S12 days of incubation on solid agar media. Based on rDNA sequencing and phenotypic characterization, a fungus recovered from the filter was determined to be Lecythophora mutabilis. The bacterial isolate was identified by rDNA sequence data to be Methylobacterium radiotolerans. Additional UPA subsystem samples were returned on STS-130 for analysis. Both liquid and solid samples were collected from the Russian urine container (EDV), Distillation Assembly (DA) and Recycle Filter Tank Assembly (RFTA) for post-flight analysis. The bacterium Pseudomonas aeruginosa and fungus Chaetomium brasiliense were isolated from the EDV samples. No viable bacteria or fungi were recovered from RFTA brine samples (N= 6), but multiple samples (N = 11) from the DA and RFTA were found to contain fungal and bacterial cells. Many recovered cells have been identified to genus by rDNA sequencing and carbon source utilization profiling (BiOLOG Gen III). The presence of viable bacteria and fungi from WRS and OGS subsystems demonstrates the need for continued monitoring of ECLSS during future ISS operations and investigation of advanced antimicrobial controls.

A data base processor semantics specification package

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

Unaligned instruction relocation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unalignedmore » ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.« less

Unaligned instruction relocation

DOEpatents

Bertolli, Carlo; O'Brien, John K.; Sallenave, Olivier H.; Sura, Zehra N.

2018-01-23

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.

Environmental Control and Life Support Integration Strategy for 6-Crew Operations Stephanie Duchesne

NASA Technical Reports Server (NTRS)

Duchesne, Stephanie M.

2009-01-01

The International Space Station (ISS) crew compliment has increased in size from 3 to 6 crew members . In order to support this increase in crew on ISS, the United States on-orbit Segment (USOS) has been outfitted with a suite of regenerative Environmental Control and Life Support (ECLS) hardware including an Oxygen Generation System(OGS), Waste and Hygiene Compartment (WHC), and a Water Recovery System (WRS). The WRS includes the Urine Processor Assembly (UPA) and the Water Processor Assembly (WPA). With this additional life support hardware, the ISS has achieved full redundancy in its on-orbit life support system between the USOS and Russian Segment (RS). The additional redundancy created by the Regenerative ECLS hardware creates the opportunity for independent support capabilities between segments, and for the first time since the start of ISS, the necessity to revise Life Support strategy agreements. Independent operating strategies coupled with the loss of the Space Shuttle supply and return capabilities in 2010 offer new and unique challenges. This paper will discuss the evolution of the ISS Life Support hardware strategy in support of 6-Crew on ISS, as well as the continued work that is necessary to ensure the support of crew and ISS Program objectives through the life of station.

Environmental Control and Life Support Integration Strategy for 6-Crew Operations

NASA Technical Reports Server (NTRS)

Duchesne, Stephanie M.; Tressler, Chad H.

2010-01-01

The International Space Station (ISS) crew complement has increased in size from 3 to 6 crew members. In order to support this increase in crew on ISS, the United States on-orbit Segment (USOS) has been outfitted with a suite of regenerative Environmental Control and Life Support (ECLS) hardware including an Oxygen Generation System (OGS), Waste and Hygiene Compartment (WHC), and a Water Recovery System (WRS). The WRS includes the Urine Processor Assembly (UPA) and the Water Processor Assembly (WPA). With this additional life support hardware, the ISS has achieved full redundancy in its on-orbit life support system between the t OS and Russian Segment (RS). The additional redundancy created by the Regenerative ECLS hardware creates the opportunity for independent support capabilities between segments, and for the first time since the start of ISS, the necessity to revise Life Support strategy agreements. Independent operating strategies coupled with the loss of the Space Shuttle supply and return capabilities in 2010 offer new and unique challenges. This paper will discuss the evolution of the ISS Life Support hardware strategy in support of 6-Crew on ISS, as well as the continued work that is necessary to ensure the support of crew and ISS Program objectives through the life of station

Dual Fan Separator within the Universal Waste Management System

NASA Technical Reports Server (NTRS)

Stapleton, Tom; Converse, Dave; Broyan, James Lee, Jr.

2014-01-01

Since NASA's new spacecraft in development for both LEO and Deep Space capability have considerable crew volume reduction in comparison to the Space Shuttle, it is clear that NASA requires a smaller and less expensive commode. The UTAS Universal Waste Management System (UWMS) was designed to address these new constraints, resulting in an 80% volume reduction in the cabin while enhancing performance. Whereas all of the current space commodes use air flow to capture both urine and feces and separate air from the captured air/urine mixture, the UWMS commode and urine fans and the urine separator were combined into a single unit. This unit enables use of a single motor and motor controller, which provides considerable packaging and weight efficiency. In some of the intended platform applications for the UWMS, the urine is pumped to a water reclamation system. The ISS Urine Processor Assembly (UPA) system requires delivered urine to include less than 0.25% air inclusion. Air inclusion in centrifugal urine separators is greatly dependent on its rotational speed. To satisfy this requirement, a gear reducer was included, allowing the fans to rotate at a much higher speed than the separator. This new design, the Dual Fan Separator (DFS) has been designed, prototyped and tested. This paper will outline the studies and analysis performed to develop the design configuration for testing. The studies included a configuration trade study, dynamic stability analysis of the rotating bodies and a performance analysis of included labyrinth seals. NASA is considereing a program to fly the UWMS aboard the ISS as a flight experiment. The goal of the design activity is to elevate the Technical Readiness Level (TRL) of the Dual Fan Separator and determine if the concept is ready to be included in flight experiment deliverable.

Integrated Advanced Microwave Sounding Unit-A(AMSU-A). Engineering Test Report: METSAT A1 Signal Processor, (P/N 1331670-2, S /N F05)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the AI METSAT Signal Processor Assembly P/N 1331670-2, S/N F05. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N 1331670-2, S/N F03)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F03. This assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N: 1331670-2, S/N: F04)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report: METSAT A2 Signal Processor (P/N 1331120-2, S/N F03) S/N 107

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F03. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report, METSAT A2 Signal Processor (P/N 1331120-2, S/N F04) S/N 108

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

International Space Station USOS Waste and Hygiene Compartment Development

NASA Technical Reports Server (NTRS)

Link, Dwight E., Jr.; Broyan, James Lee, Jr.; Gelmis, Karen; Philistine, Cynthia; Balistreri, Steven

2007-01-01

The International Space Station (ISS) currently provides human waste collection and hygiene facilities in the Russian Segment Service Module (SM) which supports a three person crew. Additional hardware is planned for the United States Operational Segment (USOS) to support expansion of the crew to six person capability. The additional hardware will be integrated in an ISS standard equipment rack structure that was planned to be installed in the Node 3 element; however, the ISS Program Office recently directed implementation of the rack, or Waste and Hygiene Compartment (WHC), into the U.S. Laboratory element to provide early operational capability. In this configuration, preserved urine from the WHC waste collection system can be processed by the Urine Processor Assembly (UPA) in either the U.S. Lab or Node 3 to recover water for crew consumption or oxygen production. The human waste collection hardware is derived from the Service Module system and is provided by RSC-Energia. This paper describes the concepts, design, and integration of the WHC waste collection hardware into the USOS including integration with U.S. Lab and Node 3 systems.

System and method for controlling a combustor assembly

DOEpatents

York, William David; Ziminsky, Willy Steve; Johnson, Thomas Edward; Stevenson, Christian Xavier

2013-03-05

A system and method for controlling a combustor assembly are disclosed. The system includes a combustor assembly. The combustor assembly includes a combustor and a fuel nozzle assembly. The combustor includes a casing. The fuel nozzle assembly is positioned at least partially within the casing and includes a fuel nozzle. The fuel nozzle assembly further defines a head end. The system further includes a viewing device configured for capturing an image of at least a portion of the head end, and a processor communicatively coupled to the viewing device, the processor configured to compare the image to a standard image for the head end.

Performance Evaluation of the ISS Water Processor Multifiltration Beds

NASA Technical Reports Server (NTRS)

Bowman, Elizabeth M.; Carter, Layne; Wilson, Mark; Cole, Harold; Orozco, Nicole; Snowdon, Doug

2012-01-01

The ISS Water Processor Assembly (WPA) produces potable water from a waste stream containing humidity condensate and urine distillate. The primary treatment process is achieved in the Multifiltration Bed, which includes adsorbent media and ion exchange resin for the removal of dissolved organic and inorganic contaminants. The first Multifiltration Bed was replaced on ISS in July 2010 after initial indication of inorganic breakthrough. This bed was returned to ground in July 2011 for an engineering investigation. The water resident in the bed was analyzed for various parameters to evaluate adsorbent loading, performance of the ion exchange resin, microbial activity, and generation of leachates from the ion exchange resin. Portions of the adsorbent media and ion exchange resin were sampled and subsequently desorbed to identify the primary contaminants removed at various points in the bed. In addition, an unused Multifiltration Bed was evaluated after two years in storage to assess the generation of leachates during storage. This assessment was performed to evaluate the possibility that these leachates are impacting performance of the Catalytic Reactor located downstream of the Multifiltration Bed. The results of these investigations and implications to the operation of the WPA on ISS are documented in this paper.

Evaluation of Brine Processing Technologies for Spacecraft Wastewater

NASA Technical Reports Server (NTRS)

Shaw, Hali L.; Flynn, Michael; Wisniewski, Richard; Lee, Jeffery; Jones, Harry; Delzeit, Lance; Shull, Sarah; Sargusingh, Miriam; Beeler, David; Howard, Jeanie;

Contaminant Permeation in the Ionomer-Membrane Water Processor (IWP) System

NASA Technical Reports Server (NTRS)

Kelsey, Laura K.; Finger, Barry W.; Pasadilla, Patrick; Perry, Jay

2016-01-01

The Ionomer-membrane Water Processor (IWP) is a patented membrane-distillation based urine brine water recovery system. The unique properties of the IWP membrane pair limit contaminant permeation from the brine to the recovered water and purge gas. A paper study was conducted to predict volatile trace contaminant permeation in the IWP system. Testing of a large-scale IWP Engineering Development Unit (EDU) with urine brine pretreated with the International Space Station (ISS) pretreatment formulation was then conducted to collect air and water samples for quality analysis. Distillate water quality and purge air GC-MS results are presented and compared to predictions, along with implications for the IWP brine processing system.

A parallel algorithm for generation and assembly of finite element stiffness and mass matrices

NASA Technical Reports Server (NTRS)

Storaasli, O. O.; Carmona, E. A.; Nguyen, D. T.; Baddourah, M. A.

1991-01-01

A new algorithm is proposed for parallel generation and assembly of the finite element stiffness and mass matrices. The proposed assembly algorithm is based on a node-by-node approach rather than the more conventional element-by-element approach. The new algorithm's generality and computation speed-up when using multiple processors are demonstrated for several practical applications on multi-processor Cray Y-MP and Cray 2 supercomputers.

Development of Reliable Life Support Systems

NASA Technical Reports Server (NTRS)

Carter, Layne

2017-01-01

The life support systems on the International Space Station (ISS) are the culmination of an extensive effort encompassing development, design, and test to provide the highest possible confidence in their operation on ISS. Many years of development testing are initially performed to identify the optimum technology and the optimum operational approach. The success of this development program depends on the accuracy of the system interfaces. The critical interfaces include the specific operational environment, the composition of the waste stream to be processed and the quality of the product. Once the development program is complete, a detailed system schematic is built based on the specific design requirements, followed by component procurement, assembly, and acceptance testing. A successful acceptance test again depends on accurately simulating the anticipated environment on ISS. The ISS Water Recovery System (WRS) provides an excellent example of where this process worked, as well as lessons learned that can be applied to the success of future missions. More importantly, ISS has provided a test bed to identify these design issues. Mechanical design issues have included an unreliable harmonic drive train in the Urine Processor's fluids pump, and seals in the Water Processor's Catalytic Reactor with insufficient life at the operational temperature. Systems issues have included elevated calcium in crew urine (due to microgravity effect) that resulted in precipitation at the desired water recovery rate, and the presence of an organosilicon compound (dimethylsilanediol) in the condensate that is not well removed by the water treatment process. Modifications to the WRS to address these issues are either complete (and now being evaluated on ISS) or are currently in work to insure the WRS has the required reliability before embarking on a mission to Mars.

Environmental Control and Life Support Integration Strategy for 6-Crew Operations

NASA Technical Reports Server (NTRS)

2009-01-01

The International Space Station (ISS) crew compliment will be increasing in size from 3 to 6 crew members in the summer of 2009. In order to support this increase in crew on ISS, the United States on-orbit Segment (USOS) has been outfitted with a suite of regenerative Environmental Control and Life Support (ECLS) hardware including an Oxygen Generation System(OGS), Waste and Hygiene Compartment (WHC), and a Water Recovery System (WRS). The WRS includes the Urine Processor Assembly (UPA) and the Water Processor Assembly (WPA). A critical step in advancing to a 6Crew support capability on ISS is a full checkedout and verification of the Regenerative ECLS hardware. With a successful checkout, the ISS will achieve full redundancy in its onorbit life support system between the USOS and Russian Segment (RS). The additional redundancy created by the Regenerative ECLS hardware creates the opportunity for independent support capabilities between segments, and for the first time since the start of ISS, the necessity to revise Life Support strategy agreements. Independent operating strategies coupled with the loss of the Space Shuttle supply and return capabilities in 2010 offers additional challenges. These challenges create the need for a higher level of onorbit consumables reserve to ensure crewmember life support during a system failure. This paper will discuss the evolution of the ISS Life Support hardware strategy in support of 6Crew on ISS, as well as the continued work which will be necessary to ensure the support of crew and ISS Program objectives through the life of station.

Dual Fan Separator within the Universal Waste Management System

NASA Technical Reports Server (NTRS)

Stapleton, Tom; Converse, Dave; Broyan, James Lee, Jr.

2014-01-01

Since NASA's new spacecraft in development for both LEO and Deep Space capability have considerable crew volume reduction in comparison to the Space Shuttle, the need became apparent for a smaller commode. In response the Universal Waste Management System (UWMS) was designed, resulting in an 80% volume reduction from the last US commode, while enhancing performance. The ISS WMS and previous shuttle commodes have a fan supplying air flow to capture feces and a separator to capture urine and separate air from the captured air/urine mixture. The UWMS combined both rotating equipment components into a single unit, referred to at the Dual Fan Separator (DFS). The combination of these components resulted in considerable packaging efficiency and weight reduction, removing inter-component plumbing, individual mounting configurations and required only a single motor and motor controller, in some of the intended UWMS platform applications the urine is pumped to the ISS Urine Processor Assembly (UPA) system. It requires the DFS to include less than 2.00% air inclusion, by volume, in the delivered urine. The rotational speed needs to be kept as low as possible in centrifugal urine separators to reduce air inclusion in the pumped fluid, while fans depend on rotational speed to develop delivered head. To satisfy these conflicting requirements, a gear reducer was included, allowing the fans to rotate at a much higher speed than the separator. This paper outlines the studies and analysis performed to develop the DFS configuration. The studies included a configuration trade study, dynamic stability analysis of the rotating bodies and a performance analysis of included labyrinth seals. NASA is considering a program to fly the UWMS aboard the ISS as a flight experiment. The goal of this activity is to advance the Technical Readiness Level (TRL) of the DFS and determine if the concept is ready to be included as part of the flight experiment deliverable.

The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

NASA Technical Reports Server (NTRS)

Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

2007-01-01

Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

Carbon Dioxide Reduction Post-Processing Sub-System Development

NASA Technical Reports Server (NTRS)

Abney, Morgan B.; Miller, Lee A.; Greenwood, Zachary; Barton, Katherine

2012-01-01

The state-of-the-art Carbon Dioxide (CO2) Reduction Assembly (CRA) on the International Space Station (ISS) facilitates the recovery of oxygen from metabolic CO2. The CRA utilizes the Sabatier process to produce water with methane as a byproduct. The methane is currently vented overboard as a waste product. Because the CRA relies on hydrogen for oxygen recovery, the loss of methane ultimately results in a loss of oxygen. For missions beyond low earth orbit, it will prove essential to maximize oxygen recovery. For this purpose, NASA is exploring an integrated post-processor system to recover hydrogen from CRA methane. The post-processor, called a Plasma Pyrolysis Assembly (PPA) partially pyrolyzes methane to recover hydrogen with acetylene as a byproduct. In-flight operation of post-processor will require a Methane Purification Assembly (MePA) and an Acetylene Separation Assembly (ASepA). Recent efforts have focused on the design, fabrication, and testing of these components. The results and conclusions of these efforts will be discussed as well as future plans.

WATERLOPP V2/64: A highly parallel machine for numerical computation

NASA Astrophysics Data System (ADS)

Ostlund, Neil S.

1985-07-01

Current technological trends suggest that the high performance scientific machines of the future are very likely to consist of a large number (greater than 1024) of processors connected and communicating with each other in some as yet undetermined manner. Such an assembly of processors should behave as a single machine in obtaining numerical solutions to scientific problems. However, the appropriate way of organizing both the hardware and software of such an assembly of processors is an unsolved and active area of research. It is particularly important to minimize the organizational overhead of interprocessor comunication, global synchronization, and contention for shared resources if the performance of a large number ( n) of processors is to be anything like the desirable n times the performance of a single processor. In many situations, adding a processor actually decreases the performance of the overall system since the extra organizational overhead is larger than the extra processing power added. The systolic loop architecture is a new multiple processor architecture which attemps at a solution to the problem of how to organize a large number of asynchronous processors into an effective computational system while minimizing the organizational overhead. This paper gives a brief overview of the basic systolic loop architecture, systolic loop algorithms for numerical computation, and a 64-processor implementation of the architecture, WATERLOOP V2/64, that is being used as a testbed for exploring the hardware, software, and algorithmic aspects of the architecture.

Improved Dynamic Modeling of the Cascade Distillation Subsystem and Analysis of Factors Affecting Its Performance

NASA Technical Reports Server (NTRS)

Perry, Bruce A.; Anderson, Molly S.

2015-01-01

The Cascade Distillation Subsystem (CDS) is a rotary multistage distiller being developed to serve as the primary processor for wastewater recovery during long-duration space missions. The CDS could be integrated with a system similar to the International Space Station Water Processor Assembly to form a complete water recovery system for future missions. A preliminary chemical process simulation was previously developed using Aspen Custom Modeler® (ACM), but it could not simulate thermal startup and lacked detailed analysis of several key internal processes, including heat transfer between stages. This paper describes modifications to the ACM simulation of the CDS that improve its capabilities and the accuracy of its predictions. Notably, the modified version can be used to model thermal startup and predicts the total energy consumption of the CDS. The simulation has been validated for both NaC1 solution and pretreated urine feeds and no longer requires retuning when operating parameters change. The simulation was also used to predict how internal processes and operating conditions of the CDS affect its performance. In particular, it is shown that the coefficient of performance of the thermoelectric heat pump used to provide heating and cooling for the CDS is the largest factor in determining CDS efficiency. Intrastage heat transfer affects CDS performance indirectly through effects on the coefficient of performance.

Methane Post-Processor Development to Increase Oxygen Recovery beyond State-of-the-Art Carbon Dioxide Reduction Technology

NASA Technical Reports Server (NTRS)

Abney, Morgan; Miller, Lee; Greenwood, Zach; Iannantuono, Michelle; Jones, Kenny

2013-01-01

State-of-the-art life support carbon dioxide (CO2) reduction technology, based on the Sabatier reaction, is theoretically capable of 50% recovery of oxygen from metabolic CO2. This recovery is constrained by the limited availability of reactant hydrogen. Post-processing of the methane byproduct from the Sabatier reactor results in hydrogen recycle and a subsequent increase in oxygen recovery. For this purpose, a Methane Post-Processor Assembly containing three sub-systems has been developed and tested. The assembly includes a Methane Purification Assembly (MePA) to remove residual CO2 and water vapor from the Sabatier product stream, a Plasma Pyrolysis Assembly (PPA) to partially pyrolyze methane into hydrogen and acetylene, and an Acetylene Separation Assembly (ASepA) to purify the hydrogen product for recycle. The results of partially integrated testing of the sub-systems are reported.

Methane Post-Processor Development to Increase Oxygen Recovery beyond State-of-the-Art Carbon Dioxide Reduction Technology

NASA Technical Reports Server (NTRS)

Abney, Morgan B.; Greenwood, Zachary; Miller, Lee A.; Alvarez, Giraldo; Iannantuono, Michelle; Jones, Kenny

2013-01-01

State-of-the-art life support carbon dioxide (CO2) reduction technology, based on the Sabatier reaction, is theoretically capable of 50% recovery of oxygen from metabolic CO2. This recovery is constrained by the limited availability of reactant hydrogen. Post-processing of the methane byproduct from the Sabatier reactor results in hydrogen recycle and a subsequent increase in oxygen recovery. For this purpose, a Methane Post-Processor Assembly containing three sub-systems has been developed and tested. The assembly includes a Methane Purification Assembly (MePA) to remove residual CO2 and water vapor from the Sabatier product stream, a Plasma Pyrolysis Assembly (PPA) to partially pyrolyze methane into hydrogen and acetylene, and an Acetylene Separation Assembly (ASepA) to purify the hydrogen product for recycle. The results of partially integrated testing of the sub-systems are reported

Data processing with microcode designed with source coding

DOEpatents

McCoy, James A; Morrison, Steven E

2013-05-07

Programming for a data processor to execute a data processing application is provided using microcode source code. The microcode source code is assembled to produce microcode that includes digital microcode instructions with which to signal the data processor to execute the data processing application.

Urine Pretreat Injection System

NASA Technical Reports Server (NTRS)

1995-01-01

A new method of introducing the OXONE (Registered Trademark) Monopersulfate Compound for urine pretreat into a two-phase urine/air flow stream has been successfully tested and evaluated. The feasibility of this innovative method has been established for purposes of providing a simple, convenient, and safe method of handling a chemical pretreat required for urine processing in a microgravity space environment. Also, the Oxone portion of the urine pretreat has demonstrated the following advantages during real time collection of 750 pounds of urine in a Space Station design two-phase urine Fan/Separator: Eliminated urine precipitate buildup on internal hardware and plumbing; Minimized odor from collected urine; and Virtually eliminated airborne bacteria. The urine pretreat, as presently defined for the Space Station program for proper downstream processing of urine, is a two-part chemical treatment of 5.0 grams of Oxone and 2.3 ml of H2SO4 per liter of urine. This study program and test demonstrated only the addition of the proper ratio of Oxone into the urine collection system upstream of the Fan/Separator. This program was divided into the following three major tasks: (1) A trade study, to define and recommend the type of Oxone injection method to pursue further; (2) The design and fabrication of the selected method; and (3) A test program using high fidelity hardware and fresh urine to demonstrate the method feasibility. The trade study was conducted which included defining several methods for injecting Oxone in different forms into a urine system. Oxone was considered in a liquid, solid, paste and powered form. The trade study and the resulting recommendation were presented at a trade study review held at Hamilton Standard on 24-25 October 94. An agreement was reached at the meeting to continue the solid tablet in a bag concept which included a series of tablets suspended in the urine/air flow stream. These Oxone tablets would slowly dissolve at a controlled rate providing the proper concentration in the collected urine. To implement the solid tablet in a bag approach, a design concept was completed with prototype drawings of the complete urine pretreat prefilter assembly. A successful fabrication technique was developed for retaining the Oxone tablets in a fabric casing attached to the end of the existing Space Station Waste Collection System urine prefilter assembly. The final pretreat prefilter configuration held sufficient Oxone in a tablet form to allow normal scheduled daily (or twice daily) change out of the urine filter depending on the use rate of the Space Station urine collection system. The actual tests to prove the concept were conducted using the Urine Fan/Separator assembly that was originally used in the STS-52 Design Test Objective (DTO) urinal assembly. Other related tests were conducted to demonstrate the actual minimum ratio of Oxone to urine that will control microbial growth.

Gyro and Accelerometer Based Navigation System for a Mobile Autonomous Robot.

DTIC Science & Technology

1985-12-02

special thanks goes to our thesis advisor Dr. Matthew Kabrisky for having the confidence to turn us loose on this project. Additionally, we would...Wordmaster Word Processor 1 Wordstar Word Processor 1 Virtual Devices Robo A 6802 Cross Assembler 1 Modem 720 Communication Program 1 CP/M Operating

Virtualization for Cost-Effective Teaching of Assembly Language Programming

ERIC Educational Resources Information Center

Cadenas, José O.; Sherratt, R. Simon; Howlett, Des; Guy, Chris G.; Lundqvist, Karsten O.

2015-01-01

This paper describes a virtual system that emulates an ARM-based processor machine, created to replace a traditional hardware-based system for teaching assembly language. The virtual system proposed here integrates, in a single environment, all the development tools necessary to deliver introductory or advanced courses on modern assembly language…

Electromagnetic compatibility test report for the tethered satellite data acquisition and control assembly

NASA Astrophysics Data System (ADS)

Hoskins, Douglas; Snead, Robert

1988-05-01

This report details the results of an electromagnetic compatibility test on the SCI Systems Data Acquisition and Control Assembly (DACA). This assembly is an electronic processor which controls the central communication link from the Tethered Satellite System (TSS) to the Space Transportation System Orbiter Space Shuttle.

Advanced On-Board Processor (AOP). [for future spacecraft applications

NASA Technical Reports Server (NTRS)

1973-01-01

Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.

Updated Performance Evaluation of the ISS Water Processor Multifiltration Beds

NASA Technical Reports Server (NTRS)

Bowman, Elizabeth M.; Carter, Layne; Carpenter, Joyce; Orozco, Nicole; Weir, Natalee; Wilson, Mark

2014-01-01

The ISS Water Processor Assembly (WPA) produces potable water from a waste stream containing humidity condensate and urine distillate. The primary treatment process is achieved in the Multifiltration Beds, which include adsorbent media and ion exchange resin for the removal of dissolved organic and inorganic contaminants. Two Multifiltration Beds (MF Beds) were replaced on ISS in July 2010 after initial indication of inorganic breakthrough of the first bed and an increasing Total Organic Carbon (TOC) trend in the product water. The first bed was sampled and analyzed Sept 2011 through March 2012. The second MF Bed was sampled and analyzed June 2012 through August 2012. The water resident in the both beds was analyzed for various parameters to evaluate adsorbent loading, performance of the ion exchange resin, microbial activity, and generation of leachates from the ion exchange resin. Portions of the adsorbent media and ion exchange resin were sampled and subsequently desorbed to identify the primary contaminants removed at various points in the bed in addition to microbial analysis. Analysis of the second bed will be compared to results from the first bed to provide a comprehensive overview of how the Multifiltration Beds function on orbit. New data from the second bed supplements the analysis of the first bed (previously reported) and gives a more complete picture of breakthrough compounds, resin breakdown products, microbial activity, and difficult to remove compounds. The results of these investigations and implications to the operation of the WPA on ISS are documented in this paper.

Improved Dynamic Modeling of the Cascade Distillation Subsystem and Integration with Models of Other Water Recovery Subsystems

NASA Technical Reports Server (NTRS)

Perry, Bruce; Anderson, Molly

2015-01-01

The Cascade Distillation Subsystem (CDS) is a rotary multistage distiller being developed to serve as the primary processor for wastewater recovery during long-duration space missions. The CDS could be integrated with a system similar to the International Space Station (ISS) Water Processor Assembly (WPA) to form a complete Water Recovery System (WRS) for future missions. Independent chemical process simulations with varying levels of detail have previously been developed using Aspen Custom Modeler (ACM) to aid in the analysis of the CDS and several WPA components. The existing CDS simulation could not model behavior during thermal startup and lacked detailed analysis of several key internal processes, including heat transfer between stages. The first part of this paper describes modifications to the ACM model of the CDS that improve its capabilities and the accuracy of its predictions. Notably, the modified version of the model can accurately predict behavior during thermal startup for both NaCl solution and pretreated urine feeds. The model is used to predict how changing operating parameters and design features of the CDS affects its performance, and conclusions from these predictions are discussed. The second part of this paper describes the integration of the modified CDS model and the existing WPA component models into a single WRS model. The integrated model is used to demonstrate the effects that changes to one component can have on the dynamic behavior of the system as a whole.

Integral Fast Reactor fuel pin processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levinskas, D.

1993-01-01

This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves.

Integral Fast Reactor fuel pin processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levinskas, D.

1993-03-01

This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves.

Waste water processing technology for Space Station Freedom - Comparative test data analysis

NASA Technical Reports Server (NTRS)

Miernik, Janie H.; Shah, Burt H.; Mcgriff, Cindy F.

1991-01-01

Comparative tests were conducted to choose the optimum technology for waste water processing on SSF. A thermoelectric integrated membrane evaporation (TIMES) subsystem and a vapor compression distillation subsystem (VCD) were built and tested to compare urine processing capability. Water quality, performance, and specific energy were compared for conceptual designs intended to function as part of the water recovery and management system of SSF. The VCD is considered the most mature and efficient technology and was selected to replace the TIMES as the baseline urine processor for SSF.

a Real-Time Computer Music Synthesis System

NASA Astrophysics Data System (ADS)

Lent, Keith Henry

A real time sound synthesis system has been developed at the Computer Music Center of The University of Texas at Austin. This system consists of several stand alone processors that were constructed jointly with White Instruments in Austin. These processors can be programmed as general purpose computers, but are provided with a number of specialized interfaces including: MIDI, 8 bit parallel, high speed serial, 2 channels analog input (18 bit A/Ds, 48kHz sample rate), and 4 channels analog output (18 bit D/As). In addition, a basic music synthesis language (Music56000) has been written in assembly code. On top of this, a symbolic compiler (PatchWork) has been developed to enable algorithms which run in these processors to be created graphically. And finally, a number of efficient time domain numerical models have been developed to enable the construction, simulation, control, and synthesis of many musical acoustics systems in real time on these processors. Specifically, assembly language models for cylindrical and conical horn sections, dissipative losses, tone holes, bells, and a number of linear and nonlinear boundary conditions have been developed.

A VME-based software trigger system using UNIX processors

NASA Astrophysics Data System (ADS)

Atmur, Robert; Connor, David F.; Molzon, William

1997-02-01

We have constructed a distributed computing platform with eight processors to assemble and filter data from digitization crates. The filtered data were transported to a tape-writing UNIX computer via ethernet. Each processor ran a UNIX operating system and was installed in its own VME crate. Each VME crate contained dual-port memories which interfaced with the digitizers. Using standard hardware and software (VME and UNIX) allows us to select from a wide variety of non-proprietary products and makes upgrades simpler, if they are necessary.

System support software for the Space Ultrareliable Modular Computer (SUMC)

NASA Technical Reports Server (NTRS)

Hill, T. E.; Hintze, G. C.; Hodges, B. C.; Austin, F. A.; Buckles, B. P.; Curran, R. T.; Lackey, J. D.; Payne, R. E.

1974-01-01

The highly transportable programming system designed and implemented to support the development of software for the Space Ultrareliable Modular Computer (SUMC) is described. The SUMC system support software consists of program modules called processors. The initial set of processors consists of the supervisor, the general purpose assembler for SUMC instruction and microcode input, linkage editors, an instruction level simulator, a microcode grid print processor, and user oriented utility programs. A FORTRAN 4 compiler is undergoing development. The design facilitates the addition of new processors with a minimum effort and provides the user quasi host independence on the ground based operational software development computer. Additional capability is provided to accommodate variations in the SUMC architecture without consequent major modifications in the initial processors.

Electrical Prototype Power Processor for the 30-cm Mercury electric propulsion engine

NASA Technical Reports Server (NTRS)

Biess, J. J.; Frye, R. J.

1978-01-01

An Electrical Prototpye Power Processor has been designed to the latest electrical and performance requirements for a flight-type 30-cm ion engine and includes all the necessary power, command, telemetry and control interfaces for a typical electric propulsion subsystem. The power processor was configured into seven separate mechanical modules that would allow subassembly fabrication, test and integration into a complete power processor unit assembly. The conceptual mechanical packaging of the electrical prototype power processor unit demonstrated the relative location of power, high voltage and control electronic components to minimize electrical interactions and to provide adequate thermal control in a vacuum environment. Thermal control was accomplished with a heat pipe simulator attached to the base of the modules.

Evaluating local indirect addressing in SIMD proc essors

NASA Technical Reports Server (NTRS)

Middleton, David; Tomboulian, Sherryl

1989-01-01

In the design of parallel computers, there exists a tradeoff between the number and power of individual processors. The single instruction stream, multiple data stream (SIMD) model of parallel computers lies at one extreme of the resulting spectrum. The available hardware resources are devoted to creating the largest possible number of processors, and consequently each individual processor must use the fewest possible resources. Disagreement exists as to whether SIMD processors should be able to generate addresses individually into their local data memory, or all processors should access the same address. The tradeoff is examined between the increased capability and the reduced number of processors that occurs in this single instruction stream, multiple, locally addressed, data (SIMLAD) model. Factors are assembled that affect this design choice, and the SIMLAD model is compared with the bare SIMD and the MIMD models.

Vapor Compression Distillation Flight Experiment

NASA Technical Reports Server (NTRS)

Hutchens, Cindy F.

2002-01-01

One of the major requirements associated with operating the International Space Station is the transportation -- space shuttle and Russian Progress spacecraft launches - necessary to re-supply station crews with food and water. The Vapor Compression Distillation (VCD) Flight Experiment, managed by NASA's Marshall Space Flight Center in Huntsville, Ala., is a full-scale demonstration of technology being developed to recycle crewmember urine and wastewater aboard the International Space Station and thereby reduce the amount of water that must be re-supplied. Based on results of the VCD Flight Experiment, an operational urine processor will be installed in Node 3 of the space station in 2005.

ISS Potable Water Sampling and Chemical Analysis Results for 2016

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Wallace William T.; Alverson, James T.; Benoit, Mickie J.; Gillispie, Robert L.; Hunter, David; Kuo, Mike; Rutz, Jeffrey A.; Hudson, Edgar K.;

ISS Potable Water Sampling and Chemical Analysis Results for 2016

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Wallace, William T.; Alverson, James T.; Benoit, Mickie J.; Gillispie, Robert L.; Hunter, David; Kuo, Mike; Rutz, Jeffrey A.; Hudson, Edgar K.;

Results for the Brine Evaporation Bag (BEB) Brine Processing Test

NASA Technical Reports Server (NTRS)

Delzeit, Lance; Flynn, Michael; Fisher, John; Shaw, Hali; Kawashima, Brian; Beeler, David; Howard, Kevin

2015-01-01

The recent Brine Processing Test compared the NASA Forward Osmosis Brine Dewatering (FOBD), Paragon Ionomer Water Processor (IWP), UMPQUA Ultrasonic Brine Dewatering System (UBDS), and the NASA Brine Evaporation Bag (BEB). This paper reports the results of the BEB. The BEB was operated at 70 deg C and a base pressure of 12 torr. The BEB was operated in a batch mode, and processed 0.4L of brine per batch. Two different brine feeds were tested, a chromic acid-urine brine and a chromic acid-urine-hygiene mix brine. The chromic acid-urine brine, known as the ISS Alternate Pretreatment Brine, had an average processing rate of 95 mL/hr with a specific power of 5kWhr/L. The complete results of these tests will be reported within this paper.

Performance Qualification Test of the ISS Water Processor Assembly (WPA) Expendables

NASA Technical Reports Server (NTRS)

Carter, Layne; Tabb, David; Tatara, James D.; Mason, Richard K.

2005-01-01

The Water Processor Assembly (WPA) for use on the International Space Station (ISS) includes various technologies for the treatment of waste water. These technologies include filtration, ion exchange, adsorption, catalytic oxidation, and iodination. The WPA hardware implementing portions of these technologies, including the Particulate Filter, Multifiltration Bed, Ion Exchange Bed, and Microbial Check Valve, was recently qualified for chemical performance at the Marshall Space Flight Center. Waste water representing the quality of that produced on the ISS was generated by test subjects and processed by the WPA. Water quality analysis and instrumentation data was acquired throughout the test to monitor hardware performance. This paper documents operation of the test and the assessment of the hardware performance.

KSC-2009-1515

NASA Image and Video Library

2009-02-05

CAPE CANAVERAL, Fla. – A replacement distillation assembly for the International Space Station's new water recycling system is being checked out in the Space Station Processing Facility at NASA's Kennedy Space Center in Florida. The unit is part of the Urine Processing Assembly that removes impurities from urine in an early stage of the recycling process. It will be flown to the station aboard space shuttle Discovery on the STS-119 mission. Photo credit: NASA/Jack Pfaller

KSC-2009-1516

NASA Image and Video Library

2009-02-05

CAPE CANAVERAL, Fla. – A closeup of the replacement distillation assembly for the International Space Station's new water recycling system being checked out in the Space Station Processing Facility at NASA's Kennedy Space Center in Florida. The unit is part of the Urine Processing Assembly that removes impurities from urine in an early stage of the recycling process. It will be flown to the station aboard space shuttle Discovery on the STS-119 mission. Photo credit: NASA/Jack Pfaller

KSC-2009-1514

NASA Image and Video Library

2009-02-05

CAPE CANAVERAL, Fla. – A replacement distillation assembly for the International Space Station's new water recycling system is being checked out in the Space Station Processing Facility at NASA's Kennedy Space Center in Florida. The unit is part of the Urine Processing Assembly that removes impurities from urine in an early stage of the recycling process. It will be flown to the station aboard space shuttle Discovery on the STS-119 mission. Photo credit: NASA/Jack Pfaller

Development of Urine Receptacle Assembly for the Crew Exploration Vehicle

NASA Technical Reports Server (NTRS)

Cibuzar, Branelle Rae; Thomas, Evan; Peterson, Laurie; Goforth, Johanna

2008-01-01

The Urine Receptacle Assembly (URA) initially was developed for Apollo as a primary means of urine collection. The aluminum housing with stainless steel honeycomb insert provided all male crewmembers with a non-invasive means of micturating into a urine capturing device and then venting to space. The performance of the URA was a substantial improvement over previous devices but its performance was not well understood. The Crew Exploration Vehicle (CEV) program is exploring the URA as a contingency liquid waste management system for the vehicle. URA improvements are required to meet CEV requirements, including: consumables minimization, flow performance, acceptable hygiene standards, crew comfort, and female crewmember capability. This paper presents the results of a historical review of URA performance during the Apollo program, recent URA performance tests on the reduced gravity aircraft flight under varying flow conditions, and a proposed development plan for the URA to meet CEV needs.

A self-sustained, complete and miniaturized methanol fuel processor for proton exchange membrane fuel cell

NASA Astrophysics Data System (ADS)

Yang, Mei; Jiao, Fengjun; Li, Shulian; Li, Hengqiang; Chen, Guangwen

2015-08-01

A self-sustained, complete and miniaturized methanol fuel processor has been developed based on modular integration and microreactor technology. The fuel processor is comprised of one methanol oxidative reformer, one methanol combustor and one two-stage CO preferential oxidation unit. Microchannel heat exchanger is employed to recover heat from hot stream, miniaturize system size and thus achieve high energy utilization efficiency. By optimized thermal management and proper operation parameter control, the fuel processor can start up in 10 min at room temperature without external heating. A self-sustained state is achieved with H2 production rate of 0.99 Nm3 h-1 and extremely low CO content below 25 ppm. This amount of H2 is sufficient to supply a 1 kWe proton exchange membrane fuel cell. The corresponding thermal efficiency of whole processor is higher than 86%. The size and weight of the assembled reactors integrated with microchannel heat exchangers are 1.4 L and 5.3 kg, respectively, demonstrating a very compact construction of the fuel processor.

A microcomputer based frequency-domain processor for laser Doppler anemometry

NASA Technical Reports Server (NTRS)

Horne, W. Clifton; Adair, Desmond

1988-01-01

A prototype multi-channel laser Doppler anemometry (LDA) processor was assembled using a wideband transient recorder and a microcomputer with an array processor for fast Fourier transform (FFT) computations. The prototype instrument was used to acquire, process, and record signals from a three-component wind tunnel LDA system subject to various conditions of noise and flow turbulence. The recorded data was used to evaluate the effectiveness of burst acceptance criteria, processing algorithms, and selection of processing parameters such as record length. The recorded signals were also used to obtain comparative estimates of signal-to-noise ratio between time-domain and frequency-domain signal detection schemes. These comparisons show that the FFT processing scheme allows accurate processing of signals for which the signal-to-noise ratio is 10 to 15 dB less than is practical using counter processors.

Vapor Compression Distillation Urine Processor Lessons Learned from Development and Life Testing

NASA Technical Reports Server (NTRS)

Hutchens, Cindy F.; Long, David A.

1999-01-01

Vapor Compression Distillation (VCD) is the chosen technology for urine processing aboard the International Space Station (155). Development and life testing over the past several years have brought to the forefront problems and solutions for the VCD technology. Testing between 1992 and 1998 has been instrumental in developing estimates of hardware life and reliability. It has also helped improve the hardware design in ways that either correct existing problems or enhance the existing design of the hardware. The testing has increased the confidence in the VCD technology and reduced technical and programmatic risks. This paper summarizes the test results and changes that have been made to the VCD design.

Water Processor and Oxygen Generation Assembly

NASA Technical Reports Server (NTRS)

Bedard, John

1997-01-01

This report documents the results of the tasks which initiated efforts on design issues relating to the Water Processor (WP) and the Oxygen Generation Assembly (OGA) Flight Hardware for the International Space Station. This report fulfills the Statement of Work deliverables requirement for contract H-29387D. The following lists the tasks required by contract H-29387D: (1) HSSSI shall coordinate a detailed review of WP/OGA Flight Hardware program requirements with personnel from MSFC to identify requirements that can be eliminated without affecting the technical integrity of the WP/OGA Hardware; (2) HSSSI shall conduct the technical interchanges with personnel from MSFC to resolve design issues related to WP/OGA Flight Hardware; (3) HSSSI will initiate discussions with Zellwegger Analytics, Inc. to address design issues related to WP and PCWQM interfaces.

C-MOS array design techniques: SUMC multiprocessor system study

NASA Technical Reports Server (NTRS)

Clapp, W. A.; Helbig, W. A.; Merriam, A. S.

1972-01-01

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Integrated High-Speed Torque Control System for a Robotic Joint

NASA Technical Reports Server (NTRS)

Davis, Donald R. (Inventor); Radford, Nicolaus A. (Inventor); Permenter, Frank Noble (Inventor); Valvo, Michael C. (Inventor); Askew, R. Scott (Inventor)

2013-01-01

A control system for achieving high-speed torque for a joint of a robot includes a printed circuit board assembly (PCBA) having a collocated joint processor and high-speed communication bus. The PCBA may also include a power inverter module (PIM) and local sensor conditioning electronics (SCE) for processing sensor data from one or more motor position sensors. Torque control of a motor of the joint is provided via the PCBA as a high-speed torque loop. Each joint processor may be embedded within or collocated with the robotic joint being controlled. Collocation of the joint processor, PIM, and high-speed bus may increase noise immunity of the control system, and the localized processing of sensor data from the joint motor at the joint level may minimize bus cabling to and from each control node. The joint processor may include a field programmable gate array (FPGA).

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

Microbiological Characterization of the International Space Station Water Processor Assembly External Filter Assembly S/N 01

NASA Technical Reports Server (NTRS)

Weir, Natalee; Wilson, Mark; Yoets, Airan; Yoets, Airan; Molina, Thomas; Bruce, Rebekah; Sitler, Glenn; Carter, Layne

2012-01-01

The External Filter Assembly (EFA) S/N 01 is a mesh screen filter with a pore size of approximately 300 micron that was installed in the International Space Station (ISS) Water Processor Assembly (WPA) between the Waste Tank and the Mostly Liquid Separator (MLS) on February 11, 2010 to protect clearances in the MLS solenoid valve SV_1121_3. A removal & replacement of the EFA Filter was performed on March 22, 2011 in response to increasing pressure across the Waste Tank solenoid valve SV_1121_1 and the EFA Filter. The EFA Filter was returned on ULF6 and received in the Boeing Huntsville Laboratory on June 13, 2011. The filter was aseptically removed from the housing, and the residual water was collected for enumeration and identification of bacteria and fungi. Swab samples of the filter surface were also collected for microbiological enumeration and identification. Sample analyses were performed by Boeing Huntsville Laboratory and NASA Johnson Space Center Microbiology for comparison. Photographic documentation of the EFA filter was performed using a stereo microscope and environmental scanning electron microscope. This paper characterizes the amount and types of microorganisms on the filter surface and in the residual water from the filter housing following 1 year of utilization in the ISS WPA.

Environmental Control and Life Support System

NASA Technical Reports Server (NTRS)

Ray, Charles; Adams, Alan

1990-01-01

Viewgraphs on the Environmental Control and Life Support System (ECLSS) for the space station are presented. The ECLSS is divided into six subsystems: temperature and humidity control (THC), atmosphere control and supply (ACS), atmosphere revitalization (AR), fire detection and suppression (FDS), water recovery management (WRM), and waste management (WM). Topics covered include: ECLSS subsystem functions; ECLSS distributed system; ECLSS functional distribution; CO2 removal; CO2 reduction; oxygen generation; urine processor; and potable water recovery.

Ray Meta: scalable de novo metagenome assembly and profiling

PubMed Central

2012-01-01

Voluminous parallel sequencing datasets, especially metagenomic experiments, require distributed computing for de novo assembly and taxonomic profiling. Ray Meta is a massively distributed metagenome assembler that is coupled with Ray Communities, which profiles microbiomes based on uniquely-colored k-mers. It can accurately assemble and profile a three billion read metagenomic experiment representing 1,000 bacterial genomes of uneven proportions in 15 hours with 1,024 processor cores, using only 1.5 GB per core. The software will facilitate the processing of large and complex datasets, and will help in generating biological insights for specific environments. Ray Meta is open source and available at http://denovoassembler.sf.net. PMID:23259615

Ground Test of the Urine Processing Assembly for Accelerations and Transfer Functions

NASA Technical Reports Server (NTRS)

Houston, Janice; Almond, Deborah F. (Technical Monitor)

2001-01-01

This viewgraph presentation gives an overview of the ground test of the urine processing assembly for accelerations and transfer functions. Details are given on the test setup, test data, data analysis, analytical results, and microgravity assessment. The conclusions of the tests include the following: (1) the single input/multiple output method is useful if the data is acquired by tri-axial accelerometers and inputs can be considered uncorrelated; (2) tying coherence with the matrix yields higher confidence in results; (3) the WRS#2 rack ORUs need to be isolated; (4) and future work includes a plan for characterizing performance of isolation materials.

Space Station Environmental Control and Life Support Systems: An Update on Waste Water Reclamation

NASA Technical Reports Server (NTRS)

Ferner, Kathleen M.

1994-01-01

Since the mid-1980's, work has been ongoing In the development of the various environmental control and life support systems (ECLSS) for the space station. Part of this effort has been focused on the development of a new subsystem to reclaim waste water that had not been previously required for shuttle missions. Because of the extended manned missions proposed, reclamation of waste water becomes imperative to avoid the weight penalties associated with resupplying a crew's entire water needs for consumption and daily hygiene. Hamilton Standard, under contract to Boeing Aerospace and Electronics, has been designing the water reclamation system for space station use. Since June of 1991, Hamilton Standard has developed a combined water processor capable of reclaiming potable quality water from waste hygiene water, used laundry water, processed urine, Shuttle fuel cell water, humidity condensate and other minor waste water sources. The system was assembled and then tested with over 27,700 pounds of 'real' waste water. During the 1700 hours of system operation required to process this waste water, potable quality water meeting NASA and Boeing specifications was produced. This paper gives a schematic overview of the system, describes the test conditions and test results and outlines the next steps for system development.

ISS Expeditions 16 through 20: Chemical Analysis Results for Potable Water

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Schultz, John R.

2010-01-01

During the 2-year span from Expedition 16 through Expedition 20, the chemical quality of the potable water onboard the International Space Station (ISS) was verified safe for crew consumption through the return and chemical analysis of archival water samples by the Water and Food Analytical Laboratory (WAFAL) at Johnson Space Center (JSC). Reclaimed cabin humidity condensate and Russian ground-supplied water were the principal sources of potable water for Expeditions 16 through 18. During Expedition 18 the U.S. water processor assembly was delivered, installed, and tested during a 90-day checkout period. Beginning with Expedition 19, U.S. potable water recovered from a combined waste stream of humidity condensate and pretreated urine was also available for ISS crew use. A total of 74 potable water samples were collected using U.S. sampling hardware during Expeditions 16 through 20 and returned on both Shuttle and Soyuz vehicles. The results of JSC chemical analyses of these ISS potable water samples are presented in this paper. Eight potable water samples collected in flight with Russian hardware were also received for analysis, as well as 5 preflight samples of Rodnik potable water delivered to ISS on Russian Progress vehicles 28 to 34. Analytical results for these additional potable water samples are also reported and discussed.

Peake works on the WPA

NASA Image and Video Library

2016-03-22

ISS047e013845 (03/22/2016) --- ESA (European Space Agency) astronaut Tim Peake works on the Water Processor Assembly (WPA) aboard the International Space Station. The WPA is is responsible for treating waste water aboard the station for recycling back into potable water.

A Micro-Computer Computational Unit for an IR-CCD Intrusion Detection System.

DTIC Science & Technology

1980-10-01

signal processor. In the laboratory this processor has met or exceeded all its design goals. LYN H. SKOLNIK Project Engineer i, viii AMONO I...4 +* * SEPIKY LANL ITINE’-10. - 4. 1 4* This section of :ode containrs all assembly lasosiae rotinec ft - used in the IRCCD tntruton 4eector rm r s...In arra -B47- -I- here o, ’t , ’ retore A0I o.- .tmp2,r! rotetre r5t jr t o I 00 to r.9ioter restore ro-tine THRESH - routix, for set.ing J thres

Plasma Methane Pyrolysis for Spacecraft Oxygen Loop Closure

NASA Technical Reports Server (NTRS)

Greenwood, Z. W.

2018-01-01

Life support is a critical function of any crewed space vehicle or habitat. Human life support systems on the International Space Station (ISS) include a number of atmosphere revitalization (AR) technologies to provide breathable air and a comfortable living environment to the crew. The Trace Contaminant Control System removes harmful volatile organic compounds and other trace contaminants from the circulating air. The Carbon Dioxide Removal Assembly (CDRA) removes metabolic carbon dioxide (CO2) and returns air to the cabin. Humidity is kept at comfortable levels by a number of condensing heat exchangers. The Oxygen Generation Assembly (OGA) electrolyzes water to produce oxygen for the crew and hydrogen (H2) as a byproduct. A Sabatier reaction-based CO2 Reduction Assembly (CRA) was launched to the ISS in 2009 and became fully operational in June 2011.The CRA interfaces with both the OGA and CDRA. Carbon dioxide from the CDRA is compressed and stored in tanks until hydrogen is available from OGA water electrolysis. When the OGA is operational and there is CO2 available, the CRA is activated and produces methane and water via the Sabatier reaction shown in Equation 1... One approach to achieve these higher recovery rates builds upon the ISS AR architecture and includes adding a methane post-processor to recover H2 from CRA methane. NASA has been developing the Plasma Pyrolysis Assembly (PPA) to fill the role of a methane post-processor.

Temporary Urine and Brine Stowage System (TUBSS) Materials Selection and Testing

NASA Technical Reports Server (NTRS)

Carrigan, Caitlin; Dries, Kevin; Pensinger, Stuart

2011-01-01

Storing wastewater in the event of a system anomaly is a necessity for closed loop water recovery systems. The temporary urine and brine stowage system (TUBSS) is an assembly used to store and transfer pre-treated urine (PTU) and brine for processing or disposal at a later date. This paper describes the selection and testing of several candidate materials from both a chemical and material strength standpoint. In addition, this paper will provide results of testing as well as lessons learned from the project, culminating in the successful launch of the hardware.

An air-bearing weight offload system for ground test of heavy LSS structures

NASA Technical Reports Server (NTRS)

Rice, R. B.

1989-01-01

The capability and use of the Gravity Offload Facility (GOF) are discussed. Briefly explained are the: truss and base casting; carriage assembly; carriage weldment; vertical lift axis control; lifting cylinder; payload gimbal; motion base layout; and control processor.

Life Cycle Analysis of a SpaceCube Printed Circuit Board Assembly Using Physics of Failure Methodologies

NASA Technical Reports Server (NTRS)

Sood, Bhanu; Evans, John; Daniluk, Kelly; Sturgis, Jason; Davis, Milton; Petrick, David

2017-01-01

In this reliability life cycle evaluation of the SpaceCube 2.0 processor card, a partially populated version of the card is being evaluated to determine its durability with respect to typical GSFC mission loads.

[Feasibility Study on Digital Signal Processor and Gear Pump of Uroflowmeter Calibration Device].

PubMed

Yuan, Qing; Ji, Jun; Gao, Jiashuo; Wang, Lixin; Xiao, Hong

2016-08-01

It will cause hidden trouble on clinical application if the uroflowmeter is out of control.This paper introduces a scheme of uroflowmeter calibration device based on digital signal processor(DSP)and gear pump and shows studies of its feasibility.According to the research plan,we analyzed its stability,repeatability and linearity by building a testing system and carried out experiments on it.The flow test system is composed of DSP,gear pump and other components.The test results showed that the system could produce a stable water flow with high precision of repeated measurement and different flow rate.The test system can calibrate the urine flow rate well within the range of 9~50mL/s which has clinical significance,and the flow error is less than 1%,which meets the technical requirements of the calibration apparatus.The research scheme of uroflowmeter calibration device on DSP and gear pump is feasible.

Digital Circuit Analysis Using an 8080 Processor.

ERIC Educational Resources Information Center

Greco, John; Stern, Kenneth

1983-01-01

Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

The advanced receiver 2: Telemetry test results in CTA 21

NASA Technical Reports Server (NTRS)

Hinedi, S.; Bevan, R.; Marina, M.

1991-01-01

Telemetry tests with the Advanced Receiver II (ARX II) in Compatibility Test Area 21 are described. The ARX II was operated in parallel with a Block-III Receiver/baseband processor assembly combination (BLK-III/BPA) and a Block III Receiver/subcarrier demodulation assembly/symbol synchronization assembly combination (BLK-III/SDA/SSA). The telemetry simulator assembly provided the test signal for all three configurations, and the symbol signal to noise ratio as well as the symbol error rates were measured and compared. Furthermore, bit error rates were also measured by the system performance test computer for all three systems. Results indicate that the ARX-II telemetry performance is comparable and sometimes superior to the BLK-III/BPA and BLK-III/SDA/SSA combinations.

iLIDS Simulations and Videos for Docking TIM

NASA Technical Reports Server (NTRS)

Lewis, James L.

2010-01-01

The video shows various aspects of the International Low Impact Docking System, including team members, some production, configuration, mated androgynous iLIDS, SCS Lockdown system, thermal analysis, electrical engineering aspects, the iLIDS control box and emulator, radiation testing at BNL, component environmental testing, component vibration testing, 3G processor board delivery system, GTA vibe test, EMA testbed, hook and hook disassembly, flex shaftdrive assembly, GSE cradle MISSE-6 Columbus, MISSE 6 and 7 seal experiments, actuated full scale seal test rig, LIDS on Hubble, dynamics test prep, EDU 54 mass emulation and SCS, load ring characterization, 6DOF proof test, SCS at 6DOF, machining EEMS and inner ring assembly, APAS assembly, inner ring fitting, rotation stand assembly, EEMS mating, and EEMS proof of concept demonstration.

A new parallel-vector finite element analysis software on distributed-memory computers

NASA Technical Reports Server (NTRS)

Qin, Jiangning; Nguyen, Duc T.

1993-01-01

A new parallel-vector finite element analysis software package MPFEA (Massively Parallel-vector Finite Element Analysis) is developed for large-scale structural analysis on massively parallel computers with distributed-memory. MPFEA is designed for parallel generation and assembly of the global finite element stiffness matrices as well as parallel solution of the simultaneous linear equations, since these are often the major time-consuming parts of a finite element analysis. Block-skyline storage scheme along with vector-unrolling techniques are used to enhance the vector performance. Communications among processors are carried out concurrently with arithmetic operations to reduce the total execution time. Numerical results on the Intel iPSC/860 computers (such as the Intel Gamma with 128 processors and the Intel Touchstone Delta with 512 processors) are presented, including an aircraft structure and some very large truss structures, to demonstrate the efficiency and accuracy of MPFEA.

CTF Preprocessor User's Manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

Avramova, Maria; Salko, Robert K.

2016-05-26

This document describes how a user should go about using the CTF pre- processor tool to create an input deck for modeling rod-bundle geometry in CTF. The tool was designed to generate input decks in a quick and less error-prone manner for CTF. The pre-processor is a completely independent utility, written in Fortran, that takes a reduced amount of input from the user. The information that the user must supply is basic information on bundle geometry, such as rod pitch, clad thickness, and axial location of spacer grids--the pre-processor takes this basic information and determines channel placement and connection informationmore » to be written to the input deck, which is the most time-consuming and error-prone segment of creating a deck. Creation of the model is also more intuitive, as the user can specify assembly and water-tube placement using visual maps instead of having to place them by determining channel/channel and rod/channel connections. As an example of the benefit of the pre-processor, a quarter-core model that contains 500,000 scalar-mesh cells was read into CTF from an input deck containing 200,000 lines of data. This 200,000 line input deck was produced automatically from a set of pre-processor decks that contained only 300 lines of data.« less

A high capacity data recording device based on a digital audio processor and a video cassette recorder.

PubMed

Bezanilla, F

1985-03-01

A modified digital audio processor, a video cassette recorder, and some simple added circuitry are assembled into a recording device of high capacity. The unit converts two analog channels into digital form at 44-kHz sampling rate and stores the information in digital form in a common video cassette. Bandwidth of each channel is from direct current to approximately 20 kHz and the dynamic range is close to 90 dB. The total storage capacity in a 3-h video cassette is 2 Gbytes. The information can be retrieved in analog or digital form.

A high capacity data recording device based on a digital audio processor and a video cassette recorder.

PubMed Central

Bezanilla, F

1985-01-01

A modified digital audio processor, a video cassette recorder, and some simple added circuitry are assembled into a recording device of high capacity. The unit converts two analog channels into digital form at 44-kHz sampling rate and stores the information in digital form in a common video cassette. Bandwidth of each channel is from direct current to approximately 20 kHz and the dynamic range is close to 90 dB. The total storage capacity in a 3-h video cassette is 2 Gbytes. The information can be retrieved in analog or digital form. PMID:3978213

Temporary Urine and Brine Stowage System (TUBSS) Development

NASA Technical Reports Server (NTRS)

Dries, Kevin; Carrigan, Caitlin

2011-01-01

International Space Station (ISS) crew liquid human waste is treated with chromic and sulfuric acids to maintain stability prior to processing to recover water. This pre-treated urine (PTU) and its processed by-product, brine, are highly toxic fluids that require special containment for on-orbit stowage. The temporary urine and brine stowage syste m (TUBSS) is an assembly used to store and transfer pre-treated urine (PTU) and brine for processing or disposal at a later date. This paper describes the development of the TUBSS, including design for two-fault tolerance and materials selection to maintain a soft, collapsible container. In addition, this paper will provide results of testing as well as lessons learned from the project, culminating in the successful launch of the hardware.

Compact propane fuel processor for auxiliary power unit application

NASA Astrophysics Data System (ADS)

Dokupil, M.; Spitta, C.; Mathiak, J.; Beckhaus, P.; Heinzel, A.

With focus on mobile applications a fuel cell auxiliary power unit (APU) using liquefied petroleum gas (LPG) is currently being developed at the Centre for Fuel Cell Technology (Zentrum für BrennstoffzellenTechnik, ZBT gGmbH). The system is consisting of an integrated compact and lightweight fuel processor and a low temperature PEM fuel cell for an electric power output of 300 W. This article is presenting the current status of development of the fuel processor which is designed for a nominal hydrogen output of 1 k Wth,H2 within a load range from 50 to 120%. A modular setup was chosen defining a reformer/burner module and a CO-purification module. Based on the performance specifications, thermodynamic simulations, benchmarking and selection of catalysts the modules have been developed and characterised simultaneously and then assembled to the complete fuel processor. Automated operation results in a cold startup time of about 25 min for nominal load and carbon monoxide output concentrations below 50 ppm for steady state and dynamic operation. Also fast transient response of the fuel processor at load changes with low fluctuations of the reformate gas composition have been achieved. Beside the development of the main reactors the transfer of the fuel processor to an autonomous system is of major concern. Hence, concepts for packaging have been developed resulting in a volume of 7 l and a weight of 3 kg. Further a selection of peripheral components has been tested and evaluated regarding to the substitution of the laboratory equipment.

Toward three-dimensional microelectronic systems: directed self-assembly of silicon microcubes via DNA surface functionalization.

PubMed

Lämmerhardt, Nico; Merzsch, Stephan; Ledig, Johannes; Bora, Achyut; Waag, Andreas; Tornow, Marc; Mischnick, Petra

2013-07-02

The huge and intelligent processing power of three-dimensional (3D) biological "processors" like the human brain with clock speeds of only 0.1 kHz is an extremely fascinating property, which is based on a massively parallel interconnect strategy. Artificial silicon microprocessors are 7 orders of magnitude faster. Nevertheless, they do not show any indication of intelligent processing power, mostly due to their very limited interconnectivity. Massively parallel interconnectivity can only be realized in three dimensions. Three-dimensional artificial processors would therefore be at the root of fabricating artificially intelligent systems. A first step in this direction would be the self-assembly of silicon based building blocks into 3D structures. We report on the self-assembly of such building blocks by molecular recognition, and on the electrical characterization of the formed assemblies. First, planar silicon substrates were functionalized with self-assembling monolayers of 3-aminopropyltrimethoxysilane for coupling of oligonucleotides (single stranded DNA) with glutaric aldehyde. The oligonucleotide immobilization was confirmed and quantified by hybridization with fluorescence-labeled complementary oligonucleotides. After the individual processing steps, the samples were analyzed by contact angle measurements, ellipsometry, atomic force microscopy, and fluorescence microscopy. Patterned DNA-functionalized layers were fabricated by microcontact printing (μCP) and photolithography. Silicon microcubes of 3 μm edge length as model objects for first 3D self-assembly experiments were fabricated out of silicon-on-insulator (SOI) wafers by a combination of reactive ion etching (RIE) and selective wet etching. The microcubes were then surface-functionalized using the same protocol as on planar substrates, and their self-assembly was demonstrated both on patterned silicon surfaces (88% correctly placed cubes), and to cube aggregates by complementary DNA functionalization and hybridization. The yield of formed aggregates was found to be about 44%, with a relative fraction of dimers of some 30%. Finally, the electrical properties of the formed dimers were characterized using probe tips inside a scanning electron microscope.

People Considerations in Word Processing.

ERIC Educational Resources Information Center

Diamond, Marion L.

1984-01-01

Business educators preparing students for jobs in business and industry should become aware of the problems faced by workers in a typical large office environment. Word processor operators face many of the same problems as factory assembly line workers--lack of personalization, lack of incentive, and removal from the mainstream. (JOW)

Mass balances for a biological life support system simulation model

NASA Technical Reports Server (NTRS)

Volk, Tyler; Rumel, John D.

1987-01-01

Design decisions to aid the development of future space-based biological life support systems (BLSS) can be made with simulation models. Here the biochemical stoichiometry is developed for: (1) protein, carbohydrate, fat, fiber, and lignin production in the edible and inedible parts of plants; (2) food consumption and production of organic solids in urine, feces, and wash water by the humans; and (3) operation of the waste processor. Flux values for all components are derived for a steady-state system with wheat as the sole food source.

Life Testing of the Vapor Compression Distillation Urine Processing Assembly (VCD/UPA) at the Marshall Space Flight Center

NASA Technical Reports Server (NTRS)

Wieland, Paul O.

1998-01-01

Wastewater and urine generated on the International Space Station will be processed to recover pure water. The method selected is vapor compression distillation (VCD). To verify the long-term reliability and performance of the VCD Urine Processing Assembly (UPA), accelerated life testing was performed at the Marshall Space Flight Center (MSFC) from January 1993 to April 1996. Two UPAS, the VCD-5 and VCD-5A, were tested for 204 days and 665 days, respectively. The compressor gears and the distillation centrifuge drive belt were found to have an operating life of approximately 4800 hours. Precise alignment of the flex-spline of the fluids pump is essential to avoid failure of the pump after about 400 hours of operation. Also, leakage around the seals of the drive shaft of the fluids pump and purge pump must be eliminated for continued good performance. Results indicate that, with some design and procedural modifications and suitable quality control, the required performance and operational life can be met with the VCD/UPA.

Solid-phase extraction of small biologically active peptides on cartridges and microelution 96-well plates from human urine.

PubMed

Semenistaya, Ekaterina; Zvereva, Irina; Krotov, Grigory; Rodchenkov, Grigory

2016-09-01

Currently liquid chromatography - mass spectrometry (LC-MS) analysis after solid-phase extraction (SPE) on weak cation-exchange cartridges is a method of choice for anti-doping analysis of small bioactive peptides such as growth hormone releasing peptides (GHRPs), desmoporessin, LHRH, and TB-500 short fragment. Dilution of urine samples with phosphate buffer for pH adjustment and SPE on weak cation exchange microelution plates was tested as a means to increase throughput of this analysis. Dilution using 200 mM phosphate buffer provides good buffering capacity without affecting the peptides recoveries. SPE on microelution plates was performed on Waters Positive Pressure-96 Processor with subsequent evaporation of eluates in nitrogen flow. Though the use of smaller sample volume decreases the pre-concentration factor and increases the limits of detection of 5 out of 17 detected peptides, the recovery, linearity, and reproducibility of the microelution extraction were comparable with cartridge SPE. The effectiveness of protocols was confirmed by analysis of urine samples containing ipamorelin, and GHRP-6 and its metabolites. SPE after urine sample dilution with buffer can be used for faster sample preparation. The use of microelution plates decreases consumption of solvents and allows processing of up to 96 samples simultaneously. Cartridge SPE with manual рН adjustment remains the best option for confirmation. Copyright © 2015 John Wiley & Sons, Ltd. Copyright © 2015 John Wiley & Sons, Ltd.

Proton exchange membrane fuel cell technology for transportation applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swathirajan, S.

1996-04-01

Proton Exchange Membrane (PEM) fuel cells are extremely promising as future power plants in the transportation sector to achieve an increase in energy efficiency and eliminate environmental pollution due to vehicles. GM is currently involved in a multiphase program with the US Department of Energy for developing a proof-of-concept hybrid vehicle based on a PEM fuel cell power plant and a methanol fuel processor. Other participants in the program are Los Alamos National Labs, Dow Chemical Co., Ballard Power Systems and DuPont Co., In the just completed phase 1 of the program, a 10 kW PEM fuel cell power plantmore » was built and tested to demonstrate the feasibility of integrating a methanol fuel processor with a PEM fuel cell stack. However, the fuel cell power plant must overcome stiff technical and economic challenges before it can be commercialized for light duty vehicle applications. Progress achieved in phase I on the use of monolithic catalyst reactors in the fuel processor, managing CO impurity in the fuel cell stack, low-cost electrode-membrane assembles, and on the integration of the fuel processor with a Ballard PEM fuel cell stack will be presented.« less

Floating-Point Modules Targeted for Use with RC Compilation Tools

NASA Technical Reports Server (NTRS)

Sahin, Ibrahin; Gloster, Clay S.

2000-01-01

Reconfigurable Computing (RC) has emerged as a viable computing solution for computationally intensive applications. Several applications have been mapped to RC system and in most cases, they provided the smallest published execution time. Although RC systems offer significant performance advantages over general-purpose processors, they require more application development time than general-purpose processors. This increased development time of RC systems provides the motivation to develop an optimized module library with an assembly language instruction format interface for use with future RC system that will reduce development time significantly. In this paper, we present area/performance metrics for several different types of floating point (FP) modules that can be utilized to develop complex FP applications. These modules are highly pipelined and optimized for both speed and area. Using these modules, and example application, FP matrix multiplication, is also presented. Our results and experiences show, that with these modules, 8-10X speedup over general-purpose processors can be achieved.

A Rapid LC-HRMS Method for the Determination of Domoic Acid in Urine Using a Self-Assembly Pipette Tip Solid-Phase Extraction

PubMed Central

Zhang, Yiping; Chen, Dawei; Hong, Zhuan

2015-01-01

In this study, we developed a self-assembly pipette tip solid-phase extraction (PTSPE) method using a high molecular weight polymer material (PAX) as the adsorbent for the determination of domoic acid (DA) in human urine samples by liquid chromatography high-resolution mass spectrometry (LC-HRMS) analysis. The PTSPE cartridge, assembled by packing 9.1 mg of PAX as sorbent into a 200 μL pipette tip, showed high adsorption capacity for DA owing to the strong cationic properties of PAX. Compared with conventional SPE, the PTSPE is simple and fast, and shows some advantages in the aspects of less solvent consumption, low cost, the absence of the evaporation step, and short time requirement. All the parameters influencing the extraction efficiency such as pH, the amount of sorbent, the number of aspirating/dispensing cycles, and the type and volume of eluent in PTSPE were carefully investigated and optimized. Under the optimized conditions, the limit of detection (LOD) and limit of quantification (LOQ) values of DA were 0.12 μg/L and 0.37 μg/L respectively. The extraction recoveries of DA from the urine samples spiked at four different concentrations were in a range from 88.4% to 102.5%. The intra- and inter-day precisions varied from 2.1% to 7.6% and from 2.6% to 12.7%, respectively. The accuracy ranged from −1.9% to −7.4%. PMID:26729165

Partial Automated Alignment and Integration System

NASA Technical Reports Server (NTRS)

Kelley, Gary Wayne (Inventor)

2014-01-01

The present invention is a Partial Automated Alignment and Integration System (PAAIS) used to automate the alignment and integration of space vehicle components. A PAAIS includes ground support apparatuses, a track assembly with a plurality of energy-emitting components and an energy-receiving component containing a plurality of energy-receiving surfaces. Communication components and processors allow communication and feedback through PAAIS.

A site oriented supercomputer for theoretical physics: The Fermilab Advanced Computer Program Multi Array Processor System (ACMAPS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nash, T.; Atac, R.; Cook, A.

1989-03-06

The ACPMAPS multipocessor is a highly cost effective, local memory parallel computer with a hypercube or compound hypercube architecture. Communication requires the attention of only the two communicating nodes. The design is aimed at floating point intensive, grid like problems, particularly those with extreme computing requirements. The processing nodes of the system are single board array processors, each with a peak power of 20 Mflops, supported by 8 Mbytes of data and 2 Mbytes of instruction memory. The system currently being assembled has a peak power of 5 Gflops. The nodes are based on the Weitek XL Chip set. Themore » system delivers performance at approximately $300/Mflop. 8 refs., 4 figs.« less

Method and apparatus for measurement of orientation in an anisotropic medium

DOEpatents

Gilmore, Robert Snee; Kline, Ronald Alan; Deaton, Jr., John Broddus

1999-01-01

A method and apparatus are provided for simultaneously measuring the anisotropic orientation and the thickness of an article. The apparatus comprises a transducer assembly which propagates longitudinal and transverse waves through the article and which receives reflections of the waves. A processor is provided to measure respective transit times of the longitudinal and shear waves propagated through the article and to calculate respective predicted transit times of the longitudinal and shear waves based on an estimated thickness, an estimated anisotropic orientation, and an elasticity of the article. The processor adjusts the estimated thickness and the estimated anisotropic orientation to reduce the difference between the measured transit times and the respective predicted transit times of the longitudinal and shear waves.

Implementing the PM Programming Language using MPI and OpenMP - a New Tool for Programming Geophysical Models on Parallel Systems

NASA Astrophysics Data System (ADS)

Bellerby, Tim

2015-04-01

PM (Parallel Models) is a new parallel programming language specifically designed for writing environmental and geophysical models. The language is intended to enable implementers to concentrate on the science behind the model rather than the details of running on parallel hardware. At the same time PM leaves the programmer in control - all parallelisation is explicit and the parallel structure of any given program may be deduced directly from the code. This paper describes a PM implementation based on the Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) standards, looking at issues involved with translating the PM parallelisation model to MPI/OpenMP protocols and considering performance in terms of the competing factors of finer-grained parallelisation and increased communication overhead. In order to maximise portability, the implementation stays within the MPI 1.3 standard as much as possible, with MPI-2 MPI-IO file handling the only significant exception. Moreover, it does not assume a thread-safe implementation of MPI. PM adopts a two-tier abstract representation of parallel hardware. A PM processor is a conceptual unit capable of efficiently executing a set of language tasks, with a complete parallel system consisting of an abstract N-dimensional array of such processors. PM processors may map to single cores executing tasks using cooperative multi-tasking, to multiple cores or even to separate processing nodes, efficiently sharing tasks using algorithms such as work stealing. While tasks may move between hardware elements within a PM processor, they may not move between processors without specific programmer intervention. Tasks are assigned to processors using a nested parallelism approach, building on ideas from Reyes et al. (2009). The main program owns all available processors. When the program enters a parallel statement then either processors are divided out among the newly generated tasks (number of new tasks < number of processors) or tasks are divided out among the available processors (number of tasks > number of processors). Nested parallel statements may further subdivide the processor set owned by a given task. Tasks or processors are distributed evenly by default, but uneven distributions are possible under programmer control. It is also possible to explicitly enable child tasks to migrate within the processor set owned by their parent task, reducing load unbalancing at the potential cost of increased inter-processor message traffic. PM incorporates some programming structures from the earlier MIST language presented at a previous EGU General Assembly, while adopting a significantly different underlying parallelisation model and type system. PM code is available at www.pm-lang.org under an unrestrictive MIT license. Reference Ruymán Reyes, Antonio J. Dorta, Francisco Almeida, Francisco de Sande, 2009. Automatic Hybrid MPI+OpenMP Code Generation with llc, Recent Advances in Parallel Virtual Machine and Message Passing Interface, Lecture Notes in Computer Science Volume 5759, 185-195

Optical links in handheld multimedia devices

NASA Astrophysics Data System (ADS)

van Geffen, S.; Duis, J.; Miller, R.

2008-04-01

Ever emerging applications in handheld multimedia devices such as mobile phones, laptop computers, portable video games and digital cameras requiring increased screen resolutions are driving higher aggregate bitrates between host processor and display(s) enabling services such as mobile video conferencing, video on demand and TV broadcasting. Larger displays and smaller phones require complex mechanical 3D hinge configurations striving to combine maximum functionality with compact building volumes. Conventional galvanic interconnections such as Micro-Coax and FPC carrying parallel digital data between host processor and display module may produce Electromagnetic Interference (EMI) and bandwidth limitations caused by small cable size and tight cable bends. To reduce the number of signals through a hinge, the mobile phone industry, organized in the MIPI (Mobile Industry Processor Interface) alliance, is currently defining an electrical interface transmitting serialized digital data at speeds >1Gbps. This interface allows for electrical or optical interconnects. Above 1Gbps optical links may offer a cost effective alternative because of their flexibility, increased bandwidth and immunity to EMI. This paper describes the development of optical links for handheld communication devices. A cable assembly based on a special Plastic Optical Fiber (POF) selected for its mechanical durability is terminated with a small form factor molded lens assembly which interfaces between an 850nm VCSEL transmitter and a receiving device on the printed circuit board of the display module. A statistical approach based on a Lean Design For Six Sigma (LDFSS) roadmap for new product development tries to find an optimum link definition which will be robust and low cost meeting the power consumption requirements appropriate for battery operated systems.

Evaluation of the on-site immunoassay drug-screening device Triage-TOX in routine forensic autopsy.

PubMed

Tominaga, Mariko; Michiue, Tomomi; Maeda, Hitoshi

2015-11-01

Instrumental identification of drugs with quantification is essential in forensic toxicology, while on-site immunoassay urinalysis drug-screening devices conveniently provide preliminary information when adequately used. However, suitable or sufficient urine specimens are not always available. The present study evaluated the efficacy of a new on-site immunoassay drug-screening device Triage-TOX (Alere Inc., San Diego, CA, USA), which has recently been developed to provide objective data on the one-step automated processor, using 51 urine and 19 pericardial fluid samples from 66 forensic autopsy cases, compared with Triage-Drug of Abuse (DOA) and Monitect-9. For benzodiazepines, the positive predictive value and specificity of Triage-TOX were higher than those of Triage-DOA; however, sensitivity was higher with Monitect-9, despite frequent false-positives. The results for the other drugs with the three devices also included a few false-negatives and false-positives. These observations indicate the applicability of Triage-TOX in preliminary drug screening using urine or alternative materials in routine forensic autopsy, when a possible false-negative is considered, especially for benzodiazepines, providing objective information; however, the combined use of another device such as Monitect-9 can help minimize misinterpretation prior to instrumental analysis. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

Performance of a Water Recirculation Loop Maintenance Device and Process for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2013-01-01

A dual-bed device to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been designed and is undergoing testing. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the development of a water recirculation maintenance device is to further enhance this advantage through the leveraging of fluid loop management lessons-learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The bed design further leverages a sorbent developed for ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Design and Evaluation of a Water Recirculation Loop Maintenance Device for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2012-01-01

A dual-bed device to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been designed and is undergoing testing. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing sublimator technology. The driver for the development of a water recirculation maintenance device is to further enhance this advantage through the leveraging of fluid loop management lessons learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high-capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit Transport Water Loop. The bed design further leverages a sorbent developed for the ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System. The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of crewed spaceflight Environmental Control and Life Support System hardware.

Design and Evaluation of a Water Recirculation Loop Maintenance Device for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2011-01-01

A dual-bed device to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been designed and is undergoing testing. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the development of a water recirculation maintenance device is to further enhance this advantage through the leveraging of fluid loop management lessons-learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The bed design further leverages a sorbent developed for ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a clear demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Performance of a Water Recirculation Loop Maintenance Device and Process for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Rector, Tony; Steele, John W.; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2012-01-01

A water loop maintenance device and process to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been undergoing a performance evaluation. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the water recirculation maintenance device and process is to further enhance this advantage through the leveraging of fluid loop management lessons-learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The maintenance process further leverages a sorbent developed for ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware. This

Development of new UV-I. I. Cerenkov Viewing Device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kuribara, Masayuki; Nemoto, Koshichi

1994-02-01

The Cerenkov glow images from boiling-water reactors (BWR) and pressurized-water reactors (PWR) irradiated fuel assemblies are generally used for inspections. However, sometimes it is difficult or impossible to identify the image by the conventional Cerenkov Viewing Device (CVD), because of the long cooling time and/or low burnup. Now a new UV-I.I. (Ultra-Violet light Image Intensifier) CVD has been developed, which can detect the very weak Cerenkov glow from spent fuel assemblies. As this new device uses the newly developed proximity focused type UV-I.I., Cerenkov photons are used efficiently, producing better quality Cerenkov glow images. Moreover, since the image is convertedmore » to a video signal, it is easy to improve the signal to noise ratio (S/N) by an image processor. The new CVD was tested at BWR and PWR power plants in Japan, with fuel burnups ranging from 6,200--33,000 MWD/MTU (megawatt days per metric ton of uranium) and cooling times ranging from 370 to 6,200 d. The tests showed that the new CVD is superior to the conventional STA/CRIEPI CVD, and could detect very feeble Cerenkov glow images using an image processor.« less

Applications Performance on NAS Intel Paragon XP/S - 15#

NASA Technical Reports Server (NTRS)

Saini, Subhash; Simon, Horst D.; Copper, D. M. (Technical Monitor)

1994-01-01

The Numerical Aerodynamic Simulation (NAS) Systems Division received an Intel Touchstone Sigma prototype model Paragon XP/S- 15 in February, 1993. The i860 XP microprocessor with an integrated floating point unit and operating in dual -instruction mode gives peak performance of 75 million floating point operations (NIFLOPS) per second for 64 bit floating point arithmetic. It is used in the Paragon XP/S-15 which has been installed at NAS, NASA Ames Research Center. The NAS Paragon has 208 nodes and its peak performance is 15.6 GFLOPS. Here, we will report on early experience using the Paragon XP/S- 15. We have tested its performance using both kernels and applications of interest to NAS. We have measured the performance of BLAS 1, 2 and 3 both assembly-coded and Fortran coded on NAS Paragon XP/S- 15. Furthermore, we have investigated the performance of a single node one-dimensional FFT, a distributed two-dimensional FFT and a distributed three-dimensional FFT Finally, we measured the performance of NAS Parallel Benchmarks (NPB) on the Paragon and compare it with the performance obtained on other highly parallel machines, such as CM-5, CRAY T3D, IBM SP I, etc. In particular, we investigated the following issues, which can strongly affect the performance of the Paragon: a. Impact of the operating system: Intel currently uses as a default an operating system OSF/1 AD from the Open Software Foundation. The paging of Open Software Foundation (OSF) server at 22 MB to make more memory available for the application degrades the performance. We found that when the limit of 26 NIB per node out of 32 MB available is reached, the application is paged out of main memory using virtual memory. When the application starts paging, the performance is considerably reduced. We found that dynamic memory allocation can help applications performance under certain circumstances. b. Impact of data cache on the i860/XP: We measured the performance of the BLAS both assembly coded and Fortran coded. We found that the measured performance of assembly-coded BLAS is much less than what memory bandwidth limitation would predict. The influence of data cache on different sizes of vectors is also investigated using one-dimensional FFTs. c. Impact of processor layout: There are several different ways processors can be laid out within the two-dimensional grid of processors on the Paragon. We have used the FFT example to investigate performance differences based on processors layout.

The design of infrared information collection circuit based on embedded technology

NASA Astrophysics Data System (ADS)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

NASA Tech Briefs, September 2013

NASA Technical Reports Server (NTRS)

2013-01-01

Topics include: ISS Ammonia Leak Detection Through X-Ray Fluorescence; A System for Measuring the Sway of the Vehicle Assembly Building; Fast, High-Precision Readout Circuit for Detector Arrays; Victim Simulator for Victim Detection Radar; Hydrometeor Size Distribution Measurements by Imaging the Attenuation of a Laser Spot; Quasi-Linear Circuit; High-Speed, High-Resolution Time-to-Digital Conversion; Li-Ion Battery and Supercapacitor Hybrid Design for Long Extravehicular Activities; Ultrasonic Low-Friction Containment Plate for Thermal and Ultrasonic Stir Weld Processes; High-Powered, Ultrasonically Assisted Thermal Stir Welding; Next-Generation MKIII Lightweight HUT/Hatch Assembly; Centrifugal Sieve for Gravity-Level-Independent Size; Segregation of Granular Materials; Ion Exchange Technology Development in Support of the Urine Processor Assembly; Nickel-Graphite Composite Compliant Interface and/or Hot Shoe Material; UltraSail CubeSat Solar Sail Flight Experiment; Mechanism for Deploying a Long, Thin-Film Antenna From a Rover; Counterflow Regolith Heat Exchanger; Acquisition and Retaining Granular Samples via a Rotating Coring Bit; Very-Low-Cost, Rugged Vacuum System; Medicine Delivery Device With Integrated Sterilization and Detection; FRET-Aptamer Assays for Bone Marker Assessment, C-Telopeptide, Creatinine, and Vitamin D; Multimode Directional Coupler for Utilization of Harmonic Frequencies from TWTAs; Dual-Polarization, Multi-Frequency Antenna Array for use with Hurricane Imaging Radiometer; Complementary Barrier Infrared Detector (CBIRD) Contact Methods; Autonomous Control of Space Nuclear Reactors; High-Power, High-Speed Electro-Optic Pockels Cell Modulator; Covariance Analysis Tool (G-CAT) for Computing Ascent, Descent, and Landing Errors; Enigma Version 12; Micrometeoroid and Orbital Debris (MMOD) Shield Ballistic Limit Analysis Program; Spitzer Telemetry Processing System; Planetary Protection Bioburden Analysis Program; Wing Leading Edge RCC Rapid Response Damage Prediction Tool (IMPACT2); ISSM: Ice Sheet System Model; Automated Loads Analysis System (ATLAS); Integrated Main Propulsion System Performance Reconstruction Process/Models. Phoenix Telemetry Processor; Contact Graph Routing Enhancements Developed in ION for DTN; GFEChutes Lo-Fi; Advanced Strategic and Tactical Relay Request Management for the Mars Relay Operations Service; Software for Generating Troposphere Corrections for InSAR Using GPS and Weather Model Data; Ionospheric Specifications for SAR Interferometry (ISSI); Implementation of a Wavefront-Sensing Algorithm; Sally Ride EarthKAM - Automated Image Geo-Referencing Using Google Earth Web Plug-In; Trade Space Specification Tool (TSST) for Rapid Mission Architecture (Version 1.2); Acoustic Emission Analysis Applet (AEAA) Software; Memory-Efficient Onboard Rock Segmentation; Advanced Multimission Operations System (ATMO); Robot Sequencing and Visualization Program (RSVP); Automating Hyperspectral Data for Rapid Response in Volcanic Emergencies; Raster-Based Approach to Solar Pressure Modeling; Space Images for NASA JPL Android Version; Kinect Engineering with Learning (KEWL); Spacecraft 3D Augmented Reality Mobile App; MPST Software: grl_pef_check; Real-Time Multimission Event Notification System for Mars Relay; SIM_EXPLORE: Software for Directed Exploration of Complex Systems; Mobile Timekeeping Application Built on Reverse-Engineered JPL Infrastructure; Advanced Query and Data Mining Capabilities for MaROS; Jettison Engineering Trajectory Tool; MPST Software: grl_suppdoc; PredGuid+A: Orion Entry Guidance Modified for Aerocapture; Planning Coverage Campaigns for Mission Design and Analysis: CLASP for DESDynl; and Space Place Prime.

Parallel processing for nonlinear dynamics simulations of structures including rotating bladed-disk assemblies

NASA Technical Reports Server (NTRS)

Hsieh, Shang-Hsien

1993-01-01

The principal objective of this research is to develop, test, and implement coarse-grained, parallel-processing strategies for nonlinear dynamic simulations of practical structural problems. There are contributions to four main areas: finite element modeling and analysis of rotational dynamics, numerical algorithms for parallel nonlinear solutions, automatic partitioning techniques to effect load-balancing among processors, and an integrated parallel analysis system.

Nutritional Status Assessment (SMO 016E)

NASA Technical Reports Server (NTRS)

Smith, S. M.; Heer, M. A.; Zwart, S. R.

2014-01-01

The Nutritional Status Assessment Supplemental Medical Objective was initiated to expand nominal clinical nutrition testing of ISS astronauts, and to gain a better understanding of the time course of changes in nutritional status during flight. The primary activity of this effort was collecting blood and urine samples during flight for analysis after return to Earth. Samples were subjected to a battery of tests. The resulting data provide a comprehensive survey of how nutritional status and related systems are affected by 4-6 months of space flight. Analysis of these data has yielded many findings to date, including: Vision. Documented evidence that biochemical markers involved in one-carbon metabolism were altered in crewmembers who experienced vision-related issues during and after flight (1). Iron, Oxidative Stress, and Bone. In-flight data document a clear association of increased iron stores, markers of oxidative damage to DNA, and bone loss (2). Exercise. Documented that well-nourished crewmembers performing heavy resistance exercise returned from ISS with bone mineral densities unchanged from preflight (3). Furthermore, the response of bone to space flight and exercise countermeasures was the same in men and women (4). Body Mass. Crewmembers lose 2-5% of their body mass in the first month of flight, and maintain the lower body mass during flight (5). Additionally, the two devices to measure body mass on orbit, the SLAMMD and BMMD, provide similar results (5). Cytokines. Findings indicated that a pattern of persistent physiological adaptations occurs during space flight that includes shifts in immune and hormonal regulation (6). Fish/Bone. Documented a relationship between fish intake and bone loss in astronauts (that is, those who ate more fish lost less bone) (7). Vitamin K. Documented that in generally well-fed and otherwise healthy individuals, vitamin K status and bone vitamin K-dependent proteins are unaffected by space flight (and bed rest) (8). Testosterone. Documented that blood concentrations of testosterone were unchanged during flight, but a transient decline occurred after landing (9). Calcium. Nutrition SMO data contributed to the ISS Program by helping understand how and why the Urine Processor Assembly clogged with calcium sulfate precipitate (10). Sample Processing. Ground-based analytical testing results have also been published (11).

Development of a soldier-portable fuel cell power system. Part I: A bread-board methanol fuel processor

NASA Astrophysics Data System (ADS)

Palo, Daniel R.; Holladay, Jamie D.; Rozmiarek, Robert T.; Guzman-Leong, Consuelo E.; Wang, Yong; Hu, Jianli; Chin, Ya-Huei; Dagle, Robert A.; Baker, Eddie G.

A 15-W e portable power system is being developed for the US Army that consists of a hydrogen-generating fuel reformer coupled to a proton-exchange membrane fuel cell. In the first phase of this project, a methanol steam reformer system was developed and demonstrated. The reformer system included a combustor, two vaporizers, and a steam reforming reactor. The device was demonstrated as a thermally independent unit over the range of 14-80 W t output. Assuming a 14-day mission life and an ultimate 1-kg fuel processor/fuel cell assembly, a base case was chosen to illustrate the expected system performance. Operating at 13 W e, the system yielded a fuel processor efficiency of 45% (LHV of H 2 out/LHV of fuel in) and an estimated net efficiency of 22% (assuming a fuel cell efficiency of 48%). The resulting energy density of 720 Wh/kg is several times the energy density of the best lithium-ion batteries. Some immediate areas of improvement in thermal management also have been identified, and an integrated fuel processor is under development. The final system will be a hybrid, containing a fuel reformer, a fuel cell, and a rechargeable battery. The battery will provide power for start-up and added capacity for times of peak power demand.

Development of a Soldier-Portable Fuel Cell Power System, Part I: A Bread-Board Methanol Fuel Processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palo, Daniel R.; Holladay, Jamelyn D.; Rozmiarek, Robert T.

A 15-We portable power system is being developed for the US Army, comprised of a hydrogen-generating fuel reformer coupled to a hydrogen-converting fuel cell. As a first phase of this project, a methanol steam reformer system was developed and demonstrated. The reformer system included a combustor, two vaporizers, and a steam-reforming reactor. The device was demonstrated as a thermally independent unit over the range of 14 to 80 Wt output. Assuming a 14-day mission life and an ultimate 1-kg fuel processor/fuel cell assembly, a base case was chosen to illustrate the expected system performance. Operating at 13 We, the systemmore » yielded a fuel processor efficiency of 45% (LHV of H2 out/LHV of fuel in) and an estimated net efficiency of 22% (assuming a fuel cell efficiency of 48%). The resulting energy density of 720 W-hr/kg is several times the energy density of the best lithium-ion batteries. Some immediate areas of improvement in thermal management also have been identified and an integrated fuel processor is under development. The final system will be a hybrid, containing a fuel reformer, fuel cell, and rechargeable battery. The battery will provide power for startup and added capacity for times of peak power demand.« less

Urine Pretreatment Configuration and Test Results for Space Applications

NASA Technical Reports Server (NTRS)

Howard, Stanley G.; Hutchens, Cindy F.; Rethke, Donald W.; Swartley, Vernon L.; Marsh, Robert W.

1998-01-01

Pretreatment of urine using Oxone and sulfuric acid is baselined in the International Space Station (ISS) waste water reclamation system to control odors, fix urea and control microbial growth. In addition, pretreatment is recommended for long term flight use of urine collection and two phase separation to reduce or eliminate fouling of the associated hardware and plumbing with urine precipitates. This is important for ISS application because the amount of maintenance time for cleaning and repairing hardware must be minimized. This paper describes the development of a chemical pretreatment system based on solid tablet shapes which are positioned in the urine collection hose and are dissolved by the intrained urine at the proper ratio of pretreatment to urine. Building upon the prior success of the developed and tested solid Oxone tablet a trade study was completed to confirm if a similar approach, or alternative, would be appropriate for the sulfuric acid injection method. In addition, a recommended handling and packaging approach of the solid tablets for long term, safe and convenient use on ISS was addressed. Consequently, the solid tablet concept with suitable packaging was identified as the Urine Pretreat / Prefilter Assembly (UPPA). Testing of the UPPA configuration confirmed the disolution rates and ratios required by ISS were achieved. This testing included laboratory controlled methods as well as a 'real world' test evaluation that occurred during the 150 day Stage 10 Water Recovery Test (WRT) conducted at NASA Marshall Space Flight Center (MSFC).

RASSP signal processing architectures

NASA Astrophysics Data System (ADS)

Shirley, Fred; Bassett, Bob; Letellier, J. P.

1995-06-01

The rapid prototyping of application specific signal processors (RASSP) program is an ARPA/tri-service effort to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are specified, designed, documented, manufactured, and supported. The domain of embedded signal processing was chosen because it is important to a variety of military and commercial applications as well as for the challenge it presents in terms of complexity and performance demands. The principal effort is being performed by two major contractors, Lockheed Sanders (Nashua, NH) and Martin Marietta (Camden, NJ). For both, improvements in methodology are to be exercised and refined through the performance of individual 'Demonstration' efforts. The Lockheed Sanders' Demonstration effort is to develop an infrared search and track (IRST) processor. In addition, both contractors' results are being measured by a series of externally administered (by Lincoln Labs) six-month Benchmark programs that measure process improvement as a function of time. The first two Benchmark programs are designing and implementing a synthetic aperture radar (SAR) processor. Our demonstration team is using commercially available VME modules from Mercury Computer to assemble a multiprocessor system scalable from one to hundreds of Intel i860 microprocessors. Custom modules for the sensor interface and display driver are also being developed. This system implements either proprietary or Navy owned algorithms to perform the compute-intensive IRST function in real time in an avionics environment. Our Benchmark team is designing custom modules using commercially available processor ship sets, communication submodules, and reconfigurable logic devices. One of the modules contains multiple vector processors optimized for fast Fourier transform processing. Another module is a fiberoptic interface that accepts high-rate input data from the sensors and provides video-rate output data to a display. This paper discusses the impact of simulation on choosing signal processing algorithms and architectures, drawing from the experiences of the Demonstration and Benchmark inter-company teams at Lockhhed Sanders, Motorola, Hughes, and ISX.

Using R in Taverna: RShell v1.2

PubMed Central

Wassink, Ingo; Rauwerda, Han; Neerincx, Pieter BT; Vet, Paul E van der; Breit, Timo M; Leunissen, Jack AM; Nijholt, Anton

2009-01-01

Background R is the statistical language commonly used by many life scientists in (omics) data analysis. At the same time, these complex analyses benefit from a workflow approach, such as used by the open source workflow management system Taverna. However, Taverna had limited support for R, because it supported just a few data types and only a single output. Also, there was no support for graphical output and persistent sessions. Altogether this made using R in Taverna impractical. Findings We have developed an R plugin for Taverna: RShell, which provides R functionality within workflows designed in Taverna. In order to fully support the R language, our RShell plugin directly uses the R interpreter. The RShell plugin consists of a Taverna processor for R scripts and an RShell Session Manager that communicates with the R server. We made the RShell processor highly configurable allowing the user to define multiple inputs and outputs. Also, various data types are supported, such as strings, numeric data and images. To limit data transport between multiple RShell processors, the RShell plugin also supports persistent sessions. Here, we will describe the architecture of RShell and the new features that are introduced in version 1.2, i.e.: i) Support for R up to and including R version 2.9; ii) Support for persistent sessions to limit data transfer; iii) Support for vector graphics output through PDF; iv)Syntax highlighting of the R code; v) Improved usability through fewer port types. Our new RShell processor is backwards compatible with workflows that use older versions of the RShell processor. We demonstrate the value of the RShell processor by a use-case workflow that maps oligonucleotide probes designed with DNA sequence information from Vega onto the Ensembl genome assembly. Conclusion Our RShell plugin enables Taverna users to employ R scripts within their workflows in a highly configurable way. PMID:19607662

Urinary Sodium and Potassium Excretion and Dietary Sources of Sodium in Maputo, Mozambique.

PubMed

Queiroz, Ana; Damasceno, Albertino; Jessen, Neusa; Novela, Célia; Moreira, Pedro; Lunet, Nuno; Padrão, Patrícia

2017-08-03

This study aimed to evaluate the urinary excretion of sodium and potassium, and to estimate the main food sources of sodium in Maputo dwellers. A cross-sectional evaluation of a sample of 100 hospital workers was conducted between October 2012 and May 2013. Sodium and potassium urinary excretion was assessed in a 24-h urine sample; creatinine excretion was used to exclude unlikely urine values. Food intake in the same period of urine collection was assessed using a 24-h dietary recall. The Food Processor Plus ® was used to estimate sodium intake corresponding to naturally occurring sodium and sodium added to processed foods (non-discretionary sodium). Salt added during culinary preparations (discretionary sodium) was computed as the difference between urinary sodium excretion and non-discretionary sodium. The mean (standard deviation) urinary sodium excretion was 4220 (1830) mg/day, and 92% of the participants were above the World Health Organization (WHO) recommendations. Discretionary sodium contributed 60.1% of total dietary sodium intake, followed by sodium from processed foods (29.0%) and naturally occurring sodium (10.9%). The mean (standard deviation) urinary potassium excretion was 1909 (778) mg/day, and 96% of the participants were below the WHO potassium intake recommendation. The mean (standard deviation) sodium to potassium molar ratio was 4.2 (2.4). Interventions to decrease sodium and increase potassium intake are needed in Mozambique.

Urinary Sodium and Potassium Excretion and Dietary Sources of Sodium in Maputo, Mozambique

PubMed Central

Queiroz, Ana; Damasceno, Albertino; Jessen, Neusa; Novela, Célia; Moreira, Pedro; Lunet, Nuno

2017-01-01

This study aimed to evaluate the urinary excretion of sodium and potassium, and to estimate the main food sources of sodium in Maputo dwellers. A cross-sectional evaluation of a sample of 100 hospital workers was conducted between October 2012 and May 2013. Sodium and potassium urinary excretion was assessed in a 24-h urine sample; creatinine excretion was used to exclude unlikely urine values. Food intake in the same period of urine collection was assessed using a 24-h dietary recall. The Food Processor Plus® was used to estimate sodium intake corresponding to naturally occurring sodium and sodium added to processed foods (non-discretionary sodium). Salt added during culinary preparations (discretionary sodium) was computed as the difference between urinary sodium excretion and non-discretionary sodium. The mean (standard deviation) urinary sodium excretion was 4220 (1830) mg/day, and 92% of the participants were above the World Health Organization (WHO) recommendations. Discretionary sodium contributed 60.1% of total dietary sodium intake, followed by sodium from processed foods (29.0%) and naturally occurring sodium (10.9%). The mean (standard deviation) urinary potassium excretion was 1909 (778) mg/day, and 96% of the participants were below the WHO potassium intake recommendation. The mean (standard deviation) sodium to potassium molar ratio was 4.2 (2.4). Interventions to decrease sodium and increase potassium intake are needed in Mozambique. PMID:28771193

Parallel architecture for rapid image generation and analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nerheim, R.J.

1987-01-01

A multiprocessor architecture inspired by the Disney multiplane camera is proposed. For many applications, this approach produces a natural mapping of processors to objects in a scene. Such a mapping promotes parallelism and reduces the hidden-surface work with minimal interprocessor communication and low-overhead cost. Existing graphics architectures store the final picture as a monolithic entity. The architecture here stores each object's image separately. It assembles the final composite picture from component images only when the video display needs to be refreshed. This organization simplifies the work required to animate moving objects that occlude other objects. In addition, the architecture hasmore » multiple processors that generate the component images in parallel. This further shortens the time needed to create a composite picture. In addition to generating images for animation, the architecture has the ability to decompose images.« less

FTMP (Fault Tolerant Multiprocessor) programmer's manual

NASA Technical Reports Server (NTRS)

Feather, F. E.; Liceaga, C. A.; Padilla, P. A.

1986-01-01

The Fault Tolerant Multiprocessor (FTMP) computer system was constructed using the Rockwell/Collins CAPS-6 processor. It is installed in the Avionics Integration Research Laboratory (AIRLAB) of NASA Langley Research Center. It is hosted by AIRLAB's System 10, a VAX 11/750, for the loading of programs and experimentation. The FTMP support software includes a cross compiler for a high level language called Automated Engineering Design (AED) System, an assembler for the CAPS-6 processor assembly language, and a linker. Access to this support software is through an automated remote access facility on the VAX which relieves the user of the burden of learning how to use the IBM 4381. This manual is a compilation of information about the FTMP support environment. It explains the FTMP software and support environment along many of the finer points of running programs on FTMP. This will be helpful to the researcher trying to run an experiment on FTMP and even to the person probing FTMP with fault injections. Much of the information in this manual can be found in other sources; we are only attempting to bring together the basic points in a single source. If the reader should need points clarified, there is a list of support documentation in the back of this manual.

Incineration for resource recovery in a closed ecological life support system

NASA Technical Reports Server (NTRS)

Upadhye, R. S.; Wignarajah, K.; Wydeven, T.

1993-01-01

A functional schematic, including mass and energy balance, of a solid waste processing system for a controlled ecological life support system (CELSS) was developed using Aspen Plus, a commercial computer simulation program. The primary processor in this system is an incinerator for oxidizing organic wastes. The major products derived from the incinerator are carbon dioxide and water, which can be recycled to a crop growth chamber (CGC) for food production. The majority of soluble inorganics are extracted or leached from the inedible biomass before they reach the incinerator, so that they can be returned directly to the CGC and reused as nutrients. The heat derived from combustion of organic compounds in the incinerator was used for phase-change water purification. The waste streams treated by the incinerator system conceptualized in this work are inedible biomass from a CGC, human urine (including urinal flush water) and feces, humidity condensate, shower water, and trash. It is estimated that the theoretical minimum surface area required for the radiator to reject the unusable heat output from this system would be 0.72 sq m/person at 298 K.

Performance of Water Recirculation Loop Maintenance Components for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Rector, Tony; Peyton, Barbara M.; Steele, John W.; Makinen, Janice; Bue, Grant C.; Campbell, Colin

2014-01-01

Water loop maintenance components to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop have undergone a comparative performance evaluation with a second SWME water recirculation loop with no water quality maintenance. Results show the benefits of periodic water maintenance. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the evaluation of water recirculation maintenance components was to further enhance this advantage through the leveraging of fluid loop management lessons learned from the International Space Station (ISS). A bed design that was developed for a UTAS military application, and considered for a potential ISS application with the Urine Processor Assembly, provided a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The maintenance cycle included the use of a biocide delivery component developed for ISS to introduce a biocide in a microgravity compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Performance of Water Recirculation Loop Maintentance Components for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Rector, Tony; Peyton, Barbara; Steele, John W.; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2014-01-01

Water loop maintenance components to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop have undergone a comparative performance evaluation with a second SWME water recirculation loop with no water quality maintenance. Results show the benefits of periodic water maintenance. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the evaluation of water recirculation maintenance components was to further enhance this advantage through the leveraging of fluid loop management lessonslearned from the International Space Station (ISS). A bed design that was developed for a UTAS military application, and considered for a potential ISS application with the Urine Processor Assembly, provided a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The maintenance cycle included the use of a biocide delivery component developed for ISS to introduce a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Occupational Exposure to Chromium of Assembly Workers in Aviation Industries.

PubMed

Genovese, G; Castiglia, L; Pieri, M; Novi, C; d'Angelo, R; Sannolo, N; Lamberti, M; Miraglia, N

2015-01-01

Aircraft are constructed by modules that are covered by a "primer" layer, which can often contain hexavalent chromium [Cr(VI)], known carcinogen to humans. While the occupational exposure to Cr(VI) during aircraft painting is ascertained, the exposure assessment of assembly workers (assemblers) requires investigations. Three biological monitoring campaigns (BM-I,II,III) were performed in an aviation industry, on homogeneous groups of assemblers (N = 43) and controls (N = 23), by measuring chromium concentrations in end-shift urine collected at the end of the working week and the chromium concentration difference between end- and before-shift urines. BM-I was conducted on full-time workers, BM-II was performed on workers after a 3-4 day absence from work, BM-III on workers using ecoprimers with lower Cr(VI) content. Samples were analyzed by atomic absorption spectroscopy and mean values were compared by T-test. Even if Cr concentrations measured during BM-I were lower than Biological Exposure Indices by ACGIH, statistically significant differences were found between urinary Cr concentrations of workers and controls. Despite 3-4 days of absence from work, urinary chromium concentrations measured during BM-II were still higher than references from nonoccupationally exposed populations. In the BM-III campaign, the obtained preliminary results suggested the efficacy of using ecoprimers. The healthcare of workers exposed to carcinogenic agents follows the principle of limiting the exposure to "the minimum technically possible". The obtained results evidence that assemblers of aviation industries, whose task does not involve the direct use of primers containing Cr(VI), show an albeit slight occupational exposure to Cr(VI), that must be carefully taken into consideration in planning suitable prevention measures during risk assessment and management processes.

Biologically Pre-Treated Habitation Waste Water as a Sustainable Green Urine Pre-Treat Solution

NASA Technical Reports Server (NTRS)

Jackson, W. Andrew; Thompson, Bret; Sevanthi, Ritesh; Morse, Audra; Meyer, Caitlin; Callahan, Michael

2017-01-01

The ability to recover water from urine and flush water is a critical process to allow long term sustainable human habitation in space or bases on the moon or mars. Organic N present as urea or similar compounds can hydrolyze producing free ammonia. This reaction results in an increase in the pH converting ammonium to ammonia which is volatile and not removed by distillation. The increase in pH will also cause precipitation reactions to occur. In order to prevent this, urine on ISS is combined with a pretreat solution. While use of a pretreatment solution has been successful, there are numerous draw backs including: storage and use of highly hazardous solutions, limitations on water recovery (less than 85%), and production of brine with pore dewatering characteristics. We evaluated the use of biologically treated habitation wastewaters (ISS and early planetary base) to replace the current pretreat solution. We evaluated both amended and un-amended bioreactor effluent. For the amended effluent, we evaluated "green" pretreat chemicals including citric acid and citric acid amended with benzoic acid. We used a mock urine/air separator modeled after the urine collection assembly on ISS. The urine/air separator was challenged continually for >6 months. Depending on the test point, the separator was challenged daily with donated urine and flushed with amended or un-amended reactor effluent. We monitored the pH of the urine, flush solution and residual pH in the urine/air separator after each urine event. We also evaluated solids production and biological growth. Our results support the use of both un-amended and amended bioreactor effluent to maintain the operability of the urine /air separator. The ability to use bioreactor effluent could decrease consumable cost, reduce hazards associated with current pre-treat chemicals, allow other membrane based desalination processes to be utilized, and improve brine characteristics.

Chemical Method of Urine Volume Measurement

NASA Technical Reports Server (NTRS)

Petrack, P.

1967-01-01

A system has been developed and qualified as flight hardware for the measurement of micturition volumes voided by crewmen during Gemini missions. This Chemical Urine Volume Measurement System (CUVMS) is used for obtaining samples of each micturition for post-flight volume determination and laboratory analysis for chemical constituents of physiological interest. The system is versatile with respect to volumes measured, with a capacity beyond the largest micturition expected to be encountered, and with respect to mission duration of inherently indefinite length. The urine sample is used for the measurement of total micturition volume by a tracer dilution technique, in which a fixed, predetermined amount of tritiated water is introduced and mixed into the voided urine, and the resulting concentration of the tracer in the sample is determined with a liquid scintillation spectrometer. The tracer employed does not interfere with the analysis for the chemical constituents of the urine. The CUVMS hardware consists of a four-way selector valve in which an automatically operated tracer metering pump is incorporated, a collection/mixing bag, and tracer storage accumulators. The assembled system interfaces with a urine receiver at the selector valve inlet, sample bags which connect to the side of the selector valve, and a flexible hose which carries the excess urine to the overboard drain connection. Results of testing have demonstrated system volume measurement accuracy within the specification limits of +/-5%, and operating reliability suitable for system use aboard the GT-7 mission, in which it was first used.

Landsat-1 and Landsat-2 flight evaluation

NASA Technical Reports Server (NTRS)

1975-01-01

The flight performance of Landsat 1 and Landsat 2 is analyzed. Flight operations of the satellites are briefly summarized. Other topics discussed include: orbital parameters; power subsystem; attitude control subsystem; command/clock subsystem; telemetry subsystem; orbit adjust subsystem; magnetic moment compensating assembly; unified s-band/premodulation processor; electrical interface subsystem; thermal subsystem; narrowband tape recorders; wideband telemetry subsystem; attitude measurement sensor; wideband video tape recorders; return beam vidicon; multispectral scanner subsystem; and data collection subsystem.

Compilation of Abstracts of Theses Submitted by Candidates for Degrees.

DTIC Science & Technology

1984-06-01

Management System for the TI - 59 Programmable Calculator Kersh, T. B. Signal Processor Interface 65 CPT, USA Simulation of the AN/SPY-lA Radar...DESIGN AND IMPLEMENTATION OF A BASIC CROSS-COMPILER AND VIRTUAL MEMORY MANAGEMENT SYSTEM FOR THE TI - 59 PROGRAMMABLE CALCULATOR Mark R. Kindl Captain...Academy, 1974 The instruction set of the TI - 59 Programmable Calculator bears a close similarity to that of an assembler. Though most of the calculator

System for Suppressing Vibration in Turbomachine Components

NASA Technical Reports Server (NTRS)

Morrison, Carlos R. (Inventor); Provenza, Andrew J. (Inventor); Choi, Benjamin B. (Inventor); Bakhle, Milind A. (Inventor); Min, James B (Inventor); Stefko, George L. (Inventor); Kussmann, John A (Inventor); Fougere, Alan J (Inventor)

2013-01-01

Disclosed is a system for suppressing vibration and noise mitigation in structures such as blades in turbomachinery. The system includes flexible piezoelectric patches which are secured on or imbedded in turbomachinery blades which, in one embodiment, comprises eight (8) fan blades. The system further includes a capacitor plate coupler and a power transfer apparatus, which may both be arranged into one assembly, that respectively transfer data and power. Each of the capacitive plate coupler and power transfer apparatus is configured so that one part is attached to a fixed member while another part is attached to a rotatable member with an air gap there between. The system still further includes a processor that has 16 channels, eight of which serve as sensor channels, and the remaining eight, serving as actuation channels. The processor collects and analyzes the sensor signals and, in turn, outputs corrective signals for vibration/noise suppression of the turbine blades.

KSC01padig006

NASA Image and Video Library

2001-01-03

KENNEDY SPACE CENTER, Fla. -- Under wispy white morning clouds, Space Shuttle Atlantis approaches Launch Pad 39A, which shows the Rotating Service Structure open (left) and the Fixed Service Structure (right). At the RSS, the payload canister is being lifted up to the Payload Changeout Room. This is the Shuttle’s second attempt at rollout. Jan. 2 a failed computer processor on the crawler transporter aborted the rollout and the Shuttle was returned to the Vehicle Assembly Building using a secondary computer processor on the vehicle. Atlantis will fly on mission STS-98, the seventh construction flight to the International Space Station, carrying the U.S. Laboratory, named Destiny. The lab will have five system racks already installed inside the module. After delivery of electronics in the lab, electrically powered attitude control for Control Moment Gyroscopes will be activated. Atlantis is scheduled for launch no earlier than Jan. 19, 2001, with a crew of five

Demonstration program for Omega receiver prototype microcomputer data processing

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

The JOLT (TM) commercial microcomputer, based on the MOS Technology 6502 processor chip, for use in Omega navigation system is evaluated. A computer program was prepared in hand-assembled code to demonstrate receiver operation. The processor provides binary processing with interrupts enabled, a carriage return is given to initialize the teleprinter, and a jump is performed to enter the program loop to wait for an interrupt. The program loop operates continuously testing the interrupt flag. The interrupt routine reads the receiver status word and determines whether the current time-slot is the A slot. If so, the interrupt flag, which is also the data index pointer, is reset to zero. The status word is stored in the status buffer. If the time-slot is not A, the interrupt flag/pointer is incremented by one to index the phase and status to the proper buffer words for later use by the print routine.

Stress Corrosion Evaluation of Various Metallic Materials for the International Space Station Water Recycling System

NASA Technical Reports Server (NTRS)

Torres, P. D.

2015-01-01

A stress corrosion evaluation was performed on Inconel 625, Hastelloy C276, titanium commercially pure (TiCP), Ti-6Al-4V, Ti-6Al-4V extra low interstitial, and Cronidur 30 steel as a consequence of a change in formulation of the pretreatment for processing the urine in the International Space Station Environmental Control and Life Support System Urine Processing Assembly from a sulfuric acid-based to a phosphoric acid-based solution. The first five listed were found resistant to stress corrosion in the pretreatment and brine. However, some of the Cronidur 30 specimens experienced reduction in load-carrying ability.

Development of a preprototype vapor compression distillation water recovery subsystem

NASA Technical Reports Server (NTRS)

Johnson, K. L.

1978-01-01

The activities involved in the design, development, and test of a preprototype vapor compression distillation water recovery subsystem are described. This subsystem, part of a larger regenerative life support evaluation system, is designed to recover usable water from urine, urinal rinse water, and concentrated shower and laundry brine collected from three space vehicle crewmen for a period of 180 days without resupply. Details of preliminary design and testing as well as component developments are included. Trade studies, considerations leading to concept selections, problems encountered, and test data are also presented. The rework of existing hardware, subsystem development including computer programs, assembly verification, and comprehensive baseline test results are discussed.

Natural Deposition Strategy for Interfacial, Self-Assembled, Large-Scale, Densely Packed, Monolayer Film with Ligand-Exchanged Gold Nanorods for In Situ Surface-Enhanced Raman Scattering Drug Detection.

PubMed

Mao, Mei; Zhou, Binbin; Tang, Xianghu; Chen, Cheng; Ge, Meihong; Li, Pan; Huang, Xingjiu; Yang, Liangbao; Liu, Jinhuai

2018-03-15

Liquid interfacial self-assembly of metal nanoparticles holds great promise for its various applications, such as in tunable optical devices, plasmonics, sensors, and catalysis. However, the construction of large-area, ordered, anisotropic, nanoparticle monolayers and the acquisition of self-assembled interface films are still significant challenges. Herein, a rapid, validated method to fabricate large-scale, close-packed nanomaterials at the cyclohexane/water interface, in which hydrophilic cetyltrimethylammonium bromide coated nanoparticles and gold nanorods (AuNRs) self-assemble into densely packed 2D arrays by regulating the surface ligand and suitable inducer, is reported. Decorating AuNRs with polyvinylpyrrolidone not only extensively decreases the charge of AuNRs, but also diminishes repulsive forces. More importantly, a general, facile, novel technique to transfer an interfacial monolayer through a designed in situ reaction cell linked to a microfluidic chip is revealed. The self-assembled nanofilm can then automatically settle on the substrate and be directly detected in the reaction cell in situ by means of a portable Raman spectrometer. Moreover, a close-packed monolayer of self-assembled AuNRs provides massive, efficient hotspots to create great surface-enhanced Raman scattering (SERS) enhancement, which provides high sensitivity and reproducibility as the SERS-active substrate. Furthermore, this strategy was exploited to detect drug molecules in human urine for cyclohexane-extracted targets acting as the oil phase to form an oil/water interface. A portable Raman spectrometer was employed to detect methamphetamine down to 100 ppb levels in human urine, exhibiting excellent practicability. As a universal platform, handy tool, and fast pretreatment method with a good capability for drug detection in biological systems, this technique shows great promise for rapid, credible, and on-spot drug detection. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Implementation of a robotic flexible assembly system

NASA Technical Reports Server (NTRS)

Benton, Ronald C.

1987-01-01

As part of the Intelligent Task Automation program, a team developed enabling technologies for programmable, sensory controlled manipulation in unstructured environments. These technologies include 2-D/3-D vision sensing and understanding, force sensing and high speed force control, 2.5-D vision alignment and control, and multiple processor architectures. The subsequent design of a flexible, programmable, sensor controlled robotic assembly system for small electromechanical devices is described using these technologies and ongoing implementation and integration efforts. Using vision, the system picks parts dumped randomly in a tray. Using vision and force control, it performs high speed part mating, in-process monitoring/verification of expected results and autonomous recovery from some errors. It is programmed off line with semiautomatic action planning.

High-speed assembly language (80386/80387) programming for laser spectra scan control and data acquisition providing improved resolution water vapor spectroscopy

NASA Technical Reports Server (NTRS)

Allen, Robert J.

1988-01-01

An assembly language program using the Intel 80386 CPU and 80387 math co-processor chips was written to increase the speed of data gathering and processing, and provide control of a scanning CW ring dye laser system. This laser system is used in high resolution (better than 0.001 cm-1) water vapor spectroscopy experiments. Laser beam power is sensed at the input and output of white cells and the output of a Fabry-Perot. The assembly language subroutine is called from Basic, acquires the data and performs various calculations at rates greater than 150 faster than could be performed by the higher level language. The width of output control pulses generated in assembly language are 3 to 4 microsecs as compared to 2 to 3.7 millisecs for those generated in Basic (about 500 to 1000 times faster). Included are a block diagram and brief description of the spectroscopy experiment, a flow diagram of the Basic and assembly language programs, listing of the programs, scope photographs of the computer generated 5-volt pulses used for control and timing analysis, and representative water spectrum curves obtained using these programs.

Algorithms and Application of Sparse Matrix Assembly and Equation Solvers for Aeroacoustics

NASA Technical Reports Server (NTRS)

Watson, W. R.; Nguyen, D. T.; Reddy, C. J.; Vatsa, V. N.; Tang, W. H.

2001-01-01

An algorithm for symmetric sparse equation solutions on an unstructured grid is described. Efficient, sequential sparse algorithms for degree-of-freedom reordering, supernodes, symbolic/numerical factorization, and forward backward solution phases are reviewed. Three sparse algorithms for the generation and assembly of symmetric systems of matrix equations are presented. The accuracy and numerical performance of the sequential version of the sparse algorithms are evaluated over the frequency range of interest in a three-dimensional aeroacoustics application. Results show that the solver solutions are accurate using a discretization of 12 points per wavelength. Results also show that the first assembly algorithm is impractical for high-frequency noise calculations. The second and third assembly algorithms have nearly equal performance at low values of source frequencies, but at higher values of source frequencies the third algorithm saves CPU time and RAM. The CPU time and the RAM required by the second and third assembly algorithms are two orders of magnitude smaller than that required by the sparse equation solver. A sequential version of these sparse algorithms can, therefore, be conveniently incorporated into a substructuring for domain decomposition formulation to achieve parallel computation, where different substructures are handles by different parallel processors.

DSS command software update

NASA Technical Reports Server (NTRS)

Stinnett, W. G.

1980-01-01

The modifications, additions, and testing results for a version of the Deep Space Station command software, generated for support of the Voyager Saturn encounter, are discussed. The software update requirements included efforts to: (1) recode portions of the software to permit recovery of approximately 2000 words of memory; (2) correct five Voyager Ground data System liens; (3) provide capability to automatically turn off the command processor assembly local printer during periods of low activity; and (4) correct anomalies existing in the software.

Elan4/SPARC V9 Cross Loader and Dynamic Linker

DOE Office of Scientific and Technical Information (OSTI.GOV)

anf Fabien Lebaillif-Delamare, Fabrizio Petrini

2004-10-25

The Elan4/Sparc V9 Croos Loader and Liner is a part of the Linux system software that allows the dynamic loading and linking of user code in the network interface Quadrics QsNETII, also called as Elan4 Quadrics. Elan44 uses a thread processor that is based on the assembly instruction set of the Sparc V9. All this software is integrated as a Linux kernel module in the Linux 2.6.5 release.

Initial Kernel Timing Using a Simple PIM Performance Model

NASA Technical Reports Server (NTRS)

Katz, Daniel S.; Block, Gary L.; Springer, Paul L.; Sterling, Thomas; Brockman, Jay B.; Callahan, David

2005-01-01

This presentation will describe some initial results of paper-and-pencil studies of 4 or 5 application kernels applied to a processor-in-memory (PIM) system roughly similar to the Cascade Lightweight Processor (LWP). The application kernels are: * Linked list traversal * Sun of leaf nodes on a tree * Bitonic sort * Vector sum * Gaussian elimination The intent of this work is to guide and validate work on the Cascade project in the areas of compilers, simulators, and languages. We will first discuss the generic PIM structure. Then, we will explain the concepts needed to program a parallel PIM system (locality, threads, parcels). Next, we will present a simple PIM performance model that will be used in the remainder of the presentation. For each kernel, we will then present a set of codes, including codes for a single PIM node, and codes for multiple PIM nodes that move data to threads and move threads to data. These codes are written at a fairly low level, between assembly and C, but much closer to C than to assembly. For each code, we will present some hand-drafted timing forecasts, based on the simple PIM performance model. Finally, we will conclude by discussing what we have learned from this work, including what programming styles seem to work best, from the point-of-view of both expressiveness and performance.

Enhancing quality practice for prevention and diagnosis of urinary tract infection during inpatient spinal cord rehabilitation.

PubMed

Alavinia, Seyed Mohammad; Omidvar, Maryam; Farahani, Farnoosh; Bayley, Mark; Zee, Joana; Craven, Beverley Catharine

2017-11-01

To reduce the incidence of Urinary Tract Infection (UTI) in subacute SCI individuals admitted for tertiary inpatient rehabilitation. A quality improvement team was assembled to improve UTI prevention/diagnosis. To plan data collection, UTI-related factors were mapped in an Ishikawa (fishbone) driver diagram. Data including patient demographics, presence and frequency of signs and/or symptoms of UTI and antibiotic initiation from August to December 2015 were recorded. Sensitivity, Specificity, Positive and Negative Predictive Values (PPV, NPV), and Likelihood Ratios (LR) were calculated for each sign and symptom. Tertiary SCI Rehabilitation Results: Among 55 inpatients with subacute SCI who had signs/symptoms prompting urine culture and sensitivity (C&S), 32 (58.18%) were diagnosed with a UTI. The most frequent symptoms were foul smelling urine (41%), change in urine color (31%), and incontinence (25%), and the most common sign was fever (34%). Most UTIs (81%) occurred among individuals using Clean Intermittent Catheterization (CIC), with 46% of catheterizations performed by nurses. Foul smelling urine had the highest sensitivity (0.50, 95% CI: 0.31-0.69), and new incontinence had the highest specificity (0.88, 95% CI: 0.69-0.97) for UTI diagnosis. The highest PPV belonged to the cloudy urine (0.71, 95% CI: 0.42-0.92). The combination of cloudy and foul smelling urine increased the PPV to 78% (95% CI: (0.40-0.97). The concurrent presence of cloudy and foul smelling urine is predicted of UTI diagnosis inpatients tertiary setting. SCI inpatients are susceptible to UTI when learning CIC technique from nurses.

UPA Fill Drain Valve Modification kit installation

NASA Image and Video Library

2016-01-25

ISS046e023885 (01/25/2016) --- NASA astronaut Tim Kopra performs regular maintenance on the Urine Processing Assembly (UPA) aboard the International Space Station. The UPA is used by the crew to recycle water for use on the station. The image shows Tim replacing the brine filter from the UPA Fill Drain Valve enclosure.

The Brain's Router: A Cortical Network Model of Serial Processing in the Primate Brain

PubMed Central

Zylberberg, Ariel; Fernández Slezak, Diego; Roelfsema, Pieter R.; Dehaene, Stanislas; Sigman, Mariano

2010-01-01

The human brain efficiently solves certain operations such as object recognition and categorization through a massively parallel network of dedicated processors. However, human cognition also relies on the ability to perform an arbitrarily large set of tasks by flexibly recombining different processors into a novel chain. This flexibility comes at the cost of a severe slowing down and a seriality of operations (100–500 ms per step). A limit on parallel processing is demonstrated in experimental setups such as the psychological refractory period (PRP) and the attentional blink (AB) in which the processing of an element either significantly delays (PRP) or impedes conscious access (AB) of a second, rapidly presented element. Here we present a spiking-neuron implementation of a cognitive architecture where a large number of local parallel processors assemble together to produce goal-driven behavior. The precise mapping of incoming sensory stimuli onto motor representations relies on a “router” network capable of flexibly interconnecting processors and rapidly changing its configuration from one task to another. Simulations show that, when presented with dual-task stimuli, the network exhibits parallel processing at peripheral sensory levels, a memory buffer capable of keeping the result of sensory processing on hold, and a slow serial performance at the router stage, resulting in a performance bottleneck. The network captures the detailed dynamics of human behavior during dual-task-performance, including both mean RTs and RT distributions, and establishes concrete predictions on neuronal dynamics during dual-task experiments in humans and non-human primates. PMID:20442869

Mass balances for a biological life support system simulation model

NASA Technical Reports Server (NTRS)

Volk, Tyler; Rummel, John D.

1987-01-01

Design decisions to aid the development of future space based biological life support systems (BLSS) can be made with simulation models. The biochemistry stoichiometry was developed for: (1) protein, carbohydrate, fat, fiber, and lignin production in the edible and inedible parts of plants; (2) food consumption and production of organic solids in urine, feces, and wash water by the humans; and (3) operation of the waste processor. Flux values for all components are derived for a steady state system with wheat as the sole food source. The large scale dynamics of a materially closed (BLSS) computer model is described in a companion paper. An extension of this methodology can explore multifood systems and more complex biochemical dynamics while maintaining whole system closure as a focus.

LANDSAT-2 and LANDSAT-3 Flight evaluation report

NASA Technical Reports Server (NTRS)

Winchester, T. W.

1978-01-01

Flight performance analysis of LANDSAT 2 and LANDSAT 3 are presented for the period July 1978 to October 1978. Spacecraft operations and orbital parameters are summarized for each spacecraft. Data are provided on the performance and operation of the following subsystems onboard the spacecraft: power; attitude control; command/clock; telemetry; orbit adjust; magnetic moment compensating assembly; unified S band/premodulation processor; electrical interface; thermal narrowband tape recorders; wideband telemetry; attitude measurement sensor; wideband video tape recorders; return beam vidicon; multispectral scanner subsystem; and data collections.

Function algorithms for MPP scientific subroutines, volume 1

NASA Technical Reports Server (NTRS)

Gouch, J. G.

1984-01-01

Design documentation and user documentation for function algorithms for the Massively Parallel Processor (MPP) are presented. The contract specifies development of MPP assembler instructions to perform the following functions: natural logarithm; exponential (e to the x power); square root; sine; cosine; and arctangent. To fulfill the requirements of the contract, parallel array and solar implementations for these functions were developed on the PDP11/34 Program Development and Management Unit (PDMU) that is resident at the MPP testbed installation located at the NASA Goddard facility.

The high energy astronomy observatories

NASA Technical Reports Server (NTRS)

Neighbors, A. K.; Doolittle, R. F.; Halpers, R. E.

1977-01-01

The forthcoming NASA project of orbiting High Energy Astronomy Observatories (HEAO's) designed to probe the universe by tracing celestial radiations and particles is outlined. Solutions to engineering problems concerning HEAO's which are integrated, yet built to function independently are discussed, including the onboard digital processor, mirror assembly and the thermal shield. The principle of maximal efficiency with minimal cost and the potential capability of the project to provide explanations to black holes, pulsars and gamma-ray bursts are also stressed. The first satellite is scheduled for launch in April 1977.

Results of the Alternative Water Processor Test, A Novel Technology for Exploration Wastewater Remediation

NASA Technical Reports Server (NTRS)

Vega, Leticia; Meyer, Caitlin

2016-01-01

Biologically-based water recovery systems are a regenerative, low energy alternative to physiochemical processes to reclaim water from wastewater. This paper summarizes the results of the Alternative Water Processor (AWP) test conducted over one year. The AWP recovered 90% of water from four crewmembers using (4) membrane aerated bioreactors (MABRs) to remove carbon and nitrogen from an exploration mission wastewater, including urine, hygiene, laundry and humidity condensate. Downstream, a coupled forward and reverse osmosis system removed large organics and inorganic salts from the biological system effluent. The system exceeded the overall objectives of the test by recovering 90% of the influent wastewater processed and a 29% reduction of consumables from the current state of the art water recovery system on the International Space Station (ISS). However the biological system fell short of its test goals, failing to remove 75% and 90% of the influent ammonium and organic carbon, respectively. Despite not meeting its test goals, the BWP demonstrated the feasibility of an attached-growth biological system for simultaneous nitrification and denitrification, an innovative, volume and consumable-saving design that doesn't require toxic pretreatment. This paper will explain the reasons for this and will discuss steps to optimize each subsystem to increase effluent quality from the MABRs and the FOST to advance the system.

Results of the Alternative Water Processor Test, A Novel Technology for Exploration Wastewater Remediation

NASA Technical Reports Server (NTRS)

Vega, Leticia; Meyer, Caitlin

2015-01-01

Biologically-based water recovery systems are a regenerative, low energy alternative to physiochemical processes to reclaim water from wastewater. This paper summarizes the results of the Alternative Water Processor (AWP) test conducted over one year. The AWP recovered 90% of water from four crewmembers using (4) membrane aerated bioreactors (MABRs) to remove carbon and nitrogen from an exploration mission wastewater, including urine, hygiene, laundry and humidity condensate. Downstream, a coupled forward and reverse osmosis system removed large organics and inorganic salts from the biological system effluent. The system exceeded the overall objectives of the test by recovering 90% of the influent wastewater processed and a 29% reduction of consumables from the current state of the art water recovery system on the International Space Station (ISS). However the biological system fell short of its test goals, failing to remove 75% and 90% of the influent ammonium and organic carbon, respectively. Despite not meeting its test goals, the BWP demonstrated the feasibility of an attachedgrowth biological system for simultaneous nitrification and denitrification, an innovative, volume and consumable-saving design that doesn't require toxic pretreatment. This paper will explain the reasons for this and will discuss steps to optimize each subsystem to increase effluent quality from the MABRs and the FOST to advance the system.

Human Urine Decreases Function and Expression of Type 1 Pili in Uropathogenic Escherichia coli

PubMed Central

Greene, Sarah E.; Hibbing, Michael E.; Janetka, James; Chen, Swaine L.

2015-01-01

ABSTRACT Uropathogenic Escherichia coli (UPEC) is the primary cause of community-acquired urinary tract infections (UTIs). UPEC bind the bladder using type 1 pili, encoded by the fim operon in nearly all E. coli. Assembled type 1 pili terminate in the FimH adhesin, which specifically binds to mannosylated glycoproteins on the bladder epithelium. Expression of type 1 pili is regulated in part by phase-variable inversion of the genomic element containing the fimS promoter, resulting in phase ON (expressing) and OFF (nonexpressing) orientations. Type 1 pili are essential for virulence in murine models of UTI; however, studies of urine samples from human UTI patients demonstrate variable expression of type 1 pili. We provide insight into this paradox by showing that human urine specifically inhibits both expression and function of type 1 pili. Growth in urine induces the fimS phase OFF orientation, preventing fim expression. Urine also contains inhibitors of FimH function, and this inhibition leads to a further bias in fimS orientation toward the phase OFF state. The dual effect of urine on fimS regulation and FimH binding presents a potential barrier to type 1 pilus-mediated colonization and invasion of the bladder epithelium. However, FimH-mediated attachment to human bladder cells during growth in urine reverses these effects such that fim expression remains ON and/or turns ON. Interestingly, FimH inhibitors called mannosides also induce the fimS phase OFF orientation. Thus, the transduction of FimH protein attachment or inhibition into epigenetic regulation of type 1 pilus expression has important implications for the development of therapeutics targeting FimH function. PMID:26126855

Test Program of the "Combined Data and Power Management Infrastructure"

NASA Astrophysics Data System (ADS)

Eickhoff, Jens; Fritz, Michael; Witt, Rouven; Bucher, Nico; Roser, Hans-Peter

2013-08-01

As already published in previous DASIA papers, the University of Stuttgart, Germany, is developing an advanced 3-axis stabilized small satellite applying industry standards for command/control techniques and Onboard Software design. This satellite furthermore features an innovative hybrid architecture of Onboard Computer and Power Control and Distribution Unit. One of the main challenges was the development of an ultra-compact and performing Onboard Computer (OBC), which was intended to support an RTEMS operating system, a PUS standard based Onboard Software (OBSW) and CCSDS standard based ground/space communication. The developed architecture (see [1, 2, 3]) is called a “Combined Onboard Data and Power Management Infrastructure” - CDPI. It features: The OBC processor boards based on a LEON3FT architecture - from Aeroflex Inc., USA The I/O Boards for all OBC digital interfaces to S/C equipment (digital RIU) - from 4Links Ltd. UK CCSDS TC/TM decoder/encoder boards - with same HW design as I/O boards - just with limited number of interfaces. HW from 4Links Ltd, UK, driver SW and IP-Core from Aeroflex Gaisler, SE Analog RIU functions via enhanced PCDU from Vectronic Aerospace, D OBC reconfiguration unit functions via Common Controller - here in PCDU [4] The CDPI overall assembly is meanwhile complete and a exhaustive description can be found in [5]. The EM test campaign including the HW/SW compatibility testing is finalized. This comprises all OBC EM units, OBC EM assembly and the EM PCDU. The unit test program for the FM Processor-Boards and Power-Boards of the OBC are completed and the unit tests of FM I/O-Boards and CCSDS-Boards have been completed by 4Links at the assembly house. The subsystem tests of the assembled OBC also are completed and the overall System tests of the CDPI with system reconfiguration in diverse possible FDIR cases also reach the last steps. Still ongoing is the subsequent integration of the CDPI with the satellite's avionics components encompassing TTC, AOCS, Power and Payload Control. This paper provides a full picture of the test campaign. Further details can be taken from

Development of an Ion Thruster and Power Processor for New Millennium's Deep Space 1 Mission

NASA Technical Reports Server (NTRS)

Sovey, James S.; Hamley, John A.; Haag, Thomas W.; Patterson, Michael J.; Pencil, Eric J.; Peterson, Todd T.; Pinero, Luis R.; Power, John L.; Rawlin, Vincent K.; Sarmiento, Charles J.;

The Fermilab lattice supercomputer project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fischler, M.; Atac, R.; Cook, A.

1989-02-01

The ACPMAPS system is a highly cost effective, local memory MIMD computer targeted at algorithm development and production running for gauge theory on the lattice. The machine consists of a compound hypercube of crates, each of which is a full crossbar switch containing several processors. The processing nodes are single board array processors based on the Weitek XL chip set, each with a peak power of 20 MFLOPS and supported by 8 MBytes of data memory. The system currently being assembled has a peak power of 5 GFLOPS, delivering performance at approximately $250/MFLOP. The system is programmable in C andmore » Fortran. An underpinning of software routines (CANOPY) provides an easy and natural way of coding lattice problems, such that the details of parallelism, and communication and system architecture are transparent to the user. CANOPY can easily be ported to any single CPU or MIMD system which supports C, and allows the coding of typical applications with very little effort. 3 refs., 1 fig.« less

Performance tuning of N-body codes on modern microprocessors: I. Direct integration with a hermite scheme on x86_64 architecture

NASA Astrophysics Data System (ADS)

Nitadori, Keigo; Makino, Junichiro; Hut, Piet

2006-12-01

The main performance bottleneck of gravitational N-body codes is the force calculation between two particles. We have succeeded in speeding up this pair-wise force calculation by factors between 2 and 10, depending on the code and the processor on which the code is run. These speed-ups were obtained by writing highly fine-tuned code for x86_64 microprocessors. Any existing N-body code, running on these chips, can easily incorporate our assembly code programs. In the current paper, we present an outline of our overall approach, which we illustrate with one specific example: the use of a Hermite scheme for a direct N2 type integration on a single 2.0 GHz Athlon 64 processor, for which we obtain an effective performance of 4.05 Gflops, for double-precision accuracy. In subsequent papers, we will discuss other variations, including the combinations of N log N codes, single-precision implementations, and performance on other microprocessors.

Automatic maintenance payload on board of a Mexican LEO microsatellite

NASA Astrophysics Data System (ADS)

Vicente-Vivas, Esaú; García-Nocetti, Fabián; Mendieta-Jiménez, Francisco

2006-02-01

Few research institutions from Mexico work together to finalize the integration of a technological demonstration microsatellite called Satex, aiming the launching of the first ever fully designed and manufactured domestic space vehicle. The project is based on technical knowledge gained in previous space experiences, particularly in developing GASCAN automatic experiments for NASA's space shuttle, and in some support obtained from the local team which assembled the México-OSCAR-30 microsatellites. Satex includes three autonomous payloads and a power subsystem, each one with a local microcomputer to provide intelligent and dedicated control. It also contains a flight computer (FC) with a pair of full redundancies. This enables the remote maintenance of processing boards from the ground station. A fourth communications payload depends on the flight computer for control purposes. A fifth payload was decided to be developed for the satellite. It adds value to the available on-board computers and extends the opportunity for a developing country to learn and to generate domestic space technology. Its aim is to provide automatic maintenance capabilities for the most critical on-board computer in order to achieve continuous satellite operations. This paper presents the virtual computer architecture specially developed to provide maintenance capabilities to the flight computer. The architecture is periodically implemented by software with a small amount of physical processors (FC processors) and virtual redundancies (payload processors) to emulate a hybrid redundancy computer. Communications among processors are accomplished over a fault-tolerant LAN. This allows a versatile operating behavior in terms of data communication as well as in terms of distributed fault tolerance. Obtained results, payload validation and reliability results are also presented.

Development Of A Three-Dimensional Circuit Integration Technology And Computer Architecture

NASA Astrophysics Data System (ADS)

Etchells, R. D.; Grinberg, J.; Nudd, G. R.

1981-12-01

This paper is the first of a series 1,2,3 describing a range of efforts at Hughes Research Laboratories, which are collectively referred to as "Three-Dimensional Microelectronics." The technology being developed is a combination of a unique circuit fabrication/packaging technology and a novel processing architecture. The packaging technology greatly reduces the parasitic impedances associated with signal-routing in complex VLSI structures, while simultaneously allowing circuit densities orders of magnitude higher than the current state-of-the-art. When combined with the 3-D processor architecture, the resulting machine exhibits a one- to two-order of magnitude simultaneous improvement over current state-of-the-art machines in the three areas of processing speed, power consumption, and physical volume. The 3-D architecture is essentially that commonly referred to as a "cellular array", with the ultimate implementation having as many as 512 x 512 processors working in parallel. The three-dimensional nature of the assembled machine arises from the fact that the chips containing the active circuitry of the processor are stacked on top of each other. In this structure, electrical signals are passed vertically through the chips via thermomigrated aluminum feedthroughs. Signals are passed between adjacent chips by micro-interconnects. This discussion presents a broad view of the total effort, as well as a more detailed treatment of the fabrication and packaging technologies themselves. The results of performance simulations of the completed 3-D processor executing a variety of algorithms are also presented. Of particular pertinence to the interests of the focal-plane array community is the simulation of the UNICORNS nonuniformity correction algorithms as executed by the 3-D architecture.

Petascale self-consistent electromagnetic computations using scalable and accurate algorithms for complex structures

NASA Astrophysics Data System (ADS)

Cary, John R.; Abell, D.; Amundson, J.; Bruhwiler, D. L.; Busby, R.; Carlsson, J. A.; Dimitrov, D. A.; Kashdan, E.; Messmer, P.; Nieter, C.; Smithe, D. N.; Spentzouris, P.; Stoltz, P.; Trines, R. M.; Wang, H.; Werner, G. R.

2006-09-01

As the size and cost of particle accelerators escalate, high-performance computing plays an increasingly important role; optimization through accurate, detailed computermodeling increases performance and reduces costs. But consequently, computer simulations face enormous challenges. Early approximation methods, such as expansions in distance from the design orbit, were unable to supply detailed accurate results, such as in the computation of wake fields in complex cavities. Since the advent of message-passing supercomputers with thousands of processors, earlier approximations are no longer necessary, and it is now possible to compute wake fields, the effects of dampers, and self-consistent dynamics in cavities accurately. In this environment, the focus has shifted towards the development and implementation of algorithms that scale to large numbers of processors. So-called charge-conserving algorithms evolve the electromagnetic fields without the need for any global solves (which are difficult to scale up to many processors). Using cut-cell (or embedded) boundaries, these algorithms can simulate the fields in complex accelerator cavities with curved walls. New implicit algorithms, which are stable for any time-step, conserve charge as well, allowing faster simulation of structures with details small compared to the characteristic wavelength. These algorithmic and computational advances have been implemented in the VORPAL7 Framework, a flexible, object-oriented, massively parallel computational application that allows run-time assembly of algorithms and objects, thus composing an application on the fly.

GaAs Supercomputing: Architecture, Language, And Algorithms For Image Processing

NASA Astrophysics Data System (ADS)

Johl, John T.; Baker, Nick C.

1988-10-01

The application of high-speed GaAs processors in a parallel system matches the demanding computational requirements of image processing. The architecture of the McDonnell Douglas Astronautics Company (MDAC) vector processor is described along with the algorithms and language translator. Most image and signal processing algorithms can utilize parallel processing and show a significant performance improvement over sequential versions. The parallelization performed by this system is within each vector instruction. Since each vector has many elements, each requiring some computation, useful concurrent arithmetic operations can easily be performed. Balancing the memory bandwidth with the computation rate of the processors is an important design consideration for high efficiency and utilization. The architecture features a bus-based execution unit consisting of four to eight 32-bit GaAs RISC microprocessors running at a 200 MHz clock rate for a peak performance of 1.6 BOPS. The execution unit is connected to a vector memory with three buses capable of transferring two input words and one output word every 10 nsec. The address generators inside the vector memory perform different vector addressing modes and feed the data to the execution unit. The functions discussed in this paper include basic MATRIX OPERATIONS, 2-D SPATIAL CONVOLUTION, HISTOGRAM, and FFT. For each of these algorithms, assembly language programs were run on a behavioral model of the system to obtain performance figures.

A personal computer-based, multitasking data acquisition system

NASA Technical Reports Server (NTRS)

Bailey, Steven A.

1990-01-01

A multitasking, data acquisition system was written to simultaneously collect meteorological radar and telemetry data from two sources. This system is based on the personal computer architecture. Data is collected via two asynchronous serial ports and is deposited to disk. The system is written in both the C programming language and assembler. It consists of three parts: a multitasking kernel for data collection, a shell with pull down windows as user interface, and a graphics processor for editing data and creating coded messages. An explanation of both system principles and program structure is presented.

FTIR spectrometer with solid-state drive system

DOEpatents

Rajic, Slobodan; Seals, Roland D.; Egert, Charles M.

1999-01-01

An FTIR spectrometer (10) and method using a solid-state drive system with thermally responsive members (27) that are subject to expansion upon heating and to contraction upon cooling. Such members (27) are assembled in the device (10) so as to move an angled, reflective surface (22) a small distance. The sample light beam (13) is received at a detector (24) along with a reference light beam (13) and there it is combined into a resulting signal. This allows the "interference" between the two beams to occur for spectral analysis by a processor (29).

Software for System for Controlling a Magnetically Levitated Rotor

NASA Technical Reports Server (NTRS)

Morrison, Carlos R. (Inventor)

2004-01-01

In a rotor assembly having a rotor supported for rotation by magnetic bearings, a processor controlled by software or firmware controls the generation of force vectors that position the rotor relative to its bearings in a 'bounce' mode in which the rotor axis is displaced from the principal axis defined between the bearings and a 'tilt' mode in which the rotor axis is tilted or inclined relative to the principal axis. Waveform driven perturbations are introduced to generate force vectors that excite the rotor in either the 'bounce' or 'tilt' modes.

Landsat-1 and Landsat-2 evaluation report, 23 January 1975 to 23 April 1975

NASA Technical Reports Server (NTRS)

1975-01-01

A description of the work accomplished with the Landsat-1 and Landsat-2 satellites during the period 23 Jan. - 23 Apr. 1975 was presented. The following information was given for each satellite: operational summary, orbital parameters, power subsystem, attitude control subsystem, command/clock subsystem, telemetry subsystem, orbit adjust subsystem, magnetic moment compensating assembly, unified S-band/premodulation processor, electrical interface subsystem, thermal subsystem, narrowband tape recorders, wideband telemetry subsystem, attitude measurement sensor, wideband video tape recorders, return beam vidicon, multispectral scanner subsystem, and data collection subsystem.

System for Controlling a Magnetically Levitated Rotor

NASA Technical Reports Server (NTRS)

Morrison, Carlos R. (Inventor)

2006-01-01

In a rotor assembly having a rotor supported for rotation by magnetic bearings, a processor controlled by software or firmware controls the generation of force vectors that position the rotor relative to its bearings in a "bounce" mode in which the rotor axis is displaced from the principal axis defined between the bearings and a "tilt" mode in which the rotor axis is tilted or inclined relative to the principal axis. Waveform driven perturbations are introduced to generate force vectors that excite the rotor in either the "bounce" or "tilt" modes.

TRACALS Evaluation Report. Initial Evaluation Report (AN/GPN-24) Nellis AFB, Nevada, 10 December 1979-6 Mar 1980.

DTIC Science & Technology

1980-05-16

Scott AFB, IL 62225 1 1842 EEG /EEIT, Scott AFB, IL 62225 1 1843 EES/EIELT, H-ickam AFB, H-I 96853 1 1844 EES/EIELT, Griffiss AFB, NY 13441 I HQ AFCC/DAPL...Time Control TDC Target Data Computer TO Technical Order TRACALS Traffic Cortrol and Landing Systems TSDA Transfer Switch Drawer Assembly TWT Traveling...the designated targets. The error detector outputs are fed to the TDC to update the beam position data during the next track interval. (b) Processor

Portable kit for identification and detection of drugs in human urine using surface-enhanced Raman spectroscopy.

PubMed

Han, Zhenzhen; Liu, Honglin; Meng, Juan; Yang, Liangbao; Liu, Jing; Liu, Jinhuai

2015-09-15

A portable kit was demonstrated for rapid and reliable surface-enhanced Raman scattering (SERS) detection of drugs in human urine. This kit contains two sealed reagent tubes, a packet of standardized SERS substrates, and a mini Raman device. A 3 min pretreatment for separating amphetamines from human urine was developed with an extraction rate of >80% examined by ultraperformance liquid chromatography (UPLC). Simultaneously, highly reproducible two-dimensional (2D) gold nanorod (GNR) arrays were assembled by the use of methoxymercaptopoly(ethylene glycol) (mPEG-SH) capping. Thirty batches of GNR arrays produced the 1001 cm(-1) intensity of methamphetamine (MA) molecules with a relative standard deviation (RSD) of 7.9%, and a 21 × 21 μm(2) area mapping on a 2D GNR array produced a statistical RSD of <10%, implying an excellent reproducibility and uniformity. The detection limit of amphetamines in human urine was at least 0.1 ppm. Moreover, the portable kit was successfully used for detecting MA, 3,4-methylenedioxymethamphetamine (MDMA), and methcathinone (MC) in 30 volunteers' urine samples with various clinical natures, and the dual-analyte detection of MA and MDMA implied a good capability of multiplex analysis. UPLC examination and the SERS recovery test clearly indicated that our pretreatment procedure was sufficient to lower the high background signals caused by complex components in urine and demonstrated the practicability and the resistance to false positives, which is a vital problem for law enforcement applications. The excellent performance of our portable kit promises a great prospective toward a rapid, reliable, and on-spot analyzer, especially for public safety and healthcare.

Airborne Optical Communications Demonstrator Design And Preflight Test Results

NASA Technical Reports Server (NTRS)

Biswas, Abhijit; Page, N.; Neal, J.; Zhu, D.; Wright, M.; Ovtiz, G.; Farr, W. H.; Hernnzati, H.

2005-01-01

A second generation optical communications demonstrator (OCD-2) intended for airborne applications like air-to-ground and air-to-air optical links is under development at JPL. This development provides the capability for unidirectional high data rate (2.5-Gbps) transmission at 1550-nm, with the ability to receive an 810-nm beacon to aid acquisition pointing and tracking. The transmitted beam width is nominally 200-(micro)rad. A 3x3 degree coarse field-of-view (FOV) acquisition sensor with a much smaller 3-mrad FOV tracking sensor is incorporated. The OCD-2 optical head will be integrated to a high performance gimbal turret assembly capable of providing pointing stability of 5- microradians from an airborne platform. Other parts of OCD-2 include a cable harness, connecting the optical head in the gimbal turret assembly to a rugged electronics box. The electronics box will house: command and control processors, laser transmitter, data-generation-electronics, power conversion/distribution hardware and state-of-health monitors. The entire assembly will be integrated and laboratory tested prior to a planned flight demonstrations.

Power estimation on functional level for programmable processors

NASA Astrophysics Data System (ADS)

Schneider, M.; Blume, H.; Noll, T. G.

2004-05-01

In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input parameters of the Correspondence to: H. Blume (blume@eecs.rwth-aachen.de) arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved.

GPS Block 2R Time Standard Assembly (TSA) architecture

NASA Technical Reports Server (NTRS)

Baker, Anthony P.

1990-01-01

The underlying philosophy of the Global Positioning System (GPS) 2R Time Standard Assembly (TSA) architecture is to utilize two frequency sources, one fixed frequency reference source and one system frequency source, and to couple the system frequency source to the reference frequency source via a sample data loop. The system source is used to provide the basic clock frequency and timing for the space vehicle (SV) and it uses a voltage controlled crystal oscillator (VCXO) with high short term stability. The reference source is an atomic frequency standard (AFS) with high long term stability. The architecture can support any type of frequency standard. In the system design rubidium, cesium, and H2 masers outputting a canonical frequency were accommodated. The architecture is software intensive. All VCXO adjustments are digital and are calculated by a processor. They are applied to the VCXO via a digital to analog converter.

Control of a Glove-Based Grasp Assist Device

NASA Technical Reports Server (NTRS)

Bergelin, Bryan J (Inventor); Ihrke, Chris A. (Inventor); Davis, Donald R. (Inventor); Linn, Douglas Martin (Inventor); Sanders, Adam M (Inventor); Askew, R. Scott (Inventor); Laske, Evan (Inventor); Ensley, Kody (Inventor)

2015-01-01

A grasp assist system includes a glove and sleeve. The glove includes a digit, i.e., a finger or thumb, and a force sensor. The sensor measures a grasping force applied to an object by an operator wearing the glove. The glove contains a tendon connected at a first end to the digit. The sleeve has an actuator assembly connected to a second end of the tendon and a controller in communication with the sensor. The controller includes a configuration module having selectable operating modes and a processor that calculates a tensile force to apply to the tendon for each of the selectable operating modes to assist the grasping force in a manner that differs for each of the operating modes. A method includes measuring the grasping force, selecting the mode, calculating the tensile force, and applying the tensile force to the tendon using the actuator assembly.

Conference on Real-Time Computer Applications in Nuclear, Particle and Plasma Physics, 6th, Williamsburg, VA, May 15-19, 1989, Proceedings

NASA Technical Reports Server (NTRS)

Pordes, Ruth (Editor)

1989-01-01

Papers on real-time computer applications in nuclear, particle, and plasma physics are presented, covering topics such as expert systems tactics in testing FASTBUS segment interconnect modules, trigger control in a high energy physcis experiment, the FASTBUS read-out system for the Aleph time projection chamber, a multiprocessor data acquisition systems, DAQ software architecture for Aleph, a VME multiprocessor system for plasma control at the JT-60 upgrade, and a multiasking, multisinked, multiprocessor data acquisition front end. Other topics include real-time data reduction using a microVAX processor, a transputer based coprocessor for VEDAS, simulation of a macropipelined multi-CPU event processor for use in FASTBUS, a distributed VME control system for the LISA superconducting Linac, a distributed system for laboratory process automation, and a distributed system for laboratory process automation. Additional topics include a structure macro assembler for the event handler, a data acquisition and control system for Thomson scattering on ATF, remote procedure execution software for distributed systems, and a PC-based graphic display real-time particle beam uniformity.

Bottom-up construction of artificial molecules for superconducting quantum processors

NASA Astrophysics Data System (ADS)

Poletto, Stefano; Rigetti, Chad; Gambetta, Jay M.; Merkel, Seth; Chow, Jerry M.; Corcoles, Antonio D.; Smolin, John A.; Rozen, Jim R.; Keefe, George A.; Rothwell, Mary B.; Ketchen, Mark B.; Steffen, Matthias

2012-02-01

Recent experiments on transmon qubits capacitively coupled to superconducting 3-dimensional cavities have shown coherence times much longer than transmons coupled to more traditional planar resonators. For the implementation of a quantum processor this approach has clear advantages over traditional techniques but it poses the challenge of scalability. We are currently implementing multi-qubits experiments based on a bottom-up scaling approach. First, transmon qubits are fabricated on individual chips and are independently characterized. Second, an artificial molecule is assembled by selecting a particular set of previously characterized single-transmon chips. We present recent data on a two-qubit artificial molecule constructed in this way. The two qubits are chosen to generate a strong Z-Z interaction by matching the 0-1 transition energy of one qubit with the 1-2 transition of the other. Single qubit manipulations and state tomography cannot be done with ``traditional'' single tone microwave pulses but instead specifically shaped pulses have to be simultaneously applied on both qubits. Coherence times, coupling strength, and optimal pulses for decoupling the two qubits and perform state tomography are presented

Biomedical engineering tasks. [electrode development for electrocardiography and electroencephalography

NASA Technical Reports Server (NTRS)

1972-01-01

Electrocardiographic and vectorcardiographic bioinstrumentation work centered on the development of a new electrode system harness for Project Skylab. Evaluation of several silver electrode configurations proved superior impedance voltage performance for silver/silver chloride electrodes mounted flush by using a paste adhesive. A portable ECG processor has been designed and a breadboard unit has been built to sample ECG input data at a rate of 500 samples per second for arrhythmia detection. A small real time display driver program has been developed for statistical analysis on selected QPS features. Engineering work on a sleep monitoring cap assembly continued.

IMAC fractionation in combination with LC-MS reveals H2B and NIF-1 peptides as potential bladder cancer biomarkers.

PubMed

Frantzi, Maria; Zoidakis, Jerome; Papadopoulos, Theofilos; Zürbig, Petra; Katafigiotis, Ioannis; Stravodimos, Konstantinos; Lazaris, Andreas; Giannopoulou, Ioanna; Ploumidis, Achilles; Mischak, Harald; Mullen, William; Vlahou, Antonia

2013-09-06

Improvement in bladder cancer (BC) management requires more effective diagnosis and prognosis of disease recurrence and progression. Urinary biomarkers attract special interest because of the noninvasive means of urine collection. Proteomic analysis of urine entails the adoption of a fractionation methodology to reduce sample complexity. In this study, we applied immobilized metal affinity chromatography in combination with high-resolution LC-MS/MS for the discovery of native urinary peptides potentially associated with BC aggressiveness. This approach was employed toward urine samples from patients with invasive BC, noninvasive BC, and benign urogenital diseases. A total of 1845 peptides were identified, corresponding to a total of 638 precursor proteins. Specific enrichment for proteins involved in nucleosome assembly and for zinc-finger transcription factors was observed. The differential expression of two candidate biomarkers, histone H2B and NIF-1 (zinc finger 335) in BC, was verified in independent sets of urine samples by ELISA and by immunohistochemical analysis of BC tissue. The results collectively support changes in the expression of both of these proteins with tumor progression, suggesting their potential role as markers for discriminating BC stages. In addition, the data indicate a possible involvement of NIF-1 in BC progression, likely as a suppressor and through interactions with Sox9 and HoxA1.

Preparation of a molecularly imprinted sensor based on quartz crystal microbalance for specific recognition of sialic acid in human urine.

PubMed

Qiu, Xiuzhen; Xu, Xian-Yan; Chen, Xuncai; Wu, Yiyong; Guo, Huishi

2018-05-08

A novel molecularly imprinted quartz crystal microbalance (QCM) sensor was successfully prepared for selective determination of sialic acid (SA) in human urine samples. To obtain the QCM sensor, we first modified the gold surface of the QCM chip by self-assembling of allylmercaptane to introduce polymerizable double bonds on the chip surface. Then, SA molecularly imprinted polymer (MIP) nanofilm was attached to the modified QCM chip surface. For comparison, we have also characterized the nonmodified and improved surfaces of the QCM sensor by using atomic force microscopy (AFM) and Fourier transform infrared (FTIR) spectroscopy. We then tested the selectivity and detection limit of the imprinted QCM sensor via a series of adsorption experiments. The results show a linear response in the range of 0.025-0.50 μmol L -1 for sialic acid. Moreover, the limit of detection (LOD) of the prepared imprinted QCM sensor was found to be 1.0 nmol L -1 for sialic acid, and high recovery values range from 87.6 to 108.5% with RSD < 8.7 (n = 5) for the spiked urine sample obtained. Overall, this work presents how a novel QCM sensor was developed and used to detect sialic acid in human urine samples. Graphical abstract Specific recognition of sialic acid by the MIP-QCM sensor system.

Summary of Documentation for DYNA3D-ParaDyn's Software Quality Assurance Regression Test Problems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zywicz, Edward

The Software Quality Assurance (SQA) regression test suite for DYNA3D (Zywicz and Lin, 2015) and ParaDyn (DeGroot, et al., 2015) currently contains approximately 600 problems divided into 21 suites, and is a required component of ParaDyn’s SQA plan (Ferencz and Oliver, 2013). The regression suite allows developers to ensure that software modifications do not unintentionally alter the code response. The entire regression suite is run prior to permanently incorporating any software modification or addition. When code modifications alter test problem results, the specific cause must be determined and fully understood before the software changes and revised test answers can bemore » incorporated. The regression suite is executed on LLNL platforms using a Python script and an associated data file. The user specifies the DYNA3D or ParaDyn executable, number of processors to use, test problems to run, and other options to the script. The data file details how each problem and its answer extraction scripts are executed. For each problem in the regression suite there exists an input deck, an eight-processor partition file, an answer file, and various extraction scripts. These scripts assemble a temporary answer file in a specific format from the simulation results. The temporary and stored answer files are compared to a specific level of numerical precision, and when differences are detected the test problem is flagged as failed. Presently, numerical results are stored and compared to 16 digits. At this accuracy level different processor types, compilers, number of partitions, etc. impact the results to various degrees. Thus, for consistency purposes the regression suite is run with ParaDyn using 8 processors on machines with a specific processor type (currently the Intel Xeon E5530 processor). For non-parallel regression problems, i.e., the two XFEM problems, DYNA3D is used instead. When environments or platforms change, executables using the current source code and the new resource are created and the regression suite is run. If differences in answers arise, the new answers are retained provided that the differences are inconsequential. This bootstrap approach allows the test suite answers to evolve in a controlled manner with a high level of confidence. Developers also run the entire regression suite with (serial) DYNA3D. While these results normally differ from the stored (parallel) answers, abnormal termination or wildly different values are strong indicators of potential issues.« less

Distributed processor allocation for launching applications in a massively connected processors complex

DOEpatents

Pedretti, Kevin

2008-11-18

A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

Vapor Phase Catalytic Ammonia Reduction

NASA Technical Reports Server (NTRS)

Flynn, Michael T.; Harper, Lynn D. (Technical Monitor)

1994-01-01

This paper discusses the development of a Vapor Phase Catalytic Ammonia Reduction (VPCAR) teststand and the results of an experimental program designed to evaluate the potential of the technology as a water purification process. In the experimental program the technology is evaluated based upon product water purity, water recovery rate, and power consumption. The experimental work demonstrates that the technology produces high purity product water and attains high water recovery rates at a relatively high specific power consumption. The experimental program was conducted in 3 phases. In phase I an Igepon(TM) soap and water mixture was used to evaluate the performance of an innovative Wiped-Film Rotating-Disk evaporator and associated demister. In phase II a phenol-water solution was used to evaluate the performance of the high temperature catalytic oxidation reactor. In phase III a urine analog was used to evaluate the performance of the combined distillation/oxidation functions of the processor.

Development of biomonitoring equivalents for barium in urine and plasma for interpreting human biomonitoring data.

PubMed

Poddalgoda, Devika; Macey, Kristin; Assad, Henry; Krishnan, Kannan

2017-06-01

The objectives of the present work were: (1) to assemble population-level biomonitoring data to identify the concentrations of urinary and plasma barium across the general population; and (2) to derive biomonitoring equivalents (BEs) for barium in urine and plasma in order to facilitate the interpretation of barium concentrations in the biological matrices. In population level biomonitoring studies, barium has been measured in urine in the U.S. (NHANES study), but no such data on plasma barium levels were identified. The BE values for plasma and urine were derived from U.S. EPA's reference dose (RfD) of 0.2 mg/kg bw/d, based on a lower confidence limit on the benchmark dose (BMDL 05 ) of 63 mg/kg bw/d. The plasma BE (9 μg Ba/L) was derived by regression analysis of the near-steady-state plasma concentrations associated with the administered doses in animals exposed to barium chloride dihydrate in drinking water for 2-years in a NTP study. Using a human urinary excretion fraction of 0.023, a BE for urinary barium (0.19 mg/L or 0.25 mg/g creatinine) was derived for US EPA's RfD. The median and the 95 th percentile barium urine concentrations of the general population in U.S. are below the BE determined in this study, indicating that the population exposure to inorganic barium is expected to be below the exposure guidance value of 0.2 mg/kg bw/d. Copyright © 2017 The Author(s). Published by Elsevier Inc. All rights reserved.

2014 ISS Potable Water Characterization and Continuation of the DMSD Chronicle

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Mudgett, Paul D.

2015-01-01

During 2014 the crews from Expeditions 38-41 were resident on the International Space Station (ISS). In addition to the U.S. potable water reclaimed from humidity condensate and urine, the other water supplies available for their use were Russian potable water reclaimed from condensate and Russian ground-supplied potable water. Beginning in June of 2014, and for the fourth time since 2010, the product water from the U.S. Water Processor Assembly (WPA) experienced a rise in the total organic carbon (TOC) level due to organic contaminants breaking through the water treatment process. Results from ground analyses of ISS archival water samples returned on Soyuz 38 confirmed that dimethylsilanediol (DMSD) was once again the contaminant responsible for the rise. With this confirmation in hand and based upon the low toxicity of DMSD, a waiver was approved to allow the crew to continue to consume the water after the TOC level exceeded the U.S. Segment limit of 3 mg/L. Several weeks after the WPA multifiltration beds were replaced, as anticipated based upon experience from previous rises, the TOC levels returned to below the method detection limit of the onboard TOC analyzer (TOCA). This paper presents and discusses the chemical analysis results for the ISS archival potable water samples returned in 2014 and analyzed by the Johnson Space Center's Toxicology and Environmental Chemistry laboratory. These results showed compliance with ISS potable water quality standards and indicated that the potable water supplies were acceptable for crew consumption. Although DMSD levels were at times elevated they remained well below the 35 mg/L health limit, so continued consumption of the U.S potable water was considered a low risk to crew health and safety. Excellent agreement between inflight and archival sample TOC data confirmed that the TOCA performed optimally and it continued to serve as a vital tool for monitoring organic breakthrough and planning remediation action.

2014 ISS Potable Water Characterization and Continuation of the Dimethylsilanediol Chronicle

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Mudgett, Paul D.

2015-01-01

During 2014 the crews from Expeditions 38-41 were in residence on the International Space Station (ISS). In addition to the U.S. potable water reclaimed from humidity condensate and urine, the other water supplies available for their use were Russian potable water reclaimed from condensate and Russian ground-supplied potable water. Beginning in June of 2014 and for the fourth time since 2010, the product water from the U.S. water processor assembly (WPA) experienced a rise in the total organic carbon (TOC) level due to organic contaminants breaking through the water treatment process. Results from ground analyses of ISS archival water samples returned on Soyuz 38 confirmed that dimethylsilanediol was once again the contaminant responsible for the rise. With this confirmation in hand and based upon the low toxicity of dimethylsilanediol, a waiver was approved to allow the crew to continue to consume the water after the TOC level exceeded the U.S. Segment limit of 3 mg/L. Several weeks after the WPA multifiltration beds were replaced, the TOC levels returned to below the method detection limit of the onboard TOC analyzer (TOCA) as anticipated based upon experience from previous rises. This paper presents and discusses the chemical analysis results for the ISS archival potable-water samples returned in 2014 and analyzed by the Johnson Space Center's Toxicology and Environmental Chemistry laboratory. These results showed compliance with ISS potable water quality standards and indicated that the potable-water supplies were acceptable for crew consumption. Although dimethylsilanediol levels were at times elevated, they remained well below the 35 mg/L health limit so the continued consumption of the U.S. potable water was considered a low risk to crew health and safety. Excellent agreement between in-flight and archival sample TOC data confirmed that the TOCA performed optimally and continued to serve as a vital tool for monitoring organic breakthrough and planning remediation action.

NASA Tech Briefs, October 2012

NASA Technical Reports Server (NTRS)

2012-01-01

Topics discussed include: Detection of Chemical Precursors of Explosives; Detecting Methane From Leaking Pipelines and as Greenhouse Gas in the Atmosphere; Onboard Sensor Data Qualification in Human-Rated Launch Vehicles; Rugged, Portable, Real-Time Optical Gaseous Analyzer for Hydrogen Fluoride; A Probabilistic Mass Estimation Algorithm for a Novel 7-Channel Capacitive Sample Verification Sensor; Low-Power Architecture for an Optical Life Gas Analyzer; Online Cable Tester and Rerouter; A Three-Frequency Feed for Millimeter-Wave Radiometry; Capacitance Probe Resonator for Multichannel Electrometer; Inverted Three-Junction Tandem Thermophotovoltaic Modules; Fabrication of Single Crystal MgO Capsules; Inflatable Hangar for Assembly of Large Structures in Space; Mars Aqueous Processing System; Hybrid Filter Membrane; Design for the Structure and the Mechanics of Moballs; Pressure Dome for High-Pressure Electrolyzer; Cascading Tesla Oscillating Flow Diode for Stirling Engine Gas Bearings; Compact, Low-Force, Low-Noise Linear Actuator; Ultra-Compact Motor Controller; Extreme Ionizing-Radiation-Resistant Bacterium; Wideband Single-Crystal Transducer for Bone Characterization; Fluorescence-Activated Cell Sorting of Live Versus Dead Bacterial Cells and Spores; Nonhazardous Urine Pretreatment Method; Laser-Ranging Transponders for Science Investigations of the Moon and Mars; Ka-Band Waveguide Three-Way Serial Combiner for MMIC Amplifiers; Structural Health Monitoring with Fiber Bragg Grating and Piezo Arrays; Low-Gain Circularly Polarized Antenna with Torus-Shaped Pattern; Stereo and IMU- Assisted Visual Odometry for Small Robots; Global Swath and Gridded Data Tiling; GOES-R: Satellite Insight; Aquarius iPhone Application; Monitoring of International Space Station Telemetry Using Shewhart Control Charts; Theory of a Traveling Wave Feed for a Planar Slot Array Antenna; Time Manager Software for a Flight Processor; Simulation of Oxygen Disintegration and Mixing With Hydrogen or Helium at Supercritical Pressure; A Superfluid Pulse Tube Refrigerator Without Moving Parts for Sub-Kelvin Cooling; Sapphire Viewports for a Venus Probe; The Mobile Chamber; Electric Propulsion Induced Secondary Mass Spectroscopy; and Radiation-Tolerant DC-DC Converters.

A new version of the CADNA library for estimating round-off error propagation in Fortran programs

NASA Astrophysics Data System (ADS)

Jézéquel, Fabienne; Chesneaux, Jean-Marie; Lamotte, Jean-Luc

2010-11-01

The CADNA library enables one to estimate, using a probabilistic approach, round-off error propagation in any simulation program. CADNA provides new numerical types, the so-called stochastic types, on which round-off errors can be estimated. Furthermore CADNA contains the definition of arithmetic and relational operators which are overloaded for stochastic variables and the definition of mathematical functions which can be used with stochastic arguments. On 64-bit processors, depending on the rounding mode chosen, the mathematical library associated with the GNU Fortran compiler may provide incorrect results or generate severe bugs. Therefore the CADNA library has been improved to enable the numerical validation of programs on 64-bit processors. New version program summaryProgram title: CADNA Catalogue identifier: AEAT_v1_1 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEAT_v1_1.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 28 488 No. of bytes in distributed program, including test data, etc.: 463 778 Distribution format: tar.gz Programming language: Fortran NOTE: A C++ version of this program is available in the Library as AEGQ_v1_0 Computer: PC running LINUX with an i686 or an ia64 processor, UNIX workstations including SUN, IBM Operating system: LINUX, UNIX Classification: 6.5 Catalogue identifier of previous version: AEAT_v1_0 Journal reference of previous version: Comput. Phys. Commun. 178 (2008) 933 Does the new version supersede the previous version?: Yes Nature of problem: A simulation program which uses floating-point arithmetic generates round-off errors, due to the rounding performed at each assignment and at each arithmetic operation. Round-off error propagation may invalidate the result of a program. The CADNA library enables one to estimate round-off error propagation in any simulation program and to detect all numerical instabilities that may occur at run time. Solution method: The CADNA library [1-3] implements Discrete Stochastic Arithmetic [4,5] which is based on a probabilistic model of round-off errors. The program is run several times with a random rounding mode generating different results each time. From this set of results, CADNA estimates the number of exact significant digits in the result that would have been computed with standard floating-point arithmetic. Reasons for new version: On 64-bit processors, the mathematical library associated with the GNU Fortran compiler may provide incorrect results or generate severe bugs with rounding towards -∞ and +∞, which the random rounding mode is based on. Therefore a particular definition of mathematical functions for stochastic arguments has been included in the CADNA library to enable its use with the GNU Fortran compiler on 64-bit processors. Summary of revisions: If CADNA is used on a 64-bit processor with the GNU Fortran compiler, mathematical functions are computed with rounding to the nearest, otherwise they are computed with the random rounding mode. It must be pointed out that the knowledge of the accuracy of the stochastic argument of a mathematical function is never lost. Restrictions: CADNA requires a Fortran 90 (or newer) compiler. In the program to be linked with the CADNA library, round-off errors on complex variables cannot be estimated. Furthermore array functions such as product or sum must not be used. Only the arithmetic operators and the abs, min, max and sqrt functions can be used for arrays. Additional comments: In the library archive, users are advised to read the INSTALL file first. The doc directory contains a user guide named ug.cadna.pdf which shows how to control the numerical accuracy of a program using CADNA, provides installation instructions and describes test runs. The source code, which is located in the src directory, consists of one assembly language file (cadna_rounding.s) and eighteen Fortran language files. cadna_rounding.s is a symbolic link to the assembly file corresponding to the processor and the Fortran compiler used. This assembly file contains routines which are frequently called in the CADNA Fortran files to change the rounding mode. The Fortran language files contain the definition of the stochastic types on which the control of accuracy can be performed, CADNA specific functions (for instance to enable or disable the detection of numerical instabilities), the definition of arithmetic and relational operators which are overloaded for stochastic variables and the definition of mathematical functions which can be used with stochastic arguments. The examples directory contains seven test runs which illustrate the use of the CADNA library and the benefits of Discrete Stochastic Arithmetic. Running time: The version of a code which uses CADNA runs at least three times slower than its floating-point version. This cost depends on the computer architecture and can be higher if the detection of numerical instabilities is enabled. In this case, the cost may be related to the number of instabilities detected.

Electrostatic Assemblies of Well-Dispersed AgNPs on the Surface of Electrospun Nanofibers as Highly Active SERS Substrates for Wide-Range pH Sensing.

PubMed

Yang, Tong; Ma, Jun; Zhen, Shu Jun; Huang, Cheng Zhi

2016-06-15

Surface-enhanced Raman scattering (SERS) has shown high promise in analysis and bioanalysis, wherein noble metal nanoparticles (NMNPs) such as silver nanoparticles were employed as substrates because of their strong localized surface plasmon resonance (LSPR) properties. However, SERS-based pH sensing was restricted because of the aggregation of NMNPs in acidic medium or biosamples with high ionic strength. Herein, by using the electrostatic interaction as a driving force, AgNPs are assembled on the surface of ethylene imine polymer (PEI)/poly(vinyl alcohol) (PVA) electrospun nanofibers, which are then applied as highly sensitive and reproducible SERS substrate with an enhancement factor (EF) of 10(7)-10(8). When p-aminothiophenol (p-ATP) is used as an indicator with its b2 mode, a good and wide linear response to pH ranging from 2.56 to 11.20 could be available, and the as-prepared nanocomposite fibers then could be fabricated as excellent pH sensors in complicated biological samples such as urine, considering that the pH of urine could reflect the acid-base status of a person. This work not only emerges a cost-effective, direct, and convenient approach to homogeneously decorate AgNPs on the surface of polymer nanofibers but also supplies a route for preparing other noble metal nanofibrous sensing membranes.

Molecular basis of maple syrup urine disease: Novel mutations at the E1[alpha] locus that impair E1([alpha][sub 2][beta][sub 2]) assembly or decrease steady-state E1[alpha] mRNA levels of branched-chain [alpha]-keto acid dehydrogenase complex

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chuang, J.L.; Fisher, C.R.; Chuang, D.T.

1994-08-01

The authors report the occurrence of three novel mutations in the E1[alpha] (BCKDHA) locus of the branched-chain [alpha]-keto acid dehydrogenase (BCKAD) complex that cause maple syrup urine disease (MSUD). An 8-bp deletion in exon 7 is present in one allele of a compound-heterozygous patient (GM-649). A single C nucleotide insertion in exon 2 occurs in one allele of an intermediate-MSUD patient (Lo). The second allele of patient Lo carries an A-to-G transition in exon 9 of the E1[alpha] gene. This missense mutation changes Tyr-368 to Cys (Y368C) in the E1[alpha] subunit. Both the 8-bp deletion and the single C insertionmore » generate a downstream nonsense codon. Both mutations appear to be associated with a low abundance of the mutant E1[alpha] mRNA, as determined by allele-specific oligonucleotide probing. Transfection studies strongly suggest that the Y368C substitution in the E1[alpha] subunit impairs its proper assembly with the normal E1[beta]. Unassembled as well as misassembled E1[alpha] and E1[beta] subunits are degraded in the cell. 32 refs., 8 figs.« less

Enabling Graph Appliance for Genome Assembly

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Rina; Graves, Jeffrey A; Lee, Sangkeun

2015-01-01

In recent years, there has been a huge growth in the amount of genomic data available as reads generated from various genome sequencers. The number of reads generated can be huge, ranging from hundreds to billions of nucleotide, each varying in size. Assembling such large amounts of data is one of the challenging computational problems for both biomedical and data scientists. Most of the genome assemblers developed have used de Bruijn graph techniques. A de Bruijn graph represents a collection of read sequences by billions of vertices and edges, which require large amounts of memory and computational power to storemore » and process. This is the major drawback to de Bruijn graph assembly. Massively parallel, multi-threaded, shared memory systems can be leveraged to overcome some of these issues. The objective of our research is to investigate the feasibility and scalability issues of de Bruijn graph assembly on Cray s Urika-GD system; Urika-GD is a high performance graph appliance with a large shared memory and massively multithreaded custom processor designed for executing SPARQL queries over large-scale RDF data sets. However, to the best of our knowledge, there is no research on representing a de Bruijn graph as an RDF graph or finding Eulerian paths in RDF graphs using SPARQL for potential genome discovery. In this paper, we address the issues involved in representing a de Bruin graphs as RDF graphs and propose an iterative querying approach for finding Eulerian paths in large RDF graphs. We evaluate the performance of our implementation on real world ebola genome datasets and illustrate how genome assembly can be accomplished with Urika-GD using iterative SPARQL queries.« less

A real-time programming system.

PubMed

Townsend, H R

1979-03-01

The paper describes a Basic Operating and Scheduling System (BOSS) designed for a small computer. User programs are organised as self-contained modular 'processes' and the way in which the scheduler divides the time of the computer equally between them, while arranging for any process which has to respond to an interrupt from a peripheral device to be given the necessary priority, is described in detail. Next the procedures provided by the operating system to organise communication between processes are described, and how they are used to construct dynamically self-modifying real-time systems. Finally, the general philosophy of BOSS and applications to a multi-processor assembly are discussed.

Risetime distortion of Shuttle Ku-band payload 50 MBPS data due to coaxial cable skin effects

NASA Technical Reports Server (NTRS)

Schadelbauer, S.; Vang, H. A.

1980-01-01

This paper discusses distortion of digital signals generated in the Space Shuttle Ku-band communications systems. Specifically, the degradation considered is due to coaxial cables which interface data and clock from a source located in the payload bay to the KuSPA (Ku-Band Signal Processor Assembly) located in the avionics bay of the Shuttle. Due to the length (nearly 100 feet) and relatively narrow bandwidth of the cable, the clock and data waveforms are significantly affected by this transmission medium. This paper presents a closed form model that closely approximates the distortion of the waveforms measured in laboratory tests.

LLL 8080 BASIC-II interpreter user's manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

McGoldrick, P.R.; Dickinson, J.; Allison, T.G.

1978-04-03

Scientists are finding increased applications for microprocessors as process controllers in their experiments. However, while microprocessors are small and inexpensive, they are difficult to program in machine or assembly language. A high-level language is needed to enable scientists to develop their own microcomputer programs for their experiments on location. Recognizing this need, LLL contracted to have such a language developed. This report describes the resulting LLL BASIC interpreter, which opeates with LLL's 8080-based MCS-8 microcomputer system. All numerical operations are done using Advanced Micro Device's Am9511 arithmetic processor chip or optionally by using a software simulation of that chip. 1more » figure.« less

Concept report: Microprocessor control of electrical power system

NASA Technical Reports Server (NTRS)

Perry, E.

1977-01-01

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

Embedded mobile farm robot for identification of diseased plants

NASA Astrophysics Data System (ADS)

Sadistap, S. S.; Botre, B. A.; Pandit, Harshavardhan; Chandrasekhar; Rao, Adesh

2013-07-01

This paper presents the development of a mobile robot used in farms for identification of diseased plants. It puts forth two of the major aspects of robotics namely automated navigation and image processing. The robot navigates on the basis of the GPS (Global Positioning System) location and data obtained from IR (Infrared) sensors to avoid any obstacles in its path. It uses an image processing algorithm to differentiate between diseased and non-diseased plants. A robotic platform consisting of an ARM9 processor, motor drivers, robot mechanical assembly, camera and infrared sensors has been used. Mini2440 microcontroller has been used wherein Embedded linux OS (Operating System) is implemented.

A strongly interacting polaritonic quantum dot

NASA Astrophysics Data System (ADS)

Jia, Ningyuan; Schine, Nathan; Georgakopoulos, Alexandros; Ryou, Albert; Clark, Logan W.; Sommer, Ariel; Simon, Jonathan

2018-06-01

Polaritons are promising constituents of both synthetic quantum matter1 and quantum information processors2, whose properties emerge from their components: from light, polaritons draw fast dynamics and ease of transport; from matter, they inherit the ability to collide with one another. Cavity polaritons are particularly promising as they may be confined and subjected to synthetic magnetic fields controlled by cavity geometry3, and furthermore they benefit from increased robustness due to the cavity enhancement in light-matter coupling. Nonetheless, until now, cavity polaritons have operated only in a weakly interacting mean-field regime4,5. Here we demonstrate strong interactions between individual cavity polaritons enabled by employing highly excited Rydberg atoms as the matter component of the polaritons. We assemble a quantum dot composed of approximately 150 strongly interacting Rydberg-dressed 87Rb atoms in a cavity, and observe blockaded transport of photons through it. We further observe coherent photon tunnelling oscillations, demonstrating that the dot is zero-dimensional. This work establishes the cavity Rydberg polariton as a candidate qubit in a photonic information processor and, by employing multiple resonator modes as the spatial degrees of freedom of a photonic particle, the primary ingredient to form photonic quantum matter6.

System for clinical photometric stereo endoscopy

NASA Astrophysics Data System (ADS)

Durr, Nicholas J.; González, Germán.; Lim, Daryl; Traverso, Giovanni; Nishioka, Norman S.; Vakoc, Benjamin J.; Parot, Vicente

2014-02-01

Photometric stereo endoscopy is a technique that captures information about the high-spatial-frequency topography of the field of view simultaneously with a conventional color image. Here we describe a system that will enable photometric stereo endoscopy to be clinically evaluated in the large intestine of human patients. The clinical photometric stereo endoscopy system consists of a commercial gastroscope, a commercial video processor, an image capturing and processing unit, custom synchronization electronics, white light LEDs, a set of four fibers with diffusing tips, and an alignment cap. The custom pieces that come into contact with the patient are composed of biocompatible materials that can be sterilized before use. The components can then be assembled in the endoscopy suite before use. The resulting endoscope has the same outer diameter as a conventional colonoscope (14 mm), plugs into a commercial video processor, captures topography and color images at 15 Hz, and displays the conventional color image to the gastroenterologist in real-time. We show that this system can capture a color and topographical video in a tubular colon phantom, demonstrating robustness to complex geometries and motion. The reported system is suitable for in vivo evaluation of photometric stereo endoscopy in the human large intestine.

Live interactive computer music performance practice

NASA Astrophysics Data System (ADS)

Wessel, David

2002-05-01

A live-performance musical instrument can be assembled around current lap-top computer technology. One adds a controller such as a keyboard or other gestural input device, a sound diffusion system, some form of connectivity processor(s) providing for audio I/O and gestural controller input, and reactive real-time native signal processing software. A system consisting of a hand gesture controller; software for gesture analysis and mapping, machine listening, composition, and sound synthesis; and a controllable radiation pattern loudspeaker are described. Interactivity begins in the set up wherein the speaker-room combination is tuned with an LMS procedure. This system was designed for improvisation. It is argued that software suitable for carrying out an improvised musical dialog with another performer poses special challenges. The processes underlying the generation of musical material must be very adaptable, capable of rapid changes in musical direction. Machine listening techniques are used to help the performer adapt to new contexts. Machine learning can play an important role in the development of such systems. In the end, as with any musical instrument, human skill is essential. Practice is required not only for the development of musically appropriate human motor programs but for the adaptation of the computer-based instrument as well.

Efficiency of static core turn-off in a system-on-a-chip with variation

DOEpatents

Cher, Chen-Yong; Coteus, Paul W; Gara, Alan; Kursun, Eren; Paulsen, David P; Schuelke, Brian A; Sheets, II, John E; Tian, Shurong

2013-10-29

A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

Calibrating thermal behavior of electronics

DOEpatents

Chainer, Timothy J.; Parida, Pritish R.; Schultz, Mark D.

2017-07-11

A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

Calibrating thermal behavior of electronics

DOEpatents

Chainer, Timothy J.; Parida, Pritish R.; Schultz, Mark D.

2016-05-31

A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

Calibrating thermal behavior of electronics

DOEpatents

Chainer, Timothy J.; Parida, Pritish R.; Schultz, Mark D.

2017-01-03

A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

Study on a novel core module based on optical fiber bundles for urine dry-chemistry analysis

NASA Astrophysics Data System (ADS)

Liu, Gaiqin; Ma, Zengwei; Li, Rui; Hu, Nan; Chen, Ping; Wang, Fei; Zhang, Ruiying; Chen, Longcong

2017-09-01

A core module with a novel optical structure is presented to analyze urine by the dry-chemistry method in this paper. It consists of a 32-bit microprocessor, optical fiber bundles, a high precision color sensor and a temperature sensor. The optical fiber bundles are adopted to control the spread path of light and reduce the influence of ambient light and the distance between the strip and sensor effectively. And the temperature sensor is applied to detect the environmental temperature to calibrate the measurement results. Therefore, all these can bring a lot of benefits to the core module, such as improving its test accuracy, reducing its volume and cost, and simplifying its assembly. Additionally, some parameters, including the calculation coefficient about reflectivity of each item, semi-quantitative intervals, the number of test items, may be modified by corresponding instructions in order to enhance its applicability. Meanwhile, its outputs can be chosen among the original data, normalized color values, reflectivity, and the semi-quantitative level of each test item by available instructions. Our results show that the module has high measurement accuracy of more than 95%, good stability, reliability, and consistency and can be easily used in various types of urine analyzers.

Electricity and catholyte production from ceramic MFCs treating urine.

PubMed

Merino Jimenez, Irene; Greenman, John; Ieropoulos, Ioannis

2017-01-19

The use of ceramics as low cost membrane materials for Microbial Fuel Cells (MFCs) has gained increasing interest, due to improved performance levels in terms of power and catholyte production. The catholyte production in ceramic MFCs can be attributed to a combination of water or hydrogen peroxide formation from the oxygen reduction reaction in the cathode, water diffusion and electroosmotic drag through the ion exchange membrane. This study aims to evaluate, for the first time, the effect of ceramic wall/membrane thickness, in terms of power, as well as catholyte production from MFCs using urine as a feedstock. Cylindrical MFCs were assembled with fine fire clay of different thicknesses (2.5, 5 and 10 mm) as structural and membrane materials. The power generated increased when the membrane thickness decreased, reaching 2.1 ± 0.19 mW per single MFC (2.5 mm), which was 50% higher than that from the MFCs with the thickest membrane (10 mm). The amount of catholyte collected also decreased with the wall thickness, whereas the pH increased. Evidence shows that the catholyte composition varies with the wall thickness of the ceramic membrane. The possibility of producing different quality of catholyte from urine opens a new field of study in water reuse and resource recovery for practical implementation.

The draft genomes and investigation of serotype distribution, antimicrobial resistance of group B Streptococcus strains isolated from urine in Suzhou, China.

PubMed

Guo, Yong; Deng, Xiao; Liang, Yuan; Zhang, Liang; Zhao, Guo-Ping; Zhou, Yan

2018-06-26

The group B Streptococcus (GBS) is a human commensal bacterium, which is capable of causing several infectious diseases in infants, and people with chronic diseases. GBS has been the most common cause of infections in urinary tract of the elders, but relatively few studies reported the urine-isolated GBS and their antimicrobial susceptibilities. Hence, we decided to investigate GBS specially isolated from urine in Suzhou, China. 27 GBS samples were isolated from urine in Suzhou, China. The PCR and agarose gel electrophoresis were used to identify the serotype distribution. Susceptibility tests were based on MIC test and Kirby-Bauer test. Genome were sequenced via Illumina Hiseq platform and assembled by SPAdes. Genomes of five isolates were sequenced and submitted to NCBI genome database. The sequencing files in fastq format were submitted to NCBI SRA database. Five serotypes were identified. The resistant rates measured for tetracycline, erythromycin, clindamycin and fluoroquinolones were 74.1, 63.0, 44.4 and 48.1%, respectively. 18.5% of the isolates were nonsusceptible to nitrofurantoin. The resistance to tetracycline was mainly associated with the gene tetM. The erythromycin resistance was mainly associated with the genes ermB and mefE. The genes ermB and lnuB were the prevalent genes in cMLSB type. No known nitrofurantoin resistance gene was found in nitrofurantoin-nonsusceptible GBS. Five serotypes were identified in our study. High rates of GBS isolates were resistant to tetracycline, erythromycin, clindamycin and fluoroquinolones. The genes ermB and lnuB occupied high rates in cMLS B phenotype.

A microprocessor-based control system for the Vienna PDS microdensitometer

NASA Technical Reports Server (NTRS)

Jenkner, H.; Stoll, M.; Hron, J.

1984-01-01

The Motorola Exorset 30 system, based on a Motorola 6809 microprocessor which serves as control processor for the microdensitometer is presented. User communication and instrument control are implemented in this syatem; data transmission to a host computer is provided via standard interfaces. The Vienna PDS system (VIPS) software was developed in BASIC and M6809 assembler. It provides efficient user interaction via function keys and argument input in a menu oriented environment. All parameters can be stored on, and retrieved from, minifloppy disks, making it possible to set up large scanning tasks. Extensive user information includes continuously updated status and coordinate displays, as well as a real time graphic display during scanning.

Structural weights analysis of advanced aerospace vehicles using finite element analysis

NASA Technical Reports Server (NTRS)

Bush, Lance B.; Lentz, Christopher A.; Rehder, John J.; Naftel, J. Chris; Cerro, Jeffrey A.

1989-01-01

A conceptual/preliminary level structural design system has been developed for structural integrity analysis and weight estimation of advanced space transportation vehicles. The system includes a three-dimensional interactive geometry modeler, a finite element pre- and post-processor, a finite element analyzer, and a structural sizing program. Inputs to the system include the geometry, surface temperature, material constants, construction methods, and aerodynamic and inertial loads. The results are a sized vehicle structure capable of withstanding the static loads incurred during assembly, transportation, operations, and missions, and a corresponding structural weight. An analysis of the Space Shuttle external tank is included in this paper as a validation and benchmark case of the system.

Silicon nanodisk array with a fin field-effect transistor for time-domain weighted sum calculation toward massively parallel spiking neural networks

NASA Astrophysics Data System (ADS)

Tohara, Takashi; Liang, Haichao; Tanaka, Hirofumi; Igarashi, Makoto; Samukawa, Seiji; Endo, Kazuhiko; Takahashi, Yasuo; Morie, Takashi

2016-03-01

A nanodisk array connected with a fin field-effect transistor is fabricated and analyzed for spiking neural network applications. This nanodevice performs weighted sums in the time domain using rising slopes of responses triggered by input spike pulses. The nanodisk arrays, which act as a resistance of several giga-ohms, are fabricated using a self-assembly bio-nano-template technique. Weighted sums are achieved with an energy dissipation on the order of 1 fJ, where the number of inputs can be more than one hundred. This amount of energy is several orders of magnitude lower than that of conventional digital processors.

Learning the Art of Electronics

NASA Astrophysics Data System (ADS)

Hayes, Thomas C.; Horowitz, Paul

2016-03-01

1. DC circuits; 2. RC circuits; 3. Diode circuits; 4. Transistors I; 5. Transistors II; 6. Operational amplifiers I; 7. Operational amplifiers II: nice positive feedback; 8. Operational amplifiers III; 9. Operational amplifiers IV: nasty positive feedback; 10. Operational amplifiers V: PID motor control loop; 11. Voltage regulators; 12. MOSFET switches; 13. Group audio project; 14. Logic gates; 15. Logic compilers, sequential circuits, flip-flops; 16. Counters; 17. Memory: state machines; 18. Analog to digital: phase-locked loop; 19. Microcontrollers and microprocessors I: processor/controller; 20. I/O, first assembly language; 21. Bit operations; 22. Interrupt: ADC and DAC; 23. Moving pointers, serial buses; 24. Dallas Standalone Micro, SiLabs SPI RAM; 25. Toys in the attic; Appendices; Index.

Environmental Control and Life Support Systems Test Facility at MSFC

NASA Technical Reports Server (NTRS)

2001-01-01

The Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. Scientists and engineers at the MSFC are working together to provide the ISS with systems that are safe, efficient, and cost-effective. These compact and powerful systems are collectively called the Environmental Control and Life Support Systems, or simply, ECLSS. In this photograph, the life test area on the left of the MSFC ECLSS test facility is where various subsystems and components are tested to determine how long they can operate without failing and to identify components needing improvement. Equipment tested here includes the Carbon Dioxide Removal Assembly (CDRA), the Urine Processing Assembly (UPA), the mass spectrometer filament assemblies and sample pumps for the Major Constituent Analyzer (MCA). The Internal Thermal Control System (ITCS) simulator facility (in the module in the right) duplicates the function and operation of the ITCS in the ISS U.S. Laboratory Module, Destiny. This facility provides support for Destiny, including troubleshooting problems related to the ITCS.

International Space Station (ISS)

NASA Image and Video Library

2001-02-01

The Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. Scientists and engineers at the MSFC are working together to provide the ISS with systems that are safe, efficient, and cost-effective. These compact and powerful systems are collectively called the Environmental Control and Life Support Systems, or simply, ECLSS. In this photograph, the life test area on the left of the MSFC ECLSS test facility is where various subsystems and components are tested to determine how long they can operate without failing and to identify components needing improvement. Equipment tested here includes the Carbon Dioxide Removal Assembly (CDRA), the Urine Processing Assembly (UPA), the mass spectrometer filament assemblies and sample pumps for the Major Constituent Analyzer (MCA). The Internal Thermal Control System (ITCS) simulator facility (in the module in the right) duplicates the function and operation of the ITCS in the ISS U.S. Laboratory Module, Destiny. This facility provides support for Destiny, including troubleshooting problems related to the ITCS.

Methods and systems for providing reconfigurable and recoverable computing resources

NASA Technical Reports Server (NTRS)

Stange, Kent (Inventor); Hess, Richard (Inventor); Kelley, Gerald B (Inventor); Rogers, Randy (Inventor)

2010-01-01

A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

Mechanism controller system for the optical spectroscopic and infrared remote imaging system instrument on board the Rosetta space mission

NASA Astrophysics Data System (ADS)

Castro Marín, J. M.; Brown, V. J. G.; López Jiménez, A. C.; Rodríguez Gómez, J.; Rodrigo, R.

2001-05-01

The optical, spectroscopic infrared remote imaging system (OSIRIS) is an instrument carried on board the European Space Agency spacecraft Rosetta that will be launched in January 2003 to study in situ the comet Wirtanen. The electronic design of the mechanism controller board (MCB) system of the two OSIRIS optical cameras, the narrow angle camera, and the wide angle camera, is described here. The system is comprised of two boards mounted on an aluminum frame as part of an electronics box that contains the power supply and the digital processor unit of the instrument. The mechanisms controlled by the MCB for each camera are the front door assembly and a filter wheel assembly. The front door assembly for each camera is driven by a four phase, permanent magnet stepper motor. Each filter wheel assembly consists of two, eight filter wheels. Each wheel is driven by a four phase, variable reluctance stepper motor. Each motor, for all the assemblies, also contains a redundant set of four stator phase windings that can be energized separately or in parallel with the main windings. All stepper motors are driven in both directions using the full step unipolar mode of operation. The MCB also performs general housekeeping data acquisition of the OSIRIS instrument, i.e., mechanism position encoders and temperature measurements. The electronic design application used is quite new due to use of a field programmable gate array electronic devices that avoid the use of the now traditional system controlled by microcontrollers and software. Electrical tests of the engineering model have been performed successfully and the system is ready for space qualification after environmental testing. This system may be of interest to institutions involved in future space experiments with similar needs for mechanisms control.

Exploiting LBL-assembled Au nanoparticles to enhance Raman signals for point-of-care testing of osteoporosis with excreta sample

NASA Astrophysics Data System (ADS)

Sun, Jian F.; Liu, Xuan; Guo, Zhi R.; Dong, Jian; Huang, Yawen; Zhang, Jie; Jin, Hui; Gu, Ning

2017-02-01

Due to the intrinsic lack of specific biomarkers, there is an increasing demand for degenerative diseases to develop a testing method independent upon the targeting biomolecules. In this paper, we proposed a novel idea for this issue which was to analyze the characteristic information of metabolites with Raman spectrum. First, we achieved the fabrication of stable, uniform and reproducible substrate to enhance the Raman signals, which is crucial to the following analysis of information. This idea was confirmed with the osteoporosis-modeled mice. Furthermore, the testing results with clinical samples also preliminarily exhibited the feasibility of this strategy. The substrate to enhance Raman signal was fabricated by the layer-by-layer assembly of Au nanoparticles. The osteoporosis modeling was made by bilateral ovariectomy. Ten female mice were randomly divided into two groups. The urine and dejecta samples of mice were collected every week. Clinic urine samples were collected from patients with osteoporosis while the controlled samples were from the young students in our university. The LBL-assembled substrate of Au nanoparticles was uniform, stable and reproducible to significantly enhance the Raman signals from tiny amount of samples. With a simple data processing technique, the Raman signal-based method can effectively reflect the development of osteoporosis by comparison with micro-CT characterization. Moreover, the Raman signal from samples of clinic patients also showed the obvious difference with that of the control. Raman spectrum may be a good tool to convey the pathological information of metabolites in molecular level. Our results manifested that the information-based testing is possibly feasible and promising. Our strategy utilizes the characteristic information rather than the biological recognition to test the diseases which are difficult to find specific biomarkers. This will be greatly beneficial to the prevention and diagnosis of degenerative diseases. Also, we believe the combination of big bio-data and characteristic recognition will change the current paradigm of medical diagnosis essentially.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Buffered coscheduling for parallel programming and enhanced fault tolerance

DOEpatents

Petrini, Fabrizio [Los Alamos, NM; Feng, Wu-chun [Los Alamos, NM

2006-01-31

A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors

Flight design system level C requirements. Solid rocket booster and external tank impact prediction processors. [space transportation system

NASA Technical Reports Server (NTRS)

Seale, R. H.

1979-01-01

The prediction of the SRB and ET impact areas requires six separate processors. The SRB impact prediction processor computes the impact areas and related trajectory data for each SRB element. Output from this processor is stored on a secure file accessible by the SRB impact plot processor which generates the required plots. Similarly the ET RTLS impact prediction processor and the ET RTLS impact plot processor generates the ET impact footprints for return-to-launch-site (RTLS) profiles. The ET nominal/AOA/ATO impact prediction processor and the ET nominal/AOA/ATO impact plot processor generate the ET impact footprints for non-RTLS profiles. The SRB and ET impact processors compute the size and shape of the impact footprints by tabular lookup in a stored footprint dispersion data base. The location of each footprint is determined by simulating a reference trajectory and computing the reference impact point location. To insure consistency among all flight design system (FDS) users, much input required by these processors will be obtained from the FDS master data base.

An Atmospheric General Circulation Model with Chemistry for the CRAY T3E: Design, Performance Optimization and Coupling to an Ocean Model

NASA Technical Reports Server (NTRS)

Farrara, John D.; Drummond, Leroy A.; Mechoso, Carlos R.; Spahr, Joseph A.

1998-01-01

The design, implementation and performance optimization on the CRAY T3E of an atmospheric general circulation model (AGCM) which includes the transport of, and chemical reactions among, an arbitrary number of constituents is reviewed. The parallel implementation is based on a two-dimensional (longitude and latitude) data domain decomposition. Initial optimization efforts centered on minimizing the impact of substantial static and weakly-dynamic load imbalances among processors through load redistribution schemes. Recent optimization efforts have centered on single-node optimization. Strategies employed include loop unrolling, both manually and through the compiler, the use of an optimized assembler-code library for special function calls, and restructuring of parts of the code to improve data locality. Data exchanges and synchronizations involved in coupling different data-distributed models can account for a significant fraction of the running time. Therefore, the required scattering and gathering of data must be optimized. In systems such as the T3E, there is much more aggregate bandwidth in the total system than in any particular processor. This suggests a distributed design. The design and implementation of a such distributed 'Data Broker' as a means to efficiently couple the components of our climate system model is described.

Data communication through multiple physical media: applications to munitions

NASA Astrophysics Data System (ADS)

Dhadwal, Harbans S.; Rastegar, Jahangir; Feng, Dake; Kwok, Philip

2015-05-01

Electronic systems comprising of subassemblies, distributed across different physical media, require seamless communication between processors and sensors embedded in the disparate volumes. For example, smart munitions systems embed sensors and other key control electronics, throughout the structure, in vastly different physical media. In addition to the obvious space constraints, these structures are subjected to high G forces during launch. Thus, communications through wire harnesses becomes cumbersome, make assembly process and testing difficult, and challenging to make survive high G firing. Here we focus on an approach that takes advantage of the partial optical transparency of epoxy material commonly used in potting electronic components in munitions, as well as the wave guiding that is possible through the body of the munitions wall which is made from composite materials. Experimental results show that a wireless optical link, connecting various parts of the distributed system, is possible at near IR frequencies. Data can be rapidly parsed between a processor, sensors and actuators. We present experimental data for a commercial epoxy system, which is used to embed a number of IrDA devices inside the cone of 120 mm mortar shell. IrDA devices using the FIR data rates establish point-to-point communication through various media, representative of the environment inside the 120 mm mortar cone.

An Assessment of the Technical Readiness of the Vapor Phase Catalytic Ammonia Removal Process (VPCAR) Technology

NASA Technical Reports Server (NTRS)

Flynn, Michael

2000-01-01

This poster provides an assessment of the technical readiness of the Vapor Phase Catalytic Ammonia Removal Process (VPCAR). The VPCAR technology is a fully regenerative water recycling technology designed specifically for applications such as a near term Mars exploration mission. The VPCAR technology is a highly integrated distillation/catalytic oxidation based water processor. It is designed to accept a combined wastewater stream (urine, condensate, and hygiene) and produces potable water in a single process step which requires -no regularly scheduled re-supply or maintenance for a 3 year mission. The technology is designed to be modular and to fit into a volume comparable to a single International Space Station Rack (when sized for a crew of 6). This poster provides a description of the VPCAR technology and a summary of the current performance of the technology. Also provided are the results of two separate NASA sponsored system trade studies which investigated the potential payback of further development of the VPCAR technology.

Jennifer Pruitt, explains ECLSS to media representatives

NASA Image and Video Library

2015-02-02

JENNIFER PRUITT, LEAD DESIGN ENGINEER FOR THE INTERNATIONAL SPACE STATION URINE PROCESSING ASSEMBLY AT MARSHALL, BRIEFS A GROUP OF MORE THAN 20 SOCIAL AND TRADITIONAL MEDIA REPRESENTATIVES ABOUT HER WORK TO IMPROVE THE RECYCLING OF WATER FOR ASTRONAUTS. THE TOUR OF MARSHALL WORK SUPPORTING NASA'S JOURNEY TO MARS WAS PART OF AGENCY-WIDE "STATE OF NASA" EVENTS FEB. 2. THE TOUR ALSO INCLUDED A LOOK AT OXYGEN RECYCLING EFFORTS, A SPACE LAUNCH SYSTEM CORE STAGE SIMULATOR AND A CHANCE TO TALK WITH MARSHALL DIRECTOR PATRICK SCHEUERMANN AND DEPUTY DIRECTOR TERESA VANHOOSER.

Generating unstructured nuclear reactor core meshes in parallel

DOE PAGES

Jain, Rajeev; Tautges, Timothy J.

2014-10-24

Recent advances in supercomputers and parallel solver techniques have enabled users to run large simulations problems using millions of processors. Techniques for multiphysics nuclear reactor core simulations are under active development in several countries. Most of these techniques require large unstructured meshes that can be hard to generate in a standalone desktop computers because of high memory requirements, limited processing power, and other complexities. We have previously reported on a hierarchical lattice-based approach for generating reactor core meshes. Here, we describe efforts to exploit coarse-grained parallelism during reactor assembly and reactor core mesh generation processes. We highlight several reactor coremore » examples including a very high temperature reactor, a full-core model of the Korean MONJU reactor, a ¼ pressurized water reactor core, the fast reactor Experimental Breeder Reactor-II core with a XX09 assembly, and an advanced breeder test reactor core. The times required to generate large mesh models, along with speedups obtained from running these problems in parallel, are reported. A graphical user interface to the tools described here has also been developed.« less

Assessment of Service Life for Regenerative ECLSS Resin Beds

NASA Technical Reports Server (NTRS)

Cloud, Dale L.; Keilich, Maria C.; Polis, Peter C.; Yanczura, Stephen J.

2013-01-01

The International Space Station (ISS) Water Processor Assembly (WPA) and Oxygen Generation Assembly (OGA) manage and process water at various levels of cleanliness for multiple purposes. The effluent of theWPA and the influent of the OGA require water at very high levels of purity. The bulk of the water purification that occurs in both systems is performed by consumable activated carbon and ion exchange resin beds. Replacement beds must be available on orbit in order to continue the ISS critical processes of water purification and oxygen generation. Various hurdles exist in order to ensure viable spare resin beds. These include the characteristics of resin beds such as: storage environment, shelf life requirements, microbial growth, and variations in the levels and species of contaminants the beds are required to remove. Careful consideration has been given to match water models, bed capacities and spares traffic models to ensure that spares are always viable. The results of these studies and considerations, in particular, how shelf life requirements affect resin bed life management, are documented in this paper.

Gas-Liquid Two-Phase Flows Through Packed Bed Reactors in Microgravity

NASA Technical Reports Server (NTRS)

Motil, Brian J.; Balakotaiah, Vemuri

2001-01-01

The simultaneous flow of gas and liquid through a fixed bed of particles occurs in many unit operations of interest to the designers of space-based as well as terrestrial equipment. Examples include separation columns, gas-liquid reactors, humidification, drying, extraction, and leaching. These operations are critical to a wide variety of industries such as petroleum, pharmaceutical, mining, biological, and chemical. NASA recognizes that similar operations will need to be performed in space and on planetary bodies such as Mars if we are to achieve our goals of human exploration and the development of space. The goal of this research is to understand how to apply our current understanding of two-phase fluid flow through fixed-bed reactors to zero- or partial-gravity environments. Previous experiments by NASA have shown that reactors designed to work on Earth do not necessarily function in a similar manner in space. Two experiments, the Water Processor Assembly and the Volatile Removal Assembly have encountered difficulties in predicting and controlling the distribution of the phases (a crucial element in the operation of this type of reactor) as well as the overall pressure drop.

Integration of In-Flight and Post-Flight Water Monitoring Resources in Addressing the U.S. Water Processor Assembly Total Organic Carbon (TOC) Anomaly

NASA Technical Reports Server (NTRS)

Straub, John E., II; McCly, J. Torin

2011-01-01

Beginning in June of 2010, the total organic carbon (TOC) concentration in the U.S. Water Processor Assembly (WPA) product water started to increase. A surprisingly consistent upward TOC trend was observed through weekly ISS total organic carbon analyzer (TOCA) monitoring. As TOC is a general organic compound indicator, return of water archive samples was needed to make better-informed crew health decisions on the specific compounds of concern and to aid in WPA troubleshooting. TOCA-measured TOC was more than halfway to the health-based screening limit of 3,000 g/L before archive samples were returned. Archive samples were returned on 22 Soyuz in September 2010 and on ULF5 in November of 2010. The samples were subjected to extensive analysis. Although TOC was confirmed to be elevated, somewhat surprisingly, none of the typical target compounds were detected at high levels. After some solid detective work, it was confirmed that the TOC was associated with a compound known as dimethylsilanediol (DMSD). DMSD is believed to be a breakdown product of siloxanes which are thought to be ubiquitous in the ISS atmosphere. A toxicological limit was set for DMSD and a forward plan was developed for conducting operations in the context of understanding the composition of the TOC measured in flight. This required careful consideration of existing ISS flight rules, coordination with ISS stakeholders, and development of a novel approach for the blending of inflight TOCA data with archive results to protect crew health. Among other challenges, team members had to determine how to utilize TOCA readings when making decisions about crew consumption of WPA water. This involved balancing very real concerns associated with the assumption that TOC would continue to be comprised of only DMSD. Demonstrated teamwork, multidisciplinary awareness, and innovative problem-solving were required to respond effectively to this anomaly.

Coding, testing and documentation of processors for the flight design system

NASA Technical Reports Server (NTRS)

1980-01-01

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

The computational structural mechanics testbed generic structural-element processor manual

NASA Technical Reports Server (NTRS)

Stanley, Gary M.; Nour-Omid, Shahram

1990-01-01

The usage and development of structural finite element processors based on the CSM Testbed's Generic Element Processor (GEP) template is documented. By convention, such processors have names of the form ESi, where i is an integer. This manual is therefore intended for both Testbed users who wish to invoke ES processors during the course of a structural analysis, and Testbed developers who wish to construct new element processors (or modify existing ones).

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1994-01-01

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, Michael S.; Strip, David R.

1996-01-01

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modelling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modelling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modelling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication.

Switch for serial or parallel communication networks

DOEpatents

Crosette, D.B.

1994-07-19

A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination. 9 figs.

Switch for serial or parallel communication networks

DOEpatents

Crosette, Dario B.

1994-01-01

A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

Conditions for space invariance in optical data processors used with coherent or noncoherent light.

PubMed

Arsenault, H R

1972-10-01

The conditions for space invariance in coherent and noncoherent optical processors are considered. All linear optical processors are shown to belong to one of two types. The conditions for space invariance are more stringent for noncoherent processors than for coherent processors, so that a system that is linear in coherent light may be nonlinear in noncoherent light. However, any processor that is linear in noncoherent light is also linear in the coherent limit.

Broadcasting collective operation contributions throughout a parallel computer

DOEpatents

Faraj, Ahmad [Rochester, MN

2012-02-21

Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications.

LANDSAT-D flight segment operations manual. Appendix B: OBC software operations

NASA Technical Reports Server (NTRS)

Talipsky, R.

1981-01-01

The LANDSAT 4 satellite contains two NASA standard spacecraft computers and 65,536 words of memory. Onboard computer software is divided into flight executive and applications processors. Both applications processors and the flight executive use one or more of 67 system tables to obtain variables, constants, and software flags. Output from the software for monitoring operation is via 49 OBC telemetry reports subcommutated in the spacecraft telemetry. Information is provided about the flight software as it is used to control the various spacecraft operations and interpret operational OBC telemetry. Processor function descriptions, processor operation, software constraints, processor system tables, processor telemetry, and processor flow charts are presented.

Managing Power Heterogeneity

NASA Astrophysics Data System (ADS)

Pruhs, Kirk

A particularly important emergent technology is heterogeneous processors (or cores), which many computer architects believe will be the dominant architectural design in the future. The main advantage of a heterogeneous architecture, relative to an architecture of identical processors, is that it allows for the inclusion of processors whose design is specialized for particular types of jobs, and for jobs to be assigned to a processor best suited for that job. Most notably, it is envisioned that these heterogeneous architectures will consist of a small number of high-power high-performance processors for critical jobs, and a larger number of lower-power lower-performance processors for less critical jobs. Naturally, the lower-power processors would be more energy efficient in terms of the computation performed per unit of energy expended, and would generate less heat per unit of computation. For a given area and power budget, heterogeneous designs can give significantly better performance for standard workloads. Moreover, even processors that were designed to be homogeneous, are increasingly likely to be heterogeneous at run time: the dominant underlying cause is the increasing variability in the fabrication process as the feature size is scaled down (although run time faults will also play a role). Since manufacturing yields would be unacceptably low if every processor/core was required to be perfect, and since there would be significant performance loss from derating the entire chip to the functioning of the least functional processor (which is what would be required in order to attain processor homogeneity), some processor heterogeneity seems inevitable in chips with many processors/cores.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Simulink/PARS Integration Support

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, B.; Nakhaee, N.

2013-12-18

The state of the art for signal processor hardware has far out-paced the development tools for placing applications on that hardware. In addition, signal processors are available in a variety of architectures, each uniquely capable of handling specific types of signal processing efficiently. With these processors becoming smaller and demanding less power, it has become possible to group multiple processors, a heterogeneous set of processors, into single systems. Different portions of the desired problem set can be assigned to different processor types as appropriate. As software development tools do not keep pace with these processors, especially when multiple processors ofmore » different types are used, a method is needed to enable software code portability among multiple processors and multiple types of processors along with their respective software environments. Sundance DSP, Inc. has developed a software toolkit called “PARS”, whose objective is to provide a framework that uses suites of tools provided by different vendors, along with modeling tools and a real time operating system, to build an application that spans different processor types. The software language used to express the behavior of the system is a very high level modeling language, “Simulink”, a MathWorks product. ORNL has used this toolkit to effectively implement several deliverables. This CRADA describes this collaboration between ORNL and Sundance DSP, Inc.« less

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, M.S.; Strip, D.R.

1996-01-30

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modeling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modeling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modeling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication. 8 figs.

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G.; Salapura, Valentina

2012-07-24

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Biochemical basis of type IB (E1beta ) mutations in maple syrup urine disease. A prevalent allele in patients from the Druze kindred in Israel.

PubMed

Wynn, R M; Chuang, J L; Sansaricq, C; Mandel, H; Chuang, D T

2001-09-28

Maple syrup urine disease (MSUD) is a metabolic disorder associated with often-fatal ketoacidosis, neurological derangement, and mental retardation. In this study, we identify and characterize two novel type IB MSUD mutations in Israeli patients, which affect the E1beta subunit in the decarboxylase (E1) component of the branched-chain alpha-ketoacid dehydrogenase complex. The recombinant mutant E1 carrying the prevalent S289L-beta (TCG --> TTG) mutation in the Druze kindred exists as a stable inactive alphabeta heterodimer. Based on the human E1 structure, the S289L-beta mutation disrupts the interactions between Ser-289-beta and Glu-290-beta', and between Arg-309-beta and Glu-290-beta', which are essential for native alpha(2)beta(2) heterotetrameric assembly. The R133P-beta (CGG --> CCG) mutation, on the other hand, is inefficiently expressed in Escherichia coli as heterotetramers in a temperature-dependent manner. The R133P-beta mutant E1 exhibits significant residual activity but is markedly less stable than the wild-type, as measured by thermal inactivation and free energy change of denaturation. The R133P-beta substitution abrogates the coordination of Arg-133-beta to Ala-95-beta, Glu-96-beta, and Ile-97-beta, which is important for strand-strand interactions and K(+) ion binding in the beta subunit. These findings provide new insights into folding and assembly of human E1 and will facilitate DNA-based diagnosis for MSUD in the Israeli population.

Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Ordering of guarded and unguarded stores for no-sync I/O

DOEpatents

Gara, Alan; Ohmacht, Martin

2013-06-25

A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.

Automated system for analyzing the activity of individual neurons

NASA Technical Reports Server (NTRS)

Bankman, Isaac N.; Johnson, Kenneth O.; Menkes, Alex M.; Diamond, Steve D.; Oshaughnessy, David M.

1993-01-01

This paper presents a signal processing system that: (1) provides an efficient and reliable instrument for investigating the activity of neuronal assemblies in the brain; and (2) demonstrates the feasibility of generating the command signals of prostheses using the activity of relevant neurons in disabled subjects. The system operates online, in a fully automated manner and can recognize the transient waveforms of several neurons in extracellular neurophysiological recordings. Optimal algorithms for detection, classification, and resolution of overlapping waveforms are developed and evaluated. Full automation is made possible by an algorithm that can set appropriate decision thresholds and an algorithm that can generate templates on-line. The system is implemented with a fast IBM PC compatible processor board that allows on-line operation.

Rapid solution of large-scale systems of equations

NASA Technical Reports Server (NTRS)

Storaasli, Olaf O.

1994-01-01

The analysis and design of complex aerospace structures requires the rapid solution of large systems of linear and nonlinear equations, eigenvalue extraction for buckling, vibration and flutter modes, structural optimization and design sensitivity calculation. Computers with multiple processors and vector capabilities can offer substantial computational advantages over traditional scalar computer for these analyses. These computers fall into two categories: shared memory computers and distributed memory computers. This presentation covers general-purpose, highly efficient algorithms for generation/assembly or element matrices, solution of systems of linear and nonlinear equations, eigenvalue and design sensitivity analysis and optimization. All algorithms are coded in FORTRAN for shared memory computers and many are adapted to distributed memory computers. The capability and numerical performance of these algorithms will be addressed.

Electronics reliability fracture mechanics. Volume 1: Causes of failures of shop replaceable units and hybrid microcircuits

NASA Astrophysics Data System (ADS)

Kallis, J.; Buechler, D.; Erickson, J.; Westerhuyzen, D. V.; Strokes, R.

1992-05-01

This is the first of two volumes. The other volume (WL-TR-91-3119) is 'Fracture Mechanics'. The objective of the Electronics Reliability Fracture Mechanics (ERFM) program was to develop and demonstrate a life prediction technique for electronic assemblies, when subjected to environmental stress of vibration and thermal cycling, based upon the mechanical properties of the materials and packaging configurations which make up an electronic system. A detailed investigation was performed of the following two shop replaceable units (SRUs): Timing and Control Module (P/N 3562102) and Linear Regulator Module (P/N 3569800). The SRUs are in the Programmable Signal Processor (3137042) Line Replaceable Unit (LRU) of the Hughes AN/APG-63 Radar for the F-15 Aircraft.

Solving a four-destination traveling salesman problem using Escherichia coli cells as biocomputers.

PubMed

Esau, Michael; Rozema, Mark; Zhang, Tuo Huang; Zeng, Dawson; Chiu, Stephanie; Kwan, Rachel; Moorhouse, Cadence; Murray, Cameron; Tseng, Nien-Tsu; Ridgway, Doug; Sauvageau, Dominic; Ellison, Michael

2014-12-19

The Traveling Salesman Problem involves finding the shortest possible route visiting all destinations on a map only once before returning to the point of origin. The present study demonstrates a strategy for solving Traveling Salesman Problems using modified E. coli cells as processors for massively parallel computing. Sequential, combinatorial DNA assembly was used to generate routes, in the form of plasmids made up of marker genes, each representing a path between destinations, and short connecting linkers, each representing a given destination. Upon growth of the population of modified E. coli, phenotypic selection was used to eliminate invalid routes, and statistical analysis was performed to successfully identify the optimal solution. The strategy was successfully employed to solve a four-destination test problem.

Electrochemical sensing using voltage-current time differential

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2017-02-28

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.; Goodman, Joseph W.

1989-01-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

Modeling heterogeneous processor scheduling for real time systems

NASA Technical Reports Server (NTRS)

Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

1994-01-01

A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Reed, D.A.; Grunwald, D.C.

The spectrum of parallel processor designs can be divided into three sections according to the number and complexity of the processors. At one end there are simple, bit-serial processors. Any one of thee processors is of little value, but when it is coupled with many others, the aggregate computing power can be large. This approach to parallel processing can be likened to a colony of termites devouring a log. The most notable examples of this approach are the NASA/Goodyear Massively Parallel Processor, which has 16K one-bit processors, and the Thinking Machines Connection Machine, which has 64K one-bit processors. At themore » other end of the spectrum, a small number of processors, each built using the fastest available technology and the most sophisticated architecture, are combined. An example of this approach is the Cray X-MP. This type of parallel processing is akin to four woodmen attacking the log with chainsaws.« less

Electrochemical sensing using comparison of voltage-current time differential values during waveform generation and detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2018-01-02

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Structure, Function, and Assembly of Adhesive Organelles by Uropathogenic Bacteria

PubMed Central

Chahales, Peter; Thanassi, David G.

2015-01-01

Bacteria assemble a wide range of adhesive proteins, termed adhesins, to mediate binding to receptors and colonization of surfaces. For pathogenic bacteria, adhesins are critical for early stages of infection, allowing the bacteria to initiate contact with host cells, colonize different tissues, and establish a foothold within the host. The adhesins expressed by a pathogen are also critical for bacterial-bacterial interactions and the formation of bacterial communities such as biofilms. The ability to adhere to host tissues is particularly important for bacteria that colonize sites such as the urinary tract, where the flow of urine functions to maintain sterility by washing away non-adherent pathogens. Adhesins vary from monomeric proteins that are directly anchored to the bacterial surface to polymeric, hairlike fibers that extend out from the cell surface. These latter fibers are termed pili or fimbriae, and were among the first identified virulence factors of uropathogenic Escherichia coli. Studies since then have identified a range of both pilus and non-pilus adhesins that contribute to bacterial colonization of the urinary tract, and have revealed molecular details of the structures, assembly pathways, and functions of these adhesive organelles. In this review, we describe the different types of adhesins expressed by both Gram-negative and Gram-positive uropathogens, what is known about their structures, how they are assembled on the bacterial surface, and the functions of specific adhesins in the pathogenesis of urinary tract infections. PMID:26542038

Hybrid Electro-Optic Processor

DTIC Science & Technology

1991-07-01

This report describes the design of a hybrid electro - optic processor to perform adaptive interference cancellation in radar systems. The processor is...modulator is reported. Included is this report is a discussion of the design, partial fabrication in the laboratory, and partial testing of the hybrid electro ... optic processor. A follow on effort is planned to complete the construction and testing of the processor. The work described in this report is the

JPRS Report, Science & Technology, Europe.

DTIC Science & Technology

1991-04-30

processor in collaboration with Intel . The processor , christened Touchstone, will be used as the core of a parallel computer with 2,000 processors . One of...ELECTRONIQUE HEBDO in French 24 Jan 91 pp 14-15 [Article by Claire Remy: "Everything Set for Neural Signal Processors " first paragraph is ELECTRONIQUE...paving the way for neural signal processors in so doing. The principal advantage of this specific circuit over a neuromimetic software program is

Processor register error correction management

DOEpatents

Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

2016-12-27

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

The CSM testbed matrix processors internal logic and dataflow descriptions

NASA Technical Reports Server (NTRS)

Regelbrugge, Marc E.; Wright, Mary A.

1988-01-01

This report constitutes the final report for subtask 1 of Task 5 of NASA Contract NAS1-18444, Computational Structural Mechanics (CSM) Research. This report contains a detailed description of the coded workings of selected CSM Testbed matrix processors (i.e., TOPO, K, INV, SSOL) and of the arithmetic utility processor AUS. These processors and the current sparse matrix data structures are studied and documented. Items examined include: details of the data structures, interdependence of data structures, data-blocking logic in the data structures, processor data flow and architecture, and processor algorithmic logic flow.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

40 CFR 791.45 - Processors.

Code of Federal Regulations, 2010 CFR

2010-07-01

...) When a test rule or subsequent Federal Register notice pertaining to a test rule expressly obligates processors as well as manufacturers to assume direct testing and data reimbursement responsibilities. (2... processors voluntarily agree to reimburse manufacturers for a portion of test costs. Only those processors...

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, R.; Fischler, M.S.; Husby, D.E.

1991-01-15

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured. 11 figures.

Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor grids

DOEpatents

Chatterjee, Siddhartha [Yorktown Heights, NY; Gunnels, John A [Brewster, NY

2011-11-08

A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by specific processors in the multi-dimensional mesh of parallel processors. The pattern of the designating includes a cyclical repetitive pattern of the parallel processor mesh, as modified to have a skew in at least one dimension so that both a row of data in the array and a column of data in the array map to respective contiguous groupings of the processors such that a dimension of the contiguous groupings is greater than one.

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, Robert; Fischler, Mark S.; Husby, Donald E.

1991-01-01

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.

Variable word length encoder reduces TV bandwith requirements

NASA Technical Reports Server (NTRS)

Sivertson, W. E., Jr.

1965-01-01

Adaptive variable resolution encoding technique provides an adaptive compression pseudo-random noise signal processor for reducing television bandwidth requirements. Complementary processors are required in both the transmitting and receiving systems. The pretransmission processor is analog-to-digital, while the postreception processor is digital-to-analog.

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

PubMed

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Allocating application to group of consecutive processors in fault-tolerant deadlock-free routing path defined by routers obeying same rules for path selection

DOEpatents

Leung, Vitus J [Albuquerque, NM; Phillips, Cynthia A [Albuquerque, NM; Bender, Michael A [East Northport, NY; Bunde, David P [Urbana, IL

2009-07-21

In a multiple processor computing apparatus, directional routing restrictions and a logical channel construct permit fault tolerant, deadlock-free routing. Processor allocation can be performed by creating a linear ordering of the processors based on routing rules used for routing communications between the processors. The linear ordering can assume a loop configuration, and bin-packing is applied to this loop configuration. The interconnection of the processors can be conceptualized as a generally rectangular 3-dimensional grid, and the MC allocation algorithm is applied with respect to the 3-dimensional grid.

Communications systems and methods for subsea processors

DOEpatents

Gutierrez, Jose; Pereira, Luis

2016-04-26

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

NASA Astrophysics Data System (ADS)

Hudec, Ján; Gramatová, Elena

2015-07-01

The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.

Experimental testing of the noise-canceling processor.

PubMed

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

A High Performance VLSI Computer Architecture For Computer Graphics

NASA Astrophysics Data System (ADS)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

NASA Astrophysics Data System (ADS)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

New Modular Ultrasonic Signal Processing Building Blocks for Real-Time Data Acquisition and Post Processing

NASA Astrophysics Data System (ADS)

Weber, Walter H.; Mair, H. Douglas; Jansen, Dion

2003-03-01

A suite of basic signal processors has been developed. These basic building blocks can be cascaded together to form more complex processors without the need for programming. The data structures between each of the processors are handled automatically. This allows a processor built for one purpose to be applied to any type of data such as images, waveform arrays and single values. The processors are part of Winspect Data Acquisition software. The new processors are fast enough to work on A-scan signals live while scanning. Their primary use is to extract features, reduce noise or to calculate material properties. The cascaded processors work equally well on live A-scan displays, live gated data or as a post-processing engine on saved data. Researchers are able to call their own MATLAB or C-code from anywhere within the processor structure. A built-in formula node processor that uses a simple algebraic editor may make external user programs unnecessary. This paper also discusses the problems associated with ad hoc software development and how graphical programming languages can tie up researchers writing software rather than designing experiments.

Array processor architecture connection network

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1982-01-01

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 9 2013-01-01 2013-01-01 false Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 9 2012-01-01 2012-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 9 2014-01-01 2013-01-01 true Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 9 2011-01-01 2011-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G; Salapura, Valentina

2014-12-02

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Noncoherent parallel optical processor for discrete two-dimensional linear transformations.

PubMed

Glaser, I

1980-10-01

We describe a parallel optical processor, based on a lenslet array, that provides general linear two-dimensional transformations using noncoherent light. Such a processor could become useful in image- and signal-processing applications in which the throughput requirements cannot be adequately satisfied by state-of-the-art digital processors. Experimental results that illustrate the feasibility of the processor by demonstrating its use in parallel optical computation of the two-dimensional Walsh-Hadamard transformation are presented.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

NASA Astrophysics Data System (ADS)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

Federal Register 2010, 2011, 2012, 2013, 2014

2012-01-03

... ENVIRONMENTAL PROTECTION AGENCY [FRL-9612-9] Biological Processors of Alabama; Decatur, Morgan... reimbursement of past response costs concerning the Biological Processors of Alabama Superfund Site located in... Ms. Paula V. Painter. Submit your comments by Site name Biological Processors of Alabama Superfund...

BLAS- BASIC LINEAR ALGEBRA SUBPROGRAMS

NASA Technical Reports Server (NTRS)

Krogh, F. T.

1994-01-01

The Basic Linear Algebra Subprogram (BLAS) library is a collection of FORTRAN callable routines for employing standard techniques in performing the basic operations of numerical linear algebra. The BLAS library was developed to provide a portable and efficient source of basic operations for designers of programs involving linear algebraic computations. The subprograms available in the library cover the operations of dot product, multiplication of a scalar and a vector, vector plus a scalar times a vector, Givens transformation, modified Givens transformation, copy, swap, Euclidean norm, sum of magnitudes, and location of the largest magnitude element. Since these subprograms are to be used in an ANSI FORTRAN context, the cases of single precision, double precision, and complex data are provided for. All of the subprograms have been thoroughly tested and produce consistent results even when transported from machine to machine. BLAS contains Assembler versions and FORTRAN test code for any of the following compilers: Lahey F77L, Microsoft FORTRAN, or IBM Professional FORTRAN. It requires the Microsoft Macro Assembler and a math co-processor. The PC implementation allows individual arrays of over 64K. The BLAS library was developed in 1979. The PC version was made available in 1986 and updated in 1988.

Multiple core computer processor with globally-accessible local memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shalf, John; Donofrio, David; Oliker, Leonid

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality ofmore » processor cores.« less

Scalable load balancing for massively parallel distributed Monte Carlo particle transport

DOE Office of Scientific and Technical Information (OSTI.GOV)

O'Brien, M. J.; Brantley, P. S.; Joy, K. I.

2013-07-01

In order to run computer simulations efficiently on massively parallel computers with hundreds of thousands or millions of processors, care must be taken that the calculation is load balanced across the processors. Examining the workload of every processor leads to an unscalable algorithm, with run time at least as large as O(N), where N is the number of processors. We present a scalable load balancing algorithm, with run time 0(log(N)), that involves iterated processor-pair-wise balancing steps, ultimately leading to a globally balanced workload. We demonstrate scalability of the algorithm up to 2 million processors on the Sequoia supercomputer at Lawrencemore » Livermore National Laboratory. (authors)« less

Parallel processor-based raster graphics system architecture

DOEpatents

Littlefield, Richard J.

1990-01-01

An apparatus for generating raster graphics images from the graphics command stream includes a plurality of graphics processors connected in parallel, each adapted to receive any part of the graphics command stream for processing the command stream part into pixel data. The apparatus also includes a frame buffer for mapping the pixel data to pixel locations and an interconnection network for interconnecting the graphics processors to the frame buffer. Through the interconnection network, each graphics processor may access any part of the frame buffer concurrently with another graphics processor accessing any other part of the frame buffer. The plurality of graphics processors can thereby transmit concurrently pixel data to pixel locations in the frame buffer.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

NASA Astrophysics Data System (ADS)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

HPCC Methodologies for Structural Design and Analysis on Parallel and Distributed Computing Platforms

NASA Technical Reports Server (NTRS)

Farhat, Charbel

1998-01-01

In this grant, we have proposed a three-year research effort focused on developing High Performance Computation and Communication (HPCC) methodologies for structural analysis on parallel processors and clusters of workstations, with emphasis on reducing the structural design cycle time. Besides consolidating and further improving the FETI solver technology to address plate and shell structures, we have proposed to tackle the following design related issues: (a) parallel coupling and assembly of independently designed and analyzed three-dimensional substructures with non-matching interfaces, (b) fast and smart parallel re-analysis of a given structure after it has undergone design modifications, (c) parallel evaluation of sensitivity operators (derivatives) for design optimization, and (d) fast parallel analysis of mildly nonlinear structures. While our proposal was accepted, support was provided only for one year.

The LSLE echocardiograph - Commercial hardware aboard Spacelab. [Life Sciences Laboratory Equipment

NASA Technical Reports Server (NTRS)

Schwarz, R.

1983-01-01

The Life Sciences Laboratory Equipment Echocardiograph, a commercial 77020AC Ultrasound Imaging System modified to meet NASA's spacecraft standards, is described. The assembly consists of four models: display and control, scanner, scan converter, and physioamplifiers. Four separate processors communicate over an IEE-488 bus, and the system has more than 6000 individual components on 35 printed circuit cards. Three levels of self test are provided: a short test during power up, a basic test initiated by a front panel switch, and interactive tests for specific routines. Default mode operation further enhances reliability. Modifications of the original system include the replacement of ac power supplies with dc to dc converters, a slide-out keyboard (to prevent accidental operation), Teflon insulated wire, and additional shielding for the ultrasound transducer cable.

Eigensolution of finite element problems in a completely connected parallel architecture

NASA Technical Reports Server (NTRS)

Akl, F.; Morel, M.

1989-01-01

A parallel algorithm is presented for the solution of the generalized eigenproblem in linear elastic finite element analysis. The algorithm is based on a completely connected parallel architecture in which each processor is allowed to communicate with all other processors. The algorithm is successfully implemented on a tightly coupled MIMD parallel processor. A finite element model is divided into m domains each of which is assumed to process n elements. Each domain is then assigned to a processor or to a logical processor (task) if the number of domains exceeds the number of physical processors. The effect of the number of domains, the number of degrees-of-freedom located along the global fronts, and the dimension of the subspace on the performance of the algorithm is investigated. For a 64-element rectangular plate, speed-ups of 1.86, 3.13, 3.18, and 3.61 are achieved on two, four, six, and eight processors, respectively.

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

Parallel grid population

DOEpatents

Wald, Ingo; Ize, Santiago

2015-07-28

Parallel population of a grid with a plurality of objects using a plurality of processors. One example embodiment is a method for parallel population of a grid with a plurality of objects using a plurality of processors. The method includes a first act of dividing a grid into n distinct grid portions, where n is the number of processors available for populating the grid. The method also includes acts of dividing a plurality of objects into n distinct sets of objects, assigning a distinct set of objects to each processor such that each processor determines by which distinct grid portion(s) each object in its distinct set of objects is at least partially bounded, and assigning a distinct grid portion to each processor such that each processor populates its distinct grid portion with any objects that were previously determined to be at least partially bounded by its distinct grid portion.

Sequence information signal processor

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1999-01-01

An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

Conditional load and store in a shared memory

DOEpatents

Blumrich, Matthias A; Ohmacht, Martin

2015-02-03

A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

Code of Federal Regulations, 2011 CFR

2011-04-01

... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

Code of Federal Regulations, 2010 CFR

2010-04-01

... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

Optical Associative Processors For Visual Perception"

NASA Astrophysics Data System (ADS)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

Enabling Future Robotic Missions with Multicore Processors

NASA Technical Reports Server (NTRS)

Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

2011-01-01

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

Hot Chips and Hot Interconnects for High End Computing Systems

NASA Technical Reports Server (NTRS)

Saini, Subhash

2005-01-01

I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

Electrokinetic Stringency Control in Self-Assembled Monolayer-based Biosensors for Multiplex Urinary Tract Infection Diagnosis

PubMed Central

Liu, Tingting; Sin, Mandy L. Y.; Pyne, Jeff D.; Gau, Vincent; Liao, Joseph C.; Wong, Pak Kin

2013-01-01

Rapid detection of bacterial pathogens is critical toward judicious management of infectious diseases. Herein, we demonstrate an in situ electrokinetic stringency control approach for a self-assembled monolayer-based electrochemical biosensor toward urinary tract infection diagnosis. The in situ electrokinetic stringency control technique generates Joule heating induced temperature rise and electrothermal fluid motion directly on the sensor to improve its performance for detecting bacterial 16S rRNA, a phylogenetic biomarker. The dependence of the hybridization efficiency reveals that in situ electrokinetic stringency control is capable of discriminating single-base mismatches. With electrokinetic stringency control, the background noise due to the matrix effects of clinical urine samples can be reduced by 60%. The applicability of the system is demonstrated by multiplex detection of three uropathogenic clinical isolates with similar 16S rRNA sequences. The results demonstrate that electrokinetic stringency control can significantly improve the signal-to-noise ratio of the biosensor for multiplex urinary tract infection diagnosis. PMID:23891989

High-performance ultra-low power VLSI analog processor for data compression

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1996-01-01

An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.

On the relationship between parallel computation and graph embedding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gupta, A.K.

1989-01-01

The problem of efficiently simulating an algorithm designed for an n-processor parallel machine G on an m-processor parallel machine H with n > m arises when parallel algorithms designed for an ideal size machine are simulated on existing machines which are of a fixed size. The author studies this problem when every processor of H takes over the function of a number of processors in G, and he phrases the simulation problem as a graph embedding problem. New embeddings presented address relevant issues arising from the parallel computation environment. The main focus centers around embedding complete binary trees into smaller-sizedmore » binary trees, butterflies, and hypercubes. He also considers simultaneous embeddings of r source machines into a single hypercube. Constant factors play a crucial role in his embeddings since they are not only important in practice but also lead to interesting theoretical problems. All of his embeddings minimize dilation and load, which are the conventional cost measures in graph embeddings and determine the maximum amount of time required to simulate one step of G on H. His embeddings also optimize a new cost measure called ({alpha},{beta})-utilization which characterizes how evenly the processors of H are used by the processors of G. Ideally, the utilization should be balanced (i.e., every processor of H simulates at most (n/m) processors of G) and the ({alpha},{beta})-utilization measures how far off from a balanced utilization the embedding is. He presents embeddings for the situation when some processors of G have different capabilities (e.g. memory or I/O) than others and the processors with different capabilities are to be distributed uniformly among the processors of H. Placing such conditions on an embedding results in an increase in some of the cost measures.« less

17 CFR 249.1001 - Form SIP, for application for registration as a securities information processor or to amend such...

Code of Federal Regulations, 2011 CFR

2011-04-01

... registration as a securities information processor or to amend such an application or registration. 249.1001..., SECURITIES EXCHANGE ACT OF 1934 Form for Registration of, and Reporting by Securities Information Processors § 249.1001 Form SIP, for application for registration as a securities information processor or to amend...

75 FR 39892 - Fisheries of the Exclusive Economic Zone Off Alaska; Community Development Quota Program

Federal Register 2010, 2011, 2012, 2013, 2014

2010-07-13

... Fisheries Act (AFA) trawl catcher/processor sector (otherwise known as the Amendment 80 sector... catcher/processors. Hook-and-line catcher/processors are allocated 48.7 percent of the annual BSAI Pacific... harvest of Pacific cod by hook-and-line catcher/processors, although this is one of the major groundfish...

78 FR 21483 - Joint Industry Plan; Order Approving the Third Amendment to the National Market System Plan to...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-10

... the Securities Information Processors (``SIPs'' or ``Processors'') responsible for consolidation of... Plan. \\9\\ 17 CFR 242.603(b). The Plan refers to this entity as the Processor. \\10\\ See Section I(T) of... Euronext, to Elizabeth M. Murphy, Secretary, Commission, dated May 24, 2012. The Processors would also...

Simulating Synchronous Processors

DTIC Science & Technology

1988-06-01

34f Fvtvru m LABORATORY FOR INMASSACHUSETTSFCOMPUTER SCIENCE TECHNOLOGY MIT/LCS/TM-359 SIMULATING SYNCHRONOUS PROCESSORS Jennifer Lundelius Welch...PROJECT TASK WORK UNIT Arlington, VA 22217 ELEMENT NO. NO. NO ACCESSION NO. 11. TITLE Include Security Classification) Simulating Synchronous Processors...necessary and identify by block number) In this paper we show how a distributed system with synchronous processors and asynchro- nous message delays can

Middle School Pupil Writing and the Word Processor.

ERIC Educational Resources Information Center

Ediger, Marlow

Pupils in middle schools should have ample opportunities to write with the use of word processors. Legible writing in longhand will always be necessary in selected situations but, nevertheless, much drudgery is taken care of when using a word processor. Word processors tend to be very user friendly in that few mechanical skills are needed by the…

17 CFR 249.1001 - Form SIP, for application for registration as a securities information processor or to amend such...

Code of Federal Regulations, 2010 CFR

2010-04-01

... registration as a securities information processor or to amend such an application or registration. 249.1001..., SECURITIES EXCHANGE ACT OF 1934 Form for Registration of, and Reporting by Securities Information Processors § 249.1001 Form SIP, for application for registration as a securities information processor or to amend...

Analog Processor To Solve Optimization Problems

NASA Technical Reports Server (NTRS)

Duong, Tuan A.; Eberhardt, Silvio P.; Thakoor, Anil P.

1993-01-01

Proposed analog processor solves "traveling-salesman" problem, considered paradigm of global-optimization problems involving routing or allocation of resources. Includes electronic neural network and auxiliary circuitry based partly on concepts described in "Neural-Network Processor Would Allocate Resources" (NPO-17781) and "Neural Network Solves 'Traveling-Salesman' Problem" (NPO-17807). Processor based on highly parallel computing solves problem in significantly less time.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, G. H.

1985-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90 percent for sufficiently large problems.

A model for tracking concentration of chemical compounds within a tank of an automatic film processor.

PubMed

Sobol, Wlad T

2002-01-01

A simple kinetic model that describes the time evolution of the chemical concentration of an arbitrary compound within the tank of an automatic film processor is presented. It provides insights into the kinetics of chemistry concentration inside the processor's tank; the results facilitate the tasks of processor tuning and quality control (QC). The model has successfully been used in several troubleshooting sessions of low-volume mammography processors for which maintaining consistent QC tracking was difficult due to fluctuations of bromide levels in the developer tank.

Multithreading in vector processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, B. H.

1984-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90% for sufficiently large problems.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

Neurovision processor for designing intelligent sensors

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

When emotionality trumps reason: a study of individual processing style and juror bias.

PubMed

Gunnell, Justin J; Ceci, Stephen J

2010-01-01

"Cognitive Experiential Self Theory" (CEST) postulates that information-processing proceeds through two pathways, a rational one and an experiential one. The former is characterized by an emphasis on analysis, fact, and logical argument, whereas the latter is characterized by emotional and personal experience. We examined whether individuals influenced by the experiential system (E-processors) are more susceptible to extralegal biases (e.g. defendant attractiveness) than those influenced by the rational system (R-processors). Participants reviewed a criminal trial transcript and defendant profile and determined verdict, sentencing, and extralegal susceptibility. Although E-processors and R-processors convicted attractive defendants at similar rates, E-processors were more likely to convict less attractive defendants. Whereas R-processors did not sentence attractive and less attractive defendants differently, E-processors gave more lenient sentences to attractive defendants and harsher sentences to less attractive defendants. E-processors were also more likely to report that extralegal factors would change their verdicts. Further, the degree to which emotionality trumped rationality within an individual, as measured by a novel scoring method, linearly correlated with harsher sentences and extralegal influence. In sum, the results support an "unattractive harshness" effect during guilt determination, an attraction leniency effect during sentencing and increased susceptibility to extralegal factors within E-processors. Copyright © 2010 John Wiley & Sons, Ltd. Copyright © 2010 John Wiley & Sons, Ltd.

Soft-core processor study for node-based architectures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James

2008-09-01

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor builtmore » out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.« less

Development of small scale cluster computer for numerical analysis

NASA Astrophysics Data System (ADS)

Zulkifli, N. H. N.; Sapit, A.; Mohammed, A. N.

2017-09-01

In this study, two units of personal computer were successfully networked together to form a small scale cluster. Each of the processor involved are multicore processor which has four cores in it, thus made this cluster to have eight processors. Here, the cluster incorporate Ubuntu 14.04 LINUX environment with MPI implementation (MPICH2). Two main tests were conducted in order to test the cluster, which is communication test and performance test. The communication test was done to make sure that the computers are able to pass the required information without any problem and were done by using simple MPI Hello Program where the program written in C language. Additional, performance test was also done to prove that this cluster calculation performance is much better than single CPU computer. In this performance test, four tests were done by running the same code by using single node, 2 processors, 4 processors, and 8 processors. The result shows that with additional processors, the time required to solve the problem decrease. Time required for the calculation shorten to half when we double the processors. To conclude, we successfully develop a small scale cluster computer using common hardware which capable of higher computing power when compare to single CPU processor, and this can be beneficial for research that require high computing power especially numerical analysis such as finite element analysis, computational fluid dynamics, and computational physics analysis.

78 FR 74063 - Fisheries of the Exclusive Economic Zone Off Alaska; Bering Sea and Aleutian Islands; 2014 and...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-12-10

...; catcher/ processor--40 percent; and motherships--10 percent. Under Sec. 679.20(a)(5)(iii)(B)(2)(i) and (ii... sector, 40 percent to the catcher/processor sector, and 10 percent to the mothership sector. In the.../processor sector will be available for harvest by AFA catcher vessels with catcher/ processor sector...

Processor architecture for airborne SAR systems

NASA Technical Reports Server (NTRS)

Glass, C. M.

1983-01-01

Digital processors for spaceborne imaging radars and application of the technology developed for airborne SAR systems are considered. Transferring algorithms and implementation techniques from airborne to spaceborne SAR processors offers obvious advantages. The following topics are discussed: (1) a quantification of the differences in processing algorithms for airborne and spaceborne SARs; and (2) an overview of three processors for airborne SAR systems.

Yes! An object-oriented compiler compiler (YOOCC)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Avotins, J.; Mingins, C.; Schmidt, H.

1995-12-31

Grammar-based processor generation is one of the most widely studied areas in language processor construction. However, there have been very few approaches to date that reconcile object-oriented principles, processor generation, and an object-oriented language. Pertinent here also. is that currently to develop a processor using the Eiffel Parse libraries requires far too much time to be expended on tasks that can be automated. For these reasons, we have developed YOOCC (Yes! an Object-Oriented Compiler Compiler), which produces a processor framework from a grammar using an enhanced version of the Eiffel Parse libraries, incorporating the ideas hypothesized by Meyer, and Grapemore » and Walden, as well as many others. Various essential changes have been made to the Eiffel Parse libraries. Examples are presented to illustrate the development of a processor using YOOCC, and it is concluded that the Eiffel Parse libraries are now not only an intelligent, but also a productive option for processor construction.« less

Effect of poor control of film processors on mammographic image quality.

PubMed

Kimme-Smith, C; Sun, H; Bassett, L W; Gold, R H

1992-11-01

With the increasingly stringent standards of image quality in mammography, film processor quality control is especially important. Current methods are not sufficient for ensuring good processing. The authors used a sensitometer and densitometer system to evaluate the performance of 22 processors at 16 mammographic facilities. Standard sensitometric values of two films were established, and processor performance was assessed for variations from these standards. Developer chemistry of each processor was analyzed and correlated with its sensitometric values. Ten processors were retested, and nine were found to be out of calibration. The developer components of hydroquinone, sulfites, bromide, and alkalinity varied the most, and low concentrations of hydroquinone were associated with lower average gradients at two facilities. Use of the sensitometer and densitometer system helps identify out-of-calibration processors, but further study is needed to correlate sensitometric values with developer component values. The authors believe that present quality control would be improved if sensitometric or other tests could be used to identify developer components that are out of calibration.

Automatic film processors' quality control test in Greek military hospitals.

PubMed

Lymberis, C; Efstathopoulos, E P; Manetou, A; Poudridis, G

1993-04-01

The two major military radiology installations (Athens, Greece) using a total of 15 automatic film processors were assessed using the 21-step-wedge method. The results of quality control in all these processors are presented. The parameters measured under actual working conditions were base and fog, contrast and speed. Base and fog as well as speed displayed large variations with average values generally higher than acceptable, whilst contrast displayed greater stability. Developer temperature was measured daily during the test and was found to be outside the film manufacturers' recommended limits in nine of the 15 processors. In only one processor did film passing time vary on an every day basis and this was due to maloperation. Developer pH test was not part of the daily monitoring service being performed every 5 days for each film processor and found to be in the range 9-12; 10 of the 15 processors presented pH values outside the limits specified by the film manufacturers.

A high-accuracy optical linear algebra processor for finite element applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Optimal processor assignment for pipeline computations

NASA Technical Reports Server (NTRS)

Nicol, David M.; Simha, Rahul; Choudhury, Alok N.; Narahari, Bhagirath

1991-01-01

The availability of large scale multitasked parallel architectures introduces the following processor assignment problem for pipelined computations. Given a set of tasks and their precedence constraints, along with their experimentally determined individual responses times for different processor sizes, find an assignment of processor to tasks. Two objectives are of interest: minimal response given a throughput requirement, and maximal throughput given a response time requirement. These assignment problems differ considerably from the classical mapping problem in which several tasks share a processor; instead, it is assumed that a large number of processors are to be assigned to a relatively small number of tasks. Efficient assignment algorithms were developed for different classes of task structures. For a p processor system and a series parallel precedence graph with n constituent tasks, an O(np2) algorithm is provided that finds the optimal assignment for the response time optimization problem; it was found that the assignment optimizing the constrained throughput in O(np2log p) time. Special cases of linear, independent, and tree graphs are also considered.

Array processor architecture

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Extended performance electric propulsion power processor design study. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30cm ion thruster power processor with a beam supply rating of 2.2kW to 10kW. Extensions in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. Preliminary electrical design, mechanical design, and thermal analysis were performed on a 6kW power transformer for the beam supply. Bi-Mod mechanical, structural, and thermal control configurations were evaluated for the power processor, and preliminary estimates of mechanical weight were determined. A program development plan was formulated that outlines the work breakdown structure for the development, qualification and fabrication of the power processor flight hardware.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Efficient Interconnection Schemes for VLSI and Parallel Computation

DTIC Science & Technology

1989-08-01

Definition: Let R be a routing network. A set S of wires in R is a (directed) cut if it partitions the network into two sets of processors A and B ...such that every path from a processor in A to a processor in B contains a wire in S. The capacity cap(S) is the number of wires in the cut. For a set of...messages M, define the load load(M, S) of M on a cut S to be the number of messages in M from a processor in A to a processor in B . The load factor

Hypercluster - Parallel processing for computational mechanics

NASA Technical Reports Server (NTRS)

Blech, Richard A.

1988-01-01

An account is given of the development status, performance capabilities and implications for further development of NASA-Lewis' testbed 'hypercluster' parallel computer network, in which multiple processors communicate through a shared memory. Processors have local as well as shared memory; the hypercluster is expanded in the same manner as the hypercube, with processor clusters replacing the normal single processor node. The NASA-Lewis machine has three nodes with a vector personality and one node with a scalar personality. Each of the vector nodes uses four board-level vector processors, while the scalar node uses four general-purpose microcomputer boards.

The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor

DTIC Science & Technology

2015-06-13

The Berkeley Out-of-Order Machine (BOOM): An Industry- Competitive, Synthesizable, Parameterized RISC-V Processor Christopher Celio David A...Synthesizable, Parameterized RISC-V Processor Christopher Celio, David Patterson, and Krste Asanović University of California, Berkeley, California 94720...Order Machine BOOM is a synthesizable, parameterized, superscalar out- of-order RISC-V core designed to serve as the prototypical baseline processor

A Medical Language Processor for Two Indo-European Languages

PubMed Central

Nhan, Ngo Thanh; Sager, Naomi; Lyman, Margaret; Tick, Leo J.; Borst, François; Su, Yun

1989-01-01

The syntax and semantics of clinical narrative across Indo-European languages are quite similar, making it possible to envison a single medical language processor that can be adapted for different European languages. The Linguistic String Project of New York University is continuing the development of its Medical Language Processor in this direction. The paper describes how the processor operates on English and French.

Performance Modeling of the ADA Rendezvous

DTIC Science & Technology

1991-10-01

queueing network of figure 2, SERVERTASK can complete only one rendezvous at a time. Thus, the rate that the rendezvous requests are processed at the... Network 1, SERVERTASK competes with the traffic tasks of Server Processor. Each time SERVERTASK gains access to the processor, SERVERTASK completes...Client Processor Server Processor Software Server Nek Netork2 Figure 10. A conceptualization of the algorithm. The SERVERTASK software server of Network 2

A parallel algorithm for 2D visco-acoustic frequency-domain full-waveform inversion: application to a dense OBS data set

NASA Astrophysics Data System (ADS)

Sourbier, F.; Operto, S.; Virieux, J.

2006-12-01

We present a distributed-memory parallel algorithm for 2D visco-acoustic full-waveform inversion of wide-angle seismic data. Our code is written in fortran90 and use MPI for parallelism. The algorithm was applied to real wide-angle data set recorded by 100 OBSs with a 1-km spacing in the eastern-Nankai trough (Japan) to image the deep structure of the subduction zone. Full-waveform inversion is applied sequentially to discrete frequencies by proceeding from the low to the high frequencies. The inverse problem is solved with a classic gradient method. Full-waveform modeling is performed with a frequency-domain finite-difference method. In the frequency-domain, solving the wave equation requires resolution of a large unsymmetric system of linear equations. We use the massively parallel direct solver MUMPS (http://www.enseeiht.fr/irit/apo/MUMPS) for distributed-memory computer to solve this system. The MUMPS solver is based on a multifrontal method for the parallel factorization. The MUMPS algorithm is subdivided in 3 main steps: a symbolic analysis step that performs re-ordering of the matrix coefficients to minimize the fill-in of the matrix during the subsequent factorization and an estimation of the assembly tree of the matrix. Second, the factorization is performed with dynamic scheduling to accomodate numerical pivoting and provides the LU factors distributed over all the processors. Third, the resolution is performed for multiple sources. To compute the gradient of the cost function, 2 simulations per shot are required (one to compute the forward wavefield and one to back-propagate residuals). The multi-source resolutions can be performed in parallel with MUMPS. In the end, each processor stores in core a sub-domain of all the solutions. These distributed solutions can be exploited to compute in parallel the gradient of the cost function. Since the gradient of the cost function is a weighted stack of the shot and residual solutions of MUMPS, each processor computes the corresponding sub-domain of the gradient. In the end, the gradient is centralized on the master processor using a collective communation. The gradient is scaled by the diagonal elements of the Hessian matrix. This scaling is computed only once per frequency before the first iteration of the inversion. Estimation of the diagonal terms of the Hessian requires performing one simulation per non redondant shot and receiver position. The same strategy that the one used for the gradient is used to compute the diagonal Hessian in parallel. This algorithm was applied to a dense wide-angle data set recorded by 100 OBSs in the eastern Nankai trough, offshore Japan. Thirteen frequencies ranging from 3 and 15 Hz were inverted. Tweny iterations per frequency were computed leading to 260 tomographic velocity models of increasing resolution. The velocity model dimensions are 105 km x 25 km corresponding to a finite-difference grid of 4201 x 1001 grid with a 25-m grid interval. The number of shot was 1005 and the number of inverted OBS gathers was 93. The inversion requires 20 days on 6 32-bits bi-processor nodes with 4 Gbytes of RAM memory per node when only the LU factorization is performed in parallel. Preliminary estimations of the time required to perform the inversion with the fully-parallelized code is 6 and 4 days using 20 and 50 processors respectively.

A Parallel Algorithm for Contact in a Finite Element Hydrocode

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pierce, Timothy G.

A parallel algorithm is developed for contact/impact of multiple three dimensional bodies undergoing large deformation. As time progresses the relative positions of contact between the multiple bodies changes as collision and sliding occurs. The parallel algorithm is capable of tracking these changes and enforcing an impenetrability constraint and momentum transfer across the surfaces in contact. Portions of the various surfaces of the bodies are assigned to the processors of a distributed-memory parallel machine in an arbitrary fashion, known as the primary decomposition. A secondary, dynamic decomposition is utilized to bring opposing sections of the contacting surfaces together on the samemore » processors, so that opposing forces may be balanced and the resultant deformation of the bodies calculated. The secondary decomposition is accomplished and updated using only local communication with a limited subset of neighbor processors. Each processor represents both a domain of the primary decomposition and a domain of the secondary, or contact, decomposition. Thus each processor has four sets of neighbor processors: (a) those processors which represent regions adjacent to it in the primary decomposition, (b) those processors which represent regions adjacent to it in the contact decomposition, (c) those processors which send it the data from which it constructs its contact domain, and (d) those processors to which it sends its primary domain data, from which they construct their contact domains. The latter three of these neighbor sets change dynamically as the simulation progresses. By constraining all communication to these sets of neighbors, all global communication, with its attendant nonscalable performance, is avoided. A set of tests are provided to measure the degree of scalability achieved by this algorithm on up to 1024 processors. Issues related to the operating system of the test platform which lead to some degradation of the results are analyzed. This algorithm has been implemented as the contact capability of the ALE3D multiphysics code, and is currently in production use.« less

Automobile Crash Sensor Signal Processor

DOT National Transportation Integrated Search

1973-11-01

The crash sensor signal processor described interfaces between an automobile-installed doppler radar and an air bag activating solenoid or equivalent electromechanical device. The processor utilizes both digital and analog techniques to produce an ou...

Software reconfigurable processor technologies: the key to long-life infrastructure for future space missions

NASA Technical Reports Server (NTRS)

Srinivasan, J.; Farrington, A.; Gray, A.

2001-01-01

They present an overview of long-life reconfigurable processor technologies and of a specific architecture for implementing a software reconfigurable (software-defined) network processor for space applications.

Multiprocessing on supercomputers for computational aerodynamics

NASA Technical Reports Server (NTRS)

Yarrow, Maurice; Mehta, Unmeel B.

1990-01-01

Very little use is made of multiple processors available on current supercomputers (computers with a theoretical peak performance capability equal to 100 MFLOPs or more) in computational aerodynamics to significantly improve turnaround time. The productivity of a computer user is directly related to this turnaround time. In a time-sharing environment, the improvement in this speed is achieved when multiple processors are used efficiently to execute an algorithm. The concept of multiple instructions and multiple data (MIMD) through multi-tasking is applied via a strategy which requires relatively minor modifications to an existing code for a single processor. Essentially, this approach maps the available memory to multiple processors, exploiting the C-FORTRAN-Unix interface. The existing single processor code is mapped without the need for developing a new algorithm. The procedure for building a code utilizing this approach is automated with the Unix stream editor. As a demonstration of this approach, a Multiple Processor Multiple Grid (MPMG) code is developed. It is capable of using nine processors, and can be easily extended to a larger number of processors. This code solves the three-dimensional, Reynolds averaged, thin-layer and slender-layer Navier-Stokes equations with an implicit, approximately factored and diagonalized method. The solver is applied to generic oblique-wing aircraft problem on a four processor Cray-2 computer. A tricubic interpolation scheme is developed to increase the accuracy of coupling of overlapped grids. For the oblique-wing aircraft problem, a speedup of two in elapsed (turnaround) time is observed in a saturated time-sharing environment.

Database for LDV Signal Processor Performance Analysis

NASA Technical Reports Server (NTRS)

Baker, Glenn D.; Murphy, R. Jay; Meyers, James F.

1989-01-01

A comparative and quantitative analysis of various laser velocimeter signal processors is difficult because standards for characterizing signal bursts have not been established. This leaves the researcher to select a signal processor based only on manufacturers' claims without the benefit of direct comparison. The present paper proposes the use of a database of digitized signal bursts obtained from a laser velocimeter under various configurations as a method for directly comparing signal processors.

The Use of a Microcomputer Based Array Processor for Real Time Laser Velocimeter Data Processing

NASA Technical Reports Server (NTRS)

Meyers, James F.

1990-01-01

The application of an array processor to laser velocimeter data processing is presented. The hardware is described along with the method of parallel programming required by the array processor. A portion of the data processing program is described in detail. The increase in computational speed of a microcomputer equipped with an array processor is illustrated by comparative testing with a minicomputer.

Contextual classification on a CDC Flexible Processor system. [for photomapped remote sensing data

NASA Technical Reports Server (NTRS)

Smith, B. W.; Siegel, H. J.; Swain, P. H.

1981-01-01

A potential hardware organization for the Flexible Processor Array is presented. An algorithm that implements a contextual classifier for remote sensing data analysis is given, along with uniprocessor classification algorithms. The Flexible Processor algorithm is provided, as are simulated timings for contextual classifiers run on the Flexible Processor Array and another system. The timings are analyzed for context neighborhoods of sizes three and nine.

Effect of processor temperature on film dosimetry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Srivastava, Shiv P.; Das, Indra J., E-mail: idas@iupui.edu

2012-07-01

Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d{sub max.}, 10 Multiplication-Sign 10 cm{sup 2}, 100 cm) to a given dose. Anmore » automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4-40.6 Degree-Sign C (85-105 Degree-Sign F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.« less

On the Efficacy of Source Code Optimizations for Cache-Based Systems

NASA Technical Reports Server (NTRS)

VanderWijngaart, Rob F.; Saphir, William C.

1998-01-01

Obtaining high performance without machine-specific tuning is an important goal of scientific application programmers. Since most scientific processing is done on commodity microprocessors with hierarchical memory systems, this goal of "portable performance" can be achieved if a common set of optimization principles is effective for all such systems. It is widely believed, or at least hoped, that portable performance can be realized. The rule of thumb for optimization on hierarchical memory systems is to maximize temporal and spatial locality of memory references by reusing data and minimizing memory access stride. We investigate the effects of a number of optimizations on the performance of three related kernels taken from a computational fluid dynamics application. Timing the kernels on a range of processors, we observe an inconsistent and often counterintuitive impact of the optimizations on performance. In particular, code variations that have a positive impact on one architecture can have a negative impact on another, and variations expected to be unimportant can produce large effects. Moreover, we find that cache miss rates - as reported by a cache simulation tool, and confirmed by hardware counters - only partially explain the results. By contrast, the compiler-generated assembly code provides more insight by revealing the importance of processor-specific instructions and of compiler maturity, both of which strongly, and sometimes unexpectedly, influence performance. We conclude that it is difficult to obtain performance portability on modern cache-based computers, and comment on the implications of this result.

On the Efficacy of Source Code Optimizations for Cache-Based Systems

NASA Technical Reports Server (NTRS)

VanderWijngaart, Rob F.; Saphir, William C.; Saini, Subhash (Technical Monitor)

1998-01-01

Obtaining high performance without machine-specific tuning is an important goal of scientific application programmers. Since most scientific processing is done on commodity microprocessors with hierarchical memory systems, this goal of "portable performance" can be achieved if a common set of optimization principles is effective for all such systems. It is widely believed, or at least hoped, that portable performance can be realized. The rule of thumb for optimization on hierarchical memory systems is to maximize temporal and spatial locality of memory references by reusing data and minimizing memory access stride. We investigate the effects of a number of optimizations on the performance of three related kernels taken from a computational fluid dynamics application. Timing the kernels on a range of processors, we observe an inconsistent and often counterintuitive impact of the optimizations on performance. In particular, code variations that have a positive impact on one architecture can have a negative impact on another, and variations expected to be unimportant can produce large effects. Moreover, we find that cache miss rates-as reported by a cache simulation tool, and confirmed by hardware counters-only partially explain the results. By contrast, the compiler-generated assembly code provides more insight by revealing the importance of processor-specific instructions and of compiler maturity, both of which strongly, and sometimes unexpectedly, influence performance. We conclude that it is difficult to obtain performance portability on modern cache-based computers, and comment on the implications of this result.

Current Controller for Multi-level Front-end Converter and Its Digital Implementation Considerations on Three-level Flying Capacitor Topology

NASA Astrophysics Data System (ADS)

Tekwani, P. N.; Shah, M. T.

2017-10-01

This paper presents behaviour analysis and digital implementation of current error space phasor based hysteresis controller applied to three-phase three-level flying capacitor converter as front-end topology. The controller is self-adaptive in nature, and takes the converter from three-level to two-level mode of operation and vice versa, following various trajectories of sector change with the change in reference dc-link voltage demanded by the load. It keeps current error space phasor within the prescribed hexagonal boundary. During the contingencies, the proposed controller takes the converter in over modulation mode to meet the load demand, and once the need is satisfied, controller brings back the converter in normal operating range. Simulation results are presented to validate behaviour of controller to meet the said contingencies. Unity power factor is assured by proposed controller with low current harmonic distortion satisfying limits prescribed in IEEE 519-2014. Proposed controller is implemented using TMS320LF2407 16-bit fixed-point digital signal processor. Detailed analysis of numerical format to avoid overflow of sensed variables in processor, and per-unit model implementation in software are discussed and hardware results are presented at various stages of signal conditioning to validate the experimental setup. Control logic for the generation of reference currents is implemented in TMS320LF2407A using assembly language and experimental results are also presented for the same.

Cargo Movement Operations System (CMOS). Requirements Traceability Matrix Increment II

DTIC Science & Technology

1990-05-17

NO [ ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No. Number Comment 1. C-i SS0-3 Change "workstation" to "processor". 2. C-2 SS0009 Change "workstation" to "processor". SS0016 3. C-6 SS0032 Change "workstation" to "processor". SS0035 4. C-9 SS0063 Add comma after "e.g." 5. C-i SS0082 Change "workstation" to "processor". 6. C-17 SS0131 Change "workstation" to "processor". SS0132 7. C-28 SS0242 Change "workstation"

A high performance linear equation solver on the VPP500 parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakanishi, Makoto; Ina, Hiroshi; Miura, Kenichi

1994-12-31

This paper describes the implementation of two high performance linear equation solvers developed for the Fujitsu VPP500, a distributed memory parallel supercomputer system. The solvers take advantage of the key architectural features of VPP500--(1) scalability for an arbitrary number of processors up to 222 processors, (2) flexible data transfer among processors provided by a crossbar interconnection network, (3) vector processing capability on each processor, and (4) overlapped computation and transfer. The general linear equation solver based on the blocked LU decomposition method achieves 120.0 GFLOPS performance with 100 processors in the LIN-PACK Highly Parallel Computing benchmark.

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Protein misfolding, congophilia, oligomerization, and defective amyloid processing in preeclampsia.

PubMed

Buhimschi, Irina A; Nayeri, Unzila A; Zhao, Guomao; Shook, Lydia L; Pensalfini, Anna; Funai, Edmund F; Bernstein, Ira M; Glabe, Charles G; Buhimschi, Catalin S

2014-07-16

Preeclampsia is a pregnancy-specific disorder of unknown etiology and a leading contributor to maternal and perinatal morbidity and mortality worldwide. Because there is no cure other than delivery, preeclampsia is the leading cause of iatrogenic preterm birth. We show that preeclampsia shares pathophysiologic features with recognized protein misfolding disorders. These features include urine congophilia (affinity for the amyloidophilic dye Congo red), affinity for conformational state-dependent antibodies, and dysregulation of prototype proteolytic enzymes involved in amyloid precursor protein (APP) processing. Assessment of global protein misfolding load in pregnancy based on urine congophilia (Congo red dot test) carries diagnostic and prognostic potential for preeclampsia. We used conformational state-dependent antibodies to demonstrate the presence of generic supramolecular assemblies (prefibrillar oligomers and annular protofibrils), which vary in quantitative and qualitative representation with preeclampsia severity. In the first attempt to characterize the preeclampsia misfoldome, we report that the urine congophilic material includes proteoforms of ceruloplasmin, immunoglobulin free light chains, SERPINA1, albumin, interferon-inducible protein 6-16, and Alzheimer's β-amyloid. The human placenta abundantly expresses APP along with prototype APP-processing enzymes, of which the α-secretase ADAM10, the β-secretases BACE1 and BACE2, and the γ-secretase presenilin-1 were all up-regulated in preeclampsia. The presence of β-amyloid aggregates in placentas of women with preeclampsia and fetal growth restriction further supports the notion that this condition should join the growing list of protein conformational disorders. If these aggregates play a pathophysiologic role, our findings may lead to treatment for preeclampsia. Copyright © 2014, American Association for the Advancement of Science.

A digital retina-like low-level vision processor.

PubMed

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Simulation of a master-slave event set processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comfort, J.C.

1984-03-01

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. The paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principal processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation program modeling this system was constructed, and was run with tracemore » output taken from two different simulation programs. Output from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and interprocessor communication times). A comparison between actual and simulation run times for a one-processor system was used to assist in the validation of the simulation. 7 references.« less

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Implementing direct, spatially isolated problems on transputer networks

NASA Technical Reports Server (NTRS)

Ellis, Graham K.

1988-01-01

Parametric studies were performed on transputer networks of up to 40 processors to determine how to implement and maximize the performance of the solution of problems where no processor-to-processor data transfer is required for the problem solution (spatially isolated). Two types of problems are investigated a computationally intensive problem where the solution required the transmission of 160 bytes of data through the parallel network, and a communication intensive example that required the transmission of 3 Mbytes of data through the network. This data consists of solutions being sent back to the host processor and not intermediate results for another processor to work on. Studies were performed on both integer and floating-point transputers. The latter features an on-chip floating-point math unit and offers approximately an order of magnitude performance increase over the integer transputer on real valued computations. The results indicate that a minimum amount of work is required on each node per communication to achieve high network speedups (efficiencies). The floating-point processor requires approximately an order of magnitude more work per communication than the integer processor because of the floating-point unit's increased computing capacity.

Support for Diagnosis of Custom Computer Hardware

NASA Technical Reports Server (NTRS)

Molock, Dwaine S.

2008-01-01

The Coldfire SDN Diagnostics software is a flexible means of exercising, testing, and debugging custom computer hardware. The software is a set of routines that, collectively, serve as a common software interface through which one can gain access to various parts of the hardware under test and/or cause the hardware to perform various functions. The routines can be used to construct tests to exercise, and verify the operation of, various processors and hardware interfaces. More specifically, the software can be used to gain access to memory, to execute timer delays, to configure interrupts, and configure processor cache, floating-point, and direct-memory-access units. The software is designed to be used on diverse NASA projects, and can be customized for use with different processors and interfaces. The routines are supported, regardless of the architecture of a processor that one seeks to diagnose. The present version of the software is configured for Coldfire processors on the Subsystem Data Node processor boards of the Solar Dynamics Observatory. There is also support for the software with respect to Mongoose V, RAD750, and PPC405 processors or their equivalents.

Methods and Devices for Space Optical Communications Using Laser Beams

NASA Technical Reports Server (NTRS)

Goorjian, Peter M. (Inventor)

2018-01-01

Light is used to communicate between objects separated by a large distance. Light beams are received in a telescopic lens assembly positioned in front of a cat's-eye lens. The light can thereby be received at various angles to be output by the cat's-eye lens to a focal plane of the cat's-eye lens, the position of the light beams upon the focal plane corresponding to the angle of the beam received. Lasers and photodetectors are distributed along this focal plane. A processor receives signals from the photodetectors, and selectively signal lasers positioned proximate the photodetectors detecting light, in order to transmit light encoding data through the cat's-eye lens and also through a telescopic lens back in the direction of the received light beams, which direction corresponds to a location upon the focal plane of the transmitting lasers.

Microgravity particle reduction system

NASA Technical Reports Server (NTRS)

Brandon, Vanessa; Joslin, Michelle; Mateo, Lili; Tubbs, Tracey

1988-01-01

The Controlled Ecological Life Support System (CELSS) project, sponsored by NASA, is assembling the knowledge required to design, construct, and operate a system which will grow and process higher plants in space for the consumption by crew members of a space station on a long term space mission. The problem of processing dry granular organic materials in microgravity is discussed. For the purpose of research and testing, wheat was chosen as the granular material to be ground into flour. Possible systems which were devised to transport wheat grains into the food processor, mill the wheat into flour, and transport the flour to the food preparation system are described. The systems were analyzed and compared and two satisfactory systems were chosen. Prototypes of the two preferred systems are to be fabricated next semester. They will be tested under simulated microgravity conditions and revised for maximum effectiveness.

A distributed microcomputer-controlled system for data acquisition and power spectral analysis of EEG.

PubMed

Vo, T D; Dwyer, G; Szeto, H H

1986-04-01

A relatively powerful and inexpensive microcomputer-based system for the spectral analysis of the EEG is presented. High resolution and speed is achieved with the use of recently available large-scale integrated circuit technology with enhanced functionality (INTEL Math co-processors 8087) which can perform transcendental functions rapidly. The versatility of the system is achieved with a hardware organization that has distributed data acquisition capability performed by the use of a microprocessor-based analog to digital converter with large resident memory (Cyborg ISAAC-2000). Compiled BASIC programs and assembly language subroutines perform on-line or off-line the fast Fourier transform and spectral analysis of the EEG which is stored as soft as well as hard copy. Some results obtained from test application of the entire system in animal studies are presented.

Space Environments Testbed

NASA Technical Reports Server (NTRS)

Leucht, David K.; Koslosky, Marie J.; Kobe, David L.; Wu, Jya-Chang C.; Vavra, David A.

2011-01-01

The Space Environments Testbed (SET) is a flight controller data system for the Common Carrier Assembly. The SET-1 flight software provides the command, telemetry, and experiment control to ground operators for the SET-1 mission. Modes of operation (see dia gram) include: a) Boot Mode that is initiated at application of power to the processor card, and runs memory diagnostics. It may be entered via ground command or autonomously based upon fault detection. b) Maintenance Mode that allows for limited carrier health monitoring, including power telemetry monitoring on a non-interference basis. c) Safe Mode is a predefined, minimum power safehold configuration with power to experiments removed and carrier functionality minimized. It is used to troubleshoot problems that occur during flight. d) Operations Mode is used for normal experiment carrier operations. It may be entered only via ground command from Safe Mode.

Command system output bit verification

NASA Technical Reports Server (NTRS)

Odd, C. W.; Abbate, S. F.

1981-01-01

An automatic test was developed to test the ability of the deep space station (DSS) command subsystem and exciter to generate and radiate, from the exciter, the correct idle bit sequence for a given flight project or to store and radiate received command data elements and files without alteration. This test, called the command system output bit verification test, is an extension of the command system performance test (SPT) and can be selected as an SPT option. The test compares the bit stream radiated from the DSS exciter with reference sequences generated by the SPT software program. The command subsystem and exciter are verified when the bit stream and reference sequences are identical. It is a key element of the acceptance testing conducted on the command processor assembly (CPA) operational program (DMC-0584-OP-G) prior to its transfer from development to operations.

Molecular processors: from qubits to fuzzy logic.

PubMed

Gentili, Pier Luigi

2011-03-14

Single molecules or their assemblies are information processing devices. Herein it is demonstrated how it is possible to process different types of logic through molecules. As long as decoherent effects are maintained far away from a pure quantum mechanical system, quantum logic can be processed. If the collapse of superimposed or entangled wavefunctions is unavoidable, molecules can still be used to process either crisp (binary or multi-valued) or fuzzy logic. The way for implementing fuzzy inference engines is declared and it is supported by the examples of molecular fuzzy logic systems devised so far. Fuzzy logic is drawing attention in the field of artificial intelligence, because it models human reasoning quite well. This ability may be due to some structural analogies between a fuzzy logic system and the human nervous system. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Verification of a Proposed Clinical Electroacoustic Test Protocol for Personal Digital Modulation Receivers Coupled to Cochlear Implant Sound Processors.

PubMed

Nair, Erika L; Sousa, Rhonda; Wannagot, Shannon

Guidelines established by the AAA currently recommend behavioral testing when fitting frequency modulated (FM) systems to individuals with cochlear implants (CIs). A protocol for completing electroacoustic measures has not yet been validated for personal FM systems or digital modulation (DM) systems coupled to CI sound processors. In response, some professionals have used or altered the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting FM systems to CI sound processors. More recently steps were outlined in a proposed protocol. The purpose of this research is to review and compare the electroacoustic test measures outlined in a 2013 article by Schafer and colleagues in the Journal of the American Academy of Audiology titled "A Proposed Electroacoustic Test Protocol for Personal FM Receivers Coupled to Cochlear Implant Sound Processors" to the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting DM systems to CI users. Electroacoustic measures were conducted on 71 CI sound processors and Phonak Roger DM systems using a proposed protocol and an adapted AAA protocol. Phonak's recommended default receiver gain setting was used for each CI sound processor manufacturer and adjusted if necessary to achieve transparency. Electroacoustic measures were conducted on Cochlear and Advanced Bionics (AB) sound processors. In this study, 28 Cochlear Nucleus 5/CP810 sound processors, 26 Cochlear Nucleus 6/CP910 sound processors, and 17 AB Naida CI Q70 sound processors were coupled in various combinations to Phonak Roger DM dedicated receivers (25 Phonak Roger 14 receivers-Cochlear dedicated receiver-and 9 Phonak Roger 17 receivers-AB dedicated receiver) and 20 Phonak Roger Inspiro transmitters. Employing both the AAA and the Schafer et al protocols, electroacoustic measurements were conducted with the Audioscan Verifit in a clinical setting on 71 CI sound processors and Phonak Roger DM systems to determine transparency and verify FM advantage, comparing speech inputs (65 dB SPL) in an effort to achieve equal outputs. If transparency was not achieved at Phonak's recommended default receiver gain, adjustments were made to the receiver gain. The integrity of the signal was monitored with the appropriate manufacturer's monitor earphones. Using the AAA hearing aid protocol, 50 of the 71 CI sound processors achieved transparency, and 59 of the 71 CI sound processors achieved transparency when using the proposed protocol at Phonak's recommended default receiver gain. After the receiver gain was adjusted, 3 of 21 CI sound processors still did not meet transparency using the AAA protocol, and 2 of 12 CI sound processors still did not meet transparency using the Schafer et al proposed protocol. Both protocols were shown to be effective in taking reliable electroacoustic measurements and demonstrate transparency. Both protocols are felt to be clinically feasible and to address the needs of populations that are unable to reliably report regarding the integrity of their personal DM systems. American Academy of Audiology

Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,

DTIC Science & Technology

2006-07-26

is, and the control laws the user implements to control it. The flight control system board will contain the processor selected for this system...Unit (IMU). The IMU contains solid-state gyros and accelerometers and uses these to determine the attitude of the UAV within the three dimensions of...multiple-UAV swarming for combat support operations. The mission processor board will contain the processor selected to execute the mission

Hybrid Optical Processor

DTIC Science & Technology

1990-08-01

LCTVs) ..................... 17 2.14 JOINT FOURIER TRANSFORM PROCESSOR .................. 18 2.15 HOLOGRAPHIC ASSOCIATIVE MEMORY USING A MICRO ...RADC-TR-90-256 Final Technical Report August1990 AD-A227 163 HYBRID OPTICAL PROCESSOR Dove Electronics, Inc. J.F. Dove, F.T .S. Yu, C. Eldering...ANM SUSUE & FUNDING NUMBERS C - F19628-87-C-0086 HYBRID OPTICAL PROCESSOR PE - 61102F PR - 2305 &AUThNOA TA - J7 J.F. Dove, F.T.S. Yu, C. Eldering WU

Communications Processor Operating System Study. Executive Summary,

DTIC Science & Technology

1980-11-01

AD-A095 b36 ROME AIR DEVELOPMENT CENTER GRIFFISS AFB NY F/e 17/2 COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY. EXECUTIVE SUMM—ETC(U) NOV 80 J...COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY Julian Gitlih SPTIC ELECTE«^ FEfi 2 6 1981^ - E APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED "a O...Subtitle) EXECUTIVE^SUMMARY 0F> COMMUNICATIONS PROCESSOR OPERATING SYSTEM $t - • >X W tdLl - ’•• • 7 AUTHORf«! ! , Julian

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

DOEpatents

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Methods and Apparatus for Aggregation of Multiple Pulse Code Modulation Channels into a Signal Time Division Multiplexing Stream

NASA Technical Reports Server (NTRS)

Chang, Chen J. (Inventor); Liaghati, Jr., Amir L. (Inventor); Liaghati, Mahsa L. (Inventor)

2018-01-01

Methods and apparatus are provided for telemetry processing using a telemetry processor. The telemetry processor can include a plurality of communications interfaces, a computer processor, and data storage. The telemetry processor can buffer sensor data by: receiving a frame of sensor data using a first communications interface and clock data using a second communications interface, receiving an end of frame signal using a third communications interface, and storing the received frame of sensor data in the data storage. After buffering the sensor data, the telemetry processor can generate an encapsulated data packet including a single encapsulated data packet header, the buffered sensor data, and identifiers identifying telemetry devices that provided the sensor data. A format of the encapsulated data packet can comply with a Consultative Committee for Space Data Systems (CCSDS) standard. The telemetry processor can send the encapsulated data packet using a fourth and a fifth communications interfaces.

Image processing for a tactile/vision substitution system using digital CNN.

PubMed

Lin, Chien-Nan; Yu, Sung-Nien; Hu, Jin-Cheng

2006-01-01

In view of the parallel processing and easy implementation properties of CNN, we propose to use digital CNN as the image processor of a tactile/vision substitution system (TVSS). The digital CNN processor is used to execute the wavelet down-sampling filtering and the half-toning operations, aiming to extract important features from the images. A template combination method is used to embed the two image processing functions into a single CNN processor. The digital CNN processor is implemented on an intellectual property (IP) and is implemented on a XILINX VIRTEX II 2000 FPGA board. Experiments are designated to test the capability of the CNN processor in the recognition of characters and human subjects in different environments. The experiments demonstrates impressive results, which proves the proposed digital CNN processor a powerful component in the design of efficient tactile/vision substitution systems for the visually impaired people.

Multiple Embedded Processors for Fault-Tolerant Computing

NASA Technical Reports Server (NTRS)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Life sciences flight experiments microcomputer

NASA Technical Reports Server (NTRS)

Bartram, Peter N.

1987-01-01

A promising microcomputer configuration for the Spacelab Life Sciences Lab. Equipment inventory consists of multiple processors. One processor's use is reserved, with additional processors dedicated to real time input and output operations. A simple form of such a configuration, with a processor board for analog to digital conversion and another processor board for digital to analog conversion, was studied. The system used digital parallel data lines between the boards, operating independently of the system bus. Good performance of individual components was demonstrated: the analog to digital converter was at over 10,000 samples per second. The combination of the data transfer between boards with the input or output functions on each board slowed performance, with a maximum throughput of 2800 to 2900 analog samples per second. Any of several techniques, such as use of the system bus for data transfer or the addition of direct memory access hardware to the processor boards, should give significantly improved performance.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

DOEpatents

Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

2013-05-21

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Parallel processing data network of master and slave transputers controlled by a serial control network

DOEpatents

Crosetto, D.B.

1996-12-31

The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor to a plurality of slave processors to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor`s status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer, a digital signal processor, a parallel transfer controller, and two three-port memory devices. A communication switch within each node connects it to a fast parallel hardware channel through which all high density data arrives or leaves the node. 6 figs.

A word processor optimized for preparing journal articles and student papers.

PubMed

Wolach, A H; McHale, M A

2001-11-01

A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

On nonlinear finite element analysis in single-, multi- and parallel-processors

NASA Technical Reports Server (NTRS)

Utku, S.; Melosh, R.; Islam, M.; Salama, M.

1982-01-01

Numerical solution of nonlinear equilibrium problems of structures by means of Newton-Raphson type iterations is reviewed. Each step of the iteration is shown to correspond to the solution of a linear problem, therefore the feasibility of the finite element method for nonlinear analysis is established. Organization and flow of data for various types of digital computers, such as single-processor/single-level memory, single-processor/two-level-memory, vector-processor/two-level-memory, and parallel-processors, with and without sub-structuring (i.e. partitioning) are given. The effect of the relative costs of computation, memory and data transfer on substructuring is shown. The idea of assigning comparable size substructures to parallel processors is exploited. Under Cholesky type factorization schemes, the efficiency of parallel processing is shown to decrease due to the occasional shared data, just as that due to the shared facilities.

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

NASA Technical Reports Server (NTRS)

Goldberg, J.; Kautz, W. H.; Melliar-Smith, P. M.; Green, M. W.; Levitt, K. N.; Schwartz, R. L.; Weinstock, C. B.

1984-01-01

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness.

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

NASA Technical Reports Server (NTRS)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

System for routing messages in a vertex symmetric network by using addresses formed from permutations of the transmission line indicees

DOEpatents

Faber, Vance; Moore, James W.

1992-01-01

A network of interconnected processors is formed from a vertex symmetric graph selected from graphs .GAMMA..sub.d (k) with degree d, diameter k, and (d+1)!/(d-k+1)! processors for each d.gtoreq.k and .GAMMA..sub.d (k,-1) with degree 3-1, diameter k+1, and (d+1)!/(d-k+1)! processors for each d.gtoreq.k.gtoreq.4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network .GAMMA..sub.d (k,-1) is provided, no processor has a channel connected to form an edge in a direction .delta..sub.1. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations.

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

Shuttle orbiter S-band payload communications equipment design evaluation

NASA Technical Reports Server (NTRS)

Springett, J. C.; Maronde, R. G.

1979-01-01

The analysis of the design, and the performance assessment of the Orbiter S-band communication equipment are reported. The equipment considered include: network transponder, network signal processor, FM transmitter, FM signal processor, payload interrogator, and payload signal processor.

Concept of a programmable maintenance processor applicable to multiprocessing systems

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1988-01-01

A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

Watchdog activity monitor (WAM) for use wth high coverage processor self-test

NASA Technical Reports Server (NTRS)

Tulpule, Bhalchandra R. (Inventor); Crosset, III, Richard W. (Inventor); Versailles, Richard E. (Inventor)

1988-01-01

A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

NASA Technical Reports Server (NTRS)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

Optical backplane interconnect switch for data processors and computers

NASA Technical Reports Server (NTRS)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

In Vitro and In Vivo Evaluation of a Novel Ferrocyanide Functionalized Nanopourous Silica Decorporation Agent for Cesium (Cs) in Rats

PubMed Central

Timchalk, Charles; Creim, Jeffrey A; Sukwarotwat, Vichaya; Wiacek, Robert; Addleman, R Shane; Fryxell, Glen E; Yantasee, Wassana

2009-01-01

Novel decorporation agents are being developed to protect against radiological terrorist attacks. These sorbents, known as the self-assembled monolayer on mesoporous supports (SAMMS™), are hybrid materials where differing organic moieties are grafted onto mesoporous silica (SiO2). In vitro experiments focused on the evaluation, and optimization of SAMMS for capturing radiocesium (137Cs); therefore based on these studies, a ferrocyanide copper (FC-Cu-EDA)-SAMMS was advanced for in vivo evaluation. In vivo experiments were conducted comparing the performance of the SAMMS vs. insoluble Prussian blue. Groups of jugular cannulated rats (4/treatment) were evaluated. Animals in group I were administered 137Cs chloride (~40 μg/kg) by intravenous (iv) injection or oral gavage; Group II animals were administered pre-bound 137Cs- SAMMS or sequential 137Cs chloride + SAMMS (~61 ng/kg) by oral gavage; and Group III was orally administered 137Cs chloride (~61 ng/kg) followed by either 0.1 g of SAMMS or Prussian blue. Following dosing, the rats were maintained in metabolism cages for 72 hour and blood, urine and fecal samples were collected for 137Cs analysis (gamma counting). Rats were then humanely euthanized, and selected tissues analyzed. Orally administered 137Cs chloride was rapidly and well absorbed (~100% relative to iv dose), and the pharmacokinetics (blood, urine, feces & tissues) were very comparable to the iv dose group. For both exposures the urine and feces accounted for 20 and 3% of the dose, respectively. The prebound 137Cs-SAMMS was retained primarily within the feces (72% of the dose), with ~1.4% detected in the urine, suggesting that the 137Cs remained tightly bound to SAMMS. SAMMS & Prussian blue both effectively captured available 137Cs in the gut with feces accounting for 80–88% of the administered dose, while less than 2% was detected in the urine. This study suggests that the functionalized SAMMS outperforms Prussian blue in vitro at low pH, but demonstrates comparable in vivo sequestration efficacy at low exposure concentrations. The comparable response may be the result of the low 137Cs chloride dose and high sorbent dosage that was utilized. Future studies are planned to optimize SAMMS in vivo performance over a broader range of doses and conditions. PMID:20699707

In Vitro and In Vivo Evaluation of a Novel Ferrocyanide Functionalized Nanopourous Silica Decorporation Agent for Cesium in Rats

DOE Office of Scientific and Technical Information (OSTI.GOV)

Timchalk, Charles; Creim, Jeffrey A.; Sukwarotwat, Vichaya

2010-09-01

Novel decorporation agents are being developed to protect against radiological terrorist attacks. These sorbents, known as the self-assembled monolayer on mesoporous supports (SAMMS™), are hybrid materials where differing organic moieties are grafted onto mesoporous silica (SiO2). In vitro experiments focused on the evaluation, and optimization of SAMMS for capturing radiocesium (137Cs); based on these studies, a ferrocyanide copper (FC-Cu-EDA)-SAMMS was advanced for in vivo evaluation. In vivo experiments were conducted comparing the performance of the SAMMS vs. insoluble Prussian blue. Groups of jugular cannulated rats (4/treatment) were evaluated. Group I was administered 137Cs (~40 μgeq/kg) by intravenous (iv) injection andmore » oral gavage; Group II was administered pre-bound 137Cs-SAMMS and sequential 137Cs + SAMMS (~61 ngeq/kg) by oral gavage; and Group III evaluated orally administered 137Cs (~0.06 μgeq/kg) followed by 0.1 g of either SAMMS or Prussian blue. Following dosing the rats were maintained in metabolism cages for 72 hour and blood, urine and fecal samples were collected for 137Cs analysis (gamma counting). Rats were then humanely euthanized, and selected tissues analyzed. Orally administered 137Cs was rapidly and well absorbed (~100% relative to iv dose), and the pharmacokinetics (blood, urine, feces & tissues) were very comparable to the iv dose group. For both exposures the urine and feces accounted for 20 and 3% of the dose, respectively. The prebound 137Cs-SAMMS was retained primarily within the feces (72% of the dose), with ~1.4% detected in the urine, suggesting that the 137Cs remained tightly bound to SAMMS. SAMMS & Prussian blue both effectively captured available 137Cs in the gut with feces accounting for 80-88% of the administered dose, while less than 2% was detected in the urine. This study suggests that the functionalized SAMMS out performs Prussian blue in vitro at low pH, but demonstrates comparable in vivo sequestration efficacy at low exposure concentrations. The comparable response may be the result of the low 137Cs dose and high sorbent dosage that was utilized. Future studies are planned to optimize SAMMS in vivo performance over a broader range of doses and conditions.« less

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Semiconductor-laser Fourier processors of electric signals

NASA Astrophysics Data System (ADS)

Blok, A. S.; Bukhenskii, A. F.; Krupitskii, É. I.; Morozov, S. V.; Pelevin, V. Yu; Sergeenko, T. N.; Yakovlev, V. I.

1995-10-01

An investigation is reported of acousto-optical and fibre-optic Fourier processors of electric signals, based on semiconductor lasers. A description is given of practical acousto-optical processors with an analysis band 120 MHz wide, a resolution of 200 kHz, and 7 cm × 8 cm × 18 cm dimensions. Fibre-optic Fourier processors are considered: they represent a new class of devices which are promising for the processing of gigahertz signals.

Spring/dimple instrument tube restraint

DOEpatents

DeMario, Edmund E.; Lawson, Charles N.

1993-01-01

A nuclear fuel assembly for a pressurized water nuclear reactor has a spring and dimple structure formed in a non-radioactive insert tube placed in the top of a sensor receiving instrumentation tube thimble disposed in the fuel assembly and attached at a top nozzle, a bottom nozzle, and intermediate grids. The instrumentation tube thimble is open at the top, where the sensor or its connection extends through the cooling water for coupling to a sensor signal processor. The spring and dimple insert tube is mounted within the instrumentation tube thimble and extends downwardly adjacent the top. The springs and dimples restrain the sensor and its connections against lateral displacement causing impact with the instrumentation tube thimble due to the strong axial flow of cooling water. The instrumentation tube has a stainless steel outer sleeve and a zirconium alloy inner sleeve below the insert tube adjacent the top. The insert tube is relatively non-radioactivated inconel alloy. The opposed springs and dimples are formed on diametrically opposite inner walls of the insert tube, the springs being formed as spaced axial cuts in the insert tube, with a web of the insert tube between the cuts bowed radially inwardly for forming the spring, and the dimples being formed as radially inward protrusions opposed to the springs.

Spring/dimple instrument tube restraint

DOEpatents

DeMario, E.E.; Lawson, C.N.

1993-11-23

A nuclear fuel assembly for a pressurized water nuclear reactor has a spring and dimple structure formed in a non-radioactive insert tube placed in the top of a sensor receiving instrumentation tube thimble disposed in the fuel assembly and attached at a top nozzle, a bottom nozzle, and intermediate grids. The instrumentation tube thimble is open at the top, where the sensor or its connection extends through the cooling water for coupling to a sensor signal processor. The spring and dimple insert tube is mounted within the instrumentation tube thimble and extends downwardly adjacent the top. The springs and dimples restrain the sensor and its connections against lateral displacement causing impact with the instrumentation tube thimble due to the strong axial flow of cooling water. The instrumentation tube has a stainless steel outer sleeve and a zirconium alloy inner sleeve below the insert tube adjacent the top. The insert tube is relatively non-radioactivated inconel alloy. The opposed springs and dimples are formed on diametrically opposite inner walls of the insert tube, the springs being formed as spaced axial cuts in the insert tube, with a web of the insert tube between the cuts bowed radially inwardly for forming the spring, and the dimples being formed as radially inward protrusions opposed to the springs. 7 figures.

Simple debugging techniques for embedded subsystems

NASA Astrophysics Data System (ADS)

MacPherson, Matthew S.; Martin, Kevin S.

1990-08-01

This paper describes some of the tools and methods used for developing and debugging embedded subsystems at Fermilab. Specifically, these tools have been used for the Flying Wire project and are currently being employed for the New TECAR upgrade. The Flying Wire is a subsystem that swings a wire through the beam in order to measure luminosity and beam density distribution, and TECAR (Tevatron excitation controller and regulator) controls the power-supply ramp generation for the superconducting Tevatron accelerator at Fermilab. In both instances the subsystem hardware consists of a VME crate with one or more processors, shared memory and a network connection to the accelerator control system. Two real-time-operating systems are currently being used: VRTX for the Flying Wire system, and MTOS for New TECAR. The code which runs in these subsystems is a combination of C and assembler and is developed using the Microtec cross-development tools on a VAX 8650 running VMS. This paper explains how multiple debuggers are used to give the greatest possible flexibility from assembly to high-level debugging. Also discussed is how network debugging and network downloading can make a very effective and efficient means of finding bugs in the subsystem environment. The debuggers used are PROBE1, TRACER and the MTOS debugger.

Fusing Sensor Paradigms to Acquire Chemical Information: An Integrative Role for Smart Biopolymeric Hydrogels

PubMed Central

Kim, Eunkyoung; Liu, Yi; Ben-Yoav, Hadar; Winkler, Thomas E.; Yan, Kun; Shi, Xiaowen; Shen, Jana; Kelly, Deanna L.; Ghodssi, Reza; Bentley, William E.

2017-01-01

The Information Age transformed our lives but it has had surprisingly little impact on the way chemical information (e.g., from our biological world) is acquired, analyzed and communicated. Sensor systems are poised to change this situation by providing rapid access to chemical information. This access will be enabled by technological advances from various fields: biology enables the synthesis, design and discovery of molecular recognition elements as well as the generation of cell-based signal processors; physics and chemistry are providing nano-components that facilitate the transmission and transduction of signals rich with chemical information; microfabrication is yielding sensors capable of receiving these signals through various modalities; and signal processing analysis enhances the extraction of chemical information. The authors contend that integral to the development of functional sensor systems will be materials that (i) enable the integrative and hierarchical assembly of various sensing components (for chemical recognition and signal transduction) and (ii) facilitate meaningful communication across modalities. It is suggested that stimuli-responsive self-assembling biopolymers can perform such integrative functions, and redox provides modality-spanning communication capabilities. Recent progress toward the development of electrochemical sensors to manage schizophrenia is used to illustrate the opportunities and challenges for enlisting sensors for chemical information processing. PMID:27616350

Operating system for a real-time multiprocessor propulsion system simulator

NASA Technical Reports Server (NTRS)

Cole, G. L.

1984-01-01

The success of the Real Time Multiprocessor Operating System (RTMPOS) in the development and evaluation of experimental hardware and software systems for real time interactive simulation of air breathing propulsion systems was evaluated. The Real Time Multiprocessor Operating System (RTMPOS) provides the user with a versatile, interactive means for loading, running, debugging and obtaining results from a multiprocessor based simulator. A front end processor (FEP) serves as the simulator controller and interface between the user and the simulator. These functions are facilitated by the RTMPOS which resides on the FEP. The RTMPOS acts in conjunction with the FEP's manufacturer supplied disk operating system that provides typical utilities like an assembler, linkage editor, text editor, file handling services, etc. Once a simulation is formulated, the RTMPOS provides for engineering level, run time operations such as loading, modifying and specifying computation flow of programs, simulator mode control, data handling and run time monitoring. Run time monitoring is a powerful feature of RTMPOS that allows the user to record all actions taken during a simulation session and to receive advisories from the simulator via the FEP. The RTMPOS is programmed mainly in PASCAL along with some assembly language routines. The RTMPOS software is easily modified to be applicable to hardware from different manufacturers.

Long-Duration Testing of a Temperature-Swing Adsorption Compressor for Carbon Dioxide for Closed-Loop Air Revitalization Systems

NASA Technical Reports Server (NTRS)

Rosen, Micha; Mulloth, Lila; Varghese, Mini

2005-01-01

This paper describes the results of long-duration testing of a temperature-swing adsorption compressor that has application in the International Space Station (ISS) and future spacecraft for closing the air revitalization loop. The air revitalization system of the ISS operates in an open loop mode and relies on the resupply of oxygen and other consumables from Earth for the life support of astronauts. A compressor is required for delivering the carbon dioxide from a removal assembly to a reduction unit to recover oxygen and thereby closing the air-loop. The TSAC is a solid-state compressor that has the capability to remove CO2 from a low-pressure source, and subsequently store, compress, and deliver at a higher pressure as required by a processor. The TSAC is an ideal interface device for CO2 removal and reduction units in the air revitalization loop of a spacecraft for oxygen recovery. The TSAC was developed and its operation was successfully verified in integration tests with the flight-like Carbon Dioxide Removal Assembly (CDRA) at Marshall Space Flight Center prior to the long-duration tests. Long-duration tests reveal the impacts of repeated thermal cycling on the compressor components and the adsorbent material.

Three-Dimensional Nacelle Aeroacoustics Code With Application to Impedance Education

NASA Technical Reports Server (NTRS)

Watson, Willie R.

2000-01-01

A three-dimensional nacelle acoustics code that accounts for uniform mean flow and variable surface impedance liners is developed. The code is linked to a commercial version of the NASA-developed General Purpose Solver (for solution of linear systems of equations) in order to obtain the capability to study high frequency waves that may require millions of grid points for resolution. Detailed, single-processor statistics for the performance of the solver in rigid and soft-wall ducts are presented. Over the range of frequencies of current interest in nacelle liner research, noise attenuation levels predicted from the code were in excellent agreement with those predicted from mode theory. The equation solver is memory efficient, requiring only a small fraction of the memory available on modern computers. As an application, the code is combined with an optimization algorithm and used to reduce the impedance spectrum of a ceramic liner. The primary problem with using the code to perform optimization studies at frequencies above I1kHz is the excessive CPU time (a major portion of which is matrix assembly). The research recommends that research be directed toward development of a rapid sparse assembler and exploitation of the multiprocessor capability of the solver to further reduce CPU time.

Compact electro-optical module with polymer waveguides on a flexible substrate for high-density board-level communication

NASA Astrophysics Data System (ADS)

Weiss, J. R. M.; Lamprecht, T.; Meier, N.; Dangel, R.; Horst, F.; Jubin, D.; Beyeler, R.; Offrein, B. J.

2010-02-01

We report on the co-packaging of electrical CMOS transceiver and VCSEL chip arrays on a flexible electrical substrate with optical polymer waveguides. The electro-optical components are attached to the substrate edge and butt-coupled to the waveguides. Electrically conductive silver-ink connects them to the substrate at an angle of 90°. The final assembly contacts the surface of a package laminate with an integrated compressible connector. The module can be folded to save space, requires only a small footprint on the package laminate and provides short electrical high-speed signal paths. With our approach, the electro-optical package becomes a compact electro-optical module with integrated polymer waveguides terminated with either optical connectors (e.g., at the card edge) or with an identical assembly for a second processor on the board. Consequently, no costly subassemblies and connectors are needed, and a very high integration density and scalability to virtually arbitrary channel counts and towards very high data rates (20+ Gbps) become possible. Future cost targets of much less than US$1 per Gbps will be reached by employing standard PCB materials and technologies that are well established in the industry. Moreover, our technology platform has both electrical and optical connectivity and functionality.

Implementation of the DPM Monte Carlo code on a parallel architecture for treatment planning applications.

PubMed

Tyagi, Neelam; Bose, Abhijit; Chetty, Indrin J

2004-09-01

We have parallelized the Dose Planning Method (DPM), a Monte Carlo code optimized for radiotherapy class problems, on distributed-memory processor architectures using the Message Passing Interface (MPI). Parallelization has been investigated on a variety of parallel computing architectures at the University of Michigan-Center for Advanced Computing, with respect to efficiency and speedup as a function of the number of processors. We have integrated the parallel pseudo random number generator from the Scalable Parallel Pseudo-Random Number Generator (SPRNG) library to run with the parallel DPM. The Intel cluster consisting of 800 MHz Intel Pentium III processor shows an almost linear speedup up to 32 processors for simulating 1 x 10(8) or more particles. The speedup results are nearly linear on an Athlon cluster (up to 24 processors based on availability) which consists of 1.8 GHz+ Advanced Micro Devices (AMD) Athlon processors on increasing the problem size up to 8 x 10(8) histories. For a smaller number of histories (1 x 10(8)) the reduction of efficiency with the Athlon cluster (down to 83.9% with 24 processors) occurs because the processing time required to simulate 1 x 10(8) histories is less than the time associated with interprocessor communication. A similar trend was seen with the Opteron Cluster (consisting of 1400 MHz, 64-bit AMD Opteron processors) on increasing the problem size. Because of the 64-bit architecture Opteron processors are capable of storing and processing instructions at a faster rate and hence are faster as compared to the 32-bit Athlon processors. We have validated our implementation with an in-phantom dose calculation study using a parallel pencil monoenergetic electron beam of 20 MeV energy. The phantom consists of layers of water, lung, bone, aluminum, and titanium. The agreement in the central axis depth dose curves and profiles at different depths shows that the serial and parallel codes are equivalent in accuracy.

Implementing wavelet inverse-transform processor with surface acoustic wave device.

PubMed

Lu, Wenke; Zhu, Changchun; Liu, Qinghong; Zhang, Jingduan

2013-02-01

The objective of this research was to investigate the implementation schemes of the wavelet inverse-transform processor using surface acoustic wave (SAW) device, the length function of defining the electrodes, and the possibility of solving the load resistance and the internal resistance for the wavelet inverse-transform processor using SAW device. In this paper, we investigate the implementation schemes of the wavelet inverse-transform processor using SAW device. In the implementation scheme that the input interdigital transducer (IDT) and output IDT stand in a line, because the electrode-overlap envelope of the input IDT is identical with the one of the output IDT (i.e. the two transducers are identical), the product of the input IDT's frequency response and the output IDT's frequency response can be implemented, so that the wavelet inverse-transform processor can be fabricated. X-112(0)Y LiTaO(3) is used as a substrate material to fabricate the wavelet inverse-transform processor. The size of the wavelet inverse-transform processor using this implementation scheme is small, so its cost is low. First, according to the envelope function of the wavelet function, the length function of the electrodes is defined, then, the lengths of the electrodes can be calculated from the length function of the electrodes, finally, the input IDT and output IDT can be designed according to the lengths and widths for the electrodes. In this paper, we also present the load resistance and the internal resistance as the two problems of the wavelet inverse-transform processor using SAW devices. The solutions to these problems are achieved in this study. When the amplifiers are subjected to the input end and output end for the wavelet inverse-transform processor, they can eliminate the influence of the load resistance and the internal resistance on the output voltage of the wavelet inverse-transform processor using SAW device. Copyright © 2012 Elsevier B.V. All rights reserved.

Rapid Damage Assessment. Volume II. Development and Testing of Rapid Damage Assessment System.

DTIC Science & Technology

1981-02-01

pixels/s Camera Line Rate 732.4 lines/s Pixels per Line 1728 video 314 blank 4 line number (binary) 2 run number (BCD) 2048 total Pixel Resolution 8 bits...sists of an LSI-ll microprocessor, a VDI -200 video display processor, an FD-2 dual floppy diskette subsystem, an FT-I function key-trackball module...COMPONENT LIST FOR IMAGE PROCESSOR SYSTEM IMAGE PROCESSOR SYSTEM VIEWS I VDI -200 Display Processor Racks, Table FD-2 Dual Floppy Diskette Subsystem FT-l

Master/Programmable-Slave Computer

NASA Technical Reports Server (NTRS)

Smaistrla, David; Hall, William A.

1990-01-01

Unique modular computer features compactness, low power, mass storage of data, multiprocessing, and choice of various input/output modes. Master processor communicates with user via usual keyboard and video display terminal. Coordinates operations of as many as 24 slave processors, each dedicated to different experiment. Each slave circuit card includes slave microprocessor and assortment of input/output circuits for communication with external equipment, with master processor, and with other slave processors. Adaptable to industrial process control with selectable degrees of automatic control, automatic and/or manual monitoring, and manual intervention.

System Level RBDO for Military Ground Vehicles using High Performance Computing

DTIC Science & Technology

2008-01-01

platform. Only the analyses that required more than 24 processors were conducted on the Onyx 350 due to the limited number of processors on the...optimization constraints varied. The queues set the number of processors and number of finite element code licenses available to the analyses. sgi ONYX ...3900: unix 24 MIPS R16000 PROCESSORS 4 IR2 GRAPHICS PIPES 4 IR3 GRAPHICS PIPES 24 GBYTES MEMORY 36 GBYTES LOCAL DISK SPACE sgi ONYX 350: unix 32 MIPS

Experience in highly parallel processing using DAP

NASA Technical Reports Server (NTRS)

Parkinson, D.

1987-01-01

Distributed Array Processors (DAP) have been in day to day use for ten years and a large amount of user experience has been gained. The profile of user applications is similar to that of the Massively Parallel Processor (MPP) working group. Experience has shown that contrary to expectations, highly parallel systems provide excellent performance on so-called dirty problems such as the physics part of meteorological codes. The reasons for this observation are discussed. The arguments against replacing bit processors with floating point processors are also discussed.

Measurements of the LHCb software stack on the ARM architecture

NASA Astrophysics Data System (ADS)

Vijay Kartik, S.; Couturier, Ben; Clemencic, Marco; Neufeld, Niko

2014-06-01

The ARM architecture is a power-efficient design that is used in most processors in mobile devices all around the world today since they provide reasonable compute performance per watt. The current LHCb software stack is designed (and thus expected) to build and run on machines with the x86/x86_64 architecture. This paper outlines the process of measuring the performance of the LHCb software stack on the ARM architecture - specifically, the ARMv7 architecture on Cortex-A9 processors from NVIDIA and on full-fledged ARM servers with chipsets from Calxeda - and makes comparisons with the performance on x86_64 architectures on the Intel Xeon L5520/X5650 and AMD Opteron 6272. The paper emphasises the aspects of performance per core with respect to the power drawn by the compute nodes for the given performance - this ensures a fair real-world comparison with much more 'powerful' Intel/AMD processors. The comparisons of these real workloads in the context of LHCb are also complemented with the standard synthetic benchmarks HEPSPEC and Coremark. The pitfalls and solutions for the non-trivial task of porting the source code to build for the ARMv7 instruction set are presented. The specific changes in the build process needed for ARM-specific portions of the software stack are described, to serve as pointers for further attempts taken up by other groups in this direction. Cases where architecture-specific tweaks at the assembler lever (both in ROOT and the LHCb software stack) were needed for a successful compile are detailed - these cases are good indicators of where/how the software stack as well as the build system can be made more portable and multi-arch friendly. The experience gained from the tasks described in this paper are intended to i) assist in making an informed choice about ARM-based server solutions as a feasible low-power alternative to the current compute nodes, and ii) revisit the software design and build system for portability and generic improvements.

Interconnection networks

DOEpatents

Faber, V.; Moore, J.W.

1988-06-20

A network of interconnected processors is formed from a vertex symmetric graph selected from graphs GAMMA/sub d/(k) with degree d, diameter k, and (d + 1)exclamation/ (d /minus/ k + 1)exclamation processors for each d greater than or equal to k and GAMMA/sub d/(k, /minus/1) with degree d /minus/ 1, diameter k + 1, and (d + 1)exclamation/(d /minus/ k + 1)exclamation processors for each d greater than or equal to k greater than or equal to 4. Each processor has an address formed by one of the permutations from a predetermined sequence of letters chosen a selected number of letters at a time, and an extended address formed by appending to the address the remaining ones of the predetermined sequence of letters. A plurality of transmission channels is provided from each of the processors, where each processor has one less channel than the selected number of letters forming the sequence. Where a network GAMMA/sub d/(k, /minus/1) is provided, no processor has a channel connected to form an edge in a direction delta/sub 1/. Each of the channels has an identification number selected from the sequence of letters and connected from a first processor having a first extended address to a second processor having a second address formed from a second extended address defined by moving to the front of the first extended address the letter found in the position within the first extended address defined by the channel identification number. The second address is then formed by selecting the first elements of the second extended address corresponding to the selected number used to form the address permutations. 9 figs.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Method and system for selecting data sampling phase for self timed interface logic

DOEpatents

Hoke, Joseph Michael; Ferraiolo, Frank D.; Lo, Tin-Chee; Yarolin, John Michael

2005-01-04

An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

The implementation and use of Ada on distributed systems with reliability requirements

NASA Technical Reports Server (NTRS)

Reynolds, P. F.; Knight, J. C.; Urquhart, J. I. A.

1983-01-01

The issues involved in the use of the programming language Ada on distributed systems are discussed. The effects of Ada programs on hardware failures such as loss of a processor are emphasized. It is shown that many Ada language elements are not well suited to this environment. Processor failure can easily lead to difficulties on those processors which remain. As an example, the calling task in a rendezvous may be suspended forever if the processor executing the serving task fails. A mechanism for detecting failure is proposed and changes to the Ada run time support system are suggested which avoid most of the difficulties. Ada program structures are defined which allow programs to reconfigure and continue to provide service following processor failure.

A novel compensation method of insertion losses for wavelet inverse-transform processors using surface acoustic wave devices.

PubMed

Lu, Wenke; Zhu, Changchun

2011-11-01

The objective of this research was to investigate the possibility of compensating for the insertion losses of the wavelet inverse-transform processors using SAW devices. The motivation for this work was prompted by the processors which are of large insertion losses. In this paper, the insertion losses are the key problem of the wavelet inverse-transform processors using SAW devices. A novel compensation method of the insertion losses is achieved in this study. When the output ends of the wavelet inverse-transform processors are respectively connected to the amplifiers, their insertion losses can be compensated for. The bandwidths of the amplifiers and their adjustment method are also given in this paper. © 2011 American Institute of Physics

An optical/digital processor - Hardware and applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Sterling, W. M.

1975-01-01

A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD2PO4) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased-array radar data processing, synthetic-aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Urine chemistry

MedlinePlus

... rate 24-hour urine protein Acid loading test (pH) Adrenalin - urine test Amylase - urine Bilirubin - urine Calcium - urine Citric acid ... Urine dermatan sulfate Urine - hemoglobin Urine metanephrine Urine pH Urine specific gravity Vanillylmandelic acid (VMA)

International Space Station (ISS) Orbital Replaceable Unit (ORU) Wet Storage Risk Assessment

NASA Technical Reports Server (NTRS)

Squire, Michael D.; Rotter, Henry A.; Lee, Jason; Packham, Nigel; Brady, Timothy K.; Kelly, Robert; Ott, C. Mark

2014-01-01

The International Space Station (ISS) Program requested the NASA Engineering and Safety Center (NESC) to evaluate the risks posed by the practice of long-term wet storage of ISS Environmental Control and Life Support (ECLS) regeneration system orbital replacement units (ORUs). The ISS ECLS regeneration system removes water from urine and humidity condensate and converts it into potable water and oxygen. A total of 29 ORUs are in the ECLS system, each designed to be replaced by the ISS crew when necessary. The NESC assembled a team to review the ISS ECLS regeneration system and evaluate the potential for biofouling and corrosion. This document contains the outcome of the evaluation.

Computer program documentation for the pasture/range condition assessment processor

NASA Technical Reports Server (NTRS)

Mcintyre, K. S.; Miller, T. G. (Principal Investigator)

1982-01-01

The processor which drives for the RANGE software allows the user to analyze LANDSAT data containing pasture and rangeland. Analysis includes mapping, generating statistics, calculating vegetative indexes, and plotting vegetative indexes. Routines for using the processor are given. A flow diagram is included.

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

A hierarchical, automated target recognition algorithm for a parallel analog processor

NASA Technical Reports Server (NTRS)

Woodward, Gail; Padgett, Curtis

1997-01-01

A hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

NASA Technical Reports Server (NTRS)

Strohkorb, G. A.; Noor, A. K.

1983-01-01

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Design of RISC Processor Using VHDL and Cadence

NASA Astrophysics Data System (ADS)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

Fault tolerant, radiation hard, high performance digital signal processor

NASA Technical Reports Server (NTRS)

Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

1990-01-01

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

Digital system for structural dynamics simulation

NASA Technical Reports Server (NTRS)

Krauter, A. I.; Lagace, L. J.; Wojnar, M. K.; Glor, C.

1982-01-01

State-of-the-art digital hardware and software for the simulation of complex structural dynamic interactions, such as those which occur in rotating structures (engine systems). System were incorporated in a designed to use an array of processors in which the computation for each physical subelement or functional subsystem would be assigned to a single specific processor in the simulator. These node processors are microprogrammed bit-slice microcomputers which function autonomously and can communicate with each other and a central control minicomputer over parallel digital lines. Inter-processor nearest neighbor communications busses pass the constants which represent physical constraints and boundary conditions. The node processors are connected to the six nearest neighbor node processors to simulate the actual physical interface of real substructures. Computer generated finite element mesh and force models can be developed with the aid of the central control minicomputer. The control computer also oversees the animation of a graphics display system, disk-based mass storage along with the individual processing elements.

Next Generation Space Telescope Integrated Science Module Data System

NASA Technical Reports Server (NTRS)

Schnurr, Richard G.; Greenhouse, Matthew A.; Jurotich, Matthew M.; Whitley, Raymond; Kalinowski, Keith J.; Love, Bruce W.; Travis, Jeffrey W.; Long, Knox S.

1999-01-01

The Data system for the Next Generation Space Telescope (NGST) Integrated Science Module (ISIM) is the primary data interface between the spacecraft, telescope, and science instrument systems. This poster includes block diagrams of the ISIM data system and its components derived during the pre-phase A Yardstick feasibility study. The poster details the hardware and software components used to acquire and process science data for the Yardstick instrument compliment, and depicts the baseline external interfaces to science instruments and other systems. This baseline data system is a fully redundant, high performance computing system. Each redundant computer contains three 150 MHz power PC processors. All processors execute a commercially available real time multi-tasking operating system supporting, preemptive multi-tasking, file management and network interfaces. These six processors in the system are networked together. The spacecraft interface baseline is an extension of the network, which links the six processors. The final selection for Processor busses, processor chips, network interfaces, and high-speed data interfaces will be made during mid 2002.

A universal computer control system for motors

NASA Technical Reports Server (NTRS)

Szakaly, Zoltan F. (Inventor)

1991-01-01

A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

NASA Astrophysics Data System (ADS)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

CADNA_C: A version of CADNA for use with C or C++ programs

NASA Astrophysics Data System (ADS)

Lamotte, Jean-Luc; Chesneaux, Jean-Marie; Jézéquel, Fabienne

2010-11-01

The CADNA library enables one to estimate round-off error propagation using a probabilistic approach. The CADNA_C version enables this estimation in C or C++ programs, while the previous version had been developed for Fortran programs. The CADNA_C version has the same features as the previous one: with CADNA the numerical quality of any simulation program can be controlled. Furthermore by detecting all the instabilities which may occur at run time, a numerical debugging of the user code can be performed. CADNA provides new numerical types on which round-off errors can be estimated. Slight modifications are required to control a code with CADNA, mainly changes in variable declarations, input and output. New version program summaryProgram title: CADNA_C Catalogue identifier: AEGQ_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEGQ_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 60 075 No. of bytes in distributed program, including test data, etc.: 710 781 Distribution format: tar.gz Programming language: C++ Computer: PC running LINUX with an i686 or an ia64 processor, UNIX workstations including SUN, IBM Operating system: LINUX, UNIX Classification: 6.5 Catalogue identifier of previous version: AEAT_v1_0 Journal reference of previous version: Comput. Phys. Comm. 178 (2008) 933 Does the new version supersede the previous version?: No Nature of problem: A simulation program which uses floating-point arithmetic generates round-off errors, due to the rounding performed at each assignment and at each arithmetic operation. Round-off error propagation may invalidate the result of a program. The CADNA library enables one to estimate round-off error propagation in any simulation program and to detect all numerical instabilities that may occur at run time. Solution method: The CADNA library [1-3] implements Discrete Stochastic Arithmetic [4,5] which is based on a probabilistic model of round-off errors. The program is run several times with a random rounding mode generating different results each time. From this set of results, CADNA estimates the number of exact significant digits in the result that would have been computed with standard floating-point arithmetic. Reasons for new version: The previous version (AEAT_v1_0) enables the estimation of round-off error propagation in Fortran programs [2]. The new version has been developed to enable this estimation in C or C++ programs. Summary of revisions: The CADNA_C source code consists of one assembly language file (cadna_rounding.s) and twenty-three C++ language files (including three header files). cadna_rounding.s is a symbolic link to the assembly file corresponding to the processor and the C++ compiler used. This assembly file contains routines which are frequently called in the CADNA_C C++ files to change the rounding mode. The C++ language files contain the definition of the stochastic types on which the control of accuracy can be performed, CADNA_C specific functions (for instance to enable or disable the detection of numerical instabilities), the definition of arithmetic and relational operators which are overloaded for stochastic variables and the definition of mathematical functions which can be used with stochastic arguments. As a remark, on 64-bit processors, the mathematical library associated with the GNU C++ compiler may provide incorrect results or generate severe bugs with rounding towards -∞ and +∞, which the random rounding mode is based on. Therefore, if CADNA_C is used on a 64-bit processor with the GNU C++ compiler, mathematical functions are computed with rounding to the nearest, otherwise they are computed with the random rounding mode. It must be pointed out that the knowledge of the accuracy of the argument of a mathematical function is never lost. Additional comments: In the library archive, users are advised to read the INSTALL file first. The doc directory contains a user guide named ug.cadna.pdf and a reference guide named, ref_cadna.pdf. The user guide shows how to control the numerical accuracy of a program using CADNA, provides installation instructions and describes test runs.The reference guide briefly describes each function of the library. The source code (which consists of C++ and assembly files) is located in the src directory. The examples directory contains seven test runs which illustrate the use of the CADNA library and the benefits of Discrete Stochastic Arithmetic. Running time: The version of a code which uses CADNA runs at least three times slower than its floating-point version. This cost depends on the computer architecture and can be higher if the detection of numerical instabilities is enabled. In this case, the cost may be related to the number of instabilities detected.

A Practical Solution Using A New Approach To Robot Vision

NASA Astrophysics Data System (ADS)

Hudson, David L.

1984-01-01

Up to now, robot vision systems have been designed to serve both application development and operational needs in inspection, assembly and material handling. This universal approach to robot vision is too costly for many practical applications. A new industrial vision system separates the function of application program development from on-line operation. A Vision Development System (VDS) is equipped with facilities designed to simplify and accelerate the application program development process. A complimentary but lower cost Target Application System (TASK) runs the application program developed with the VDS. This concept is presented in the context of an actual robot vision application that improves inspection and assembly for a manufacturer of electronic terminal keyboards. Applications developed with a VDS experience lower development cost when compared with conventional vision systems. Since the TASK processor is not burdened with development tools, it can be installed at a lower cost than comparable "universal" vision systems that are intended to be used for both development and on-line operation. The VDS/TASK approach opens more industrial applications to robot vision that previously were not practical because of the high cost of vision systems. Although robot vision is a new technology, it has been applied successfully to a variety of industrial needs in inspection, manufacturing, and material handling. New developments in robot vision technology are creating practical, cost effective solutions for a variety of industrial needs. A year or two ago, researchers and robot manufacturers interested in implementing a robot vision application could take one of two approaches. The first approach was to purchase all the necessary vision components from various sources. That meant buying an image processor from one company, a camera from another and lens and light sources from yet others. The user then had to assemble the pieces, and in most instances he had to write all of his own software to test, analyze and process the vision application. The second and most common approach was to contract with the vision equipment vendor for the development and installation of a turnkey inspection or manufacturing system. The robot user and his company paid a premium for their vision system in an effort to assure the success of the system. Since 1981, emphasis on robotics has skyrocketed. New groups have been formed in many manufacturing companies with the charter to learn about, test and initially apply new robot and automation technologies. Machine vision is one of new technologies being tested and applied. This focused interest has created a need for a robot vision system that makes it easy for manufacturing engineers to learn about, test, and implement a robot vision application. A newly developed vision system addresses those needs. Vision Development System (VDS) is a complete hardware and software product for the development and testing of robot vision applications. A complimentary, low cost Target Application System (TASK) runs the application program developed with the VDS. An actual robot vision application that demonstrates inspection and pre-assembly for keyboard manufacturing is used to illustrate the VDS/TASK approach.

OHD/HL - XEFS

Science.gov Websites

Assimilator Ensemble Post-processor (EnsPost) Hydrologic Model Output Statistics (HMOS) Ensemble Verification capabilities (see diagram below): the Ensemble Pre-processor, the Ensemble Post-processor, the Hydrologic Model (OpenDA, http://www.openda.org/joomla/index.php) to be used within the CHPS environment. Ensemble Post

40 CFR 747.195 - Triethanolamine salt of a substituted organic acid.

Code of Federal Regulations, 2010 CFR

2010-07-01

..., commerce, importer, impurity, Inventory, manufacturer, person, process, processor, and small quantities... control of the processor. (ii) Distribution in commerce is limited to purposes of export. (iii) The processor or distributor may not use the substance except in small quantities solely for research and...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

Advanced Multiple Processor Configuration Study. Final Report.

ERIC Educational Resources Information Center

Clymer, S. J.

This summary of a study on multiple processor configurations includes the objectives, background, approach, and results of research undertaken to provide the Air Force with a generalized model of computer processor combinations for use in the evaluation of proposed flight training simulator computational designs. An analysis of a real-time flight…

75 FR 52507 - Submission for OMB Review; Comment Request

Federal Register 2010, 2011, 2012, 2013, 2014

2010-08-26

... standards designed to ensure that all catch delivered to the processor is accurately weighed and accounted... NMFS for catcher/processors and motherships is based on the vessel meeting a series of design criteria. Because of the wide variations in factory layout for inshore processors, NMFS requires a performance-based...

PREMAQ: A NEW PRE-PROCESSOR TO CMAQ FOR AIR-QUALITY FORECASTING

EPA Science Inventory

A new pre-processor to CMAQ (PREMAQ) has been developed as part of the national air-quality forecasting system. PREMAQ combines the functionality of MCIP and parts of SMOKE in a single real-time processor. PREMAQ was specifically designed to link NCEP's Eta model with CMAQ, and...

50 CFR 679.30 - General CDQ regulations.

Code of Federal Regulations, 2010 CFR

2010-10-01

... description of the target fisheries, the types of vessels and processors that will be used, the locations and... vessels or processors fishing under contract with any CDQ group. Any vessel or processor harvesting or... nature of the work and the career advancement potential for each type of work. (iv) Community eligibility...

A Survey of Parallel Sorting Algorithms.

DTIC Science & Technology

1981-12-01

see that, in this algorithm, each Processor i, for 1 itp -2, interacts directly only with Processors i+l and i-l. Processor j 0 only interacts with...Chan76] Chandra, A.K., "Maximal Parallelism in Matrix Multiplication," IBM Report RC. 6193, Watson Research Center, Yorktown Heights, N.Y., October 1976

7 CFR 1435.503 - In-kind payments.

Code of Federal Regulations, 2013 CFR

2013-01-01

... OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Processor Sugar Payment-In-Kind..., make payments in the form of sugar held in CCC inventory. (b) To the maximum extent practicable, CCC... sugar held in storage by the processor; (2) CCC-owned sugar held in storage by any other processor in...

78 FR 33243 - Amendment 94 to the Gulf of Alaska Fishery Management Plan and Regulatory Amendments for...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-06-04

... floating processor landing reporting requirements; and to consolidate CQE Program eligibility by community... determine their annual reporting requirements. CQE Floating Processor Landing Report Requirements This action revises the recordkeeping and reporting regulations at Sec. 679.5(e) for CQE floating processors...

78 FR 14490 - Amendment 94 to the Gulf of Alaska Fishery Management Plan and Regulatory Amendments for...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-03-06

... clarify the CQE floating processor landing reporting requirements; and to consolidate CQE Program... their annual reporting requirements. CQE Floating Processor Landing Report Requirements This action would revise the recordkeeping and reporting regulations at Sec. 679.5(e) for CQE floating processors...

50 CFR 679.94 - Economic data report (EDR) for the Amendment 80 sector.

Code of Federal Regulations, 2010 CFR

2010-10-01

...: NMFS, Alaska Fisheries Science Center, Economic Data Reports, 7600 Sand Point Way NE, F/AKC2, Seattle... Operation Description of code Code NMFS Alaska region ADF&G FCP Catcher/processor Floating catcher processor. FLD Mothership Floating domestic mothership. IFP Stationary Floating Processor Inshore floating...

SAPIENS: Spreading Activation Processor for Information Encoded in Network Structures. Technical Report No. 296.

ERIC Educational Resources Information Center

Ortony, Andrew; Radin, Dean I.

The product of researchers' efforts to develop a computer processor which distinguishes between relevant and irrelevant information in the database, Spreading Activation Processor for Information Encoded in Network Structures (SAPIENS) exhibits (1) context sensitivity, (2) efficiency, (3) decreasing activation over time, (4) summation of…