Product assurance technology for custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

1985-01-01

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

Parallel VLSI architecture emulation and the organization of APSA/MPP

NASA Technical Reports Server (NTRS)

Odonnell, John T.

1987-01-01

The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

NASA Astrophysics Data System (ADS)

Makhijani, Vinod B.; Przekwas, Andrzej J.

2002-10-01

This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

Application of a Silicon Compiler to VLSI (Very Large Scale Integrated Circuits) Design of Digital Pipelined Multipliers.

DTIC Science & Technology

1984-06-01

programming environment and then dumped, as described in the Franz Lisp manual [Ref. 13]. A synopsis of the functional elements which make up this LISP...the average system usage rate. Lines i4 and 15 reflect a function of Franz Lisp wherein past used storage locations are reclaimed for the available... Franz Lisp Opus 38. Also included in this distribu- tion are two library files containing the bonding Fad a layouts in CIF, and a library file

Circuit Recognition of VLSI Layouts

DTIC Science & Technology

1989-09-01

from the ** ** input file contain information on each transitor . ** totaltransistors=O; while(((strcmp(buffer. "n")))=O) 1Ms(trcmp(buffer.tp"))-=O)) I... statistics and information on transistors ** ** inverters and passgates prior to entering level2 recognition.** fprintf (fo. "no more transistors.\

Design and implementation of highly parallel pipelined VLSI systems

NASA Astrophysics Data System (ADS)

Delange, Alphonsus Anthonius Jozef

A methodology and its realization as a prototype CAD (Computer Aided Design) system for the design and analysis of complex multiprocessor systems is presented. The design is an iterative process in which the behavioral specifications of the system components are refined into structural descriptions consisting of interconnections and lower level components etc. A model for the representation and analysis of multiprocessor systems at several levels of abstraction and an implementation of a CAD system based on this model are described. A high level design language, an object oriented development kit for tool design, a design data management system, and design and analysis tools such as a high level simulator and graphics design interface which are integrated into the prototype system and graphics interface are described. Procedures for the synthesis of semiregular processor arrays, and to compute the switching of input/output signals, memory management and control of processor array, and sequencing and segmentation of input/output data streams due to partitioning and clustering of the processor array during the subsequent synthesis steps, are described. The architecture and control of a parallel system is designed and each component mapped to a module or module generator in a symbolic layout library, compacted for design rules of VLSI (Very Large Scale Integration) technology. An example of the design of a processor that is a useful building block for highly parallel pipelined systems in the signal/image processing domains is given.

Reconfigurable tree architectures using subtree oriented fault tolerance

NASA Technical Reports Server (NTRS)

Lowrie, Matthew B.

1987-01-01

An approach to the design of reconfigurable tree architecture is presented in which spare processors are allocated at the leaves. The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur. The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links. VLSI layout is 0(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation.

Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

PubMed

Carvajal, Gonzalo; Figueroa, Miguel

2014-07-01

Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights reserved.

Electron-beam lithography with character projection exposure for throughput enhancement with line-edge quality optimization

NASA Astrophysics Data System (ADS)

Ikeno, Rimon; Maruyama, Satoshi; Mita, Yoshio; Ikeda, Makoto; Asada, Kunihiro

2016-03-01

Among various electron-beam lithography (EBL) techniques, variable-shaped beam (VSB) and character projection (CP) methods have attracted many EBL users for their high-throughput feature, but they are considered to be more suited to small-featured VLSI fabrication with regularly-arranged layouts like standard-cell logics and memory arrays. On the other hand, non-VLSI applications like photonics, MEMS, MOEMS, and so on, have not been fully utilized the benefit of CP method due to their wide variety of layout patterns. In addition, the stepwise edge shapes by VSB method often causes intolerable edge roughness to degrade device characteristics from its intended performance with smooth edges. We proposed an overall EBL methodology applicable to wade-variety of EBL applications utilizing VSB and CP methods. Its key idea is in our layout data conversion algorithm that decomposes curved or oblique edges of arbitrary layout patterns into CP shots. We expect significant reduction in EB shot count with a CP-bordered exposure data compared to the corresponding VSB-alone conversion result. Several CP conversion parameters are used to optimize EB exposure throughput, edge quality, and resultant device characteristics. We demonstrated out methodology using the leading-edge VSB/CP EBL tool, ADVANTEST F7000S-VD02, with high resolution Hydrogen Silsesquioxane (HSQ) resist. Through our experiments of curved and oblique edge lithography under various data conversion conditions, we learned correspondence of the conversion parameters to the resultant edge roughness and other conditions. They will be utilized as the fundamental data for further enhancement of our EBL strategy for optimized EB exposure.

The 1991 3rd NASA Symposium on VLSI Design

NASA Technical Reports Server (NTRS)

Maki, Gary K.

1991-01-01

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

Silicon Compilation Using a Lisp-Based Layout Language.

DTIC Science & Technology

1986-06-01

12, 15 October 19184. Gajski , D.D., "The Structure of A Silicon Compiler", IEEE International Conference on Circuits and Comouters 1982(ICCC 82...IEEE Press, 1982. Gajski , D.D. and Kuhn, R.H.," Guest Editors’ Introduction: New VLSI Tools", Comguter Volume 16, Number 12, 1983. Gajs i, D.D., "Silicon

The Fifth NASA Symposium on VLSI Design

NASA Technical Reports Server (NTRS)

1993-01-01

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

Improvement of the user interface of multimedia applications by automatic display layout

NASA Astrophysics Data System (ADS)

Lueders, Peter; Ernst, Rolf

1995-03-01

Multimedia research has mainly focussed on real-time data capturing and display combined with compression, storage and transmission of these data. However, there is another problem considering real-time selecting and arranging a possibly large amount of data from multiple media on the computer screen together with textual and graphical data of regular software. This problem has already been known from complex software systems, such as CASE and hypertest, and will even be aggravated in multimedia systems. The aim of our work is to alleviate the user from the burden of continuously selecting, placing and sizing windows and their contents, but without introducing solutions limited to only few applications. We present an experimental system which controls the computer screen contents and layouts, directed by a user and/or tool provided information filter and prioritization. To be application independent, the screen layout is based on general layout optimization algorithms adapted from the VLSI layout which are controlled by application specific objective functions. In this paper, we discuss the problems of a comprehensible screen layout including the stability of optical information in time, the information filtering, the layout algorithms and the adaptation of the objective function to include a specific application. We give some examples of different standard applications with layout problems ranging from hierarchical graph layout to window layout. The results show that the automatic tool independent display layout will be possible in a real time interactive environment.

Area-Efficient Graph Layouts (for VLSI).

DTIC Science & Technology

1980-08-13

thle short side, then no rectangle is ew r generated x’.ho se aspect r~itho i s \\orse di ai aJ. ’I lie d i % ide-I mid -cimq tier clInt ruolIn in... Sutherland and Donald Oestrcichcr, "flow big should a printed circuit board be?," ILEEE, Transactions on Computers, Vol. C-22, May 1973, pp. 537-542. 22

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

ERIC Educational Resources Information Center

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Parallel optimization algorithms and their implementation in VLSI design

NASA Technical Reports Server (NTRS)

Lee, G.; Feeley, J. J.

1991-01-01

Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

Lossless compression of VLSI layout image data.

PubMed

Dai, Vito; Zakhor, Avideh

2006-09-01

We present a novel lossless compression algorithm called Context Copy Combinatorial Code (C4), which integrates the advantages of two very disparate compression techniques: context-based modeling and Lempel-Ziv (LZ) style copying. While the algorithm can be applied to many lossless compression applications, such as document image compression, our primary target application has been lossless compression of integrated circuit layout image data. These images contain a heterogeneous mix of data: dense repetitive data better suited to LZ-style coding, and less dense structured data, better suited to context-based encoding. As part of C4, we have developed a novel binary entropy coding technique called combinatorial coding which is simultaneously as efficient as arithmetic coding, and as fast as Huffman coding. Compression results show C4 outperforms JBIG, ZIP, BZIP2, and two-dimensional LZ, and achieves lossless compression ratios greater than 22 for binary layout image data, and greater than 14 for gray-pixel image data.

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1981-01-01

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

The 1992 4th NASA SERC Symposium on VLSI Design

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R.

1992-01-01

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

NASA Space Engineering Research Center Symposium on VLSI Design

NASA Technical Reports Server (NTRS)

Maki, Gary K.

1990-01-01

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers.

Imbalance aware lithography hotspot detection: a deep learning approach

NASA Astrophysics Data System (ADS)

Yang, Haoyu; Luo, Luyang; Su, Jing; Lin, Chenxi; Yu, Bei

2017-03-01

With the advancement of VLSI technology nodes, light diffraction caused lithographic hotspots have become a serious problem affecting manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with extreme scaling of transistor feature size and more and more complicated layout patterns, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. In this paper, we present a deep convolutional neural network (CNN) targeting representative feature learning in lithography hotspot detection. We carefully analyze impact and effectiveness of different CNN hyper-parameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always minorities in VLSI mask design, the training data set is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from high false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply minority upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves highly comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

VLSI design of a single chip reed-solomon encoder

DOE Office of Scientific and Technical Information (OSTI.GOV)

Truong, T.K.; Deutsch, L.J.; Reed, I.S.

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

NASA Space Engineering Research Center for VLSI System Design

NASA Technical Reports Server (NTRS)

1993-01-01

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

On testing VLSI chips for the big Viterbi decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.

1989-01-01

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

The VLSI design of a single chip Reed-Solomon encoder

NASA Technical Reports Server (NTRS)

Truong, T. K.; Deutsch, L. J.; Reed, I. S.

1982-01-01

A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

NASA Space Engineering Research Center for VLSI systems design

NASA Technical Reports Server (NTRS)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Imbalance aware lithography hotspot detection: a deep learning approach

NASA Astrophysics Data System (ADS)

Yang, Haoyu; Luo, Luyang; Su, Jing; Lin, Chenxi; Yu, Bei

2017-07-01

With the advancement of very large scale integrated circuits (VLSI) technology nodes, lithographic hotspots become a serious problem that affects manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with the extreme scaling of transistor feature size and layout patterns growing in complexity, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. We present a deep convolutional neural network (CNN) that targets representative feature learning in lithography hotspot detection. We carefully analyze the impact and effectiveness of different CNN hyperparameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always in the minority in VLSI mask design, the training dataset is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from a high number of false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply hotspot upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shao, H.M.; Reed, I.S.

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous paper is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area, therefore making it possible to build a pipelinemore » Reed-Solomon decoder on a single VLSI chip.« less

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Grain-size considerations for optoelectronic multistage interconnection networks.

PubMed

Krishnamoorthy, A V; Marchand, P J; Kiamilev, F E; Esener, S C

1992-09-10

This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K x K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MIN's.

The Area-Time Complexity of Sorting.

DTIC Science & Technology

1984-12-01

suggests a classification of keys into short (k < logn), long (k > 2 logn), and of medium length. Optimal or near-optimal designs of VLSI sorters are...suggests a classification of keys into short (k 4 logn ), long (k > 21ogn ), and of medium length. Optimal or near-optimal designs of VLSI sorters are...ARCHITECTURES 79 5.1 Introduction 79 5.2 Parallel Algorithms for Sorting 80 . 5.3 Parallel Architectures 88 6 OPTIMAL VLSI SORTERS FOR KEYS OF LENGTH k - logn

Architecture for VLSI design of Reed-Solomon encoders

NASA Technical Reports Server (NTRS)

Liu, K. Y.

1982-01-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Architecture for VLSI design of Reed-Solomon encoders

NASA Astrophysics Data System (ADS)

Liu, K. Y.

1982-02-01

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Research in the design of high-performance reconfigurable systems

NASA Technical Reports Server (NTRS)

Mcewan, S. D.; Spry, A. J.

1985-01-01

Computer aided design and computer aided manufacturing have the potential for greatly reducing the cost and lead time in the development of VLSI components. This potential paves the way for the design and fabrication of a wide variety of economically feasible high level functional units. It was observed that current computer systems have only a limited capacity to absorb new VLSI component types other than memory, microprocessors, and a relatively small number of other parts. The first purpose is to explore a system design which is capable of effectively incorporating a considerable number of VLSI part types and will both increase the speed of computation and reduce the attendant programming effort. A second purpose is to explore design techniques for VLSI parts which when incorporated by such a system will result in speeds and costs which are optimal. The proposed work may lay the groundwork for future efforts in the extensive simulation and measurements of the system's cost effectiveness and lead to prototype development.

Design of Tactile Sensor Using Dynamic Wafer Technology Based on VLSI Technique

DTIC Science & Technology

2001-10-25

Charles Noback, Rober Carola," Human Anatomy and Physiology" third edition, 1995. [5] M.H. Raibert and John E. Tanner, "Design and Implementation of VLSI Tactile Sensing Computer" Robotics Research vol 1, 1983.

A single chip VLSI Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Hsu, I. S.; Deutsch, L. J.; Reed, I. S.

1986-01-01

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.

Functional Abstraction from Structure in VLSI Simulation Models,

DTIC Science & Technology

1987-05-01

wide vari- ety of powerful tools, designed around the Y model proposed by Gajski and Kuhn [11]. The heart of the system is the data representation...34Fuictional Models for VLSI Design", 20th IEEE Design Automation Conference (DAC󈨗), 1983, paper 32.2, pp. 506-514. * 21 [11] Gajski , Daniel D., Kuhn, Robert H

Princeton VLSI Project.

DTIC Science & Technology

1982-01-01

a rectilinear graph. iefnition 2.1: A rectiliwr graph G is a triple (V. E. X). where V is the vertex set, E is the edge set, and X:Vx V-E U le , where...G,(V, ,) as follows: . =e(z) I =z(a),a E Viand E., = (z, ) I Z1 >Z2E:I, V and E-V are similarly defined. It can be easily shown that C is consistent...width of the layout after the introduction the le .’gths of the drivers introduced on wn to u _-, If we of drivers, which is given by so,+m. is 0(m2

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

NASA Technical Reports Server (NTRS)

Shao, H. M.; Deutsch, L. J.; Reed, I. S.

1987-01-01

A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

NASA Technical Reports Server (NTRS)

Shao, Howard M.; Reed, Irving S.

1988-01-01

A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

Performance, Resources, and Complexity: A Systematic Approach to Microarchitectural Design

DTIC Science & Technology

1989-05-01

Approved: ********************************** Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...Approved for public release; distribution unlimited 13. SUPPLEMENTARY NOTES 14. ABSTRACT VLSI design in general -- microprocessor design in particular...has been treated more like an art than a science in the past. The goal of this thesis is to explain the science of VLSI design to someone who wants

Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Benny N.; Spotnitz, Matthew

1997-01-01

VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

NASA Astrophysics Data System (ADS)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Feasibility study, software design, layout and simulation of a two-dimensional Fast Fourier Transform machine for use in optical array interferometry

NASA Technical Reports Server (NTRS)

Boriakoff, Valentin

1994-01-01

The goal of this project was the feasibility study of a particular architecture of a digital signal processing machine operating in real time which could do in a pipeline fashion the computation of the fast Fourier transform (FFT) of a time-domain sampled complex digital data stream. The particular architecture makes use of simple identical processors (called inner product processors) in a linear organization called a systolic array. Through computer simulation the new architecture to compute the FFT with systolic arrays was proved to be viable, and computed the FFT correctly and with the predicted particulars of operation. Integrated circuits to compute the operations expected of the vital node of the systolic architecture were proven feasible, and even with a 2 micron VLSI technology can execute the required operations in the required time. Actual construction of the integrated circuits was successful in one variant (fixed point) and unsuccessful in the other (floating point).

Verification of VLSI designs

NASA Technical Reports Server (NTRS)

Windley, P. J.

1991-01-01

In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

Compact Interconnection Networks Based on Quantum Dots

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

2003-01-01

Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary-signal wires described in the cited prior article. One of these advances would be the development of QCA-based wires capable of bidirectional transmission of signals. The other advance would be the development of QCA circuits capable of high-impedance state outputs. The high-impedance states would be utilized along with the 0- and 1-state outputs of QCA.

VLSI 'smart' I/O module development

NASA Astrophysics Data System (ADS)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

A Coherent VLSI Design Environment

DTIC Science & Technology

1987-12-31

contract the total research volume in VLSI rose from an estimated $3,000,000 to over 3 $10,000,000, and a state-of-the-art VLSI fabrication facility costing...Research" 11:30 John Melngailic , "Submicron Structures Research at M.I.T." 11:55 Dimitri A. Antoniadis, "Status of the M.I.T. LSI Fabrication Facility ...1984. Contributions were made by Prof. Antoniadis and, to a small degree, Pro£ Glasser. Objective: • To develop techniques for fabricating integrated

Electron-beam lithography with character projection technique for high-throughput exposure with line-edge quality control

NASA Astrophysics Data System (ADS)

Ikeno, Rimon; Maruyama, Satoshi; Mita, Yoshio; Ikeda, Makoto; Asada, Kunihiro

2016-07-01

The high throughput of character projection (CP) electron-beam (EB) lithography makes it a promising technique for low-to-medium volume device fabrication with regularly arranged layouts, such as for standard-cell logics and memory arrays. However, non-VLSI applications such as MEMS and MOEMS may not be able to fully utilize the benefits of the CP method due to the wide variety of layout figures including curved and oblique edges. In addition, the stepwise shapes that appear because of the EB exposure process often result in intolerable edge roughness, which degrades device performances. In this study, we propose a general EB lithography methodology for such applications utilizing a combination of the CP and variable-shaped beam methods. In the process of layout data conversion with CP character instantiation, several control parameters were optimized to minimize the shot count, improve the edge quality, and enhance the overall device performance. We have demonstrated EB shot reduction and edge-quality improvement with our methodology by using a leading-edge EB exposure tool, ADVANTEST F7000S-VD02, and a high-resolution hydrogen silsesquioxane resist. Atomic force microscope observations were used to analyze the resist edge profiles' quality to determine the influence of the control parameters used in the data conversion process.

A Systolic VLSI Design of a Pipeline Reed-solomon Decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

1984-01-01

A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

A VLSI design of a pipeline Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

1985-01-01

A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

Testing Methods for Integrated Circuit Chips.

DTIC Science & Technology

1986-03-27

DWf <I IAV ~IMi MORY OUT LOGIC~~ IPOGRAM ASYC S’E4i E...* 16o, CO% T ROL CO%TROL 32 Figure 2 . 14 VLSI Tester Block Diagram. registers, memory and test...neral-pIurpos’ processor wi th standard bus- inte-rfaco se-rves as,- th- test control Ii’r and ( 2 ) a c-ustom VLSI test Controller inti-rfacing direc(_t1...Engineering 2 WTWTY ABSTRACT Provision for the functional testing of fabricated VLSI chips frequently involves as much design effort as the orig- _ inal

Large-Constraint-Length, Fast Viterbi Decoder

NASA Technical Reports Server (NTRS)

Collins, O.; Dolinar, S.; Hsu, In-Shek; Pollara, F.; Olson, E.; Statman, J.; Zimmerman, G.

1990-01-01

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

NASA Technical Reports Server (NTRS)

Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

1990-01-01

The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

A cost-effective methodology for the design of massively-parallel VLSI functional units

NASA Technical Reports Server (NTRS)

Venkateswaran, N.; Sriram, G.; Desouza, J.

1993-01-01

In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

Hybrid VLSI/QCA Architecture for Computing FFTs

NASA Technical Reports Server (NTRS)

Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

2003-01-01

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Princeton VLSI Project: Semi-Annual Report.

DTIC Science & Technology

1982-11-01

already fully defined the new language and implementation is now under way o [7]. AMl differs from AU in two essential ways. First, it is based on...Our main thesis is that the VLSI design task can be profitably thought of as a progremmiW task, as opposed to a geometric editing task. We believe...S. Thesis , MIT, EECS Department, June, 1980. [4] Batali, J., Mayle, N., Shrobe, H., Sussman, G., Weise, D., "The DPL/Daedalus Design Environment

The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

NASA Technical Reports Server (NTRS)

Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

1986-01-01

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

The VLSI design of error-trellis syndrome decoding for convolutional codes

NASA Technical Reports Server (NTRS)

Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

1985-01-01

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Plane representations of graphs and visibility between parallel segments

NASA Astrophysics Data System (ADS)

Tamassia, R.; Tollis, I. G.

1985-04-01

Several layout compaction strategies for VLSI are based on the concept of visibility between parallel segments, where we say that two parallel segments of a given set are visible if they can be joined by a segment orthogonal to them, which does not intersect any other segment. This paper studies visibility representations of graphs, which are constructed by mapping vertices to horizontal segments, and edges to vertical segments drawn between visible vertex-segments. Clearly, every graph that admits such a representation must be a planar. The authors consider three types of visibility representations, and give complete characterizations of the classes of graphs that admit them. Furthermore, they present linear time algorithms for testing the existence of and constructing visibility representations of planar graphs.

On VLSI Design of Rank-Order Filtering using DCRAM Architecture

PubMed Central

Lin, Meng-Chun; Dung, Lan-Rong

2009-01-01

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply. PMID:19865599

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Artificial immune system algorithm in VLSI circuit configuration

NASA Astrophysics Data System (ADS)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

Periodically Self Restoring Redundant Systems for VLSI Based Highly Reliable Design,

DTIC Science & Technology

1984-01-01

fault tolerance technique for realizing highly reliable computer systems for critical control applications . However, VL.SI technology has imposed a...operating correctly; failed critical real time control applications . n modules are discarded from the vote. the classical "static" voted redundancy...redundant modules are failure number of InterconnecttIon3. This results In f aree. However, for applications requiring higm modular complexity because

Real-Time Reed-Solomon Decoder

NASA Technical Reports Server (NTRS)

Maki, Gary K.; Cameron, Kelly B.; Owsley, Patrick A.

1994-01-01

Generic Reed-Solomon decoder fast enough to correct errors in real time in practical applications designed to be implemented in fewer and smaller very-large-scale integrated, VLSI, circuit chips. Configured to operate in pipelined manner. One outstanding aspect of decoder design is that Euclid multiplier and divider modules contain Galoisfield multipliers configured as combinational-logic cells. Operates at speeds greater than older multipliers. Cellular configuration highly regular and requires little interconnection area, making it ideal for implementation in extraordinarily dense VLSI circuitry. Flight electronics single chip version of this technology implemented and available.

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Patrick

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

A combined approach of simulation and analytic hierarchy process in assessing production facility layouts

NASA Astrophysics Data System (ADS)

Ramli, Razamin; Cheng, Kok-Min

2014-07-01

One of the important areas of concern in order to obtain a competitive level of productivity in a manufacturing system is the layout design and material transportation system (conveyor system). However, changes in customers' requirements have triggered the need to design other alternatives of the manufacturing layout for existing production floor. Hence, this paper discusses effective alternatives of the process layout specifically, the conveyor system layout. Subsequently, two alternative designs for the conveyor system were proposed with the aims to increase the production output and minimize space allocation. The first proposed layout design includes the installation of conveyor oven in the particular manufacturing room based on priority, and the second one is the one without the conveyor oven in the layout. Simulation technique was employed to design the new facility layout. Eventually, simulation experiments were conducted to understand the performance of each conveyor layout design based on operational characteristics, which include predicting the output of layouts. Utilizing the Analytic Hierarchy Process (AHP), the newly and improved layout designs were assessed before the final selection was done. As a comparison, the existing conveyor system layout was included in the assessment process. Relevant criteria involved in this layout design problem were identified as (i) usage of space of each design, (ii) operator's utilization rates, (iii) return of investment (ROI) of the layout, and (iv) output of the layout. In the final stage of AHP analysis, the overall priority of each alternative layout was obtained and thus, a selection for final use by the management was made based on the highest priority value. This efficient planning and designing of facility layout in a particular manufacturing setting is able to minimize material handling cost, minimize overall production time, minimize investment in equipment, and optimize utilization of space.

Sensing and perception research for space telerobotics at JPL

NASA Technical Reports Server (NTRS)

Gennery, Donald B.; Litwin, Todd; Wilcox, Brian; Bon, Bruce

1987-01-01

PIFLEX is a pipelined-image processor that can perform elaborate computations whose exact nature is not fixed in the hardware, and that can handle multiple images. A wire-wrapped prototype PIFEX module has been produced and debugged, using a version of the convolver composed of three custom VLSI chips (plus the line buffers). A printed circuit layout is being designed for use with a single-chip convolver, leading to production of a PIFEX with about 120 modules. A high-level language for programming PIFEX has been designed, and a compiler will be written for it. The camera calibration software has been completed and tested. Two more terms in the camera model, for lens distortion, probably will be added later. The acquisition and tracking system has been designed and most of it has been coded in Pascal for the MicroVAX-II. The feature tracker, motion stereo module and stereo matcher have executed successfully. The model matcher is still under development, and coding has begun on the tracking initializer. The object tracker was running on a different computer from the VAX, and preliminary runs on real images have been performed there. Once all modules are working, optimization and integration will begin. Finally, when a sufficiently large PIFEX is available, appropriate parts of acquisition and tracking, including much of the feature tracker, will be programmed into PIFEX, thus increasing the speed and robustness of the system.

Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Brouwer, Randall Jay

1991-01-01

The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

A subthreshold aVLSI implementation of the Izhikevich simple neuron model.

PubMed

Rangan, Venkat; Ghosh, Abhishek; Aparin, Vladimir; Cauwenberghs, Gert

2010-01-01

We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience.

The VLSI design of a Reed-Solomon encoder using Berlekamps bit-serial multiplier algorithm

NASA Technical Reports Server (NTRS)

Truong, T. K.; Deutsch, L. J.; Reed, I. S.; Hsu, I. S.; Wang, K.; Yeh, C. S.

1982-01-01

Realization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes ofter requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.

Layout Design of Human-Machine Interaction Interface of Cabin Based on Cognitive Ergonomics and GA-ACA.

PubMed

Deng, Li; Wang, Guohua; Yu, Suihuai

2016-01-01

In order to consider the psychological cognitive characteristics affecting operating comfort and realize the automatic layout design, cognitive ergonomics and GA-ACA (genetic algorithm and ant colony algorithm) were introduced into the layout design of human-machine interaction interface. First, from the perspective of cognitive psychology, according to the information processing process, the cognitive model of human-machine interaction interface was established. Then, the human cognitive characteristics were analyzed, and the layout principles of human-machine interaction interface were summarized as the constraints in layout design. Again, the expression form of fitness function, pheromone, and heuristic information for the layout optimization of cabin was studied. The layout design model of human-machine interaction interface was established based on GA-ACA. At last, a layout design system was developed based on this model. For validation, the human-machine interaction interface layout design of drilling rig control room was taken as an example, and the optimization result showed the feasibility and effectiveness of the proposed method.

Layout Design of Human-Machine Interaction Interface of Cabin Based on Cognitive Ergonomics and GA-ACA

PubMed Central

Deng, Li; Wang, Guohua; Yu, Suihuai

2016-01-01

In order to consider the psychological cognitive characteristics affecting operating comfort and realize the automatic layout design, cognitive ergonomics and GA-ACA (genetic algorithm and ant colony algorithm) were introduced into the layout design of human-machine interaction interface. First, from the perspective of cognitive psychology, according to the information processing process, the cognitive model of human-machine interaction interface was established. Then, the human cognitive characteristics were analyzed, and the layout principles of human-machine interaction interface were summarized as the constraints in layout design. Again, the expression form of fitness function, pheromone, and heuristic information for the layout optimization of cabin was studied. The layout design model of human-machine interaction interface was established based on GA-ACA. At last, a layout design system was developed based on this model. For validation, the human-machine interaction interface layout design of drilling rig control room was taken as an example, and the optimization result showed the feasibility and effectiveness of the proposed method. PMID:26884745

Design and Simulation Plant Layout Using Systematic Layout Planning

NASA Astrophysics Data System (ADS)

Suhardini, D.; Septiani, W.; Fauziah, S.

2017-12-01

This research aims to design the factory layout of PT. Gunaprima Budiwijaya in order to increase production capacity. The problem faced by this company is inappropriate layout causes cross traffic on the production floor. The re-layout procedure consist of these three steps: analysing the existing layout, designing plant layout based on SLP and evaluation and selection of alternative layout using Simulation Pro model version 6. Systematic layout planning is used to re-layout not based on the initial layout. This SLP produces four layout alternatives, and each alternative will be evaluated based on two criteria, namely cost of material handling using Material Handling Evaluation Sheet (MHES) and processing time by simulation. The results showed that production capacity is increasing as much as 37.5% with the addition of the machine and the operator, while material handling cost was reduced by improvement of the layout. The use of systematic layout planning method reduces material handling cost of 10,98% from initial layout or amounting to Rp1.229.813,34.

VLSI architectures for computing multiplications and inverses in GF(2m)

NASA Technical Reports Server (NTRS)

Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

1985-01-01

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

VLSI architectures for computing multiplications and inverses in GF(2-m)

NASA Technical Reports Server (NTRS)

Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

1983-01-01

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Noise-margin limitations on gallium-arsenide VLSI

NASA Technical Reports Server (NTRS)

Long, Stephen I.; Sundaram, Mani

1988-01-01

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

VLSI architectures for computing multiplications and inverses in GF(2m).

PubMed

Wang, C C; Truong, T K; Shao, H M; Deutsch, L J; Omura, J K; Reed, I S

1985-08-01

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

32 CFR 553.7 - Design and layout of Army national cemeteries.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 32 National Defense 3 2012-07-01 2009-07-01 true Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

32 CFR 553.7 - Design and layout of Army national cemeteries.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 32 National Defense 3 2011-07-01 2009-07-01 true Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

32 CFR 553.7 - Design and layout of Army national cemeteries.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 32 National Defense 3 2014-07-01 2014-07-01 false Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

32 CFR 553.7 - Design and layout of Army national cemeteries.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 32 National Defense 3 2010-07-01 2010-07-01 true Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

32 CFR 553.7 - Design and layout of Army national cemeteries.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 32 National Defense 3 2013-07-01 2013-07-01 false Design and layout of Army national cemeteries... RESERVATIONS AND NATIONAL CEMETERIES ARMY NATIONAL CEMETERIES § 553.7 Design and layout of Army national cemeteries. (a) General cemetery layout plans, landscape planting plans and gravesite layout plans for Army...

User-friendly design approach for analog layout design

NASA Astrophysics Data System (ADS)

Li, Yongfu; Lee, Zhao Chuan; Tripathi, Vikas; Perez, Valerio; Ong, Yoong Seang; Hui, Chiu Wing

2017-03-01

Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing processes, and variations. This paper presents analog verification flow with five types of analogfocused layout constraint checks to assist engineers in identifying any potential device mismatch and layout drawing mistakes. Compared to several solutions, our approach only requires layout design, which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation and allows seamless integration into the layout environment with minimum disruption to the custom layout flow. Our user-friendly analog verification flow provides the engineer with more confident with their layouts quality.

Line-edge quality optimization of electron beam resist for high-throughput character projection exposure utilizing atomic force microscope analysis

NASA Astrophysics Data System (ADS)

Ikeno, Rimon; Mita, Yoshio; Asada, Kunihiro

2017-04-01

High-throughput electron-beam lithography (EBL) by character projection (CP) and variable-shaped beam (VSB) methods is a promising technique for low-to-medium volume device fabrication with regularly arranged layouts, such as standard-cell logics and memory arrays. However, non-VLSI applications like MEMS and MOEMS may not fully utilize the benefits of CP method due to their wide variety of layout figures including curved and oblique edges. In addition, the stepwise shapes that appear on such irregular edges by VSB exposure often result in intolerable edge roughness, which may degrade performances of the fabricated devices. In our former study, we proposed a general EBL methodology for such applications utilizing a combination of CP and VSB methods, and demonstrated its capabilities in electron beam (EB) shot reduction and edge-quality improvement by using a leading-edge EB exposure tool, ADVANTEST F7000S-VD02, and high-resolution Hydrogen Silsesquioxane resist. Both scanning electron microscope and atomic force microscope observations were used to analyze quality of the resist edge profiles to determine the influence of the control parameters used in the exposure-data preparation process. In this study, we carried out detailed analysis of the captured edge profiles utilizing Fourier analysis, and successfully distinguish the systematic undulation by the exposed CP character profiles from random roughness components. Such capability of precise edge-roughness analysis is useful to our EBL methodology to maintain both the line-edge quality and the exposure throughput by optimizing the control parameters in the layout data conversion.

Sequence invariant state machines

NASA Technical Reports Server (NTRS)

Whitaker, S.; Manjunath, S.

1990-01-01

A synthesis method and new VLSI architecture are introduced to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. A design method is proposed that utilizes BTS logic to implement regular and dense circuits. A given state sequence can be programmed with power supply connections or dynamically reallocated if stored in a register. Arbitrary flow table sequences can be modified or programmed to dynamically alter the function of the machine. This allows VLSI controllers to be designed with the programmability of a general purpose processor but with the compact size and performance of dedicated logic.

Sequence-invariant state machines

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R.; Manjunath, Shamanna K.; Maki, Gary K.

1991-01-01

A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured (BTS) logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods.

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

PubMed

Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

2013-01-01

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

Facility Layout Problems Using Bays: A Survey

NASA Astrophysics Data System (ADS)

Davoudpour, Hamid; Jaafari, Amir Ardestani; Farahani, Leila Najafabadi

2010-06-01

Layout design is one of the most important activities done by industrial Engineers. Most of these problems have NP hard Complexity. In a basic layout design, each cell is represented by a rectilinear, but not necessarily convex polygon. The set of fully packed adjacent polygons is known as a block layout (Asef-Vaziri and Laporte 2007). Block layout is divided by slicing tree and bay layout. In bay layout, departments are located in vertical columns or horizontal rows, bays. Bay layout is used in real worlds especially in concepts such as semiconductor and aisles. There are several reviews in facility layout; however none of them focus on bay layout. The literature analysis given here is not limited to specific considerations about bay layout design. We present a state of art review for bay layout considering some issues such as the used objectives, the techniques of solving and the integration methods in bay.

Electronic shift register memory based on molecular electron-transfer reactions

NASA Technical Reports Server (NTRS)

Hopfield, J. J.; Onuchic, Jose Nelson; Beratan, David N.

1989-01-01

The design of a shift register memory at the molecular level is described in detail. The memory elements are based on a chain of electron-transfer molecules incorporated on a very large scale integrated (VLSI) substrate, and the information is shifted by photoinduced electron-transfer reactions. The design requirements for such a system are discussed, and several realistic strategies for synthesizing these systems are presented. The immediate advantage of such a hybrid molecular/VLSI device would arise from the possible information storage density. The prospect of considerable savings of energy per bit processed also exists. This molecular shift register memory element design solves the conceptual problems associated with integrating molecular size components with larger (micron) size features on a chip.

Distributed asynchronous microprocessor architectures in fault tolerant integrated flight systems

NASA Technical Reports Server (NTRS)

Dunn, W. R.

1983-01-01

The paper discusses the implementation of fault tolerant digital flight control and navigation systems for rotorcraft application. It is shown that in implementing fault tolerance at the systems level using advanced LSI/VLSI technology, aircraft physical layout and flight systems requirements tend to define a system architecture of distributed, asynchronous microprocessors in which fault tolerance can be achieved locally through hardware redundancy and/or globally through application of analytical redundancy. The effects of asynchronism on the execution of dynamic flight software is discussed. It is shown that if the asynchronous microprocessors have knowledge of time, these errors can be significantly reduced through appropiate modifications of the flight software. Finally, the papear extends previous work to show that through the combined use of time referencing and stable flight algorithms, individual microprocessors can be configured to autonomously tolerate intermittent faults.

Cellular-automata-based learning network for pattern recognition

NASA Astrophysics Data System (ADS)

Tzionas, Panagiotis G.; Tsalides, Phillippos G.; Thanailakis, Adonios

1991-11-01

Most classification techniques either adopt an approach based directly on the statistical characteristics of the pattern classes involved, or they transform the patterns in a feature space and try to separate the point clusters in this space. An alternative approach based on memory networks has been presented, its novelty being that it can be implemented in parallel and it utilizes direct features of the patterns rather than statistical characteristics. This study presents a new approach for pattern classification using pseudo 2-D binary cellular automata (CA). This approach resembles the memory network classifier in the sense that it is based on an adaptive knowledge based formed during a training phase, and also in the fact that both methods utilize pattern features that are directly available. The main advantage of this approach is that the sensitivity of the pattern classifier can be controlled. The proposed pattern classifier has been designed using 1.5 micrometers design rules for an N-well CMOS process. Layout has been achieved using SOLO 1400. Binary pseudo 2-D hybrid additive CA (HACA) is described in the second section of this paper. The third section describes the operation of the pattern classifier and the fourth section presents some possible applications. The VLSI implementation of the pattern classifier is presented in the fifth section and, finally, the sixth section draws conclusions from the results obtained.

Designing for Communication: The Key to Successful Desktop Publishing.

ERIC Educational Resources Information Center

McCain, Ted D. E.

Written for those who are new to design and page layout, this book focuses on providing novice desktop publishers with an understanding of communication, graphic design, typography, page layout, and page layout techniques. The book also discusses how people read, design as a consequence of understanding, and the principles of page layout. Chapters…

Overlay Tolerances For VLSI Using Wafer Steppers

NASA Astrophysics Data System (ADS)

Levinson, Harry J.; Rice, Rory

1988-01-01

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

Research News: Are VLSI Microcircuits Too Hard to Design?

ERIC Educational Resources Information Center

Robinson, Arthur L.

1980-01-01

This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)

A novel approach of ensuring layout regularity correct by construction in advanced technologies

NASA Astrophysics Data System (ADS)

Ahmed, Shafquat Jahan; Vaderiya, Yagnesh; Gupta, Radhika; Parthasarathy, Chittoor; Marin, Jean-Claude; Robert, Frederic

2017-03-01

In advanced technology nodes, layout regularity has become a mandatory prerequisite to create robust designs less sensitive to variations in manufacturing process in order to improve yield and minimizing electrical variability. In this paper we describe a method for designing regular full custom layouts based on design and process co-optimization. The method includes various design rule checks that can be used on-the-fly during leaf-cell layout development. We extract a Layout Regularity Index (LRI) from the layouts based on the jogs, alignments and pitches used in the design for any given metal layer. Regularity Index of a layout is the direct indicator of manufacturing yield and is used to compare the relative health of different layout blocks in terms of process friendliness. The method has been deployed for 28nm and 40nm technology nodes for Memory IP and is being extended to other IPs (IO, standard-cell). We have quantified the gain of layout regularity with the deployed method on printability and electrical characteristics by process-variation (PV) band simulation analysis and have achieved up-to 5nm reduction in PV band.

Highly efficient simulation environment for HDTV video decoder in VLSI design

NASA Astrophysics Data System (ADS)

Mao, Xun; Wang, Wei; Gong, Huimin; He, Yan L.; Lou, Jian; Yu, Lu; Yao, Qingdong; Pirsch, Peter

2002-01-01

With the increase of the complex of VLSI such as the SoC (System on Chip) of MPEG-2 Video decoder with HDTV scalability especially, simulation and verification of the full design, even as high as the behavior level in HDL, often proves to be very slow, costly and it is difficult to perform full verification until late in the design process. Therefore, they become bottleneck of the procedure of HDTV video decoder design, and influence it's time-to-market mostly. In this paper, the architecture of Hardware/Software Interface of HDTV video decoder is studied, and a Hardware-Software Mixed Simulation (HSMS) platform is proposed to check and correct error in the early design stage, based on the algorithm of MPEG-2 video decoding. The application of HSMS to target system could be achieved by employing several introduced approaches. Those approaches speed up the simulation and verification task without decreasing performance.

Learning Layouts for Single-Page Graphic Designs.

PubMed

O'Donovan, Peter; Agarwala, Aseem; Hertzmann, Aaron

2014-08-01

This paper presents an approach for automatically creating graphic design layouts using a new energy-based model derived from design principles. The model includes several new algorithms for analyzing graphic designs, including the prediction of perceived importance, alignment detection, and hierarchical segmentation. Given the model, we use optimization to synthesize new layouts for a variety of single-page graphic designs. Model parameters are learned with Nonlinear Inverse Optimization (NIO) from a small number of example layouts. To demonstrate our approach, we show results for applications including generating design layouts in various styles, retargeting designs to new sizes, and improving existing designs. We also compare our automatic results with designs created using crowdsourcing and show that our approach performs slightly better than novice designers.

Design space exploration for early identification of yield limiting patterns

NASA Astrophysics Data System (ADS)

Li, Helen; Zou, Elain; Lee, Robben; Hong, Sid; Liu, Square; Wang, JinYan; Du, Chunshan; Zhang, Recco; Madkour, Kareem; Ali, Hussein; Hsu, Danny; Kabeel, Aliaa; ElManhawy, Wael; Kwan, Joe

2016-03-01

In order to resolve the causality dilemma of which comes first, accurate design rules or real designs, this paper presents a flow for exploration of the layout design space to early identify problematic patterns that will negatively affect the yield. A new random layout generating method called Layout Schema Generator (LSG) is reported in this paper, this method generates realistic design-like layouts without any design rule violation. Lithography simulation is then used on the generated layout to discover the potentially problematic patterns (hotspots). These hotspot patterns are further explored by randomly inducing feature and context variations to these identified hotspots through a flow called Hotspot variation Flow (HSV). Simulation is then performed on these expanded set of layout clips to further identify more problematic patterns. These patterns are then classified into design forbidden patterns that should be included in the design rule checker and legal patterns that need better handling in the RET recipes and processes.

Automatic Layout Design for Power Module

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ning, Puqi; Wang, Fei; Ngo, Khai

The layout of power modules is one of the most important elements in power module design, especially for high power densities, where couplings are increased. In this paper, an automatic design process using a genetic algorithm is presented. Some practical considerations are introduced in the optimization of the layout design of the module. This paper presents a process for automatic layout design for high power density modules. Detailed GA implementations are introduced both for outer loop and inner loop. As verified by a design example, the results of the automatic design process presented here are better than those from manualmore » design and also better than the results from a popular design software. This automatic design procedure could be a major step toward improving the overall performance of future layout design.« less

Embeddable Reconfigurable Neuroprocessors

NASA Technical Reports Server (NTRS)

Daud, Taher; Duong, Tuan; Langenbacher, Harry; Tran, Mua; Thakoor, Anil

1993-01-01

Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

NASA Technical Reports Server (NTRS)

Truong, T. K.; Hsu, I. S.; Chang, J. J.; Shyu, H. C.; Reed, I. S.

1986-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

NASA Technical Reports Server (NTRS)

Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

1987-01-01

A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

VLSI Design of Trusted Virtual Sensors.

PubMed

Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

2018-01-25

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

VLSI Design of Trusted Virtual Sensors

PubMed Central

2018-01-01

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μs. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time). PMID:29370141

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

NASA Astrophysics Data System (ADS)

Castro-Lopez, Rafael; Fernandez, Francisco V.; Rodriguez Vazquez, Angel

2005-06-01

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.

A flexible layout design method for passive micromixers.

PubMed

Deng, Yongbo; Liu, Zhenyu; Zhang, Ping; Liu, Yongshun; Gao, Qingyong; Wu, Yihui

2012-10-01

This paper discusses a flexible layout design method of passive micromixers based on the topology optimization of fluidic flows. Being different from the trial and error method, this method obtains the detailed layout of a passive micromixer according to the desired mixing performance by solving a topology optimization problem. Therefore, the dependence on the experience of the designer is weaken, when this method is used to design a passive micromixer with acceptable mixing performance. Several design disciplines for the passive micromixers are considered to demonstrate the flexibility of the layout design method for passive micromixers. These design disciplines include the approximation of the real 3D micromixer, the manufacturing feasibility, the spacial periodic design, and effects of the Péclet number and Reynolds number on the designs obtained by this layout design method. The capability of this design method is validated by several comparisons performed between the obtained layouts and the optimized designs in the recently published literatures, where the values of the mixing measurement is improved up to 40.4% for one cycle of the micromixer.

Selecting a pharmacy layout design using a weighted scoring system.

PubMed

McDowell, Alissa L; Huang, Yu-Li

2012-05-01

A weighted scoring system was used to select a pharmacy layout redesign. Facilities layout design techniques were applied at a local hospital pharmacy using a step-by-step design process. The process involved observing and analyzing the current situation, observing the current available space, completing activity flow charts of the pharmacy processes, completing communication and material relationship charts to detail which areas in the pharmacy were related to one another and how they were related, researching applications in other pharmacies or in scholarly works that could be beneficial, numerically defining space requirements for areas within the pharmacy, measuring the available space within the pharmacy, developing a set of preliminary designs, and modifying preliminary designs so they were all acceptable to the pharmacy staff. To select a final layout that could be implemented in the pharmacy, those layouts were compared via a weighted scoring system. The weighted aspect further allowed additional emphasis on categories based on their effect on pharmacy performance. The results produced a beneficial layout design as determined through simulated models of the pharmacy operation that more effectively allocated and strategically located space to improve transportation distances and materials handling, employee utilization, and ergonomics. Facilities layout designs for a hospital pharmacy were evaluated using a weighted scoring system to identify a design that was superior to both the current layout and alternative layouts in terms of feasibility, cost, patient safety, employee safety, flexibility, robustness, transportation distance, employee utilization, objective adherence, maintainability, usability, and environmental impact.

Using pattern based layout comparison for a quick analysis of design changes

NASA Astrophysics Data System (ADS)

Huang, Lucas; Yang, Legender; Kan, Huan; Zou, Elain; Wan, Qijian; Du, Chunshan; Hu, Xinyi; Liu, Zhengfang

2018-03-01

A design usually goes through several versions until achieving a most successful one. These changes between versions are not a complete substitution but a continual improvement, either fixing the known issues of its prior versions (engineering change order) or a more optimized design substitution of a portion of the design. On the manufacturing side, process engineers care more about the design pattern changes because any new pattern occurrence may be a killer of the yield. An effective and efficient way to narrow down the diagnosis scope appeals to the engineers. What is the best approach of comparing two layouts? A direct overlay of two layouts may not always work as even though most of the design instances will be kept in the layout from version to version, the actual placements may be different. An alternative way, pattern based layout comparison, comes to play. By expanding this application, it makes it possible to transfer the learning in one cycle to another and accelerate the process of failure analysis. This paper presents a solution to compare two layouts by using Calibre DRC and Pattern Matching. The key step in this flow is layout decomposition. In theory, with a fixed pattern size, a layout can always be decomposed into limited number of patterns by moving the pattern center around the layout, the number is limited but may be huge if the layout is not processed smartly! A mathematical answer is not what we are looking for but an engineering solution is more desired. Layouts must be decomposed into patterns with physical meaning in a smart way. When a layout is decomposed and patterns are classified, a pattern library with unique patterns inside is created for that layout. After individual pattern libraries for each layout are created, run pattern comparison utility provided by Calibre Pattern Matching to compare the pattern libraries, unique patterns will come out for each layout. This paper illustrates this flow in details and demonstrates the advantage of combining Calibre DRC and Calibre Pattern Matching.

Automatic Layout Design for Power Module

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ning, Puqi; Wang, Fei; Ngo, Khai

The layout of power modules is one of the key points in power module design, especially for high power densities, where couplings are increased. In this paper, along with the design example, an automatic design processes by using a genetic algorithm are presented. Some practical considerations and implementations are introduced in the optimization of module layout design.

A Tool for the Automated Design and Evaluation of Habitat Interior Layouts

NASA Technical Reports Server (NTRS)

Simon, Matthew A.; Wilhite, Alan W.

2013-01-01

The objective of space habitat design is to minimize mass and system size while providing adequate space for all necessary equipment and a functional layout that supports crew health and productivity. Unfortunately, development and evaluation of interior layouts is often ignored during conceptual design because of the subjectivity and long times required using current evaluation methods (e.g., human-in-the-loop mockup tests and in-depth CAD evaluations). Early, more objective assessment could prevent expensive design changes that may increase vehicle mass and compromise functionality. This paper describes a new interior design evaluation method to enable early, structured consideration of habitat interior layouts. This interior layout evaluation method features a comprehensive list of quantifiable habitat layout evaluation criteria, automatic methods to measure these criteria from a geometry model, and application of systems engineering tools and numerical methods to construct a multi-objective value function measuring the overall habitat layout performance. In addition to a detailed description of this method, a C++/OpenGL software tool which has been developed to implement this method is also discussed. This tool leverages geometry modeling coupled with collision detection techniques to identify favorable layouts subject to multiple constraints and objectives (e.g., minimize mass, maximize contiguous habitable volume, maximize task performance, and minimize crew safety risks). Finally, a few habitat layout evaluation examples are described to demonstrate the effectiveness of this method and tool to influence habitat design.

HDL to verification logic translator

NASA Technical Reports Server (NTRS)

Gambles, J. W.; Windley, P. J.

1992-01-01

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

Supporting the design of office layout meeting ergonomics requirements.

PubMed

Margaritis, Spyros; Marmaras, Nicolas

2007-11-01

This paper proposes a method and an information technology tool aiming to support the ergonomics layout design of individual workstations in a given space (building). The proposed method shares common ideas with previous generic methods for office layout. However, it goes a step forward and focuses on the cognitive tasks which have to be carried out by the designer or the design team trying to alleviate them. This is achieved in two ways: (i) by decomposing the layout design problem to six main stages, during which only a limited number of variables and requirements are considered and (ii) by converting the ergonomics requirements to functional design guidelines. The information technology tool (ErgoOffice 0.1) automates certain phases of the layout design process, and supports the design team either by its editing and graphical facilities or by providing adequate memory support.

Safety assessment in plant layout design using indexing approach: implementing inherent safety perspective. Part 2-Domino Hazard Index and case study.

PubMed

Tugnoli, Alessandro; Khan, Faisal; Amyotte, Paul; Cozzani, Valerio

2008-12-15

The design of layout plans requires adequate assessment tools for the quantification of safety performance. The general focus of the present work is to introduce an inherent safety perspective at different points of the layout design process. In particular, index approaches for safety assessment and decision-making in the early stages of layout design are developed and discussed in this two-part contribution. Part 1 (accompanying paper) of the current work presents an integrated index approach for safety assessment of early plant layout. In the present paper (Part 2), an index for evaluation of the hazard related to the potential of domino effects is developed. The index considers the actual consequences of possible escalation scenarios and scores or ranks the subsequent accident propagation potential. The effects of inherent and passive protection measures are also assessed. The result is a rapid quantification of domino hazard potential that can provide substantial support for choices in the early stages of layout design. Additionally, a case study concerning selection among various layout options is presented and analyzed. The case study demonstrates the use and applicability of the indices developed in both parts of the current work and highlights the value of introducing inherent safety features early in layout design.

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

NASA Technical Reports Server (NTRS)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

The test of VLSI circuits

NASA Astrophysics Data System (ADS)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Compact VLSI neural computer integrated with active pixel sensor for real-time ATR applications

NASA Astrophysics Data System (ADS)

Fang, Wai-Chi; Udomkesmalee, Gabriel; Alkalai, Leon

1997-04-01

A compact VLSI neural computer integrated with an active pixel sensor has been under development to mimic what is inherent in biological vision systems. This electronic eye- brain computer is targeted for real-time machine vision applications which require both high-bandwidth communication and high-performance computing for data sensing, synergy of multiple types of sensory information, feature extraction, target detection, target recognition, and control functions. The neural computer is based on a composite structure which combines Annealing Cellular Neural Network (ACNN) and Hierarchical Self-Organization Neural Network (HSONN). The ACNN architecture is a programmable and scalable multi- dimensional array of annealing neurons which are locally connected with their local neurons. Meanwhile, the HSONN adopts a hierarchical structure with nonlinear basis functions. The ACNN+HSONN neural computer is effectively designed to perform programmable functions for machine vision processing in all levels with its embedded host processor. It provides a two order-of-magnitude increase in computation power over the state-of-the-art microcomputer and DSP microelectronics. A compact current-mode VLSI design feasibility of the ACNN+HSONN neural computer is demonstrated by a 3D 16X8X9-cube neural processor chip design in a 2-micrometers CMOS technology. Integration of this neural computer as one slice of a 4'X4' multichip module into the 3D MCM based avionics architecture for NASA's New Millennium Program is also described.

Research Plan of the Department of Systems Engineering and the Operations Research Center for the Academic Year 2006

DTIC Science & Technology

2005-09-01

Facilities Layout o Scope problem with client in terms of options for M&S facilities layouts with regards to infrastructure, personnel... Facilities Layout o Develop M&S Installation Facilities Layout Design(s) Requirements and Milestones: • Scope problem with client (systems on which...objectives of this study are to (a) identify the desired technology and facilities layouts which would enhance inter-installation simulation

A novel method for designing and optimizing the layout of facilities in bathroom for the elderly in home-based rehabilitation.

PubMed

Wang, Duojin; Wu, Jing; Lin, Qinglian

2018-05-01

The home-based rehabilitation of elderly patients improves their autonomy, independence and reintegration into society. Hence, a suitable environment plays an important role in rehabilitation, as do different assistance technologies. The majority of accidents at home involving elderly people occur in the bathroom. Therefore, the planning of the layout of facilities is important in this potentially dangerous area. This paper proposes an approach towards designing and optimizing the layout of facilities in the bathroom, based on logistical and nonlogistical relationships. A fuzzy-based analytical hierarchical process (fuzzy-AHP) is then proposed for a comprehensive evaluation of the alternatives for this layout plan. This approach was applied to the home of a 71 years old female patient, who was experiencing home-based rehabilitation. After the initial designing and optimizing of the layout of the facilities in her bathroom, a plan could then be created for her particular needs. The results of this research could then enable the home-based rehabilitation of elderly patients to be more effective. Value: This paper develops a new approach to design and optimize the layout of facilities in bathroom for the elderly. Implications for Rehabilitation Develop a new approach to design and optimize the layout of facilities in bathroom. Provide a mathematical and more scientific approach to home layout design for home-based rehabilitation. Provide new opportunities for research, for both the therapist and the patient to analyse the home facility layout.

Ultra high speed image processing techniques. [electronic packaging techniques

NASA Technical Reports Server (NTRS)

Anthony, T.; Hoeschele, D. F.; Connery, R.; Ehland, J.; Billings, J.

1981-01-01

Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels.

WARP: Weight Associative Rule Processor. A dedicated VLSI fuzzy logic megacell

NASA Technical Reports Server (NTRS)

Pagni, A.; Poluzzi, R.; Rizzotto, G. G.

1992-01-01

During the last five years Fuzzy Logic has gained enormous popularity in the academic and industrial worlds. The success of this new methodology has led the microelectronics industry to create a new class of machines, called Fuzzy Machines, to overcome the limitations of traditional computing systems when utilized as Fuzzy Systems. This paper gives an overview of the methods by which Fuzzy Logic data structures are represented in the machines (each with its own advantages and inefficiencies). Next, the paper introduces WARP (Weight Associative Rule Processor) which is a dedicated VLSI megacell allowing the realization of a fuzzy controller suitable for a wide range of applications. WARP represents an innovative approach to VLSI Fuzzy controllers by utilizing different types of data structures for characterizing the membership functions during the various stages of the Fuzzy processing. WARP dedicated architecture has been designed in order to achieve high performance by exploiting the computational advantages offered by the different data representations.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Optimal Control Surface Layout for an Aeroservoelastic Wingbox

NASA Technical Reports Server (NTRS)

Stanford, Bret K.

2017-01-01

This paper demonstrates a technique for locating the optimal control surface layout of an aeroservoelastic Common Research Model wingbox, in the context of maneuver load alleviation and active utter suppression. The combinatorial actuator layout design is solved using ideas borrowed from topology optimization, where the effectiveness of a given control surface is tied to a layout design variable, which varies from zero (the actuator is removed) to one (the actuator is retained). These layout design variables are optimized concurrently with a large number of structural wingbox sizing variables and control surface actuation variables, in order to minimize the sum of structural weight and actuator weight. Results are presented that demonstrate interdependencies between structural sizing patterns and optimal control surface layouts, for both static and dynamic aeroelastic physics.

Analysis on flexible manufacturing system layout using arena simulation software

NASA Astrophysics Data System (ADS)

Fadzly, M. K.; Saad, Mohd Sazli; Shayfull, Z.

2017-09-01

Flexible manufacturing system (FMS) was defined as highly automated group technology machine cell, consisting of a group of processing stations interconnected by an automated material handling and storage system, and controlled by an integrated computer system. FMS can produce parts or products are in the mid-volume, mid-variety production range. The layout system in FMS is an important criterion to design the FMS system to produce a part or product. This facility layout of an FMS involves the positioning of cells within given boundaries, so as to minimize the total projected travel time between cells. Defining the layout includes specifying the spatial coordinates of each cell, its orientation in either a horizontal or vertical position, and the location of its load or unloads point. There are many types of FMS layout such as In-line, loop ladder and robot centered cell layout. The research is concentrating on the design and optimization FMS layout. The final conclusion can be summarized that the objective to design and optimisation of FMS layout for this study is successful because the FMS In-line layout is the best layout based on effective time and cost using ARENA simulation software.

Safety assessment in plant layout design using indexing approach: implementing inherent safety perspective. Part 1 - guideword applicability and method description.

PubMed

Tugnoli, Alessandro; Khan, Faisal; Amyotte, Paul; Cozzani, Valerio

2008-12-15

Layout planning plays a key role in the inherent safety performance of process plants since this design feature controls the possibility of accidental chain-events and the magnitude of possible consequences. A lack of suitable methods to promote the effective implementation of inherent safety in layout design calls for the development of new techniques and methods. In the present paper, a safety assessment approach suitable for layout design in the critical early phase is proposed. The concept of inherent safety is implemented within this safety assessment; the approach is based on an integrated assessment of inherent safety guideword applicability within the constraints typically present in layout design. Application of these guidewords is evaluated along with unit hazards and control devices to quantitatively map the safety performance of different layout options. Moreover, the economic aspects related to safety and inherent safety are evaluated by the method. Specific sub-indices are developed within the integrated safety assessment system to analyze and quantify the hazard related to domino effects. The proposed approach is quick in application, auditable and shares a common framework applicable in other phases of the design lifecycle (e.g. process design). The present work is divided in two parts: Part 1 (current paper) presents the application of inherent safety guidelines in layout design and the index method for safety assessment; Part 2 (accompanying paper) describes the domino hazard sub-index and demonstrates the proposed approach with a case study, thus evidencing the introduction of inherent safety features in layout design.

Issues in Text Design and Layout for Computer Based Communications.

ERIC Educational Resources Information Center

Andresen, Lee W.

1991-01-01

Discussion of computer-based communications (CBC) focuses on issues involved with screen design and layout for electronic text, based on experiences with electronic messaging, conferencing, and publishing within the Australian Open Learning Information Network (AOLIN). Recommendations for research on design and layout for printed text are also…

Topology-optimized metasurfaces: impact of initial geometric layout.

PubMed

Yang, Jianji; Fan, Jonathan A

2017-08-15

Topology optimization is a powerful iterative inverse design technique in metasurface engineering and can transform an initial layout into a high-performance device. With this method, devices are optimized within a local design phase space, making the identification of suitable initial geometries essential. In this Letter, we examine the impact of initial geometric layout on the performance of large-angle (75 deg) topology-optimized metagrating deflectors. We find that when conventional metasurface designs based on dielectric nanoposts are used as initial layouts for topology optimization, the final devices have efficiencies around 65%. In contrast, when random initial layouts are used, the final devices have ultra-high efficiencies that can reach 94%. Our numerical experiments suggest that device topologies based on conventional metasurface designs may not be suitable to produce ultra-high-efficiency, large-angle metasurfaces. Rather, initial geometric layouts with non-trivial topologies and shapes are required.

Constructing an optimal facility layout to maximize adjacency as a function of common boundary length

NASA Astrophysics Data System (ADS)

Ghassemi Tari, Farhad; Neghabi, Hossein

2018-03-01

An effective facility layout implies that departments with high flow are laid adjacent. However, in the case of a very narrow boundary length between the neighbouring departments, the adjacency would actually be useless. In traditional layout design methods, a score is generally assigned independent of the department's boundary length. This may result in a layout design with a restricted material flow. This article proposes a new concept of adjacency in which the department pairs are laid adjacent with a wider path. To apply this concept, a shop with unequal rectangular departments is contemplated and a mathematical programming model with the objective of maximizing the sum of the adjacency degrees is proposed. A computational experiment is conducted to demonstrate the efficiency of the layout design. It is demonstrated that the new concept provides a more efficient and a more realistic layout design.

Coach design for the Korean high-speed train: a systematic approach to passenger seat design and layout.

PubMed

Jung, E S; Han, S H; Jung, M; Choe, J

1998-12-01

Proper ergonomic design of a passenger seat and coach layout for a high-speed train is an essential component that is directly related to passenger comfort. In this research, a systematic approach to the design of passenger seats was described and the coach layout which reflected the tradeoff between transportation capacity and passenger comfort was investigated for the Korean high-speed train. As a result, design recommendations and specifications of the passenger seat and its layout were suggested. The whole design process is composed of four stages. A survey and analysis of design requirement was first conducted, which formed the base for designing the first and second class passenger seats. Prototypes were made and evaluated iteratively, and seat arrangement and coach layout were finally obtained. The systematic approach and recommendations suggested in this study are expected to be applicable to the seat design for public transportations and to help modify and redesign existing vehicular seats.

EM calibration based on Post OPC layout analysis

NASA Astrophysics Data System (ADS)

Sreedhar, Aswin; Kundu, Sandip

2010-03-01

Design for Manufacturability (DFM) involves changes to the design and CAD tools to help increase pattern printability and improve process control. Design for Reliability (DFR) performs the same to improve reliability of devices from failures such as Electromigration (EM), gate-oxide break down, hot carrier injection (HCI), Negative Bias Temperature Insatiability (NBTI) and mechanical stress effects. Electromigration (EM) occurs due to migration or displacement of atoms as a result of the movement of electrons through a conducting medium. The rate of migration determines the Mean Time to Failure (MTTF) which is modeled as a function of temperature and current density. The model itself is calibrated through failure analysis (FA) of parts that are deemed to have failed due to EM against design parameters such as linewidth. Reliability Verification (RV) of a design involves verifying that every conducting line in a design meets certain MTTF threshold. In order to perform RV, current density for each wire must be computed. Current itself is a function of the parasitics that are determined through RC extraction. The standard practice is to perform the RC extraction and current density calculation on drawn, pre-OPC layouts. If a wire fails to meet threshold for MTTF, it may be resized. Subsequently, mask preparation steps such as OPC and PSM introduce extra features such as SRAFs, jogs,hammerheads and serifs that change their resistance, capacitance and current density values. Hence, calibrating EM model based on pre-OPC layouts will lead to different results compared to post-OPC layouts. In this work, we compare EM model calibration and reliability check based on drawn layout versus predicted layout, where the drawn layout is pre-OPC layout and predicted layout is based on litho simulation of post-OPC layout. Results show significant divergence between these two approaches, making a case for methodology based on predicted layout.

DSS 13 phase 2 pedestal room microwave layout

NASA Technical Reports Server (NTRS)

Cwik, T.; Chen, J. C.

1991-01-01

The design and predicted performance is described of the microwave layout for three band operation of the beam waveguide antenna Deep Space Station 13. Three pedestal room microwave candidate layout designs were produced for simultaneous X/S and X/Ka band operation. One of the three designs was chosen based on given constraints, and for this design the microwave performance was estimated.

Design and Implementation of a New Real-Time Frequency Sensor Used as Hardware Countermeasure

PubMed Central

Jiménez-Naharro, Raúl; Gómez-Galán, Juan Antonio; Sánchez-Raya, Manuel; Gómez-Bravo, Fernando; Pedro-Carrasco, Manuel

2013-01-01

A new digital countermeasure against attacks related to the clock frequency is –presented. This countermeasure, known as frequency sensor, consists of a local oscillator, a transition detector, a measurement element and an output block. The countermeasure has been designed using a full-custom technique implemented in an Application-Specific Integrated Circuit (ASIC), and the implementation has been verified and characterized with an integrated design using a 0.35 μm standard Complementary Metal Oxide Semiconductor (CMOS) technology (Very Large Scale Implementation—VLSI implementation). The proposed solution is configurable in resolution time and allowed range of period, achieving a minimum resolution time of only 1.91 ns and an initialization time of 5.84 ns. The proposed VLSI implementation shows better results than other solutions, such as digital ones based on semi-custom techniques and analog ones based on band pass filters, all design parameters considered. Finally, a counter has been used to verify the good performance of the countermeasure in avoiding the success of an attack. PMID:24008285

Submicron Systems Architecture Project

DTIC Science & Technology

1981-11-01

This project is concerned with the architecture , design , and testing of VLSI Systems. The principal activities in this report period include: The Tree Machine; COPE, The Homogeneous Machine; Computational Arrays; Switch-Level Model for MOS Logic Design; Testing; Local Network and Designer Workstations; Self-timed Systems; Characterization of Deadlock Free Resource Contention; Concurrency Algebra; Language Design and Logic for Program Verification.

A VLSI pipeline design of a fast prime factor DFT on a finite field

NASA Technical Reports Server (NTRS)

Truong, T. K.; Hsu, I. S.; Shao, H. M.; Reed, I. S.; Shyu, H. C.

1986-01-01

A conventional prime factor discrete Fourier transform (DFT) algorithm is used to realize a discrete Fourier-like transform on the finite field, GF(q sub n). A pipeline structure is used to implement this prime factor DFT over GF(q sub n). This algorithm is developed to compute cyclic convolutions of complex numbers and to decode Reed-Solomon codes. Such a pipeline fast prime factor DFT algorithm over GF(q sub n) is regular, simple, expandable, and naturally suitable for VLSI implementation. An example illustrating the pipeline aspect of a 30-point transform over GF(q sub n) is presented.

Automatic page composition with nested sub-layouts

NASA Astrophysics Data System (ADS)

Hunter, Andrew

2013-03-01

This paper provides an overview of a system for the automatic composition of publications. The system first composes nested hierarchies of contents, then applies layout engines at branch points in the hierarchies to explore layout options, and finally selects the best overall options for the finished publications. Although the system has been developed as a general platform for automated publishing, this paper describes its application to the composition and layout of a magazine-like publication for social content from Facebook. The composition process works by assembling design fragments that have been populated with text and images from the Facebook social network. The fragments constitute a design language for a publication. Each design fragment is a nested mutable sub-layout that has no specific size or shape until after it has been laid-out. The layout process balances the space requirements of the fragment's internal contents with its external context in the publication. The mutability of sub-layouts requires that their layout options must be kept open until all the other contents that share the same space have been considered. Coping with large numbers of options is one of the greatest challenges in layout automation. Most existing layout methods work by rapidly elimination design options rather than by keeping options open. A further goal of this publishing system is to confirm that a custom publication can be generated quickly by the described methods. In general, the faster that publications can be created, the greater the opportunities for the technology.

Layout compliance for triple patterning lithography: an iterative approach

NASA Astrophysics Data System (ADS)

Yu, Bei; Garreton, Gilda; Pan, David Z.

2014-10-01

As the semiconductor process further scales down, the industry encounters many lithography-related issues. In the 14nm logic node and beyond, triple patterning lithography (TPL) is one of the most promising techniques for Metal1 layer and possibly Via0 layer. As one of the most challenging problems in TPL, recently layout decomposition efforts have received more attention from both industry and academia. Ideally the decomposer should point out locations in the layout that are not triple patterning decomposable and therefore manual intervention by designers is required. A traditional decomposition flow would be an iterative process, where each iteration consists of an automatic layout decomposition step and manual layout modification task. However, due to the NP-hardness of triple patterning layout decomposition, automatic full chip level layout decomposition requires long computational time and therefore design closure issues continue to linger around in the traditional flow. Challenged by this issue, we present a novel incremental layout decomposition framework to facilitate accelerated iterative decomposition. In the first iteration, our decomposer not only points out all conflicts, but also provides the suggestions to fix them. After the layout modification, instead of solving the full chip problem from scratch, our decomposer can provide a quick solution for a selected portion of layout. We believe this framework is efficient, in terms of performance and designer friendly.

A new eddy current model for magnetic bearing control system design

NASA Technical Reports Server (NTRS)

Feeley, Joseph J.; Ahlstrom, Daniel J.

1992-01-01

This paper describes a new VLSI-based controller for the implementation of a Linear-Quadratic-Gaussian (LQG) theory-based control system. Use of the controller is demonstrated by design of a controller for a magnetic bearing and its performance is evaluated by computer simulation.

Model aerodynamic test results for two variable cycle engine coannular exhaust systems at simulated takeoff and cruise conditions. Comprehensive data report. Volume 1: Design layouts

NASA Technical Reports Server (NTRS)

Nelson, D. P.

1981-01-01

The design layouts and detailed design drawings of coannular exhaust nozzle models for a supersonic propulsion system are presented. The layout drawings show the assembly of the component parts for each configuration. A listing of the component parts is also given.

ProperCAD: A portable object-oriented parallel environment for VLSI CAD

NASA Technical Reports Server (NTRS)

Ramkumar, Balkrishna; Banerjee, Prithviraj

1993-01-01

Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

The effect of design modifications to the typographical layout of the New York State elementary science learning standards on user preference and process time

NASA Astrophysics Data System (ADS)

Arnold, Jeffery E.

The purpose of this study was to determine the effect of four different design layouts of the New York State elementary science learning standards on user processing time and preference. Three newly developed layouts contained the same information as the standards core curriculum. In this study, the layout of the core guide is referred to as Book. The layouts of the new documents are referred to as Chart, Map, and Tabloid based on the format used to convey content hierarchy information. Most notably, all the new layouts feature larger page sizes, color, page tabs, and an icon based navigation system (IBNS). A convenience sample of 48 New York State educators representing three educator types (16 pre-service teachers, 16 in-service teachers, and 16 administrators) participated in the study. After completing timed tasks accurately, participants scored each layout based on preference. Educator type and layout were the independent variables, and process time and user preference were the dependent variables. A two-factor experimental design with Educator Type as the between variable and with repeated measures on Layout, the within variable, showed a significant difference in process time for Educator Type and Layout. The main effect for Educator Type (F(2, 45) = 8.03, p <.001) was significant with an observed power of .94, and an effect size of .26. The pair-wise comparisons for process time showed that pre-service teachers (p = .02) and administrators (p =.009) completed the assigned tasks more quickly when compared to in-service teachers. The main effect for Layout (F(3, 135) = 4.47, p =.01) was also significant with an observed power of .80, and an effect size of .09. Pair-wise comparisons showed that the newly developed Chart (p = .019) and Map (p = .032) layouts reduced overall process time when compared to the existing state learning standards (Book). The Layout X Educator type interaction was not significant. The same two-factor experimental design on preference, showed the main effect for Layout (F(3, 135) = 28.43, p =.001) was significant. The observed power was 1.0, with an effect size of .39. Pair-wise comparisons for preference scores showed that the Chart (p = .001), Map (p = .001), and Tabloid (p = .001) were preferred over the Book layout. The Layout Type X Educator Type interaction and the main effect for Educator Type were not significant. This study provides evidence that the newly developed design layouts improve usability (as measured by process time and preference scores) of the New York State elementary science learning standard documents. Features in the new layout design, such as the IBNS, may provide a foundation for a visual language and aid users in navigating standard documents across grade level and subject areas. Implications for the next generation of standard documents are presented.

Occupational Survey Report. Visual Information, AFSC 3V0X1

DTIC Science & Technology

2000-04-01

of the career ladder include: Scan artwork using flatbed scanners Convert graphic file formats Design layouts Letter certificates using laser...Design layouts Scan artwork using flatbed scanners Produce artwork using mouse or digitizing tablets Design and produce imagery for web pages Produce...DAFSC 3V031 PERSONNEL TASKS A0034 Scan artwork using flatbed scanners C0065 Design layouts A0004 Convert graphic file formats A0006 Create

Low Carbon Design Research on the Space Layout Types of Office Buildings

NASA Astrophysics Data System (ADS)

Xia, Bing

2018-01-01

It is beneficial to find out the relationship of the spatial layout and low-carbon design in order to reduce buildings’ carbon emissions in the conceptual design phase. This paper analyzes and compares shape coefficient values, annual energy consumption and lighting performance of office buildings of different space layout types in Shanghai. Based on morphological characteristics of different types, the study also analyzes and presents low-carbon design strategies for each single type. This study assumes that architects should conduct passive and active design according to the specific building space layout, so that to make best use of the advantages and bypassing the disadvantages, in order to maximally reduce buildings’ carbon emissions.

Silicon Compilation: A Solution to the Complexity of VLSI (Very Large-Scale Integrated) Circuit Design.

DTIC Science & Technology

1985-09-01

Design Language Xi." International Conference on Computer Design, pp. 652-655. 1983. [GAJ 84] D. D. Gajski and J. J. Bozek. "ARSENIC: Methodology and...Report R-1015 UIUL-ENG 84-2209. August 1984. [LUR 84] C. Lursinsap and D. Gajski , "Cell Compilation with Constraints." Proceedings of the 21st Design

Very Large Scale Integration (VLSI).

ERIC Educational Resources Information Center

Yeaman, Andrew R. J.

Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

The Effect of Design Modifications to the Typographical Layout of the New York State Elementary Science Learning Standards on User Preference and Process Time

ERIC Educational Resources Information Center

Arnold, Jeffery E.

2010-01-01

The purpose of this study was to determine the effect of four different design layouts of the New York State elementary science learning standards on user processing time and preference. Three newly developed layouts contained the same information as the standards core curriculum. In this study, the layout of the core guide is referred to as Book.…

The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.; Shao, H. M.; Deutsch, L. J.

1987-01-01

The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

GaAs VLSI for aerospace electronics

NASA Technical Reports Server (NTRS)

Larue, G.; Chan, P.

1990-01-01

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

41 CFR 102-85.35 - What definitions apply to this part?

Code of Federal Regulations, 2011 CFR

2011-01-01

..., due to its layout, design, location, or other characteristics, is unlikely to be needed by another GSA... professional techniques of planning, layout and interior design to determine the best internal location and the... definition of “tenant improvement.” Initial space layout means the specific placement of workstations...

41 CFR 102-85.35 - What definitions apply to this part?

Code of Federal Regulations, 2013 CFR

2013-07-01

..., due to its layout, design, location, or other characteristics, is unlikely to be needed by another GSA... professional techniques of planning, layout and interior design to determine the best internal location and the... definition of “tenant improvement.” Initial space layout means the specific placement of workstations...

41 CFR 102-85.35 - What definitions apply to this part?

Code of Federal Regulations, 2012 CFR

2012-01-01

..., due to its layout, design, location, or other characteristics, is unlikely to be needed by another GSA... professional techniques of planning, layout and interior design to determine the best internal location and the... definition of “tenant improvement.” Initial space layout means the specific placement of workstations...

41 CFR 102-85.35 - What definitions apply to this part?

Code of Federal Regulations, 2014 CFR

2014-01-01

..., due to its layout, design, location, or other characteristics, is unlikely to be needed by another GSA... professional techniques of planning, layout and interior design to determine the best internal location and the... definition of “tenant improvement.” Initial space layout means the specific placement of workstations...

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Summary of workshop on the application of VLSI for robotic sensing

NASA Technical Reports Server (NTRS)

Brooks, T.; Wilcox, B.

1984-01-01

It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

PLA realizations for VLSI state machines

NASA Technical Reports Server (NTRS)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

New business opportunity: Green field project with new technology

NASA Astrophysics Data System (ADS)

Lee, Seung Jae; Woo, Jong Hun; Shin, Jong Gye

2014-06-01

Since 2009 of global financial crisis, shipbuilding industry has undergone hard times seriously. After such a long depression, the latest global shipping market index shows that the economic recovery of global shipbuilding market is underway. Especially, nations with enormous resources are going to increase their productivity or expanding their shipyards to accommodate a large amount of orders expected in the near future. However, few commercial projects have been carried out for the practical shipyard layout designs even though those can be good commercial opportunities for shipbuilding engineers. Shipbuilding starts with a shipyard construction with a large scale investment initially. Shipyard design and the equipment layout problem, which is directly linked to the productivity of ship production, is an important issue in the production planning of mass production of ships. In many cases, shipbuilding yard design has relied on the experience of the internal engineer, resulting in sporadic and poorly organized processes. Consequently, economic losses and the trial and error involved in such a design process are inevitable problems. The starting point of shipyard construction is to design a shipyard layout. Four kinds of engineering parts required for the shipyard layout design and construction. Those are civil engineering, building engineering, utility engineering and production layout engineering. Among these parts, production layout engineering is most important because its result is used as a foundation of the other engineering parts, and also, determines the shipyard capacity in the shipyard lifecycle. In this paper, the background of shipbuilding industry is explained in terms of engineering works for the recognition of the macro trend. Nextly, preliminary design methods and related case study is introduced briefly by referencing the previous research. Lastly, the designed work of layout design is validated using the computer simulation technology.

Layout as Political Expression: Visual Literacy and the Peruvian Press.

ERIC Educational Resources Information Center

Barnhurst, Kevin G.

Newspaper layout and design studies ignore politics, and most studies of newspaper politics ignore visual design. News layout is generally thought to be a set of neutral, efficient practices. This study suggests that the political position of Peruvian newspapers parallels their visual presentation of terrorism. The liberal "La Republica"…

Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond

NASA Astrophysics Data System (ADS)

Liebmann, Lars; Pileggi, Larry; Hibbeler, Jason; Rovner, Vyacheslav; Jhaveri, Tejas; Northrop, Greg

2009-03-01

The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed. Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a 65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the integrated process-design co-optimization, is introduced.

New shipyard layout design for the preliminary phase & case study for the green field project

NASA Astrophysics Data System (ADS)

Song, Young Joo; Woo, Jong Hun

2013-03-01

For several decades, Asian nations such as Korea, Japan and China have been leading the shipbuilding industry since the decline in Europe and America. However, several developing countries such as India, Brazil, etc. are going to make an entrance into the shipbuilding industry. These developing countries are finding technical partners or information providers because they are in situation of little experiences and technologies. Now, the shipbuilding engineering companies of shipbuilding advanced countries are getting a chance of engineering business against those developing countries. The starting point of this business model is green field project for the construction of new shipyard. This business model is started with a design of the shipyard layout. For the conducting of the shipyard layout design, four kinds of engineering parts are required. Those are civil engineering, building engineering, utility engineering and production layout engineering. Among these parts, production layout engineering is most important because its result is the foundation of the other engineering parts and it determines the shipyard capacity during the shipyard operation lifecycle. Previous researches about the shipyard layout design are out of the range from the business requirements because most research cases are in the tower of ivory, which means that there are little consideration of real ship and shipbuilding operation. In this paper, a shipyard layout design for preliminary phase is conducted for the target of newly planned shipyard at Venezuela of South America with an integrated method that is capable of dealing with actual master data from the shipyard. The layout design method of this paper is differentiated from the previous researches in that the actual product data from the target ship and the actual shipbuilding operation data are used for the required area estimation.

Microprocessor Design Using Hardware Description Language

ERIC Educational Resources Information Center

Mita, Rosario; Palumbo, Gaetano

2008-01-01

The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

NASA Astrophysics Data System (ADS)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Automatic layout of structured hierarchical reports.

PubMed

Bakke, Eirik; Karger, David R; Miller, Robert C

2013-12-01

Domain-specific database applications tend to contain a sizable number of table-, form-, and report-style views that must each be designed and maintained by a software developer. A significant part of this job is the necessary tweaking of low-level presentation details such as label placements, text field dimensions, list or table styles, and so on. In this paper, we present a horizontally constrained layout management algorithm that automates the display of structured hierarchical data using the traditional visual idioms of hand-designed database UIs: tables, multi-column forms, and outline-style indented lists. We compare our system with pure outline and nested table layouts with respect to space efficiency and readability, the latter with an online user study on 27 subjects. Our layouts are 3.9 and 1.6 times more compact on average than outline layouts and horizontally unconstrained table layouts, respectively, and are as readable as table layouts even for large datasets.

Exact solution for the optimal neuronal layout problem.

PubMed

Chklovskii, Dmitri B

2004-10-01

Evolution perfected brain design by maximizing its functionality while minimizing costs associated with building and maintaining it. Assumption that brain functionality is specified by neuronal connectivity, implemented by costly biological wiring, leads to the following optimal design problem. For a given neuronal connectivity, find a spatial layout of neurons that minimizes the wiring cost. Unfortunately, this problem is difficult to solve because the number of possible layouts is often astronomically large. We argue that the wiring cost may scale as wire length squared, reducing the optimal layout problem to a constrained minimization of a quadratic form. For biologically plausible constraints, this problem has exact analytical solutions, which give reasonable approximations to actual layouts in the brain. These solutions make the inverse problem of inferring neuronal connectivity from neuronal layout more tractable.

78 FR 49551 - Vogtle Electric Generating Station, Units 3 and 4; Southern Nuclear Operating Company; Change to...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-14

... design and layout of the turbine building. As part of this request, the licensee needed to change the... information related to the design and layout of the Turbine Building detailed in the amendment request. These... Structures and Layout AGENCY: Nuclear Regulatory Commission. ACTION: Exemption and combined license amendment...

Optical design of the National Ignition Facility main laser and switchyard/target area beam transport systems

NASA Astrophysics Data System (ADS)

Miller, John L.; English, R. Edward, Jr.; Korniski, Ronald J.; Rodgers, J. Michael

1999-07-01

The optical design of the main laser and transport mirror sections of the National Ignition Facility are described. For the main laser the configuration, layout constraints, multiple beam arrangement, pinhole layout and beam paths, clear aperture budget, ray trace models, alignment constraints, lens designs, wavefront performance, and pupil aberrations are discussed. For the transport mirror system the layout, alignment controls and clear aperture budget are described.

Operator Station Design System - A computer aided design approach to work station layout

NASA Technical Reports Server (NTRS)

Lewis, J. L.

1979-01-01

The Operator Station Design System is resident in NASA's Johnson Space Center Spacecraft Design Division Performance Laboratory. It includes stand-alone minicomputer hardware and Panel Layout Automated Interactive Design and Crew Station Assessment of Reach software. The data base consists of the Shuttle Transportation System Orbiter Crew Compartment (in part), the Orbiter payload bay and remote manipulator (in part), and various anthropometric populations. The system is utilized to provide panel layouts, assess reach and vision, determine interference and fit problems early in the design phase, study design applications as a function of anthropometric and mission requirements, and to accomplish conceptual design to support advanced study efforts.

Automated solar collector installation design including ability to define heterogeneous design preferences

DOEpatents

Wayne, Gary; Frumkin, Alexander; Zaydman, Michael; Lehman, Scott; Brenner, Jules

2014-04-29

Embodiments may include systems and methods to create and edit a representation of a worksite, to create various data objects, to classify such objects as various types of pre -defined "features" with attendant properties and layout constraints. As part of or in addition to classification, an embodiment may include systems and methods to create, associate, and edit intrinsic and extrinsic properties to these objects. A design engine may apply of design rules to the features described above to generate one or more solar collectors installation design alternatives, including generation of on-screen and/or paper representations of the physical layout or arrangement of the one or more design alternatives. Embodiments may also include definition of one or more design apertures, each of which may correspond to boundaries in which solar collector layouts should comply with distinct sets of user-defined design preferences. Distinct apertures may provide heterogeneous regions of collector layout according to the user-defined design preferences.

Automated solar collector installation design including ability to define heterogeneous design preferences

DOEpatents

Wayne, Gary; Frumkin, Alexander; Zaydman, Michael; Lehman, Scott; Brenner, Jules

2013-01-08

Embodiments may include systems and methods to create and edit a representation of a worksite, to create various data objects, to classify such objects as various types of pre-defined "features" with attendant properties and layout constraints. As part of or in addition to classification, an embodiment may include systems and methods to create, associate, and edit intrinsic and extrinsic properties to these objects. A design engine may apply of design rules to the features described above to generate one or more solar collectors installation design alternatives, including generation of on-screen and/or paper representations of the physical layout or arrangement of the one or more design alternatives. Embodiments may also include definition of one or more design apertures, each of which may correspond to boundaries in which solar collector layouts should comply with distinct sets of user-defined design preferences. Distinct apertures may provide heterogeneous regions of collector layout according to the user-defined design preferences.

VLSI technology for smaller, cheaper, faster return link systems

NASA Technical Reports Server (NTRS)

Nanzetta, Kathy; Ghuman, Parminder; Bennett, Toby; Solomon, Jeff; Dowling, Jason; Welling, John

1994-01-01

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Evidence-based ergonomics. A comparison of Japanese and American office layouts.

PubMed

Noro, Kageyu; Fujimaki, Goroh; Kishi, Shinsuke

2003-01-01

There is a variety of alternatives in office layouts. Yet the theoretical basis and criteria for predicting how well these layouts accommodate employees are poorly understood. The objective of this study was to evaluate criteria for selecting office layouts. Intensive computer workers worked in simulated office layouts in a controlled experimental laboratory. Eye movement measures indicate that knowledge work requires both concentration and interaction. Findings pointed to one layout as providing optimum balance between these 2 requirements. Recommendations for establishing a theoretical basis and design criteria for selecting office layouts based on work style are suggested.

Schematic driven layout of Reed Solomon encoders

NASA Technical Reports Server (NTRS)

Arave, Kari; Canaris, John; Miles, Lowell; Whitaker, Sterling

1992-01-01

Two Reed Solomon error correcting encoders are presented. Schematic driven layout tools were used to create the encoder layouts. Special consideration had to be given to the architecture and logic to provide scalability of the encoder designs. Knowledge gained from these projects was used to create a more flexible schematic driven layout system.

Seating Considerations for Spaceflight: The Human to Machine Interface

NASA Technical Reports Server (NTRS)

Gohmert, Dustin M.

2011-01-01

Seating is one of the most critical components to be considered during design of a spacecraft. Since seats are the final interface between the occupant and the vehicle wherein all launch and landing operations are performed, significant effort must be spent to ensure proper integration of the human to the spacecraft. The importance of seating can be divided into two categories: seat layout and seat design. The layout of the seats drives the overall cabin configuration - from displays and controls, to windows, to stowage, to egress paths. Since the layout of the seats is such a critical design parameter within the crew compartment, it is one of the first design challenges that must be completed in the critical path of the spacecraft design. In consideration of seat layout in the vehicle, it is important for the designers to account for often intangible factors such as safety, operability, contingency performance, crew rescue. Seat layout will lead to definition of the quantity, shape, and posture of the seats. The seats of the craft must restrain and protect the occupant in all seated phases of flight, while allowing for nominal mission performance. In design of a spacecraft seat, the general posture of the occupant and the landing loads to be encountered are the greatest drivers of overall design. Variances, such as upright versus recumbent postures will dictate fit of the seat to the occupant and drive the total envelope of the seat around the occupant. Seat design revolves around applying sound principles of seated occupant protection coupled with the unique environments driven by the seat layout, landing loads, and operational and emergency scenarios.

tkLayout: a design tool for innovative silicon tracking detectors

NASA Astrophysics Data System (ADS)

Bianchi, G.

2014-03-01

A new CMS tracker is scheduled to become operational for the LHC Phase 2 upgrade in the early 2020's. tkLayout is a software package developed to create 3d models for the design of the CMS tracker and to evaluate its fundamental performance figures. The new tracker will have to cope with much higher luminosity conditions, resulting in increased track density, harsher radiation exposure and, especially, much higher data acquisition bandwidth, such that equipping the tracker with triggering capabilities is envisaged. The design of an innovative detector involves deciding on an architecture offering the best trade-off among many figures of merit, such as tracking resolution, power dissipation, bandwidth, cost and so on. Quantitatively evaluating these figures of merit as early as possible in the design phase is of capital importance and it is best done with the aid of software models. tkLayout is a flexible modeling tool: new performance estimates and support for different detector geometries can be quickly added, thanks to its modular structure. Besides, the software executes very quickly (about two minutes), so that many possible architectural variations can be rapidly modeled and compared, to help in the choice of a viable detector layout and then to optimize it. A tracker geometry is generated from simple configuration files, defining the module types, layout and materials. Support structures are automatically added and services routed to provide a realistic tracker description. The tracker geometries thus generated can be exported to the standard CMS simulation framework (CMSSW) for full Monte Carlo studies. tkLayout has proven essential in giving guidance to CMS in studying different detector layouts and exploring the feasibility of innovative solutions for tracking detectors, in terms of design, performance and projected costs. This tool has been one of the keys to making important design decisions for over five years now and has also enabled project engineers and simulation experts to focus their efforts on other important or specific issues. Even if tkLayout was designed for the CMS tracker upgrade project, its flexibility makes it experiment-agnostic, so that it could be easily adapted to model other tracking detectors. The technology behind tkLayout is presented, as well as some of the results obtained in the context of the CMS silicon tracker design studies.

VLSI (Very Large Scale Integrated) Design of a 16 Bit Very Fast Pipelined Carry Look Ahead Adder.

DTIC Science & Technology

1983-09-01

the ability for systems engineers to custom design digital integrated circuits. Until recently, the design of integrated circuits has been...traditionally carried out by a select group of logic designers working in semiconductor laboratories. Systems engineers had to "make do" or "fit in" the...products of these labs to realize their designs. The systems engineers had little participation in the actual design of the chip. The MED and CONWAY design

Describing litho-constrained layout by a high-resolution model filter

NASA Astrophysics Data System (ADS)

Tsai, Min-Chun

2008-05-01

A novel high-resolution model (HRM) filtering technique was proposed to describe litho-constrained layouts. Litho-constrained layouts are layouts that have difficulties to pattern or are highly sensitive to process-fluctuations under current lithography technologies. HRM applies a short-wavelength (or high NA) model simulation directly on the pre-OPC, original design layout to filter out low spatial-frequency regions, and retain high spatial-frequency components which are litho-constrained. Since no OPC neither mask-synthesis steps are involved, this new technique is highly efficient in run time and can be used in design stage to detect and fix litho-constrained patterns. This method has successfully captured all the hot-spots with less than 15% overshoots on a realistic 80 mm2 full-chip M1 layout in 65nm technology node. A step by step derivation of this HRM technique is presented in this paper.

VLSI realization of learning vector quantization with hardware/software co-design for different applications

NASA Astrophysics Data System (ADS)

An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

2015-04-01

This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

Packaging of ferroelectric liquid crystal-on-silicon spatial light modulators

NASA Astrophysics Data System (ADS)

Lin, W.; Morozova, Nina D.; Ju, TehHua; Zhang, Weidong; Lee, Yung-Cheng; McKnight, Douglas J.; Johnson, Kristina M.

1996-11-01

A self-pulling soldering technology has been demonstrated for assembling liquid crystal on silicon (LCOS) spatial light modulators (SLMs). One of the major challenges in manufacturing the LCOS modules is to reproducibly control the thickness of the gap between the very large scale integrated circuit (VLSI) chip and the cover glass. The liquid crystal material is sandwiched between the VLSI chop and the cover glass which is coated with a transparent conductor. Solder joints with different profiles and sizes have been designed to provide surface tension forces to control the gap accommodating the ferroelectric liquid crystal layer in the range of a micron level with sub- micron uniformity. The optimum solder joint design is defined as a joint that results in the maximum pulling force. This technology provides an automatic, batch assembly process for a LCOS SLM through one reflow process. Fluxless soldering technology is used to assemble the module. This approach avoids residues from chemical of flux and oxides, and eliminates potential contamination to the device. Two different LCOS SLM designs and the process optimization are described.

Schematic driven silicon photonics design

NASA Astrophysics Data System (ADS)

Chrostowski, Lukas; Lu, Zeqin; Flückiger, Jonas; Pond, James; Klein, Jackson; Wang, Xu; Li, Sarah; Tai, Wei; Hsu, En Yao; Kim, Chan; Ferguson, John; Cone, Chris

2016-03-01

Electronic circuit designers commonly start their design process with a schematic, namely an abstract representation of the physical circuit. In integrated photonics on the other hand, it is very common for the design to begin at the physical component level. In order to build large integrated photonic systems, it is crucial to design using a schematic-driven approach. This includes simulations based on schematics, schematic-driven layout, layout versus schematic verification, and post-layout simulations. This paper describes such a design framework implemented using Mentor Graphics and Lumerical Solutions design tools. In addition, we describe challenges in silicon photonics related to manufacturing, and how these can be taken into account in simulations and how these impact circuit performance.

EUVL back-insertion layout optimization

NASA Astrophysics Data System (ADS)

Civay, D.; Laffosse, E.; Chesneau, A.

2018-03-01

Extreme ultraviolet lithography (EUVL) is targeted for front-up insertion at advanced technology nodes but will be evaluated for back insertion at more mature nodes. EUVL can put two or more mask levels back on one mask, depending upon what level(s) in the process insertion occurs. In this paper, layout optimization methods are discussed that can be implemented when EUVL back insertion is implemented. The layout optimizations can be focused on improving yield, reliability or density, depending upon the design needs. The proposed methodology modifies the original two or more colored layers and generates an optimized single color EUVL layout design.

41 CFR 102-85.35 - What definitions apply to this part?

Code of Federal Regulations, 2010 CFR

2010-07-01

... professional techniques of planning, layout and interior design to determine the best internal location and the..., due to its layout, design, location, or other characteristics, is unlikely to be needed by another GSA... space means surface land, structures, or areas within structures designed and designated for the purpose...

Design & layout of recreation facilities

Treesearch

Howard R. Orr

1971-01-01

Design and layout of recreation facilities is a problem solving process that must be divorced from the emotionalism that has shrouded outdoor recreation and must deal deliberately with the growing information concerning people and natural resources.

Applications to car bodies - Generalized layout design of three-dimensional shells

NASA Technical Reports Server (NTRS)

Fukushima, Junichi; Suzuki, Katsuyuki; Kikuchi, Noboru

1993-01-01

We shall describe applications of the homogenization method, formulated in Part 1, to design layout of car bodies represented by three-dimensional shell structures based on a multi-loading optimization.

Seating Considerations for Spaceflight: The Human to Machine Interface

NASA Astrophysics Data System (ADS)

Gohmert, D. M.

2012-01-01

Seating is one of the most critical components to be considered during design of a spacecraft. Since seats are the final interface between the occupant and the vehicle wherein all launch and landing operations are performed, significant effort must be spent to ensure proper integration of the human to the spacecraft. The importance of seating can be divided into two categories: seat layout and seat design. The layout of the seats drives the overall cabin configuration - from displays and controls, to windows, to stowage, to egress paths. Since the layout of the seats is such a critical design parameter within the crew compartment, it is one of the first design challenges that must be completed in the critical path of the spacecraft design. In consideration of seat layout in the vehicle, it is important for the designers to account for often intangible factors such as safety, operability, contingency performance, and crew rescue. Seat layout will lead to definition of the quantity, shape, and posture of the seats. The seats of the craft must restrain and protect the occupant in all seated phases of flight, while allowing for nominal mission performance. In design of a spacecraft seat, the general posture of the occupant and the landing loads to be encountered are the greatest drivers of overall design. Variances, such as upright versus recumbent postures will dictate fit of the seat to the occupant and drive the total envelope of the seat around the occupant. Seat design revolves around applying sound principles of seated occupant protection coupled with the unique environments driven by the seat layout, landing loads, and operational and emergency scenarios.

Defense Acquisitions Acronyms and Terms

DTIC Science & Technology

2012-12-01

Computer-Aided Design CADD Computer-Aided Design and Drafting CAE Component Acquisition Executive; Computer-Aided Engineering CAIV Cost As an...Radiation to Ordnance HFE Human Factors Engineering HHA Health Hazard Assessment HNA Host-Nation Approval HNS Host-Nation Support HOL High -Order...Engineering Change Proposal VHSIC Very High Speed Integrated Circuit VLSI Very Large Scale Integration VOC Volatile Organic Compound W WAN Wide

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

DTIC Science & Technology

2007-03-31

IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

Image processing via VLSI: A concept paper

NASA Technical Reports Server (NTRS)

Nathan, R.

1982-01-01

Implementing specific image processing algorithms via very large scale integrated systems offers a potent solution to the problem of handling high data rates. Two algorithms stand out as being particularly critical -- geometric map transformation and filtering or correlation. These two functions form the basis for data calibration, registration and mosaicking. VLSI presents itself as an inexpensive ancillary function to be added to almost any general purpose computer and if the geometry and filter algorithms are implemented in VLSI, the processing rate bottleneck would be significantly relieved. A set of image processing functions that limit present systems to deal with future throughput needs, translates these functions to algorithms, implements via VLSI technology and interfaces the hardware to a general purpose digital computer is developed.

Hardware Algorithm Implementation for Mission Specific Processing

DTIC Science & Technology

2008-03-01

knowledge about the VLSI technology and understands VHDL, scripting, and intergrating the script in Cadencersoftware pro- gram or Modelsimr. The main...possible to have a trade off between parallel and serial logic design for the circuit. Power can be saved by using parallization, pipelining, or a

The Xpress Transfer Protocol (XTP): A tutorial (expanded version)

NASA Technical Reports Server (NTRS)

Sanders, Robert M.; Weaver, Alfred C.

1990-01-01

The Xpress Transfer Protocol (XTP) is a reliable, real-time, light weight transfer layer protocol. Current transport layer protocols such as DoD's Transmission Control Protocol (TCP) and ISO's Transport Protocol (TP) were not designed for the next generation of high speed, interconnected reliable networks such as fiber distributed data interface (FDDI) and the gigabit/second wide area networks. Unlike all previous transport layer protocols, XTP is being designed to be implemented in hardware as a VLSI chip set. By streamlining the protocol, combining the transport and network layers and utilizing the increased speed and parallelization possible with a VLSI implementation, XTP will be able to provide the end-to-end data transmission rates demanded in high speed networks without compromising reliability and functionality. This paper describes the operation of the XTP protocol and in particular, its error, flow and rate control; inter-networking addressing mechanisms; and multicast support features, as defined in the XTP Protocol Definition Revision 3.4.

Bio-Inspired Microsystem for Robust Genetic Assay Recognition

PubMed Central

Lue, Jaw-Chyng; Fang, Wai-Chi

2008-01-01

A compact integrated system-on-chip (SoC) architecture solution for robust, real-time, and on-site genetic analysis has been proposed. This microsystem solution is noise-tolerable and suitable for analyzing the weak fluorescence patterns from a PCR prepared dual-labeled DNA microchip assay. In the architecture, a preceding VLSI differential logarithm microchip is designed for effectively computing the logarithm of the normalized input fluorescence signals. A posterior VLSI artificial neural network (ANN) processor chip is used for analyzing the processed signals from the differential logarithm stage. A single-channel logarithmic circuit was fabricated and characterized. A prototype ANN chip with unsupervised winner-take-all (WTA) function was designed, fabricated, and tested. An ANN learning algorithm using a novel sigmoid-logarithmic transfer function based on the supervised backpropagation (BP) algorithm is proposed for robustly recognizing low-intensity patterns. Our results show that the trained new ANN can recognize low-fluorescence patterns better than an ANN using the conventional sigmoid function. PMID:18566679

A grid layout algorithm for automatic drawing of biochemical networks.

PubMed

Li, Weijiang; Kurata, Hiroyuki

2005-05-01

Visualization is indispensable in the research of complex biochemical networks. Available graph layout algorithms are not adequate for satisfactorily drawing such networks. New methods are required to visualize automatically the topological architectures and facilitate the understanding of the functions of the networks. We propose a novel layout algorithm to draw complex biochemical networks. A network is modeled as a system of interacting nodes on squared grids. A discrete cost function between each node pair is designed based on the topological relation and the geometric positions of the two nodes. The layouts are produced by minimizing the total cost. We design a fast algorithm to minimize the discrete cost function, by which candidate layouts can be produced efficiently. A simulated annealing procedure is used to choose better candidates. Our algorithm demonstrates its ability to exhibit cluster structures clearly in relatively compact layout areas without any prior knowledge. We developed Windows software to implement the algorithm for CADLIVE. All materials can be freely downloaded from http://kurata21.bio.kyutech.ac.jp/grid/grid_layout.htm; http://www.cadlive.jp/ http://kurata21.bio.kyutech.ac.jp/grid/grid_layout.htm; http://www.cadlive.jp/

Lithography-induced limits to scaling of design quality

NASA Astrophysics Data System (ADS)

Kahng, Andrew B.

2014-03-01

Quality and value of an IC product are functions of power, performance, area, cost and reliability. The forthcoming 2013 ITRS roadmap observes that while manufacturers continue to enable potential Moore's Law scaling of layout densities, the "realizable" scaling in competitive products has for some years been significantly less. In this paper, we consider aspects of the question, "To what extent should this scaling gap be blamed on lithography?" Non-ideal scaling of layout densities has been attributed to (i) layout restrictions associated with multi-patterning technologies (SADP, LELE, LELELE), as well as (ii) various ground rule and layout style choices that stem from misalignment, reliability, variability, device architecture, and electrical performance vs. power constraints. Certain impacts seem obvious, e.g., loss of 2D flexibility and new line-end placement constraints with SADP, or algorithmically intractable layout stitching and mask coloring formulations with LELELE. However, these impacts may well be outweighed by weaknesses in design methodology and tooling. Arguably, the industry has entered a new era in which many new factors - (i) standard-cell library architecture, and layout guardbanding for automated place-and-route: (ii) performance model guardbanding and signoff analyses: (iii) physical design and manufacturing handoff algorithms spanning detailed placement and routing, stitching and RET; and (iv) reliability guardbanding - all contribute, hand in hand with lithography, to a newly-identified "design capability gap". How specific aspects of process and design enablements limit the scaling of design quality is a fundamental question whose answer must guide future RandD investment at the design-manufacturing interface. terface.

An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

NASA Astrophysics Data System (ADS)

Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

2016-09-01

The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

77 FR 64521 - Announcement of Requirements and Registration for “Health Design Challenge”

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-22

... it with visuals and a better layout. Innovators will be invited to submit their best designs for a... a sample CCD. Challenge entrants will submit a design that: [ssquf] Improves the visual layout and... Design Challenge'' AGENCY: Office of the National Coordinator for Health Information Technology, HHS...

VLSI chips for vision-based vehicle guidance

NASA Astrophysics Data System (ADS)

Masaki, Ichiro

1994-02-01

Sensor-based vehicle guidance systems are gathering rapidly increasing interest because of their potential for increasing safety, convenience, environmental friendliness, and traffic efficiency. Examples of applications include intelligent cruise control, lane following, collision warning, and collision avoidance. This paper reviews the research trends in vision-based vehicle guidance with an emphasis on VLSI chip implementations of the vision systems. As an example of VLSI chips for vision-based vehicle guidance, a stereo vision system is described in detail.

VLSI Implementation of Neuromorphic Learning Networks

DTIC Science & Technology

1993-03-31

AND DATES COVEREDFINAL/O1 AUG 90 TO 31 MAR 93 4. TITLE AND SUBTII1L S. FUNDING NUMBERS VLSI IMPLEMENTATION OF NEUROMORPHIC LEARNING NETWORKS (U) 6...Standard Form 298 (Rev 2-89) rtrfbc byv nN$I A Z’Si - 8 9- A* qip. COVER SHEET VLSI Implementation of Neuromorphic Learning Networks Contract Number... Neuromorphic Learning Networks Sponsored by Defense Advanced Research Projects Agency DARPA Order No. 7013 Monitored by AFOSR Under Contract No. F49620-90-C

Camera Layout Design for the Upper Stage Thrust Cone

NASA Technical Reports Server (NTRS)

Wooten, Tevin; Fowler, Bart

2010-01-01

Engineers in the Integrated Design and Analysis Division (EV30) use a variety of different tools to aid in the design and analysis of the Ares I vehicle. One primary tool in use is Pro-Engineer. Pro-Engineer is a computer-aided design (CAD) software that allows designers to create computer generated structural models of vehicle structures. For the Upper State thrust cone, Pro-Engineer was used to assist in the design of a layout for two camera housings. These cameras observe the separation between the first and second stage of the Ares I vehicle. For the Ares I-X, one standard speed camera was used. The Ares I design calls for two separate housings, three cameras, and a lighting system. With previous design concepts and verification strategies in mind, a new layout for the two camera design concept was developed with members of the EV32 team. With the new design, Pro-Engineer was used to draw the layout to observe how the two camera housings fit with the thrust cone assembly. Future analysis of the camera housing design will verify the stability and clearance of the camera with other hardware present on the thrust cone.

Electro-optic techniques for VLSI interconnect

NASA Astrophysics Data System (ADS)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

Ergonomics and simulation-based approach in improving facility layout

NASA Astrophysics Data System (ADS)

Abad, Jocelyn D.

2018-02-01

The use of the simulation-based technique in facility layout has been a choice in the industry due to its convenience and efficient generation of results. Nevertheless, the solutions generated are not capable of addressing delays due to worker's health and safety which significantly impact overall operational efficiency. It is, therefore, critical to incorporate ergonomics in facility design. In this study, workstation analysis was incorporated into Promodel simulation to improve the facility layout of a garment manufacturing. To test the effectiveness of the method, existing and improved facility designs were measured using comprehensive risk level, efficiency, and productivity. Results indicated that the improved facility layout generated a decrease in comprehensive risk level and rapid upper limb assessment score; an increase of 78% in efficiency and 194% increase in productivity compared to existing design and thus proved that the approach is effective in attaining overall facility design improvement.

Development of a Prediction Model Based on RBF Neural Network for Sheet Metal Fixture Locating Layout Design and Optimization.

PubMed

Wang, Zhongqi; Yang, Bo; Kang, Yonggang; Yang, Yuan

2016-01-01

Fixture plays an important part in constraining excessive sheet metal part deformation at machining, assembly, and measuring stages during the whole manufacturing process. However, it is still a difficult and nontrivial task to design and optimize sheet metal fixture locating layout at present because there is always no direct and explicit expression describing sheet metal fixture locating layout and responding deformation. To that end, an RBF neural network prediction model is proposed in this paper to assist design and optimization of sheet metal fixture locating layout. The RBF neural network model is constructed by training data set selected by uniform sampling and finite element simulation analysis. Finally, a case study is conducted to verify the proposed method.

Development of a Prediction Model Based on RBF Neural Network for Sheet Metal Fixture Locating Layout Design and Optimization

PubMed Central

Wang, Zhongqi; Yang, Bo; Kang, Yonggang; Yang, Yuan

2016-01-01

Fixture plays an important part in constraining excessive sheet metal part deformation at machining, assembly, and measuring stages during the whole manufacturing process. However, it is still a difficult and nontrivial task to design and optimize sheet metal fixture locating layout at present because there is always no direct and explicit expression describing sheet metal fixture locating layout and responding deformation. To that end, an RBF neural network prediction model is proposed in this paper to assist design and optimization of sheet metal fixture locating layout. The RBF neural network model is constructed by training data set selected by uniform sampling and finite element simulation analysis. Finally, a case study is conducted to verify the proposed method. PMID:27127499

Screen Layout Design: Research into the Overall Appearance of the Screen.

ERIC Educational Resources Information Center

Grabinger, R. Scott

1989-01-01

Examines the current state of research into the visual effects of screen designs used in computer-assisted instruction and suggests areas for future efforts. Topics discussed include technical elements and comprehensibility elements in layout design; single element and multiple element research methodologies; dependent variables; and learning…

76 FR 15001 - Entergy Nuclear Operations, Inc,. Entergy Nuclear Vermont Yankee, LLC, Vermont Yankee Nuclear...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-03-18

... understand VY's design, layout, and construction. This failure to comprehend and understand the layout... Facilities,'' and General Design Criteria 60, ``Control of Releases of Radioactive Materials to the Environment,'' and 64, ``Monitoring Radioactivity Releases,'' of Appendix A, ``General Design Criteria for...

HOLA: Human-like Orthogonal Network Layout.

PubMed

Kieffer, Steve; Dwyer, Tim; Marriott, Kim; Wybrow, Michael

2016-01-01

Over the last 50 years a wide variety of automatic network layout algorithms have been developed. Some are fast heuristic techniques suitable for networks with hundreds of thousands of nodes while others are multi-stage frameworks for higher-quality layout of smaller networks. However, despite decades of research currently no algorithm produces layout of comparable quality to that of a human. We give a new "human-centred" methodology for automatic network layout algorithm design that is intended to overcome this deficiency. User studies are first used to identify the aesthetic criteria algorithms should encode, then an algorithm is developed that is informed by these criteria and finally, a follow-up study evaluates the algorithm output. We have used this new methodology to develop an automatic orthogonal network layout method, HOLA, that achieves measurably better (by user study) layout than the best available orthogonal layout algorithm and which produces layouts of comparable quality to those produced by hand.

A comparative study on stress and compliance based structural topology optimization

NASA Astrophysics Data System (ADS)

Hailu Shimels, G.; Dereje Engida, W.; Fakhruldin Mohd, H.

2017-10-01

Most of structural topology optimization problems have been formulated and solved to either minimize compliance or weight of a structure under volume or stress constraints, respectively. Even if, a lot of researches are conducted on these two formulation techniques separately, there is no clear comparative study between the two approaches. This paper intends to compare these formulation techniques, so that an end user or designer can choose the best one based on the problems they have. Benchmark problems under the same boundary and loading conditions are defined, solved and results are compared based on these formulations. Simulation results shows that the two formulation techniques are dependent on the type of loading and boundary conditions defined. Maximum stress induced in the design domain is higher when the design domains are formulated using compliance based formulations. Optimal layouts from compliance minimization formulation has complex layout than stress based ones which may lead the manufacturing of the optimal layouts to be challenging. Optimal layouts from compliance based formulations are dependent on the material to be distributed. On the other hand, optimal layouts from stress based formulation are dependent on the type of material used to define the design domain. High computational time for stress based topology optimization is still a challenge because of the definition of stress constraints at element level. Results also shows that adjustment of convergence criterions can be an alternative solution to minimize the maximum stress developed in optimal layouts. Therefore, a designer or end user should choose a method of formulation based on the design domain defined and boundary conditions considered.

Lithography-based automation in the design of program defect masks

NASA Astrophysics Data System (ADS)

Vakanas, George P.; Munir, Saghir; Tejnil, Edita; Bald, Daniel J.; Nagpal, Rajesh

2004-05-01

In this work, we are reporting on a lithography-based methodology and automation in the design of Program Defect masks (PDM"s). Leading edge technology masks have ever-shrinking primary features and more pronounced model-based secondary features such as optical proximity corrections (OPC), sub-resolution assist features (SRAF"s) and phase-shifted mask (PSM) structures. In order to define defect disposition specifications for critical layers of a technology node, experience alone in deciding worst-case scenarios for the placement of program defects is necessary but may not be sufficient. MEEF calculations initiated from layout pattern data and their integration in a PDM layout flow provide a natural approach for improvements, relevance and accuracy in the placement of programmed defects. This methodology provides closed-loop feedback between layout and hard defect disposition specifications, thereby minimizing engineering test restarts, improving quality and reducing cost of high-end masks. Apart from SEMI and industry standards, best-known methods (BKM"s) in integrated lithographically-based layout methodologies and automation specific to PDM"s are scarce. The contribution of this paper lies in the implementation of Design-For-Test (DFT) principles to a synergistic interaction of CAD Layout and Aerial Image Simulator to drive layout improvements, highlight layout-to-fracture interactions and output accurate program defect placement coordinates to be used by tools in the mask shop.

Research in VLSI Systems. Heuristic Programming Project and VLSI Theory Project. A Fast Turn Around Facility for Very Large Scale Integration (VLSI)

DTIC Science & Technology

1982-11-01

to occur). When a rectangle is inserted, all currently selected items are de -selected, and the newly inserted rectangle is selected. This makes it...Items are de - * selected before the selection takes place. A selected symbol instance is displayed with a bold outline, and a selected rectangle edge...symbol instance or set of rectangle edges, everything previously selected is first de -selected. If the selected object is a reference point the old

Recursive computer architecture for VLSI

DOE Office of Scientific and Technical Information (OSTI.GOV)

Treleaven, P.C.; Hopkins, R.P.

1982-01-01

A general-purpose computer architecture based on the concept of recursion and suitable for VLSI computer systems built from replicated (lego-like) computing elements is presented. The recursive computer architecture is defined by presenting a program organisation, a machine organisation and an experimental machine implementation oriented to VLSI. The experimental implementation is being restricted to simple, identical microcomputers each containing a memory, a processor and a communications capability. This future generation of lego-like computer systems are termed fifth generation computers by the Japanese. 30 references.

Mechanical Design of High Lift Systems for High Aspect Ratio Swept Wings

NASA Technical Reports Server (NTRS)

Rudolph, Peter K. C.

1998-01-01

The NASA Ames Research Center is working to develop a methodology for the optimization and design of the high lift system for future subsonic airliners with the involvement of two partners. Aerodynamic analysis methods for two dimensional and three dimensional wing performance with flaps and slats deployed are being developed through a grant with the aeronautical department of the University of California Davis, and a flap and slat mechanism design procedure is being developed through a contract with PKCR, Inc., of Seattle, WA. This report documents the work that has been completed in the contract with PKCR on mechanism design. Flap mechanism designs have been completed for seven (7) different mechanisms with a total of twelve (12) different layouts all for a common single slotted flap configuration. The seven mechanisms are as follows: Simple Hinge, Upside Down/Upright Four Bar Linkage (two layouts), Upside Down Four Bar Linkages (three versions), Airbus A330/340 Link/Track Mechanism, Airbus A320 Link/Track Mechanism (two layouts), Boeing Link/Track Mechanism (two layouts), and Boeing 767 Hinged Beam Four Bar Linkage. In addition, a single layout has been made to investigate the growth potential from a single slotted flap to a vane/main double slotted flap using the Boeing Link/Track Mechanism. All layouts show Fowler motion and gap progression of the flap from stowed to a fully deployed position, and evaluations based on spanwise continuity, fairing size and number, complexity, reliability and maintainability and weight as well as Fowler motion and gap progression are presented. For slat design, the options have been limited to mechanisms for a shallow leading edge slat. Three (3) different layouts are presented for maximum slat angles of 20 deg, 15 deg and 1O deg all mechanized with a rack and pinion drive similar to that on the Boeing 757 airplane. Based on the work of Ljungstroem in Sweden, this type of slat design appears to shift the lift curve so that higher lift is achieved with the deployed slat with no increase in angle of attack. The layouts demonstrate that these slat systems can be designed with no need for slave links, and an experimental test program is outlined to experimentally validate the lift characteristics of the shallow slat.

Laser Microchemistry : A Powerful Tool For VLSI

NASA Astrophysics Data System (ADS)

Tonneau, Didier; Guern, Yves; Pelous, Gerard

1989-01-01

Interconnection direct writing on ICs is possible by localized laser-assisted Chemical Vapor Deposition. Recently we have developed and marketed a new laser microchemistry tool particularly designed for VLSI prototypes rewiring. By dissociating Ni(CO)4 molecules, Ni lines can be written at speeds higher than 5 gm/s under laser induced temperature as low as 400°C. At the same temperature tungsten stripes can be driven from decomposition of WF6-H2 mixtures. However the tungsten deposition rate is about two orders of magnitude lower than the nickel growth rate in the same temperature conditions. The resistivities of the deposits are in both cases around 10 μΩ.cm. Silicon dioxide layers can be promoted from dissociation of a Si2H6-N20 mixture under surface temperature around 500°C. These metal and insulator deposition basic steps have been integrated in a complete metal bridging process suitable for the last interconnection level of a VLSI circuit. This process has been firstly estimated from a functional point of view, by electrical characterizations realized on test patterns entirely drawn by laser chemistry. At least, by measuring the time necessary to perform a metal bridge, the process has been evaluated from an economical point of view.

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

The Hermod Behavioral Synthesis System

DTIC Science & Technology

1988-06-08

LDescription 1 lib tech-independent Transformation & Parser Optimization lib Hardware • g - utSynhesze Generator li Datapath lb Hardware liCotllb...Proc. 22nd Design Automation Conference, ACM/IEEE, June 1985, pp. 475-481. [7] G . De Micheli, "Synthesis of Control Systems", in Design Systems for...VLSI Circuits: Logic Synthesis and Silicon Compilation, G . De Micheli, A. Sangiovanni-Vincentelli, and P. Antognetti, (editor), Martinus Nijhoff

Laser Direct Routing for High Density Interconnects

NASA Astrophysics Data System (ADS)

Moreno, Wilfrido Alejandro

The laser restructuring of electronic circuits fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative that allows low-cost quick turnaround production with full circuit similarity between the Laser Restructured prototype and the customized product for mass production. Laser Restructurable VLSI (LRVLSI) would allow design engineers the capability to interconnect cells that implement generic logic functions and signal processing schemes to achieve a higher level of design complexity. LRVLSI of a particular circuit at the wafer or packaged chip level is accomplished using an integrated computer controlled laser system to create low electrical resistance links between conductors and to cut conductor lines. An infrastructure for rapid prototyping and quick turnaround using Laser Restructuring of VLSI circuits was developed to meet three main parallel objectives: to pursue research on novel interconnect technologies using LRVLSI, to develop the capability of operating in a quick turnaround mode, and to maintain standardization and compatibility with commercially available equipment for feasible technology transfer. The system is to possess a high degree of flexibility, high data quality, total controllability, full documentation, short downtime, a user-friendly operator interface, automation, historical record keeping, and error indication and logging. A specially designed chip "SLINKY" was used as the test vehicle for the complete characterization of the Laser Restructuring system. With the use of Design of Experiment techniques the Lateral Diffused Link (LDL), developed originally at MIT Lincoln Laboratories, was completely characterized and for the first time a set of optimum process parameters was obtained. With the designed infrastructure fully operational, the priority objective was the search for a substitute for the high resistance, high current leakage to substrate, and relatively low density Lateral Diffused Link. A high density Laser Vertical Link with resistance values below 10 ohms was developed, studied and tested using design of experiment methodologies. The vertical link offers excellent advantages in the area of quick prototyping of electronic circuits, but even more important, due to having similar characteristics to a foundry produced via, it gives quick transfer from the prototype system verification stage to the mass production stage.

Optical Layout Analysis of Polarization Interference Imaging Spectrometer by Jones Calculus in View of both Optical Throughput and Interference Fringe Visibility

NASA Astrophysics Data System (ADS)

Zhang, Xuanni; Zhang, Chunmin

2013-01-01

A polarization interference imaging spectrometer based on Savart polariscope was presented. Its optical throughput was analyzed by Jones calculus. The throughput expression was given, and clearly showed that the optical throughput mainly depended on the intensity of incident light, transmissivity, refractive index and the layout of optical system. The simulation and analysis gave the optimum layout in view of both optical throughput and interference fringe visibility, and verified that the layout of our former design was optimum. The simulation showed that a small deviation from the optimum layout influenced interference fringe visibility little for the optimum one, but influenced severely for others, so a small deviation is admissible in the optimum, and this can mitigate the manufacture difficulty. These results pave the way for further research and engineering design.

Design optimization of highly asymmetrical layouts by 2D contour metrology

NASA Astrophysics Data System (ADS)

Hu, C. M.; Lo, Fred; Yang, Elvis; Yang, T. H.; Chen, K. C.

2018-03-01

As design pitch shrinks to the resolution limit of up-to-date optical lithography technology, the Critical Dimension (CD) variation tolerance has been dramatically decreased for ensuring the functionality of device. One of critical challenges associates with the narrower CD tolerance for whole chip area is the proximity effect control on asymmetrical layout environments. To fulfill the tight CD control of complex features, the Critical Dimension Scanning Electron Microscope (CD-SEM) based measurement results for qualifying process window and establishing the Optical Proximity Correction (OPC) model become insufficient, thus 2D contour extraction technique [1-5] has been an increasingly important approach for complementing the insufficiencies of traditional CD measurement algorithm. To alleviate the long cycle time and high cost penalties for product verification, manufacturing requirements are better to be well handled at design stage to improve the quality and yield of ICs. In this work, in-house 2D contour extraction platform was established for layout design optimization of 39nm half-pitch Self-Aligned Double Patterning (SADP) process layer. Combining with the adoption of Process Variation Band Index (PVBI), the contour extraction platform enables layout optimization speedup as comparing to traditional methods. The capabilities of identifying and handling lithography hotspots in complex layout environments of 2D contour extraction platform allow process window aware layout optimization to meet the manufacturing requirements.

VLSI Design Techniques for Floating-Point Computation

DTIC Science & Technology

1988-11-18

J. C. Gibson, The Gibson Mix, IBM Systems Development Division Tech. Report(June 1970). [Heni83] A. Heninger, The Zilog Z8070 Floating-Point...Broadcast Oock Gen. ’ itp Divide Module Module byN Module Oock Communication l I T Oock Communication Bus Figure 7.2. Clock Distribution between

A Coherent VLSI Design Environment.

DTIC Science & Technology

1985-09-30

deviation were only a few percent. If the number of paths with a delay close to 9ns were large, even more statistical accuracy would be required to...Zippel, 1Capsules, IGPLAN Bulletn, vol. 18, no. 6, waveforms. In the bottom window, the currents into the pp. 164-169, 1983. depletion transitors are

A Fast Turn-Around Facility for Very Large Scale Integration (VLSI)

DTIC Science & Technology

1982-06-01

statistics determination, the first test mask set will use the MATRIX chip design which was recently developed here at Stanford. This chip provides...reached when the basewidth is reduced to zero. Such devices, variably known as depleted- base transistors or bipolar static-induction transitors , have been

Computer Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices

DTIC Science & Technology

1980-01-01

diffusion coefficient and surface conc,,tration of the chlorine as well as any field present; X is related to the ratio ol the diffusion coefficient to...with polysilicon gat(. .ed contacts, the interaction of oxidation, segregation and diffusion in all regions of the simulation space is a critical

32 CFR Appendix B to Part 247 - CE Publications

Code of Federal Regulations, 2012 CFR

2012-07-01

... liaison functions on publisher premises including monitoring and coordinating layout and design and other... coordinate layout and ensure that the preparation of editorial material is performed in such a way as to... commander's representative shall have the authority to specify newspaper advertising layout when required to...

The role of simulation in the design of a neural network chip

NASA Technical Reports Server (NTRS)

Desai, Utpal; Roppel, Thaddeus A.; Padgett, Mary L.

1993-01-01

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

Process Mining-Based Method of Designing and Optimizing the Layouts of Emergency Departments in Hospitals.

PubMed

Rismanchian, Farhood; Lee, Young Hoon

2017-07-01

This article proposes an approach to help designers analyze complex care processes and identify the optimal layout of an emergency department (ED) considering several objectives simultaneously. These objectives include minimizing the distances traveled by patients, maximizing design preferences, and minimizing the relocation costs. Rising demand for healthcare services leads to increasing demand for new hospital buildings as well as renovating existing ones. Operations management techniques have been successfully applied in both manufacturing and service industries to design more efficient layouts. However, high complexity of healthcare processes makes it challenging to apply these techniques in healthcare environments. Process mining techniques were applied to address the problem of complexity and to enhance healthcare process analysis. Process-related information, such as information about the clinical pathways, was extracted from the information system of an ED. A goal programming approach was then employed to find a single layout that would simultaneously satisfy several objectives. The layout identified using the proposed method improved the distances traveled by noncritical and critical patients by 42.2% and 47.6%, respectively, and minimized the relocation costs. This study has shown that an efficient placement of the clinical units yields remarkable improvements in the distances traveled by patients.

Thermal Design, Analysis, and Testing of the Quench Module Insert Bread Board

NASA Technical Reports Server (NTRS)

Breeding, Shawn; Khodabandeh, Julia

2002-01-01

Contents include the following: Quench Module Insert (QMI) science requirements. QMI interfaces. QMI design layout. QMI thermal analysis and design methodology. QMI bread board testing and instrumentation approach. QMI thermal probe design parameters. Design features for gradient measurement. Design features for heated zone measurements. Thermal gradient analysis results. Heated zone analysis results. Bread board thermal probe layout. QMI bread board correlation and performance. Summary and conclusions.

Machine detector interface studies: Layout and synchrotron radiation estimate in the future circular collider interaction region

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boscolo, Manuela; Burkhardt, Helmut; Sullivan, Michael

The interaction region layout for the e +e – future circular collider FCC-ee is presented together with a preliminary estimate of synchrotron radiation that affects this region. We describe in this paper the main guidelines of this design and the estimate of synchrotron radiation coming from the last bending magnets and from the final focus quadrupoles, with the software tools developed for this purpose. Here, the design follows the asymmetric optics layout as far as incoming bend radiation is concerned with the maximum foreseen beam energy of 175 GeV and we present a feasible initial layout with an indication ofmore » tolerable synchrotron radiation.« less

Machine detector interface studies: Layout and synchrotron radiation estimate in the future circular collider interaction region

DOE PAGES

Boscolo, Manuela; Burkhardt, Helmut; Sullivan, Michael

2017-01-27

The interaction region layout for the e +e – future circular collider FCC-ee is presented together with a preliminary estimate of synchrotron radiation that affects this region. We describe in this paper the main guidelines of this design and the estimate of synchrotron radiation coming from the last bending magnets and from the final focus quadrupoles, with the software tools developed for this purpose. Here, the design follows the asymmetric optics layout as far as incoming bend radiation is concerned with the maximum foreseen beam energy of 175 GeV and we present a feasible initial layout with an indication ofmore » tolerable synchrotron radiation.« less

VLSI-based video event triggering for image data compression

NASA Astrophysics Data System (ADS)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Asynchronous transfer mode distribution network by use of an optoelectronic VLSI switching chip.

PubMed

Lentine, A L; Reiley, D J; Novotny, R A; Morrison, R L; Sasian, J M; Beckman, M G; Buchholz, D B; Hinterlong, S J; Cloonan, T J; Richards, G W; McCormick, F B

1997-03-10

We describe a new optoelectronic switching system demonstration that implements part of the distribution fabric for a large asynchronous transfer mode (ATM) switch. The system uses a single optoelectronic VLSI modulator-based switching chip with more than 4000 optical input-outputs. The optical system images the input fibers from a two-dimensional fiber bundle onto this chip. A new optomechanical design allows the system to be mounted in a standard electronic equipment frame. A large section of the switch was operated as a 208-Mbits/s time-multiplexed space switch, which can serve as part of an ATM switch by use of an appropriate out-of-band controller. A larger section with 896 input light beams and 256 output beams was operated at 160 Mbits/s as a slowly reconfigurable space switch.

VLSI-based Video Event Triggering for Image Data Compression

NASA Technical Reports Server (NTRS)

Williams, Glenn L.

1994-01-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Expert-guided evolutionary algorithm for layout design of complex space stations

NASA Astrophysics Data System (ADS)

Qian, Zhiqin; Bi, Zhuming; Cao, Qun; Ju, Weiguo; Teng, Hongfei; Zheng, Yang; Zheng, Siyu

2017-08-01

The layout of a space station should be designed in such a way that different equipment and instruments are placed for the station as a whole to achieve the best overall performance. The station layout design is a typical nondeterministic polynomial problem. In particular, how to manage the design complexity to achieve an acceptable solution within a reasonable timeframe poses a great challenge. In this article, a new evolutionary algorithm has been proposed to meet such a challenge. It is called as the expert-guided evolutionary algorithm with a tree-like structure decomposition (EGEA-TSD). Two innovations in EGEA-TSD are (i) to deal with the design complexity, the entire design space is divided into subspaces with a tree-like structure; it reduces the computation and facilitates experts' involvement in the solving process. (ii) A human-intervention interface is developed to allow experts' involvement in avoiding local optimums and accelerating convergence. To validate the proposed algorithm, the layout design of one-space station is formulated as a multi-disciplinary design problem, the developed algorithm is programmed and executed, and the result is compared with those from other two algorithms; it has illustrated the superior performance of the proposed EGEA-TSD.

Active Optical Zoom for Tracking

DTIC Science & Technology

2008-09-01

optical system. 2. Current Setup Deformable Flat Two Deformable Flat Figure 1. Zemax lens design layout and experimental layout on the...optical bench. Figure 1 is a ZEMAX design and setup on the optical bench of two Deformable Mirrors (DMs) from OKO technologies. These mirrors have

Integrated layout based Monte-Carlo simulation for design arc optimization

NASA Astrophysics Data System (ADS)

Shao, Dongbing; Clevenger, Larry; Zhuang, Lei; Liebmann, Lars; Wong, Robert; Culp, James

2016-03-01

Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

An Engineering Methodology for Implementing and Testing VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-03-01

the pad frame and associated routing, conducted additional testing. and submitted the finished design effort to MOSIS for manufacturing. Throughout...register bank TSTCON Allows the XNOR circuitry to enter the TEST register bank PADIN Test signal to check operation of the input pad VCC Power connection...MOSSIM II simulation program. but the design offered little observability within the circuit. The initial design used 35 pins of a 40 pin pad frame

Modeling human-machine interactions for operations room layouts

NASA Astrophysics Data System (ADS)

Hendy, Keith C.; Edwards, Jack L.; Beevis, David

2000-11-01

The LOCATE layout analysis tool was used to analyze three preliminary configurations for the Integrated Command Environment (ICE) of a future USN platform. LOCATE develops a cost function reflecting the quality of all human-human and human-machine communications within a workspace. This proof- of-concept study showed little difference between the efficacy of the preliminary designs selected for comparison. This was thought to be due to the limitations of the study, which included the assumption of similar size for each layout and a lack of accurate measurement data for various objects in the designs, due largely to their notional nature. Based on these results, the USN offered an opportunity to conduct a LOCATE analysis using more appropriate assumptions. A standard crew was assumed, and subject matter experts agreed on the communications patterns for the analysis. Eight layouts were evaluated with the concepts of coordination and command factored into the analysis. Clear differences between the layouts emerged. The most promising design was refined further by the USN, and a working mock-up built for human-in-the-loop evaluation. LOCATE was applied to this configuration for comparison with the earlier analyses.

A parallel VLSI architecture for a digital filter using a number theoretic transform

NASA Technical Reports Server (NTRS)

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1983-01-01

The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

Simplified microprocessor design for VLSI control applications

NASA Technical Reports Server (NTRS)

Cameron, K.

1991-01-01

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

Variability-aware double-patterning layout optimization for analog circuits

NASA Astrophysics Data System (ADS)

Li, Yongfu; Perez, Valerio; Tripathi, Vikas; Lee, Zhao Chuan; Tseng, I.-Lun; Ong, Jonathan Yoong Seang

2018-03-01

The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit's mismatch. To overcome the problem and improve the turn-around time, we proposed our smart "anchoring" placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.

The impact of visual layout factors on performance in Web pages: a cross-language study.

PubMed

Parush, Avi; Shwarts, Yonit; Shtub, Avy; Chandra, M Jeya

2005-01-01

Visual layout has a strong impact on performance and is a critical factor in the design of graphical user interfaces (GUIs) and Web pages. Many design guidelines employed in Web page design were inherited from human performance literature and GUI design studies and practices. However, few studies have investigated the more specific patterns of performance with Web pages that may reflect some differences between Web page and GUI design. We investigated interactions among four visual layout factors in Web page design (quantity of links, alignment, grouping indications, and density) in two experiments: one with pages in Hebrew, entailing right-to-left reading, and the other with English pages, entailing left-to-right reading. Some performance patterns (measured by search times and eye movements) were similar between languages. Performance was particularly poor in pages with many links and variable densities, but it improved with the presence of uniform density. Alignment was not shown to be a performance-enhancing factor. The findings are discussed in terms of the similarities and differences in the impact of layout factors between GUIs and Web pages. Actual or potential applications of this research include specific guidelines for Web page design.

33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Layout and spacing of marine... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Hazardous Gas Design and Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 33 Navigation and Navigable Waters 2 2011-07-01 2011-07-01 false Layout and spacing of marine... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Hazardous Gas Design and Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 33 Navigation and Navigable Waters 2 2013-07-01 2013-07-01 false Layout and spacing of marine... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Hazardous Gas Design and Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

49 CFR 238.447 - Train operator's controls and power car cab layout.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Train operator's controls and power car cab layout... layout. (a) Train operator controls in the power car cab shall be arranged so as to minimize the chance.... (d) Power car cab information displays shall be designed with the following characteristics: (1...

33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 33 Navigation and Navigable Waters 2 2014-07-01 2014-07-01 false Layout and spacing of marine... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Hazardous Gas Design and Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

49 CFR 238.447 - Train operator's controls and power car cab layout.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Train operator's controls and power car cab layout... layout. (a) Train operator controls in the power car cab shall be arranged so as to minimize the chance.... (d) Power car cab information displays shall be designed with the following characteristics: (1...

49 CFR 238.447 - Train operator's controls and power car cab layout.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Train operator's controls and power car cab layout... layout. (a) Train operator controls in the power car cab shall be arranged so as to minimize the chance.... (d) Power car cab information displays shall be designed with the following characteristics: (1...

33 CFR 127.1105 - Layout and spacing of marine transfer area for LHG.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 33 Navigation and Navigable Waters 2 2012-07-01 2012-07-01 false Layout and spacing of marine... AND LIQUEFIED HAZARDOUS GAS Waterfront Facilities Handling Liquefied Hazardous Gas Design and Construction § 127.1105 Layout and spacing of marine transfer area for LHG. Each new waterfront facility...

A second generation 50 Mbps VLSI level zero processing system prototype

NASA Technical Reports Server (NTRS)

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

SUSTAINABLE ENERGY SYSTEMS DESIGN FOR A TRIBAL VILLAGE IN INDIA

EPA Science Inventory