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Sample records for vlsi technology wafers

  1. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

  2. High speed synchronizer card utilizing VLSI technology

    NASA Technical Reports Server (NTRS)

    Speciale, Nicholas; Wunderlich, Kristin

    1988-01-01

    A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

  3. VLSI Technology: Impact and Promise. Identifying Emerging Issues and Trends in Technology for Special Education.

    ERIC Educational Resources Information Center

    Bayoumi, Magdy

    As part of a 3-year study to identify emerging issues and trends in technology for special education, this paper addresses the implications of very large scale integrated (VLSI) technology. The first section reviews the development of educational technology, particularly microelectronics technology, from the 1950s to the present. The implications…

  4. GaAs VLSI technology and circuit elements for DSP

    NASA Astrophysics Data System (ADS)

    Mikkelson, James M.

    1990-10-01

    Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability

  5. Comparison of the radiation hardness of various VLSI technologies for defense applications

    SciTech Connect

    Gibbon, C.F.

    1985-01-01

    In this review the radiation hardness of various potential very large scale (VLSI) IC technologies is evaluated. IC scaling produces several countervailing trends. Reducing vertical dimensions tends to increase total dose hardness, while reducing lateral feature sizes may increase susceptibility to transient radiation effects. It is concluded that during the next decade at least, silicon complimentary MOS (CMOS), perhaps on an insulating substrate (SOI) will be the technology of choice for VLSI in defense systems.

  6. Deep sub-micron stud-via technology for superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-05-01

    A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.

  7. Deep sub-micron stud-via technology of superconductor VLSI circuits

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.; Bolkhovsky, V.; Weir, T.; Johnson, L. M.; Oliver, W. D.; Gouker, M. A.

    2014-02-01

    A fabrication process has been developed for fully planarized Nb-based superconducting interlayer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of etched contact holes in the interlayer dielectric it employs etched and planarized Nb pillars (studs) as connectors between adjacent wiring layers. Detailed results are presented for one version of the process that utilizes Nb/Al/Nb trilayers for each wiring layer instead of single Nb wiring layers. Nb studs are etched in the top layer of the trilayer to provide vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented in the normal and superconducting states. Superconducting critical current density in the fabricated stud-vias is about 0.3 A μm-2 and approaches the depairing current density of Nb films.

  8. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; French, M.; Manolopoulos, S.; Tyndel, M.; Allport, P.; Bates, R.; O'Shea, V.; Hall, G.; Raymond, M.

    2003-03-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to tape. Because of the large number of pixels, data reduction is needed on the sensor itself or just outside. This brings in stringent requirements on the temporal noise as well as to the sensor uniformity, expressed as a Fixed Pattern Noise (FPN). A pixel architecture with an additional transistor is proposed. This architecture, coupled to correlated double sampling of the signal will allow cancellation of the two dominant noise sources, namely the reset or kTC noise and the FPN. A prototype has been designed in a standard 0.25 μm CMOS technology. It has also a structure for electrical calibration of the sensor. The prototype is functional and detailed tests are under way.

  9. A VLSI implementation of DCT using pass transistor technology

    NASA Technical Reports Server (NTRS)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    1992-01-01

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  10. A VLSI implementation of DCT using pass transistor technology

    NASA Astrophysics Data System (ADS)

    Kamath, S.; Lynn, Douglas; Whitaker, Sterling

    A VLSI design for performing the Discrete Cosine Transform (DCT) operation on image blocks of size 16 x 16 in a real time fashion operating at 34 MHz (worst case) is presented. The process used was Hewlett-Packard's CMOS26--A 3 metal CMOS process with a minimum feature size of 0.75 micron. The design is based on Multiply-Accumulate (MAC) cells which make use of a modified Booth recoding algorithm for performing multiplication. The design of these cells is straight forward, and the layouts are regular with no complex routing. Two versions of these MAC cells were designed and their layouts completed. Both versions were simulated using SPICE to estimate their performance. One version is slightly faster at the cost of larger silicon area and higher power consumption. An improvement in speed of almost 20 percent is achieved after several iterations of simulation and re-sizing.

  11. A benchmark investigation on cleaning photomasks using wafer cleaning technologies

    NASA Astrophysics Data System (ADS)

    Kindt, Louis; Burnham, Jay; Marmillion, Pat

    2004-12-01

    As new technologies are developed for smaller linewidths, the specifications for mask cleanliness become much stricter. Not only must the particle removal efficiency increase, but the largest allowable particle size decreases. Specifications for film thickness and surface roughness are becoming tighter and consequently the integrity of these films must be maintained in order to preserve the functionality of the masks. Residual contamination remaining on the surface of the mask after cleaning processes can lead to subpellicle defect growth once the mask is exposed in a stepper environment. Only during the last several years, has an increased focus been put on improving mask cleaning. Over the years, considerably more effort has been put into developing advanced wafer cleaning technologies. However, because of the small market involved with mask cleaning, wafer cleaning equipment vendors have been reluctant to invest time and effort into developing cleaning processes and adapting their toolset to accommodate masks. With the advent of 300 mm processing, wafer cleaning tools are now more easily adapted to processing masks. These wafer cleaning technologies may offer a solution to the difficulties of mask cleaning and need to be investigated to determine whether or not they warrant continued investigation. This paper focuses on benchmarking advanced wafer cleaning technologies applied to mask cleaning. Ozonated water, hydrogenated water, super critical fluids, and cryogenic cleaning have been investigated with regards to stripping resist and cleaning particles from masks. Results that include film thickness changes, surface contamination, and particle removal efficiency will be discussed.

  12. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 μm or thicker, such as ribbons, sheet, or spheral silicon.

  13. Product assurance technology for custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

    1985-01-01

    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.

  14. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  15. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  16. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  17. New dynamic FET logic and serial memory circuits for VLSI GaAs technology

    NASA Technical Reports Server (NTRS)

    Eldin, A. G.

    1991-01-01

    The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

  18. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  19. SEMICONDUCTOR TECHNOLOGY: Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

    NASA Astrophysics Data System (ADS)

    Yuhan, Cao; Le, Luo

    2009-08-01

    A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.

  20. An electron-multiplying ‘Micromegas’ grid made in silicon wafer post-processing technology

    NASA Astrophysics Data System (ADS)

    Chefdeville, M.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E. H. M.; van der Putten, S.; Salm, C.; Schmitz, J.; Smits, S.; Timmermans, J.; Visschers, J. L.

    2006-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 μm by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication occurs: primary electrons from the drift space above the grid enter the holes and cause electron avalanches in the high-field region between the grid and the anode. Production and operational characteristics of the device are described. With this newly developed technology, CMOS (pixel) readout chips can be covered with a gas multiplication grid. Such a chip forms, together with the grid, an integrated device which can be applied as readout in a wide field of gaseous detectors.

  1. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  2. An aluminum-germanium eutectic structure for silicon wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Perez-Quintana, I.; Ottaviani, G.; Tonini, R.; Felisari, L.; Garavaglia, M.; Oggioni, L.; Morin, D.

    2005-08-01

    An aluminum-germanium eutectic bonding technology has been used to uniformly bond two silicon wafers for MEMS packaging at temperatures as low as 450 °C, well below the aluminum-silicon eutectic temperature (577 °C). A device silicon wafer has been put in contact with a cap wafer where an aluminum film covered by a germanium film has been thermally evaporated. The annealing has been performed in a vacuum furnace under uniaxial pressure variable from 1.8 up to 30 kbar. The samples have been analyzed with various analytical techniques. 4He+ MeV Rutherford Backscattering Spectrometry (RBS) has been used to measure the thicknesses of the deposited films and to follow the aluminum-germanium intermixing, Scanning Acoustic Microscope (SAM) to control the uniformity of the bonding, Scanning Electron Microscope (SEM) associated with electron induced X-ray fluorescence to analyze composition, morphology and elements distribution in the film between the two bonded wafers. The temperatures for the annealing were selected above and below the Ge-Al the eutectic temperature. At temperatures below the eutectic no-bonding has been obtained for any applied pressure. Above the eutectic bonding occurs. The formation of a liquid film is mandatory to obtain a reproducible and robust bonding. The pressure is necessary to improve the contacts between the two wafers; its role in the metallurgy of the bonding needs to be explored.

  3. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    NASA Astrophysics Data System (ADS)

    Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

    2013-05-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  4. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  5. Silicon TSV interposers for photonics and VLSI packaging

    NASA Astrophysics Data System (ADS)

    Vodrahalli, N.; Li, C. Y.; Kosenko, V.

    2011-02-01

    Miniaturization, higher performance, and higher bandwidth needs of the electronic industry continue to drive technology innovations through increased levels of integration. Through Silicon Via (TSV) technology along with flip chip technology provides significant improvements over the traditional technologies for packaging VLSI circuits. Silicon Interposers built using TSVs and embedded capacitors provide solutions to the next generation needs of VLSI Packaging. TSV Si interposers also provide a paltform for integrating photonic elements like the laser diodes and optical fibers for next generation high bandwidth VLSI packaging. The presentation describes (i) the TSV technologies developed, (ii) implementation of Si TSV interposer with embedded capacitors for VLSI packaging, and (iii) development of Si TSV interposer for integration of photonics and VLSI subsystems. Reliability results of interposers with embedded capacitors are also presented.

  6. A novel technology for fabricating customizable VLSI artificial neural network chips

    SciTech Connect

    Fu, C.Y.; Law, B.; Chapline, G.; Swenson, D.

    1992-02-05

    This paper describes an implementation of hardware neural networks using highly linear thin-film resistor technology and an 8-bit binary weight circuit to produce customizable artificial neural network chips and systems. These neural networks are programmed using precision laser cutting and deposition. The fast turnaround of laser-based customization allows us to explore different neural network architectures and to rapidly program the synaptic weights. Our customizable chip allows us to expand an artificial network laterally and vertically. This flexibility permits us to build very large neural network systems.

  7. Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies

    NASA Astrophysics Data System (ADS)

    Lee, Tien-Hsi

    Wafer bonding is an attractive technology for modern semiconductor and microelectronic industry due to its variability in allowing combination of materials. Initially, the bonding of wafers of the same material, such as silicon-silicon wafer bonding has been major interest. In the meantime, research interest has shifted to the bonding of dissimilar materials such as silicon to quartz or to sapphire. Thermal stress coming from the different expansion coefficients usually is a barrier to the success of dissimilar material bonding. Thermal stress may cause debonding, sliding, cracking, thermal misfit dislocations, or film wrinkle to impair the quality of the transferred layer. This dissertation presents several effective approaches to solve the thermal stress problem. These approaches concern bonding processes (low vacuum bonding and storage), thinning (advanced ion implantation layer splitting), and annealing processes (accumulative effect of blister generation) and are combined to design the best heat-treatment cycle. For this propose the concept of hot bonding is used in order to effectively minimize the thermal mismatch of dissimilar material bonding during the bonding and thinning procedures. During the initial bonding and bond strengthening phase, the difference in the temperature between bonding and annealing processes should be decreased as much as possible to avoid excessive thermal stresses. This concept can be realized either by increasing the bonding temperature or by decreasing the annealing temperature. A thinning technique has to employed that can thin the device wafer before debonding occurs due to the thermal stress generated either from the cooling-down process in the first case or by the annealing process itself in the late case. The ion implantation layer splitting method, also known as the Smart-cutsp°ler process, developed by Bruel at LEIT in France is a practical thinning technique which satisfies the above requirement. In the study, an

  8. VLSI Universal Noiseless Coder

    NASA Technical Reports Server (NTRS)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  9. Sensitivity analysis of add-on price estimate for select silicon wafering technologies

    NASA Technical Reports Server (NTRS)

    Mokashi, A. R.

    1982-01-01

    The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

  10. Thin-film encapsulation technology for above-IC MEMS wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Zhang, Qing; Cicek, Paul-Vahé; Nabki, Frederic; El-Gamal, Mourad

    2013-12-01

    This work presents a low-cost and low-temperature wafer-level packaging solution for microelectromechanical systems (MEMS) devices. Heat-sensitive polymer poly(propylene carbonate) is used as the sacrificial material to release the capping layer in a clean and fast manner. Free-standing caps made of amorphous silicon carbide films and as large as 450 µm in diameter are successfully fabricated. To demonstrate the validity of this technology, surface-micromachined Pirani vacuum gauges are fabricated as an example of MEMS devices and encapsulated. Capped Pirani gauges respond to pressure between 1 mTorr and 1 atm. The Pirani gauges are sealed with Parylene C films that exhibit near-hermetic properties and the initial sealing pressure for 300 µm diameter cavities is characterized to be in the range of tens of torr.

  11. Innovative design methodology for implementing heterogeneous multiprocessor architectures in VLSI

    SciTech Connect

    Tientien Li

    1983-01-01

    Considering the design cost of today's VLSI systems, advanced VLSI technology may not be cost-effective for implementing complex computer systems. In the paper, an innovative design approach which can drastically reduce the cost of implementing heterogeneous multiprocessor architectures in VLSI is presented. The author introduces high-level architectural design tools for assisting the design of multiprocessor systems with distributed memory modules and communication networks, and presents a logic/firmware synthesis scheme for automatically implementing multitasking structures and system service functions for multiprocessor architectures. Furthermore, the importance of the firmware synthesis aspect of VLSI system design is emphasized. Most logic of complex VLSI systems can be implemented very easily in firmware using the design approach introduced here. 10 references.

  12. Single-wafer-processed nano-positioning XY-stages with trench-sidewall micromachining technology

    NASA Astrophysics Data System (ADS)

    Gu, Lei; Li, Xinxin; Bao, Haifei; Liu, Bin; Wang, Yuelin; Liu, Min; Yang, Zunxian; Cheng, Baoluo

    2006-07-01

    For operation and manipulation with nanometric positioning precision, a single crystalline silicon micro XY-stage is developed by using double-sided bulk-micromachining technology. Front-side deep reactive ion etching combined with backside anisotropic etching constructs the high-aspect-ratio comb-driven XY-stage in a single standard silicon wafer (i.e., no silicon on insulator wafer is used). For integrating several electrostatic actuators in one silicon chip, different actuators are electrically isolated from each other using a trench-sidewall insulating technique. SiO2-refilled trench bars are formed on vertical trench sidewalls to isolate adjacent comb-drive elements. Combined with the reverse-biased p-n junction along the boron-diffused trench sidewall for comb driving, individual actuators can be operated independently. The developed XY-stage of 1600 × 1600 µm2 is suspended by four sets of folded-beam and bending-flexure composite springs. To maximize the moving distance, a two-segment comb finger with a gently curved transition is used for both improving the actuation efficiency and avoiding side instability of the stage. The experimental results verify the stage design including the gentle transition of a two-segment comb-drive scheme. Under 23 V driving voltage, a 10 µm moving stroke is measured in each of the four directions. Compared with a conventional comb structure, the two-segment comb fingers contribute 70% improvement in actuating amplitude. The positioning precision of the stage is evaluated with a nano-mechanical indenting experiment. A scanning probe microscopy probe with an electrical-heated nano tip is put in contact with the surface of a polymethyl methacrylate film that is coated on the stage surface. Along with the movement of the stage, pulsed heating on the nano tip produces serial nano-pitches. With the nano-indenting experiment, better than 18 nm positioning precision is obtained for the XY-stage.

  13. 300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

    NASA Astrophysics Data System (ADS)

    Widiez, Julie; Sollier, Sébastien; Baron, Thierry; Martin, Mickaël; Gaudin, Gweltaz; Mazen, Frédéric; Madeira, Florence; Favier, Sylvie; Salaun, Amélie; Alcotte, Reynald; Beche, Elodie; Grampeix, Helen; Veytizou, Christelle; Moulet, Jean-Sébastien

    2016-04-01

    This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III-V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III-V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III-V compound interface.

  14. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  15. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for

  16. Supercomputing with VLSI

    SciTech Connect

    Manohar, S.

    1989-01-01

    Supercoprocessors (SCPs), highly parallel VLSI architectures tuned to solving a specific problem class, are shown to provide a means of cost-effective supercomputing. A methodology for building SCPs for different computation-intensive problems is described: two pragmatic constraints namely problem-size-independence and limited-bandwidth constraint are imposed on special-purposes architectures; a simple but powerful model of computation is used to derive general upper bounds on the speedup obtainable using such architectures. It is shown that bounds established by other authors for matrix multiplication and sorting, using problem-specific approaches, can be derived very simply using this model. Poisson Engine-I (PE-I), a prototype SCP, is a system for solving the Laplace equation using the finite difference approximation. PE-I uses a novel approach: asynchronous iteration methods are implemented using a fixed-size, synchronous array of simple processing elements. Architectural and algorithmic extensions to PE-I are briefly considered: the solution of a wider class of PDEs and the use of more sophisticated algorithms like the multigrid method are some of the issues addressed. The SCP methodology is applied to the problems of matrix-multiplication and sorting. For sorting, an SCP with superlinear speedup is outlined. For the matrix problem, the architecture and implementation details of SMP are described in detail. SMP, realized with about fifty chips using current technology, is capable of through-puts greater than 150 Mflops, and is also unique in being optimal with respect to the lowerbound derived using the SCP model. The use of a collection of sup SCPs is advanced as a cost-effective supercomputing alternative.

  17. The 1992 4th NASA SERC Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  18. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  19. NASA Space Engineering Research Center for VLSI System Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  20. High Energy IED measurements with MEMs based Si grid technology inside a 300mm Si wafer

    NASA Astrophysics Data System (ADS)

    Funk, Merritt

    2012-10-01

    The measurement of ion energy at the wafer surface for commercial equipment and process development without extensive modification of the reactor geometry has been an industry challenge. High energy, wide frequency range, process gases tolerant, contamination free and accurate ion energy measurements are the base requirements. In this work we will report on the complete system developed to achieve the base requirements. The system includes: a reusable silicon ion energy analyzer (IEA) wafer, signal feed through, RF confinement, and high voltage measurement and control. The IEA wafer design required carful understanding of the relationships between the plasma Debye length, the number of grids, intergrid charge exchange (spacing), capacitive coupling, materials, and dielectric flash over constraints. RF confinement with measurement transparency was addressed so as not to disturb the chamber plasma, wafer sheath and DC self-bias as well as to achieve spectral accuracy The experimental results were collected using a commercial parallel plate etcher powered by a dual frequency (VHF + LF). Modeling and Simulations also confirmed the details captured in the IED.

  1. Verification of VLSI designs

    NASA Technical Reports Server (NTRS)

    Windley, P. J.

    1991-01-01

    In this paper we explore the specification and verification of VLSI designs. The paper focuses on abstract specification and verification of functionality using mathematical logic as opposed to low-level boolean equivalence verification such as that done using BDD's and Model Checking. Specification and verification, sometimes called formal methods, is one tool for increasing computer dependability in the face of an exponentially increasing testing effort.

  2. Very Large Scale Integration (VLSI).

    ERIC Educational Resources Information Center

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  3. VLSI physical design analyzer: A profiling and data mining tool

    NASA Astrophysics Data System (ADS)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  4. Holographic optical interconnects for VLSI

    NASA Technical Reports Server (NTRS)

    Bergman, L. A.; Wu, W. H.; Johnston, A. R.; Nixon, R.; Esener, Sadik C.

    1986-01-01

    This paper introduces new applications and design trade-offs anticipated for free-space optical interconnections of VLSI chips. New implementation s of VLSI functions are described that use the capability of making optical inputs at any point on a chip and take advantage of greater flexibility in on-chip signal routing. These include n-port addressable memories, CPU clock phase distribution, hardware multipliers, and dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper focuses on identifying the design issues, their possible solutions, and their impact on VLSI design techniques and, finally, presents some preliminary measurements on various system components.

  5. Holographic optical interconnects for VLSI

    NASA Astrophysics Data System (ADS)

    Bergman, L. A.; Wu, W. H.; Johnston, A. R.; Nixon, R.; Esener, Sadik C.

    1986-10-01

    This paper introduces new applications and design trade-offs anticipated for free-space optical interconnections of VLSI chips. New implementation s of VLSI functions are described that use the capability of making optical inputs at any point on a chip and take advantage of greater flexibility in on-chip signal routing. These include n-port addressable memories, CPU clock phase distribution, hardware multipliers, and dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper focuses on identifying the design issues, their possible solutions, and their impact on VLSI design techniques and, finally, presents some preliminary measurements on various system components.

  6. ATM in B-ISDN communication systems and VLSI realization

    NASA Astrophysics Data System (ADS)

    Koinuma, Takeo; Miyaho, Noriharu

    1995-04-01

    The VLSI trends and how VLSI's can be used to achieve Asynchronous Transfer Mode (ATM) switching node systems for B-ISDN were discussed. Implementing a practical ATM node system will need the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service controls need several hundred thousand logic gates and several megabytes of high-speed static RAM. ATM node system architecture was based on design concepts of a building-block-type configuration and hierarchical multiplexing. Moreover, future ATM node systems are considered on the basis of 0.2 micron VLSI development trends and hardware prerequisites.

  7. Neural Networks Of VLSI Components

    NASA Technical Reports Server (NTRS)

    Eberhardt, Silvio P.

    1991-01-01

    Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.

  8. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  9. GaAs VLSI for aerospace electronics

    NASA Technical Reports Server (NTRS)

    Larue, G.; Chan, P.

    1990-01-01

    Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

  10. Fundamentals of Microelectronics Processing (VLSI).

    ERIC Educational Resources Information Center

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  11. VLSI mixed signal processing system

    NASA Technical Reports Server (NTRS)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  12. 3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

    NASA Astrophysics Data System (ADS)

    Hofmann, L.; Dempwolf, S.; Reuter, D.; Ecke, R.; Gottfried, K.; Schulz, S. E.; Knechtel, R.; Geßner, T.

    2015-05-01

    Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

  13. Wafer Manufacturing and Slicing Using Wiresaw

    NASA Astrophysics Data System (ADS)

    Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

    Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer

  14. A parallel processing VLSI BAM engine.

    PubMed

    Hasan, S R; Siong, N K

    1997-01-01

    In this paper emerging parallel/distributed architectures are explored for the digital VLSI implementation of adaptive bidirectional associative memory (BAM) neural network. A single instruction stream many data stream (SIMD)-based parallel processing architecture, is developed for the adaptive BAM neural network, taking advantage of the inherent parallelism in BAM. This novel neural processor architecture is named the sliding feeder BAM array processor (SLiFBAM). The SLiFBAM processor can be viewed as a two-stroke neural processing engine, It has four operating modes: learn pattern, evaluate pattern, read weight, and write weight. Design of a SLiFBAM VLSI processor chip is also described. By using 2-mum scalable CMOS technology, a SLiFBAM processor chip with 4+4 neurons and eight modules of 256x5 bit local weight-storage SRAM, was integrated on a 6.9x7.4 mm(2) prototype die. The system architecture is highly flexible and modular, enabling the construction of larger BAM networks of up to 252 neurons using multiple SLiFBAM chips.

  15. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  16. An efficient interpolation filter VLSI architecture for HEVC standard

    NASA Astrophysics Data System (ADS)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  17. The Fifth NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  18. Summary of workshop on the application of VLSI for robotic sensing

    NASA Technical Reports Server (NTRS)

    Brooks, T.; Wilcox, B.

    1984-01-01

    It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

  19. SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    NASA Astrophysics Data System (ADS)

    Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

    2010-10-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

  20. Novel spin-coating technology for 248-nm/193-nm DUV lithography and low-k spin on dielectrics of 200-mm/300-mm wafers

    NASA Astrophysics Data System (ADS)

    Gurer, Emir; Zhong, Tom X.; Lewellen, John W.; Lee, Ed C.

    2000-06-01

    An alternative coating technology was developed for 248 nm/193 nm DUV lithography and low-k spin on dielectric (SOD) materials used in the interconnect area. This is a 300 mm enabling technology which overcomes turbulent flow limitations above 2000 rpm and it prevents 40 - 60% reduction on the process latitudes of evaporation-related variables, common to 300 mm conventional coaters. Our new coating technology is fully enclosed and it is capable of controlling the solvent concentration above the resist film dynamically in the gas phase. This feature allows a direct control of the evaporation mass transfer which determines the quality of the final resist profiles. Following process advantages are reported in this paper: (1) Demonstrated that final resist film thickness can be routinely varied by 4000 angstrom at a fixed drying spin speed, thus minimizing the impact of turbulence wall for 300 mm wafers. (2) Evaporation control allows wider range of useful thickness from a fixed viscosity material. (3) Latitudes of evaporation-related process variables is about 40% larger than that of a conventional coater. (4) Highly uniform films of 0.05% were obtained for 8800 angstrom target thickness with tighter wafer-wafer profile control because of the enclosed nature of the technology. (5) Dynamic evaporation control facilitates resist consumption minimization. Preliminary results indicate feasibility of a 0.4 cc process of record (POR) for a 200 mm substrate. (6) Lower COO due to demonstrated relative insensitivity to environmental variables, robust resist consumption minimization and superior process capabilities. (7) Improved planarization and gap fill properties for the new generation photoresist/low-k SOD materials deposited using this enclosed coating technology.

  1. SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

    NASA Astrophysics Data System (ADS)

    Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

    2010-02-01

    To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

  2. Compaction-based VLSI layout

    SciTech Connect

    Xiong, Xiao-Ming.

    1989-01-01

    Generally speaking, a compaction based VLSI layout system consists of two major parts: (1) a symbolic editor which maintains explicit connectivity and structural information about the circuit; (2) a compactor which translates the high level description of a circuit to the detailed layout needed for fabrication and tries to make as compact a layout as Possible without violating any design rules. Instead of developing a complete compaction based VLSI layout system, this thesis presents some theoretical concepts and several new compaction techniques, such as scan line based approach, which can either cooperate with a symbolic editor to form a layout system or work as a post-process step to improve the results obtained by an existing layout system. Also, some compaction related problems are solved and proposed. Based on the special property of channel routing, the author presents a geometric method for channel compaction. For a given channel routing topology, the minimum channel height is always achieved with the incorporation of sliding contacts and automatically inserting necessary jogs. The geometric compaction approach is then generalized and applied to compact the entire VLSI chip at the building-block level. With a systematic way of automatic jog insertion, he proves that under the given layout topology and design rules, the lower bound of one dimensional compaction with automatic jog insertion is achieved by the geometric compaction algorithm. A new simultaneous two-dimensional compaction algorithm is developed primarily for placement refinement of building-block layout. The algorithm is based on a set of defined graph operations on a mixed adjacency graph for a given placement. The mixed-adjacency graph can be updated efficiently if the placement is represented by tiles in the geometric domain.

  3. Fast and area-efficient VLSI adders

    SciTech Connect

    Han, T.D.

    1987-01-01

    Area-time tradeoffs have been an important topic in VLSI research. This is because the cost of fabricating a circuit is an exponential function of its area. As a result, optimizing the area of a VLSI design is much more important than optimizing the speed of an algorithm. This dissertation examines area-time tradeoffs in VLSI for prefix computation using graph representations of the problem. Since the problem is intimately related to binary addition, results obtained lead to design of area-time efficient VLSI adders. This is a major goal of the work: to design very low latency-addition circuitry that is also area-efficient. To this end, a new graph representation is presented for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, the author designed VLSI adders having area A = O(n log n) whose delay time is the lowest possible value, i.e., the fastest possible area-efficient VLSI adder. For the large number of inputs, the pipelined model of prefix circuit is presented. Also presented is a fault-tolerant model for the developed prefix circuit, based on the partitioning of the network.

  4. Using Ant Colony Optimization for Routing in VLSI Chips

    NASA Astrophysics Data System (ADS)

    Arora, Tamanna; Moses, Melanie

    2009-04-01

    Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

  5. Development of wafer-level-packaging technology for simultaneous sealing of accelerometer and gyroscope under different pressures

    NASA Astrophysics Data System (ADS)

    Aono, T.; Suzuki, K.; Kanamaru, M.; Okada, R.; Maeda, D.; Hayashi, M.; Isono, Y.

    2016-10-01

    This research demonstrates a newly developed anodic bonding-based wafer-level-packaging technique to simultaneously seal an accelerometer in the atmosphere and a gyroscope in a vacuum with a glass cap for micro-electromechanical systems sensors. It is necessary for the accelerometer, with a damping oscillator, to be sealed in the atmosphere to achieve a high-speed response. As the gyroscope can achieve high sensitivity with a large displacement at the resonant frequency without air-damping, the gyroscope must be sealed in a vacuum. The technique consists of three processing steps: the first bonding step in the atmosphere for the accelerometer, the pressure control step and the second bonding step in a vacuum for the gyroscope. The process conditions were experimentally determined to achieve higher shear strength at the interface of the packaging. The packaging performance of the accelerometer and gyroscope after wafer-level packaging was also investigated using a laser Doppler velocimeter at room temperature. The amplitude at the resonant frequency of the accelerometer was reduced by air damping, and the quality factor of the gyroscope showed a value higher than 1000. The reliability of the gyroscope was also confirmed by a thermal cyclic test and an endurance test at high humidity and high temperature.

  6. Reconfigurable VLSI architecture for a database processor

    SciTech Connect

    Oflazer, K.

    1983-01-01

    This work brings together the processing potential offered by regularly structured VLSI processing units and the architecture of a database processor-the relational associative processor (RAP). The main motivations are to integrate a RAP cell processor on a few VLSI chips and improve performance by employing procedures exploiting these VLSI chips and the system level reconfigurability of processing resources. The resulting VLSI database processor consists of parallel processing cells that can be reconfigured into a large processor to execute the hard operations of projection and semijoin efficiently. It is shown that such a configuration can provide 2 to 3 orders of magnitude of performance improvement over previous implementations of the RAP system in the execution of such operations. 27 refs.

  7. A second generation 50 Mbps VLSI level zero processing system prototype

    NASA Technical Reports Server (NTRS)

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  8. Designing of Low-Power VLSI Circuits using Non-Clocked Logic Style

    NASA Astrophysics Data System (ADS)

    Sharma, Vishal; Srivastava, Jitendra Kaushal

    2012-08-01

    Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi circuit, it is preferable to use Nonclocked logic styles as they have less switching power. In this work various Non-clocked logic styles are compared by performing transistor level simulations for half adder circuit using TSMC 0.18 µm Technology and Eldo simulator of Mentor graphics.

  9. Virtual model surgery and wafer fabrication using 2-dimensional cephalograms, 3-dimensional virtual dental models, and stereolithographic technology.

    PubMed

    Choi, Jin-Young; Hwang, Jong-Min; Baek, Seung-Hak

    2012-02-01

    Although several 3-dimensional virtual model surgery (3D-VMS) programs have been introduced to reduce time-consuming manual laboratory steps and potential errors, these programs still require 3D-computed tomography (3D-CT) data and involve complex computerized maneuvers. Because it is difficult to take 3D-CTs for all cases, a new VMS program using 2D lateral and posteroanterior cephalograms and 3D virtual dental models (2.5D-VMS program; 3Txer version 2.5, Orapix, Seoul, Korea) has recently been introduced. The purposes of this article were to present the methodology of the 2.5D-VMS program and to verify the accuracy of intermediate surgical wafers fabricated with the stereolithographic technique. Two cases successfully treated using the 2.5D-VMS program are presented. There was no significant difference in the position of upper dentition after surgical movement between 2.5D-VMS and 3D-VMS in 18 samples (less than 0.10 mm, P > .05, Wilcoxon-signed rank test). The 2.5D-VMS can be regarded as an effective alternative for 3D-VMS for cases in which 3D-CT data are not available.

  10. Characterization of degradation processes in MOS VLSI structures

    NASA Astrophysics Data System (ADS)

    Brozek, Tomasz; Jakubowski, Andrzej; Majkusiak, Bogdan

    1992-08-01

    The detailed investigations of degradation processes, their characterization and understanding of mechanisms responsible for degradation is of great technological interest, both from the fabrication point of view, and as a long-term reliability concern. Some of the effects usually need investigation in the completed MOS transistor structure (hot carrier degradation, threshold voltage, and channel mobility deterioration), but others should be studied with the special test structures so that effects can be investigated independently (electromigration, radiation effects, oxide wear-out). The paper presents a review of problems related to reliability of VLSI ICs, degradation processes, and their characterization.

  11. The 1991 3rd NASA Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1991-01-01

    Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2.

  12. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  13. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  14. The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Hsu, I.-S.; Truong, T. K.

    1986-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  15. The VLSI design of error-trellis syndrome decoding for convolutional codes

    NASA Technical Reports Server (NTRS)

    Reed, I. S.; Jensen, J. M.; Truong, T. K.; Hsu, I. S.

    1985-01-01

    A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

  16. Interconnection capacitance models for VLSI circuits

    NASA Astrophysics Data System (ADS)

    Wong, Shyh-Chyi; Liu, Patrick S.; Ru, Jien-Wen; Lin, Shi-Tron

    1998-06-01

    A new set of capacitance models is developed for delay estimation of VLSI interconnections. The set of models is derived for five representative wiring structures, with their combinations covering arbitrary VLSI layouts. A semi-empirical approach is adopted to deal with complicated geometry nature in VLSI and to allow for closed-form capacitance formulas to be developed to provide direct observation of capacitance variation vs process parameters as well as computational efficiency for circuit simulation. The formulas are given explicitly in terms of wire width, wire thickness, dielectric thickness and inter-wire spacing. The models show good agreement with numerical solutions from RAPHAEL and measurement data of fabricated capacitance test structures. The models are further applied and validated on a ring oscillator. It is shown that the frequency of the ring oscillator obtained from HSPICE simulation with our models agrees well with the bench measurement.

  17. Ultrafast nanoelectromechanical switches for VLSI power management

    NASA Astrophysics Data System (ADS)

    Venumbaka, Sri Ramya

    Power consumption is a major concern in the present chip design industry. Complementary Metal Oxide Semiconductor (CMOS) technology scaling has led to an exponential increase in the leakage power. The excessive power dissipation can result in more heat generation, which in turn increases the temperature. According to Intel's source, power density increased to a value of 1000 W/cm2 and is approaching the value which is equal to the radiation from the sun's surface (10000 W/cm2). This leads to reliability issues in nanometer-scale CMOS as Silicon starts melting at 1687K. To resolve this issue, we introduce a novel architecture to design nanoelectromechanical switches and implementation results with virtually zero leakage current, ˜1 V operation voltage, ˜1 GHz resonant frequency and nanometer-scale footprint. Microelectromechanical Switches (MEMS) have very low "on" and very high "off" resistances. Their switching voltages are usually high (5-50 V), switching speeds are usually low (1 MHz) and their footprints tend to be very large (many um2). We have designed and fabricated devices with very low actuation voltages and very high speed using tuning fork geometry compatible with conventional CMOS fabrication technologies. This unique switch geometry decreases the actuation voltage by a factor of 1.4 and doubles the switching speed. It consists of a cantilever beam that acts as a ground plane. Upon actuation, both the ground plane and the switch's main beam move towards each other that makes the center of mass stationary during switching and thus, the switching speed doubles. These tuning fork nanoelectromechanical switches can be readily implemented in Very Large Scale Integration (VLSI) circuits to manage leakage power. The thesis will describe the Nanoelectromechanical systems (NEMS) structures, their characteristics, leakage reduction techniques, reliability of the devices and piezo actuator structures to determine contact resistance and longevity of switches.

  18. Associative Pattern Recognition In Analog VLSI Circuits

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  19. Extremely long life and low-cost 193nm excimer laser chamber technology for 450mm wafer multipatterning lithography

    NASA Astrophysics Data System (ADS)

    Tsushima, Hiroaki; Katsuumi, Hisakazu; Ikeda, Hiroyuki; Asayama, Takeshi; Kumazaki, Takahito; Kurosu, Akihiko; Ohta, Takeshi; Kakizaki, Kouji; Matsunaga, Takashi; Mizoguchi, Hakaru

    2014-04-01

    193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. 193nm ArF exicmer lasers are expected to continue to be the main solution in photolithography, since advanced lithography technologies such as multiple patterning and Self-Aligned Double Patterning (SADP) are being developed. In order to apply these technologies to high-volume semiconductor manufacturing, the key is to reduce the total operating cost. To reduce the total operating cost, life extension of consumable part and reduction of power consumption are an important factor. The chamber life time and power consumption are a main factor to decide the total operating cost. Therefore, we have developed the new technology for extension of the chamber life time and low electricity consumption. In this paper, we will report the new technology to extend the life time of the laser chamber and to reduce the electricity consumption.

  20. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  1. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  2. SSI/MSI/LSI/VLSI/ULSI.

    ERIC Educational Resources Information Center

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  3. Bridging the gaps between mask inspection/review systems and actual wafer printability using computational metrology and inspection (CMI) technologies

    NASA Astrophysics Data System (ADS)

    Pang, Linyong; Tolani, Vikram; Satake, Masaki; Hu, Peter; Peng, Danping; Liu, Tingyang; Chen, Dongxue; Gleason, Bob; Vacca, Anthony

    2012-11-01

    Computational techniques have become increasingly important to improve resolution of optical lithography. Advanced computational lithography technologies, such as inverse lithography (ILT) and source mask optimization (SMO), are needed to print the most challenging layers, such as contact and metal, at the 20nm node and beyond. In order to deploy SMO and ILT into production, improvements and upgrades of mask manufacturing technology are required. These include writing, inspection, defect review, and repair. For example, mask plane inspection detects defect at highest resolution, but does not correlate accurately with scanner images. Aerial plane mask inspection and AIMSTM produce images close to those of a scanner, but except fot the latest AIMS-32TM, it does not have the flexibility needed to capture all the characteristics of free-form illumination. Advanced Computational Inspection and Metrology provides solutions to many of these issues.

  4. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  5. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  6. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  7. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    NASA Astrophysics Data System (ADS)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  8. Architecture for VLSI design of Reed-Solomon encoders

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1981-01-01

    The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

  9. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  10. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  11. VLSI 'smart' I/O module development

    NASA Astrophysics Data System (ADS)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  12. Systolic VLSI Reed-Solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.

    1986-01-01

    Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

  13. Leak detection utilizing analog binaural (VLSI) techniques

    NASA Astrophysics Data System (ADS)

    Hartley, Frank T.

    1993-08-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium is presented. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  14. Leak detection utilizing analog binaural (VLSI) techniques

    NASA Astrophysics Data System (ADS)

    Hartley, Frank T.

    1995-06-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  15. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    NASA Technical Reports Server (NTRS)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  16. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  17. Replacing design rules in the VLSI design cycle

    NASA Astrophysics Data System (ADS)

    Hurley, Paul; Kryszczuk, Krzysztof

    2012-03-01

    We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

  18. VLSI readout for imaging with polycrystalline mercuric iodide detectors

    NASA Astrophysics Data System (ADS)

    Turchetta, Renato; Dulinski, Wojtek; Husson, D.; Klein, N.; Riester, J. L.; Schieber, Michael M.; Zuck, A.; Braiman, M.; Melekhov, L.; Nissenbaum, J.; Sanguinetti, S.

    1998-11-01

    Recently polycrystalline mercuric iodide have become available, for room temperature radiation detectors over large areas at low cost. Though the quality of this material is still under improvement, ceramic detectors have been already been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors used are of different kinds: microstrips and pixels; of different sizes, up to about 1 square inch; and of different thickness, up to 600 microns. The properties of this first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed.

  19. Custom Analog VLSI for the Advanced Composition Explorer (ACE)

    NASA Astrophysics Data System (ADS)

    Cook, W. R.; Cummings, A.; Keeman, B.; Mewaldt, R. A.; Aalami, D.; Kleinfelder, S. A.; Marshall, J. H.

    1993-11-01

    Two custom analog VLSI chips are currently in development for scientific payloads of NASA's Advanced Composition Explorer. One chip will be fabricated in the radiation hard 1.2 um CMOS process of the United Technologies Microelectronics Center (UlMC), and will contain 16 complete discriminator/12 bit pulse-height-analysis chains for the readout of heavy ion Si strip detectors. The second chip will be fabricated by Harris Semiconductor in their dielectrically isolated bipolar VHF process. This chip will contain the active elements of a single precision pulse-height-analysis chain and several precision discriminator chains. The chips designed in this effort and the techniques employed are expected to be applicable in science payloads of future missions, especially those which place extraordinary premiums on weight, power, and/or performance.

  20. Realistic model of compact VLSI FitzHugh-Nagumo oscillators

    NASA Astrophysics Data System (ADS)

    Cosp, Jordi; Binczak, Stéphane; Madrenas, Jordi; Fernández, Daniel

    2014-02-01

    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

  1. Cascaded VLSI Chips Help Neural Network To Learn

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  2. VLSI implementation of moment invariants for automated inspection

    NASA Astrophysics Data System (ADS)

    Armstrong, G. A.; Simpson, M. L.; Bouldin, D. W.

    This paper describes the design of a very large scale integration (VLSI) application specific integrated circuit (ASIC) for use in automated inspection. The inspection scheme uses Hu and Maitra's algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. The prototype ASIC is currently being fabricated in 2.0-micron CMOS technology and has been simulated at 20 MHz. The final ASICs will be used in parallel at the board level to achieve the 230 MOPs necessary to perform the moment invariant algorithms in real time on 512 by 512 pixel images with 256 grey scales.

  3. Silicon waveguides produced by wafer bonding

    SciTech Connect

    Poulsen, M.; Jensen, F.; Bunk, O.; Feidenhans'l, R.; Breiby, D.W.

    2005-12-26

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 {mu}m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides to excite single guided modes at typical x-ray energies.

  4. Scanning holographic scatterometer for wafer surface inspection

    NASA Astrophysics Data System (ADS)

    Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

    2004-05-01

    The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

  5. Wafer-scale graphene integrated circuit.

    PubMed

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  6. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  7. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  8. A VLSI structure for the deadlock avoidance problem

    SciTech Connect

    Bertolazzi, P.; Bongiovanni, G.

    1985-11-01

    In this paper the authors present two VLSI structures implementing the banker's algorithm for the deadlock avoidance problem, and we derive the area x (time)/sup 2/ lower bound for such an algorithm. The first structure is based on the VLSI mesh of trees. The second structure is a modification of the first one, and it approaches more closely the theoretical lower bound.

  9. Parallel optimization algorithms and their implementation in VLSI design

    NASA Technical Reports Server (NTRS)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  10. Image Compression on a VLSI Neural-Based Vector Quantizer.

    ERIC Educational Resources Information Center

    Chen, Oscal T.-C.; And Others

    1992-01-01

    Describes a modified frequency-sensitive self-organization (FSO) algorithm for image data compression and the associated VLSI architecture. Topics discussed include vector quantization; VLSI neural processor architecture; detailed circuit implementation; and a neural network vector quantization prototype chip. Examples of images using the FSO…

  11. VLSI architectures for geometrical mapping problems in high-definition image processing

    NASA Technical Reports Server (NTRS)

    Kim, K.; Lee, J.

    1991-01-01

    This paper explores a VLSI architecture for geometrical mapping address computation. The geometric transformation is discussed in the context of plane projective geometry, which invokes a set of basic transformations to be implemented for the general image processing. The homogeneous and 2-dimensional cartesian coordinates are employed to represent the transformations, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme for a processor, which utilizes full-pipelining at the macro-level and parallel constant-factor-redundant arithmetic and full-pipelining at the micro-level, is assessed to produce a single VLSI chip for HDTV applications using state-of-art MOS technology.

  12. 30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

    NASA Technical Reports Server (NTRS)

    Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

    1986-01-01

    An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

  13. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  14. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

  15. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  16. Neural algorithms on VLSI concurrent architectures

    SciTech Connect

    Caviglia, D.D.; Bisio, G.M.; Parodi, G.

    1988-09-01

    The research concerns the study of neural algorithms for developing CAD tools with A.I. features in VLSI design activities. In this paper the focus is on optimization problems such as partitioning, placement and routing. These problems require massive computational power to be solved (NP-complete problems) and the standard approach is usually based on euristic techniques. Neural algorithms can be represented by a circuital model. This kind of representation can be easily mapped in a real circuit, which, however, features limited flexibility with respect to the variety of problems. In this sense the simulation of the neural circuit, by mapping it on a digital VLSI concurrent architecture seems to be preferrable; in addition this solution offers a wider choice with regard to algorithms characteristics (e.g. transfer curve of neural elements, reconfigurability of interconnections, etc.). The implementation with programmable components, such as transputers, allows an indirect mapping of the algorithm (one transputer for N neurons) accordingly to the dimension and the characteristics of the problem. In this way the neural algorithm described by the circuit is reduced to the algorithm that simulates the network behavior. The convergence properties of that formulation are studied with respect to the characteristics of the neural element transfer curve.

  17. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  18. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  19. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  20. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  1. Applications And Design Considerations For Optical Interconnects In VLSI

    NASA Astrophysics Data System (ADS)

    Bergman, L.; Johnston, A.; Nixon, R.; Esener, S.; Guest, C.; Yu, P.; Drabik, T.; Feldman, M.; Lee, S. H.

    1986-06-01

    This paper introduces new applications and design tradeoffs anticipated for free space optical interconnections of VLSI chips. New implementations of VLSI functions are described that use the capability of making optical inputs at any point on a chip, and take advantage of greater flexibility in on-chip signal routing. These include N-port addressable memories, CPU clock phase distribution, hardware multipliers, dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper will focus on identifying the design issues, their possible solution, and their impact on VLSI design techniques.

  2. A statistical approach to electromigration design for high performance VLSI

    NASA Astrophysics Data System (ADS)

    Kitchin, John; Sriram, T. S.

    1998-01-01

    Statistical Electromigration Budgeting (J. Kitchin, 1995 Symposium on VLSI Circuits) or SEB is based on the concepts: (a) reliable design in VLSI means achieving a chip-level reliability goal and (b) electromigration degradation is inherently statistical in nature. The SEB methodology is reviewed along with results from recent high performance VLSI designs. Two SEB-based approaches for efficiently coupling metallization reliability statistics to design options are developed. Allowable-length-at-stress design rules communicate electromigration risk budget constraints to designers without the need for sophisticated CAD tools for chip-level interconnect analysis. Electromigration risk contours allow comparison of evolving metallization reliability statistics with design requirements having multiple frequency, temperature, and voltage options, a common need in high performance VLSI product development.

  3. NASA Space Engineering Research Center Symposium on VLSI Design

    NASA Technical Reports Server (NTRS)

    Maki, Gary K.

    1990-01-01

    The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers.

  4. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  5. Analog VLSI neural network integrated circuits

    NASA Astrophysics Data System (ADS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-12-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  6. Periodic binary sequence generators: VLSI circuits considerations

    NASA Technical Reports Server (NTRS)

    Perlman, M.

    1984-01-01

    Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.

  7. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  8. Analog VLSI system for active drag reduction

    SciTech Connect

    Gupta, B.; Goodman, R.; Jiang, F.; Tai, Y.C.; Tung, S.; Ho, C.M.

    1996-10-01

    In today`s cost-conscious air transportation industry, fuel costs are a substantial economic concern. Drag reduction is an important way to reduce costs. Even a 5% reduction in drag translates into estimated savings of millions of dollars in fuel costs. Drawing inspiration from the structure of shark skin, the authors are building a system to reduce drag along a surface. Our analog VLSI system interfaces with microfabricated, constant-temperature shear stress sensors. It detects regions of high shear stress and outputs a control signal to activate a microactuator. We are in the process of verifying the actual drag reduction by controlling microactuators in wind tunnel experiments. We are encouraged that an approach similar to one that biology employs provides a very useful contribution to the problem of drag reduction. 9 refs., 21 figs.

  9. Implementation of optical interconnections for VLSI

    NASA Technical Reports Server (NTRS)

    Wu, Wennie H.; Bergman, Larry A.; Johnston, Alan R.; Guest, Clark C.; Esener, Sadik C.

    1987-01-01

    This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: (1) the holographic optical element (HOE), (2) the laser sources, (3) the detectors and associated circuits forming an optically addressed gate, and (4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 x 20 microns has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity, and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five holograms.

  10. Finite element computation with parallel VLSI

    NASA Technical Reports Server (NTRS)

    Mcgregor, J.; Salama, M.

    1983-01-01

    This paper describes a parallel processing computer consisting of a 16-bit microcomputer as a master processor which controls and coordinates the activities of 8086/8087 VLSI chip set slave processors working in parallel. The hardware is inexpensive and can be flexibly configured and programmed to perform various functions. This makes it a useful research tool for the development of, and experimentation with parallel mathematical algorithms. Application of the hardware to computational tasks involved in the finite element analysis method is demonstrated by the generation and assembly of beam finite element stiffness matrices. A number of possible schemes for the implementation of N-elements on N- or n-processors (N is greater than n) are described, and the speedup factors of their time consumption are determined as a function of the number of available parallel processors.

  11. VLSI processors for signal detection in SETI

    NASA Technical Reports Server (NTRS)

    Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

    1989-01-01

    The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

  12. Mask registration and wafer overlay

    NASA Astrophysics Data System (ADS)

    Lee, Chulseung; Bang, Changjin; Kim, Myoungsoo; Kang, Hyosang; Lee, Dohwa; Jeong, Woonjae; Lim, Ok-Sung; Yoon, Seunghoon; Jung, Jaekang; Laske, Frank; Parisoli, Lidia; Roeth, Klaus-Dieter; Robinson, John C.; Jug, Sven; Izikson, Pavel; Dinu, Berta; Widmann, Amir; Choi, DongSub

    2010-03-01

    Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

  13. Development of a monolithic, multi-MEMS microsystem on a chip demonstrating iMEMS{trademark} VLSI technology. R and D status report number 10, January 1--March 31, 1996

    SciTech Connect

    1996-04-17

    This quarter saw the first silicon from the iMEMS{reg_sign} test chip, with complete circuits and beam structures. The wafers looked fine cosmetically and the circuits functioned as designed, but the beams suffered an anomaly that the authors have never seen before. Diagnostic work is under way to sort out the root cause, and other wafers are coming out this quarter to see if it was a one-time anomaly. Work on the process-development front has slowed because of the construction of a dedicated fabrication line for the last-generation process. With the current robust market place for ADI`s business, the existing fabrication line has been operating at 100% capacity. On the device front, great progress has been made by both Berkeley and ADI in the area of gyroscopes. Measurements of close to a degree per second or better have been made for gyros of all three axes and of both single- (linear) and double- (rotary) axis devices. In addition, ADI has designed a gyro that can be packaged in air that very well might meet some of the low-precision needs. Accelerometers of several new formats have been designed and several have been implemented in silicon. First samples of the ADXL 181 designed especially for the fuzing, safe and arming application have been assembled and are in characterization by ADI and others. In addition, 2-axis, Z-axis and digital output designs have been demonstrated. A 3-axis micro-watt accelerometer has been designed and is in fabrication. A 2-axis design for tilt applications is also nearing silicon realization. This portfolio of linear accelerometers, and even angular versions of the same provide, an arsenal of capability for specialized needs as they arise in both commercial and military applications.

  14. Time memory cell VLSI for the PHENIX drift chamber

    SciTech Connect

    Arai, Y.; Ikeno, M.; Sagara, M.; Emura, T.

    1998-06-01

    A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 {micro}sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 {micro}m CMOS gate-array technology.

  15. A new method of VLSI conform design for MOS cells

    NASA Astrophysics Data System (ADS)

    Schmidt, K. H.; Wach, W.; Mueller-Glaser, K. D.

    An automated method for the design of specialized SSI/LSI-level MOS cells suitable for incorporation in VLSI chips is described. The method uses the symbolic-layout features of the CABBAGE computer program (Hsueh, 1979; De Man et al., 1982), but restricted by a fixed grid system to facilitate compaction procedures. The techniques used are shown to significantly speed the processes of electrical design, layout, design verification, and description for subsequent CAD/CAM application. In the example presented, a 211-transistor, parallel-load, synchronous 4-bit up/down binary counter cell was designed in 9 days, as compared to 30 days for a manually-optimized-layout version and 3 days for a larger, less efficient cell designed by a programmable logic array; the cell areas were 0.36, 0.21, and 0.79 sq mm, respectively. The primary advantage of the method is seen in the extreme ease with which the cell design can be adapted to new parameters or design rules imposed by improvements in technology.

  16. A VLSI architecture for high performance CABAC encoding

    NASA Astrophysics Data System (ADS)

    Shojania, Hassan; Sudharsanan, Subramania

    2005-07-01

    One key technique for improving the coding e+/-ciency of H.264 video standard is the entropy coder, context- adaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is signicantly higher than the table driven entropy encoding schemes such as the Hu®man coding. CABAC is also bit serial and its multi-bit parallelization is extremely di+/-cult. For a high denition video encoder, multi-giga hertz RISC processors will be needed to implement the CABAC encoder. In this paper, we provide an e+/-cient, pipelined VLSI architecture for CABAC encoding along with an analysis of critical issues. The solution encodes a binary symbol every cycle. An FPGA implementation of the proposed scheme capable of 104 Mbps encoding rate and test results are presented. An ASIC synthesis and simulation for a 0.18 ¹m process technology indicates that the design is capable of encoding 190 million binary symbols per second using an area of 0.35 mm2. ¤

  17. A hierarchical approach to test generation for CMOS VLSI circuits

    NASA Astrophysics Data System (ADS)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  18. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  19. Wafer temperature measurement: Status utilizing optical fibers

    SciTech Connect

    Schietinger, C.; Jensen, E.

    1996-12-01

    This paper reviews the current status and problems of optical fiber temperature measurements for RTP and single wafer processing. Included is a discussion of a range of fiber based options available and currently being utilized today. The advantages and disadvantages of the options are presented. In addition new data from the use of the Ripple Technique pyrometer is presented. Included are data from AT and T (Lucent Technologies) ripple pyrometer development. Lucent Technologies is evaluating and improving the ripple pyrometer on a number of different style production RTP furnaces. Recent advances in signal processing for very low level photo diode currents in the range of 10 e-14 amps, also is presented.

  20. A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

    1986-01-01

    A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

  1. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    NASA Technical Reports Server (NTRS)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  2. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L.

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  3. Note: Near infrared interferometric silicon wafer metrology.

    PubMed

    Choi, M S; Park, H M; Joo, K N

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer. PMID:27131722

  4. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  5. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  6. VLSI digital demodulator co-processor

    NASA Astrophysics Data System (ADS)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  7. Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding

    NASA Astrophysics Data System (ADS)

    Beggans, Michael H.; Ivanov, Dentcho I.; Fu, Steven G.; Digges, Thomas G., III; Farmer, Kenneth R.

    1999-03-01

    A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been fabricated on 10 cm diameter, 500-micron thick, Pyrex glass wafers. The glass wafers have been micro-machined using ultrasonic drilling in order to form cavities, optical fiber feedthrough holes and vent holes. One of the main challenges of the manufacturing process is the handling of the ultra-thin silicon wafers. Being extremely flexible, the thin silicon wafers cannot be cleaned, oxidized, or dried in the same way as normal since wafers with a thickness of the order of 400 microns. Specific handling techniques have been developed in order to achieve reproducible cleaning and oxidation processes. The anodic bonding was performed using an Electronic Visions EV501S bonder. The wafers were heated at 420 degrees C and a voltage of 1200 volts was applied in vacuum of 10-5 Torr. The bonded wafer stack was then fixed in a wax and diced. The resulting chips have been used to fabricate operating pressure sensors.

  8. On testing VLSI chips for the big Viterbi decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.

    1989-01-01

    A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

  9. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  10. A VLSI implementation for synthetic aperture radar image processing

    NASA Technical Reports Server (NTRS)

    Premkumar, A.; Purviance, J.

    1990-01-01

    A simple physical model for the Synthetic Aperture Radar (SAR) is presented. This model explains the one dimensional and two dimensional nature of the received SAR signal in the range and azimuth directions. A time domain correlator, its algorithm, and features are explained. The correlator is ideally suited for VLSI implementation. A real time SAR architecture using these correlators is proposed. In the proposed architecture, the received SAR data is processed using one dimensional correlators for determining the range while two dimensional correlators are used to determine the azimuth of a target. The architecture uses only three different types of custom VLSI chips and a small amount of memory.

  11. A single chip VLSI Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Hsu, I. S.; Deutsch, L. J.; Reed, I. S.

    1986-01-01

    A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a time domain algorithm. A new architecture that implements such an algorithm permits efficient pipeline processing with minimum circuitry. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclid's algorithm is implemented by a new architecture that maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and a significant reduction in silicon area, therefore making it possible to build a pipeline (31,15)RS decoder on a single VLSI chip.

  12. Architecture for VLSI design of Reed-Solomon encoders

    NASA Technical Reports Server (NTRS)

    Liu, K. Y.

    1982-01-01

    A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

  13. NASA Space Engineering Research Center for VLSI systems design

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  14. A radial basis function neurocomputer implemented with analog VLSI circuits

    NASA Technical Reports Server (NTRS)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  15. VLSI architecture for computer vision based on neurobiological principles of organization

    SciTech Connect

    Ginosar, R.; Zeevi, Y.Y.

    1988-09-01

    Biological and technological (wide-field-of-view) vision systems are confronted with the formidable task of managing data sets at a rate in excess of 10/sup 0/10 bits per second. In both cases, however, considering the required tasks, it appears that the data are highly redundant, and therefore must be reorganized before any type of higher level processing is applied to them. Reorganizations may include compression, and dimensional reduction according to the various relevant parameters. Biological processing at both the retinal and cortical levels often consists of repetitive simple operations applied to spatial and/or temporal neighborhoods, limited in their extend and duration. These are most adequate for the very high image data rates, in spite of the fact that those neurobiological systems actually consists of simple components which are several orders of magnitude slower than electronic components. It is the authors' goal to follow biological algorithms and principles of organization in the design of VLSI architectures, and to achieve similar or better performance in image processing and machine vision. Their efforts have yielded the following families of VLSI devices and systems. A highly parallel Intelligent Scan Image Acquisition VLSI sensing device has been constructed. It selectively scans only the relevant areas of interest in each image, thus effectively providing a compressed image for later processing stages. The device is controlled by an algorithm which is highly sensitive to image content. This sensor imitates the capability of the eye to concentrate on (attend) certain parts of the image, and even extends this by processing multiple focal points simultaneously. This is an example of how we applied the nonuniform sample-and-process algorithm, characteristic of biological vision, in a highly parallel architecture which surpasses the performance of the human eye.

  16. Wafer sampling by regression for systematic wafer variation detection

    NASA Astrophysics Data System (ADS)

    Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

    2005-05-01

    In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

  17. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L.

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  18. Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

    2015-04-01

    In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

  19. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  20. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  1. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  2. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  3. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  4. VLSI implementation of a reduced symmetric fuzzy singleton set

    NASA Astrophysics Data System (ADS)

    Chang, Yi-Chieh; Wu, Kung C.

    1993-08-01

    A fuzzy logic controller (FLC) has been proposed and implemented in many control systems to deliver smooth and more reliable outputs than the traditional control systems. In most of the existing VLSI FLC chips, the architectures are based on general purpose microcontroller structure tailored to fuzzy logic implementation. The drawbacks in these types of FLC VLSI chips are low speed, high cost, and long design time. Moreover, an expensive development system is also needed to program a general purpose microcontroller for a specific fuzzy logic control system. In order to alleviate the drawbacks in existing VLSI fuzzy logic circuits, a reduced symmetric fuzzy singleton set (RSFSS) is proposed in this paper. The proposed RSFSS system can handle three input variables, nine rules for each input variable, and produces two output values. Each rule is based on a symmetric triangular membership function. The triangular membership functions of each state variable are defined symmetrically with respect to the centroid of the universe of discourse. Since the hardware complexity is greatly reduced, the entire FLC based on the RSFS structure can be implemented on a VLSI chip with a dimension of 2.22 mm X 2.22 mm.

  5. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  6. Hybrid VLSI/QCA Architecture for Computing FFTs

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  7. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    ERIC Educational Resources Information Center

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  8. A special purpose silicon compiler for designing supercomputing VLSI systems

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  9. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  10. A multi coding technique to reduce transition activity in VLSI circuits

    NASA Astrophysics Data System (ADS)

    Vithyalakshmi, N.; Rajaram, M.

    2014-02-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.

  11. The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Shao, H. M.; Deutsch, L. J.

    1987-01-01

    The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions.

  12. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  13. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  14. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  15. Mask qualification strategies in a wafer fab

    NASA Astrophysics Data System (ADS)

    Jaehnert, Carmen; Kunowski, Angela

    2007-02-01

    Having consistent high quality photo masks is one of the key factors in lithography in the wafer fab. Combined with stable exposure- and resist processes, it ensures yield increases in production and fast learning cycles for technology development and design evaluation. Preventive controlling of incoming masks and quality monitoring while using the mask in production is essential for the fab to avoid yield loss or technical problems caused by mask issues, which eventually result in delivery problems to the customer. In this paper an overview of the procedures used for mask qualification and production release, for both logic and DRAM, at Infineon Dresden is presented. Incoming qualification procedures, such as specification checks, incoming inspection, and inline litho process window evaluation, are described here. Pinching and electrical tests, including compatibility tests for mask copies for high volume products on optimized litho processes, are also explained. To avoid mask degradation over lifetime, re-inspection checks are done for re-qualification while using the mask in production. The necessity of mask incoming inspection and re-qualification, due to the repeater printing from either the processing defects of the original mask or degrading defects of being used in the fab (i.e. haze, ESD, and moving particles, etc.), is demonstrated. The need and impact of tight mask specifications, such as CD uniformity signatures and corresponding electrical results, are shown with examples of mask-wafer CD correlation.

  16. Deposition uniformity inspection in IC wafer surface

    NASA Astrophysics Data System (ADS)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  17. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  18. Noise-margin limitations on gallium-arsenide VLSI

    NASA Technical Reports Server (NTRS)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  19. A novel 3D algorithm for VLSI floorplanning

    NASA Astrophysics Data System (ADS)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  20. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H. ); Johns, K. . Dept. of Physics)

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers.

  1. Drift chamber tracking with a VLSI neural network

    SciTech Connect

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We`ll briefly discuss possible applications in high energy physics detector triggers.

  2. A VLSI design of a pipeline Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1985-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  3. Data path design considerations for a high performance VLSI multiprocessor

    SciTech Connect

    Lee, D.

    1987-01-01

    A VLSI data path implementation for the SPUR (Symbolic Processing Using RISCs) processor is presented. There are many tradeoffs to be considered in the design of a microprocessor data path. Often, these tradeoffs are interrelated and thus increase the complexity of the design. This report focuses on the design of the CMOS data path with the tradeoffs considered throughout the implementation of the data path for the SPUR CPU.

  4. Radiation hardness and annealing tests of a custom VLSI device

    SciTech Connect

    Breakstone, A.; Parker, S.; Adolphsen, C.; Litke, A.; Schwarz, A.; Turala, M.; Lueth, V.; California Univ., Santa Cruz, CA . Inst. for Particle Physics; Stanford Linear Accelerator Center, Menlo Park, CA )

    1986-10-01

    Several NMOS custom VLSI ( Microplex'') circuits have been irradiated with a 500 rad/hr {sup 60}Co source. With power off three of four chips tested have survived doses exceeding 1 Mrad. With power on at a 25% duty cycle, all chips tested failed at doses ranging from 10 to 130 krad. Annealing at 200{degree}C was only partially successful in restoring the chips to useful operating conditions. 10 refs., 4 figs., 1 tab.

  5. Handshake circuits: An intermediary between communicating processes and VLSI

    NASA Astrophysics Data System (ADS)

    Vanberkel, Cornelis Hermanus

    Tangram and handshake circuits are introduced. The cost and performance of the circuits is the primary concern, as they make Very Large Scale Integration (VLSI) programming different from (and also more difficult than) traditional computer programming. The theory for handshake circuits makes up the body of the thesis. The key motion is that of the handshake process. A handshake process is a mathematical object that describes a handshake communication behavior. This handshake behavior may be that of the components of a handshake circuit. A handshake circuit is a set of handshake processes that satisfy a simple compositional rule. The behavior of the handshake circuit is defined through parallel composition of its constituents components and is, again, a handshake process. In appendix A, the delay insensitivity of handshake circuits is related to the theory reported in the literature. A calculus for handshake processes is developed. This calculus allows concise descriptions of behaviors of handshake components. A precise definition of Tangram is given. For a subset of Tangram, which we call Core Tangram, a formal denotation 'H' is given in terms of handshake processes. In appendix B, a link to the well known failure semantics of CSP (Communication Sequential Processes) is established. The translation of Tangram programs into handshake circuits by means of the mathematical function 'C' is described. For Core Tangram it is proven that the behavior of the compiled handshake circuit is equivalent to that of the original program in a well defined sense. The realization of handshake circuits in VLSI is considered. Issues such as peephole optimization, handshake refinement, data encoding, decompositions into VLSI operator networks, initialization, and testing are discussed. VLSI programming and silicon compilation are discussed.

  6. Platinum-coated probes sliding at up to 100 mm s-1 against coated silicon wafers for AFM probe-based recording technology

    NASA Astrophysics Data System (ADS)

    Bhushan, Bharat; Kwak, Kwang Joo

    2007-08-01

    One of the new alternative information storage technologies being researched is based on the probe-based recording technique. In one technique, a phase-change medium is used, and the phase change is accomplished by applying either a high or low magnitude of current which heats the interface to different temperatures. Tip wear is a serious concern. For wear protection of the phase-change chalcogenide medium with a silicon substrate, diamond-like carbon (DLC) film with various lubricant overcoats was deposited on the recording layer surface. Nanowear properties of platinum (Pt)-coated probes with high electrical conductivity have been investigated in sliding against the coated medium using an atomic force microscope (AFM). A silicon grating sample and software to deconvolute tip shape were used to characterize the change in the tip shape and evaluate the tip radius and its wear volume. The nanowear experiments were performed at sliding velocities ranging from 0.1 to 100 mm s-1. Pt-coated tips on the lubricant-coated DLC film surfaces showed less sensitivity to the velocity and the load as compared to the unlubricated DLC film surfaces. In wear life threshold experiments, the threshold reaches a smaller sliding distance at higher loads. In high-temperature experiments at 80 °C, the wear rate is higher compared to that at 20 °C. The results suggest that the wear mechanism at low velocity appears to be primarily adhesive and abrasive. At high velocity, an additional wear mechanism of the tribochemical reaction is important.

  7. ULYSSES - an expert-system-based VLSI design environment

    SciTech Connect

    Bushnell, M.L.

    1987-01-01

    Ulysses is a VLSI computer-aided design (CAD) environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation (DA) system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An integrated-circuit silicon compilation task is presented as an example of the ability of Ulysses to automatically execute CAD tools to solve a problem where inferencing is required to obtain a viable VLSI layout. The inferencing mechanism, in the form of a controlled production system, allows Ulysses to recover when routing channel congestion or over-constrained leaf-cell boundary conditions make it impossible for CAD tools to complete layouts. Also, Ulysses allows the designer to intervene while design activities are being carried out. Consistency-maintenance rules encoded in the scripts language enforce geometric floor-plan consistency when CAD tools fail and when the designer makes adjustments to a VLSI chip layout.

  8. Fault sensitivity and wear-out analysis of VLSI systems

    NASA Astrophysics Data System (ADS)

    Choi, Gwan Seung

    1994-07-01

    This thesis describes simulation approaches to conduct fault sensitivity and wear-out failure analysis of VLSI systems. A fault-injection approach to study transient impact in VLSI systems is developed. Through simulated fault injection at the device level and, subsequent fault propagation at the gate functional and software levels, it is possible to identify critical bottlenecks in dependability. Techniques to speed up the fault simulation and to perform statistical analysis of fault-impact are developed. A wear-out simulation environment is also developed to closely mimic dynamic sequences of wear-out events in a device through time, to localize weak location/aspect of target chip and to allow generation of TTF (Time-to-failure) distribution of VLSI chip as a whole. First, an accurate simulation of a target chip and its application code is performed to acquire trace data (real workload) on switch activity. Then, using this switch activity information, wear-out of the each component in the entire chip is simulated using Monte Carlo techniques.

  9. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards. [Very Large Scale Integration (VLSI)

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-01-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using human-like'' reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver's aid using the new fuzzy inferencing VLSI hardware and human-like'' reasoning schemes.

  10. New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level

    NASA Astrophysics Data System (ADS)

    Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

    2013-03-01

    For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces

  11. A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT

    NASA Astrophysics Data System (ADS)

    Liu, Kai; Li, YunSong; Belyaev, Eugeniy

    2010-08-01

    The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

  12. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    NASA Astrophysics Data System (ADS)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  13. A two-dimensional analog VLSI circuit for detecting discontinuities in early vision.

    PubMed

    Harris, J G; Koch, C; Luo, J

    1990-06-01

    A large number of computer vision algorithms for finding intensity edges, computing motion, depth, and color, and recovering the three-dimensional shape of objects have been developed within the framework of minimizing an associated "energy" or "cost" functional. Particularly successful has been the introduction of binary variables coding for discontinuities in intensity, optical flow field, depth, and other variables, allowing image segmentation to occur in these modalities. The associated nonconvex variational functionals can be mapped onto analog, resistive networks, such that the stationary voltage distribution in the network corresponds to a minimum of the functional. The performance of an experimental analog very-large-scale integration (VLSI) circuit implementing the nonlinear resistive network for the problem of two-dimensional surface interpolation in the presence of discontinuities is demonstrated; this circuit is implemented in complementary metal oxide semiconductor technology.

  14. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    ERIC Educational Resources Information Center

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  15. Fast-ramp rapid vertical processor for 300-mm Si wafer processing

    NASA Astrophysics Data System (ADS)

    Porter, Cole; Laser, Allan; Herring, Robert; Pandey, Pradeep

    1998-09-01

    Fast-ramp vertical furnace technology has been established on the 200-nm wafer platform providing higher capacity production, decreased cycle time and lower thermal budgets. Fast-ramp furnaces are capable of instantaneous temperature ramp rates up to 100 degrees C/min. This fast-ramp technology is now applied to 300-nm wafer processing on the SVG/Thermco Rapid Vertical Processor Vertical Furnace. 300- mm fast-ramp capability using the latest in real-time adaptive model based temperature control technology, Clairvoyant Control, is reported. Atmospheric Thermal Oxidation, LPCVD Nitride and Polysilicon Deposition, and LPCVD TEOS-based SiO2 Deposition results are discussed. 300- mm wafer Radial Delta Temperature dependence on temperature ramp rate, wafer pitch, and wafer support fixtures are discussed. Wafer throughput is calculated and reported. The Clairvoyant Control methodology of combining thermal, direct and virtually-sensed parameters to produce real-tim e estimation of wafer temperatures, thermal trajectory optimization, and feedback to minimize variations in film thickness and electrical properties is presented.

  16. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle

  17. Phase shift reflectometry for wafer inspection

    NASA Astrophysics Data System (ADS)

    Peng, Kuang; Cao, Yiping; Li, Hongru; Sun, Jianfei; Bourgade, Thomas; Asundi, Anand Krishna

    2015-07-01

    In 3D measurement, specular surfaces can be reconstructed by phase shift reflectometry and the system configuration is simple. In this paper, a wafer is measured for industrial inspection to make sure the quality of the wafer by calibrating, phase unwrapping, slope calculation and integration. The profile result of the whole wafer can be reconstructed and it is a curve. As the height of the structures on the wafer is the target we are interested in, by fitting and subtracting the curve surface, the structures on the wafer can be observed on the flat surface. To confirm the quality farther, a part of the wafer is captured and zoomed in to be detected so that the difference between two structures can be observed better.

  18. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  19. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  20. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  1. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  2. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  3. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  4. Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

    NASA Astrophysics Data System (ADS)

    Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

    2003-07-01

    In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

  5. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  6. CR-1 Chip: Custom VLSI Circuitry for Cosmic Rays

    NASA Astrophysics Data System (ADS)

    Adams, James

    This paper describes a custom VLSI chip developed for use with large arrays of silicon detectors in cosmic ray experiments. It provides 16 channels of front-end electronics for integrating the charge pulse from silicon detectors and present the result as a held DC level. The outputs are multiplexed onto a common output line. The chip also has circuitry for calibration pulse injection into each channel. The noise is low enough to clearly distinguish minimum ionizing proton signals while the dynamic range of 1:4000 allows all charges from H to Fe to be measured even at large angles. The nominal power consumption is < 5.4 mW/channel.

  7. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    NASA Technical Reports Server (NTRS)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  8. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices

    NASA Astrophysics Data System (ADS)

    Kim, Dae Jong; Yoo, Hyung Won; Kim, Chul Hong; Lee, Hak Kwon; Kim, Sung Su; Bae, Koon Ho; Spielberg, Hedvi; Lee, Yun Ho; Levi, Shimon; Bustan, Yariv; Rozentsvige, Moshe

    2010-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values

  9. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  10. Cryogenic wafer prober for Josephson devices

    SciTech Connect

    Geary, J.; Vella-Coleiro, G.

    1983-05-01

    A wafer probing system has been built for the testing of Josephson junction devices at helium temperature. A mechanism moves a probe card from one position to another on a two inch wafer while immersed in liquid helium. The mechanism is actuated by shafts which connect to stepper motors positioned above the helium dewar. A positioning accuracy of + or - 50 ..mu..m at the probe tips is achieved. The replaceable probe card is all ceramic and carries 120 rigidly mounted palladium-alloy needles, arranged in signal-ground pairs and positioned in an array which matches the pad design of the particular device under test. Controlled impedance transmission lines are maintained all the way to the wafer's surface. A computer interface is included so that probing of a whole wafer can be conducted under software control. The system is intended for routine testing of Josephson devices in wafer form as well as for testing very large numbers of individual junctions.

  11. Models to relate wafer geometry measurements to in-plane distortion of wafers

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Vukkadala, Pradeep; Sinha, Jaydeep K.

    2016-04-01

    Achieving satisfactory overlay is increasingly challenging as feature sizes are reduced and allowable overlay budgets shrink to several nanometers and below. Overlay errors induced by wafer processing, such as film deposition and etching, constitute a meaningful fraction of overlay budgets. Wafer geometry measurements provide the opportunity to quantify stress-induced distortions at the wafer level and provide information that can be used in a feedback mode to alter wafer processing or in a feed-forward mode to set wafer-specific corrections in the lithography tool. In order for such feed-forward schemes based on wafer geometry to be realized, there is a need for mechanics models that relate in-plane distortion of a chucked wafer to the out-of-plane distortion of a wafer in a free state. Here, a simple analytical model is presented that shows the stress-induced component of overlay is correlated to a corrected local wafer slope metric for a wide range of cases. The analytical model is validated via finite element (FE) simulations of wafers with nonuniform stress distributions. Furthermore, FE modeling is used here to examine the effect of the spatial wavelength of stress variation on the connection between slope and the wafer stress-induced component of overlay.

  12. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to

  13. Qualification procedures for VHSIC/VLSI

    NASA Astrophysics Data System (ADS)

    Baumes, Thomas A.

    1990-12-01

    This program developed, outlined, refined, and verified the test methodology and qualification criteria and procedures to be used to ensure the integrity and reliability of microcircuit devices designed for insertion into military systems. A major portion of the criteria and procedures, reflected herein, enables a significant reduction in time and cost of the microcircuit Quality/Reliability Assurance process by addressing up front simulations during design prior to commitment, complex and expensive manufacturing processes with in-line quality processes controlled by a SPC (Statistical Process Control) program and ongoing QA Program using their TRB (Technology Review Board) and SEC (Standard Evaluation Circuit) programs.

  14. SCALX: A VLSI architecture for concurrent symbolic processing

    SciTech Connect

    Shiue, L.C.

    1989-01-01

    A VLSI architecture intended for concurrent symbolic processing is presented. The approach starts with developing a hardware model for on-chip knowledge acquisition and works progressively towards the architectural basis. The model concepts, while formally conceived from neural network theory, do not target physiological modeling. Instead, the goal is to help develop autonomous systems that can make intelligent decisions on a real time basis. With this model, the knowledge is first represented by conceptual digraphs that in turn are stored into a reconfigurable perceptron-like network in which each node is a Boolean McCulloch-Pitts neuron. For on-chip knowledge representation, two methods are presented which directly map digraphs onto silicon. For inference, a computational approach is developed by which knowledge deduction and search processes are resorted to matrix and/or vector operations. A few algorithms which are specifically designed to implement the high speed search operations based on index-driven and value-driven systolic arrays are presented. These algorithms are analyzed in terms of time and space requirements. It is also shown that the index-driven systolic processing architecture can effectively solve the sparse matrix computation problem. Based on the computational model and the systolic design methodology, an array processor architecture suitable for VLSI implementation is developed. A hierarchical network simulator, encoded in C under VAX-8650, is also developed. This simulator is comprised of a conceptual digraph interpreter and a functional emulator for an application specific microprocessor, named SCALX 8900.

  15. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    NASA Technical Reports Server (NTRS)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  16. Development of Radhard VLSI electronics for SSC calorimeters

    SciTech Connect

    Dawson, J.W.; Nodulman, L.J.

    1989-01-01

    A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs.

  17. A fast neural-network algorithm for VLSI cell placement.

    PubMed

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  18. Efficient VLSI architecture for multi-dimensional discrete wavelet transform

    NASA Astrophysics Data System (ADS)

    Xiong, Cheng-Yi; Tian, Jin-Wen; Liu, Jian

    2005-10-01

    Efficient VLSI architectures for multi-dimensional (m-D) discrete wavelet transform (DWT), e.g. m=2, 3, are presented, in which the lifting scheme of DWT is used to reduce efficiently hardware complexity. The parallelism of 2m subbands transforms in lifting-based m-D DWT is explored, which increases efficiently the throughput rate of separable m-D DWT. The proposed architecture is composed of m2m-1 1-D DWT modules working in parallel and pipelined, which is designed to process 2m input samples per clock cycle, and generate 2m subbands coefficients synchronously. The total time of computing one level of decomposition for a 2-D image (3-D image sequence) of size N2 (MN2) is approximately N2/4 (MN2/8) intra- clock cycles (ccs). An efficient line-based architecture framework for both 2D+t and t+2D 3-D DWT is first proposed. Compared with the similar works reported in previous literature, the proposed architecture has good performance in terms of production of computation time and hardware cost. The proposed architecture is simple, regular, scalable and well suited for VLSI implementation.

  19. New VLSI complexity results for threshold gate comparison

    SciTech Connect

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  20. A silicon wafer packaging solution for HB-LEDs

    NASA Astrophysics Data System (ADS)

    Murphy, Tom; Weichel, Steen; Isaacs, Steven; Kuhmann, Jochen

    2007-09-01

    In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone/colour conversion substance. The base material, silicon, has excellent mechanical and thermal properties and enables direct integration of intelligence. We present customer specific solutions, open tool samples and performance data for optical and thermal parameters and reliability testing. Thermal resistance values of R<5 K/W, junction-to-board are demonstrated.

  1. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    SciTech Connect

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.

  2. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE PAGES

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; Castellanos, Sergio; Buonassisi, Tonio

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  3. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  4. Parallel VLSI architecture emulation and the organization of APSA/MPP

    NASA Technical Reports Server (NTRS)

    Odonnell, John T.

    1987-01-01

    The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

  5. The VLSI design of a single chip Reed-Solomon encoder

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Deutsch, L. J.; Reed, I. S.

    1982-01-01

    A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.

  6. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  7. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  8. Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

    NASA Technical Reports Server (NTRS)

    Aanstoos, J. V.; Snyder, W. E.

    1981-01-01

    Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort.

  9. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  10. VLSI-based video event triggering for image data compression

    NASA Astrophysics Data System (ADS)

    Williams, Glenn L.

    1994-02-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  11. Distributed predetection of moving point targets with analog VLSI

    NASA Astrophysics Data System (ADS)

    Bartolac, Thomas J.

    1992-07-01

    When large-field IR sensors are quite distant from the scene, targets appear as points, so detection is based on their motion, rather than their structure. The appearance of background and clutter bright points, although eventually rejected as nontargets, unnecessarily burdens tracking algorithms. Typical approaches involve eliminating background prior to tracking, or only looking within dynamic search boxes based on previous-frame target observations. This presentation describes a method for distributed predetection of points due to moving targets, in which background points are be automatically rejected, and only those detector returns that are most likely to be from targets are be provided to the tracking algorithm. The paper discusses the retinally inspired concepts behind the proposed method, analytical and empirical evaluations of its performance, and a hardware implementation based on Mead's (1989) analog VLSI circuits, resulting in a fine-grained-parallel architecture suitable for on-focal-plane applications.

  12. Aspects of full-custom VLSI microprocessor design and implementation

    SciTech Connect

    Lee, Daebum.

    1989-01-01

    There is a broad spectrum of design styles that have proven successful for the construction of VLSI circuits and systems. Semi-custom to full-custom design styles offer a wide range of resulting performance, expected turn-around time, and required design effort. Implementation alternatives, such as replacing dynamic memory for static memory to implement a denser on-chip memory, also exist at all levels of design hierarchy. To make the best use of scarce resources on a single chip microprocessor and to make the emerging CAD tools truly useful, alternatives in the implementation of a microprocessor must be carefully evaluated. The research reported in this thesis focuses on issues concerning these alternatives, especially in the areas of on-chip memory design and automated control logic design.

  13. VLSI-based Video Event Triggering for Image Data Compression

    NASA Technical Reports Server (NTRS)

    Williams, Glenn L.

    1994-01-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  14. Efficient VLSI Architecture for Training Radial Basis Function Networks

    PubMed Central

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  15. Efficient VLSI architecture for training radial basis function networks.

    PubMed

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  16. Analyzes Data from Semiconductor Wafers

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  17. Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.

    PubMed

    Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

    2000-10-01

    We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are

  18. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  19. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  20. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the

  1. Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling

    NASA Astrophysics Data System (ADS)

    Choi, Young Sin; Nam, Young Sun; Lee, Dong Han; Lee, Jae Il; Kang, Young Seog; Jang, Se Yeon; Kong, Jeong Heung

    2016-03-01

    As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry's preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement. In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer's behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

  2. Submicron X-Ray Replication Technology For Early Application

    NASA Astrophysics Data System (ADS)

    Fencil, C. R.; Hughes, G. P.

    1983-11-01

    First-generation, full-wafer exposure, X-ray lithography equipment has been in continuous operation since 1979 in a pilot line application.(1,2,3) Second-generation, full-wafer exposure systems that incorporate the latest advancements in X-ray lithography are now being developed for early, submicron, VLSI patterning. This paper discusses recent advances in E-beam gun design and high-speed rotating anode development in terms of X-ray lithographic performances such as resolution and image contrast. In addition, the performance of a physical optics alignment technique that is compatible with submicron IC pattern overlay requirements is reported. The Perkin-Elmer X-100 full-wafer exposure system is a valuable development tool because of its flexibility. It is compatible with all X-ray masks and resists and can be used to expose either 75 mm or 100 mm diameter wafers.

  3. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  4. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture

  5. High-performance VLSI architectures for turbo decoders with QPP interleaver

    NASA Astrophysics Data System (ADS)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  6. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    NASA Astrophysics Data System (ADS)

    Bellazzini, R.; Angelini, F.; Baldini, L.; Bitti, F.; Brez, A.; Ceccanti, M.; Latronico, L.; Massai, M. M.; Minuti, M.; Omodei, N.; Razzano, M.; Sgro, C.; Spandre, G.; Costa, E.; Soffitta, P.

    2004-12-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of integration and resolution typical of solid state pixel detectors. Results from the first tests of this new read-out concept are presented. An Astronomical X-Ray Polarimetry application is also discussed.

  7. Investigation of VLSI Bipolar Transistors Irradiated with Electrons, Ions and Neutrons for Space Application

    NASA Astrophysics Data System (ADS)

    D'Angelo, P.; Fallica, G.; Galbiati, A.; Mangoni, R.; Modica, R.; Pensotti, S.; Rancoita, P. G.

    2006-04-01

    A systematic investigation of radiation effects on a BICMOS technology manufactured by STM has been undertaken. Bipolar transistors were irradiated by neutrons, C, Ar and Kr ions, and recently by electrons. Fast neutrons, as well as other types of particles, produce defects mainly by displacing silicon atoms from their lattice positions to interstitial locations, i.e. generating vacancy-interstitial pairs (the so-called Frenkel pairs). Although imparted doses differ largely, the experimental results indicate that the gain (β) variation is mostly related to the non-ionizing energy-loss (NIEL) deposition for neutrons, ions and electrons. The variation of the inverse of the gain degradation, Δ(1/β), is found to be linearly related (as predicted by the Messenger-Spratt equation for neutron irradiations) to the concentrations of the Frenkel pairs generated independently of the kind of incoming particle. For space applications, this linear dependence on the concentration of Frenkel pairs allows to evaluate the total amount of the gain degradation of VLSI components due to the flux of charged particles during the full life of operation of any pay-load. In fact, the total amount of expected Frenkel pairs can be estimated taking into account the isotopic spectra. It has to be point out that in cosmic rays there is relevant flux of electrons and isotopes up to Ni, which are within the range of particles presently investigated.

  8. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    NASA Astrophysics Data System (ADS)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  9. Design and implementation of moment invariants for pattern recognition in VLSI

    NASA Astrophysics Data System (ADS)

    Armstrong, Gary A.; Simpson, Marc L.; Bouldin, Donald W.

    1990-09-01

    This paper describes the design of a very large scale integration (VLSI) application specific integrated circuit (ASIC) for use in pattern recognition. The pattern recognition scheme uses Hu1 and Mailra''s2 algorithms for moment invariants. A prototype design was generated that resolved the long delay time of the multiplier by custom designing adder cells based on the Manchester carry chain. Use of the Manchester carry chain effectively incorporated the lookahead carry function into the adder cells. The prototype ASIC is currently being fabricated in 2. 0-mm compiled simulator for metal oxide semiconductor (CMOS) technology (simulated at 20 MHz). The prototype consisted of a 4x8 multiplier and a 12-bit accumulator stage. The present ASIC design consists of a 9x26 multiplier (maximum propagation time of 50 ns) and a 48-bit accumulator stage. The final ASICs will be used in parallel at the board level to achieve the 56 MegaPixels/s [230 million operations per second (MOPs)] necessary to perform the moment invariant algorithms in real time on 512x512 pixel images with 256 grey scales. 2.

  10. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  11. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  12. Semiconducting wafer form shaping with an electric discharge machine

    NASA Astrophysics Data System (ADS)

    Yang, Yu-Tung

    1988-09-01

    Gallium can be used as a temporary glue for semiconducting wafer mounting. The good electric contact between the electrode, the gallium layer, and the semiconducting wafer makes the spark cutting and the semiconducting wafer form shaping much easier. After wafer spark cutting, the residual gallium can be easily removed by a cotton swab from the surface of the wafer in warm isopropyl alcohol (IPA). Also, in this report, improved circuitry of the electric discharge machine for easy and economical construction is described. Gallium arsenide wafers have been form shaped by the present method.

  13. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease

    PubMed Central

    Niu, Chuanxin M.; Nandyala, Sirish K.; Sanger, Terence D.

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin–Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems. PMID:25538613

  14. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  15. Simulation Study on Quantum Capacitances of Graphene Nanoribbon VLSI Interconnects

    NASA Astrophysics Data System (ADS)

    Dutta, Arin; Rahman, Silvia; Nandy, Turja; Mahmood, Zahid Hasan

    2016-03-01

    In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1-5V. Then, the total capacitance of GNR is studied as a function of gate voltage of -2-5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.

  16. A VLSI decomposition of the deBruijn graph

    NASA Technical Reports Server (NTRS)

    Collins, O.; Dolinar, S.; Mceliece, R.; Pollara, F.

    1990-01-01

    A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

  17. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    PubMed

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system. PMID:17385639

  18. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  19. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  20. Bubble-domain circuit wafer evaluation coil set

    NASA Technical Reports Server (NTRS)

    Chen, T. T.; Williams, J. L.

    1975-01-01

    Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

  1. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  2. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    NASA Technical Reports Server (NTRS)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  3. Effective Memetic Algorithms for VLSI design = Genetic Algorithms + local search + multi-level clustering.

    PubMed

    Areibi, Shawki; Yang, Zhen

    2004-01-01

    Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem. PMID:15355604

  4. Effective Memetic Algorithms for VLSI design = Genetic Algorithms + local search + multi-level clustering.

    PubMed

    Areibi, Shawki; Yang, Zhen

    2004-01-01

    Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem.

  5. Advanced technologies for Mission Control Centers

    NASA Technical Reports Server (NTRS)

    Dalton, John T.; Hughes, Peter M.

    1991-01-01

    Advance technologies for Mission Control Centers are presented in the form of the viewgraphs. The following subject areas are covered: technology needs; current technology efforts at GSFC (human-machine interface development, object oriented software development, expert systems, knowledge-based software engineering environments, and high performance VLSI telemetry systems); and test beds.

  6. First thin AC-coupled silicon strip sensors on 8-inch wafers

    NASA Astrophysics Data System (ADS)

    Bergauer, T.; Dragicevic, M.; König, A.; Hacker, J.; Bartl, U.

    2016-09-01

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  7. Dynamic opto-VLSI lens and lenslet generation with programmable focal length

    NASA Astrophysics Data System (ADS)

    Wang, Zhenglin; Alameh, Kamal E.; Zheng, Rong; Ahderom, Selam

    2004-12-01

    In this paper we present and demonstrate a dynamic lens and lens array generation method with programmable focal length based on an Opto-VLSI processor. The Opto-VLSI is driven by computer generated algorithm to generate a discrete Fresnel lens phase hologram. By optimizing the phase hologram, lenses and lens arrays of different focal lengths ranging from 300mm to infinity can be realized. The optical axis of each lens element can be independently addressed to simultaneously focus and steer an optical beam within an angular range of +/-0.5°.

  8. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, Howard M.; Reed, Irving S.

    1988-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  9. On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Deutsch, L. J.; Reed, I. S.

    1987-01-01

    A new very large scale integration (VLSI) design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area.

  10. A procedural method for the efficient implementation of full-custom VLSI designs

    NASA Technical Reports Server (NTRS)

    Belk, P.; Hickey, N.

    1987-01-01

    An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system.

  11. Crystal defects in silicon integrated circuits with respect to very large scale integration (VLSI)

    NASA Astrophysics Data System (ADS)

    Franz, G.; Kolbesen, B.

    1982-04-01

    The impact of process induced crystal defects on single bit refresh loss in dynamic MOS memory devices (bipolar and MOS technology) was investigated. Analytical techniques for detection of crystal defects were preferential etching, X-ray topography, and high voltage electron microscopy. Impurity levels were determined by infrared spectroscopy (carbon and oxygen) and neutron activation analysis (metals). Device characteristics and measurements of the MOS relaxation time were utilized as electrical results for quality control. Nuclei, sources and driving forces were analyzed, correlated to special technology steps, and measures for elimination were determined. Results show that metallic impurities introduced during wafer processing influence the generation as well as the electrical activity of crystal defects. The gettering ability of defects, due to the precipitation of oxygen in liquid (CZ) silicon, is explained.

  12. Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

    NASA Astrophysics Data System (ADS)

    Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

    2001-07-01

    The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

  13. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  14. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  15. Wafer-scale fabrication of penetrating neural microelectrode arrays

    NASA Astrophysics Data System (ADS)

    Bhandari, Rajmohan

    In order to have an efficient neural interface, uniformity and predictability of electrodes electrical, and mechanical characteristics are desired. Furthermore, the electrodes should have small active sites to selectively record or stimulate neural signals. Also, there should be close geometrical match between the electrode array and the targeted tissue for long-term stability. Currently the Utah electrode array (UEA) is in either constant electrode length (UEA) or varying length configurations (Utah slant electrode array: USEA). The current processes used to fabricate the UEAs impose limitations in the tolerances of the electrode array geometry. Furthermore, the flat architecture of the UEA and convoluted geometry of the targeted tissue results in poor coupling between the two "mating" surfaces, leading in active electrode tips that are not in proximity to the neuronal tissue. Therefore, a robust, flexible and high precision fabrication technology is needed that can produce (a) uniformly shaped microelectrodes (b) small and uniformly exposed active tip sites and (c) convoluted electrode arrays for better geometrical match. This dissertation presents a wafer-scale fabrication process for both the UEA and the USEA. A wafer-scale etching method has been developed and optimum etching conditions are established to achieve uniform shape electrode arrays. Also, the etching rate of silicon columns, produced by dicing, is studied as a function of temperature, etching time and stirring rate in the acid solution. Furthermore, a novel photoresist based masking technique for procuring extremely small active area has been developed on wafer-scale. In this technique, the tip exposure is controlled by varying the spin speed during photoresist coating. The technique allows fabrication of uniformly exposed tip lengths, over a range of 30 to 350 microm in length. Lastly, a novel array fabrication technique is developed for building a variety of neural interface devices having

  16. A fast lightstripe rangefinding system with smart VLSI sensor

    NASA Technical Reports Server (NTRS)

    Gruss, Andrew; Carley, L. Richard; Kanade, Takeo

    1989-01-01

    The focus of the research is to build a compact, high performance lightstripe rangefinder using a Very Large Scale Integration (VLSI) smart photosensor array. Rangefinding, the measurement of the three-dimensional profile of an object or scene, is a critical component for many robotic applications, and therefore many techniques were developed. Of these, lightstripe rangefinding is one of the most widely used and reliable techniques available. Though practical, the speed of sampling range data by the conventional light stripe technique is severely limited. A conventional light stripe rangefinder operates in a step-and-repeat manner. A stripe source is projected on an object, a video image is acquired, range data is extracted from the image, the stripe is stepped, and the process repeats. Range acquisition is limited by the time needed to grab the video images, increasing linearly with the desired horizontal resolution. During the acquisition of a range image, the objects in the scene being scanned must be stationary. Thus, the long scene sampling time of step-and-repeat rangefinders limits their application. The fast range sensor proposed is based on the modification of this basic lightstripe ranging technique in a manner described by Sato and Kida. This technique does not require a sampling of images at various stripe positions to build a range map. Rather, an entire range image is acquired in parallel while the stripe source is swept continuously across the scene. Total time to acquire the range image data is independent of the range map resolution. The target rangefinding system will acquire 1,000 100 x 100 point range images per second with 0.5 percent range accuracy. It will be compact and rugged enough to be mounted on the end effector of a robot arm to aid in object manipulation and assembly tasks.

  17. Wafer-scale fabrication of nanoapertures using corner lithography

    NASA Astrophysics Data System (ADS)

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-01

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated—based on a theoretical foundation including a statistical analysis—with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

  18. Correlation between reticle- and wafer-CD difference of multiple 28nm reticle-sites

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Richter, Frank; Thamm, Thomas; Ackmann, Paul; Staples, Marc; Weisbuch, Francois; Kurth, Karin; Schenker, Joerg; Leschok, Andre; GN, Fang Hong

    2012-11-01

    Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like "middle side lobe measurement", evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology

  19. EUVL mask substrate specifications (wafer-type)

    SciTech Connect

    Tong, W

    1999-07-01

    The Extreme Ultraviolet Lithography (EUVL) program currently is constructing an alpha-class exposure tool known as the Engineering Test Stand (ETS) that will employ 200mm wafer format masks. This report lists and explains the current specifications for the EUVL mask substrates suitable for use on the ETS. The shape and size of the mask are the same as those of a standard 200mm Si wafer. The flatness requirements are driven by the potential image placement distortion caused by the non-telecentric illumination of EUVL. The defect requirements are driven by the printable-defect size and desired yield for mask blank fabrication. Surface roughness can cause both a loss of light throughput and image speckle. The EUVL mask substrate must be made of low-thermal-expansion material because 40% of the light is absorbed by the multilayers and causes some uncorrectable thermal distortion during printing.

  20. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  1. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  2. Simple method for decreasing wafer topography effect for implant mask

    NASA Astrophysics Data System (ADS)

    You, Taejun; Lee, Taehyeong; Yoo, Gyun; Park, Youngjoon; Kim, Cheolkyun; Yim, Donggyu

    2016-03-01

    Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build. In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.

  3. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  4. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  5. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  6. VLSI chip-set for data compression using the Rice algorithm

    NASA Technical Reports Server (NTRS)

    Venbrux, J.; Liu, N.

    1990-01-01

    A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

  7. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    NASA Astrophysics Data System (ADS)

    Guo, Yuanbin; Zhang, Jianzhong(Charlie); McCain, Dennis; Cavallaro, Joseph R.

    2006-12-01

    We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size[InlineEquation not available: see fulltext.] with[InlineEquation not available: see fulltext.] complexity to some FFT operations with[InlineEquation not available: see fulltext.] complexity and the inverse of some[InlineEquation not available: see fulltext.] submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the[InlineEquation not available: see fulltext.] high-order receiver from partitioned[InlineEquation not available: see fulltext.] submatrices. This leads to more parallel VLSI design with[InlineEquation not available: see fulltext.] further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  8. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  9. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    NASA Astrophysics Data System (ADS)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  10. High density circuit technology, part 3

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations.

  11. Laser cutting silicon-glass double layer wafer with laser induced thermal-crack propagation

    NASA Astrophysics Data System (ADS)

    Cai, Yecheng; Yang, Lijun; Zhang, Hongzhi; Wang, Yang

    2016-07-01

    This study was aimed at introducing the laser induced thermal-crack propagation (LITP) technology to solve the silicon-glass double layer wafer dicing problems in the packaging procedure of silicon-glass device packaged by WLCSP technology, investigating the feasibility of this idea, and studying the crack propagation process of LITP cutting double layer wafer. In this paper, the physical process of the 1064 nm laser beam interact with the double layer wafer during the cutting process was studied theoretically. A mathematical model consists the volumetric heating source and the surface heating source has been established. The temperature and stress distribution was simulated by using finite element method (FEM) analysis software ABAQUS. The extended finite element method (XFEM) was added to the simulation as the supplementary features to simulate the crack propagation process and the crack propagation profile. The silicon-glass double layer wafer cutting verification experiment under typical parameters was conducted by using the 1064 nm semiconductor laser. The crack propagation profile on the fracture surface was examined by optical microscope and explained from the stress distribution and XFEM status. It was concluded that the quality of the finished fracture surface has been greatly improved, and the experiment results were well supported by the numerical simulation results.

  12. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  13. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    PubMed

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  14. High density circuit technology, part 1

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  15. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    PubMed

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  16. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  17. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  18. Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins

    NASA Astrophysics Data System (ADS)

    Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

    2014-04-01

    Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

  19. In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

    NASA Astrophysics Data System (ADS)

    Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

    2015-09-01

    In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

  20. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  1. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  2. Dominant factors of the laser gettering of silicon wafers

    SciTech Connect

    Bokhan, Yu. I. E-mail: yuibokhan@gmail.com; Kamenkov, V. S.; Tolochko, N. K.

    2015-02-15

    The laser gettering of silicon wafers is experimentally investigated. The typical gettering parameters are considered. The surfaces of laser-treated silicon wafers are investigated by microscopy. When studying the effect of laser radiation on silicon wafers during gettering, a group of factors determining the conditions of interaction between the laser beam and silicon-wafer surface and affecting the final result of treatment are selected. The main factors determining the gettering efficiency are revealed. Limitations on the desired value of the getter-layer capacity on surfaces with insufficiently high cleanness (for example, ground or matte) are established.

  3. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  4. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  5. The impact of wafering on organic and inorganic surface contaminations

    NASA Astrophysics Data System (ADS)

    Meyer, S.; Wahl, S.; Timmel, S.; Köpge, R.; Jang, B.-Y.

    2016-08-01

    Beside the silicon feedstock material, the crystallization process and the cell processing itself, the wafer sawing process can strongly determine the final solar cell quality. Especially surface contamination is introduced in this process step because impurities from sawing meet with a virgin silicon surface which is highly reactive until the oxide layer is formed. In this paper we quantitatively analysed both, the organic and inorganic contamination on wafer surfaces and show that changes of process parameters during wafering may cause dramatic changes in surface purity. We present powerful techniques for the monitoring of wafer surface quality which is essential for the production of high efficiency and high quality solar cells.

  6. Development of Fixture Element for Vacuum Transportation of Silicon Wafer Using Electro-Rheological Gel

    NASA Astrophysics Data System (ADS)

    Tanaka, Masayuki; Kakinuma, Yasuhiro; Aoyama, Tojiro; Anzai, Hidenobu; Kawaguchi, Takafumi

    Semiconductor process technology increasingly requires high accuracy and efficiency. In the case of processing thin fragile substrate such as silicon wafer, it has to be fixed with low strain. In addition, its fixture device can be used under vacuum condition because some processes are carried out in vacuum. It is required to develop a new fixture device for vacuum transportation of silicon wafer. ERG is the functional material whose friction characteristic varies according to the intensity of applied electric field. The surface friction of ERG can be changed quickly and reversibly applying the electric field. In other words, it becomes easy to fix and release a substrate by control of electric field. In this study, ERG is applied to a fixture element of silicon wafer available for vacuum process. The ERG fixture element was trial-manufactured and its performance under vacuum condition was evaluated experimentally. The result shows that the ERG effect emerges in vacuum and ERG can fix silicon wafer sufficiently. Moreover, numerical analysis of electric filed was carried out to obtain the optimal pattern of the one-sided electrodes used for the ERG fixture element. It is clear that the optimal width of electrodes exists according to the gap of electrodes and the thickness of ERG.

  7. Investigation of bidirectional reflectance and transmittance of rough silicon wafers

    NASA Astrophysics Data System (ADS)

    Shen, Yu-Jiun

    2002-01-01

    This research seeks to perform accurate measurements of bidirectional reflectance and transmittance of rough silicon wafers by a new benchtop scatterometer. An empirical model was developed according to the measurement data. The results will contribute to the application of radiative heat transfer modeling for a rapid thermal processing (RTP) system. In an RTP system, the radiation environment can greatly affect the reading of a lightpipe radiation thermometer. Knowledge of the bidirectional reflectance of rough silicon wafers is needed for the prediction of the reflected radiation into the radiometer, so that it can be used for accurate temperature measurement. The new scatterometer is capable of measuring out-of-plane scattering distribution at wavelengths of 635, 785, and 1550 nm from a diode laser system. Results were analyzed and compared to standard measurements at the National Institute of Standards and Technology. The relative difference is within the level of 5% for wavelengths of 635 and 785 nm and 10% for 1550 nm. An empirical model in the simple form of a two-parameter exponential function was proposed to fit the measured data. The results show that this approach can represent the measured data better than some other theoretical models discussed in this thesis. The empirical model can be used to estimate conical reflectance around a specular direction for different collecting half-cone angles. That provides a quick way to compare specular peak measurements from different instruments with varied collecting resolution. An in situ measurement in the mock-up RTP chamber was also performed. Results demonstrated the feasibility of compact optics setup, which mainly uses fiber-coupled devices.

  8. VLSI architectures for computing multiplications and inverses in GF(2-m)

    NASA Technical Reports Server (NTRS)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  9. VLSI architectures for computing multiplications and inverses in GF(2m)

    NASA Technical Reports Server (NTRS)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  10. Tunable multi-wavelength fiber lasers based on an Opto-VLSI processor and optical amplifiers.

    PubMed

    Xiao, Feng; Alameh, Kamal; Lee, Yong Tak

    2009-12-01

    A multi-wavelength tunable fiber laser based on the use of an Opto-VLSI processor in conjunction with different optical amplifiers is proposed and experimentally demonstrated. The Opto-VLSI processor can simultaneously select any part of the gain spectrum from each optical amplifier into its associated fiber ring, leading to a multiport tunable fiber laser source. We experimentally demonstrate a 3-port tunable fiber laser source, where each output wavelength of each port can independently be tuned within the C-band with a wavelength step of about 0.05 nm. Experimental results demonstrate a laser linewidth as narrow as 0.05 nm and an optical side-mode-suppression-ratio (SMSR) of about 35 dB. The demonstrated three fiber lasers have excellent stability at room temperature and output power uniformity less than 0.5 dB over the whole C-band.

  11. A cost-effective methodology for the design of massively-parallel VLSI functional units

    NASA Technical Reports Server (NTRS)

    Venkateswaran, N.; Sriram, G.; Desouza, J.

    1993-01-01

    In this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.

  12. A Very Large Scale Integration (VLSI) System For Image Reconstruction From Projections

    NASA Astrophysics Data System (ADS)

    Skellern, David J.

    1986-04-01

    An architecture and alforithms for a VLSI computer for back-projection image reconstruction are described. The computer consists of multiple identical back-projection processors connected in a linear array. Image pixels are pumped through the processor array, collecting at each processor a contribution to the image from one of its projections. Given one back-projection processor for each image projection, the entire reconstruction can be performed in a time comparable to that needed for sequential access of all image pixels. Implementation of a MOS VLSI back-projection processor is well advanced with working designs obtained for most processor subsystems. The processor incorporates a linear interpolator to estimate values between projection samples and accommodates non-linearity in the geometrical relationship between an image and its projection.

  13. A new VLSI architecture for a single-chip-type Reed-Solomon decoder

    NASA Technical Reports Server (NTRS)

    Hsu, I. S.; Truong, T. K.

    1989-01-01

    A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

  14. WARP: Weight Associative Rule Processor. A dedicated VLSI fuzzy logic megacell

    NASA Technical Reports Server (NTRS)

    Pagni, A.; Poluzzi, R.; Rizzotto, G. G.

    1992-01-01

    During the last five years Fuzzy Logic has gained enormous popularity in the academic and industrial worlds. The success of this new methodology has led the microelectronics industry to create a new class of machines, called Fuzzy Machines, to overcome the limitations of traditional computing systems when utilized as Fuzzy Systems. This paper gives an overview of the methods by which Fuzzy Logic data structures are represented in the machines (each with its own advantages and inefficiencies). Next, the paper introduces WARP (Weight Associative Rule Processor) which is a dedicated VLSI megacell allowing the realization of a fuzzy controller suitable for a wide range of applications. WARP represents an innovative approach to VLSI Fuzzy controllers by utilizing different types of data structures for characterizing the membership functions during the various stages of the Fuzzy processing. WARP dedicated architecture has been designed in order to achieve high performance by exploiting the computational advantages offered by the different data representations.

  15. Learning and optimization with cascaded VLSI neural network building-block chips

    NASA Technical Reports Server (NTRS)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  16. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    SciTech Connect

    Chiang, Patrick

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  17. A Systolic VLSI Design of a Pipeline Reed-solomon Decoder

    NASA Technical Reports Server (NTRS)

    Shao, H. M.; Truong, T. K.; Deutsch, L. J.; Yuen, J. H.; Reed, I. S.

    1984-01-01

    A pipeline structure of a transform decoder similar to a systolic array was developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation.

  18. A VLSI design for universal noiseless coding. [for spacecraft imaging equipment

    NASA Technical Reports Server (NTRS)

    Lee, Jun-Ji; Fang, Wai-Chi; Rice, Robert F.

    1988-01-01

    The practical, noiseless and efficient data-compression technique presented involves a conceptual VLSI design which is capable of meeting real-time processing rates and meets low-power, low-weight, and small-volume requirements. This form of data compression is applicable to image data compression aboard future low-budget spaceflight missions, for such instruments as visual-IR mapping spectrometers and high-resolution imaging spectrometers.

  19. Application of a VLSI vector quantization processor to real-time speech coding

    NASA Technical Reports Server (NTRS)

    Davidson, G.; Gersho, A.

    1986-01-01

    Attention is given to a working vector quantization processor for speech coding that is based on a first-generation VLSI chip which efficiently performs the pattern-matching operation needed for the codebook search process (CPS). Using this chip, the CPS architecture has been successfully incorporated into a compact, single-board Vector PCM implementation operating at 7-18 kbits/sec. A real time Adaptive Vector Predictive Coder system using the CPS has also been implemented.

  20. Eutectic bonds on wafer scale by thin film multilayers

    NASA Astrophysics Data System (ADS)

    Christensen, Carsten; Bouwstra, Siebe

    1996-09-01

    The use of gold based thin film multilayer systems for forming eutectic bonds on wafer scale is investigated and preliminary results will be presented. On polished 4 inch wafers different multilayer systems are developed using thin film techniques and bonded afterwards under reactive atmospheres and different bonding temperatures and forces. Pull tests are performed to extract the bonding strengths.

  1. Analysis of wafer heating in 14nm DUV layers

    NASA Astrophysics Data System (ADS)

    Subramany, Lokesh; Chung, Woong Jae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Minghetti, Blandine; Lee, Shawn

    2016-03-01

    To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

  2. Effects of Wafer Emissivity on Rapid Thermal Processing Temperature Measurement

    NASA Astrophysics Data System (ADS)

    Chen, D. H.; DeWitt, D. P.; Tsai, B. K.; Kreider, K. G.; Kimes, W. A.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are widely used to measure wafer temperatures in rapid thermal processing (RTP) tools. To use blackbody-calibrated LPRTs to infer the wafer temperature, it is necessary to build a model to predict the effective emissivity accounting for the wafer and chamber radiative properties as well as geometrical features of the chamber. The uncertainty associated with model-corrected temperatures can be investigated using test wafers instrumented with thin-film thermocouples (TFTCs) on which the LPRT target spot has been coated with films of different emissivity. A finite-element model of the wafer-chamber arrangement was used to investigate the effects of Pt spot (ɛs = 0.25) and Au spot (ɛs = 0.05) on the temperature distribution of test wafers with spectral emissivities of 0.65 and 0.84. The effects of the shield reflectivity and the cool lightpipe (LP) tip on the wafer temperature were evaluated. A radiance analysis method was developed, and a comparison of model-based predictions with experimental observations was made on a 200 mm diameter wafer in the NIST RTP test bed. The temperature rises caused by the low-emissivity spot were predicted and the cooling effect of the LP tip was determined. The results of the study are important for developing the model-based corrections for temperature measurements and related uncertainties using LPRTs in semiconductor thermal processes.

  3. Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

    PubMed Central

    Thomson, Stephen R. D.; Perron, Justin K.; Kimball, Mark O.; Mehta, Sarabjit; Gasparini, Francis M.

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

  4. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  5. Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

    PubMed

    Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

  6. Fault-sensitivity and wear-out analysis of VLSI systems

    NASA Astrophysics Data System (ADS)

    Choi, Gwan S.

    1995-06-01

    This thesis describes simulation approaches to conduct fault sensitivity and wear-out failure analysis of VLSI systems. A fault-injection approach to study transient impact in VLSI systems is developed. Through simulated fault injection at the device level and subsequent fault propagation at the gate, functional and software levels, it is possible to identify critical bottlenecks in dependability. Techniques to speed up the fault simulation and to perform statistical analysis of fault impact are developed. A wear-out simulation environment is also developed to closely mimic dynamic sequences of wear-out events in a device through time, to localize weak location/aspect of target chip and to allow generation of Time-to-Failure (TTF) distribution of a VLSI chip as whole. First, an accurate simulation of a target chip and its application code is performed to acquire real workload trace data on switch activity. Then, using this switch activity information, wear-out of the each component of the chip is simulated using Monte Carlo techniques.

  7. Low-temperature vacuum hermetic wafer-level package for uncooled microbolometer FPAs

    NASA Astrophysics Data System (ADS)

    Garcia-Blanco, S.; Topart, P.; Desroches, Y.; Caron, J. S.; Williamson, F.; Alain, C.; Jerominek, H.

    2008-02-01

    Micro-Electro-Mechanical Systems (MEMS) packaging constitutes most of the cost of such devices. For the integration of MEMS with microelectronics systems to be widespread, a drastic reduction of the overall price is required. Wafer-level-packaging allows a fundamental reduction of the packaging cost by combining wafer-level microfabrication techniques with wafer-to-wafer bonding. To achieve the vacuum atmosphere required for the operation of many MEMS devices, bonding techniques such as anodic bonding, eutectic bonding, fusion bonding and gold to gold thermocompression bonding have been utilized, which require relatively high temperatures (>300°C) being in some cases incompatible with MEMS and microelectronics devices. Furthermore, to maintain vacuum integrity over long periods of time, getters requiring high activation temperatures are usually employed. INO has developed a hybrid wafer-level micropackaging technology based on low temperature fluxless solder joints in which the micropackaged MEMS device is not exposed to a temperature over 150°C. The micropackages have been designed for 160×120 microbolometer FPAs. Ceramic spacers are patterned by standard microfabrication techniques followed by laser micromachining. AR-coated floatzone silicon IR windows are patterned with a solderable layer. Both, microbolometer dies and windows are soldered to the ceramic tray by a combination of solder paste stencil printing, reflow and fluxless flip-chip bonding. A low temperature getter is also introduced to control outgassing of moisture and CO II during the lifetime of the package. Vacuum sealing is carried out by locally heating the vacuum port after bake out of the micropackages. In this paper, the vacuum integrity of micropackaged FPA dies will be reported. Base pressures as low as 5 mTorr and equivalent flow rates at room temperature of 4×10 -14 Torr.l/s without getter incorporation have been demonstrated using integrated micro-pressure gauges. A study of the

  8. Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

    2016-04-01

    In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

  9. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  10. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  11. Investigations of Wafer Scale Etching with Xenon Difluoride

    NASA Astrophysics Data System (ADS)

    Chen, K. N.; Hoivik, N.; Lin, C. Y.; Young, A.; Ieong, M.; Shahidi, G.

    2006-03-01

    A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process cycle. Theoretical results are used to compare with the experimental results as well. A clean wafer surface by proper surface treatments is significant to achieve a uniform surface profile and morphology for XeF2 etching. A proper design of etching cycle with nitrogen ambient during etching is necessary to achieve the fastest and uniform silicon etching rate. The silicon etching rate is reported as a function of etching pressure, nitrogen pressure, and etching duration.

  12. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  13. CMOS VLSI pilot and support chip for a liquid crystal on silicon 8x8 optical cross connect

    NASA Astrophysics Data System (ADS)

    Lelah, Alan; Vinouze, Bruno; Martel, Gilbert; Perez-Segovia, Tomas; Geoffroy, Philippe; Laval, Jean-Paul; Jayet, Philippe; Senn, Patrice; Gravey, Philippe; Wolffer, Nicole; Lever, Roger; Tan, Antione

    2001-12-01

    With the explosion of Internet and multi-service traffic, telecommunication transport networks today are turning to Wavelength Division Multiplexing. Optical cross-connects (OXCs) allow flexible rerouting of wavelength channels. It has been shown that 2-D free-space beam deflection by nematic liquid crystal gratings provide a good solution for the realization of optical switches in OXCs. Operating in the telecom 1.5 micrometers wavelength region they serve as an active holographic element. Liquid Crystal on Silicon (LCOS) combined with VLSI technologies allow the fabrication of large capacity, low cost and low consumption compact free-space switches. An N X N optical switch can be built by cascading two LCOS-based spatial light modulators (SLMs). The first part of the paper describes a circuit that provides the physical support as well as piloting circuitry for such SLMs. It is capable of piloting beams from a linear array of 8 incoming fibers towards a similar array of 8 outgoing fibers. The electrode command voltages are analog while the external interface as well as on-chip memory is digital. The chip has been implemented in a CMOS 0.5 (mu) process with 600,000 transistors while die size is 320 mm2 (80 mm2 active area).

  14. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  15. The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

    NASA Astrophysics Data System (ADS)

    Lee, Jeffrey; McGarvey, Steve

    2013-04-01

    The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

  16. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  17. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    PubMed

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing.

  18. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  19. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    NASA Astrophysics Data System (ADS)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  20. Wafer-level vacuum packaging for an optical readout bi-material cantilever infrared FPA

    NASA Astrophysics Data System (ADS)

    Li, Shuyu; Zhou, Xiaoxiong; Yu, Xiaomei

    2013-12-01

    In this paper, we report the design and fabrication of an uncooled infrared (IR) focal plane array (FPA) on quartz substrate and the wafer-level vacuum packaging for the IR FPA in view of an optical readout method. This FPA is composed of bi-material cantilever array which fabricated by the Micro-Electro Mechanical System (MEMS) technology, and the wafer-level packaging of the IR FPA is realized based on AuSn solder bonding technique. The interface of soldering is observed by scan electron microscope (SEM), which indicates that bonding interface is smooth and with no bubbles. The air leakage rate of packaged FPA is measured to be 1.3×10-9 atm·cc/s.

  1. Research News: Are VLSI Microcircuits Too Hard to Design?

    ERIC Educational Resources Information Center

    Robinson, Arthur L.

    1980-01-01

    This research news article on microelectronics discusses the scientific challenge the integrated circuit industry will have in the next decade, for designing the complicated microcircuits made possible by advancing miniaturization technology. (HM)

  2. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  3. Contamination control: removing small particles from increasingly large wafers

    NASA Astrophysics Data System (ADS)

    de Jong, A. J.; van der Donck, J. C. J.; Huijser, T.; Kievit, O.; Koops, R.; Koster, N. B.; Molkenboer, F. T.; Theulings, A. M. M. G.

    2012-03-01

    With the introduction of 450 mm wafers, which are considerably larger than the currently largest wafers of 300mm, handling with side grippers is no longer possible and backside grippers are required. Backside gripping increases the possible buildup of particles on the backside of the wafers with possible cross-contamination to the front-side. Therefore, regular backside cleaning is required. Three vacuum compatible cleaning methods were selected. Tacky rollers and highvoltage cleaning were selected for particles and plasma cleaning for molecular layers. A test-bench was designed and constructed implementing these three cleaning methods. The first experiments show promising results for the plasma cleaner and the tacky roller.

  4. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  5. Direct to Digital Holography for Semiconductor Wafer Defect Detection and Review

    SciTech Connect

    ThomasJr., C. E.; Bahm, Tracy M.; Baylor, Larry R; Bingham, Philip R.; Burns, Steven W.; Chidley, Matthew D; Dai, Xiaolong; Delahanty, Robert J.; Doti, Christopher J.; El-Khashab, Ayman; Fisher, Robert L.; Gilbert, Judd M.; Cui, Hongtao; Goddard Jr, James Samuel; Hanson, Gregory R; Hickson, Joel D.; Hunt, Martin A.; Hylton, Kathy W; John, George C.; Jones, Michael L.; McDonald, Kenneth R.; Mayo, Michael W.; McMackin, Ian; Patek, David; Price, John H.; Rasmussen, David A; Schaefer, Louis J.; Scheidt, Thomas R.; Schulze, Mark A.; Schumaker, Philip D.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin Jr, Kenneth William; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Jones, Paul G.; Owen, Robert W.

    2002-01-01

    A method for recording true holograms (not holographic interferometry) directly to a digital video medium in a single image has been invented. This technology makes the amplitude and phase for every pixel of the target object wave available. Since phase is proportional to wavelength, this makes high-resolution metrology an implicit part of the holographic recording. Measurements of phase can be made to one hundredth or even one thousandth of a wavelength, so the technology is attractive for finding defects on semiconductor wafers, where feature sizes are now smaller than the wavelength of even deep ultra-violet light.

  6. Development of thin edgeless silicon pixel sensors on epitaxial wafers

    NASA Astrophysics Data System (ADS)

    Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

    2014-09-01

    The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 × 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

  7. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  8. Automated radiometric cryoprobe of IR focal plane array wafers

    NASA Astrophysics Data System (ADS)

    Whicker, Stephen L.

    1994-07-01

    Texas Instruments (TI) validated the feasibility of cryoprobing IRFPA arrays in late 1991. Since then, TI has developed a revolutionary automated cryoprobe for screening four and six inch wafers of IRFPAs. Generic prober automation features include cassette to cassette wafer load and unload, wafer alignment, black body selection, aperture selection, probe tip continuity test, and 77.5 degree(s) to 400 degree(s)K wafer temperature control. Modular construction of the prober enables placement of product specific components such as MWIR or LWIR bandpass filters, coldshield, coldfilter, probe card, and noise suppression circuitry on an easily removable `product specific' tooling plate. Prober operation is controlled through object oriented software. IRFPA specific software modules control array operation, data collection, and data reduction. In addition to describing the prober capabilities and versatility, this paper compares prober test data to lab dewar test data for 240 X 1 IRFPAs and projects benefits in reduced cycle time and labor savings.

  9. 9nm node wafer defect inspection using visible light

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  10. Optical analysis on the wafer defect inspection for yield enhancement

    NASA Astrophysics Data System (ADS)

    Ahn, Jeongho; Lee, Byoungho; Lee, Dong-Ryul; Seong, Shijin; Kim, Hyungseop; Choi, Seongchae; Sunwoo, Heewon; Lee, Junbum; Ihm, Dongchul; Chin, Soobok; Kang, Ho-Kyu

    2013-04-01

    This paper presents a methodology for detecting defects more effectively that have a substantial yield impact on several critical layers using a simulation program, which is considerably helpful in analyzing defects on the wafer. First, this paper presents a simple analysis method that uses mathematical treatment for multi thin film layers. This instantly gives us a highly intuitive idea for selecting an inspection mode based on the reflectivity and transmittivity. Second, we introduce numerical method for wafer defect of interest with finite difference time domain (FDTD) method, and provide correlation between the expectation and experimental results. The goal of these studies is to determine the feasibility of implementing theoretical approaches with numerical method at wafer defect inspection. Overall, this paper discusses the effective wafer inspection methodology and the advantages of defect simulation with numerical analysis at semiconductor manufacturing for accelerated development of advanced design node devices.

  11. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  12. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  13. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  14. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  15. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  16. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  17. A VLSI pipeline design of a fast prime factor DFT on a finite field

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Hsu, I. S.; Shao, H. M.; Reed, I. S.; Shyu, H. C.

    1986-01-01

    A conventional prime factor discrete Fourier transform (DFT) algorithm is used to realize a discrete Fourier-like transform on the finite field, GF(q sub n). A pipeline structure is used to implement this prime factor DFT over GF(q sub n). This algorithm is developed to compute cyclic convolutions of complex numbers and to decode Reed-Solomon codes. Such a pipeline fast prime factor DFT algorithm over GF(q sub n) is regular, simple, expandable, and naturally suitable for VLSI implementation. An example illustrating the pipeline aspect of a 30-point transform over GF(q sub n) is presented.

  18. An effective timing characterization method for an accuracy-proved VLSI standard cell library

    NASA Astrophysics Data System (ADS)

    Jianhua, Jiang; Man, Liang; Lei, Wang; Yumei, Zhou

    2014-02-01

    This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

  19. VLSI Implementation of a Bio-inspired Olfactory Spiking Neural Network

    NASA Astrophysics Data System (ADS)

    Hsieh, Hung-Yi; Tang, Kea-Tiong

    2011-11-01

    This paper proposes a VLSI circuit implementing a low power, high-resolution spiking neural network (SNN) with STDP synapses, inspired by mammalian olfactory systems. By representing mitral cell action potential by a step function, the power consumption and the chip area can be reduced. By cooperating sub-threshold oscillation and inhibition, the network outputs can be distinct. This circuit was fabricated using the TSMC 0.18 μm 1P6M CMOS process. Post-layout simulation results are reported.

  20. Innovative through-silicon-via formation approach for wafer-level packaging applications

    NASA Astrophysics Data System (ADS)

    Tang, Chao Wei; Tsu Young, Hong; Li, Kuan Ming

    2012-04-01

    Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system-in-packaging and wafer-level packaging applications. Among several available TSV formation methods, Bosch deep reactive ion etching (DRIE) is widely used because it enables the fabrication of TSVs with almost any diameter, from the submicrometer level to hundreds of micrometers. However, the high cost of Bosch DRIE makes it uneconomical for industrial production. We present a novel wafer-level TSV formation approach that is effective and cost-efficient. The proposed method integrates a diode-pumped solid-state ultraviolet nanosecond pulsed laser and rapid wet chemical etching. The former is effective in drilling through 400 µm thick silicon wafers and the latter is used for removing the unwanted heat-affected zone, recast layer and debris left after drilling. Experimental results demonstrate that the combined approach effectively eliminates the unwanted material formed by nanosecond laser pulses. Furthermore, this approach has a significant cost advantage over Bosch DRIE. In summary, the proposed approach affords superior TSV quality, higher TSV throughput and lower cost of process ownership than Bosch DRIE. These advantages could provide the necessary impetus for rapid commercialization of the several high-density fabrication methodologies that depend on TSVs.

  1. Imprinted laminate wafer-level packaging for SAW ID-tags and SAW delay line sensors.

    PubMed

    Kuypers, Jan H; Tanaka, Shuji; Esashi, Masayoshi

    2011-02-01

    We have developed a wafer-level packaging solution for surface acoustic wave devices using imprinted dry film resist (DFR). The packaging process involves the preparation of an imprinted dry film resist that is aligned and laminated to the device wafer and requires one additional lithography step to define the package outline. Two commercial dry film solutions, SU-8 and TMMF, have been evaluated. Compared with traditional ceramic packages, no detectable RF parasitics are introduced by this packaging process. At the same time, the miniature package dimensions allow for wafer-level probing. The packaging process has the great advantage that the cavity formation does not require any sacrificial layer and no liquids, and therefore prevents contamination or stiction of the packaged device. This non-hermetic packaging process is ideal for passive antenna modules using polymer technology for low-cost SAW identification (ID)-tags or lidding in low-temperature cofired ceramic (LTCC) antenna substrates for high-performance wireless sensors. This technique is also applicable to SAW filters and duplexers for module integration in cellular phones using flip-chip mounting and hermetic overcoating. PMID:21342826

  2. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

  3. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

  4. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  5. Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Sharma, Himani; Krabbe, Joshua D.; Farsinezhad, Samira; van Popta, Andy C.; Wakefield, Nick G.; Fitzpatrick, Glen A.; Shankar, Karthik

    2015-04-01

    Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accurate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing downstream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-μm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ˜9 to 11 μm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100°C postanneal was found to reduce average stresses by 40%.

  6. 1.5-μm optical up-conversion: wafer fusion and related issues

    NASA Astrophysics Data System (ADS)

    Ban, Dayan; Luo, Hui; Liu, Hui-Chun; SpringThorpe, Anthony J.; Wasilewski, Zbigniew R.; Bezinger, Andrew; Bogdanov, Alexei; Buchanan, Margaret

    2004-11-01

    Imaging devices working in the near infrared (NIR), especially in the so-called eye-safe range, i.e., around 1.5 mm, have become increasingly important in many military and commercial applications; these include night vision, covert surveillance, range finding and semiconductor wafer inspection. We proposed a new approach in which a wafer-fused optical up-converter, combined with a commercially available charged coupled device (CCD), functions as an infrared camera. The optical up-converter converts incoming infrared light into shorter wavelength radiation that can be efficiently detected by the silicon CCD (cutoff wavelength about 1 mm). An optical up-converter with high efficiency at room-temperature is critical for low cost and large-area infrared imaging applications. A prototype 1.5 mm optical up-converter based on wafer fusion technology has been successfully fabricated. The device consists of an InGaAs/InP pin photodetector and a GaAs/AlGaAs light emitting diode. Experimental results show that the end-to-end up-conversion efficiency is 0.0177 W/W at room-temperature, corresponding to an internal quantum up-conversion efficiency of 76%. In this paper, the design, fabrications and characterization of the optical up-conversion devices is presented. Issues related to device optimization, such as improving internal and external up-conversion efficiency, are addressed. Preliminary results demonstrate the room-temperature up-conversion imaging operation of a pixelated wafer-fused device.

  7. Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger

    NASA Astrophysics Data System (ADS)

    Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

    2010-10-01

    We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

  8. Data storage technology comparisons

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.

    1990-01-01

    The role of data storage and data storage technology is an integral, though conceptually often underestimated, portion of data processing technology. Data storage is important in the mass storage mode in which generated data is buffered for later use. But data storage technology is also important in the data flow mode when data are manipulated and hence required to flow between databases, datasets and processors. This latter mode is commonly associated with memory hierarchies which support computation. VLSI devices can reasonably be defined as electronic circuit devices such as channel and control electronics as well as highly integrated, solid-state devices that are fabricated using thin film deposition technology. VLSI devices in both capacities play an important role in data storage technology. In addition to random access memories (RAM), read-only memories (ROM), and other silicon-based variations such as PROM's, EPROM's, and EEPROM's, integrated devices find their way into a variety of memory technologies which offer significant performance advantages. These memory technologies include magnetic tape, magnetic disk, magneto-optic disk, and vertical Bloch line memory. In this paper, some comparison between selected technologies will be made to demonstrate why more than one memory technology exists today, based for example on access time and storage density at the active bit and system levels.

  9. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    NASA Technical Reports Server (NTRS)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  10. Sensor-based driving of a car with fuzzy inferencing VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Watanabe, Y.

    1992-09-01

    This paper discusses the sensor-based driving of a car in a-priori unknown environments using ``human-like`` reasoning schemes. The schemes are implemented on custom-designed VLSI fuzzy inferencing boards and are used to investigate two control modes for driving a car on the basis of very sparse and imprecise range data. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver`s aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up, slow down, stop, or back up depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Sample results are presented which illustrate the feasibility of developing autonomous navigation systems and robust safety enhancing driver`s aid using the new fuzzy inferencing VLSI hardware and ``human-like`` reasoning schemes.

  11. Real-Time Classification of Complex Patterns Using Spike-Based Learning in Neuromorphic VLSI.

    PubMed

    Mitra, S; Fusi, S; Indiveri, G

    2009-02-01

    Real-time classification of patterns of spike trains is a difficult computational problem that both natural and artificial networks of spiking neurons are confronted with. The solution to this problem not only could contribute to understanding the fundamental mechanisms of computation used in the biological brain, but could also lead to efficient hardware implementations of a wide range of applications ranging from autonomous sensory-motor systems to brain-machine interfaces. Here we demonstrate real-time classification of complex patterns of mean firing rates, using a VLSI network of spiking neurons and dynamic synapses which implement a robust spike-driven plasticity mechanism. The learning rule implemented is a supervised one: a teacher signal provides the output neuron with an extra input spike-train during training, in parallel to the spike-trains that represent the input pattern. The teacher signal simply indicates if the neuron should respond to the input pattern with a high rate or with a low one. The learning mechanism modifies the synaptic weights only as long as the current generated by all the stimulated plastic synapses does not match the output desired by the teacher, as in the perceptron learning rule. We describe the implementation of this learning mechanism and present experimental data that demonstrate how the VLSI neural network can learn to classify patterns of neural activities, also in the case in which they are highly correlated. PMID:23853161

  12. Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics.

    PubMed

    Yu, Theodore; Cauwenberghs, Gert

    2010-06-01

    We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW.

  13. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  14. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  15. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-02-11

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  16. Fast on-wafer electrical, mechanical, and electromechanical characterization of piezoresistive cantilever force sensors.

    PubMed

    Tosolini, G; Villanueva, L G; Perez-Murano, F; Bausells, J

    2012-01-01

    Validation of a technological process requires an intensive characterization of the performance of the resulting devices, circuits, or systems. The technology for the fabrication of micro and nanoelectromechanical systems (MEMS and NEMS) is evolving rapidly, with new kind of device concepts for applications like sensing or harvesting are being proposed and demonstrated. However, the characterization tools and methods for these new devices are still not fully developed. Here, we present an on-wafer, highly precise, and rapid characterization method to measure the mechanical, electrical, and electromechanical properties of piezoresistive cantilevers. The setup is based on a combination of probe-card and atomic force microscopy technology, it allows accessing many devices across a wafer and it can be applied to a broad range of MEMS and NEMS. Using this setup we have characterized the performance of multiple submicron thick piezoresistive cantilever force sensors. For the best design we have obtained a force sensitivity Re(F) = 158μV/nN, a noise of 5.8 μV (1 Hz-1 kHz) and a minimum detectable force of 37 pN with a relative standard deviation of σ(r) ≈ 8%. This small value of σ(r), together with a high fabrication yield >95%, validates our fabrication technology. These devices are intended to be used as bio-molecular detectors for the measurement of intermolecular forces between ligand and receptor molecule pairs.

  17. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  18. VLSI circuits implementing computational models of neocortical circuits.

    PubMed

    Wijekoon, Jayawan H B; Dudek, Piotr

    2012-09-15

    This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. PMID:22342970

  19. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  20. Low-temperature titanium-based wafer bonding

    NASA Astrophysics Data System (ADS)

    Yu, Jian

    This thesis presents novel methods of metal-based wafer bonding at back-end-of-the-line (BEOL) compatible conditions (≤450°C). For the first time to our knowledge, 200 mm diameter oxidized Si wafers are bonded with prime Si wafers using 10-300 nm thick Ti as bonding intermediate at 300-450°C. Nearly void-free bonding with strong mechanical integrity has been confirmed. Moreover, microcavity formation has been demonstrated by bonding of patterned wafers. Both Rutherford backscattering spectroscopy (RBS) and Auger electron spectroscopy (AES) show clear evidence of Si and Ti interdiffusion, whereas high-resolution transmission electron microscopy (HRTEM) reveals an approximately 8 nm thick amorphous layer at the bonding interface. Those results indicate that the strong adhesion at the Ti/Si bonding interface is attributed to a solid-state amorphization (SSA) assisted by interdiffusion. A key effort is devoted to fundamental investigation of low-temperature transition metal(TM)/Si-based wafer bonding. With the extensive work on Ti/Si system, additional experiments are performed with six other TM/Si systems, namely Ni/Si, Co/Si, Pd/Si, Hf/Si, Au/Si and Ta/Si. The results indicate there are two principal requirements for TM/Si-based wafer bonding: (1) intimate contact (able to break through kinetic barriers), and (2) adequate chemical bonding. Three kinetic barriers addressed in this thesis are: (1) enclosed microvoids due to surface roughness, (2) gas molecules at the bonding interface, and (3) interfacial oxides. Presence of these barriers can prevent formation of intimate contact, consequently retarding or even blocking interfacial interactions for chemical bonding. The unique properties of Group IVA metals (e.g., Ti and Hf) to reduce native SiO2 on Si surfaces and their exceptionally large solid solubility for O2 and N2, help overcome those issues. Once kinetic barriers are surmounted, the key for strong metal/Si-based wafer bonding is formation of chemical bonds

  1. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  2. Simple and accurate optical height sensor for wafer inspection systems

    NASA Astrophysics Data System (ADS)

    Shimura, Kei; Nakai, Naoya; Taniguchi, Koichi; Itoh, Masahide

    2016-02-01

    An accurate method for measuring the wafer surface height is required for wafer inspection systems to adjust the focus of inspection optics quickly and precisely. A method for projecting a laser spot onto the wafer surface obliquely and for detecting its image displacement using a one-dimensional position-sensitive detector is known, and a variety of methods have been proposed for improving the accuracy by compensating the measurement error due to the surface patterns. We have developed a simple and accurate method in which an image of a reticle with eight slits is projected on the wafer surface and its reflected image is detected using an image sensor. The surface height is calculated by averaging the coordinates of the images of the slits in both the two directions in the captured image. Pattern-related measurement error was reduced by applying the coordinates averaging to the multiple-slit-projection method. Accuracy of better than 0.35 μm was achieved for a patterned wafer at the reference height and ±0.1 mm from the reference height in a simple configuration.

  3. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  4. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    NASA Technical Reports Server (NTRS)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  5. VLSI partitioning of a 2-Gs/s digital spectrometer

    NASA Astrophysics Data System (ADS)

    von Herzen, Brian

    1991-05-01

    A digital correlating spectrometer for radio astronomy that is based on a custom GaAs digitizer and a custom micropipelined CMOS correlator is described. The digitizer quantizes at two gigasamples per second (Gs/s) and 2-b resolution. A GaAs demultiplexer distributes the data into eight parallel streams of 250 Ms/s each. The CMOS correlator operates at 250 Ms/s using 20 mW per correlator lag. The correlator output is processed on a host microcomputer to create a 1-GHz spectrum of the input signal that can be displayed interactively. An 8 x 9-mm chip is being developed in a 2-micron process that contains 320 correlator lags. The design is partitioned into GaAs and CMOS components according to the required throughput at each stage of the system. The fastest signals (2 GHz) are kept on the chip level to minimize delay, crosstalk, system noise, and power consumption. Moderate-speed signals (250 MHz) are driven by GaAs components. CMOS components are used where high-speed outputs are not required. A strong synergy between the correlator architecture and micropipelined CMOS technology improves the performance by an order of magnitude compared to existing designs. Preliminary correlator chips have been built and tested at 250 Ms/s; final chips are under design.

  6. Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

    NASA Technical Reports Server (NTRS)

    Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

    1996-01-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  7. Development of a wafer positioning system for the Sandia extreme ultraviolet lithography tool

    SciTech Connect

    Wronosky, J.B.; Smith, T.G.; Darnold, J.R.

    1995-12-01

    A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

  8. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  9. Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

    NASA Astrophysics Data System (ADS)

    den Boef, Arie J.

    2016-06-01

    This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

  10. Influences of the exhaust flow on the boundary layer flow on the wafer surface in spin coating system

    NASA Astrophysics Data System (ADS)

    Kimura, Seiichi; Munekata, Mizue; Kurishima, Hiroaki; Matsuzaki, Kazuyoshi; Ohba, Hideki

    2005-06-01

    Recently, development of high technology has been required for the formation of thin uniform film in manufacturing processes of semiconductor as the semiconductor become more sophisticated. Spin coating is usually used for spreading photoresist on a wafer surface. However, since rotating speed of the disk is very high in spin coating, the dropped resist scatters outward and reattaches to the film surface. So, the scattered resist is removed by the exhaust flow generated at the gap between the wafer edge and the catch cup. It is seriously concemed that the stripes called Ekman spiral vortices appears on the disk in the case of high rotating speed and the film thickness increases near the wafer edge in the case of low rotating speed, because it prevent the formation of uniform film. The purpose of this study is to make clear the generation mechanism of Ekman spiral vortices and the influence of exhaust flow on it. Moreover the influence of the catch cup geometry on the wafer surface boundary layer flow is investigated.

  11. White-light interferometric microscopy for wafer defect inspection

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  12. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    NASA Astrophysics Data System (ADS)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  13. Growth of silver nanowires on GaAs wafers.

    PubMed

    Sun, Yugang

    2011-05-01

    Silver (Ag) nanowires with chemically clean surfaces have been directly grown on semi-insulating gallium arsenide (GaAs) wafers through a simple solution/solid interfacial reaction (SSIR) between the GaAs wafers themselves and aqueous solutions of silver nitrate (AgNO(3)) at room temperature. The success in synthesis of Ag nanowires mainly benefits from the low concentration of surface electrons in the semi-insulating GaAs wafers that can lead to the formation of a low-density of nuclei that facilitate their anisotropic growth into nanowires. The resulting Ag nanowires exhibit rough surfaces and reasonably good electric conductivity. These characteristics are beneficial to sensing applications based on single-nanowire surface-enhanced Raman scattering (SERS) and possible surface-adsorption-induced conductivity variation.

  14. Monitoring of acoustic emission activity using thin wafer piezoelectric sensors

    NASA Astrophysics Data System (ADS)

    Trujillo, Blaine; Zagrai, Andrei; Meisner, Daniel; Momeni, Sepand

    2014-03-01

    Acoustic emission (AE) is a well-known technique for monitoring onset and propagation of material damage. The technique has demonstrated utility in assessment of metallic and composite materials in applications ranging from civil structures to aerospace vehicles. While over the course of few decades AE hardware has changed dramatically with the sensors experiencing little changes. A traditional acoustic emission sensor solution utilizes a thickness resonance of the internal piezoelectric element which, coupled with internal amplification circuit, results in relatively large sensor footprint. Thin wafer piezoelectric sensors are small and unobtrusive, but they have seen limited AE applications due to low signal-to-noise ratio and other operation difficulties. In this contribution, issues and possible solutions pertaining to the utility of thin wafer piezoelectrics as AE sensors are discussed. Results of AE monitoring of fatigue damage using thin wafer piezoelectric and conventional AE sensors are presented.

  15. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  16. Wafer scale fabrication of submicron chessboard gratings using phase masks in proximity lithography

    NASA Astrophysics Data System (ADS)

    Stuerzebecher, Lorenz; Harzendorf, Torsten; Fuchs, Frank; Zeitner, Uwe D.

    2012-03-01

    One and two dimensional grating structures with submicron period have a huge number of applications in optics and photonics. Such structures are conventionally fabricated using interference or e-beam lithography. However, both technologies have significant drawbacks. Interference lithography is limited to rather simple geometries and the sequential writing scheme of e-beam lithography leads to time consuming exposures for each grating. We present a novel fabrication technique for this class of microstructures which is based on proximity lithography in a mask aligner. The technology is capable to pattern a complete wafer within less than one minute of exposure time and offers thereby high lateral resolution and a reliable process. Our advancements compared to standard mask aligner lithography are twofold: First of all, we are using periodic binary phase masks instead of chromium masks to generate an aerial image of high resolution and exceptional light efficiency at certain distances behind the mask. Second, a special mask aligner illumination set-up is employed which allows to precisely control the incidence angles of the exposure light. This degree of freedom allows both, to shape the aerial image (e. g. transformation of a periodic spot pattern into a chessboard pattern) and to increase its depth of focus considerably. That way, our technology enables the fabrication of high quality gratings with arbitrary geometry in a fast and stable wafer scale process.

  17. Design and development of wafer-level short wave infrared micro-camera

    NASA Astrophysics Data System (ADS)

    Sood, Ashok K.; Richwine, Robert A.; Pethuraja, Gopal; Puri, Yash R.; Lee, Je-Ung; Haldar, Pradeep; Dhar, Nibir K.

    2013-06-01

    Low cost IR Sensors are needed for a variety of Defense and Commercial Applications as low cost imagers for various Army and Marine missions. SiGe based IR Focal Planes offers a low cost alternative for developing wafer-level shortwave infrared micro-camera that will not require any cooling and can operate in the Visible-NIR band. The attractive features of SiGe based IRFPA's will take advantage of Silicon based technology, that promises small feature size and compatibility with the low power silicon CMOS circuits for signal processing. SiGe technology offers a low cost alternative for developing Visible-NIR sensors that will not require any cooling and can operate from 0.4- 1.7 microns. The attractive features of SiGe based IRFPA's will take advantage of Silicon based technology that can be processed on 12-inch silicon substrates, that can promise small feature size and compatibility with the Silicon CMOS circuit for signal processing. In this paper, we will discuss the design and development of Wafer-Level Short Wave Infrared (SWIR) Micro-Camera. We will discuss manufacturing approaches and sensor configurations for short wave infrared (SWIR) focal plane arrays (FPAs) that significantly reduce the cost of SWIR FPA packaging, optics and integration into micro-systems.

  18. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  19. Digital model planning and computerized fabrication of orthognathic surgery wafers.

    PubMed

    Cousley, Richard R J; Turner, Mark J A

    2014-03-01

    Conventional orthognathic wafers are made by a process involving manual movement of stone dental models and acrylic laboratory fabrication. In addition, a facebow record and semi-adjustable articulator system are required for maxillary osteotomy cases. This paper introduces a novel process of producing both intermediate and final orthognathic surgical wafers using a combination of computerized digital model simulation and three-dimensional print fabrication, without the need for either a facebow record or the additional ionizing radiation exposure associated with cone beam computerized tomography.

  20. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  1. Noble approach for mask-wafer measurement by design-based metrology integration system

    NASA Astrophysics Data System (ADS)

    Mito, Hiroaki; Hayano, Katsuya; Maeda, Tatsuya; Mohri, Hiroshi; Sato, Hidetoshi; Matsuoka, Ryoichi; Sukegawa, Shigeki

    2009-10-01

    OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask technique need be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to be reported that there are cases that size cannot be matched between a mask pattern and the corresponding printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the device size is so small that low k1 lithography had been developed and widely used in a production. Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using contour that was extracted from mask SEM image in addition to mask model. This paper describes a newly developed integration system in order to solve issues above, and the applications. This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using DesignGauge; OPC evaluation system by Hitachi High-Technologies. It was investigated that a measurement accuracy improvement by executing a mask-wafer same point measurement with same measurement algorithm utilizing the new system. At first, we measured patterns described on a mask and verified the validity based on a measurement value, picture, measurement parameter and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same patterns that were exposed using the mask. In addition, average CD measurement was tried in order to improve the

  2. New approach for mask-wafer measurement by design-based metrology integration system

    NASA Astrophysics Data System (ADS)

    Maeda, Tatsuya; Hayano, Katsuya; Kawashima, Satoshi; Mohri, Hiroshi; Sakai, Hideo; Sato, Hiodetoshi; Matsuoka, Ryoichi; Nishihara, Makoto; Sukegawa, Shigeki

    2009-03-01

    OPC (Optical Proximity Correction) technique is getting more complicated towards 32 nm technology node and beyond, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and their manufacturing process is complicated. In order to shorten TAT (Turn around time), mask design technique needs be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so its current performance is very close to the ideal. On the other hand, when down sizing of device feature size reaches the 32nm technology node, cases begin to be reported where the feature dimension is not matched between a mask pattern and the corresponding printed pattern. Therefore, it is indispensable to understand the pattern size correlation between a mask and the corresponding printed wafer in order to improve the processing accuracy and the quality in the situation where the device size is so small that the low k1 lithography is widely used in production. One of the approaches to improve the estimated accuracy of lithography is the use of contour data extracted from mask SEM image in addition to the application of a mask model. This paper describes a newly developed integration system that aims to solve the issues above, and its applications. This is a system that integrates mask CD-SEM (Critical Dimension-Scanning Electron Microscope) CG4500, wafer CD-SEM CG4000, OPC evaluation system DesignGauge, all manufactured by Hitachi High-Technologies. The measurement accuracy improvement was examined by executing a mask-wafer same point measurement, i.e. measurement of the corresponding points, with same measurement algorithm utilizing the new system. First, we measured mask patterns and verified the validity based on the measurement value, the image, the measurement parameter and the coordinates. Then a job file was formulated for a wafer CD-SEM using the new system so as to measure the corresponding

  3. Low-temperature thin-film indium bonding for reliable wafer-level hermetic MEMS packaging

    NASA Astrophysics Data System (ADS)

    Straessle, R.; Pétremand, Y.; Briand, D.; Dadras, M.; de Rooij, N. F.

    2013-07-01

    This paper reports on low-temperature and hermetic thin-film indium bonding for wafer-level encapsulation and packaging of delicate and temperature sensitive devices. This indium-bonding technology enables bonding of surface materials commonly used in MEMS technology. The temperature is kept below 140 °C for all process steps and no surface treatment is applied before and during bonding. This bonding technology allows hermetic sealing at 140 °C with a leak rate below 4 × 10-12 mbar l s-1 at room temperature. The tensile strength of the bonds up to 25 MPa goes along with a very high yield.

  4. Abstract specification of synchronous data types for VLSI and proving the correctness of systolic network implementations

    SciTech Connect

    Probst, D.K.; Li, H.F.

    1988-06-01

    The authors present a combined methodology for specifying abstract synchronous data types and proving the correctness of systolic network implementations. 1) The authors show that an extension of the Parnas trace method of specifying software modules containing distinct access programs yields a natural method of specifying abstract synchronous data types which possess distinct access operators and are intended for implementation in VLSI. 2). They present associated systematic proof techniques and establish the correctness of several novel systolic network implementations of familiar data types. In so far as these specifications refer to the ongoing, externally visible behavior of (abstract) synchronous objects rather than the instantaneous internal configurations of (concrete, implementing) synchronous systems, the methodology appears to be naturally suited to systolic network implementations with their associated rippling of control flow and data flow. The important distinction between systolic control-flow networks and systolic data-flow networks is also presented.

  5. A VLSI ASIC front end for the optical module of the NEMO underwater neutrino detector

    NASA Astrophysics Data System (ADS)

    Lo Presti, Domenico

    2006-11-01

    The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and designing a front-end electronics for the Optical Modules, which contains the telescope optical sensors, as a full-custom Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC). The solution has a multitude of advantages. The most important are low power consumption and the pre-analysis and suitable reduction of data to be transferred to the shore station for acquisition. A detailed description of the chosen architecture and the design principles of the blocks, that carry out the specialized function required by this architecture, will be given. The chips produced will be described and the test measurements performed will be shown.

  6. Continuous-time calibration of VLSI sensors for gain and offset variations

    NASA Astrophysics Data System (ADS)

    Harris, John G.

    1995-05-01

    Parameter variations cause unavoidable nonuniformities in infrared focal plane arrays and other integrated sensors. A one-time calibration procedure is normally used to counteract the effect of these variations between components. Unfortunately, many of these variations fluctuate with time--either with operating point (such as data-dependent variations) or with external conditions (such as temperature). Calibrating these sensors one-time only at the `factory' is not suitable--much more frequent calibration is required. We have developed an adaptive algorithm that continually calibrates an array of sensors that contains gain and offset variations. This paper extends the work of Ullman and Schechtman who developed an algorithm for gain adjustment. The adaptive nonlinear dynamical system can be mapped to analog VLSI or a discretized version may be efficiently implemented in digital hardware.

  7. A family of analog and mixed signal VLSI ASICs for NASA science missions

    NASA Astrophysics Data System (ADS)

    Paschalidis, Nick

    2003-11-01

    This paper presents several analog and mixed signal VLSI chips that have been successfully developed over the past several years at JHU/APL for space science missions. The chips have applications on spacecraft avionics and several types of instrumentation. The family of the chips include: the TRIO Smart Sensor multiplexed ADC chip for spacecraft/instrument avionics, the Time of Flight chip for precise time interval measurement, the Energy Chip for low noise particle/photon measurement, a Commandable Discriminator Pulse High Analyzer, Event Accumulator, a radiation hardened voltage reference, an ADC and other. The talk will address some design, radiation hard by design, design for testability, testing, and space qualification issues. The talk will also briefly describe the spacecraft and instrument applications of these chips including: the Cassini mission, Image, Contour, Messenger, Stereo, Pluto, Europa.

  8. A family of analog and mixed signal VLSI ASICs for NASA science missions

    NASA Astrophysics Data System (ADS)

    Paschalidis, Nikolaos P.

    2006-10-01

    This paper presents several analog and mixed signal VLSI chips that have been successfully developed over the past several years at JHU/APL for space science missions. The chips have applications for spacecraft avionics and several types of instrumentation. The family of the chips include: the TRIO smart sensor multiplexed ADC chip for spacecraft/instrument avionics, the time-of-flight (TOF) chip for precise time interval measurement, the CFD chip for time discrimination, the energy chip for low-noise particle/photon measurement, a commandable discriminator pulse high analyzer, event accumulator, a radiation hardened voltage reference, an ADC and other. This paper addresses some design, radiation hard by design, design for testability, testing, and space qualification issues. The paper also briefly describes the spacecraft and instrument applications of these chips including: the NASA missions CASSINI, IMAGE, CONTOUR, MESSENGER, STEREO, PLUTO, oncoming funded missions MMS, JUNO, RBSP, as well as planned planetary and moon missions.

  9. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    NASA Technical Reports Server (NTRS)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  10. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    NASA Technical Reports Server (NTRS)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  11. Asynchronous transfer mode distribution network by use of an optoelectronic VLSI switching chip.

    PubMed

    Lentine, A L; Reiley, D J; Novotny, R A; Morrison, R L; Sasian, J M; Beckman, M G; Buchholz, D B; Hinterlong, S J; Cloonan, T J; Richards, G W; McCormick, F B

    1997-03-10

    We describe a new optoelectronic switching system demonstration that implements part of the distribution fabric for a large asynchronous transfer mode (ATM) switch. The system uses a single optoelectronic VLSI modulator-based switching chip with more than 4000 optical input-outputs. The optical system images the input fibers from a two-dimensional fiber bundle onto this chip. A new optomechanical design allows the system to be mounted in a standard electronic equipment frame. A large section of the switch was operated as a 208-Mbits/s time-multiplexed space switch, which can serve as part of an ATM switch by use of an appropriate out-of-band controller. A larger section with 896 input light beams and 256 output beams was operated at 160 Mbits/s as a slowly reconfigurable space switch. PMID:18250868

  12. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    SciTech Connect

    Pin, F.G.; Pattay, R.S. ); Watanabe, H.; Symon, J. . Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  13. VLSI systems design for digital signal processing. Volume 1 - Signal processing and signal processors

    NASA Astrophysics Data System (ADS)

    Bowen, B. A.; Brown, W. R.

    This book is concerned with the design of digital signal processing systems which utilize VLSI (Very Large Scale Integration) components. The presented material is intended for use by electrical engineers at the senior undergraduate or introductory graduate level. It is the purpose of this volume to present an overview of the important elements of background theory, processing techniques, and hardware evolution. Digital signals are considered along with linear systems and digital filters, taking into account the transform analysis of deterministic signals, a statistical signal model, time domain representations of discrete-time linear systems, and digital filter design techniques and implementation issues. Attention is given to aspects of detection and estimation, digital signal processing algorithms and techniques, issues which must be resolved in a processor design methodology, the fundamental concepts of high performance processing in terms of two early super computers, and the extension of these concepts to more recent processors.

  14. VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation

    NASA Astrophysics Data System (ADS)

    Li, Kang; Yu, Juebang; Li, Jian

    In modern VLSI physical design, huge integration scale necessitates hierarchical design and IP reuse to cope with design complexity. Besides, interconnect delay becomes dominant to overall circuit performance. These critical factors require some modules to be placed along designated boundaries to effectively facilitate hierarchical design and interconnection optimization related problems. In this paper, boundary constraints of general floorplan are solved smoothly based on the novel representation Single-Sequence (SS). Necessary and sufficient conditions of rooms along specified boundaries of a floorplan are proposed and proved. By assigning constrained modules to proper boundary rooms, our proposed algorithm always guarantees a feasible SS code with appropriate boundary constraints in each perturbation. Time complexity of the proposed algorithm is O(n). Experimental results on MCNC benchmarks show effectiveness and efficiency of the proposed method.

  15. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    NASA Astrophysics Data System (ADS)

    Cheely, Matthew; Horiuchi, Timothy

    2003-12-01

    Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  16. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    SciTech Connect

    Pin, F.G.; Pattay, R.S. ); Watanabe, Hiroyuki; Symon, J. . Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  17. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    NASA Technical Reports Server (NTRS)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  18. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  19. Wafer and reticle positioning system for the Extreme Ultraviolet Lithography Engineering Test Stand

    SciTech Connect

    WRONOSKY,JOHN B.; SMITH,TONY G.; CRAIG,MARCUS J.; STURGIS,BEVERLY R.; DARNOLD,JOEL R.; WERLING,DAVID K.; KINCY,MARK A.; TICHENOR,DANIEL A.; WILLIAMS,MARK E.; BISCHOFF,PAUL

    2000-01-27

    This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS is under development at the EUV Virtual National Laboratory, to demonstrate EUV full-field imaging and provide data that supports production-tool development. The stages and their associated metrology operated in a vacuum environment and must meet stringent outgassing specifications. A tight tolerance is placed on the stage tracking performance to minimize image distortion and provide high position repeatability. The wafer must track the reticle with less than {+-}3nm of position error and jitter must not exceed 10nm rms. To meet these performance requirements, magnetically levitated positioning stages utilizing a system of sophisticated control electronics will be used. System modeling and experimentation have contributed to the development of the positioning system and results indicate that desired ETS performance is achievable.

  20. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  1. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  2. Crack propagation and fracture in silicon wafers under thermal stress

    PubMed Central

    Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

    2013-01-01

    The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

  3. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  4. Face-to-face transfer of wafer-scale graphene films.

    PubMed

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  5. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  6. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  7. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    NASA Astrophysics Data System (ADS)

    Calaway, M. J.; Rodriguez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-03-01

    The cleaning efficiency of the Genesis Ultra-pure Water Megasonic Wafer Spin Cleaner will be presented. Results show the effectiveness of the new cleaner removing particle contamination from Genesis silicon wafers implanted with solar wind.

  8. Integrated optical MEMS using through-wafer vias and bump-bonding.

    SciTech Connect

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  9. Switchable adhesion for wafer-handling based on dielectric elastomer stack transducers

    NASA Astrophysics Data System (ADS)

    Grotepaß, T.; Butz, J.; Förster-Zügel, F.; Schlaak, H. F.

    2016-04-01

    Vacuum grippers are often used for the handling of wafers and small devices. In order to evacuate the gripper, a gas flow is created that can harm the micro structures on the wafer. A promising alternative to vacuum grippers could be adhesive grippers with switchable adhesion. There have been some publications of gecko-inspired adhesive devices. Most of these former works consist of a structured surface which adheres to the object manipulated and an actuator for switching the adhesion. Until now different actuator principles have been investigated, like smart memory alloys and pneumatics. In this work for the first time dielectric elastomer stack transducers (DEST) are combined with a structured surface. DESTs are a promising new transducer technology with many applications in different industry sectors like medical devices, human-machine-interaction and soft robotics. Stacked dielectric elastomer transducers show thickness contraction originating from the electromechanical pressure of two compliant electrodes compressing an elastomeric dielectric when a voltage is applied. Since DESTs and the adhesive surfaces previously described are made of elastomers, it is self-evident to combine both systems in one device. The DESTs are fabricated by a spin coating process. If the flat surface of the spinning carrier is substituted for example by a perforated one, the structured elastomer surface and the DEST can be fabricated in one process. By electrical actuation the DEST contracts and laterally expands which causes the gecko-like cilia to adhere on the object to manipulate. This work describes the assembly and the experimental results of such a device using switchable adhesion. It is intended to be used for the handling of glass wafers.

  10. Characteristics and issues of haze management in a wafer fabrication environment

    NASA Astrophysics Data System (ADS)

    Woo, Sung Ha; Hwang, Dae Ho; Jeong, Goo Min; Lee, Young Mo; Kim, Sang Pyo; Yim, Dong Gyu

    2014-10-01

    The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Fortunately, a novel technology which uses a dry (no chemical effluents) removal system, laser-based, through pellicle process has been reported recently. The technology presented here avoids many of the shortcomings of the wet clean process mentioned previously. The dry clean process extends the life of the photomask; maintains more consistent CD's, phase, and transmission; avoids adjustment to the exposure dose to account for photomask changes, reduces the number of required inspections and otherwise improves the efficiency and predictability of the lithography cell. We report on the performance of photomask based on a design developed to study the impact of metrology variations on dry clean process. In a first step we focus on basic characteristics: CD variation, phase, Cr/MoSi transmission, pellicle transmission, registration variations. In a second step, we evaluate haze removal and prevention performance and wafer photo margin. Haze removal is studied on the masks for several haze types and various exposure conditions. The results of this study show that some of metrology variation are likely to be a problem at high technology node, and haze removal performance is determined whether the component of haze is remained or not after treatment.

  11. Wafer bonding process for building MEMS devices

    NASA Astrophysics Data System (ADS)

    Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

    2014-06-01

    The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

  12. A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system.

    PubMed

    Shen, Mingya; Xiao, Feng; Alameh, Kamal

    2009-12-01

    A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

  13. Rinsing of wafers after wet processing: Simulation and experiments

    NASA Astrophysics Data System (ADS)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second

  14. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  15. Wafer-level Au-Au bonding in the 350-450 °C temperature range

    NASA Astrophysics Data System (ADS)

    Tofteberg, Hannah R.; Schjølberg-Henriksen, Kari; Fasting, Eivind J.; Moen, Alexander S.; Taklo, Maaike M. V.; Poppe, Erik U.; Simensen, Christian J.

    2014-08-01

    Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au-Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au-Si eutectic temperature 363 °C is recommended.

  16. High-Level Synthesis of VLSI Processors for Intelligent Integrated SystemsBased on Logic-in-Memory Structure

    NASA Astrophysics Data System (ADS)

    Kudoh, Takao; Kameyama, Michitaka

    One of the most serious problems in recent VLSI systems is data transfer bottleneck between memories and processing elements. To solve the problem, a model of highly parallel VLSI processors for intelligent integrated systems is presented. A logic-in-memory module composed of a processing element, a register and a local memory is defined as a basic building block to form a regular parallel structure. The data transfer between adjacent modules are done simply in a single clock period by a shift-register chain. A high-level synthesis method is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of an chip area. That is, we consider the best scheduling together with allocation such that the processing time becomes minimum under a constraint of a fixed number of modules. Not only an exhaustive enumeration method but also a branch-and-bound method is proposed for the problem. As a result, it is made clear that the proposed high-level synthesis method is very effective to design special-purpose VLSI processors free from data transfer bottleneck.

  17. Height inspection of wafer bumps without explicit 3D reconstruction

    NASA Astrophysics Data System (ADS)

    Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

    2006-02-01

    The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and

  18. An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

    PubMed

    Shih, Wei-Yeh; Liao, Jui-Chieh; Huang, Kuan-Ju; Fang, Wai-Chi; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2013-01-01

    This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763.

  19. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  20. E-beam inspection system for comparison of wafer and design data

    NASA Astrophysics Data System (ADS)

    Patterson, Oliver D.; Lee, Julie; Monkowski, Michael D.; Ryan, Deborah A.; Chen, Shih-tsung; Lei, Shuen C.; Wang, Fei; Lee, Chung H.; Tomlinson, Derek; Fang, Wei; Jau, Jack

    2012-03-01

    Effectively patterning the intended design on the wafer for all possible geometries allowed by the design rule document is one of the most critical challenges for semiconductor manufacturing. Despite new lithography techniques like OPC, double patterning and the latest patterning simulation methods, and on-wafer evaluation using brightfield inspection and SEM review tools, patterning problems still occur and can result in a major delay in the qualification of a technology or product. Of particular concern are shorts and opens that cause product chip failure. Initial discovery of yield issues when a chip is being functionally tested is highly undesirable. A system for in-line, die to database (D2DB) comparison using E-beam inspection has been developed to address this risk. This system offers a substantial new line of defense against these patterning issues. The D2DB system is described along with a methodology for applying it for pattern fidelity inspection. Some examples illustrating the system operation are presented.

  1. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

    PubMed Central

    Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

    2016-01-01

    The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers. PMID:27657087

  2. Characterization of Boron Diffusion Phenomena According to the Specific Resistivity of N-Type Si Wafer.

    PubMed

    Lee, Woo-Jin; Choi, Chel-Jong; Park, Gye-Choon; Yang, O-Bong

    2016-02-01

    This paper is directed to characterize the boron diffusion process according to the specific resistivity of the Si wafer. N-type Si wafers were used with the specific resistivity of 0.5-3.2 omega-cm, 1.0-6.5 omega-cm and 2.0-8.0 omega-cm. The boron tribromide (BBr3) was used as boron source to create the PN junction on N-type Si wafer. The boron diffusion in N-type Si wafer was characterized by sheet resistance of wafer surface, secondary ion mass spectroscopy measurements (SIMS) and surface life time analysis. The degree of boron diffusion was depended on the variation in specific resistivity and sheet resistance of the bare N-type Si wafer. The boron diffused N-Si wafer exhibited the average junction depth of 750 nm and boron concentration of 1 x 10(19). N-type Si wafer with the different specific resistance considerably affected the boron diffusion length and life time of Si wafer. It was found that the lifetime of boron diffused wafer was proportional to the sheet resistance and resistivity. However, optimization process may necessary to achieve the high efficiency through the high sheet resistance wafer, because the metallization process control is very sensitive.

  3. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  4. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  5. Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

    NASA Astrophysics Data System (ADS)

    Xianglong, Zhu; Renke, Kang; Zhigang, Dong; Guang, Feng

    2011-10-01

    Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (>= 300 mm) silicon wafers for integrated circuits. It is important, but insufficiently studied, to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables. In this paper, the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed. A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed. Based on the proposed configuration, an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived. The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

  6. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  7. A photo-sensor on thin polysilicon membrane embedded in wafer level package LED

    NASA Astrophysics Data System (ADS)

    Kim, Jin Kwan; Lee, Hee Chul

    2012-06-01

    A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

  8. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  9. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  10. Towards reduced impact of EUV mask defectivity on wafer

    NASA Astrophysics Data System (ADS)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  11. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  12. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  13. Physical mechanisms of copper-copper wafer bonding

    SciTech Connect

    Rebhan, B.; Hingerl, K.

    2015-10-07

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  14. Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

    NASA Astrophysics Data System (ADS)

    Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

    2011-08-01

    This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

  15. Bulk Laser Material Modification: Towards a Kerfless Laser Wafering Process

    NASA Astrophysics Data System (ADS)

    LeBeau, James

    Due to the ever increasing relevance of finer machining control as well as necessary reduction in material waste by large area semiconductor device manufacturers, a novel bulk laser machining method was investigated. Because the cost of silicon and sapphire substrates are limiting to the reduction in cost of devices in both the light emitting diode (LED) and solar industries, and the present substrate wafering process results in >50% waste, the need for an improved ingot wafering technique exists. The focus of this work is the design and understanding of a novel semiconductor wafering technique that utilizes the nonlinear absorption properties of band-gapped materials to achieve bulk (subsurface) morphological changes in matter using highly focused laser light. A method and tool was designed and developed to form controlled damage regions in the bulk of a crystalline sapphire wafer leaving the surfaces unaltered. The controllability of the subsurface damage geometry was investigated, and the effect of numerical aperture of the focusing optic, energy per pulse, wavelength, and number of pulses was characterized for a nanosecond pulse length variable wavelength Nd:YAG OPO laser. A novel model was developed to describe the geometry of laser induced morphological changes in the bulk of semiconducting materials for nanosecond pulse lengths. The beam propagation aspect of the model was based on ray-optics, and the full Keldysh multiphoton photoionization theory in conjuncture with Thornber's and Drude's models for impact ionization were used to describe high fluence laser light absorption and carrier generation ultimately resulting in permanent material modification though strong electron-plasma absorption and plasma melting. Although the electron-plasma description of laser damage formation is usually reserved for extremely short laser pulses (<20 ps), this work shows that it can be adapted for longer pulses of up to tens of nanoseconds. In addition to a model

  16. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  17. The optimization of FA/O barrier slurry with respect to removal rate selectivity on patterned Cu wafers

    NASA Astrophysics Data System (ADS)

    Yi, Hu; Yan, Li; Yuling, Liu; Yangang, He

    2016-02-01

    Because the polishing of different materials is required in barrier chemical mechanical planarization (CMP) processes, the development of a kind of barrier slurry with improved removal rate selectivity for Cu/barrier/TEOS would reduce erosion and dishing defects on patterned Cu wafers. In this study, we developed a new benzotriazole-free barrier slurry named FA/O barrier slurry, containing 20 mL/L of the chelating agent FA/O, 5 mL/L surfactant, and a 1:5 concentration of abrasive particles. By controlling the polishing slurry ingredients, the removal rate of different materials could be controlled. For process integration considerations, the effect of the FA/O barrier slurry on the dielectric layer of the patterned Cu wafer was investigated. After CMP processing by the FA/O barrier slurry, the characteristics of the dielectric material were tested. The results showed that the dielectric characteristics met demands for industrial production. The current leakage was of pA scale. The resistance and capacitance were 2.4 kω and 2.3 pF, respectively. The dishing and erosion defects were both below 30 nm in size. CMP-processed wafers using this barrier slurry could meet industrial production demands. Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Natural Science Foundation of Hebei Province (No. F2012202094), and the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226).

  18. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  19. Functional test generation of digital LSI/VLSI systems using machine symbolic execution technique

    SciTech Connect

    Lin, T.

    1985-01-01

    Functional testing is among the promising solutions proposed in recent years for the challenging problems of testing modern digital LSI/VLSI systems. It is aimed at validating the correct operation of a digital system with respect to its functional specification. Functional test generation is performed before functional testing. In this dissertation, a functional test pattern generation algorithm is developed. This algorithm is explicit, systematic, and practical. The whole research work consists of five related topics including theoretical development and computer experiment. First, a register transfer language specially designed for the functional description of a general digital system is defined. Second, a register-transfer (RT) level fault model quite different from the conventional gate-level stuck-at fault model is established and the fault collapsing analysis is performed for better test generation efficiency. Third, the technique of register-transfer-level symbolic execution is explored. The major problems are defined, analyzed, and solved. A register-transfer-level symbolic execution system is designed and implemented. Fourth, an overall RT-level test pattern generation algorithm is developed based on the RT-level fault model and the RT-level symbolic execution technique. The symbolic executions are performed on both fault-free and fault-injected machines for symbolic results. By comparing the symbolic results and path constraints obtained from fault-free and fault-injected machines, an input test pattern which distinguishes each bad machine from the good machine is derived.

  20. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    NASA Astrophysics Data System (ADS)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  1. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    NASA Astrophysics Data System (ADS)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  2. Low-noise custom VLSI for CdZnTe pixel detectors

    NASA Astrophysics Data System (ADS)

    Cook, Walter R.; Burnham, Jill A.; Harrison, Fiona A.

    1998-11-01

    A custom analog VLSI chip is being developed for the readout of pixelated CdZnTe detectors in the focal plane of an astronomical hard x-ray telescope. The chip is intended for indium bump bonding to a pixel detector having pitch near 0.5 mm. A complete precision analog signal processing chain, including charge sensitive preamplifier, shaping amplifiers and peak detect and hold circuit, is provided for each pixel. Here we describe the circuitry and discus the performance of a functional prototype fabricated in a 1.2 micrometers CMOS process at Orbit Semiconductor. Dynamic performance is found to be close to SPICE model predictions over a self-triggering range extending from 1 to 50 keV. Integral non-linearity and noise while acceptable ar not as god as predicted. Power consumption is only 250 uW per pixel. Layout and design techniques are discussed which permit successful self-triggering operation at the low 1 keV threshold.

  3. A deterministic BIST scheme for test time reduction in VLSI circuits

    NASA Astrophysics Data System (ADS)

    Solana, Jose M.

    2005-06-01

    A Built-In Self-Test scheme for VLSI scan-based digital circuits, capable of considerably reducing the number of test cycles, is presented. The core circuit structure consists of a modification of the original scan-based circuit requiring no extra I/O pin. Only a moderate area increment is used to accommodate the extra test circuitry. The structure does not use scan-out, but scan-in exclusively, which implies that the complete circuit responses are observed through the circuit primary-outputs. Based on this structure, a deterministic ROM-based Built-In Self-Test scheme has been developed. In this scheme, the circuit responses are compressed in a Multiple-Input Signature Register. Deterministic test patterns are stored in two ROMs. The first stores the sub-patterns to be serially loaded into the scan chain, while the second stores the sub-patterns to be applied in parallel to the circuit primary inputs. All the control bits for clocks and for selecting the loading of a new sub-pattern into the scan chain are also included in this last ROM. Thus, the clocks and the select-mode input are the only external inputs to the scheme. The comparison of the proposed scheme with a similar one, based on the classical full single-serial scan-path, for a set of benchmark circuits, shows a 19% reduction in ROM-bits, while a reduction of over 45% in the test time is obtained.

  4. A novel algorithm and its VLSI architecture for connected component labeling

    NASA Astrophysics Data System (ADS)

    Zhao, Hualong; Sang, Hongshi; Zhang, Tianxu

    2011-11-01

    A novel line-based streaming labeling algorithm with its VLSI architecture is proposed in this paper. Line-based neighborhood examination scheme is used for efficient local connected components extraction. A novel reversed rooted tree hook-up strategy, which is very suitable for hardware implementation, is applied on the mergence stage of equivalent connected components. The reversed rooted tree hook-up strategy significant reduces the requirement of on-chip memory, which makes the chip area smaller. Clock domains crossing FIFOs are also applied for connecting the label core and external memory interface, which makes the label engine working in a higher frequency and raises the throughput of the label engine. Several performance tests have been performed for our proposed hardware implementation. The processing bandwidth of our hardware architecture can reach the I/O transfer boundary according to the external interface clock in all the real image tests. Beside the advantage of reducing the processing time, our hardware implementation can support the image size as large as 4096*4096, which will be very appealing in remote sensing or any other high-resolution image applications. The implementation of proposed architecture is synthesized with SMIC 180nm standard cell library. The work frequency of the label engine reaches 200MHz.

  5. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    PubMed

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system. PMID:18249973

  6. Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

    NASA Astrophysics Data System (ADS)

    L'Insalata, Nicola E.; Saponara, Sergio; Fanucci, Luca; Terreni, Pierangelo

    This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.

  7. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    PubMed

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  8. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    NASA Technical Reports Server (NTRS)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  9. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI

    PubMed Central

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of “high” and “low”-firing activity. Depending on the overall excitability, transitions to the “high” state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the “high” state retains a “working memory” of a stimulus until well after its release. In the latter case, “high” states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated “corrupted” “high” states comprising neurons of both excitatory populations. Within a “basin of attraction,” the network dynamics “corrects” such states and re-establishes the prototypical “high” state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons. PMID:22347151

  10. Wafer-scale high-throughput ordered growth of vertically aligned ZnO nanowire arrays.

    PubMed

    Wei, Yaguang; Wu, Wenzhuo; Guo, Rui; Yuan, Dajun; Das, Suman; Wang, Zhong Lin

    2010-09-01

    This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices.

  11. Indium Zinc Oxide Mediated Wafer Bonding for III-V/Si Tandem Solar Cells

    SciTech Connect

    Tamboli, Adele C.; Essig, Stephanie; Horowitz, Kelsey A. W.; Woodhouse, Michael; van Hest, Maikel F. A. M.; Norman, Andrew G.; Steiner, Myles A.; Stradins, Paul

    2015-06-14

    Silicon-based tandem solar cells are desirable as a high efficiency, economically viable approach to one sun or low concentration photovoltaics. We present an approach to wafer bonded III-V/Si solar cells using amorphous indium zinc oxide (IZO) as an interlayer. We investigate the impact of a heavily doped III-V contact layer on the electrical and optical properties of bonded test samples, including the predicted impact on tandem cell performance. We present economic modeling which indicates that the path to commercial viability for bonded cells includes developing low-cost III-V growth and reducing constraints on material smoothness. If these challenges can be surmounted, bonded tandems on Si can be cost-competitive with incumbent PV technologies, especially in low concentration, single axis tracking systems.

  12. GaAs wafer overlay performance affected by annealing heat treatment: II

    NASA Astrophysics Data System (ADS)

    Liu, Ying; Black, Iain

    2002-07-01

    Further analysis on how wafer distortion affecting the overlay performance during annealing treatment in GaAs wafer fabrication was conducted quantitatively using MONO-LITH software. The experimental results were decomposed as wafer translation, scaling at X and Y direction, rotation and orthogonality. The grid residual was used to describe non- correctable distortion of the wafers, which fits the equations given below: Residual equals Measured - Modeled, which is not a modeled component. The Vector Map displays distribution of error vectors over the wafer or field for various components or overall effect. Based on the component analysis that the misalignment caused by translation and scaling can be compensated by heat treatment if the wafer is placed at a favorable orientation. This can help mitigate the effects of substrate quality in manufactory.

  13. Generation and detection of guided waves using PZT wafer transducers.

    PubMed

    Nieuwenhuis, Jeroen H; Neumann, John J; Greve, David W; Oppenheim, Irving J

    2005-11-01

    We report here the use of finite element simulation and experiments to further explore the operation of the wafer transducer. We have separately modeled the emission and detection processes. In particular, we have calculated the wave velocities and the received voltage signals due to A0 and S0 modes at an output transducer as a function of pulse center frequency. These calculations include the effects of finite pulse width, pulse dispersion, and the detailed interaction between the piezoelectric element and the transmitting medium. We show that the received signals for A0 and S0 modes have maxima near the frequencies predicted from the previously published point-force model.

  14. THz quantum cascade lasers with wafer bonded active regions.

    PubMed

    Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

    2012-10-01

    We demonstrate terahertz quantum-cascade lasers with a 30 μm thick double-metal waveguide, which are fabricated by stacking two 15 μm thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current.

  15. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  16. Network analyzer calibration for cryogenic on-wafer measurements

    SciTech Connect

    Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

    1994-04-01

    A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

  17. Characterization of wafer charging mechanisms and oxide survival prediction methodology

    SciTech Connect

    Lukaszek, W.; Dixon, W.; Vella, M.; Messick, C.; Reno, S.; Shideler, J.

    1994-04-01

    Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

  18. Phosphorus-induced positive charge in native oxide of silicon wafers

    NASA Astrophysics Data System (ADS)

    Shimizu, Hirofumi; Munakata, Chusuke

    1994-06-01

    Alternating current surface photovoltage is enhanced in p-type silicon (Si) wafers, which are rinsed with a phosphorus (P)-contaminated water solution, whereas it is reduced in n-type Si wafers, indicating that the positive charge appears at wafer surfaces. This result suggests that P reacts with SiO2 in the form of (POSi)+ network, causing a positive charge in the native oxide.

  19. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  20. Influence of temperature and backside roughness on the emissivity of Si wafers during rapid thermal processing

    NASA Astrophysics Data System (ADS)

    Vandenabeele, Peter; Maex, Karen

    1992-12-01

    The influence of temperature and roughness on the backside emissivity of Si wafers was studied. In situ measurements were done in two commercial rapid thermal processing systems. An experimental setup was built for in situ emissivity measurements of wafers with a polished or nonpolished backside. The emissivity of double-side polished wafers was measured for temperatures ranging from 300 to 700 °C and at wavelengths of 1.7 and 3.4 μm. It was found that the absorption coefficient α of lightly doped silicon is described by the equation α=4.15×10-5λ1.51T2.95 exp(-7000/T) cm-1, for wavelengths λ ranging from 1.5 to 5 μm and temperatures T ranging from 673 to 973 K (λ in μm, T in K). The backside emissivity of Si wafers with different roughnesses was measured. At temperatures above 600-700 °C the wafers are opaque and the emissivity is only slightly dependent on backside roughness. At lower temperatures the wafers are partially transparent and the emissivity is strongly dependent on the backside roughness of the wafer due to light trapping in the bulk of the wafer. For the latter case a new model was developed to simulate the emissivity of wafers with a rough backside at low temperatures.

  1. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    PubMed

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers.

  2. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  3. Determination of wafer center position during the transfer process by using the beam-breaking method

    NASA Astrophysics Data System (ADS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  4. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    PubMed

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers. PMID:27248817

  5. Ambient condition laser writing of graphene structures on polycrystalline SiC thin film deposited on Si wafer

    SciTech Connect

    Yue, Naili; Zhang, Yong; Tsu, Raphael

    2013-02-18

    We report laser induced local conversion of polycrystalline SiC thin-films grown on Si wafers into multi-layer graphene, a process compatible with the Si based microelectronic technologies. The conversion can be achieved using a 532 nm CW laser with as little as 10 mW power, yielding {approx}1 {mu}m graphene discs without any mask. The conversion conditions are found to vary with the crystallinity of the film. More interestingly, the internal structure of the graphene disc, probed by Raman imaging, can be tuned with varying the film and illumination parameters, resembling either the fundamental or doughnut mode of a laser beam.

  6. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  7. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    PubMed

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  8. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    NASA Technical Reports Server (NTRS)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  9. Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications

    SciTech Connect

    Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

    1999-07-20

    We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

  10. Deposition and removal of sodium contamination on silicon wafers

    NASA Astrophysics Data System (ADS)

    Constant, I.; Tardif, F.; Derrien, J.

    2000-01-01

    In this paper investigations are performed in order to understand the source of sodium contamination in clean-room environments and to find different cleaning processes able to limit or suppress sodium deposition. In a clean-room environment, the human being has been identified as one of the major sources of sodium. The airborne sodium contamination is essentially transmitted in particle form. In order to limit sodium deposition from the air, the wafers awaiting subsequent processing need to be stored in a protective box or placed far from the human environment and should not be left for much more than 1 week in a class 1 clean room. Also, wet chemistries could cause sodium contamination on wafers particularly during the deionized water rinse. In order to limit the possible contamination, the sodium deposition mechanisms have been studied: they show the typical characteristics of Langmuir adsorption. Temperature and ionic concentration are both parameters which influence the deposition. In water, sodium deposition can be avoided by introducing acid or alkaline solutions or increasing the temperature: it can be drastically reduced by adding traces of HCl (0.01%). Finally, other cleaning chemistries such as SC1 (NH4 OH-H2 O2 -H2 O) in 0.25:1:5 proportion, SC2 (HCl-H2 O2 -H2 O) in 1:1:5 proportion, 0.1% HF and SPM (H2 SO4 -H2 O2 ) in 3:1 proportion reduce the contamination as well.

  11. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  12. Video-rate fuzzy Golay processor for wafer scale integration

    SciTech Connect

    Steinvorth, R.H.

    1987-01-01

    The fuzzy Golay transformation is a novel approach for gray-level image processing. Fuzzy-set theory is used to modify the binary image processing techniques developed by M. J. Golay to permit direct gray-level image processing without thresholding. The comparison between gray-level pixels is accomplished with the Pixel Closeness Value (PCV) while comparison between gray-level neighborhoods uses the Neighborhood Closeness Value (NCV). Feature extraction is done by comparing the gray-level image neighborhood to a subset of the fourteen Golay neighborhoods using the NCV function. The Fuzzy Golay Processor (FGP) is an architecture designed to implement the fuzzy Golay transformation. The design of the FGP has been optimized to permit a successful implementation in Wafer Scale Integration (WSI). A system containing four FGPs is capable of performing thirty fuzzy Golay transformations per second on a 256 by 256 eight-bit pixel image. Such a system could fit on a four-inch wafer with enough redundant dies to allow a 30% die yield. The required dies are four Input-Output Modules (IOM) and 56 Neighborhood Evaluation Modules (NEM).

  13. Improving scanner wafer alignment performance by target optimization

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  14. Process Performance of Optima XEx Single Wafer High Energy Implanter

    SciTech Connect

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

  15. Technology.

    ERIC Educational Resources Information Center

    Callison, Daniel

    2002-01-01

    Discussion of technology focuses on instructional technology. Topics include inquiry and technology; curriculum development; reflection and curriculum evaluation; criteria for technological innovations that will increase student motivation; standards; impact of new technologies on library media centers; software; and future trends. (LRW)

  16. Molded, wafer level optics for long wave infra-red applications

    NASA Astrophysics Data System (ADS)

    Franks, John

    2016-05-01

    For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

  17. Elastic Softening of Surface Acoustic Wave Caused by Vacancy Orbital in Silicon Wafer

    NASA Astrophysics Data System (ADS)

    Mitsumoto, Keisuke; Akatsu, Mitsuhiro; Baba, Shotaro; Takasu, Rie; Nemoto, Yuichi; Goto, Terutaka; Yamada-Kaneta, Hiroshi; Furumura, Yuji; Saito, Hiroyuki; Kashima, Kazuhiko; Saito, Yoshihiko

    2014-03-01

    We have performed surface acoustic wave (SAW) measurements to examine vacancies in a surface layer of a boron-doped silicon wafer currently used in semiconductor industry. A SAW with a frequency of fs = 517 MHz was optimally generated by an interdigital transducer with a comb gap of w=2.5 µm on a piezoelectric ZnO film deposited on the (001) silicon surface. The SAW propagating along the [100] axis with a velocity of vs=4.967 km/s is in agreement with the Rayleigh wave, which shows an ellipsoidal trajectory motion in the displacement components ux and uz within a penetration depth of λp = 3.5 µm. The elastic constant Cs of the SAW revealed the softening of ΔCs/Cs = 1.9 × 10-4 below 2 K down to 23 mK. Applied magnetic fields of up to 2 T completely suppress the softening. The quadrupole susceptibilities based on the coupling between the electric quadrupoles Ou, Ov, and Ozx of the vacancy orbital consisting of Γ8-Γ7 states and the symmetry strains ɛu, ɛv, and ɛzx associated with the SAW account for the softening and its field dependence on Cs. We deduced a low vacancy concentration N = 3.1 × 1012/cm3 in the surface layer within λp = 3.5 µm of the silicon wafer. This result promises an innovative technology for vacancy evaluation in the fabrication of high-density semiconductor devices in industry.

  18. Reticle process monitoring and qualification based on reticle CDU and wafer CDU correlation

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Choi, Byoung Il; Holfeld, Christian; Ngow, Yee Ta; Tan, Sia Kim; Tchikoulaeva, Anna; Gn, Fang Hong

    2011-11-01

    Reticle process of record (POR) sometimes needs fine tuning for some reasons such as multiple layer process, better critical dimension uniformity (CDU) or new etch chamber. The sidewall angle and corner rounding will be varied due to the reticle processing tuned comparing to previous POR. However, because the reticle critical dimension (CD) measurement is based on middle side lobe measurement or other algorithm, the reticle CD cannot reflect the changes of reticle sidewall angle and corner rounding variation which are critical for 65nm node and below. Each of the scanner, wafer process, reticle and metrology tool contributes to the intra-field wafer CD. Normally, the reticle contribution to the wafer CDU should be as small as possible, that is less than 33%. By averaging all wafer CD of individual features to obtain a wafer CD reference independent of feature location and wafer die, the correlation of wafer measurement to target (MTT) and reticle MTT can be obtained. The correlation can accurately qualify and monitor the tuning processing of reticle. We have manufactured two masks for active layer of 65nm tech node by different reticle process. One used the original POR process of active layer, while another used multi-layer-reticle (MLR) process. The correlations between wafer CDU and reticle CDU of these reticles are demonstrated for both isolated and dense features in vertical and horizontal direction, respectively. Similar experiments were implemented and the correlations for both dense and isolated structures are demonstrated as well, for two different POR process for first metal layer of 40nm tech node. Referring to the wafer and reticle MTT correlation, the contribution of reticle CDU to wafer CDU can be used as an evaluation methodology for reticle processing. The wafer and reticle CDU correlations for 45nm node poly and contact layers POR process are also demonstrated.

  19. A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits

    NASA Technical Reports Server (NTRS)

    Palumbo, Daniel L.; Finelli, George B.

    1987-01-01

    Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability.

  20. Controlling state explosion during automatic verification of delay-insensitive and delay-constrained VLSI systems using the POM verifier

    NASA Technical Reports Server (NTRS)

    Probst, D.; Jensen, L.

    1991-01-01

    Delay-insensitive VLSI systems have a certain appeal on the ground due to difficulties with clocks; they are even more attractive in space. We answer the question, is it possible to control state explosion arising from various sources during automatic verification (model checking) of delay-insensitive systems? State explosion due to concurrency is handled by introducing a partial-order representation for systems, and defining system correctness as a simple relation between two partial orders on the same set of system events (a graph problem). State explosion due to nondeterminism (chiefly arbitration) is handled when the system to be verified has a clean, finite recurrence structure. Backwards branching is a further optimization. The heart of this approach is the ability, during model checking, to discover a compact finite presentation of the verified system without prior composition of system components. The fully-implemented POM verification system has polynomial space and time performance on traditional asynchronous-circuit benchmarks that are exponential in space and time for other verification systems. We also sketch the generalization of this approach to handle delay-constrained VLSI systems.