Anodic bonding using SOI wafer for fabrication of capacitive micromachined ultrasonic transducers

NASA Astrophysics Data System (ADS)

Bellaredj, M.; Bourbon, G.; Walter, V.; Le Moal, P.; Berthillier, M.

2014-02-01

In medical ultrasound imaging, mostly piezoelectric crystals are used as ultrasonic transducers. Capacitive micromachined ultrasonic transducers (CMUTs) introduced around 1994 have been shown to be a good alternative to conventional piezoelectric transducers in various aspects, such as sensitivity, transduction efficiency or bandwidth. This paper focuses on a fabrication process for CMUTs using anodic bonding of a silicon on insulator wafer on a glass wafer. The processing steps are described leading to a good control of the mechanical response of the membrane. This technology makes possible the fabrication of large membranes and can extend the frequency range of CMUTs to lower frequencies of operation. Silicon membranes having radii of 50, 70, 100 and 150 µm and a 1.5 µm thickness are fabricated and electromechanically characterized using an auto-balanced bridge impedance analyzer. Resonant frequencies from 0.6 to 2.3 MHz and an electromechanical coupling coefficient around 55% are reported. The effects of residual stress in the membranes and uncontrolled clamping conditions are clearly responsible for the discrepancies between experimental and theoretical values of the first resonance frequency. The residual stress in the membranes is determined to be between 90 and 110 MPa. The actual boundary conditions are between the clamped condition and the simply supported condition and can be modeled with a torsional stiffness of 2.10-7 Nm rad-1 in the numerical model.

Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

NASA Astrophysics Data System (ADS)

Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

2015-02-01

This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439 ) at particle velocities of up to 9.6 mm s-1 inside the chip.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

A thermal microprobe fabricated with wafer-stage processing

NASA Astrophysics Data System (ADS)

Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

1998-05-01

A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

PubMed

Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

2014-12-07

We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated.

Wafer-scale Fabrication of Non-Polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification.

PubMed

Zhu, Tongtong; Liu, Yingjun; Ding, Tao; Fu, Wai Yuen; Jarman, John; Ren, Christopher Xiang; Kumar, R Vasant; Oliver, Rachel A

2017-03-27

Distributed Bragg reflectors (DBRs) are essential components for the development of optoelectronic devices. For many device applications, it is highly desirable to achieve not only high reflectivity and low absorption, but also good conductivity to allow effective electrical injection of charges. Here, we demonstrate the wafer-scale fabrication of highly reflective and conductive non-polar gallium nitride (GaN) DBRs, consisting of perfectly lattice-matched non-polar (11-20) GaN and mesoporous GaN layers that are obtained by a facile one-step electrochemical etching method without any extra processing steps. The GaN/mesoporous GaN DBRs exhibit high peak reflectivities (>96%) across the entire visible spectrum and wide spectral stop-band widths (full-width at half-maximum >80 nm), while preserving the material quality and showing good electrical conductivity. Such mesoporous GaN DBRs thus provide a promising and scalable platform for high performance GaN-based optoelectronic, photonic, and quantum photonic devices.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Development and fabrication of a solar cell junction processing system

NASA Technical Reports Server (NTRS)

Bunker, S.

1981-01-01

A solar cell junction processing system was developed and fabricated. A pulsed electron beam for the four inch wafers is being assembled and tested, wafers were successfully pulsed, and solar cells fabricated. Assembly of the transport locks is completed. The transport was operated successfully but not with sufficient reproducibility. An experiment test facility to examine potential scaleup problems associated with the proposed ion implanter design was constructed and operated. Cells were implanted and found to have efficiency identical to the normal Spire implant process.

A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

NASA Astrophysics Data System (ADS)

Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

2016-08-01

This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

Wafer-fused semiconductor radiation detector

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Wafer-level colinearity monitoring for TFH applications

NASA Astrophysics Data System (ADS)

Moore, Patrick; Newman, Gary; Abreau, Kelly J.

2000-06-01

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines

HED-TIE: A wafer-scale approach for fabricating hybrid electronic devices with trench isolated electrodes

NASA Astrophysics Data System (ADS)

Banerjee, Sreetama; Bülz, Daniel; Solonenko, Dmytro; Reuter, Danny; Deibel, Carsten; Hiller, Karla; Zahn, Dietrich R. T.; Salvan, Georgeta

2017-05-01

Organic-inorganic hybrid electronic devices (HEDs) offer opportunities for functionalities that are not easily obtainable with either organic or inorganic materials individually. In the strive for down-scaling the channel length in planar geometry HEDs, the best results were achieved with electron beam lithography or nanoimprint lithography. Their application on the wafer level is, however, cost intensive and time consuming. Here, we propose trench isolated electrode (TIE) technology as a fast, cost effective, wafer-level approach for the fabrication of planar HEDs with electrode gaps in the range of 100 nm. We demonstrate that the formation of the organic channel can be realized by deposition from solution as well as by the thermal evaporation of organic molecules. To underline one key feature of planar HED-TIEs, namely full accessibility of the active area of the devices by external stimuli such as light, 6,13-bis (triisopropylsilylethynyl) (TIPS)-pentacene/Au HED-TIEs are successfully tested for possible application as hybrid photodetectors in the visible spectral range.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

A front-end wafer-level microsystem packaging technique with micro-cap array

NASA Astrophysics Data System (ADS)

Chiang, Yuh-Min

2002-09-01

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

Developing quartz wafer mold manufacturing process for patterned media

NASA Astrophysics Data System (ADS)

Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

2009-04-01

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.

PubMed

Hossain, Md Nazmul; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

2014-09-05

Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Enhancing Scheduling Performance for a Wafer Fabrication Factory: The Biobjective Slack-Diversifying Nonlinear Fluctuation-Smoothing Rule

PubMed Central

Chen, Toly; Wang, Yu Cheng

2012-01-01

A biobjective slack-diversifying nonlinear fluctuation-smoothing rule (biSDNFS) is proposed in the present work to improve the scheduling performance of a wafer fabrication factory. This rule was derived from a one-factor bi-objective nonlinear fluctuation-smoothing rule (1f-biNFS) by dynamically maximizing the standard deviation of the slack, which has been shown to benefit scheduling performance by several previous studies. The efficacy of the biSDNFS was validated with a simulated case; evidence was found to support its effectiveness. We also suggested several directions in which it can be exploited in the future. PMID:23509446

Scheduling revisited workstations in integrated-circuit fabrication

NASA Technical Reports Server (NTRS)

Kline, Paul J.

1992-01-01

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

SuperCDMS Underground Detector Fabrication Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Platt, M.; Mahapatra, R.; Bunker, Raymond A.

The SuperCDMS SNOLAB dark matter experiment processes Ge and Si crystals into fully tested phonon and ionization detectors at surface fabrication and test facilities. If not mitigated, it is anticipated that trace-level production of radioisotopes in the crystals due to exposure to cosmic rays at (or above) sea level will result in the dominant source of background events in future dark matter searches using the current SuperCDMS detector technology. Fabrication and testing of detectors in underground facilities shielded from cosmic radiation is one way to directly reduce production of trace levels of radioisotopes, thereby improving experimental sensitivity for the discoverymore » of dark matter beyond the level of the current experiment. In this report, we investigate the cost and feasibility to establish a complete detector fabrication processing chain in an underground location to mitigate cosmogenic activation of the Ge and Si detector substrates. For a specific and concrete evaluation, we explore options for such a facility located at SNOLAB, an underground laboratory in Sudbury, Canada hosting the current and future experimental phases of SuperCDMS.« less

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Graphene photodetectors with a bandwidth  >76 GHz fabricated in a 6″ wafer process line

NASA Astrophysics Data System (ADS)

Schall, Daniel; Porschatis, Caroline; Otto, Martin; Neumaier, Daniel

2017-03-01

In recent years, the data traffic has grown exponentially and the forecasts indicate a huge market that could be addressed by communication infrastructure and service providers. However, the processing capacity, space, and energy consumption of the available technology is a serious bottleneck for the exploitation of these markets. Chip-integrated optical communication systems hold the promise of significantly improving these issues related to the current technology. At the moment, the answer to the question which material is best suited for ultrafast chip integrated communication systems is still open. In this manuscript we report on ultrafast graphene photodetectors with a bandwidth of more than 76 GHz well suitable for communication links faster than 100 GBit s-1 per channel. We extract an upper value of 7.2 ps for the timescale in which the bolometric photoresponse in graphene is generated. The photodetectors were fabricated on 6″ silicon-on-insulator wafers in a semiconductor pilot line, demonstrating the scalable fabrication of high-performance graphene based devices.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Facile fabrication of a silicon nanowire sensor by two size reduction steps for detection of alpha-fetoprotein biomarker of liver cancer

NASA Astrophysics Data System (ADS)

Binh Pham, Van; ThanhTung Pham, Xuan; Nhat Khoa Phan, Thanh; Thanh Tuyen Le, Thi; Chien Dang, Mau

2015-12-01

We present a facile technique that only uses conventional micro-techniques and two size-reduction steps to fabricate wafer-scale silicon nanowire (SiNW) with widths of 200 nm. Initially, conventional lithography was used to pattern SiNW with 2 μm width. Then the nanowire width was decreased to 200 nm by two size-reduction steps with isotropic wet etching. The fabricated SiNW was further investigated when used with nanowire field-effect sensors. The electrical characteristics of the fabricated SiNW devices were characterized and pH sensitivity was investigated. Then a simple and effective surface modification process was carried out to modify SiNW for subsequent binding of a desired receptor. The complete SiNW-based biosensor was then used to detect alpha-fetoprotein (AFP), one of the medically approved biomarkers for liver cancer diagnosis. Electrical measurements showed that the developed SiNW biosensor could detect AFP with concentrations of about 100 ng mL-1. This concentration is lower than the necessary AFP concentration for liver cancer diagnosis.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

Pulse plating of Pt on n-GaAs ( 1 0 0 ) wafer surfaces: Synchrotron induced photoelectron spectroscopy and XPS of wet fabrication processes

NASA Astrophysics Data System (ADS)

Ensling, D.; Hunger, R.; Kraft, D.; Mayer, Th.; Jaegermann, W.; Rodriguez-Girones, M.; Ichizli, V.; Hartnagel, H. L.

2003-01-01

Preparation steps of Pt/n-GaAs Schottky contacts as applied in the fabrication process of varactor diode arrays for THz applications are analysed by photoelectron spectroscopy. Pulsed cathodic deposition of Pt onto GaAs (1 0 0) wafer surfaces from acidic solution has been studied by core level photoelectron spectroscopy using different excitation energies. A laboratory AlKα source as well as synchrotron radiation of hν=130 and 645 eV at BESSY was used. Chemical analyses and semiquantitative estimates of layer thickness are given for the natural oxide of an untreated wafer surface, a surface conditioning NH 3 etching step, and stepwise pulse plating of Pt. The structural arrangement of the detected species and interface potentials are considered.

Disc resonator gyroscope fabrication process requiring no bonding alignment

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor)

2010-01-01

A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

Wafer-scale plasmonic and photonic crystal sensors

NASA Astrophysics Data System (ADS)

George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

2015-08-01

200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Epitaxial gallium arsenide wafers

NASA Technical Reports Server (NTRS)

Black, J. F.; Robinson, L. B.

1971-01-01

The preparation of GaAs epitaxial layers by a vapor transport process using AsCl3, Ga and H2 was pursued to provide epitaxial wafers suitable for the fabrication of transferred electron oscillators and amplifiers operating in the subcritical region. Both n-n(+) structures, and n(++)-n-n(+) sandwich structures were grown using n(+) (Si-doped) GaAs substrates. Process variables such as the input AsCl3 concentration, gallium temperature, and substrate temperature and temperature gradient and their effects on properties are presented and discussed.

Wafer-level radiometric performance testing of uncooled microbolometer arrays

NASA Astrophysics Data System (ADS)

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Wafer-shape metrics based foundry lithography

NASA Astrophysics Data System (ADS)

Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

2017-03-01

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Fabricating with crystalline Si to improve superconducting detector performance

NASA Astrophysics Data System (ADS)

Beyer, A. D.; Hollister, M. I.; Sayers, J.; Frez, C. F.; Day, P. K.; Golwala, S. R.

2017-05-01

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Fabrication of an X-Ray Imaging Detector

NASA Technical Reports Server (NTRS)

Alcorn, G. E.; Burgess, A. S.

1986-01-01

X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

1.3 μm wavelength vertical cavity surface emitting laser fabricated by orientation-mismatched wafer bonding: A prospect for polarization control

NASA Astrophysics Data System (ADS)

Okuno, Yae L.; Geske, Jon; Gan, Kian-Giap; Chiu, Yi-Jen; DenBaars, Steven P.; Bowers, John E.

2003-04-01

We propose and demonstrate a long-wavelength vertical cavity surface emitting laser (VCSEL) which consists of a (311)B InP-based active region and (100) GaAs-based distributed Bragg reflectors (DBRs), with an aim to control the in-plane polarization of output power. Crystal growth on (311)B InP substrates was performed under low-migration conditions to achieve good crystalline quality. The VCSEL was fabricated by wafer bonding, which enables us to combine different materials regardless of their lattice and orientation mismatch without degrading their quality. The VCSEL was polarized with a power extinction ratio of 31 dB.

Wafer integrated micro-scale concentrating photovoltaics

NASA Astrophysics Data System (ADS)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

Wafer-level fabrication of arrays of glass lens doublets

NASA Astrophysics Data System (ADS)

Passilly, Nicolas; Perrin, Stéphane; Albero, Jorge; Krauter, Johann; Gaiffe, Olivier; Gauthier-Manuel, Ludovic; Froehly, Luc; Lullin, Justine; Bargiel, Sylwester; Osten, Wolfgang; Gorecki, Christophe

2016-04-01

Systems for imaging require to employ high quality optical components in order to dispose of optical aberrations and thus reach sufficient resolution. However, well-known methods to get rid of optical aberrations, such as aspherical profiles or diffractive corrections are not easy to apply to micro-optics. In particular, some of these methods rely on polymers which cannot be associated when such lenses are to be used in integrated devices requiring high temperature process for their further assembly and separation. Among the different approaches, the most common is the lens splitting that consists in dividing the focusing power between two or more optical components. In here, we propose to take advantage of a wafer-level technique, devoted to the generation of glass lenses, which involves thermal reflow in silicon cavities to generate lens doublets. After the convex lens sides are generated, grinding and polishing of both stack sides allow, on the first hand, to form the planar lens backside and, on the other hand, to open the silicon cavity. Nevertheless, silicon frames are then kept and thinned down to form well-controlled and auto-aligned spacers between the lenses. Subsequent accurate vertical assembly of the glass lens arrays is performed by anodic bonding. The latter ensures a high level of alignment both laterally and axially since no additional material is required. Thanks to polishing, the generated lens doublets are then as thin as several hundreds of microns and compatible with micro-opto-electro-systems (MOEMS) technologies since they are only made of glass and silicon. The generated optical module is then robust and provide improved optical performances. Indeed, theoretically, two stacked lenses with similar features and spherical profiles can be almost diffraction limited whereas a single lens characterized by the same numerical aperture than the doublet presents five times higher wavefront error. To demonstrate such assumption, we fabricated glass

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

NASA Astrophysics Data System (ADS)

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Stable wafer-carrier system

DOEpatents

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Modifications of Fabrication of Vibratory Microgyroscopes

NASA Technical Reports Server (NTRS)

Bae, Sam Y.; Yee, Karl Y.; Wiberg, Dean

2005-01-01

A micromachining process for the fabrication of vibratory microgyroscopes from silicon wafers, and aspects of the microgyroscope design that are inextricably linked with the fabrication process, have been modified in an effort to increase production yields from perspectives of both quantity and quality. Prior to the modifications, the effective production yield of working microgyroscopes was limited to one or less per wafer. The modifications are part of a continuing effort to improve the design and increase production yields to more than 30 working microgyroscopes per wafer. A discussion of pertinent aspects of the unmodified design and the unmodified fabrication process is prerequisite to a meaningful description of the modifications. The design of the microgyroscope package was not conducive to high yield and rapid testing of many microgyroscopes. One of the major impediments to high yield and testing was found to lie in vibration- isolation beams around the four edges of each microgyroscope, which beams were found to be unnecessary for achieving high resonance quality factors (Q values) characterizing the vibrations of petallike cantilevers. The fabrication process included an 8- m-deep plasma etch. The purpose of the etch was to create 8- m vertical gaps, below which were to be placed large gold evaporated electrodes and sensing pads to drive and sense resonant vibrations of the "petals." The process also included a step in which bridges between dies were cut to separate the dies. The etched areas must be kept clean and smooth (free of debris and spikes), because any object close to 8 m high in those areas would stop the vibrations. However, it was found that after the etch, there remained some spikes with heights that were, variously, almost as high or as high as the etch depth. It also was found that the cutting of bridges created silicon debris, some of which lodged in the 8- m gaps and some of which landed on top of the petals. The masses added to the

Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

NASA Astrophysics Data System (ADS)

Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

2003-09-01

The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

Wafer level reliability for high-performance VLSI design

NASA Technical Reports Server (NTRS)

Root, Bryan J.; Seefeldt, James D.

1987-01-01

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

Fabrication of an Absorber-Coupled MKID Detector

NASA Technical Reports Server (NTRS)

Brown, Ari; Hsieh, Wen-Ting; Moseley, Samuel; Stevenson, Thomas; U-Yen, Kongpop; Wollack, Edward

2012-01-01

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a

Wafer-scale high-throughput ordered arrays of Si and coaxial Si/Si(1-x)Ge(x) wires: fabrication, characterization, and photovoltaic application.

PubMed

Pan, Caofeng; Luo, Zhixiang; Xu, Chen; Luo, Jun; Liang, Renrong; Zhu, Guang; Wu, Wenzhuo; Guo, Wenxi; Yan, Xingxu; Xu, Jun; Wang, Zhong Lin; Zhu, Jing

2011-08-23

We have developed a method combining lithography and catalytic etching to fabricate large-area (uniform coverage over an entire 5-in. wafer) arrays of vertically aligned single-crystal Si nanowires with high throughput. Coaxial n-Si/p-SiGe wire arrays are also fabricated by further coating single-crystal epitaxial SiGe layers on the Si wires using ultrahigh vacuum chemical vapor deposition (UHVCVD). This method allows precise control over the diameter, length, density, spacing, orientation, shape, pattern and location of the Si and Si/SiGe nanowire arrays, making it possible to fabricate an array of devices based on rationally designed nanowire arrays. A proposed fabrication mechanism of the etching process is presented. Inspired by the excellent antireflection properties of the Si/SiGe wire arrays, we built solar cells based on the arrays of these wires containing radial junctions, an example of which exhibits an open circuit voltage (V(oc)) of 650 mV, a short-circuit current density (J(sc)) of 8.38 mA/cm(2), a fill factor of 0.60, and an energy conversion efficiency (η) of 3.26%. Such a p-n radial structure will have a great potential application for cost-efficient photovoltaic (PV) solar energy conversion. © 2011 American Chemical Society

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, C.M.; Hui, W.C.

1996-11-19

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, Conrad M.; Hui, Wing C.

1996-01-01

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Reliable four-point flexion test and model for die-to-wafer direct bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.

2015-07-07

For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, bothmore » D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.« less

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 {mu}m wide (111) sidewalls was fabricated using a 220 {mu}m thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

PubMed

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Maskless wafer-level microfabrication of optical penetrating neural arrays out of soda-lime glass: Utah Optrode Array.

PubMed

Boutte, Ronald W; Blair, Steve

2016-12-01

Borrowing from the wafer-level fabrication techniques of the Utah Electrode Array, an optical array capable of delivering light for neural optogenetic studies is presented in this paper: the Utah Optrode Array. Utah Optrode Arrays are micromachined out of sheet soda-lime-silica glass using standard backend processes of the semiconductor and microelectronics packaging industries such as precision diamond grinding and wet etching. 9 × 9 arrays with 1100μ m × 100μ m optrodes and a 500μ m back-plane are repeatably reproduced on 2i n wafers 169 arrays at a time. This paper describes the steps and some of the common errors of optrode fabrication.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-05-20

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-11-25

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

NASA Technical Reports Server (NTRS)

Horowitz, Stephen; Chen, Tai-An; Chandrasekaran, Venkataraman; Tedjojuwono, Ken; Cattafesta, Louis; Nishida, Toshikazu; Sheplak, Mark

2004-01-01

This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

2008-10-01

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an

450mm wafer patterning with jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Length separation of single-walled carbon nanotubes and its impact on structural and electrical properties of wafer-level fabricated carbon nanotube-field-effect transistors

NASA Astrophysics Data System (ADS)

Böttger, Simon; Hermann, Sascha; Schulz, Stefan E.; Gessner, Thomas

2016-10-01

For an industrial realization of devices based on single-walled carbon nanotube (SWCNTs) such as field-effect transistors (FETs) it becomes increasingly important to consider technological aspects such as intrinsic device structure, integration process controllability as well as yield. From the perspective of a wafer-level integration technology, the influence of SWCNT length on the performance of short-channel CNT-FETs is demonstrated by means of a statistical and comparative study. Therefore, a methodological development of a length separation process based on size-exclusion chromatography was conducted in order to extract well-separated SWCNT dispersions with narrowed length distribution. It could be shown that short SWCNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the integration yield with respect to long SWCNTs. Furthermore, it turns out that the significant changes in electrical performance are directly linked to a SWCNT chain formation in the transistor channel. In particular, CNT-FETs with long SWCNTs outperform reference and short SWCNTs with respect to hole mobility and subthreshold controllability by up to 300% and up to 140%, respectively. As a whole, this study provides a statistical and comparative analysis towards chain-less CNT-FETs fabricated with a wafer-level technology.

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

NASA Astrophysics Data System (ADS)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

NASA Technical Reports Server (NTRS)

Denis, Kevin L. (Inventor)

2018-01-01

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Through-wafer interrogation of microstructure motion for MEMS feedback control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

1999-09-01

Closed-loop MEMS control enables mechanical microsystems to adapt to the demands of the environment which they are actuating opening a new window of opportunity for future MEMS applications. Planar diffractive optical microsystems have the potential to enable the integrated optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation which is central to realization of feedback control. This paper presents the results of initial research evaluating through-wafer optical microsystems for MEMS integrated optical monitoring. Positional monitoring results obtained from a 1.3 micrometer wavelength through- wafer free-space optical probe of a lateral comb resonator fabricated using the Multi-User MEMS Process Service (MUMPS) are presented. Given the availability of positional information via probe signal feedback, a simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

NASA Astrophysics Data System (ADS)

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

PubMed

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

A new fabrication technique for back-to-back varactor diodes

NASA Technical Reports Server (NTRS)

Smith, R. Peter; Choudhury, Debabani; Martin, Suzanne; Frerking, Margaret A.; Liu, John K.; Grunthaner, Frank A.

1992-01-01

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

CMUT Fabrication Based On A Thick Buried Oxide Layer.

PubMed

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O; Khuri-Yakub, Butrus T

2010-10-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required - in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

CMUT Fabrication Based On A Thick Buried Oxide Layer

PubMed Central

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O.; Khuri-Yakub, Butrus T.

2010-01-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required – in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate. PMID:22685377

Fabrication of plastic microparts on wafer level

NASA Astrophysics Data System (ADS)

Weber, Lutz; Ehrfeld, Wolfgang; Begemann, Marc; Berg, Udo; Michel, Frank

1999-08-01

In the recent years micromolding has become one of the most important key technologies of microengineering. At the current state of art, the mass fabrication of plastic microparts for a wide range of applications like telecommunications, sensors, medical technology and biochemistry is feasible. Here a micro motor, plastic optical waveguides, a micro pump, and nanotiterplates are presented.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

Fabrication of Pop-up Detector Arrays on Si Wafers

NASA Technical Reports Server (NTRS)

Li, Mary J.; Allen, Christine A.; Gordon, Scott A.; Kuhn, Jonathan L.; Mott, David B.; Stahle, Caroline K.; Wang, Liqin L.

1999-01-01

High sensitivity is a basic requirement for a new generation of thermal detectors. To meet the requirement, close-packed, two-dimensional silicon detector arrays have been developed in NASA Goddard Space Flight Center. The goal of the task is to fabricate detector arrays configured with thermal detectors such as infrared bolometers and x-ray calorimeters to use in space fliGht missions. This paper focuses on the fabrication and the mechanical testing of detector arrays in a 0.2 mm pixel size, the smallest pop-up detectors being developed so far. These array structures, nicknamed "PUDS" for "Pop-Up Detectors", are fabricated on I pm thick, single-crystal, silicon membranes. Their designs have been refined so we can utilize the flexibility of thin silicon films by actually folding the silicon membranes to 90 degrees in order to obtain close-packed two-dimensional arrays. The PUD elements consist of a detector platform and two legs for mechanical support while also serving as electrical and thermal paths. Torsion bars and cantilevers connecting the detector platform to the legs provide additional flexures for strain relief. Using micro-electromechanical structure (MEMS) fabrication techniques, including photolithography, anisotropic chemical etching, reactive-ion etching, and laser dicing, we have fabricated PLTD detector arrays of fourteen designs with a variation of four parameters including cantilever length, torsion bar length and width, and leg length. Folding tests were conducted to test mechanical stress distribution for the array structures. We obtained folding yields and selected optimum design parameters to reach minimal stress levels. Computer simulation was also employed to verify mechanical behaviors of PUDs in the folding process. In addition, scanning electron microscopy was utilized to examine the flatness of detectors and the alignment of detector pixels in arrays. The fabrication of thermistors and heaters on the pop-up detectors is under way

Switchable adhesion for wafer-handling based on dielectric elastomer stack transducers

NASA Astrophysics Data System (ADS)

Grotepaß, T.; Butz, J.; Förster-Zügel, F.; Schlaak, H. F.

2016-04-01

Vacuum grippers are often used for the handling of wafers and small devices. In order to evacuate the gripper, a gas flow is created that can harm the micro structures on the wafer. A promising alternative to vacuum grippers could be adhesive grippers with switchable adhesion. There have been some publications of gecko-inspired adhesive devices. Most of these former works consist of a structured surface which adheres to the object manipulated and an actuator for switching the adhesion. Until now different actuator principles have been investigated, like smart memory alloys and pneumatics. In this work for the first time dielectric elastomer stack transducers (DEST) are combined with a structured surface. DESTs are a promising new transducer technology with many applications in different industry sectors like medical devices, human-machine-interaction and soft robotics. Stacked dielectric elastomer transducers show thickness contraction originating from the electromechanical pressure of two compliant electrodes compressing an elastomeric dielectric when a voltage is applied. Since DESTs and the adhesive surfaces previously described are made of elastomers, it is self-evident to combine both systems in one device. The DESTs are fabricated by a spin coating process. If the flat surface of the spinning carrier is substituted for example by a perforated one, the structured elastomer surface and the DEST can be fabricated in one process. By electrical actuation the DEST contracts and laterally expands which causes the gecko-like cilia to adhere on the object to manipulate. This work describes the assembly and the experimental results of such a device using switchable adhesion. It is intended to be used for the handling of glass wafers.

CAD/CAM transtibial prosthetic sockets from central fabrication facilities: How accurate are they?

PubMed Central

Sanders, Joan E.; Rogers, Ellen L.; Sorenson, Elizabeth A.; Lee, Gregory S.; Abrahamson, Daniel C.

2014-01-01

This research compares transtibial prosthetic sockets made by central fabrication facilities with their corresponding American Academy of Orthotists and Prosthetists (AAOP) electronic shape files and assesses the central fabrication process. We ordered three different socket shapes from each of 10 manufacturers. Then we digitized the sockets using a very accurate custom mechanical digitizer. Results showed that quality varied considerably among the different manufacturers. Four of the companies consistently made sockets within +/−1.1% volume (approximately 1 sock ply) of the AAOP electronic shape file, while six other companies did not. Six of the companies showed consistent undersizing or oversizing in their sockets, which suggests a consistent calibration or manufacturing error. Other companies showed inconsistent sizing or shape distortion, a difficult problem that represents a most challenging limitation for central fabrication facilities. PMID:18247236

A Wafer Transfer Technology for MEMS Adaptive Optics

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

76 FR 65544 - Standard Format and Content of License Applications for Mixed Oxide Fuel Fabrication Facilities

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-21

...The U.S. Nuclear Regulatory Commission (NRC or Commission) is issuing a revision to regulatory guide (RG) 3.39, ``Standard Format and Content of License Applications for Mixed Oxide Fuel Fabrication Facilities.'' This guide endorses the standard format and content for license applications and integrated safety analysis (ISA) summaries described in the current version of NUREG-1718, ``Standard Review Plan for the Review of an Application for a Mixed Oxide (MOX) Fuel Fabrication Facility,'' as a method that the NRC staff finds acceptable for meeting the regulatory requirements of Title 10 of the Code of Federal Regulations (10 CFR) part 70, ``Domestic Licensing of Special Nuclear Material'' for mixed oxide fuel fabrication facilities.

Complete Fabrication of a Traversable 3 µm Thick NbN Film Superconducting Coil with Cu plated layer of 42m in Length in a Spiral Three-Storied Trench Engraved in a Si Wafer of 76.2 mm in Diameter Formed by MEMS Technology for a Compact SMES with High Energy Storage Volume Density

NASA Astrophysics Data System (ADS)

Suzuki, Yasuhiro; Iguchi, Nobuhiro; Adachi, Kazuhiro; Ichiki, Akihisa; Hioki, Tatsumi; Hsu, Che-Wei; Sato, Ryoto; Kumagai, Shinya; Sasaki, Minoru; Noh, Joo-Hyong; Sakurahara, Yuuske; Okabe, Kyohei; Takai, Osamu; Honma, Hideo; Watanabe, Hideo; Sakoda, Hitoshi; Sasagawa, Hiroaki; Doy, Hideyuki; Zhou, Shuliang; Hori, H.; Nishikawa, Shigeaki; Nozaki, Toshihiro; Sugimoto, Noriaki; Motohiro, Tomoyoshi

2017-09-01

Based on the concept of a novel approach to make a compact SMES unit composed of a stack of Si wafers using MEMS process proposed previously, a complete fabrication of a traversable 3 µam thick NbN film superconducting coil lined with Cu plated layer of 42m in length in a spiral three-storied trench engraved in and extended over a whole Si-wafer of 76.2 mm in diameter was attained for the first time. With decrease in temperature, the DC resistivity showed a metallic decrease indicating the current pass was in the Cu plated layer and then made a sudden fall to residual contact resistance indicating the shift of current pass from the Cu plated layer to the NbN film at the critical temperature Tc of 15.5K by superconducting transition. The temperature dependence of I-V curve showed the increase in the critical current with decrease in the temperature and the highest critical current measured was 220 mA at 4K which is five times as large as that obtained in the test fabrication as the experimental proof of concept presented in the previous report. This completion of a one wafer superconducting NbN coil is an indispensable step for the next proof of concept of fabrication of series-connected two wafer coils via superconductive joint which will read to series connected 600 wafer coils finally, and for replacement of NbN by high Tc superconductor such as YBa2Cu3O7-x for operation under the cold energy of liquid hydrogen or liquid nitrogen.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

NASA Astrophysics Data System (ADS)

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

NASA Astrophysics Data System (ADS)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

NASA Astrophysics Data System (ADS)

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

2014-01-01

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, Ekmel; Tuttle, Gary; Michel, Erick; Ho, Kai-Ming; Biswas, Rana; Chan, Che-Ting; Soukoulis, Costas

1995-01-01

A method for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

DOEpatents

Sopori, Bhushan

2014-05-27

Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

PubMed

Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

2016-05-11

Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials.

Validation of cleaning method for various parts fabricated at a Beryllium facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Davis, Cynthia M.

This study evaluated and documented a cleaning process that is used to clean parts that are fabricated at a beryllium facility at Los Alamos National Laboratory. The purpose of evaluating this cleaning process was to validate and approve it for future use to assure beryllium surface levels are below the Department of Energy’s release limits without the need to sample all parts leaving the facility. Inhaling or coming in contact with beryllium can cause an immune response that can result in an individual becoming sensitized to beryllium, which can then lead to a disease of the lungs called chronic berylliummore » disease, and possibly lung cancer. Thirty aluminum and thirty stainless steel parts were fabricated on a lathe in the beryllium facility, as well as thirty-two beryllium parts, for the purpose of testing a parts cleaning method that involved the use of ultrasonic cleaners. A cleaning method was created, documented, validated, and approved, to reduce beryllium contamination.« less

On the design of GaN vertical MESFETs on commercial LED sapphire wafers

NASA Astrophysics Data System (ADS)

Atalla, Mahmoud R. M.; Noor Elahi, Asim M.; Mo, Chen; Jiang, Zhenyu; Liu, Jie; Ashok, S.; Xu, Jian

2016-12-01

Design of GaN-based vertical metal-semiconductor field-effect transistors (MESFETs) on commercial light-emitting-diode (LED) epi-wafers has been proposed and proof of principle devices have been fabricated. In order to better understand the IV curves, these devices have been simulated using the charge transport model. It was found that shrinking the drain pillar size would significantly help in reaching cut-off at much lower gate bias even at high carrier concentration of unintentionally doped GaN and considerable leakage current caused by the Schottky barrier lowering. The realization of these vertical MESFETs on LED wafers would allow their chip-level integration. This would open a way to many intelligent lighting applications like on-chip current regulator and signal regulation/communication in display technology.

Wafer characteristics via reflectometry

DOEpatents

Sopori, Bhushan L.

2010-10-19

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

THz quantum cascade lasers with wafer bonded active regions.

PubMed

Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

2012-10-08

We demonstrate terahertz quantum-cascade lasers with a 30 μm thick double-metal waveguide, which are fabricated by stacking two 15 μm thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current.

High-wafer-yield, high-performance vertical cavity surface-emitting lasers

NASA Astrophysics Data System (ADS)

Li, Gabriel S.; Yuen, Wupen; Lim, Sui F.; Chang-Hasnain, Constance J.

1996-04-01

Vertical cavity surface emitting lasers (VCSELs) with very low threshold current and voltage of 340 (mu) A and 1.5 V is achieved. The molecular beam epitaxially grown wafers are grown with a highly accurate, low cost and versatile pre-growth calibration technique. One- hundred percent VCSEL wafer yield is obtained. Low threshold current is achieved with a native oxide confined structure with excellent current confinement. Single transverse mode with stable, predetermined polarization direction up to 18 times threshold is also achieved, due to stable index guiding provided by the structure. This is the highest value reported to data for VCSELs. We have established that p-contact annealing in these devices is crucial for low voltage operation, contrary to the general belief. Uniform doping in the mirrors also appears not to be inferior to complicated doping engineering. With these design rules, very low threshold voltage VCSELs are achieved with very simple growth and fabrication steps.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, E.; Tuttle, G.; Michel, E.; Ho, K.M.; Biswas, R.; Chan, C.T.; Soukoulis, C.

1995-04-11

A method is disclosed for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap. 42 figures.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

Effect of wafer geometry on lithography chucking processes

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Sinha, Jaydeep K.

2015-03-01

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

Facile Hydrothermal Preparation of ZNO/CO3O4 Heterogeneous Nanostructures and its Photovoltaic Effect

NASA Astrophysics Data System (ADS)

Wei, Fanan; Jiang, Minlin; Liu, Lianqing

2015-07-01

Photovoltaic technology offers great potential in the replacement of fossil fuel resources, but still suffers from high device fabrication cost. Herein, we attempted to provide a solution to these issues with heterogeneous nanostructures. Firstly, Zinc oxide (ZnO)/cobalt oxide (Co3O4) heterojunction nanowires are prepared through facile fabrication methods. By assembling Co(OH)2 nanoplates on ZnO nanowire arrays, the ZnO/Co3O4 heterogeneous nanostructures are uniformly synthesized on ITO coated glass and wafer. Current (I)-voltage (V) measurement through conductive atomic force microscope shows excellent photovoltaic effect. And, the heterojunction nanostructures shows unprecedented high open circuit voltage. Therefore, the potential application of the heterogeneous nanostructures in solar cells is demonstrated.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

Wafer scale oblique angle plasma etching

DOEpatents

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Methane production using resin-wafer electrodeionization

DOEpatents

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Behind the Scenes at Berkeley Lab - The Mechanical Fabrication Facility

ScienceCinema

Wells, Russell; Chavez, Pete; Davis, Curtis; Bentley, Brian

2018-04-16

Part of the Behind the Scenes series at Berkeley Lab, this video highlights the lab's mechanical fabrication facility and its exceptional ability to produce unique tools essential to the lab's scientific mission. Through a combination of skilled craftsmanship and precision equipment, machinists and engineers work with scientists to create exactly what's needed - whether it's measured in microns or meters.

Fabrication of 20 nm embedded longitudinal nanochannels transferred from metal nanowire patterns

NASA Technical Reports Server (NTRS)

Choi, D.; Yang, E. H.

2003-01-01

bstract we describe a technique for fabricating nanometer-scale channels embedded by dielectric materials. Longitudinal 'embedded ' nanochannels with an opening size 20 nm x 80 nm have been successfully fabricated on silicon wafer by transferring sacrificial nanowire structures.

High-Strength Composite Fabric Tested at Structural Benchmark Test Facility

NASA Technical Reports Server (NTRS)

Krause, David L.

2002-01-01

Large sheets of ultrahigh strength fabric were put to the test at NASA Glenn Research Center's Structural Benchmark Test Facility. The material was stretched like a snare drum head until the last ounce of strength was reached, when it burst with a cacophonous release of tension. Along the way, the 3-ft square samples were also pulled, warped, tweaked, pinched, and yanked to predict the material's physical reactions to the many loads that it will experience during its proposed use. The material tested was a unique multi-ply composite fabric, reinforced with fibers that had a tensile strength eight times that of common carbon steel. The fiber plies were oriented at 0 and 90 to provide great membrane stiffness, as well as oriented at 45 to provide an unusually high resistance to shear distortion. The fabric's heritage is in astronaut space suits and other NASA programs.

A facile and low-cost micro fabrication material: flash foam.

PubMed

He, Yong; Xiao, Xiao; Wu, Yan; Fu, Jian-zhong

2015-08-28

Although many microfabrication methods have been reported, the preliminary replication templates used in most microfabrication still depend on the expensive and long-period photolithography. This paper explores an alternative replication templates based on a daily used material, flash foam (FF), and proposes a facile microfabrication method, flash foam stamp lithography (FFSL). When FF is exposed with a desired pattern mask, the negative of the pattern is transferred to its surface and micro structures are formed due to the shrinkage of the exposed area. As FF is commonly used in personal stamps, FFSL is very simple and cost-effective. In this paper, we demonstrated that FF is a good and low-cost template for many micro fabrication methods, such as micro casting and soft lithography. Thus, designing and fabricating micro structures at personal office immediately become possible with FFSL. Furthermore, we demonstrated that multi-scale micro structures can be easily fabricated by double exposure with FFSL. Skin textures is used as another case to demonstrate that FFSL can fabricate structures with different depth in a single exposure. As a result, FF shows a promising future in biology, and analytical chemistry, such as rapid fabrication of point of care diagnostics and microfluidic analytical devices with low cost.

A facile and low-cost micro fabrication material: flash foam

PubMed Central

He, Yong; Xiao, Xiao; Wu, Yan; Fu, Jian-zhong

2015-01-01

Although many microfabrication methods have been reported, the preliminary replication templates used in most microfabrication still depend on the expensive and long-period photolithography. This paper explores an alternative replication templates based on a daily used material, flash foam (FF), and proposes a facile microfabrication method, flash foam stamp lithography (FFSL). When FF is exposed with a desired pattern mask, the negative of the pattern is transferred to its surface and micro structures are formed due to the shrinkage of the exposed area. As FF is commonly used in personal stamps, FFSL is very simple and cost-effective. In this paper, we demonstrated that FF is a good and low-cost template for many micro fabrication methods, such as micro casting and soft lithography. Thus, designing and fabricating micro structures at personal office immediately become possible with FFSL. Furthermore, we demonstrated that multi-scale micro structures can be easily fabricated by double exposure with FFSL. Skin textures is used as another case to demonstrate that FFSL can fabricate structures with different depth in a single exposure. As a result, FF shows a promising future in biology, and analytical chemistry, such as rapid fabrication of point of care diagnostics and microfluidic analytical devices with low cost. PMID:26314247

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

PubMed Central

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Bio-inspired Fabrication of Complex Hierarchical Structure in Silicon.

PubMed

Gao, Yang; Peng, Zhengchun; Shi, Tielin; Tan, Xianhua; Zhang, Deqin; Huang, Qiang; Zou, Chuanping; Liao, Guanglan

2015-08-01

In this paper, we developed a top-down method to fabricate complex three dimensional silicon structure, which was inspired by the hierarchical micro/nanostructure of the Morpho butterfly scales. The fabrication procedure includes photolithography, metal masking, and both dry and wet etching techniques. First, microscale photoresist grating pattern was formed on the silicon (111) wafer. Trenches with controllable rippled structures on the sidewalls were etched by inductively coupled plasma reactive ion etching Bosch process. Then, Cr film was angled deposited on the bottom of the ripples by electron beam evaporation, followed by anisotropic wet etching of the silicon. The simple fabrication method results in large scale hierarchical structure on a silicon wafer. The fabricated Si structure has multiple layers with uniform thickness of hundreds nanometers. We conducted both light reflection and heat transfer experiments on this structure. They exhibited excellent antireflection performance for polarized ultraviolet, visible and near infrared wavelengths. And the heat flux of the structure was significantly enhanced. As such, we believe that these bio-inspired hierarchical silicon structure will have promising applications in photovoltaics, sensor technology and photonic crystal devices.

A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

NASA Astrophysics Data System (ADS)

Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

2006-11-01

In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Temperature Dependent Electrical Properties of PZT Wafer

NASA Astrophysics Data System (ADS)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

PubMed Central

Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

2015-01-01

Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

NASA Astrophysics Data System (ADS)

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Porous solid ion exchange wafer for immobilizing biomolecules

DOEpatents

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Polyurethane-acrylate-based hydrophobic film: Facile fabrication, characterization, and application

NASA Astrophysics Data System (ADS)

Park, Jongsung; Nguyen, Bui Quoc Huy; Kim, Ji-Kwan; Shanmugasundaram, Arunkumar; Lee, Dong-Weon

2018-06-01

Polyurethane-acrylate (PUA) is a versatile UV-curable polymer with a short curing time at room temperature, whose surface structure can be flexibly modified by applying various micropatterns. In this paper, we propose a facile and cost-effective fabrication method for the continuous production of an optically transparent PUA-based superhydrophobic thin film. Poly(dimethylsiloxane) (PDMS) was employed as a soft mold for the fabrication of PUA films through the roll-to-roll technique. In addition, nanosilica was spray-coated onto the PUA surface to further improve the hydrophobicity. The fabricated PUA thin film showed the highest static water contact angle (WCA) of ∼140°. The high durability of the PUA film was also demonstrated through mechanical impacting tests. Furthermore, only ∼2% of voltage loss was observed in the solar panel covered with the PUA-based superhydrophobic film. These obtained results indicate the feasibility of applying the film as a protective layer in applications requiring a high transparency and a self-cleaning effect.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

Fabrication of high-quality superconductor-insulator-superconductor junctions on thin SiN membranes

NASA Technical Reports Server (NTRS)

Garcia, Edouard; Jacobson, Brian R.; Hu, Qing

1993-01-01

We have successfully fabricated high-quality and high-current density superconductor-insulator-superconductor (SIS) junctions on freestanding thin silicon nitride (SIN) membranes. These devices can be used in a novel millimeter-wave and THz receiver system which is made using micromachining. The SIS junctions with planar antennas were fabricated first on a silicon wafer covered with a SiN membrane, the Si wafer underneath was then etched away using an anisotropic KOH etchant. The current-voltage characteristics of the SIS junctions remained unchanged after the whole process, and the junctions and the membrane survived thermal cycling.

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

NASA Astrophysics Data System (ADS)

Tanake, Katsuaki

We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of

Through-wafer optical probe characterization for microelectromechanical systems positional state monitoring and feedback control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

2000-12-01

Implementation of closed-loop microelectromechanical system (MEMS) control enables mechanical microsystems to adapt to the demands of the environment that they are actuating, opening a broad range of new opportunities for future MEMS applications. Integrated optical microsystems have the potential to enable continuous in situ optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation that is necessary for realization of feedback control. We present the results of initial research evaluating through-wafer optical microprobes for surface micromachined MEMS integrated optical position monitoring. Results from the through-wafer free-space optical probe of a lateral comb resonator fabricated using the multiuser MEMS process service (MUMPS) indicate significant positional information content with an achievable return probe signal dynamic range of up to 80% arising from film transmission contrast. Static and dynamic deflection analysis and experimental results indicate a through-wafer probe positional signal sensitivity of 40 mV/micrometers for the present setup or 10% signal change per micrometer. A simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure given the availability of positional state information.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

NASA Astrophysics Data System (ADS)

Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

2003-09-01

As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

Heating device for semiconductor wafers

DOEpatents

Vosen, Steven R.

1999-01-01

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

Facile fabrication of superhydrophobic surfaces from austenitic stainless steel (AISI 304) by chemical etching

NASA Astrophysics Data System (ADS)

Kim, Jae-Hun; Mirzaei, Ali; Kim, Hyoun Woo; Kim, Sang Sub

2018-05-01

Stainless steels are among the most common engineering materials and are used extensively in humid areas. Therefore, it is important that these materials must be robust to humidity and corrosion. This paper reports the fabrication of superhydrophobic surfaces from austenitic stainless steel (type AISI 304) using a facile two-step chemical etching method. In the first step, the stainless steel plates were etched in a HF solution, followed by a fluorination process, where they showed a water contact angle (WCA) of 166° and a sliding angle of 5° under the optimal conditions. To further enhance the superhydrophobicity, in the second step, they were dipped in a 0.1 wt.% NaCl solution at 100 °C, where the WCA was increased to 168° and the sliding angle was decreased to ∼2°. The long-term durability of the fabricated superhydrophobic samples for 1 month storage in air and water was investigated. The potential applicability of the fabricated samples was demonstrated by the excellent superhydrophobicity after 1 month. In addition, the self-cleaning properties of the fabricated superhydrophobic surface were also demonstrated. This paper outlines a facile, low-cost and scalable chemical etching method that can be adopted easily for large-scale purposes.

Facilely Fabricating Multifunctional N-Enriched Carbon.

PubMed

Wan, Mi Mi; Sun, Xiao Dan; Li, Yan Yan; Zhou, Jun; Wang, Ying; Zhu, Jian Hua

2016-01-20

A new synthetic strategy, named "carbonization in limited space" and based on the specific interaction between eutectic salt and dual-ionic liquids (dual-ILs), is reported in this article. N-Containing dual-ILs (1,4-diethyl-1,4-diazaniabicyclo[2,2,2]octane imidazolide-4,5-dicyanoiazolide, [2C2DABCO](2+)[Im](-)[CN-Im](-)) were synthesized as new carbon-nitrogen precursors, while eutectic salt was chosen as a reuseable template in order to facilely fabricate the N-doped porous carbon with sheetlike morphology. Nitrogen can be directly and efficiently incorporated into the porous carbon, resulting in the materials with suitable N content, tunable pore structure, and controllable thickness of sheet as well as high surface area. They exhibited good performance as electrodes for supercapacitors, photocatalysts in degradation of methyl orange (MO) under visible light, and the sorbent to capture tobacco-specific N-nitrosamines (TSNAs) in solution, offering a new simplified but effective method to prepare versatile carbon material.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

NASA Astrophysics Data System (ADS)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

Heating device for semiconductor wafers

DOEpatents

Vosen, S.R.

1999-07-27

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

[Micro fabricated enzyme battery].

PubMed

Sasaki, S; Karube, I

1996-10-01

Although various work has been done in the field of implantable micro actuators such as artificial organs and micro surgery robots, a suitable electric power supply for these is yet to be developed. For this purpose a micro fabricated enzyme fuel cell was developed which uses glucose contained in the human body as a fuel. In order to obtain enough voltage each cell was formed as part of a serial array on a silicon wafer. Glucose solution enters the cells by a capillary effect. In this article fuel cells already developed using biocatalysts are described, and the future possibility of a micro fabricated enzyme battery is discussed.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Facile fabrication of microfluidic surface-enhanced Raman scattering devices via lift-up lithography

NASA Astrophysics Data System (ADS)

Wu, Yuanzi; Jiang, Ye; Zheng, Xiaoshan; Jia, Shasha; Zhu, Zhi; Ren, Bin; Ma, Hongwei

2018-04-01

We describe a facile and low-cost approach for a flexibly integrated surface-enhanced Raman scattering (SERS) substrate in microfluidic chips. Briefly, a SERS substrate was fabricated by the electrostatic assembling of gold nanoparticles, and shaped into designed patterns by subsequent lift-up soft lithography. The SERS micro-pattern could be further integrated within microfluidic channels conveniently. The resulting microfluidic SERS chip allowed ultrasensitive in situ SERS monitoring from the transparent glass window. With its advantages in simplicity, functionality and cost-effectiveness, this method could be readily expanded into optical microfluidic fabrication for biochemical applications.

Novel On-wafer Radiation Pattern Measurement Technique for MEMS Actuator Based Reconfigurable Patch Antennas

NASA Technical Reports Server (NTRS)

Simons, Rainee N.

2002-01-01

The paper presents a novel on-wafer, antenna far field pattern measurement technique for microelectromechanical systems (MEMS) based reconfigurable patch antennas. The measurement technique significantly reduces the time and the cost associated with the characterization of printed antennas, fabricated on a semiconductor wafer or dielectric substrate. To measure the radiation patterns, the RF probe station is modified to accommodate an open-ended rectangular waveguide as the rotating linearly polarized sampling antenna. The open-ended waveguide is attached through a coaxial rotary joint to a Plexiglas(Trademark) arm and is driven along an arc by a stepper motor. Thus, the spinning open-ended waveguide can sample the relative field intensity of the patch as a function of the angle from bore sight. The experimental results include the measured linearly polarized and circularly polarized radiation patterns for MEMS-based frequency reconfigurable rectangular and polarization reconfigurable nearly square patch antennas, respectively.

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Binary phase digital reflection holograms - Fabrication and potential applications

NASA Technical Reports Server (NTRS)

Gallagher, N. C., Jr.; Angus, J. C.; Coffield, F. E.; Edwards, R. V.; Mann, J. A., Jr.

1977-01-01

A novel technique for the fabrication of binary-phase computer-generated reflection holograms is described. By use of integrated circuit technology, the holographic pattern is etched into a silicon wafer and then aluminum coated to make a reflection hologram. Because these holograms reflect virtually all the incident radiation, they may find application in machining with high-power lasers. A number of possible modifications of the hologram fabrication procedure are discussed.

Characterization of Atomic-Layer-Deposited (ALD) Al2O3-Passivated Sub-50-μm-thick Kerf-less Si Wafers by Controlled Spalling

NASA Astrophysics Data System (ADS)

Lee, Yong Hwan; Cha, Hamchorom; Choi, Sunho; Chang, Hyo Sik; Jang, Boyun; Oh, Jihun

2018-05-01

A systematic characterization of sub-50-μm-thick, kerf-less monocrystalline Si wafers fabricated by a controlled fracture method is presented. The spalling process introduces various defects on the Si surface, which result in high surface roughness levels, residual stress, and low effective minority carrier lifetimes. In addition, metals used to induce fracturing in Si diffuse in the Si at room temperature and degrade the effective minority carrier lifetime. Selective removal of these defected Si regions improves the residual stress and effective lifetimes of spalled Si wafers.

High throughput wafer defect monitor for integrated metrology applications in photolithography

NASA Astrophysics Data System (ADS)

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-03-01

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Wafer hot spot identification through advanced photomask characterization techniques

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2016-10-01

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

Design Study of Wafer Seals for Future Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

PubMed

Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

2015-10-16

A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved.

Wafer-level packaging with compression-controlled seal ring bonding

DOEpatents

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

PRELIMINARY DATA CALL REPORT ADVANCED BURNER REACTOR START UP FUEL FABRICATION FACILITY

DOE Office of Scientific and Technical Information (OSTI.GOV)

S. T. Khericha

2007-04-01

The purpose of this report is to provide data for preparation of a NEPA Environmental Impact Statement in support the U. S. Department of Energy (DOE) Global Nuclear Energy Partnership (GNEP). One of the GNEP objectives is to reduce the inventory of long lived actinide from the light water reactor (LWR) spent fuel. The LWR spent fuel contains Plutonium (Pu) -239 and other transuranics (TRU) such as Americium-241. One of the options is to transmute or burn these actinides in fast neutron spectra as well as generate the electricity. A sodium-cooled Advanced Recycling Reactor (ARR) concept has been proposed tomore » achieve this goal. However, fuel with relatively high TRU content has not been used in the fast reactor. To demonstrate the utilization of TRU fuel in a fast reactor, an Advanced Burner Reactor (ABR) prototype of ARR is proposed, which would necessarily be started up using weapons grade (WG) Pu fuel. The WG Pu is distinguished by relatively highest proportions of Pu-239 and lesser amount of other actinides. The WG Pu will be used as the startup fuel along with TRU fuel in lead test assemblies. Because such fuel is not currently being produced in the US, a new facility (or new capability in an existing facility) is being considered for fabrication of WG Pu fuel for the ABR. This report is provided in response to ‘Data Call’ for the construction of startup fuel fabrication facility. It is anticipated that the facility will provide the startup fuel for 10-15 years and will take to 3 to 5 years to construct.« less

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

Novel wafer stepper with violet LED light source

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Wafer scale fabrication of carbon nanotube thin film transistors with high yield

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tian, Boyuan; Liang, Xuelei, E-mail: liangxl@pku.edu.cn, E-mail: ssxie@iphy.ac.cn; Yan, Qiuping

Carbon nanotube thin film transistors (CNT-TFTs) are promising candidates for future high performance and low cost macro-electronics. However, most of the reported CNT-TFTs are fabricated in small quantities on a relatively small size substrate. The yield of large scale fabrication and the performance uniformity of devices on large size substrates should be improved before the CNT-TFTs reach real products. In this paper, 25 200 devices, with various geometries (channel width and channel length), were fabricated on 4-in. size ridged and flexible substrates. Almost 100% device yield were obtained on a rigid substrate with high out-put current (>8 μA/μm), high on/off current ratiomore » (>10{sup 5}), and high mobility (>30 cm{sup 2}/V·s). More importantly, uniform performance in 4-in. area was achieved, and the fabrication process can be scaled up. The results give us more confidence for the real application of the CNT-TFT technology in the near future.« less

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment

DOEpatents

Farino, A.J.; Montague, S.; Sniegowski, J.J.; Smith, J.H.; McWhorter, P.J.

1998-07-21

A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface. 15 figs.

Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment

DOEpatents

Farino, Anthony J.; Montague, Stephen; Sniegowski, Jeffry J.; Smith, James H.; McWhorter, Paul J.

1998-01-01

A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Big data driven cycle time parallel prediction for production planning in wafer manufacturing

NASA Astrophysics Data System (ADS)

Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

2018-07-01

Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

Modelling deformation and fracture in confectionery wafers

NASA Astrophysics Data System (ADS)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Design and development of wafer-level near-infrared micro-camera

NASA Astrophysics Data System (ADS)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Haldar, Pradeep; Dhar, Nibir K.; Lewis, Jay S.; Wijewarnasuriya, Priyalal; Puri, Yash R.; Sood, Ashok K.

2015-08-01

SiGe offers a low-cost alternative to conventional infrared sensor material systems such as InGaAs, InSb, and HgCdTe for developing near-infrared (NIR) photodetector devices that do not require cooling and can offer high bandwidths and responsivities. As a result of the significant difference in thermal expansion coefficients between germanium and silicon, tensile strain incorporated into Ge epitaxial layers deposited on Si utilizing specialized growth processes can extend the operational range of detection to 1600 nm and longer wavelengths. We have fabricated SiGe based PIN detector devices on 300 mm diameter Si wafers in order to take advantage of high throughput, large-area complementary metal-oxide semiconductor (CMOS) technology. This device fabrication process involves low temperature epitaxial deposition of Ge to form a thin p+ seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. An n+-Ge layer formed by ion implantation of phosphorus, passivating oxide cap, and then top copper contacts complete the PIN photodetector design. Various techniques including transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS) have been employed to characterize the material and structural properties of the epitaxial growth and fabricated detector devices. In addition, electrical characterization was performed to compare the I-V dark current vs. photocurrent response as well as the time and wavelength varying photoresponse properties of the fabricated devices, results of which are likewise presented.

Fabrication of close-packed TES microcalorimeter arrays using superconducting molybdenum/gold transition-edge sensors

NASA Astrophysics Data System (ADS)

Finkbeiner, F. M.; Brekosky, R. P.; Chervenak, J. A.; Figueroa-Feliciano, E.; Li, M. J.; Lindeman, M. A.; Stahle, C. K.; Stahle, C. M.; Tralshawala, N.

2002-02-01

We present an overview of our efforts in fabricating Transition-Edge Sensor (TES) microcalorimeter arrays for use in astronomical x-ray spectroscopy. Two distinct types of array schemes are currently pursued: 5×5 single pixel TES array where each pixel is a TES microcalorimeter, and Position-Sensing TES (PoST) array. In the latter, a row of 7 or 15 thermally-linked absorber pixels is read out by two TES at its ends. Both schemes employ superconducting Mo/Au bilayers as the TES. The TES are placed on silicon nitride membranes for thermal isolation from the structural frame. The silicon nitride membranes are prepared by a Deep Reactive Ion Etch (DRIE) process into a silicon wafer. In order to achieve the concept of closely packed arrays without decreasing its structural and functional integrity, we have already developed the technology to fabricate arrays of cantilevered pixel-sized absorbers and slit membranes in silicon nitride films. Furthermore, we have started to investigate ultra-low resistance through-wafer micro-vias to bring the electrical contact out to the back of a wafer. .

Modelling deformation and fracture in confectionery wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon

2015-01-22

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which wasmore » then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.« less

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

NASA Technical Reports Server (NTRS)

Reck, Theodore (Inventor); Perez, Jose Vicente Siles (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Jung-Kubiak, Cecile (Inventor); Mehdi, Imran (Inventor); Chattopadhyay, Goutam (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Fabrication of microchannels in polycrystalline diamond using pre-fabricated Si substrates

NASA Astrophysics Data System (ADS)

Chandran, Maneesh; Elfimchev, Sergey; Michaelson, Shaul; Akhvlediani, Rozalia; Ternyak, Orna; Hoffman, Alon

2017-10-01

In this paper, we report on a simple, feasible method to fabricate microchannels in diamond. Polycrystalline diamond microchannels were produced by fabricating trenches in a Si wafer and subsequently depositing a thin layer of diamond onto this substrate using the hot filament vapor deposition technique. Fabrication of trenches in the Si substrate at different depths was carried out by standard photolithography, and the subsequent deposition of the diamond layer was performed by the hot filament chemical vapor deposition technique. The growth mechanism of diamond that leads to the formation of closed diamond microchannels is discussed in detail based on the Knudsen number and growth chemistry of diamond. Variations in the crystallite size, crystalline quality, and thickness of the diamond layer along the trench depths were systematically analyzed using cross-sectional scanning electron microscopy and Raman spectroscopy. Defect density and formation of non-diamond forms of carbon in the diamond layer were found to increase with the trench depth, which sets a limit of 5-45 μm trench depth (or an aspect ratio of 1-9) for the fabrication of diamond microchannels using this method under the present conditions.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Wafering economies for industrialization from a wafer manufacturer's viewpoint

NASA Technical Reports Server (NTRS)

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Chelant Enhanced Solution Processing for Wafer Scale Synthesis of Transition Metal Dichalcogenide Thin Films.

PubMed

Ionescu, Robert; Campbell, Brennan; Wu, Ryan; Aytan, Ece; Patalano, Andrew; Ruiz, Isaac; Howell, Stephen W; McDonald, Anthony E; Beechem, Thomas E; Mkhoyan, K Andre; Ozkan, Mihrimah; Ozkan, Cengiz S

2017-07-25

It is of paramount importance to improve the control over large area growth of high quality molybdenum disulfide (MoS 2 ) and other types of 2D dichalcogenides. Such atomically thin materials have great potential for use in electronics, and are thought to make possible the first real applications of spintronics. Here in, a facile and reproducible method of producing wafer scale atomically thin MoS 2 layers has been developed using the incorporation of a chelating agent in a common organic solvent, dimethyl sulfoxide (DMSO). Previously, solution processing of a MoS 2 precursor, ammonium tetrathiomolybdate ((NH 4 ) 2 MoS 4 ), and subsequent thermolysis was used to produce large area MoS 2 layers. Our work here shows that the use of ethylenediaminetetraacetic acid (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demonstrate that the chelating action and dispersing effect of EDTA is critical in growing uniform films. Raman spectroscopy, photoluminescence (PL), x-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM) and high-resolution scanning transmission electron microscopy (HR-STEM) indicate the formation of homogenous few layer MoS 2 films at the wafer scale, resulting from the novel chelant-in-solution method.

Mechanical Strength and Broadband Transparency Improvement of Glass Wafers via Surface Nanostructures.

PubMed

Kumar, Amarendra; Kashyap, Kunal; Hou, Max T; Yeh, J Andrew

2016-06-17

In this study, we mechanically strengthened a borosilicate glass wafer by doubling its bending strength and simultaneously enhancing its transparency using surface nanostructures for different applications including sensors, displays and panels. A fabrication method that combines dry and wet etching is used for surface nanostructure fabrication. Specifically, we improved the bending strength of plain borosilicate glass by 96% using these surface nanostructures on both sides. Besides bending strength improvement, a limited optical transmittance enhancement of 3% was also observed in the visible light wavelength region (400-800 nm). Both strength and transparency were improved by using surface nanostructures of 500 nm depth on both sides of the borosilicate glass without affecting its bulk properties or the glass manufacturing process. Moreover, we observed comparatively smaller fragments during the breaking of the nanostructured glass, which is indicative of strengthening. The range for the nanostructure depth is defined for different applications with which improvements of the strength and transparency of borosilicate glass substrate are obtained.

Mechanical Strength and Broadband Transparency Improvement of Glass Wafers via Surface Nanostructures

PubMed Central

Kumar, Amarendra; Kashyap, Kunal; Hou, Max T.; Yeh, J. Andrew

2016-01-01

In this study, we mechanically strengthened a borosilicate glass wafer by doubling its bending strength and simultaneously enhancing its transparency using surface nanostructures for different applications including sensors, displays and panels. A fabrication method that combines dry and wet etching is used for surface nanostructure fabrication. Specifically, we improved the bending strength of plain borosilicate glass by 96% using these surface nanostructures on both sides. Besides bending strength improvement, a limited optical transmittance enhancement of 3% was also observed in the visible light wavelength region (400–800 nm). Both strength and transparency were improved by using surface nanostructures of 500 nm depth on both sides of the borosilicate glass without affecting its bulk properties or the glass manufacturing process. Moreover, we observed comparatively smaller fragments during the breaking of the nanostructured glass, which is indicative of strengthening. The range for the nanostructure depth is defined for different applications with which improvements of the strength and transparency of borosilicate glass substrate are obtained. PMID:27322276

Fabrication of terahertz metamaterials using electrohydrodynamic jet printing for sensitive detection of yeast

NASA Astrophysics Data System (ADS)

Pradhipta Tenggara, Ayodya; Park, S. J.; Teguh Yudistira, Hadi; Ahn, Y. H.; Byun, Doyoung

2017-03-01

We demonstrated the fabrication of terahertz metamaterial sensor for the accurate and on-site detection of yeast using electrohydrodynamic jet printing, which is inexpensive, simple, and environmentally friendly. The very small sized pattern up to 5 µm-width of electrical split ring resonator unit structures could be printed on a large area on both a rigid substrate and flexible substrate, i.e. silicon wafer and polyimide film using the drop on demand technique to eject liquid ink containing silver nanoparticles. Experimental characterization and simulation were performed to study their performances in detecting yeast of different weights. It was shown that the metamaterial sensor fabricated on a flexible polyimide film had higher sensitivity by more than six times than the metamaterial sensor fabricated on a silicon wafer, due to the low refractive index of the PI substrate and due to the extremely thin substrate thickness which lowers the effective index further. The resonance frequency shift saturated when the yeast weights were 145 µg and 215 µg for metamaterial structures with gap size 6.5 µm fabricated on the silicon substrate and on the polyimide substrate, respectively.

Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

NASA Astrophysics Data System (ADS)

Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

2006-03-01

The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

NASA Astrophysics Data System (ADS)

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-03-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

PubMed Central

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-01-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

Method of Fabricating a Composite Apparatus

NASA Technical Reports Server (NTRS)

Wilkie, W. Keats (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Hellbaum, Richard F. (Inventor); High, James W. (Inventor); Jalink, Antony, Jr. (Inventor)

2007-01-01

A method for fabricating a piezoelectric macro-fiber composite actuator comprises making a piezoelectric fiber sheet by providing a plurality of wafers of piezoelectric material, bonding the wafers together with an adhesive material to from a stack of alternating layers of piezoelectric material and adhesive material, and cutting through the stack in a direction substantially parallel to the thickness of the stack and across the alternating layers of piezoelectric material and adhesive material to provide at least one piezoelectric fiber sheet having two sides comprising a plurality of piezoelectric fibers in juxtaposition to the adhesive material. The method further comprises bonding two electrically conductive films to the two sides of the piezoelectric fiber sheet. At least one conductive film has first and second conductive patterns formed thereon which are electrically isolated from one another and in electrical contact with the piezoelectric fiber sheet.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Facile fabrication of BiVO4 nanofilms with controlled pore size and their photoelectrochemical performances

NASA Astrophysics Data System (ADS)

Feng, Chenchen; Jiao, Zhengbo; Li, Shaopeng; Zhang, Yan; Bi, Yingpu

2015-12-01

We demonstrate a facile method for the rational fabrication of pore-size controlled nanoporous BiVO4 photoanodes, and confirmed that the optimum pore-size distributions could effectively absorb visible light through light diffraction and confinement functions. Furthermore, in situ X-ray photoelectron spectroscopy (XPS) reveals more efficient photoexcited electron-hole separation than conventional particle films, induced by light confinement and rapid charge transfer in the inter-crossed worm-like structures.We demonstrate a facile method for the rational fabrication of pore-size controlled nanoporous BiVO4 photoanodes, and confirmed that the optimum pore-size distributions could effectively absorb visible light through light diffraction and confinement functions. Furthermore, in situ X-ray photoelectron spectroscopy (XPS) reveals more efficient photoexcited electron-hole separation than conventional particle films, induced by light confinement and rapid charge transfer in the inter-crossed worm-like structures. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr06584d

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

NASA Astrophysics Data System (ADS)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Fabrication of Continuous Microfibers Containing Magnetic Nanoparticles by a Facile Magneto-Mechanical Drawing

NASA Astrophysics Data System (ADS)

Li, Jin-Tao; Jia, Xian-Sheng; Yu, Gui-Feng; Yan, Xu; He, Xiao-Xiao; Yu, Miao; Gong, Mao-Gang; Ning, Xin; Long, Yun-Ze

2016-09-01

A facile method termed magneto-mechanical drawing is used to produce polymer composite microfibers. Compared with electrospinning and other fiber spinning methods, magneto-mechanical drawing uses magnetic force generated by a permanent magnet to draw droplets of polymer/magnetic nanoparticle suspensions, leading to fabrication of composite microfibers. In addition, because of the rotating collector, it is easy to control the fiber assembly such as fibrous array in parallel or crossed fibrous structure. The general applicability of this method has also been proved by spinning different polymers and magnetic nanoparticles. The resultant fibers exhibit good superparamagnetic behavior at room temperature and ultrahigh stretchability (~443.8 %). The results indicate that magneto-mechanical drawing is a promising technique to fabricate magnetic and stretchable microfibers and devices.

Fabrication of Continuous Microfibers Containing Magnetic Nanoparticles by a Facile Magneto-Mechanical Drawing.

PubMed

Li, Jin-Tao; Jia, Xian-Sheng; Yu, Gui-Feng; Yan, Xu; He, Xiao-Xiao; Yu, Miao; Gong, Mao-Gang; Ning, Xin; Long, Yun-Ze

2016-12-01

A facile method termed magneto-mechanical drawing is used to produce polymer composite microfibers. Compared with electrospinning and other fiber spinning methods, magneto-mechanical drawing uses magnetic force generated by a permanent magnet to draw droplets of polymer/magnetic nanoparticle suspensions, leading to fabrication of composite microfibers. In addition, because of the rotating collector, it is easy to control the fiber assembly such as fibrous array in parallel or crossed fibrous structure. The general applicability of this method has also been proved by spinning different polymers and magnetic nanoparticles. The resultant fibers exhibit good superparamagnetic behavior at room temperature and ultrahigh stretchability (~443.8 %). The results indicate that magneto-mechanical drawing is a promising technique to fabricate magnetic and stretchable microfibers and devices.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

From magic to technology: materials integration by wafer bonding

NASA Astrophysics Data System (ADS)

Dragoi, Viorel

2006-02-01

Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

NASA Technical Reports Server (NTRS)

Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

1986-01-01

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Mask-to-wafer alignment system

DOEpatents

Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

2003-11-04

A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

WaferOptics® mass volume production and reliability

NASA Astrophysics Data System (ADS)

Wolterink, E.; Demeyer, K.

2010-05-01

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

Fabrication of flexible and vertical silicon nanowire electronics.

PubMed

Weisse, Jeffrey M; Lee, Chi Hwan; Kim, Dong Rip; Zheng, Xiaolin

2012-06-13

Vertical silicon nanowire (SiNW) array devices directly connected on both sides to metallic contacts were fabricated on various non-Si-based substrates (e.g., glass, plastics, and metal foils) in order to fully exploit the nanomaterial properties for final applications. The devices were realized with uniform length Ag-assisted electroless etched SiNW arrays that were detached from their fabrication substrate, typically Si wafers, reattached to arbitrary substrates, and formed with metallic contacts on both sides of the NW array. Electrical characterization of the SiNW array devices exhibits good current-voltage characteristics consistent with the SiNW morphology.

Facile Fabrication of Multi-hierarchical Porous Polyaniline Composite as Pressure Sensor and Gas Sensor with Adjustable Sensitivity

NASA Astrophysics Data System (ADS)

He, Xiao-Xiao; Li, Jin-Tao; Jia, Xian-Sheng; Tong, Lu; Wang, Xiao-Xiong; Zhang, Jun; Zheng, Jie; Ning, Xin; Long, Yun-Ze

2017-08-01

A multi-hierarchical porous polyaniline (PANI) composite which could be used in good performance pressure sensor and adjustable sensitivity gas sensor has been fabricated by a facile in situ polymerization. Commercial grade sponge was utilized as a template scaffold to deposit PANI via in situ polymerization. With abundant interconnected pores throughout the whole structure, the sponge provided sufficient surface for the growth of PANI nanobranches. The flexible porous structure helped the composite to show high performance in pressure detection with fast response and favorable recoverability and gas detection with adjustable sensitivity. The sensing mechanism of the PANI/sponge-based flexible sensor has also been discussed. The results indicate that this work provides a feasible approach to fabricate efficient sensors with advantages of low cost, facile preparation, and easy signal collection.

Facile Fabrication of Multi-hierarchical Porous Polyaniline Composite as Pressure Sensor and Gas Sensor with Adjustable Sensitivity.

PubMed

He, Xiao-Xiao; Li, Jin-Tao; Jia, Xian-Sheng; Tong, Lu; Wang, Xiao-Xiong; Zhang, Jun; Zheng, Jie; Ning, Xin; Long, Yun-Ze

2017-12-01

A multi-hierarchical porous polyaniline (PANI) composite which could be used in good performance pressure sensor and adjustable sensitivity gas sensor has been fabricated by a facile in situ polymerization. Commercial grade sponge was utilized as a template scaffold to deposit PANI via in situ polymerization. With abundant interconnected pores throughout the whole structure, the sponge provided sufficient surface for the growth of PANI nanobranches. The flexible porous structure helped the composite to show high performance in pressure detection with fast response and favorable recoverability and gas detection with adjustable sensitivity. The sensing mechanism of the PANI/sponge-based flexible sensor has also been discussed. The results indicate that this work provides a feasible approach to fabricate efficient sensors with advantages of low cost, facile preparation, and easy signal collection.

Structural fabrication quality as a factor of industrial facilities safety

NASA Astrophysics Data System (ADS)

Tishkov, E. V.; Kardaev, E. M.; Stolbova, S. Yu; Shishova, O. S.

2018-04-01

In the conditions of industrial facilities high wear degree, it is very important to ensure the possibility of their safe operation in order to avoid various kinds of accidents and catastrophes. As practice shows, industrial plant collapses can occur suddenly under normal operating conditions. Usually, such accidents can take place at different stages of structures life cycle. One of the reasons for this is the initially low quality of reinforced concrete structures fabrication. The article considers the factors contributing to the collapse of reinforced concrete structures of water purification tanks located on the territory of the Omsk Region. The main surveys results on tank structures after collapse with the use of ultrasonic and physical methods of investigation are presented. On the basis of the obtained data analysis, it was found that the main cause of the accidents was the insufficient load-bearing capacity of typical reinforced concrete structures, caused by defects in their fabrication in the factory conditions because of exceeding the standard displacement from the design position of the working reinforcement. Recommendations are given on the identification of defective structures and the prevention of similar accidents when operating similar tanks at manufacturing plants constructed from standard designs.

Compact Submillimeter-Wave Receivers Made with Semiconductor Nano-Fabrication Technologies

NASA Technical Reports Server (NTRS)

Jung, C.; Thomas, B.; Lee, C.; Peralta, A.; Chattopadhyay, G.; Gill, J.; Cooper, K.; Mehdi, I.

2011-01-01

Advanced semiconductor nanofabrication techniques are utilized to design, fabricate and demonstrate a super-compact, low-mass (<10 grams) submillimeter-wave heterodyne front-end. RF elements such as waveguides and channels are fabricated in a silicon wafer substrate using deep-reactive ion etching (DRIE). Etched patterns with sidewalls angles controlled with 1 deg precision are reported, while maintaining a surface roughness of better than 20 nm rms for the etched structures. This approach is being developed to build compact 2-D imaging arrays in the THz frequency range.

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

PubMed

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Wafer-Level Hermetic Package by Low-Temperature Cu/Sn TLP Bonding with Optimized Sn Thickness

NASA Astrophysics Data System (ADS)

Wu, Zijian; Cai, Jian; Wang, Qian; Wang, Junqiang; Wang, Dejun

2017-10-01

In this paper, a wafer-level package with hermetic sealing by low-temperature Cu/Sn transient liquid phase (TLP) bonding for a micro-electromechanical system was introduced. A Cu bump with a Sn cap and sealing ring were fabricated simultaneously by electroplating. The model of Cu/Sn TLP bonding was established and the thicknesses of Cu and Sn were optimized after a series of bonding experiments. Cu/Sn wafer-level bonding was undertaken at 260°C for 30 min under a vacuum condition. An average shear strength of 50.36 MPa and a fine leak rate of 1.9 × 10-8 atm cc/s were achieved. Scanning electron microscope photos of the Cu/Sn/Cu interlayers were presented, and energy dispersive x-ray analysis was conducted simultaneously. The results showed that the Sn was completely consumed to form the stable intermetallic compound Cu3Sn. An aging test of 200 h at 200°C was conducted to test the performance of the hermetic sealing, while the results of shear strength, fine leak rate and bonding interface were also set out.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

NASA Astrophysics Data System (ADS)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

Design and Fabrication of Opacity Targets for the National Ignition Facility

DOE PAGES

Cardenas, Tana; Schmidt, Derek William; Dodd, Evan S.; ...

2017-12-22

Accurate models for opacity of partially ionized atoms are important for modeling and understanding stellar interiors and other high-energy-density phenomena such as inertial confinement fusion. Lawrence Livermore National Laboratory is leading a multilaboratory effort to conduct experiments on the National Ignition Facility (NIF) to try to reproduce recent opacity tests at the Sandia National Laboratory Z-facility. Since 2015, the NIF effort has evolved several hohlraum designs that consist of multiple pieces joined together. The target also has three components attached to the main stalk over a long distance with high tolerances that have resulted in several design iterations. The targetmore » has made use of rapid prototyped features to attach a capsule and collimator under the hohlraum while avoiding interference with the beams. Furthermore, this paper discusses the evolution of the hohlraum and overall target design and the challenges involved with fabricating and assembling these targets.« less

Design and Fabrication of Opacity Targets for the National Ignition Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cardenas, Tana; Schmidt, Derek William; Dodd, Evan S.

Accurate models for opacity of partially ionized atoms are important for modeling and understanding stellar interiors and other high-energy-density phenomena such as inertial confinement fusion. Lawrence Livermore National Laboratory is leading a multilaboratory effort to conduct experiments on the National Ignition Facility (NIF) to try to reproduce recent opacity tests at the Sandia National Laboratory Z-facility. Since 2015, the NIF effort has evolved several hohlraum designs that consist of multiple pieces joined together. The target also has three components attached to the main stalk over a long distance with high tolerances that have resulted in several design iterations. The targetmore » has made use of rapid prototyped features to attach a capsule and collimator under the hohlraum while avoiding interference with the beams. Furthermore, this paper discusses the evolution of the hohlraum and overall target design and the challenges involved with fabricating and assembling these targets.« less

Solar Cell Fabrication Studies Pertinent to Developing Countries.

NASA Astrophysics Data System (ADS)

Prah, Joseph Henry

That there is a need in the world today, and in the Third World in particular, for developing renewable energy sources is a proposition without question. Toward that end, the harnessing of solar energy has attracted much attention recently. In this thesis, we have addressed the question of Photovoltaics among the many approaches to the problem as being of poignant relevance in the Third World. Based on our studies, which involved the physics of solar cells, various solar cell configurations, the materials for their fabrication and their fabrication sequences, we arrived at the conclusion that silicon homojunction solar cells are best suited to the present needs and environment of, and suitable for development in the Third World, though Cadmium Sulphide-Cuprous Sulphide solar cell could be considered as a viable future candidate. Attendant with the adoption of photovoltaics as electric energy supply, is the problem of technology transfer and development. Towards that goal, we carried out in the laboratory, the fabrication of solar cells using very simple fabrication sequences and materials to demonstrate that tolerable efficiencies are achievable by their use. The view is also presented that for a thriving and viable solar cell industry in the Third World, the sine qua non is an integrated national policies involving all facets of solar cell manufacture and application, namely, material processing and fabrication, basic research, and development and socio -economic acceptance of solar cell appliances. To demonstrate how basic research could benefit solar cell fabrication, we undertook a number of experiments, such as varying our fabrication sequences and materials, finding their radiation tolerance, and carrying out Deep Level Transient Spectroscopy (DLTS) studies, in an attempt to understand some of the fabrication and environmental factors which limit solar cell performance. We thus found that subjecting wafers to preheat treatments does not improve solar cell

Design and Fabrication Highlights Enabling a 2 mm, 128 Element Bolometer Array for GISMO

NASA Technical Reports Server (NTRS)

Allen, Christine; Benford, Dominic; Miller, Timothy; Staguhn, Johannes; Wollack, Edward; Moseley, Harvey

2007-01-01

The Backshort-Under-Grid (BUG) superconducting bolometer array architecture is intended to be highly versatile, operating in a large range of wavelengths and background conditions. We have undertaken a three-year program to develop key technologies and processes required to build kilopixel arrays. To validate the basic array design and to demonstrate its applicability for future kilopixel arrays, we have chosen to demonstrate a 128 element bolometer array optimized for 2 mm wavelength using a newly built Goddard instrument, GISMO (Goddard /RAM Superconducting 2-millimeter Observer). The arrays are fabricated using batch wafer processing developed and optimized for high pixel yield, low noise, and high uniformity. The molybdenum-gold superconducting transition edge sensors are fabricated using batch sputter deposition and are patterned using dry etch techniques developed at Goddard. With a detector pitch of 2 mm 8x16 array for GISMO occupies nearly one half of the processing area of a 100 mm silicon-on-insulator starting wafer. Two such arrays are produced from a single wafer along with witness samples for process characterization. To provide thermal isolation for the detector elements, at the end of the process over 90% of the silicon must be removed using deep reactive ion etching techniques. The electrical connections for each bolometer element are patterned on the top edge of the square grid supporting the array. The design considerations unique to GISMO, key fabrication challenges, and laboratory experimental results will be presented.

Environmentally benign processing of YAG transparent wafers

NASA Astrophysics Data System (ADS)

Yang, Yan; Wu, Yiquan

2015-12-01

Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

PubMed

Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

2015-09-21

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

P/N InP solar cells on Ge wafers

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

Wafer level reliability testing: An idea whose time has come

NASA Technical Reports Server (NTRS)

Trapp, O. D.

1987-01-01

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Locally-enhanced light scattering by a monocrystalline silicon wafer

NASA Astrophysics Data System (ADS)

Ma, Li; Zhang, Pan; Li, Zhen-Hua; Liu, Chun-Xiang; Li, Xing; Zhan, Zi-Jun; Ren, Xiao-Rong; He, Chang-Wei; Chen, Chao; Cheng, Chuan-Fu

2018-03-01

We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

The iMoD display: considerations and challenges in fabricating MOEMS on large area glass substrates

NASA Astrophysics Data System (ADS)

Chui, Clarence; Floyd, Philip D.; Heald, David; Arbuckle, Brian; Lewis, Alan; Kothari, Manish; Cummings, Bill; Palmateer, Lauren; Bos, Jan; Chang, Daniel; Chiang, Jedi; Wang, Li-Ming; Pao, Edmon; Su, Fritz; Huang, Vincent; Lin, Wen-Jian; Tang, Wen-Chung; Yeh, Jia-Jiun; Chan, Chen-Chun; Shu, Fang-Ann; Ju, Yuh-Diing

2007-01-01

QUALCOMM has developed and transferred to manufacturing iMoD displays, a MEMS-based reflective display technology. The iMoD array architecture allows for development at wafer scale, yet easily scales up to enable fabrication on flat-panel display (FPD) lines. In this paper, we will describe the device operation, process flow and fabrication, technology transfer issues, and display performance.

Propagation of resist heating mask error to wafer level

NASA Astrophysics Data System (ADS)

Babin, S. V.; Karklin, Linard

2006-10-01

As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

Fabrication and Modification of Nanoporous Silicon Particles

NASA Technical Reports Server (NTRS)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

A single blue nanorod light emitting diode.

PubMed

Hou, Y; Bai, J; Smith, R; Wang, T

2016-05-20

We report a light emitting diode (LED) consisting of a single InGaN/GaN nanorod fabricated by a cost-effective top-down approach from a standard LED wafer. The device demonstrates high performance with a reduced quantum confined Stark effect compared with a standard planar counterpart fabricated from the same wafer, confirmed by optical and electrical characterization. Current density as high as 5414 A cm(-2) is achieved without significant damage to the device due to the high internal quantum efficiency. The efficiency droop is mainly ascribed to Auger recombination, which was studied by an ABC model. Our work provides a potential method for fabricating compact light sources for advanced photonic integrated circuits without involving expensive or time-consuming fabrication facilities.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Wafer scale BN on sapphire substrates for improved graphene transport.

PubMed

Vangala, Shivashankar; Siegel, Gene; Prusnick, Timothy; Snure, Michael

2018-06-11

Wafer scale (2") BN grown by metal organic chemical vapor deposition (MOCVD) on sapphire was examined as a weakly interacting dielectric substrate for graphene, demonstrating improved transport properties over conventional sapphire and SiO 2 /Si substrates. Chemical vapor deposition grown graphene was transferred to BN/sapphire substrates for evaluation of more than 30 samples using Raman and Hall effects measurements. A more than 2x increase in Hall mobility and 10x reduction in sheet carrier density was measured for graphene on BN/sapphire compared to sapphire substrates. Through control of the MOCVD process, BN films with roughness ranging from <0.1 nm to >1 nm were grown and used to study the effects of substrate roughness on graphene transport. Arrays of graphene field effect transistors were fabricated on 2" BN/sapphire substrates demonstrating scalability and device performance enhancement.

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

2001-06-01

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Elasto-Capillary Folding Using Stop-Programmable Hinges Fabricated by 3D Micro-Machining

PubMed Central

Legrain, Antoine; Berenschot, Erwin J. W.; Tas, Niels R.; Abelmann, Leon

2015-01-01

We show elasto-capillary folding of silicon nitride objects with accurate folding angles between flaps of (70.6 ± 0.1)° and demonstrate the feasibility of such accurate micro-assembly with a final folding angle of 90°. The folding angle is defined by stop-programmable hinges that are fabricated starting from silicon molds employing accurate three-dimensional corner lithography. This nano-patterning method exploits the conformal deposition and the subsequent timed isotropic etching of a thin film in a 3D shaped silicon template. The technique leaves a residue of the thin film in sharp concave corners which can be used as an inversion mask in subsequent steps. Hinges designed to stop the folding at 70.6° were fabricated batchwise by machining the V-grooves obtained by KOH etching in (110) silicon wafers; 90° stop-programmable hinges were obtained starting from silicon molds obtained by dry etching on (100) wafers. The presented technique has potential to achieve any folding angle and opens a new route towards creating structures with increased complexity, which will ultimately lead to a novel method for device fabrication. PMID:25992886

Scalable planar fabrication processes for chalcogenide-based topological insulators

NASA Astrophysics Data System (ADS)

Sharma, Peter; Henry, M. David; Douglas, Erica; Wiwi, Michael; Lima Sharma, Ana; Lewis, Rupert; Sugar, Joshua; Salehi, Maryam; Koirala, Nikesh; Oh, Seongshik

Surface currents in topological insulators are expected to have long spin diffusion lengths, which could lead to numerous applications. Experiments that show promising transport properties were conducted on exfoliated flakes from bulk material, thin films on substrates of limited dimensions, or bulk material, with limited yield. A planar thin film-based technology is needed to make topological insulator devices at scale and could also lead to new device designs. We address two problems related to fabricating chalcogenide-based topological insulator devices on 3'' wafers in the Sandia Microfabrication Facility using Bi2Te3 films. (2) Implantation damage and its subsequent mitigation through annealing is characterized. (2) The degradation in dielectric layers used to manipulate surface potential for elucidating topological surface state transport is characterized under different processing conditions. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under Contract No. DE-AC04-94AL85000. Funded by the Office of Naval Research (N0001416IP00098-0).

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

Wafer plane inspection for advanced reticle defects

NASA Astrophysics Data System (ADS)

Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

2008-05-01

Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

Electrical properties of Si-Si interfaces obtained by room temperature covalent wafer bonding

NASA Astrophysics Data System (ADS)

Jung, A.; Zhang, Y.; Arroyo Rojas Dasilva, Y.; Isa, F.; von Känel, H.

2018-02-01

We study covalent bonds between p-doped Si wafers (resistivity ˜10 Ω cm) fabricated on a recently developed 200 mm high-vacuum system. Oxide- and void free interfaces were obtained by argon (Ar) or neon (Ne) sputtering prior to wafer bonding at room temperature. The influence of the sputter induced amorphous Si layer at the bonding interface on the electrical behavior is accessed with temperature-dependent current-voltage measurements. In as-bonded structures, charge transport is impeded by a potential barrier of 0.7 V at the interface with thermionic emission being the dominant charge transport mechanism. Current-voltage characteristics are found to be asymmetric which can tentatively be attributed to electric dipole formation at the interface as a result of the time delay between the surface preparation of the two bonding partners. Electron beam induced current measurements confirm the corresponding asymmetric double Schottky barrier like band-alignment. Moreover, we demonstrate that defect annihilation at a low temperature of 400 °C increases the electrical conductivity by up to three orders of magnitude despite the lack of recrystallization of the amorphous layer. This effect is found to be more pronounced for Ne sputtered surfaces which is attributed to the lighter atomic mass compared to Ar, inducing weaker lattice distortions during the sputtering.

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE PAGES

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; ...

2016-07-04

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

PubMed Central

Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

2015-01-01

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

Engineering study for a melting, casting, rolling and fabrication facility for recycled contaminated stainless steel

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

This Preliminary Report is prepared to study the facilities required for recycling contaminated stainless steel scrap into plate which will be fabricated into boxes suitable for the storage of contaminated wastes and rubble. The study is based upon the underlying premise that the most cost effective way to produce stainless steel is to use the same processes employed by companies now in production of high quality stainless steel. Therefore, the method selected for this study for the production of stainless steel plate from scrap is conventional process using an Electric Arc Furnace for meltdown to hot metal, a Continuous Castermore » for production of cast slabs, and a Reversing Hot Mill for rolling the slabs into plate. The fabrication of boxes from the plate utilizes standard Shears, Punch Presses and welding equipment with Robotic Manipulators. This Study presumes that all process fumes, building dusts and vapors will be cycled through a baghouse and a nuclear grade HEPA filter facility prior to discharge. Also, all process waste water will be evaporated into the hot flue gas stream from the furnace utilizing a quench tank; so there will be no liquid discharges from the facility and all vapors will be processed through a HEPA filter. Even though HEPA filters are used today in controlling radioactive contamination from nuclear facilities there is a sparsity of data concerning radioactivity levels and composition of waste that may be collected from contaminated scrap steel processing. This report suggests some solutions to these problems but it is recommended that additional study must be given to these environmental problems.« less

1.3 micrometers Wavelength Vertical Cavity Surface Emitting Laser Fabricated by Orientation-Mismatched Wafer Bonding: A Prospect for Polarization Control

DTIC Science & Technology

2005-06-01

mismatched wafer bonding: A prospect for polarization control Yae L. Okuno,a) Jon Geske , Kian-Giap Gan, Yi-Jen Chiu, Steven P. DenBaars, and John E. Bowers...Uomi, M. Aoki, and T. Tsuchiya, IEEE J. Quantum Electron. 33, 959 ~1997!. 20 Y. L. Okuno, J. Geske , Y.-J. Chiu, S. P. DenBaars, and J. E. Bowers, Proc

Ultrathin body GaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi

2015-02-16

We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al{sub 2}O{sub 3} and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ∼76 cm{sup 2}/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al{sub 2}O{sub 3} ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm{sup 2}/V s for GaSb-OI p-MOSFETs with themore » 20-nm-thick GaSb layer.« less

Design and fabrication of Si-HDPE hybrid Fresnel lenses for infrared imaging systems.

PubMed

Manaf, Ahmad Rosli Abdul; Sugiyama, Tsunetoshi; Yan, Jiwang

2017-01-23

In this work, novel hybrid Fresnel lenses for infrared (IR) optical applications were designed and fabricated. The Fresnel structures were replicated from an ultraprecision diamond-turned aluminum mold to an extremely thin layer (tens of microns) of high-density polyethylene polymer, which was directly bonded onto a flat single-crystal silicon wafer by press molding without using adhesives. Night mode imaging results showed that the fabricated lenses were able to visualize objects in dark fields with acceptable image quality. The capability of the lenses for thermography imaging was also demonstrated. This research provides a cost-effective method for fabricating ultrathin IR optical components.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Design and characterization of Ge passive waveguide components on Ge-on-insulator wafer for mid-infrared photonics

NASA Astrophysics Data System (ADS)

Kang, Jian; Takagi, Shinichi; Takenaka, Mitsuru

2018-04-01

We present the design methodology for Ge passive components including single-mode waveguide, grating couplers, multimode interferometer (MMI) couplers, and micro-ring resonators on the Ge-on-insulator wafer at a 1.95 µm wavelength. Characterizations of the fabricated Ge passive devices reveal a good consistence between the experimental and simulation results. By using the Ge micro-ring device, we also reveal that the thermo-optic coefficient in the Ge strip waveguide is 5.74 × 10-4/°C, which is much greater than that in Si.

Tricobalt tetroxide nanoplate arrays on flexible conductive fabric substrate: Facile synthesis and application for electrochemical supercapacitors

NASA Astrophysics Data System (ADS)

Nagaraju, Goli; Ko, Yeong Hwan; Yu, Jae Su

2015-06-01

Tricobalt tetroxide (Co3O4) nanoplate arrays (NPAs) were synthesized on flexible conductive fabric substrate (FCFs) by a facile two-electrode system based electrochemical deposition method, followed by a simple heat treatment process. Initially, cobalt hydroxide (Co(OH)2) NPAs were electrochemically deposited on FCFs by applying an external voltage of -1.5 V for 30 min. Then, the Co3O4 NPAs on FCFs was obtained by thermal treatment of as-deposited Co(OH)2 NPAs on FCFs at 200 °C for 2 h. From the analysis of morphological and crystal properties, the Co3O4 NPAs were well integrated and uniformly covered over the entire surface of substrate with good crystallinity in the cubic phase. Additionally, the fabricated sample was directly used as a binder-free electrode to examine the feasibility for electrochemical supercapacitors using cyclic voltammetry and galvanic charge-discharge measurements in 1 M KOH electrolyte solution. The Co3O4 NPAs coated FCFs electrode exhibited a maximum specific capacitance of 145.6 F/g at a current density of 1 A/g and an excellent rate capability after 1000 cycles at a current density of 3 A/g. This facile fabrication method for integrating the Co3O4 nanostructures on FCFs could be a promising approach for advanced flexible electronic and energy-storage device applications.

Whole Wafer Design and Fabrication for the Alignment of Nanostructures for Chemical Sensor Applications

NASA Technical Reports Server (NTRS)

Biaggi-Labiosa, Azlin M.; Hunter, Gary W.

2013-01-01

A major objective in aerospace sensor development is to produce sensors that are small in size, easy to batch fabricate and low in cost, and have low power consumption The fabrication of chemical sensors involving nanostructured materials can provide these properties as well as the potential for the development of sensor systems with unique properties and improved performance. However, the fabrication and processing of nanostructures for sensor applications currently is limited in the ability to control their location on the sensor. Currently, our group at NASA Glenn Research Center has demonstrated the controlled placement of nanostructures in sensors using a sawtooth patterned electrode design. With this design the nanostructures are aligned between opposing sawtooth electrodes by applying an alternating current.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

NASA Astrophysics Data System (ADS)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Overlay Tolerances For VLSI Using Wafer Steppers

NASA Astrophysics Data System (ADS)

Levinson, Harry J.; Rice, Rory

1988-01-01

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

NASA Astrophysics Data System (ADS)

Balpande, Suresh S.; Pande, Rajesh S.

2016-04-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of harvester and

Ultrashort pulse laser dicing of thin Si wafers: the influence of laser-induced periodic surface structures on the backside breaking strength

NASA Astrophysics Data System (ADS)

Domke, Matthias; Egle, Bernadette; Piredda, Giovanni; Stroj, Sandra; Fasching, Gernot; Bodea, Marius; Schwarz, Elisabeth

2016-11-01

High power electronic chips are usually fabricated on about 50 µm thin Si wafers to improve heat dissipation. At these chip thicknesses mechanical dicing becomes challenging. Chippings may occur at the cutting edges, which reduce the mechanical stability of the die. Thermal load changes could then lead to sudden chip failure. Ultrashort pulsed lasers are a promising tool to improve the cutting quality, because thermal side effects can be reduced to a minimum. However, laser-induced periodic surface structures occur at the sidewalls and at the trench bottom during scribing. The goal of this study was to investigate the influence of these periodic structures on the backside breaking strength of the die. An ultrafast laser with a pulse duration of 380 fs and a wavelength of 1040 nm was used to cut a wafer into single chips. The pulse energy and the number of scans was varied. The cuts in the wafer were investigated using transmitted light microscopy, the sidewalls of the cut chips were investigated using scanning electron and confocal microscopy, and the breaking strength was evaluated using the 3-point bending test. The results indicated that periodic holes with a distance of about 20-30 µm were formed at the bottom of the trench, if the number of scans was set too low to completely cut the wafer; the wafer was only perforated. Mechanical breaking of the bridges caused 5 µm deep kerfs in the sidewall. These kerfs reduced the breaking strength at the backside of the chip to about 300 MPa. As the number of scans was increased, the bridges were ablated and the wafer was cut completely. Periodic structures were observed on the sidewall; the roughness was below 1 µm. The surface roughness remained on a constant level even when the number of scans was doubled. However, the periodic structures on the sidewall seemed to vanish and the probability to remove local flaws increases with the number of scans. As a consequence, the breaking strength was increased to about

Wafer chamber having a gas curtain for extreme-UV lithography

DOEpatents

Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

2001-01-01

An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

DOE Office of Scientific and Technical Information (OSTI.GOV)

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In thismore » manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented« less

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

PubMed Central

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

A Blueprint for GNEP Advanced Burner Reactor Startup Fuel Fabrication Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

S. Khericha

2010-12-01

The purpose of this article is to identify the requirements and issues associated with design of GNEP Advanced Burner Reactor Fuel Facility. The report was prepared in support of providing data for preparation of a NEPA Environmental Impact Statement in support the U. S. Department of Energy (DOE) Global Nuclear Energy Partnership (GNEP). One of the GNEP objectives was to reduce the inventory of long lived actinide from the light water reactor (LWR) spent fuel. The LWR spent fuel contains Plutonium (Pu) -239 and other transuranics (TRU) such as Americium-241. One of the options is to transmute or burn thesemore » actinides in fast neutron spectra as well as generate the electricity. A sodium-cooled Advanced Recycling Reactor (ARR) concept was proposed to achieve this goal. However, fuel with relatively high TRU content has not been used in the fast reactor. To demonstrate the utilization of TRU fuel in a fast reactor, an Advanced Burner Reactor (ABR) prototype of ARR was proposed, which would necessarily be started up using weapons grade (WG) Pu fuel. The WG Pu is distinguished by relatively highest proportions of Pu-239 and lesser amount of other actinides. The WG Pu was assumed to be used as the startup fuel along with TRU fuel in lead test assemblies. Because such fuel is not currently being produced in the US, a new facility (or new capability in an existing facility) was being considered for fabrication of WG Pu fuel for the ABR. It was estimated that the facility will provide the startup fuel for 10-15 years and would take 3 to 5 years to construct.« less

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Epitaxial solar cells fabrication

NASA Technical Reports Server (NTRS)

Daiello, R. V.; Robinson, P. H.; Kressel, H.

1975-01-01

Silicon epitaxy has been studied for the fabrication of solar cell structures, with the intent of optimizing efficiency while maintaining suitability for space applications. SiH2CL2 yielded good quality layers and junctions with reproducible impurity profiles. Diode characteristics and lifetimes in the epitaxial layers were investigated as a function of epitaxial growth conditions and doping profile, as was the effect of substrates and epitaxial post-gettering on lifetime. The pyrolytic decomposition of SiH4 was also used in the epitaxial formation of highly doped junction layers on bulk Si wafers. The effects of junction layer thickness and bulk background doping level on cell performance, in particular, open-circuit voltage, were investigated. The most successful solar cells were fabricated with SiH2 CL2 to grow p/n layers on n(+) substrates. The best performance was obtained from a p(+)/p/n/n(+) structure grown with an exponential grade in the n-base layer.

Fabrication of (U, Zr) C-fueled/tungsten-clad specimens for irradiation in the Plum Brook Reactor Facility

NASA Technical Reports Server (NTRS)

1972-01-01

Fuel samples, 90UC - 10 ZrC, and chemically vapor deposited tungsten fuel cups were fabricated for the study of the long term dimensional stability and compatibility of the carbide-tungsten fuel-cladding systems under irradiation. These fuel samples and fuel cups were assembled into the fuel pins of two capsules, designated as V-2E and V-2F, for irradiation in NASA Plum Brook Reactor Facility at a fission power density of 172 watts/c.c. and a miximum cladding temperature of 1823 K. Fabrication methods and characteristics of the fuel samples and fuel cups prepared are described.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Comparison of fabrication methods for microstructured deep UV multimode waveguides based on fused silica

NASA Astrophysics Data System (ADS)

Elmlinger, Philipp; Schreivogel, Martin; Schmid, Marc; Kaiser, Myriam; Priester, Roman; Sonström, Patrick; Kneissl, Michael

2016-04-01

The suitability of materials for deep ultraviolet (DUV) waveguides concerning transmittance, fabrication, and coupling properties is investigated and a fused silica core/ambient air cladding waveguide system is presented. This high refractive index contrast system has far better coupling efficiency especially for divergent light sources like LEDs and also a significantly smaller critical bending radius compared to conventional waveguide systems, as simulated by ray-tracing simulations. For the fabrication of 300-ffm-thick multimode waveguides a hydrouoric (HF) acid based wet etch process is compared to selective laser etching (SLE). In order to fabricate thick waveguides out of 300-ffm-thick silica wafers by HF etching, two masking materials, LPCVD silicon nitride and LPCVD poly silicon, are investigated. Due to thermal stress, the silicon nitride deposited wafers show cracks and even break. Using poly silicon as a masking material, no cracks are observed and deep etching in 50 wt% HF acid up to 180 min is performed. While the masked and unmasked silica surface is almost unchanged in terms of roughness, notching defects occur at the remaining polysilicon edge leading to jagged sidewalls. Using SLE, waveguides with high contour accuracy are fabricated and the DUV guiding properties are successfully demonstrated with propagation losses between 0.6 and 0:8 dB=mm. These values are currently limited by sidewall scattering losses.

NIOSH field studies team assessment: Worker exposure to aerosolized metal oxide nanoparticles in a semiconductor fabrication facility.

PubMed

Brenner, Sara A; Neu-Baker, Nicole M; Eastlake, Adrienne C; Beaucham, Catherine C; Geraci, Charles L

2016-11-01

The ubiquitous use of engineered nanomaterials-particulate materials measuring approximately 1-100 nanometers (nm) on their smallest axis, intentionally engineered to express novel properties-in semiconductor fabrication poses unique issues for protecting worker health and safety. Use of new substances or substances in a new form may present hazards that have yet to be characterized for their acute or chronic health effects. Uncharacterized or emerging occupational health hazards may exist when there is insufficient validated hazard data available to make a decision on potential hazard and risk to exposed workers under condition of use. To advance the knowledge of potential worker exposure to engineered nanomaterials, the National Institute for Occupational Safety and Health Nanotechnology Field Studies Team conducted an on-site field evaluation in collaboration with on-site researchers at a semiconductor research and development facility on April 18-21, 2011. The Nanomaterial Exposure Assessment Technique (2.0) was used to perform a complete exposure assessment. A combination of filter-based sampling and direct-reading instruments was used to identify, characterize, and quantify the potential for worker inhalation exposure to airborne alumina and amorphous silica nanoparticles associated with th e chemical mechanical planarization wafer polishing process. Engineering controls and work practices were evaluated to characterize tasks that might contribute to potential exposures and to assess existing engineering controls. Metal oxide structures were identified in all sampling areas, as individual nanoparticles and agglomerates ranging in size from 60 nm to >1,000 nm, with varying structure morphology, from long and narrow to compact. Filter-based samples indicated very little aerosolized material in task areas or worker breathing zone. Direct-reading instrument data indicated increased particle counts relative to background in the wastewater treatment area; however

77 FR 70193 - Shaw Areva MOX Services (Mixed Oxide Fuel Fabrication Facility); Notice of Atomic Safety and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-11-23

... MOX Services (Mixed Oxide Fuel Fabrication Facility); Notice of Atomic Safety and Licensing Board Reconstitution Pursuant to 10 CFR 2.313(c) and 2.321(b), the Atomic Safety and Licensing Board (Board) in the... Rockville, Maryland this 16th day of November 2012. E. Roy Hawkens, Chief Administrative Judge, Atomic...

Silicon solar cell process development, fabrication, and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Work has progressed in fabrication and characterization of solar cells from ubiquitous crystallization process (UCP) wafers and LASS ribbons. Gettering tests applied to UCP wafers made little change on their performance compared with corresponding baseline data. Advanced processes such as shallow junction (SJ), back surface field (BSF), and multilayer antireflection (MLAR) were also applied. While BSF by Al paste had shunting problems, cells with SJ and BSF by evaporated Al, and MLAR did achieve 14.1% AMI on UCP silicon. The study of LASS material was very preliminary. Only a few cells with SJ, BSR, (no BSF) and MLAR were completed due to mechanical yield problems after lapping the material. Average efficiency was 10.7% AMI with 13.4% AMI for CZ controls. Relatively high minority carrier diffusion lengths were obtained. The lower than expected Jsc could be partially explained by low active area due to irregular sizes.

Solution-Processable High-Purity Semiconducting SWCNTs for Large-Area Fabrication of High-Performance Thin-Film Transistors.

PubMed

Gu, Jianting; Han, Jie; Liu, Dan; Yu, Xiaoqin; Kang, Lixing; Qiu, Song; Jin, Hehua; Li, Hongbo; Li, Qingwen; Zhang, Jin

2016-09-01

For the large-area fabrication of thin-film transistors (TFTs), a new conjugated polymer poly[9-(1-octylonoyl)-9H-carbazole-2,7-diyl] is developed to harvest ultrahigh-purity semiconducting single-walled carbon nanotubes. Combined with spectral and nanodevice characterization, the purity is estimated up to 99.9%. High density and uniform network formed by dip-coating process is liable to fabricate high-performance TFTs on a wafer-scale and the as-fabricated TFTs exhibit a high degree of uniformity. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Facile fabrication of BiVO4 nanofilms with controlled pore size and their photoelectrochemical performances.

PubMed

Feng, Chenchen; Jiao, Zhengbo; Li, Shaopeng; Zhang, Yan; Bi, Yingpu

2015-12-28

We demonstrate a facile method for the rational fabrication of pore-size controlled nanoporous BiVO(4) photoanodes, and confirmed that the optimum pore-size distributions could effectively absorb visible light through light diffraction and confinement functions. Furthermore, in situ X-ray photoelectron spectroscopy (XPS) reveals more efficient photoexcited electron-hole separation than conventional particle films, induced by light confinement and rapid charge transfer in the inter-crossed worm-like structures.

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

NASA Technical Reports Server (NTRS)

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Facile fabrication of well-defined hydrogel beads with magnetic nanocomposite shells.

PubMed

Liu, Hongxia; Wang, Chaoyang; Gao, Quanxing; Chen, Jianxin; Ren, Biye; Liu, Xinxing; Tong, Zhen

2009-07-06

Well-defined magnetic nanocomposite beads with alginate gel cores and shells of iron oxide (gamma-Fe(2)O(3)) nanoparticles were prepared by self-assembly of colloidal particles at liquid-liquid interfaces and subsequent in situ gelation. Fe(2)O(3) nanoparticles could spontaneously adsorb onto the water droplet surfaces to stabilize water-in-hexane emulsions. Water droplets containing sodium alginate were in situ gelled by calcium cations, which were released from calcium-ethylenediamine tetraacetic acid (Ca-EDTA) chelate by decreasing pH value through slow hydrolysis of d-glucono-delta-lactone (GDL). The resulting hybrid beads with a core-shell structure were easily collected by removing hexane. This facile and high efficient fabrication had a 100% yield and could be carried out at room temperature. Insulin microcrystal was encapsulated into the hybrid beads by dispersing them in the aqueous solution of alginate sodium in the fabrication process. The sustained release could be obtained due to the dual barriers of the hydrogel core and the close-packed inorganic shell. The release curves were nicely fitted by the Weibull equation and the release followed Fickian diffusion. The hybrid beads may find applications as delivery vehicles for biomolecules, drugs, cosmetics, food supplements and living cells.

Fabrication of a Miniaturized ZnO Nanowire Accelerometer and Its Performance Tests

PubMed Central

Kim, Hyun Chan; Song, Sangho; Kim, Jaehwan

2016-01-01

This paper reports a miniaturized piezoelectric accelerometer suitable for a small haptic actuator array. The accelerometer is made with zinc oxide (ZnO) nanowire (NW) grown on a copper wafer by a hydrothermal process. The size of the accelerometer is 1.5 × 1.5 mm2, thus fitting the 1.8 × 1.8 mm2 haptic actuator array cell. The detailed fabrication process of the miniaturized accelerometer is illustrated. Performance evaluation of the fabricated accelerometer is conducted by comparing it with a commercial piezoelectric accelerometer. The output current of the fabricated accelerometer increases linearly with the acceleration. The miniaturized ZnO NW accelerometer is feasible for acceleration measurement of small and lightweight devices. PMID:27649184

Neural Network Modeling for Gallium Arsenide IC Fabrication Process and Device Characteristics.

NASA Astrophysics Data System (ADS)

Creech, Gregory Lee, I.

This dissertation presents research focused on the utilization of neurocomputing technology to achieve enhanced yield and effective yield prediction in integrated circuit (IC) manufacturing. Artificial neural networks are employed to model complex relationships between material and device characteristics at critical stages of the semiconductor fabrication process. Whole wafer testing was performed on the starting substrate material and during wafer processing at four critical steps: Ohmic or Post-Contact, Post-Recess, Post-Gate and Final, i.e., at completion of fabrication. Measurements taken and subsequently used in modeling include, among others, doping concentrations, layer thicknesses, planar geometries, layer-to-layer alignments, resistivities, device voltages, and currents. The neural network architecture used in this research is the multilayer perceptron neural network (MLPNN). The MLPNN is trained in the supervised mode using the generalized delta learning rule. It has one hidden layer and uses continuous perceptrons. The research focuses on a number of different aspects. First is the development of inter-process stage models. Intermediate process stage models are created in a progressive fashion. Measurements of material and process/device characteristics taken at a specific processing stage and any previous stages are used as input to the model of the next processing stage characteristics. As the wafer moves through the fabrication process, measurements taken at all previous processing stages are used as input to each subsequent process stage model. Secondly, the development of neural network models for the estimation of IC parametric yield is demonstrated. Measurements of material and/or device characteristics taken at earlier fabrication stages are used to develop models of the final DC parameters. These characteristics are computed with the developed models and compared to acceptance windows to estimate the parametric yield. A sensitivity analysis is

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

High frequency guided wave propagation in monocrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

NASA Astrophysics Data System (ADS)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

Micro-fabricated packed gas chromatography column based on laser etching technology.

PubMed

Sun, J H; Guan, F Y; Zhu, X F; Ning, Z W; Ma, T J; Liu, J H; Deng, T

2016-01-15

In this work, a micro packed gas chromatograph column integrated with a micro heater was fabricated by using laser etching technology (LET) for analyzing environmental gases. LET is a powerful tool to etch deep well-shaped channels on the glass wafer, and it is the most effective way to increase depth of channels. The fabricated packed GC column with a length of over 1.6m, to our best knowledge, which is the longest so far. In addition, the fabricated column with a rectangular cross section of 1.2mm (depth) × 0.6mm (width) has a large aspect ratio of 2:1. The results show that the fabricated packed column had a large sample capacity, achieved a separation efficiency of about 5800 plates/m and eluted highly symmetrical Gaussian peaks. Copyright © 2015 Elsevier B.V. All rights reserved.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hegedus, Steven S.

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

Lamb wave propagation in monocrystalline silicon wafers.

PubMed

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

NASA Technical Reports Server (NTRS)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Wafer Scale Fabrication of Dense and High Aspect Ratio Sub-50 nm Nanopillars from Phase Separation of Cross-Linkable Polysiloxane/Polystyrene Blend.

PubMed

Li, Yang; Hao, Yuli; Huang, Chunyu; Chen, Xingyao; Chen, Xinyu; Cui, Yushuang; Yuan, Changsheng; Qiu, Kai; Ge, Haixiong; Chen, Yanfeng

2017-04-19

We demonstrated a simple and effective approach to fabricate dense and high aspect ratio sub-50 nm pillars based on phase separation of a polymer blend composed of a cross-linkable polysiloxane and polystyrene (PS). In order to obtain the phase-separated domains with nanoscale size, a liquid prepolymer of cross-linkable polysiloxane was employed as one moiety for increasing the miscibility of the polymer blend. After phase separation via spin-coating, the dispersed domains of liquid polysiloxane with sub-50 nm size could be solidified by UV exposure. The solidified polysiloxane domains took the role of etching mask for formation of high aspect ratio nanopillars by O 2 reactive ion etching (RIE). The aspect ratio of the nanopillars could be further amplified by introduction of a polymer transfer layer underneath the polymer blend film. The effects of spin speeds, the weight ratio of the polysiloxane/PS blend, and the concentration of polysiloxane/PS blend in toluene on the characters of the nanopillars were investigated. The gold-coated nanopillar arrays exhibited a high Raman scattering enhancement factor in the range of 10 8 -10 9 with high uniformity across over the wafer scale sample. A superhydrophobic surface could be realized by coating a self-assembled monolayers (SAM) of fluoroalkyltrichlorosilane on the nanopillar arrays. Sub-50 nm silicon nanowires (SiNWs) with high aspect ratio of about 1000 were achieved by using the nanopillars as etching mask through a metal-assisted chemical etching process. They showed an ultralow reflectance of approximately 0.1% for wavelengths ranging from 200 to 800 nm.

Large-Scale Fabrication of Carbon Nanotube Probe Tips For Atomic Force Microscopy Critical Dimension Imaging Applications

NASA Technical Reports Server (NTRS)

Ye, Qi Laura; Cassell, Alan M.; Stevens, Ramsey M.; Meyyappan, Meyya; Li, Jun; Han, Jie; Liu, Hongbing; Chao, Gordon

2004-01-01

Carbon nanotube (CNT) probe tips for atomic force microscopy (AFM) offer several advantages over Si/Si3N4 probe tips, including improved resolution, shape, and mechanical properties. This viewgraph presentation discusses these advantages, and the drawbacks of existing methods for fabricating CNT probe tips for AFM. The presentation introduces a bottom up wafer scale fabrication method for CNT probe tips which integrates catalyst nanopatterning and nanomaterials synthesis with traditional silicon cantilever microfabrication technology. This method makes mass production of CNT AFM probe tips feasible, and can be applied to the fabrication of other nanodevices with CNT elements.

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

‘Chip-olate’ and dry-film resists for efficient fabrication, singulation and sealing of microfluidic chips

NASA Astrophysics Data System (ADS)

Temiz, Yuksel; Delamarche, Emmanuel

2014-09-01

This paper describes a technique for high-throughput fabrication and efficient singulation of chips having closed microfluidic structures and takes advantage of dry-film resists (DFRs) for efficient sealing of capillary systems. The technique is illustrated using 4-inch Si/SiO2 wafers. Wafers carrying open microfluidic structures are partially diced to about half of their thickness. Treatments such as surface cleaning are done at wafer-level, then the structures are sealed using low-temperature (45 °C) lamination of a DFR that is pre-patterned using a craft cutter, and ready-to-use chips are finally separated manually like a chocolate bar by applying a small force (≤ 4 N). We further show that some DFRs have low auto-fluorescence at wavelengths typically used for common fluorescent dyes and that mechanical properties of some DFRs allow for the lamination of 200 μm wide microfluidic structures with negligible sagging (~1 μm). The hydrophilicity (advancing contact angle of ~60°) of the DFR supports autonomous capillary-driven flow without the need for additional surface treatment of the microfluidic chips. Flow rates from 1 to 5 µL min-1 are generated using different geometries of channels and capillary pumps. In addition, the ‘chip-olate’ technique is compatible with the patterning of capture antibodies on DFR for use in immunoassays. We believe this technique to be applicable to the fabrication of a wide range of microfluidic and lab-on-a-chip devices and to offer a viable alternative to many labor-intensive processes that are currently based on wafer bonding techniques or on the molding of poly(dimethylsiloxane) (PDMS) layers.

End-of-fabrication CMOS process monitor

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

1990-01-01

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

A facile fabrication of multifunctional knit polyester fabric based on chitosan and polyaniline polymer nanocomposite

NASA Astrophysics Data System (ADS)

Tang, Xiaoning; Tian, Mingwei; Qu, Lijun; Zhu, Shifeng; Guo, Xiaoqing; Han, Guangting; Sun, Kaikai; Hu, Xili; Wang, Yujiao; Xu, Xiaoqi

2014-10-01

Knit polyester fabric was successively modified and decorated with chitosan layer and polyaniline polymer nanocomposite layer in this paper. The fabric was firstly treated with chitosan to form a stable layer through the pad-dry-cure process, and then the polyaniline polymer nanocomposite layer was established on the outer layer by in situ chemical polymerization method using ammonium persulfate as oxidant and chlorhydric acid as dopant. The surface morphology of coated fabric was characterized by scanning electron microscopy (SEM), and the co-existence of chitosan layer and granular polyaniline polymer nanocomposite was confirmed and well dispersed on the fabric surface. The resultant fabric was endowed with remarkable electrical conductivity properties and efficient water-repellent capability, which also have been found stable after water laundering. In addition, the photocatalytic decomposition activity for reactive red dye was observed when the multifunctional knit polyester fabric was exposed to the illumination of ultraviolet lamp. These results indicated that chitosan and polyaniline polymer nanocomposite could form ideal multifunctional coatings on the surface of knit polyester fabric.

Warpage Measurement of Thin Wafers by Reflectometry

NASA Astrophysics Data System (ADS)

Ng, Chi Seng; Asundi, Anand Krishna

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Balpande, Suresh S., E-mail: balpandes@rknec.edu; Pande, Rajesh S.

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition tomore » this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

Facile Fabrication of Composition-Tuned Ru-Ni Bimetallics in Ordered Mesoporous Carbon for Levulinic Acid Hydrogenation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Ying; Gao, Guang; Zhang, Xin

Bimetallic catalysts are of great importance due to their unique catalytic properties. However, their conventional synthesis requires tedious multistep procedures and prolonged synthetic time, and the resulting bimetallics usually disperse unevenly and show poor stability. It is challenging to develop a facile and step-economic synthetic methodology for highly efficient bimetallic catalysts. In this study, we report an elegant metal complex-involved multicomponent assembly route to highly efficient Ru–Ni bimetallics in ordered mesoporous carbons (OMC). The fabrication of composition-tuned Ru–Ni bimetallics in OMC (Ru xNi 1–x–OMC, x = 0.5–0.9) was facilely realized via in situ construction of CTAB-directed cubic Ia3d chitosan-ruthenium–nickel–silica mesophasemore » before pyrolysis and silica removal. The resulting Ru xNi 1–x–OMC materials are in-depth characterized with X-ray diffraction, N 2 adsorption–desorption, transmission electron microscopy, infrared spectrum, and X-ray absorption fine structure. This facile fabrication method renders homogeneously dispersed Ru–Ni bimetallics embedded in the mesoporous carbonaceous framework and creates a highly active and stable Ru 0.9Ni 0.1–OMC catalyst for the hydrogenation of levulinic acid (LA) to prepare γ-valerolactone (GVL), a biomass-derived platform molecule with wide application in the preparation of renewable chemicals and liquid transportation fuels. A high TOF (>2000 h –1) was obtained, and the Ru 0.9Ni 0.1–OMC catalyst could be used at least 15 times without obvious loss of its catalytic performance.« less

Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

Thin film fabrication and system integration test run for a microactuator for a tuneable lens

NASA Astrophysics Data System (ADS)

Hoheisel, Dominik; Rissing, Lutz

2014-03-01

An electromagnetic microactuator, for controlling of a tuneable lens, with an integrated electrostatic element is fabricated by thin film technology. The actuator consists of two parts: the first part with microcoil and flux guide and the second part with a ring shaped back iron on a polyimide membrane. The back iron is additionally useable as electrode for electrostatic measurement of the air gap and for electrostatic actuation. By attracting the back iron an optical liquid is displaced and forms a liquid lens inside the back iron ring covered by the membrane. For testing the thin film fabrication sequence, up-scaled systems are generated in a test run. To fabricate the flux guide in an easy and quick way, a Ni-Fe foil with a thickness of 50 μm is laminated on the Si-wafer. This foil is also utilized in the following fabrication sequence as seed layer for electroplating. Compared to Ni-Fe structures deposited by electroplating, the foil is featuring better soft magnetic properties. The foil is structured by wet chemical etching and the backside of the wafer is structured by deep reactive ion etching (DRIE). For post fabrication thinning, the polyimide membrane is treated by oxygen plasma etching. To align the back iron to the microcoil and the flux guide, a flip-chip-bonder is used during test run of system integration. To adjust a constant air gap, a water solvable polymer is tested. A two component epoxy and a polyimide based glue are compared for their bonding properties of the actuator parts.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

Enhanced capture rate for haze defects in production wafer inspection

NASA Astrophysics Data System (ADS)

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers.

PubMed

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-03-04

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers

PubMed Central

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-01-01

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications. PMID:26940260

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

PubMed

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Facile Fabrication of Hierarchically Thermoresponsive Binary Polymer Pattern for Controlled Cell Adhesion.

PubMed

Hou, Jianwen; Cui, Lele; Chen, Runhai; Xu, Xiaodong; Chen, Jiayue; Yin, Ligang; Liu, Jingchuan; Shi, Qiang; Yin, Jinghua

2018-03-01

A versatile platform allowing capture and detection of normal and dysfunctional cells on the same patterned surface is important for accessing the cellular mechanism, developing diagnostic assays, and implementing therapy. Here, an original and effective method for fabricating binary polymer brushes pattern is developed for controlled cell adhesion. The binary polymer brushes pattern, composed of poly(N-isopropylacrylamide) (PNIPAAm) and poly[poly(ethylene glycol) methyl ether methacrylate] (POEGMA) chains, is simply obtained via a combination of surface-initiated photopolymerization and surface-activated free radical polymerization. This method is unique in that it does not utilize any protecting groups or procedures of backfilling with immobilized initiator. It is demonstrated that the precise and well-defined binary polymer patterns with high resolution are fabricated using this facile method. PNIPAAm chains capture and release cells by thermoresponsiveness, while POEGMA chains possess high capability to capture dysfunctional cells specifically, inducing a switch of normal red blood cells (RBCs) arrays to hemolytic RBCs arrays on the pattern with temperature. This novel platform composed of binary polymer brush pattern is smart and versatile, which opens up pathways to potential applications as microsensors, biochips, and bioassays. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tiriolo, Raffaele; Rangnekar, Neel; Zhang, Han

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservationmore » of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.« less

Advanced FTIR technology for the chemical characterization of product wafers

NASA Astrophysics Data System (ADS)

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Facile fabrication of networked patterns and their superior application to realize the virus immobilized networked pattern circuit.

PubMed

Choi, Kyung Min; Lee, Seok Jae; Choi, Jung Hoon; Park, Tae Jung; Park, Jong Wan; Shin, Weon Ho; Kang, Jeung Ku

2010-12-07

A facile route to fabricate a protein-immobilized network pattern circuit for rapid and highly sensitive diagnosis was developed via the evaporation directed impromptu patterning method and selective avian influenza virus (AIV) immobilization. The response to the 10 fg mL(-1) anti-AI antibody demonstrates that this easy and simple circuit has about 1000 times higher sensitivity compared to those of conventional approaches.

ITER Central Solenoid Module Fabrication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, John

The fabrication of the modules for the ITER Central Solenoid (CS) has started in a dedicated production facility located in Poway, California, USA. The necessary tools have been designed, built, installed, and tested in the facility to enable the start of production. The current schedule has first module fabrication completed in 2017, followed by testing and subsequent shipment to ITER. The Central Solenoid is a key component of the ITER tokamak providing the inductive voltage to initiate and sustain the plasma current and to position and shape the plasma. The design of the CS has been a collaborative effort betweenmore » the US ITER Project Office (US ITER), the international ITER Organization (IO) and General Atomics (GA). GA’s responsibility includes: completing the fabrication design, developing and qualifying the fabrication processes and tools, and then completing the fabrication of the seven 110 tonne CS modules. The modules will be shipped separately to the ITER site, and then stacked and aligned in the Assembly Hall prior to insertion in the core of the ITER tokamak. A dedicated facility in Poway, California, USA has been established by GA to complete the fabrication of the seven modules. Infrastructure improvements included thick reinforced concrete floors, a diesel generator for backup power, along with, cranes for moving the tooling within the facility. The fabrication process for a single module requires approximately 22 months followed by five months of testing, which includes preliminary electrical testing followed by high current (48.5 kA) tests at 4.7K. The production of the seven modules is completed in a parallel fashion through ten process stations. The process stations have been designed and built with most stations having completed testing and qualification for carrying out the required fabrication processes. The final qualification step for each process station is achieved by the successful production of a prototype coil. Fabrication of

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on

Energy Systems Fabrication Laboratory | Energy Systems Integration Facility

Science.gov Websites

Fabrication The fuel cell fabrication hub includes laboratory spaces with local exhaust and chemical fume hoods that support electrolysis and other chemical process research. Key Infrastructure Perchloric acid washdown hood, local exhaust, specialty gas manifolding, deionized water, chemical fume hoods, glassware

Mechanics of wafer bonding: Effect of clamping

NASA Astrophysics Data System (ADS)

Turner, K. T.; Thouless, M. D.; Spearing, S. M.

2004-01-01

A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Progress Toward Fabrication of Machined Metal Shells for the First Double-Shell Implosions at the National Ignition Facility

DOE PAGES

Cardenas, Tana; Schmidt, Derek W.; Loomis, Eric N.; ...

2018-01-25

The double-shell platform fielded at the National Ignition Facility requires developments in new machining techniques and robotic assembly stations to meet the experimental specifications. Current double-shell target designs use a dense high-Z inner shell, a foam cushion, and a low-Z outer shell. The design requires that the inner shell be gas filled using a fill tube. This tube impacts the entire machining and assembly design. Other intermediate physics designs have to be fielded to answer physics questions and advance the technology to be able to fabricate the full point design in the near future. One of these intermediate designs ismore » a mid-Z imaging design. The methods of designing, fabricating, and characterizing each of the major components of an imaging double shell are discussed with an emphasis on the fabrication of the machined outer metal shell.« less

Progress Toward Fabrication of Machined Metal Shells for the First Double-Shell Implosions at the National Ignition Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cardenas, Tana; Schmidt, Derek W.; Loomis, Eric N.

The double-shell platform fielded at the National Ignition Facility requires developments in new machining techniques and robotic assembly stations to meet the experimental specifications. Current double-shell target designs use a dense high-Z inner shell, a foam cushion, and a low-Z outer shell. The design requires that the inner shell be gas filled using a fill tube. This tube impacts the entire machining and assembly design. Other intermediate physics designs have to be fielded to answer physics questions and advance the technology to be able to fabricate the full point design in the near future. One of these intermediate designs ismore » a mid-Z imaging design. The methods of designing, fabricating, and characterizing each of the major components of an imaging double shell are discussed with an emphasis on the fabrication of the machined outer metal shell.« less

Peel-and-Stick: Fabricating Thin Film Solar Cell on Universal Substrates

PubMed Central

Lee, Chi Hwan; Kim, Dong Rip; Cho, In Sun; William, Nemeth; Wang, Qi; Zheng, Xiaolin

2012-01-01

Fabrication of thin-film solar cells (TFSCs) on substrates other than Si and glass has been challenging because these nonconventional substrates are not suitable for the current TFSC fabrication processes due to poor surface flatness and low tolerance to high temperature and chemical processing. Here, we report a new peel-and-stick process that circumvents these fabrication challenges by peeling off the fully fabricated TFSCs from the original Si wafer and attaching TFSCs to virtually any substrates regardless of materials, flatness and rigidness. With the peel-and-stick process, we integrated hydrogenated amorphous silicon (a-Si:H) TFSCs on paper, plastics, cell phone and building windows while maintaining the original 7.5% efficiency. The new peel-and-stick process enables further reduction of the cost and weight for TFSCs and endows TFSCs with flexibility and attachability for broader application areas. We believe that the peel-and-stick process can be applied to thin film electronics as well. PMID:23277871

Peel-and-Stick: Fabricating Thin Film Solar Cell on Universal Substrates

NASA Astrophysics Data System (ADS)

Lee, Chi Hwan; Kim, Dong Rip; Cho, In Sun; William, Nemeth; Wang, Qi; Zheng, Xiaolin

2012-12-01

Fabrication of thin-film solar cells (TFSCs) on substrates other than Si and glass has been challenging because these nonconventional substrates are not suitable for the current TFSC fabrication processes due to poor surface flatness and low tolerance to high temperature and chemical processing. Here, we report a new peel-and-stick process that circumvents these fabrication challenges by peeling off the fully fabricated TFSCs from the original Si wafer and attaching TFSCs to virtually any substrates regardless of materials, flatness and rigidness. With the peel-and-stick process, we integrated hydrogenated amorphous silicon (a-Si:H) TFSCs on paper, plastics, cell phone and building windows while maintaining the original 7.5% efficiency. The new peel-and-stick process enables further reduction of the cost and weight for TFSCs and endows TFSCs with flexibility and attachability for broader application areas. We believe that the peel-and-stick process can be applied to thin film electronics as well.

Evaluation of anti-sticking layers performances for 200mm wafer scale Smart NILTM process through surface and defectivity characterizations

NASA Astrophysics Data System (ADS)

Delachat, F.; Phillipe, J.-C.; Larrey, V.; Fournel, F.; Bos, S.; Teyssèdre, H.; Chevalier, Xavier; Nicolet, Célia; Navarro, Christophe; Cayrefourcq, Ian

2018-03-01

In this work, an evaluation of various ASL processes for 200 mm wafer scale in the HERCULES® NIL equipment platform available at the CEA-Leti through the INSPIRE program is reported. The surface and adherence energies were correlated to the AFM and defectivity results in order to select the most promising ASL process for high resolution etch mask applications. The ASL performances of the selected process were evaluated by multiple working stamp fabrication using unpatterned and patterned masters though defectivity monitoring on optical based-inspection tools. Optical and SEM defect reviews were systematically performed. Multiple working stamps fabrication without degradation of the master defectivity was witnessed. This evaluation enabled to benchmark several ASL solutions based on the grafted technology develop by ARKEMA in order to reduce and optimize the soft stamp defectivity prior to its replication and therefore considerably reduce the final imprint defectivity for the Smart NIL process.

Dense arrays of millimeter-sized glass lenses fabricated at wafer-level.

PubMed

Albero, Jorge; Perrin, Stéphane; Bargiel, Sylwester; Passilly, Nicolas; Baranski, Maciej; Gauthier-Manuel, Ludovic; Bernard, Florent; Lullin, Justine; Froehly, Luc; Krauter, Johann; Osten, Wolfgang; Gorecki, Christophe

2015-05-04

This paper presents the study of a fabrication technique of lenses arrays based on the reflow of glass inside cylindrical silicon cavities. Lenses whose sizes are out of the microfabrication standards are considered. In particular, the case of high fill factor arrays is discussed in detail since the proximity between lenses generates undesired effects. These effects, not experienced when lenses are sufficiently separated so that they can be considered as single items, are corrected by properly designing the silicon cavities. Complete topographic as well as optical characterizations are reported. The compatibility of materials with Micro-Opto-Electromechanical Systems (MOEMS) integration processes makes this technology attractive for the miniaturization of inspection systems, especially those devoted to imaging.

One-step Maskless Fabrication and Optical Characterization of Silicon Surfaces with Antireflective Properties and a White Color Appearance

PubMed Central

Schneider, Ling; Feidenhans’l, Nikolaj A.; Telecka, Agnieszka; Taboryski, Rafael J.

2016-01-01

We report a simple one-step maskless fabrication of inverted pyramids on silicon wafers by reactive ion etching. The fabricated surface structures exhibit excellent anti-reflective properties: The total reflectance of the nano inverted pyramids fabricated by our method can be as low as 12% without any anti-reflective layers, and down to only 0.33% with a silicon nitride coating. The results from angle resolved scattering measurements indicate that the existence of triple reflections is responsible for the reduced reflectance. The surfaces with the nano inverted pyramids also exhibit a distinct milky white color. PMID:27725703

Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

NASA Astrophysics Data System (ADS)

Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

2018-02-01

Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

Accurate characterization of wafer bond toughness with the double cantilever specimen

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Spearing, S. Mark

2008-01-01

The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

Fabrication of optical filters using multilayered porous silicon

NASA Astrophysics Data System (ADS)

Gaber, Noha; Khalil, Diaa; Shaarawi, Amr

2011-02-01

In this work we describe a method for fabricating optical filters using multilayered porous silicon 1D photonic structure. An electrochemical cell is constructed to control the porosity of variable layers in p-type Si wafers. Porous silicon multilayered structures are formed of λ/4 (or multiples) thin films that construct optical interference filters. By changing the anodizing current density of the cell during fabrication, different porosities can be obtained as the optical refractive index is a direct function of the layer porosity. To determine the morphology, the wavelength dependent refractive index n and absorption coefficient α, first, porous silicon free standing mono-layers have been fabricated at different conditions and characterized in the near infrared region (from 1000 to 2500nm). Large difference in refractive index (between 1.6 and 2.6) is obtained. Subsequently, multilayer structures have been fabricated and tested. Their spectral response has been measured and it shows good agreement with numerical simulations. A technique based on inserting etching breaks is adopted to ensure the depth homogeneity. The effect of differing etching/break times on the reproducibility of the filters is studied.

Scatterometry on pelliclized masks: an option for wafer fabs

NASA Astrophysics Data System (ADS)

Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

2007-03-01

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Inversion layer solar cell fabrication and evaluation. [etching on silicon films

NASA Technical Reports Server (NTRS)

Call, R. L.

1974-01-01

Inversion layer solar cells were fabricated by etching through the diffused layer on p-type silicon wafers in a comb-like contact pattern. The charge separation comes from an induced p-n junction at the surface. The inverted surface is caused by a layer of transparent material applied to the surface that either contains free positive ions or that creates donor states at the interface. Cells are increased from 3 ma I sub sc to 100 ma by application of sodium silicate. The action is unstable, however, and decays. Non-mesa contaminated oxide cells were fabricated with short circuit currents of over 100 ma measured in the sun. Cells of this type have demonstrated stability.

Wafer plane inspection with soft resist thresholding

NASA Astrophysics Data System (ADS)

Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

2008-10-01

Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

MiRNA-181d Expression Significantly Affects Treatment Responses to Carmustine Wafer Implantation.

PubMed

Sippl, Christoph; Ketter, Ralf; Bohr, Lisa; Kim, Yoo Jin; List, Markus; Oertel, Joachim; Urbschat, Steffi

2018-05-26

Standard therapeutic protocols for glioblastoma, the most aggressive type of brain cancer, include surgery followed by chemoradiotherapy. Additionally, carmustine-eluting wafers can be implanted locally into the resection cavity. To evaluate microRNA (miRNA)-181d as a prognostic marker of responses to carmustine wafer implantation. A total of 80 glioblastoma patients (40/group) were included in a matched pair analysis. One group (carmustine wafer group) received concomitant chemoradiotherapy with carmustine wafer implantation (Stupp protocol). The second group (control group) received only concomitant chemoradiotherapy. All tumor specimens were subjected to evaluations of miRNA-181d expression, results were correlated with further individual clinical data. The Cancer Genome Atlas (TCGA) dataset of 149 patients was used as an independent cohort to validate the results. Patients in the carmustine wafer group with low miRNA-181d expression had significantly longer overall (hazard ratio [HR], 35.03, [95% confidence interval (CI): 3.50-350.23], P = .002) and progression-free survival (HR, 20.23, [95% CI: 2.19-186.86], P = .008) than patients of the same group with a high miRNA-181d expression. These correlations were not observed in the control group. The nonsignificance in the control group was confirmed in the independent TCGA dataset. The carmustine wafer group patients with low miRNA-181d expression also had a significantly longer progression-free (P = .049) and overall survival (OS) (P = .034), compared with control group patients. Gross total resection correlated significantly with longer OS (P = .023). MiRNA-181d expression significantly affects treatment responses to carmustine wafer implantation.

Grain-boundary type and distribution in silicon carbide coatings and wafers

NASA Astrophysics Data System (ADS)

Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

2018-03-01

Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

Facile fabrication of ultrathin hybrid membrane for highly flexible supercapacitors via in-situ phase separation of polyethersulfone

NASA Astrophysics Data System (ADS)

Zhao, Xiaoning; Ran, Fen; Shen, Kuiwen; Yang, Yunlong; Wu, Jiayu; Niu, Xiaoqin; Kong, Lingbin; Kang, Long; Chen, Shaowei

2016-10-01

In this article, a facile method based on in-situ phase-separation was developed for the fabrication of ultrathin hybrid membranes for highly flexible supercapacitors. The structures and morphologies of the prepared electrodes were characterized by scanning electron microscopy (SEM), Fourier-transformed infrared spectroscopy (FTIR), and thermogravimetric analysis (TGA) measurements; and the electrochemical behaviors were examined in 2 M KOH solution. SEM and FTIR characterizations reveal that activated carbon was imbedded into the polymer membrane of polyethersulfone to form a uniform and flexible hybrid membrane. When the thin polymer-carbon membrane (PCM) was used as an electrode material for supercapacitor, a high specific capacitance of 169.4 Fg-1 was obtained at a current density of 0.5 Ag-1 along with good long-term cycle life of 94.6% capacity retention after 2000 charging-discharging cycles. Benefiting from these merits, the as-fabricated PCM//PCM cell shows an excellent electrochemical property. These results suggest a promising route towards the fabrication of highly flexible electrodes for high-performance supercapacitors.

Facile fabrication of robust TiO2@SnO2@C hollow nanobelts for outstanding lithium storage

NASA Astrophysics Data System (ADS)

Tian, Qinghua; Li, Lingxiangyu; Chen, Jizhang; Yang, Li; Hirano, Shin-ichi

2018-02-01

Elaborate fabrication of state-of-the-art nanostructure SnO2@C-based composites greatly contributes to alleviate the huge volume expansion issue of the SnO2 anodes. But the preparation processes of most of them are complicated and tedious, which is generally adverse to the development of SnO2@C-based composite anodes. Herein, a unique nanostructure of TiO2@SnO2@C hollow nanobelts (TiO2@SnO2@C HNBs), including the characteristics of one-dimensional architecture, sandwich protection, hollow structure, carbon coating, and a mechanically robust TiO2 support, has been fabricated by a facile approach for the first time. As anodes for lithium-ion batteries, the as-fabricated TiO2@SnO2@C HNBs exhibit an outstanding lithium storage performance, delivering capacity of 804.6 and 384. 5 mAh g-1 at 200 and even 1000 mA g-1 after 500 cycles, respectively. It is demonstrated that thus outstanding performance is mainly attributed to the unique nanostructure of TiO2@SnO2@C HNBs.

Single step sequential polydimethylsiloxane wet etching to fabricate a microfluidic channel with various cross-sectional geometries

NASA Astrophysics Data System (ADS)

Wang, C.-K.; Liao, W.-H.; Wu, H.-M.; Lo, Y.-H.; Lin, T.-R.; Tung, Y.-C.

2017-11-01

Polydimethylsiloxane (PDMS) has become a widely used material to construct microfluidic devices for various biomedical and chemical applications due to its desirable material properties and manufacturability. PDMS microfluidic devices are usually fabricated using soft lithography replica molding methods with master molds made of photolithogrpahy patterned photoresist layers on silicon wafers. The fabricated microfluidic channels often have rectangular cross-sectional geometries with single or multiple heights. In this paper, we develop a single step sequential PDMS wet etching process that can be used to fabricate microfluidic channels with various cross-sectional geometries from single-layer PDMS microfluidic channels. The cross-sections of the fabricated channel can be non-rectangular, and varied along the flow direction. Furthermore, the fabricated cross-sectional geometries can be numerically simulated beforehand. In the experiments, we fabricate microfluidic channels with various cross-sectional geometries using the developed technique. In addition, we fabricate a microfluidic mixer with alternative mirrored cross-sectional geometries along the flow direction to demonstrate the practical usage of the developed technique.

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

PubMed

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Facile fabrication of a well-ordered porous Cu-doped SnO2 thin film for H2S sensing.

PubMed

Zhang, Shumin; Zhang, Pingping; Wang, Yun; Ma, Yanyun; Zhong, Jun; Sun, Xuhui

2014-09-10

Well-ordered Cu-doped and undoped SnO2 porous thin films with large specific surface areas have been fabricated on a desired substrate using a self-assembled soft template combined with simple physical cosputtering deposition. The Cu-doped SnO2 porous film gas sensor shows a significant enhancement in its sensing performance, including a high sensitivity, selectivity, and a fast response and recovery time. The sensitivity of the Cu-doped SnO2 porous sensor is 1 order of magnitude higher than that of the undoped SnO2 sensor, with average response and recovery times to 100 ppm of H2S of ∼ 10.1 and ∼ 42.4 s, respectively, at the optimal operating temperature of 180 °C. The well-defined porous sensors fabricated by the method also exhibit high reproducibility because of the accurately controlled fabrication process. The facile process can be easily extended to the fabrication of other semiconductor oxide gas sensors with easy doping and multilayer porous nanostructure for practical sensing applications.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Smoother Scribing of Silicon Wafers

NASA Technical Reports Server (NTRS)

Danyluk, S.

1986-01-01

Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

Commercial production of QWIP wafers by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Fastenau, J. M.; Liu, W. K.; Fang, X. M.; Lubyshev, D. I.; Pelzel, R. I.; Yurasits, T. R.; Stewart, T. R.; Lee, J. H.; Li, S. S.; Tidrow, M. Z.

2001-06-01

As the performance of quantum well infrared photodetectors (QWIPs) and QWIP-based imaging systems continues to improve, their demand will undoubtedly grow. This points to the importance of a reliable commercial supplier of semiconductor QWIP material on three inch and, in the near future, four-inch substrates. Molecular beam epitaxy (MBE) is the preferred technique for growing the demanding QWIP structure, as tight control is required over the material composition and layer thickness. We report the current status of MBE-grown GaAs-based QWIP structures in a commercial production environment at IQE. Uniformity data and run-to-run reproducibility on both three-inch and four-inch GaAs substrates are quantified using alloy composition and QW thickness. Initial results on growth technology transfer to a multi-wafer MBE reactor are also presented. High-resolution X-ray diffraction measurements demonstrate GaAs QW thickness variations and AlGaAs barrier compositions changes to be less than 4% and 1% Al, respectively, across four-inch QWIP wafers from both single- and multiple-wafer MBE platforms.

Strategy For Yield Control And Enhancement In VLSI Wafer Manufacturing

NASA Astrophysics Data System (ADS)

Neilson, B.; Rickey, D.; Bane, R. P.

1988-01-01

In most fully utilized integrated circuit (IC) production facilities, profit is very closely linked with yield. In even the most controlled manufacturing environments, defects due to foreign material are a still major contributor to yield loss. Ideally, an IC manufacturer will have ample engineering resources to address any problem that arises. In the real world, staffing limitations require that some tasks must be left undone and potential benefits left unrealized. Therefore, it is important to prioritize problems in a manner that will give the maximum benefit to the manufacturer. When offered a smorgasbord of problems to solve, most people (engineers included) will start with what is most interesting or the most comfortable to work on. By providing a system that accurately predicts the impact of a wide variety of defect types, a rational method of prioritizing engineering effort can be made. To that effect, a program was developed to determine and rank the major yield detractors in a mixed analog/digital FET manufacturing line. The two classical methods of determining yield detractors are chip failure analysis and defect monitoring on drop in test die. Both of these methods have short comings: 1) Chip failure analysis is painstaking and very time consuming. As a result, the sample size is very small. 2) Drop in test die are usually designed for device parametric analysis rather than defect analysis. To provide enough wafer real estate to do meaningful defect analysis would render the wafer worthless for production. To avoid these problems, a defect monitor was designed that provided enough area to detect defects at the same rate or better than the NMOS product die whose yield was to be optimized. The defect monitor was comprehensive and electrically testable using such equipment as the Prometrix LM25 and other digital testers. This enabled the quick accumulation of data which could be handled statistically and mapped individually. By scaling the defect densities

Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

NASA Astrophysics Data System (ADS)

Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

2018-02-01

We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

Fabrication of Superconducting Quantum Interference Device Magnetometers on a Glass Epoxy Polyimide Resin Substrate with Copper Terminals

NASA Astrophysics Data System (ADS)

Kawai, Jun; Kawabata, Miki; Oyama, Daisuke; Uehara, Gen

We have developed fabrication technique of superconducting quantum interference device (SQUID) magnetometers based on Nb/AlAlOx/Nb junctions directly on a glass epoxy polyimide resin substrate, which has copper terminals embedded in advance. The advantage of this method is that no additional substrate and wirebonds are needed for assembly. Compared to conventional SQUID magnetometers, which are assembled with a SQUID chip fabricated on a Si substrate and wirebonding technique, low risk of disconnection can be expected. A directly-coupled multi-loop SQUID magnetometer fabricated with this method has as good noise performance as a SQUID magnetometer with the same design fabricated on a Si wafer. The magnetometer sustained its performance through thermal cycle test 13 times so far.

Fabrication and electrical characterization of partially metallized vias fabricated by inkjet

NASA Astrophysics Data System (ADS)

Khorramdel, B.; Mäntysalo, M.

2016-04-01

Through silicon vias (TSVs), acting as vertical interconnections, play an important role in micro-electro-mechanical systems (MEMS) 3D wafer level packaging. Today, taking advantage of nanoparticle inks, inkjet technologies as local filling methods could be used to plate the inside the vias with a conductive material, rather than using a current method, such as chemical vapor deposition or electrolytic growth. This could decrease the processing time, cost and waste material produced. In this work, we have fabricated and demonstrated electrical characterization of TSVs with a top diameter of 85 μm, and partially metallized on their inside walls using silver nanoparticle ink and drop-on-demand inkjet printing. Electrical measurement showed that the resistance of a single via with a void free coverage from top to bottom could be less than 4 Ω, which is still acceptable for MEMS applications.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

PubMed

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-02-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

Fabrication of a microfluidic chip by UV bonding at room temperature for integration of temperature-sensitive layers

NASA Astrophysics Data System (ADS)

Schlautmann, S.; Besselink, G. A. J.; Radhakrishna Prabhu, G.; Schasfoort, R. B. M.

2003-07-01

A method for the bonding of a microfluidic device at room temperature is presented. The wafer with the fluidic structures was bonded to a sensor wafer with gold pads by means of adhesive bonding, utilizing an UV-curable glue layer. To avoid filling the fluidic channels with the glue, a stamping process was developed which allows the selective application of a thin glue layer. In this way a microfluidic glass chip was fabricated that could be used for performing surface plasmon resonance measurements without signs of leakage. The advantage of this method is the possibility of integration of organic layers as well as other temperature-sensitive layers into a microfluidic glass device.

Facile Fabrication of Electrically Conductive Low-Density Polyethylene/Carbon Fiber Tubes for Novel Smart Materials via Multiaxial Orientation.

PubMed

Li, Yijun; Nie, Min; Wang, Qi

2018-01-10

Electromechanical sensors are indispensable components in functional devices and robotics application. However, the fabrication of the sensors still maintains a challenging issue that high percolation threshold and easy failure of conductive network are derived from uniaxial orientation of conductive fillers in practical melt processing. Herein, we reported a facile fabrication method to prepare a multiaxial low-density polyethylene (LDPE)/carbon fibers (CFs) tube with bidirectional controllable electrical conductivity and sensitive strain-responsive performance via rotation extrusion technology. The multidimensional helical flow is confirmed in the reverse rotation extrusion, and the CFs readily respond to the flow field leading to a multiaxial orientation in the LDPE matrix. In contrast to uniaxial LDPE/CF composites, which perform a "head to head" conjunction, multiaxial-orientated CF networks exhibit a unique multilayer structure in which the CFs with distinct orientation direction intersect in the interface, endowing the LDPE/CF composites with a low percolation threshold (15 wt %) to those of the uniaxial ones (∼35 wt %). The angles between two axes play a vital role in determining the density of the conductive networks in the interface, which is predominant in tuning the bending-responsive behaviors with a gauge factor range from 12.5 to 56.3 and the corresponding linear respond region from ∼15 to ∼1%. Such a superior performance of conductive LDPE/CF tube confirms that the design of multiaxial orientation paves a novel way to facile fabrication of advanced cost-effective CF-based smart materials, shedding light on promising applications such as smart materials and intelligent engineering monitoring.

Three-dimensional micro/nano-scale structure fabricated by combination of non-volatile polymerizable RTIL and FIB irradiation

PubMed Central

Kuwabata, Susumu; Minamimoto, Hiro; Inoue, Kosuke; Imanishi, Akihito; Hosoya, Ken; Uyama, Hiroshi; Torimoto, Tsukasa; Tsuda, Tetsuya; Seki, Shu

2014-01-01

Room-temperature ionic liquid (RTIL) has been widely investigated as a nonvolatile solvent as well as a unique liquid material because of its interesting features, e.g., negligible vapor pressure and high thermal stability. Here we report that a non-volatile polymerizable RTIL is a useful starting material for the fabrication of micro/nano-scale polymer structures with a focused-ion-beam (FIB) system operated under high-vacuum condition. Gallium-ion beam irradiation to the polymerizable 1-allyl-3-ethylimidazolium bis((trifluoromethane)sulfonyl)amide RTIL layer spread on a Si wafer induced a polymerization reaction without difficulty. What is interesting to note is that we have succeeded in provoking the polymerization reaction anywhere on the Si wafer substrate by using FIB irradiation with a raster scanning mode. By this finding, two- and three-dimensional micro/nano-scale polymer structure fabrications were possible at the resolution of 500,000 dpi. Even intricate three-dimensional micro/nano-figures with overhang and hollow moieties could be constructed at the resolution of approximately 100 nm. PMID:24430465

High-rotational symmetry lattices fabricated by moiré nanolithography.

PubMed

Lubin, Steven M; Zhou, Wei; Hryn, Alexander J; Huntington, Mark D; Odom, Teri W

2012-09-12

This paper describes a new nanofabrication method, moiré nanolithography, that can fabricate subwavelength lattices with high-rotational symmetries. By exposing elastomeric photomasks sequentially at multiple offset angles, we created arrays with rotational symmetries as high as 36-fold, which is three times higher than quasiperiodic lattices (≤12-fold) and six times higher than two-dimensional periodic lattices (≤6-fold). Because these moiré nanopatterns can be generated over wafer-scale areas, they are promising for a range of photonic applications, especially those that require broadband, omnidirectional absorption of visible light.

Facile approach to the fabrication of a micropattern possessing nanoscale substructure.

PubMed

Ji, Qiang; Jiang, Xuesong; Yin, Jie

2007-12-04

On the basis of the combined technologies of photolithography and reaction-induced phase separation (RIPS), a facile approach has been successfully developed for the fabrication of a micropattern possessing nanoscale substructure on the thin film surface. This approach involves three steps. In the first step, a thin film was prepared by spin coating from a solution of a commercial random copolymer, polystyrene-r-poly(methyl methacrylate) (PS-r-PMMA) and a commercial crosslinker, trimethylolpropane triacrylate (TMPTA). In the second step, photolithograph was performed with the thin film using a 250 W high-pressure mercury lamp to produce the micropattern. Finally, the resulting micropattern was annealed at 200 degrees C for a certain time, and reaction-induced phase separation occurred. After soaking in chloroform for 4 h, nanoscale substructure was obtained. The whole processes were traced by atomic force microscopy (AFM), X-ray photoelectron spectrometry (XPS), and Fourier transform infrared (FTIR) spectroscopy, and the results supported the proposed structure.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Advances in process overlay on 300-mm wafers

NASA Astrophysics Data System (ADS)

Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

2002-07-01

Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC

Wafer-size free-standing single-crystalline graphene device arrays

NASA Astrophysics Data System (ADS)

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Fabrication of a Ni nano-imprint stamp for an anti-reflective layer using an anodic aluminum oxide template.

PubMed

Park, Eun-Mi; Lim, Seung-Kyu; Ra, Senug-Hyun; Suh, Su-Jung

2013-11-01

Aluminum anodizing can alter pore diameter, density distribution, periodicity and layer thickness in a controlled way. Because of this property, porous type anodic aluminum oxide (AAO) was used as a template for nano-structure fabrication. The alumina layer generated at a constant voltage increased the pore size from 120 nm to 205 nm according to an increasing process time from 60 min to 150 min. The resulting fabricated AAO templates had pore diameters at or less than 200 nm. Ni was sputtered as a conductive layer onto this AAO template and electroplated using DC and pulse power. Comparing these Ni stamps, those generated from electroplating using on/reverse/off pulsing had an ordered pillar array and maintained the AAO template morphology. This stamp was used for nano-imprinting on UV curable resin coated glass wafer. Surface observations via electron microscopy showed that the nano-imprinted patterned had the same shape as the AAO template. A soft mold was subsequently fabricated and nano-imprinted to form a moth-eye structure on the glass wafer. An analysis of the substrate transmittance using UV-VIS/NIR spectroscopy showed that the transmittance of the substrate with the moth-eye structure was 5% greater that the non-patterned substrate.

Laser treatment of plasma-hydrogenated silicon wafers for thin layer exfoliation

NASA Astrophysics Data System (ADS)

Ghica, Corneliu; Nistor, Leona Cristina; Teodorescu, Valentin Serban; Maraloiu, Adrian; Vizireanu, Sorin; Scarisoreanu, Nae Doinel; Dinescu, Maria

2011-03-01

We have studied by transmission electron microscopy the microstructural effects induced by pulsed laser annealing in comparison with thermal treatments of RF plasma hydrogenated Si wafers aiming for further application in the smart-cut procedure. While thermal annealing mainly produces a slight decrease of the density of plasma-induced planar defects and an increase of the size and number of plasma-induced nanocavities in the Si matrix, pulsed laser annealing of RF plasma hydrogenated Si wafers with a 355 nm wavelength radiation results in both the healing of defects adjacent to the wafer surface and the formation of a well defined layer of nanometric cavities at a depth of 25-50 nm. In this way, a controlled fracture of single crystal layers of Si thinner than 50 nm is favored.

Fabrication of microelectromechanical systems (MEMS) cantilevers for photoacoustic (PA) detection of terahertz (THz) radiation

NASA Astrophysics Data System (ADS)

Newberry, R.; Glauvitz, N.; Coutu, R. A.; Medvedev, I. R.; Petkie, D.

2014-03-01

Historically, spectroscopy has been a cumbersome endeavor due to the relatively large sizes (3ft - 100ft in length) of modern spectroscopy systems. Taking advantage of the photoacoustic effect would allow for much smaller absorption chambers since the photoacoustic (PA) effect is independent of the absorption path length. In order to detect the photoacoustic waves being generated, a photoacoustic microphone would be required. This paper reports on the fabrication efforts taken in order to create microelectromechanical systems (MEMS) cantilevers for the purpose of sensing photoacoustic waves generated via terahertz (THz) radiation passing through a gaseous sample. The cantilevers are first modeled through the use of the finite element modeling software, CoventorWare®. The cantilevers fabricated with bulk micromachining processes and are 7x2x0.010mm on a silicon-on-insulator (SOI) wafer which acts as the physical structure of the cantilever. The devices are released by etching through the wafer's backside and etching through the buried oxide with hydrofluoric acid. The cantilevers are placed in a test chamber and their vibration and deflection are measured via a Michelson type interferometer that reflects a laser off a gold tip evaporated onto the tip of the cantilever. The test chamber is machined from stainless steel and housed in a THz testing environment at Wright State University. Fabricated devices have decreased residual stress and larger radii of curvatures by approximately 10X.

CMOS-Compatible Fabrication for Photonic Crystal-Based Nanofluidic Structure.

PubMed

Peng, Wang; Chen, Youping; Ai, Wu; Zhang, Dailin; Song, Han; Xiong, Hui; Huang, Pengcheng

2017-12-01

Photonic crystal (PC)-based devices have been widely used since 1990s, while PC has just stepped into the research area of nanofluidic. In this paper, photonic crystal had been used as a complementary metal oxide semiconductors (CMOS) compatible part to create a nanofluidic structure. A nanofluidic structure prototype had been fabricated with CMOS-compatible techniques. The nanofluidic channels were sealed by direct bonding polydimethylsiloxane (PDMS) and the periodic gratings on photonic crystal structure. The PC was fabricated on a 4-in. Si wafer with Si 3 N 4 as the guided mode layer and SiO 2 film as substrate layer. The higher order mode resonance wavelength of PC-based nanofluidic structure had been selected, which can confine the enhanced electrical field located inside the nanochannel area. A design flow chart was used to guide the fabrication process. By optimizing the fabrication device parameters, the periodic grating of PC-based nanofluidic structure had a high-fidelity profile with fill factor at 0.5. The enhanced electric field was optimized and located within the channel area, and it can be used for PC-based nanofluidic applications with high performance.

Resonance ultrasonic diagnostics of defects in full-size silicon wafers

NASA Astrophysics Data System (ADS)

Belyaev, A.; Ostapenko, S.

2001-12-01

A resonance acoustic effect was observed recently in full-size 200 mm Cz-Si wafers and applied to characterize as-grown and process-induced defects. Ultrasonic vibrations can be excited into wafers using an external ultrasonic transducer and their amplitude is recorded using a scanning air-coupled acoustic probe operated in a non-contact mode. By sweeping driving frequency, f, of the transducer, we observed an amplification of a specific acoustic mode referred to as ‘whistle’. In this paper, we performed theoretical modeling of the whistle which allowed in attributing this mode to resonant flexural vibrations in a thin circular plate. We calculated normal frequencies of the flexural vibrations of a circular plate of radius ρ in the case of the free edge. The model gives an excellent fit to experimental data with regard to whistle spatial distribution. The results of calculation allow the evaluation of resonance acoustic effect in wafers of different geometries employed in the industry.

Fabrication of Thin Film Heat Flux Sensors

NASA Technical Reports Server (NTRS)

Will, Herbert A.

1992-01-01

Prototype thin film heat flux sensors have been constructed and tested. The sensors can be applied to propulsion system materials and components. The sensors can provide steady state and fast transient heat flux information. Fabrication of the sensor does not require any matching of the mounting surface. Heat flux is proportional to the temperature difference across the upper and lower surfaces of an insulation material. The sensor consists of an array of thermocouples on the upper and lower surfaces of a thin insulating layer. The thermocouples for the sensor are connected in a thermopile arrangement. A 100 thermocouple pair heat flux sensor has been fabricated on silicon wafers. The sensor produced an output voltage of 200-400 microvolts when exposed to a hot air heat gun. A 20 element thermocouple pair heat flux sensor has been fabricated on aluminum oxide sheet. Thermocouples are Pt-Pt/Rh with silicon dioxide as the insulating material. This sensor produced an output of 28 microvolts when exposed to the radiation of a furnace operating at 1000 C. Work is also underway to put this type of heat flux sensor on metal surfaces.

Fabrication of Large-area Free-standing Ultrathin Polymer Films

PubMed Central

Stadermann, Michael; Baxamusa, Salmaan H.; Aracne-Ruddle, Chantel; Chea, Maverick; Li, Shuaili; Youngblood, Kelly; Suratwala, Tayyab

2015-01-01

This procedure describes a method for the fabrication of large-area and ultrathin free-standing polymer films. Typically, ultrathin films are prepared using either sacrificial layers, which may damage the film or affect its mechanical properties, or they are made on freshly cleaved mica, a substrate that is difficult to scale. Further, the size of ultrathin film is typically limited to a few square millimeters. In this method, we modify a surface with a polyelectrolyte that alters the strength of adhesion between polymer and deposition substrate. The polyelectrolyte can be shown to remain on the wafer using spectroscopy, and a treated wafer can be used to produce multiple films, indicating that at best minimal amounts of the polyelectrolyte are added to the film. The process has thus far been shown to be limited in scalability only by the size of the coating equipment, and is expected to be readily scalable to industrial processes. In this study, the protocol for making the solutions, preparing the deposition surface, and producing the films is described. PMID:26066738

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

30 CFR 285.702 - What must I include in my Fabrication and Installation Report?

Code of Federal Regulations, 2010 CFR

2010-07-01

... INTERIOR OFFSHORE RENEWABLE ENERGY ALTERNATE USES OF EXISTING FACILITIES ON THE OUTER CONTINENTAL SHELF Facility Design, Fabrication, and Installation Reports § 285.702 What must I include in my Fabrication and... fabricated and installed in accordance with the design criteria identified in the Facility Design Report...

Method of fabricating porous silicon carbide (SiC)

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Green and facile fabrication of carbon aerogels from cellulose-based waste newspaper for solving organic pollution.

PubMed

Han, Shenjie; Sun, Qingfeng; Zheng, Huanhuan; Li, Jingpeng; Jin, Chunde

2016-01-20

Carbon-based aerogel fabricated from waste biomass is a potential absorbent material for solving organic pollution. Herein, the lightweight, hydrophobic and porous carbon aerogels (CAs) have been synthesized through freezing-drying and post-pyrolysis by using waste newspaper as the only raw materials. The as-prepared CAs exhibited a low density of 18.5 mg cm(-3) and excellent hydrophobicity with a water contact angle of 132° and selective absorption for organic reagents. The absorption capacity of CA for organic compounds can be 29-51 times its own weight. Moreover, three methods (e.g., squeezing, combustion, and distillation) can be employed to recycle CA and harvest organic pollutants. Combined with waste biomass as raw materials, green and facile fabrication process, excellent hydrophobicity and oleophilicity, CA used as an absorbent material has great potential in application of organic pollutant solvents absorption and environmental protection. Copyright © 2015 Elsevier Ltd. All rights reserved.

Optical cavity furnace for semiconductor wafer processing

DOEpatents

Sopori, Bhushan L.

2014-08-05

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Chemical sensors fabricated by a photonic integrated circuit foundry

NASA Astrophysics Data System (ADS)

Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

2018-02-01

We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

"Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

NASA Astrophysics Data System (ADS)

van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

1987-01-01

An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Wafer-level manufacturing technology of glass microlenses

NASA Astrophysics Data System (ADS)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

NASA Astrophysics Data System (ADS)

Bakhshizadeh, N.; Sivoththaman, S.

2017-12-01

Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

Chemical method for producing smooth surfaces on silicon wafers

DOEpatents

Yu, Conrad

2003-01-01

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

Wafer-scalable high-performance CVD graphene devices and analog circuits

NASA Astrophysics Data System (ADS)

Tao, Li; Lee, Jongho; Li, Huifeng; Piner, Richard; Ruoff, Rodney; Akinwande, Deji

2013-03-01

Graphene field effect transistors (GFETs) will serve as an essential component for functional modules like amplifier and frequency doublers in analog circuits. The performance of these modules is directly related to the mobility of charge carriers in GFETs, which per this study has been greatly improved. Low-field electrostatic measurements show field mobility values up to 12k cm2/Vs at ambient conditions with our newly developed scalable CVD graphene. For both hole and electron transport, fabricated GFETs offer substantial amplification for small and large signals at quasi-static frequencies limited only by external capacitances at high-frequencies. GFETs biased at the peak transconductance point featured high small-signal gain with eventual output power compression similar to conventional transistor amplifiers. GFETs operating around the Dirac voltage afforded positive conversion gain for the first time, to our knowledge, in experimental graphene frequency doublers. This work suggests a realistic prospect for high performance linear and non-linear analog circuits based on the unique electron-hole symmetry and fast transport now accessible in wafer-scalable CVD graphene. *Support from NSF CAREER award (ECCS-1150034) and the W. M. Keck Foundation are appreicated.

Laser ablative decoration of micro-diamonds by gold nanoparticles for fabrication of hybrid plasmonic-dielectric antennae

NASA Astrophysics Data System (ADS)

Ivanova, A. K.; Ionin, A. A.; Khmelnitskii, R. A.; Kudryashov, S. I.; Levchenko, A. O.; Mel'nik, N. N.; Rudenko, A. A.; Saraeva, I. N.; Umanskaya, S. P.; Zayarny, D. A.; Nguyen, L. V.; Nguyen, T. T. H.; Pham, M. H.; Pham, D. V.; Do, T. H.

2017-06-01

Hybrid plasmonic-dielectric antennae are fabricated by laser ablation of gold in water sols of micro-diamonds. Electron microscopy and energy-dispersive x-ray spectroscopy of their deposits on a silicon wafer surface indicate close proximity of gold nanoparticles and micro-diamonds, which is supported by photoluminescence studies demonstrating strong (eight-fold) damping of micro-diamond luminescence owing to the attachment of the gold nanoparticles. UV-near-IR spectroscopy of their sols reveals a considerable plasmonic effect, related to red spectral shifts of surface plasmon resonance for the gold nanoparticles in the laser-ablation-fabricated antennae.

Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

PubMed

Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

2011-01-01

Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

A top-down approach to fabrication of high quality vertical heterostructure nanowire arrays.

PubMed

Wang, Hua; Sun, Minghua; Ding, Kang; Hill, Martin T; Ning, Cun-Zheng

2011-04-13

We demonstrate a novel top-down approach for fabricating nanowires with unprecedented complexity and optical quality by taking advantage of a nanoscale self-masking effect. We realized vertical arrays of nanowires of 20-40 nm in diameter with 16 segments of complex longitudinal InGaAsP/InP structures. The unprecedented high quality of etched wires is evidenced by the narrowest photoluminescence linewidth ever produced in similar wavelengths, indistinguishable from that of the corresponding wafer. This top-down, mask-free, large scale approach is compatible with the established device fabrication processes and could serve as an important alternative to the bottom-up approach, significantly expanding ranges and varieties of applications of nanowire technology.

Study on fabrication of the superhydrophobic sol-gel films based on copper wafer and its anti-corrosive properties

NASA Astrophysics Data System (ADS)

Fan, Youhua; Li, Changzhu; Chen, Zejun; Chen, Hong

2012-06-01

In the present study, superhydrophobic copper wafer was prepared by a sol-gel deposition method. Different molar ratios of vinyltrimethoxysilane (VTES), ethanol (EtOH), water (H2O) and ammonia water (NH3·OH) were involved in this research. The morphologies, chemical compositions and hydrophobicity of the films were analyzed by scanning electron microscopy (SEM), energy dispersive X-ray detector (EDX), Fourier transfer infrared spectrometer (FTIR) and water contact angle measurement (CA). It was shown by the surface morphological study that different structures, such as pyramid-shaped protrusions, nipple-shaped protrusions or ball-shaped silica particles, were distributed on the copper substrate. The films had a high water contact angle larger than 155.4°. The durability properties revealed that the films had a good superhydrophobicity deposited in 3.5 wt.% sodium chloride solution for up to 14 days.

Wafer-level Cu-Sn micro-joints with high mechanical strength and low Sn overflow

NASA Astrophysics Data System (ADS)

Duan, Ani; Luu, Thi-Thuy; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2015-09-01

In this paper, we report wafer-level bonding using solid-liquid inter-diffusion (SLID) processes for fabricating micro-joints Cu-Sn at low temperature (270 °C). The evolution of multilayer Cu/Sn to micro-joint alloys has been characterized by optical microscopy and mechanical die-shear testing. The Cu-Sn joints with line width from 80 to 200 μm prove to be reliable packaging materials for bonding vacuum micro-cavities with controllable Sn overflow, as well as high mechanical strength (>70 MPa). A thermodynamic model has been performed to further understand the formation of Cu-Sn intermetallic alloys. There are two important findings for this work: 1) Using a two-step temperature profile may significantly reduce the amount of Sn overflow; 2) for packaging, a bond frame width greater than 80 μm will result in high yield.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

PubMed Central

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-01-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Layer-by-layer assembly of two-dimensional materials into wafer-scale heterostructures

NASA Astrophysics Data System (ADS)

Kang, Kibum; Lee, Kan-Heng; Han, Yimo; Gao, Hui; Xie, Saien; Muller, David A.; Park, Jiwoong

2017-10-01

High-performance semiconductor films with vertical compositions that are designed to atomic-scale precision provide the foundation for modern integrated circuitry and novel materials discovery. One approach to realizing such films is sequential layer-by-layer assembly, whereby atomically thin two-dimensional building blocks are vertically stacked, and held together by van der Waals interactions. With this approach, graphene and transition-metal dichalcogenides--which represent one- and three-atom-thick two-dimensional building blocks, respectively--have been used to realize previously inaccessible heterostructures with interesting physical properties. However, no large-scale assembly method exists at present that maintains the intrinsic properties of these two-dimensional building blocks while producing pristine interlayer interfaces, thus limiting the layer-by-layer assembly method to small-scale proof-of-concept demonstrations. Here we report the generation of wafer-scale semiconductor films with a very high level of spatial uniformity and pristine interfaces. The vertical composition and properties of these films are designed at the atomic scale using layer-by-layer assembly of two-dimensional building blocks under vacuum. We fabricate several large-scale, high-quality heterostructure films and devices, including superlattice films with vertical compositions designed layer-by-layer, batch-fabricated tunnel device arrays with resistances that can be tuned over four orders of magnitude, band-engineered heterostructure tunnel diodes, and millimetre-scale ultrathin membranes and windows. The stacked films are detachable, suspendable and compatible with water or plastic surfaces, which will enable their integration with advanced optical and mechanical systems.

Layer-by-layer assembly of two-dimensional materials into wafer-scale heterostructures.

PubMed

Kang, Kibum; Lee, Kan-Heng; Han, Yimo; Gao, Hui; Xie, Saien; Muller, David A; Park, Jiwoong

2017-10-12

High-performance semiconductor films with vertical compositions that are designed to atomic-scale precision provide the foundation for modern integrated circuitry and novel materials discovery. One approach to realizing such films is sequential layer-by-layer assembly, whereby atomically thin two-dimensional building blocks are vertically stacked, and held together by van der Waals interactions. With this approach, graphene and transition-metal dichalcogenides-which represent one- and three-atom-thick two-dimensional building blocks, respectively-have been used to realize previously inaccessible heterostructures with interesting physical properties. However, no large-scale assembly method exists at present that maintains the intrinsic properties of these two-dimensional building blocks while producing pristine interlayer interfaces, thus limiting the layer-by-layer assembly method to small-scale proof-of-concept demonstrations. Here we report the generation of wafer-scale semiconductor films with a very high level of spatial uniformity and pristine interfaces. The vertical composition and properties of these films are designed at the atomic scale using layer-by-layer assembly of two-dimensional building blocks under vacuum. We fabricate several large-scale, high-quality heterostructure films and devices, including superlattice films with vertical compositions designed layer-by-layer, batch-fabricated tunnel device arrays with resistances that can be tuned over four orders of magnitude, band-engineered heterostructure tunnel diodes, and millimetre-scale ultrathin membranes and windows. The stacked films are detachable, suspendable and compatible with water or plastic surfaces, which will enable their integration with advanced optical and mechanical systems.

Functionalization of MEMS cantilever beams for interconnect reliability investigation: development practice

NASA Astrophysics Data System (ADS)

Bieniek, T.; Janczyk, G.; Dobrowolski, R.; Wojciechowska, K.; Malinowska, A.; Panas, A.; Nieprzecki, M.; Kłos, H.

2016-11-01

This paper covers research results on development of the cantilevers beams test structures for interconnects reliability and robustness investigation. Presented results include design, modelling, simulation, optimization and finally fabrication stage performed on 4 inch Si wafers using the ITE microfabrication facility. This paper also covers experimental results from the test structures characterization.

Facile Fabrication of Composite Membranes with Dual Thermo- and pH-Responsive Characteristics.

PubMed

Ma, Bing; Ju, Xiao-Jie; Luo, Feng; Liu, Yu-Qiong; Wang, Yuan; Liu, Zhuang; Wang, Wei; Xie, Rui; Chu, Liang-Yin

2017-04-26

Facile fabrication of novel functional membranes with excellent dual thermo- and pH-responsive characteristics has been achieved by simply designing dual-layer composite membranes. pH-Responsive poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) block copolymers and polystyrene blended with thermoresponsive poly(N-isopropylacrylamide) (PNIPAM) nanogels are respectively used to construct the top layer and bottom layer of composite membranes. The stretching/coiling conformation changes of the P4VP chains around the pK a (∼3.5-4.5) provide the composite membranes with extraordinary pH-responsive characteristics, and the volume phase transitions of PNIPAM nanogels at the pore/matrix interfaces in the bottom layer around the volume phase transition temperature (VPTT, ∼33 °C) provide the composite membranes with great thermoresponsive characteristics. The microstructures, permeability performances, and dual stimuli-responsive characteristics can be well tuned by adjusting the content of PNIPAM nanogels and the thickness of the PS-b-P4VP top layer. The water fluxes of the composite membranes can be changed in order of magnitude by changing the environment temperature and pH, and the dual thermo- and pH-responsive permeation performances of the composite membranes are satisfactorily reversible and reproducible. The membrane fabrication strategy in this work provides valuable guidance for further development of dual stimuli-responsive membranes or even multi stimuli-responsive membranes.

Beneficial defects: exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowires

PubMed Central

2014-01-01

We outline a metal-free fabrication route of in-plane Ge nanowires on Ge(001) substrates. By positively exploiting the polishing-induced defects of standard-quality commercial Ge(001) wafers, micrometer-length wires are grown by physical vapor deposition in ultra-high-vacuum environment. The shape of the wires can be tailored by the epitaxial strain induced by subsequent Si deposition, determining a progressive transformation of the wires in SiGe faceted quantum dots. This shape transition is described by finite element simulations of continuous elasticity and gives hints on the equilibrium shape of nanocrystals in the presence of tensile epitaxial strain. PACS 81.07.Gf; 68.35.bg; 68.35.bj; 62.23.Eg PMID:25114649

Beneficial defects: exploiting the intrinsic polishing-induced wafer roughness for the catalyst-free growth of Ge in-plane nanowires.

PubMed

Persichetti, Luca; Sgarlata, Anna; Mori, Stefano; Notarianni, Marco; Cherubini, Valeria; Fanfoni, Massimo; Motta, Nunzio; Balzarotti, Adalberto

2014-01-01

We outline a metal-free fabrication route of in-plane Ge nanowires on Ge(001) substrates. By positively exploiting the polishing-induced defects of standard-quality commercial Ge(001) wafers, micrometer-length wires are grown by physical vapor deposition in ultra-high-vacuum environment. The shape of the wires can be tailored by the epitaxial strain induced by subsequent Si deposition, determining a progressive transformation of the wires in SiGe faceted quantum dots. This shape transition is described by finite element simulations of continuous elasticity and gives hints on the equilibrium shape of nanocrystals in the presence of tensile epitaxial strain. 81.07.Gf; 68.35.bg; 68.35.bj; 62.23.Eg.

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Fabrication and characterization of the Si-photonics-integrated vertical resonant-cavity light-emitting diode

NASA Astrophysics Data System (ADS)

Kong, Duanhua; Kim, Taek; Kim, Sihan; Hong, Hyungi; Shcherbatko, Igor; Park, Youngsoo; Shin, Dongjae; Ha, Kyoung-Ho; Jeong, Gitae

2014-03-01

We designed and fabricated a 1.3-um hybrid vertical Resonant-Cavity Light-Emitting Diode for optical interconnect by using direct III-V wafer bonding on silicon on insulator (SOI). The device included InP based front distributed Bragg reflector (DBR), InGaAlAs based active layer, and SOI-based high-contrast-grating (HCG) as a back reflector. 42-uW continuous wave optical power was achieved at 20mA at room temperature.